1 /* 2 * sPAPR CPU core device, acts as container of CPU thread devices. 3 * 4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 #include "hw/cpu/core.h" 10 #include "hw/ppc/spapr_cpu_core.h" 11 #include "target-ppc/cpu.h" 12 #include "hw/ppc/spapr.h" 13 #include "hw/boards.h" 14 #include "qapi/error.h" 15 #include <sysemu/cpus.h> 16 #include "target-ppc/kvm_ppc.h" 17 #include "hw/ppc/ppc.h" 18 #include "target-ppc/mmu-hash64.h" 19 #include <sysemu/numa.h> 20 21 static void spapr_cpu_reset(void *opaque) 22 { 23 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 24 PowerPCCPU *cpu = opaque; 25 CPUState *cs = CPU(cpu); 26 CPUPPCState *env = &cpu->env; 27 28 cpu_reset(cs); 29 30 /* All CPUs start halted. CPU0 is unhalted from the machine level 31 * reset code and the rest are explicitly started up by the guest 32 * using an RTAS call */ 33 cs->halted = 1; 34 35 env->spr[SPR_HIOR] = 0; 36 37 ppc_hash64_set_external_hpt(cpu, spapr->htab, spapr->htab_shift, 38 &error_fatal); 39 } 40 41 static void spapr_cpu_destroy(PowerPCCPU *cpu) 42 { 43 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 44 45 xics_cpu_destroy(spapr->icp, cpu); 46 qemu_unregister_reset(spapr_cpu_reset, cpu); 47 } 48 49 void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, Error **errp) 50 { 51 CPUPPCState *env = &cpu->env; 52 CPUState *cs = CPU(cpu); 53 int i; 54 55 /* Set time-base frequency to 512 MHz */ 56 cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); 57 58 /* Enable PAPR mode in TCG or KVM */ 59 cpu_ppc_set_papr(cpu); 60 61 if (cpu->max_compat) { 62 Error *local_err = NULL; 63 64 ppc_set_compat(cpu, cpu->max_compat, &local_err); 65 if (local_err) { 66 error_propagate(errp, local_err); 67 return; 68 } 69 } 70 71 /* Set NUMA node for the added CPUs */ 72 for (i = 0; i < nb_numa_nodes; i++) { 73 if (test_bit(cs->cpu_index, numa_info[i].node_cpu)) { 74 cs->numa_node = i; 75 break; 76 } 77 } 78 79 xics_cpu_setup(spapr->icp, cpu); 80 81 qemu_register_reset(spapr_cpu_reset, cpu); 82 spapr_cpu_reset(cpu); 83 } 84 85 /* 86 * Return the sPAPR CPU core type for @model which essentially is the CPU 87 * model specified with -cpu cmdline option. 88 */ 89 char *spapr_get_cpu_core_type(const char *model) 90 { 91 char *core_type; 92 gchar **model_pieces = g_strsplit(model, ",", 2); 93 94 core_type = g_strdup_printf("%s-%s", model_pieces[0], TYPE_SPAPR_CPU_CORE); 95 g_strfreev(model_pieces); 96 return core_type; 97 } 98 99 static void spapr_core_release(DeviceState *dev, void *opaque) 100 { 101 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 102 const char *typename = object_class_get_name(sc->cpu_class); 103 size_t size = object_type_get_instance_size(typename); 104 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 105 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 106 CPUCore *cc = CPU_CORE(dev); 107 int smt = kvmppc_smt_threads(); 108 int i; 109 110 for (i = 0; i < cc->nr_threads; i++) { 111 void *obj = sc->threads + i * size; 112 DeviceState *dev = DEVICE(obj); 113 CPUState *cs = CPU(dev); 114 PowerPCCPU *cpu = POWERPC_CPU(cs); 115 116 spapr_cpu_destroy(cpu); 117 cpu_remove_sync(cs); 118 object_unparent(obj); 119 } 120 121 spapr->cores[cc->core_id / smt] = NULL; 122 123 g_free(core->threads); 124 object_unparent(OBJECT(dev)); 125 } 126 127 void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 128 Error **errp) 129 { 130 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 131 PowerPCCPU *cpu = POWERPC_CPU(core->threads); 132 int id = ppc_get_vcpu_dt_id(cpu); 133 sPAPRDRConnector *drc = 134 spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, id); 135 sPAPRDRConnectorClass *drck; 136 Error *local_err = NULL; 137 138 g_assert(drc); 139 140 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 141 drck->detach(drc, dev, spapr_core_release, NULL, &local_err); 142 if (local_err) { 143 error_propagate(errp, local_err); 144 return; 145 } 146 147 spapr_hotplug_req_remove_by_index(drc); 148 } 149 150 void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 151 Error **errp) 152 { 153 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(OBJECT(hotplug_dev)); 154 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 155 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 156 CPUCore *cc = CPU_CORE(dev); 157 CPUState *cs = CPU(core->threads); 158 sPAPRDRConnector *drc; 159 sPAPRDRConnectorClass *drck; 160 Error *local_err = NULL; 161 void *fdt = NULL; 162 int fdt_offset = 0; 163 int index; 164 int smt = kvmppc_smt_threads(); 165 166 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, cc->core_id); 167 index = cc->core_id / smt; 168 spapr->cores[index] = OBJECT(dev); 169 170 if (!smc->dr_cpu_enabled) { 171 /* 172 * This is a cold plugged CPU core but the machine doesn't support 173 * DR. So skip the hotplug path ensuring that the core is brought 174 * up online with out an associated DR connector. 175 */ 176 return; 177 } 178 179 g_assert(drc); 180 181 /* 182 * Setup CPU DT entries only for hotplugged CPUs. For boot time or 183 * coldplugged CPUs DT entries are setup in spapr_finalize_fdt(). 184 */ 185 if (dev->hotplugged) { 186 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 187 } 188 189 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 190 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err); 191 if (local_err) { 192 g_free(fdt); 193 spapr->cores[index] = NULL; 194 error_propagate(errp, local_err); 195 return; 196 } 197 198 if (dev->hotplugged) { 199 /* 200 * Send hotplug notification interrupt to the guest only in case 201 * of hotplugged CPUs. 202 */ 203 spapr_hotplug_req_add_by_index(drc); 204 } else { 205 /* 206 * Set the right DRC states for cold plugged CPU. 207 */ 208 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); 209 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); 210 } 211 } 212 213 void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 214 Error **errp) 215 { 216 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 217 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(OBJECT(hotplug_dev)); 218 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 219 int spapr_max_cores = max_cpus / smp_threads; 220 int index; 221 int smt = kvmppc_smt_threads(); 222 Error *local_err = NULL; 223 CPUCore *cc = CPU_CORE(dev); 224 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model); 225 const char *type = object_get_typename(OBJECT(dev)); 226 227 if (strcmp(base_core_type, type)) { 228 error_setg(&local_err, "CPU core type should be %s", base_core_type); 229 goto out; 230 } 231 232 if (!smc->dr_cpu_enabled && dev->hotplugged) { 233 error_setg(&local_err, "CPU hotplug not supported for this machine"); 234 goto out; 235 } 236 237 if (cc->nr_threads != smp_threads) { 238 error_setg(&local_err, "threads must be %d", smp_threads); 239 goto out; 240 } 241 242 if (cc->core_id % smt) { 243 error_setg(&local_err, "invalid core id %d\n", cc->core_id); 244 goto out; 245 } 246 247 index = cc->core_id / smt; 248 if (index < 0 || index >= spapr_max_cores) { 249 error_setg(&local_err, "core id %d out of range", cc->core_id); 250 goto out; 251 } 252 253 if (spapr->cores[index]) { 254 error_setg(&local_err, "core %d already populated", cc->core_id); 255 goto out; 256 } 257 258 out: 259 g_free(base_core_type); 260 error_propagate(errp, local_err); 261 } 262 263 static int spapr_cpu_core_realize_child(Object *child, void *opaque) 264 { 265 Error **errp = opaque; 266 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 267 CPUState *cs = CPU(child); 268 PowerPCCPU *cpu = POWERPC_CPU(cs); 269 270 object_property_set_bool(child, true, "realized", errp); 271 if (*errp) { 272 return 1; 273 } 274 275 spapr_cpu_init(spapr, cpu, errp); 276 if (*errp) { 277 return 1; 278 } 279 return 0; 280 } 281 282 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp) 283 { 284 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 285 CPUCore *cc = CPU_CORE(OBJECT(dev)); 286 const char *typename = object_class_get_name(sc->cpu_class); 287 size_t size = object_type_get_instance_size(typename); 288 Error *local_err = NULL; 289 Object *obj; 290 int i; 291 292 sc->threads = g_malloc0(size * cc->nr_threads); 293 for (i = 0; i < cc->nr_threads; i++) { 294 char id[32]; 295 void *obj = sc->threads + i * size; 296 297 object_initialize(obj, size, typename); 298 snprintf(id, sizeof(id), "thread[%d]", i); 299 object_property_add_child(OBJECT(sc), id, obj, &local_err); 300 if (local_err) { 301 goto err; 302 } 303 } 304 object_child_foreach(OBJECT(dev), spapr_cpu_core_realize_child, &local_err); 305 if (local_err) { 306 goto err; 307 } else { 308 return; 309 } 310 311 err: 312 while (i >= 0) { 313 obj = sc->threads + i * size; 314 object_unparent(obj); 315 i--; 316 } 317 g_free(sc->threads); 318 error_propagate(errp, local_err); 319 } 320 321 static void spapr_cpu_core_class_init(ObjectClass *oc, void *data) 322 { 323 DeviceClass *dc = DEVICE_CLASS(oc); 324 dc->realize = spapr_cpu_core_realize; 325 } 326 327 /* 328 * instance_init routines from different flavours of sPAPR CPU cores. 329 * TODO: Add support for 'host' core type. 330 */ 331 #define SPAPR_CPU_CORE_INITFN(_type, _fname) \ 332 static void glue(glue(spapr_cpu_core_, _fname), _initfn(Object *obj)) \ 333 { \ 334 sPAPRCPUCore *core = SPAPR_CPU_CORE(obj); \ 335 char *name = g_strdup_printf("%s-" TYPE_POWERPC_CPU, stringify(_type)); \ 336 ObjectClass *oc = object_class_by_name(name); \ 337 g_assert(oc); \ 338 g_free((void *)name); \ 339 core->cpu_class = oc; \ 340 } 341 342 SPAPR_CPU_CORE_INITFN(POWER7_v2.3, POWER7); 343 SPAPR_CPU_CORE_INITFN(POWER7+_v2.1, POWER7plus); 344 SPAPR_CPU_CORE_INITFN(POWER8_v2.0, POWER8); 345 SPAPR_CPU_CORE_INITFN(POWER8E_v2.1, POWER8E); 346 347 typedef struct SPAPRCoreInfo { 348 const char *name; 349 void (*initfn)(Object *obj); 350 } SPAPRCoreInfo; 351 352 static const SPAPRCoreInfo spapr_cores[] = { 353 /* POWER7 and aliases */ 354 { .name = "POWER7_v2.3", .initfn = spapr_cpu_core_POWER7_initfn }, 355 { .name = "POWER7", .initfn = spapr_cpu_core_POWER7_initfn }, 356 357 /* POWER7+ and aliases */ 358 { .name = "POWER7+_v2.1", .initfn = spapr_cpu_core_POWER7plus_initfn }, 359 { .name = "POWER7+", .initfn = spapr_cpu_core_POWER7plus_initfn }, 360 361 /* POWER8 and aliases */ 362 { .name = "POWER8_v2.0", .initfn = spapr_cpu_core_POWER8_initfn }, 363 { .name = "POWER8", .initfn = spapr_cpu_core_POWER8_initfn }, 364 { .name = "power8", .initfn = spapr_cpu_core_POWER8_initfn }, 365 366 /* POWER8E and aliases */ 367 { .name = "POWER8E_v2.1", .initfn = spapr_cpu_core_POWER8E_initfn }, 368 { .name = "POWER8E", .initfn = spapr_cpu_core_POWER8E_initfn }, 369 370 { .name = NULL } 371 }; 372 373 static void spapr_cpu_core_register(const SPAPRCoreInfo *info) 374 { 375 TypeInfo type_info = { 376 .parent = TYPE_SPAPR_CPU_CORE, 377 .instance_size = sizeof(sPAPRCPUCore), 378 .instance_init = info->initfn, 379 }; 380 381 type_info.name = g_strdup_printf("%s-" TYPE_SPAPR_CPU_CORE, info->name); 382 type_register(&type_info); 383 g_free((void *)type_info.name); 384 } 385 386 static const TypeInfo spapr_cpu_core_type_info = { 387 .name = TYPE_SPAPR_CPU_CORE, 388 .parent = TYPE_CPU_CORE, 389 .abstract = true, 390 .instance_size = sizeof(sPAPRCPUCore), 391 .class_init = spapr_cpu_core_class_init, 392 }; 393 394 static void spapr_cpu_core_register_types(void) 395 { 396 const SPAPRCoreInfo *info = spapr_cores; 397 398 type_register_static(&spapr_cpu_core_type_info); 399 while (info->name) { 400 spapr_cpu_core_register(info); 401 info++; 402 } 403 } 404 405 type_init(spapr_cpu_core_register_types) 406