1 /* 2 * sPAPR CPU core device, acts as container of CPU thread devices. 3 * 4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 #include "hw/cpu/core.h" 10 #include "hw/ppc/spapr_cpu_core.h" 11 #include "target/ppc/cpu.h" 12 #include "hw/ppc/spapr.h" 13 #include "hw/boards.h" 14 #include "qapi/error.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/kvm.h" 17 #include "target/ppc/kvm_ppc.h" 18 #include "hw/ppc/ppc.h" 19 #include "target/ppc/mmu-hash64.h" 20 #include "sysemu/numa.h" 21 #include "qemu/error-report.h" 22 23 static void spapr_cpu_reset(void *opaque) 24 { 25 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 26 PowerPCCPU *cpu = opaque; 27 CPUState *cs = CPU(cpu); 28 CPUPPCState *env = &cpu->env; 29 30 cpu_reset(cs); 31 32 /* All CPUs start halted. CPU0 is unhalted from the machine level 33 * reset code and the rest are explicitly started up by the guest 34 * using an RTAS call */ 35 cs->halted = 1; 36 37 env->spr[SPR_HIOR] = 0; 38 39 /* 40 * This is a hack for the benefit of KVM PR - it abuses the SDR1 41 * slot in kvm_sregs to communicate the userspace address of the 42 * HPT 43 */ 44 if (kvm_enabled()) { 45 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab 46 | (spapr->htab_shift - 18); 47 if (kvmppc_put_books_sregs(cpu) < 0) { 48 error_report("Unable to update SDR1 in KVM"); 49 exit(1); 50 } 51 } 52 } 53 54 static void spapr_cpu_destroy(PowerPCCPU *cpu) 55 { 56 qemu_unregister_reset(spapr_cpu_reset, cpu); 57 } 58 59 static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, 60 Error **errp) 61 { 62 CPUPPCState *env = &cpu->env; 63 64 /* Set time-base frequency to 512 MHz */ 65 cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); 66 67 /* Enable PAPR mode in TCG or KVM */ 68 cpu_ppc_set_papr(cpu, PPC_VIRTUAL_HYPERVISOR(spapr)); 69 70 if (cpu->max_compat) { 71 Error *local_err = NULL; 72 73 ppc_set_compat(cpu, cpu->max_compat, &local_err); 74 if (local_err) { 75 error_propagate(errp, local_err); 76 return; 77 } 78 } 79 80 qemu_register_reset(spapr_cpu_reset, cpu); 81 spapr_cpu_reset(cpu); 82 } 83 84 /* 85 * Return the sPAPR CPU core type for @model which essentially is the CPU 86 * model specified with -cpu cmdline option. 87 */ 88 char *spapr_get_cpu_core_type(const char *model) 89 { 90 char *core_type; 91 gchar **model_pieces = g_strsplit(model, ",", 2); 92 93 core_type = g_strdup_printf("%s-%s", model_pieces[0], TYPE_SPAPR_CPU_CORE); 94 95 /* Check whether it exists or whether we have to look up an alias name */ 96 if (!object_class_by_name(core_type)) { 97 const char *realmodel; 98 99 g_free(core_type); 100 core_type = NULL; 101 realmodel = ppc_cpu_lookup_alias(model_pieces[0]); 102 if (realmodel) { 103 core_type = spapr_get_cpu_core_type(realmodel); 104 } 105 } 106 107 g_strfreev(model_pieces); 108 return core_type; 109 } 110 111 static void spapr_cpu_core_unrealizefn(DeviceState *dev, Error **errp) 112 { 113 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 114 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev)); 115 const char *typename = object_class_get_name(scc->cpu_class); 116 size_t size = object_type_get_instance_size(typename); 117 CPUCore *cc = CPU_CORE(dev); 118 int i; 119 120 for (i = 0; i < cc->nr_threads; i++) { 121 void *obj = sc->threads + i * size; 122 DeviceState *dev = DEVICE(obj); 123 CPUState *cs = CPU(dev); 124 PowerPCCPU *cpu = POWERPC_CPU(cs); 125 126 spapr_cpu_destroy(cpu); 127 object_unparent(cpu->intc); 128 cpu_remove_sync(cs); 129 object_unparent(obj); 130 } 131 g_free(sc->threads); 132 } 133 134 static void spapr_cpu_core_realize_child(Object *child, Error **errp) 135 { 136 Error *local_err = NULL; 137 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 138 CPUState *cs = CPU(child); 139 PowerPCCPU *cpu = POWERPC_CPU(cs); 140 Object *obj = NULL; 141 142 object_property_set_bool(child, true, "realized", &local_err); 143 if (local_err) { 144 goto error; 145 } 146 147 spapr_cpu_init(spapr, cpu, &local_err); 148 if (local_err) { 149 goto error; 150 } 151 152 obj = object_new(spapr->icp_type); 153 object_property_add_child(child, "icp", obj, &error_abort); 154 object_unref(obj); 155 object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(spapr), 156 &error_abort); 157 object_property_add_const_link(obj, ICP_PROP_CPU, child, &error_abort); 158 object_property_set_bool(obj, true, "realized", &local_err); 159 if (local_err) { 160 goto error; 161 } 162 163 return; 164 165 error: 166 object_unparent(obj); 167 error_propagate(errp, local_err); 168 } 169 170 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp) 171 { 172 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 173 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev)); 174 CPUCore *cc = CPU_CORE(OBJECT(dev)); 175 const char *typename = object_class_get_name(scc->cpu_class); 176 size_t size = object_type_get_instance_size(typename); 177 Error *local_err = NULL; 178 void *obj; 179 int i, j; 180 181 sc->threads = g_malloc0(size * cc->nr_threads); 182 for (i = 0; i < cc->nr_threads; i++) { 183 char id[32]; 184 CPUState *cs; 185 PowerPCCPU *cpu; 186 187 obj = sc->threads + i * size; 188 189 object_initialize(obj, size, typename); 190 cs = CPU(obj); 191 cpu = POWERPC_CPU(cs); 192 cs->cpu_index = cc->core_id + i; 193 194 /* Set NUMA node for the threads belonged to core */ 195 cpu->node_id = sc->node_id; 196 197 snprintf(id, sizeof(id), "thread[%d]", i); 198 object_property_add_child(OBJECT(sc), id, obj, &local_err); 199 if (local_err) { 200 goto err; 201 } 202 object_unref(obj); 203 } 204 205 for (j = 0; j < cc->nr_threads; j++) { 206 obj = sc->threads + j * size; 207 208 spapr_cpu_core_realize_child(obj, &local_err); 209 if (local_err) { 210 goto err; 211 } 212 } 213 return; 214 215 err: 216 while (--i >= 0) { 217 obj = sc->threads + i * size; 218 object_unparent(obj); 219 } 220 g_free(sc->threads); 221 error_propagate(errp, local_err); 222 } 223 224 static const char *spapr_core_models[] = { 225 /* 970 */ 226 "970_v2.2", 227 228 /* 970MP variants */ 229 "970MP_v1.0", 230 "970mp_v1.0", 231 "970MP_v1.1", 232 "970mp_v1.1", 233 234 /* POWER5+ */ 235 "POWER5+_v2.1", 236 237 /* POWER7 */ 238 "POWER7_v2.3", 239 240 /* POWER7+ */ 241 "POWER7+_v2.1", 242 243 /* POWER8 */ 244 "POWER8_v2.0", 245 246 /* POWER8E */ 247 "POWER8E_v2.1", 248 249 /* POWER8NVL */ 250 "POWER8NVL_v1.0", 251 252 /* POWER9 */ 253 "POWER9_v1.0", 254 }; 255 256 static Property spapr_cpu_core_properties[] = { 257 DEFINE_PROP_INT32("node-id", sPAPRCPUCore, node_id, CPU_UNSET_NUMA_NODE_ID), 258 DEFINE_PROP_END_OF_LIST() 259 }; 260 261 void spapr_cpu_core_class_init(ObjectClass *oc, void *data) 262 { 263 DeviceClass *dc = DEVICE_CLASS(oc); 264 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc); 265 266 dc->realize = spapr_cpu_core_realize; 267 dc->unrealize = spapr_cpu_core_unrealizefn; 268 dc->props = spapr_cpu_core_properties; 269 scc->cpu_class = cpu_class_by_name(TYPE_POWERPC_CPU, data); 270 g_assert(scc->cpu_class); 271 } 272 273 static const TypeInfo spapr_cpu_core_type_info = { 274 .name = TYPE_SPAPR_CPU_CORE, 275 .parent = TYPE_CPU_CORE, 276 .abstract = true, 277 .instance_size = sizeof(sPAPRCPUCore), 278 .class_size = sizeof(sPAPRCPUCoreClass), 279 }; 280 281 static void spapr_cpu_core_register_types(void) 282 { 283 int i; 284 285 type_register_static(&spapr_cpu_core_type_info); 286 287 for (i = 0; i < ARRAY_SIZE(spapr_core_models); i++) { 288 TypeInfo type_info = { 289 .parent = TYPE_SPAPR_CPU_CORE, 290 .instance_size = sizeof(sPAPRCPUCore), 291 .class_init = spapr_cpu_core_class_init, 292 .class_data = (void *) spapr_core_models[i], 293 }; 294 295 type_info.name = g_strdup_printf("%s-" TYPE_SPAPR_CPU_CORE, 296 spapr_core_models[i]); 297 type_register(&type_info); 298 g_free((void *)type_info.name); 299 } 300 } 301 302 type_init(spapr_cpu_core_register_types) 303