1 /* 2 * sPAPR CPU core device, acts as container of CPU thread devices. 3 * 4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/cpu/core.h" 12 #include "hw/ppc/spapr_cpu_core.h" 13 #include "hw/qdev-properties.h" 14 #include "migration/vmstate.h" 15 #include "target/ppc/cpu.h" 16 #include "hw/ppc/spapr.h" 17 #include "qapi/error.h" 18 #include "sysemu/cpus.h" 19 #include "sysemu/kvm.h" 20 #include "target/ppc/kvm_ppc.h" 21 #include "hw/ppc/ppc.h" 22 #include "target/ppc/mmu-hash64.h" 23 #include "sysemu/numa.h" 24 #include "sysemu/reset.h" 25 #include "sysemu/hw_accel.h" 26 #include "qemu/error-report.h" 27 28 static void spapr_reset_vcpu(PowerPCCPU *cpu) 29 { 30 CPUState *cs = CPU(cpu); 31 CPUPPCState *env = &cpu->env; 32 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 33 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 34 target_ulong lpcr; 35 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 36 37 cpu_reset(cs); 38 39 env->spr[SPR_HIOR] = 0; 40 41 lpcr = env->spr[SPR_LPCR]; 42 43 /* Set emulated LPCR to not send interrupts to hypervisor. Note that 44 * under KVM, the actual HW LPCR will be set differently by KVM itself, 45 * the settings below ensure proper operations with TCG in absence of 46 * a real hypervisor. 47 * 48 * Disable Power-saving mode Exit Cause exceptions for the CPU, so 49 * we don't get spurious wakups before an RTAS start-cpu call. 50 * For the same reason, set PSSCR_EC. 51 */ 52 lpcr &= ~(LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm); 53 lpcr |= LPCR_LPES0 | LPCR_LPES1; 54 env->spr[SPR_PSSCR] |= PSSCR_EC; 55 56 ppc_store_lpcr(cpu, lpcr); 57 58 /* Set a full AMOR so guest can use the AMR as it sees fit */ 59 env->spr[SPR_AMOR] = 0xffffffffffffffffull; 60 61 spapr_cpu->vpa_addr = 0; 62 spapr_cpu->slb_shadow_addr = 0; 63 spapr_cpu->slb_shadow_size = 0; 64 spapr_cpu->dtl_addr = 0; 65 spapr_cpu->dtl_size = 0; 66 67 spapr_caps_cpu_apply(spapr, cpu); 68 69 kvm_check_mmu(cpu, &error_fatal); 70 71 spapr_irq_cpu_intc_reset(spapr, cpu); 72 } 73 74 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, 75 target_ulong r1, target_ulong r3, 76 target_ulong r4) 77 { 78 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 79 CPUPPCState *env = &cpu->env; 80 81 env->nip = nip; 82 env->gpr[1] = r1; 83 env->gpr[3] = r3; 84 env->gpr[4] = r4; 85 kvmppc_set_reg_ppc_online(cpu, 1); 86 CPU(cpu)->halted = 0; 87 /* Enable Power-saving mode Exit Cause exceptions */ 88 ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm); 89 } 90 91 /* 92 * Return the sPAPR CPU core type for @model which essentially is the CPU 93 * model specified with -cpu cmdline option. 94 */ 95 const char *spapr_get_cpu_core_type(const char *cpu_type) 96 { 97 int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 98 char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"), 99 len, cpu_type); 100 ObjectClass *oc = object_class_by_name(core_type); 101 102 g_free(core_type); 103 if (!oc) { 104 return NULL; 105 } 106 107 return object_class_get_name(oc); 108 } 109 110 static bool slb_shadow_needed(void *opaque) 111 { 112 SpaprCpuState *spapr_cpu = opaque; 113 114 return spapr_cpu->slb_shadow_addr != 0; 115 } 116 117 static const VMStateDescription vmstate_spapr_cpu_slb_shadow = { 118 .name = "spapr_cpu/vpa/slb_shadow", 119 .version_id = 1, 120 .minimum_version_id = 1, 121 .needed = slb_shadow_needed, 122 .fields = (VMStateField[]) { 123 VMSTATE_UINT64(slb_shadow_addr, SpaprCpuState), 124 VMSTATE_UINT64(slb_shadow_size, SpaprCpuState), 125 VMSTATE_END_OF_LIST() 126 } 127 }; 128 129 static bool dtl_needed(void *opaque) 130 { 131 SpaprCpuState *spapr_cpu = opaque; 132 133 return spapr_cpu->dtl_addr != 0; 134 } 135 136 static const VMStateDescription vmstate_spapr_cpu_dtl = { 137 .name = "spapr_cpu/vpa/dtl", 138 .version_id = 1, 139 .minimum_version_id = 1, 140 .needed = dtl_needed, 141 .fields = (VMStateField[]) { 142 VMSTATE_UINT64(dtl_addr, SpaprCpuState), 143 VMSTATE_UINT64(dtl_size, SpaprCpuState), 144 VMSTATE_END_OF_LIST() 145 } 146 }; 147 148 static bool vpa_needed(void *opaque) 149 { 150 SpaprCpuState *spapr_cpu = opaque; 151 152 return spapr_cpu->vpa_addr != 0; 153 } 154 155 static const VMStateDescription vmstate_spapr_cpu_vpa = { 156 .name = "spapr_cpu/vpa", 157 .version_id = 1, 158 .minimum_version_id = 1, 159 .needed = vpa_needed, 160 .fields = (VMStateField[]) { 161 VMSTATE_UINT64(vpa_addr, SpaprCpuState), 162 VMSTATE_END_OF_LIST() 163 }, 164 .subsections = (const VMStateDescription * []) { 165 &vmstate_spapr_cpu_slb_shadow, 166 &vmstate_spapr_cpu_dtl, 167 NULL 168 } 169 }; 170 171 static const VMStateDescription vmstate_spapr_cpu_state = { 172 .name = "spapr_cpu", 173 .version_id = 1, 174 .minimum_version_id = 1, 175 .fields = (VMStateField[]) { 176 VMSTATE_END_OF_LIST() 177 }, 178 .subsections = (const VMStateDescription * []) { 179 &vmstate_spapr_cpu_vpa, 180 NULL 181 } 182 }; 183 184 static void spapr_unrealize_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc) 185 { 186 if (!sc->pre_3_0_migration) { 187 vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data); 188 } 189 spapr_irq_cpu_intc_destroy(SPAPR_MACHINE(qdev_get_machine()), cpu); 190 qdev_unrealize(DEVICE(cpu)); 191 } 192 193 /* 194 * Called when CPUs are hot-plugged. 195 */ 196 static void spapr_cpu_core_reset(DeviceState *dev) 197 { 198 CPUCore *cc = CPU_CORE(dev); 199 SpaprCpuCore *sc = SPAPR_CPU_CORE(dev); 200 int i; 201 202 for (i = 0; i < cc->nr_threads; i++) { 203 spapr_reset_vcpu(sc->threads[i]); 204 } 205 } 206 207 /* 208 * Called by the machine reset. 209 */ 210 static void spapr_cpu_core_reset_handler(void *opaque) 211 { 212 spapr_cpu_core_reset(opaque); 213 } 214 215 static void spapr_delete_vcpu(PowerPCCPU *cpu) 216 { 217 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 218 219 cpu->machine_data = NULL; 220 g_free(spapr_cpu); 221 object_unparent(OBJECT(cpu)); 222 } 223 224 static void spapr_cpu_core_unrealize(DeviceState *dev) 225 { 226 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 227 CPUCore *cc = CPU_CORE(dev); 228 int i; 229 230 for (i = 0; i < cc->nr_threads; i++) { 231 if (sc->threads[i]) { 232 /* 233 * Since this we can get here from the error path of 234 * spapr_cpu_core_realize(), make sure we only unrealize 235 * vCPUs that have already been realized. 236 */ 237 if (object_property_get_bool(OBJECT(sc->threads[i]), "realized", 238 &error_abort)) { 239 spapr_unrealize_vcpu(sc->threads[i], sc); 240 } 241 spapr_delete_vcpu(sc->threads[i]); 242 } 243 } 244 g_free(sc->threads); 245 qemu_unregister_reset(spapr_cpu_core_reset_handler, sc); 246 } 247 248 static bool spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr, 249 SpaprCpuCore *sc, Error **errp) 250 { 251 CPUPPCState *env = &cpu->env; 252 CPUState *cs = CPU(cpu); 253 254 if (!qdev_realize(DEVICE(cpu), NULL, errp)) { 255 return false; 256 } 257 258 /* Set time-base frequency to 512 MHz */ 259 cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); 260 261 cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr)); 262 kvmppc_set_papr(cpu); 263 264 if (spapr_irq_cpu_intc_create(spapr, cpu, errp) < 0) { 265 qdev_unrealize(DEVICE(cpu)); 266 return false; 267 } 268 269 if (!sc->pre_3_0_migration) { 270 vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state, 271 cpu->machine_data); 272 } 273 return true; 274 } 275 276 static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp) 277 { 278 SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc); 279 CPUCore *cc = CPU_CORE(sc); 280 g_autoptr(Object) obj = NULL; 281 g_autofree char *id = NULL; 282 CPUState *cs; 283 PowerPCCPU *cpu; 284 285 obj = object_new(scc->cpu_type); 286 287 cs = CPU(obj); 288 cpu = POWERPC_CPU(obj); 289 /* 290 * All CPUs start halted. CPU0 is unhalted from the machine level reset code 291 * and the rest are explicitly started up by the guest using an RTAS call. 292 */ 293 cs->start_powered_off = true; 294 cs->cpu_index = cc->core_id + i; 295 if (!spapr_set_vcpu_id(cpu, cs->cpu_index, errp)) { 296 return NULL; 297 } 298 299 cpu->node_id = sc->node_id; 300 301 id = g_strdup_printf("thread[%d]", i); 302 object_property_add_child(OBJECT(sc), id, obj); 303 304 cpu->machine_data = g_new0(SpaprCpuState, 1); 305 306 return cpu; 307 } 308 309 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp) 310 { 311 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user 312 * tries to add a sPAPR CPU core to a non-pseries machine. 313 */ 314 SpaprMachineState *spapr = 315 (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(), 316 TYPE_SPAPR_MACHINE); 317 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 318 CPUCore *cc = CPU_CORE(OBJECT(dev)); 319 int i; 320 321 if (!spapr) { 322 error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine"); 323 return; 324 } 325 326 qemu_register_reset(spapr_cpu_core_reset_handler, sc); 327 sc->threads = g_new0(PowerPCCPU *, cc->nr_threads); 328 for (i = 0; i < cc->nr_threads; i++) { 329 sc->threads[i] = spapr_create_vcpu(sc, i, errp); 330 if (!sc->threads[i] || 331 !spapr_realize_vcpu(sc->threads[i], spapr, sc, errp)) { 332 spapr_cpu_core_unrealize(dev); 333 return; 334 } 335 } 336 } 337 338 static Property spapr_cpu_core_properties[] = { 339 DEFINE_PROP_INT32("node-id", SpaprCpuCore, node_id, CPU_UNSET_NUMA_NODE_ID), 340 DEFINE_PROP_BOOL("pre-3.0-migration", SpaprCpuCore, pre_3_0_migration, 341 false), 342 DEFINE_PROP_END_OF_LIST() 343 }; 344 345 static void spapr_cpu_core_class_init(ObjectClass *oc, void *data) 346 { 347 DeviceClass *dc = DEVICE_CLASS(oc); 348 SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc); 349 350 dc->realize = spapr_cpu_core_realize; 351 dc->unrealize = spapr_cpu_core_unrealize; 352 dc->reset = spapr_cpu_core_reset; 353 device_class_set_props(dc, spapr_cpu_core_properties); 354 scc->cpu_type = data; 355 } 356 357 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \ 358 { \ 359 .parent = TYPE_SPAPR_CPU_CORE, \ 360 .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \ 361 .class_init = spapr_cpu_core_class_init, \ 362 .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \ 363 } 364 365 static const TypeInfo spapr_cpu_core_type_infos[] = { 366 { 367 .name = TYPE_SPAPR_CPU_CORE, 368 .parent = TYPE_CPU_CORE, 369 .abstract = true, 370 .instance_size = sizeof(SpaprCpuCore), 371 .class_size = sizeof(SpaprCpuCoreClass), 372 }, 373 DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"), 374 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"), 375 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"), 376 DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"), 377 DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"), 378 DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"), 379 DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"), 380 DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"), 381 DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"), 382 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"), 383 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), 384 DEFINE_SPAPR_CPU_CORE_TYPE("power10_v1.0"), 385 DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"), 386 #ifdef CONFIG_KVM 387 DEFINE_SPAPR_CPU_CORE_TYPE("host"), 388 #endif 389 }; 390 391 DEFINE_TYPES(spapr_cpu_core_type_infos) 392