1 /* 2 * sPAPR CPU core device, acts as container of CPU thread devices. 3 * 4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 #include "qemu/osdep.h" 10 #include "hw/cpu/core.h" 11 #include "hw/ppc/spapr_cpu_core.h" 12 #include "target/ppc/cpu.h" 13 #include "hw/ppc/spapr.h" 14 #include "hw/ppc/xics.h" /* for icp_create() - to be removed */ 15 #include "hw/boards.h" 16 #include "qapi/error.h" 17 #include "sysemu/cpus.h" 18 #include "sysemu/kvm.h" 19 #include "target/ppc/kvm_ppc.h" 20 #include "hw/ppc/ppc.h" 21 #include "target/ppc/mmu-hash64.h" 22 #include "sysemu/numa.h" 23 #include "sysemu/hw_accel.h" 24 #include "qemu/error-report.h" 25 26 static void spapr_cpu_reset(void *opaque) 27 { 28 PowerPCCPU *cpu = opaque; 29 CPUState *cs = CPU(cpu); 30 CPUPPCState *env = &cpu->env; 31 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 32 sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu); 33 target_ulong lpcr; 34 35 cpu_reset(cs); 36 37 /* All CPUs start halted. CPU0 is unhalted from the machine level 38 * reset code and the rest are explicitly started up by the guest 39 * using an RTAS call */ 40 cs->halted = 1; 41 42 /* Set compatibility mode to match the boot CPU, which was either set 43 * by the machine reset code or by CAS. This should never fail. 44 */ 45 ppc_set_compat(cpu, POWERPC_CPU(first_cpu)->compat_pvr, &error_abort); 46 47 env->spr[SPR_HIOR] = 0; 48 49 lpcr = env->spr[SPR_LPCR]; 50 51 /* Set emulated LPCR to not send interrupts to hypervisor. Note that 52 * under KVM, the actual HW LPCR will be set differently by KVM itself, 53 * the settings below ensure proper operations with TCG in absence of 54 * a real hypervisor. 55 * 56 * Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for 57 * real mode accesses, which thankfully defaults to 0 and isn't 58 * accessible in guest mode. 59 * 60 * Disable Power-saving mode Exit Cause exceptions for the CPU, so 61 * we don't get spurious wakups before an RTAS start-cpu call. 62 */ 63 lpcr &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm); 64 lpcr |= LPCR_LPES0 | LPCR_LPES1; 65 66 /* Set RMLS to the max (ie, 16G) */ 67 lpcr &= ~LPCR_RMLS; 68 lpcr |= 1ull << LPCR_RMLS_SHIFT; 69 70 ppc_store_lpcr(cpu, lpcr); 71 72 /* Set a full AMOR so guest can use the AMR as it sees fit */ 73 env->spr[SPR_AMOR] = 0xffffffffffffffffull; 74 75 spapr_cpu->vpa_addr = 0; 76 spapr_cpu->slb_shadow_addr = 0; 77 spapr_cpu->slb_shadow_size = 0; 78 spapr_cpu->dtl_addr = 0; 79 spapr_cpu->dtl_size = 0; 80 81 spapr_caps_cpu_apply(SPAPR_MACHINE(qdev_get_machine()), cpu); 82 83 kvm_check_mmu(cpu, &error_fatal); 84 } 85 86 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3) 87 { 88 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 89 CPUPPCState *env = &cpu->env; 90 91 env->nip = nip; 92 env->gpr[3] = r3; 93 kvmppc_set_reg_ppc_online(cpu, 1); 94 CPU(cpu)->halted = 0; 95 /* Enable Power-saving mode Exit Cause exceptions */ 96 ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm); 97 } 98 99 /* 100 * Return the sPAPR CPU core type for @model which essentially is the CPU 101 * model specified with -cpu cmdline option. 102 */ 103 const char *spapr_get_cpu_core_type(const char *cpu_type) 104 { 105 int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 106 char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"), 107 len, cpu_type); 108 ObjectClass *oc = object_class_by_name(core_type); 109 110 g_free(core_type); 111 if (!oc) { 112 return NULL; 113 } 114 115 return object_class_get_name(oc); 116 } 117 118 static bool slb_shadow_needed(void *opaque) 119 { 120 sPAPRCPUState *spapr_cpu = opaque; 121 122 return spapr_cpu->slb_shadow_addr != 0; 123 } 124 125 static const VMStateDescription vmstate_spapr_cpu_slb_shadow = { 126 .name = "spapr_cpu/vpa/slb_shadow", 127 .version_id = 1, 128 .minimum_version_id = 1, 129 .needed = slb_shadow_needed, 130 .fields = (VMStateField[]) { 131 VMSTATE_UINT64(slb_shadow_addr, sPAPRCPUState), 132 VMSTATE_UINT64(slb_shadow_size, sPAPRCPUState), 133 VMSTATE_END_OF_LIST() 134 } 135 }; 136 137 static bool dtl_needed(void *opaque) 138 { 139 sPAPRCPUState *spapr_cpu = opaque; 140 141 return spapr_cpu->dtl_addr != 0; 142 } 143 144 static const VMStateDescription vmstate_spapr_cpu_dtl = { 145 .name = "spapr_cpu/vpa/dtl", 146 .version_id = 1, 147 .minimum_version_id = 1, 148 .needed = dtl_needed, 149 .fields = (VMStateField[]) { 150 VMSTATE_UINT64(dtl_addr, sPAPRCPUState), 151 VMSTATE_UINT64(dtl_size, sPAPRCPUState), 152 VMSTATE_END_OF_LIST() 153 } 154 }; 155 156 static bool vpa_needed(void *opaque) 157 { 158 sPAPRCPUState *spapr_cpu = opaque; 159 160 return spapr_cpu->vpa_addr != 0; 161 } 162 163 static const VMStateDescription vmstate_spapr_cpu_vpa = { 164 .name = "spapr_cpu/vpa", 165 .version_id = 1, 166 .minimum_version_id = 1, 167 .needed = vpa_needed, 168 .fields = (VMStateField[]) { 169 VMSTATE_UINT64(vpa_addr, sPAPRCPUState), 170 VMSTATE_END_OF_LIST() 171 }, 172 .subsections = (const VMStateDescription * []) { 173 &vmstate_spapr_cpu_slb_shadow, 174 &vmstate_spapr_cpu_dtl, 175 NULL 176 } 177 }; 178 179 static const VMStateDescription vmstate_spapr_cpu_state = { 180 .name = "spapr_cpu", 181 .version_id = 1, 182 .minimum_version_id = 1, 183 .fields = (VMStateField[]) { 184 VMSTATE_END_OF_LIST() 185 }, 186 .subsections = (const VMStateDescription * []) { 187 &vmstate_spapr_cpu_vpa, 188 NULL 189 } 190 }; 191 192 static void spapr_unrealize_vcpu(PowerPCCPU *cpu, sPAPRCPUCore *sc) 193 { 194 if (!sc->pre_3_0_migration) { 195 vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data); 196 } 197 qemu_unregister_reset(spapr_cpu_reset, cpu); 198 object_unparent(cpu->intc); 199 cpu_remove_sync(CPU(cpu)); 200 object_unparent(OBJECT(cpu)); 201 } 202 203 static void spapr_cpu_core_unrealize(DeviceState *dev, Error **errp) 204 { 205 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 206 CPUCore *cc = CPU_CORE(dev); 207 int i; 208 209 for (i = 0; i < cc->nr_threads; i++) { 210 spapr_unrealize_vcpu(sc->threads[i], sc); 211 } 212 g_free(sc->threads); 213 } 214 215 static void spapr_realize_vcpu(PowerPCCPU *cpu, sPAPRMachineState *spapr, 216 sPAPRCPUCore *sc, Error **errp) 217 { 218 CPUPPCState *env = &cpu->env; 219 CPUState *cs = CPU(cpu); 220 Error *local_err = NULL; 221 222 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 223 if (local_err) { 224 goto error; 225 } 226 227 /* Set time-base frequency to 512 MHz */ 228 cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); 229 230 cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr)); 231 kvmppc_set_papr(cpu); 232 233 qemu_register_reset(spapr_cpu_reset, cpu); 234 spapr_cpu_reset(cpu); 235 236 cpu->intc = icp_create(OBJECT(cpu), spapr->icp_type, XICS_FABRIC(spapr), 237 &local_err); 238 if (local_err) { 239 goto error_unregister; 240 } 241 242 if (!sc->pre_3_0_migration) { 243 vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state, 244 cpu->machine_data); 245 } 246 247 return; 248 249 error_unregister: 250 qemu_unregister_reset(spapr_cpu_reset, cpu); 251 cpu_remove_sync(CPU(cpu)); 252 error: 253 error_propagate(errp, local_err); 254 } 255 256 static PowerPCCPU *spapr_create_vcpu(sPAPRCPUCore *sc, int i, Error **errp) 257 { 258 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc); 259 CPUCore *cc = CPU_CORE(sc); 260 Object *obj; 261 char *id; 262 CPUState *cs; 263 PowerPCCPU *cpu; 264 Error *local_err = NULL; 265 266 obj = object_new(scc->cpu_type); 267 268 cs = CPU(obj); 269 cpu = POWERPC_CPU(obj); 270 cs->cpu_index = cc->core_id + i; 271 spapr_set_vcpu_id(cpu, cs->cpu_index, &local_err); 272 if (local_err) { 273 goto err; 274 } 275 276 cpu->node_id = sc->node_id; 277 278 id = g_strdup_printf("thread[%d]", i); 279 object_property_add_child(OBJECT(sc), id, obj, &local_err); 280 g_free(id); 281 if (local_err) { 282 goto err; 283 } 284 285 cpu->machine_data = g_new0(sPAPRCPUState, 1); 286 287 object_unref(obj); 288 return cpu; 289 290 err: 291 object_unref(obj); 292 error_propagate(errp, local_err); 293 return NULL; 294 } 295 296 static void spapr_delete_vcpu(PowerPCCPU *cpu, sPAPRCPUCore *sc) 297 { 298 sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu); 299 300 cpu->machine_data = NULL; 301 g_free(spapr_cpu); 302 object_unparent(OBJECT(cpu)); 303 } 304 305 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp) 306 { 307 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user 308 * tries to add a sPAPR CPU core to a non-pseries machine. 309 */ 310 sPAPRMachineState *spapr = 311 (sPAPRMachineState *) object_dynamic_cast(qdev_get_machine(), 312 TYPE_SPAPR_MACHINE); 313 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 314 CPUCore *cc = CPU_CORE(OBJECT(dev)); 315 Error *local_err = NULL; 316 int i, j; 317 318 if (!spapr) { 319 error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine"); 320 return; 321 } 322 323 sc->threads = g_new(PowerPCCPU *, cc->nr_threads); 324 for (i = 0; i < cc->nr_threads; i++) { 325 sc->threads[i] = spapr_create_vcpu(sc, i, &local_err); 326 if (local_err) { 327 goto err; 328 } 329 } 330 331 for (j = 0; j < cc->nr_threads; j++) { 332 spapr_realize_vcpu(sc->threads[j], spapr, sc, &local_err); 333 if (local_err) { 334 goto err_unrealize; 335 } 336 } 337 return; 338 339 err_unrealize: 340 while (--j >= 0) { 341 spapr_unrealize_vcpu(sc->threads[j], sc); 342 } 343 err: 344 while (--i >= 0) { 345 spapr_delete_vcpu(sc->threads[i], sc); 346 } 347 g_free(sc->threads); 348 error_propagate(errp, local_err); 349 } 350 351 static Property spapr_cpu_core_properties[] = { 352 DEFINE_PROP_INT32("node-id", sPAPRCPUCore, node_id, CPU_UNSET_NUMA_NODE_ID), 353 DEFINE_PROP_BOOL("pre-3.0-migration", sPAPRCPUCore, pre_3_0_migration, 354 false), 355 DEFINE_PROP_END_OF_LIST() 356 }; 357 358 static void spapr_cpu_core_class_init(ObjectClass *oc, void *data) 359 { 360 DeviceClass *dc = DEVICE_CLASS(oc); 361 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc); 362 363 dc->realize = spapr_cpu_core_realize; 364 dc->unrealize = spapr_cpu_core_unrealize; 365 dc->props = spapr_cpu_core_properties; 366 scc->cpu_type = data; 367 } 368 369 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \ 370 { \ 371 .parent = TYPE_SPAPR_CPU_CORE, \ 372 .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \ 373 .class_init = spapr_cpu_core_class_init, \ 374 .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \ 375 } 376 377 static const TypeInfo spapr_cpu_core_type_infos[] = { 378 { 379 .name = TYPE_SPAPR_CPU_CORE, 380 .parent = TYPE_CPU_CORE, 381 .abstract = true, 382 .instance_size = sizeof(sPAPRCPUCore), 383 .class_size = sizeof(sPAPRCPUCoreClass), 384 }, 385 DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"), 386 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"), 387 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"), 388 DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"), 389 DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"), 390 DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"), 391 DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"), 392 DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"), 393 DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"), 394 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"), 395 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), 396 #ifdef CONFIG_KVM 397 DEFINE_SPAPR_CPU_CORE_TYPE("host"), 398 #endif 399 }; 400 401 DEFINE_TYPES(spapr_cpu_core_type_infos) 402