1 /* 2 * sPAPR CPU core device, acts as container of CPU thread devices. 3 * 4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 #include "qemu/osdep.h" 10 #include "hw/cpu/core.h" 11 #include "hw/ppc/spapr_cpu_core.h" 12 #include "target/ppc/cpu.h" 13 #include "hw/ppc/spapr.h" 14 #include "hw/boards.h" 15 #include "qapi/error.h" 16 #include "sysemu/cpus.h" 17 #include "sysemu/kvm.h" 18 #include "target/ppc/kvm_ppc.h" 19 #include "hw/ppc/ppc.h" 20 #include "target/ppc/mmu-hash64.h" 21 #include "sysemu/numa.h" 22 #include "sysemu/hw_accel.h" 23 #include "qemu/error-report.h" 24 25 static void spapr_cpu_reset(void *opaque) 26 { 27 PowerPCCPU *cpu = opaque; 28 CPUState *cs = CPU(cpu); 29 CPUPPCState *env = &cpu->env; 30 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 31 32 cpu_reset(cs); 33 34 /* All CPUs start halted. CPU0 is unhalted from the machine level 35 * reset code and the rest are explicitly started up by the guest 36 * using an RTAS call */ 37 cs->halted = 1; 38 39 env->spr[SPR_HIOR] = 0; 40 41 /* Disable Power-saving mode Exit Cause exceptions for the CPU. 42 * This can cause issues when rebooting the guest if a secondary 43 * is awaken */ 44 if (cs != first_cpu) { 45 env->spr[SPR_LPCR] &= ~pcc->lpcr_pm; 46 } 47 48 /* Set compatibility mode to match the boot CPU, which was either set 49 * by the machine reset code or by CAS. This should never fail. 50 */ 51 if (cs != first_cpu) { 52 ppc_set_compat(cpu, POWERPC_CPU(first_cpu)->compat_pvr, &error_abort); 53 } 54 } 55 56 static void spapr_cpu_destroy(PowerPCCPU *cpu) 57 { 58 qemu_unregister_reset(spapr_cpu_reset, cpu); 59 } 60 61 static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, 62 Error **errp) 63 { 64 CPUPPCState *env = &cpu->env; 65 66 /* Set time-base frequency to 512 MHz */ 67 cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); 68 69 /* Enable PAPR mode in TCG or KVM */ 70 cpu_ppc_set_papr(cpu, PPC_VIRTUAL_HYPERVISOR(spapr)); 71 72 qemu_register_reset(spapr_cpu_reset, cpu); 73 spapr_cpu_reset(cpu); 74 } 75 76 /* 77 * Return the sPAPR CPU core type for @model which essentially is the CPU 78 * model specified with -cpu cmdline option. 79 */ 80 const char *spapr_get_cpu_core_type(const char *cpu_type) 81 { 82 int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 83 char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"), 84 len, cpu_type); 85 ObjectClass *oc = object_class_by_name(core_type); 86 87 g_free(core_type); 88 if (!oc) { 89 return NULL; 90 } 91 92 return object_class_get_name(oc); 93 } 94 95 static void spapr_cpu_core_unrealizefn(DeviceState *dev, Error **errp) 96 { 97 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 98 CPUCore *cc = CPU_CORE(dev); 99 int i; 100 101 for (i = 0; i < cc->nr_threads; i++) { 102 Object *obj = OBJECT(sc->threads[i]); 103 DeviceState *dev = DEVICE(obj); 104 CPUState *cs = CPU(dev); 105 PowerPCCPU *cpu = POWERPC_CPU(cs); 106 107 spapr_cpu_destroy(cpu); 108 object_unparent(cpu->intc); 109 cpu_remove_sync(cs); 110 object_unparent(obj); 111 } 112 g_free(sc->threads); 113 } 114 115 static void spapr_cpu_core_realize_child(Object *child, 116 sPAPRMachineState *spapr, Error **errp) 117 { 118 Error *local_err = NULL; 119 CPUState *cs = CPU(child); 120 PowerPCCPU *cpu = POWERPC_CPU(cs); 121 122 object_property_set_bool(child, true, "realized", &local_err); 123 if (local_err) { 124 goto error; 125 } 126 127 spapr_cpu_init(spapr, cpu, &local_err); 128 if (local_err) { 129 goto error; 130 } 131 132 cpu->intc = icp_create(child, spapr->icp_type, XICS_FABRIC(spapr), 133 &local_err); 134 if (local_err) { 135 goto error; 136 } 137 138 return; 139 140 error: 141 error_propagate(errp, local_err); 142 } 143 144 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp) 145 { 146 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user 147 * tries to add a sPAPR CPU core to a non-pseries machine. 148 */ 149 sPAPRMachineState *spapr = 150 (sPAPRMachineState *) object_dynamic_cast(qdev_get_machine(), 151 TYPE_SPAPR_MACHINE); 152 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 153 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev)); 154 CPUCore *cc = CPU_CORE(OBJECT(dev)); 155 Error *local_err = NULL; 156 Object *obj; 157 int i, j; 158 159 if (!spapr) { 160 error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine"); 161 return; 162 } 163 164 sc->threads = g_new(PowerPCCPU *, cc->nr_threads); 165 for (i = 0; i < cc->nr_threads; i++) { 166 char id[32]; 167 CPUState *cs; 168 PowerPCCPU *cpu; 169 170 obj = object_new(scc->cpu_type); 171 172 cs = CPU(obj); 173 cpu = sc->threads[i] = POWERPC_CPU(obj); 174 cs->cpu_index = cc->core_id + i; 175 cpu->vcpu_id = (cc->core_id * spapr->vsmt / smp_threads) + i; 176 if (kvm_enabled() && !kvm_vcpu_id_is_valid(cpu->vcpu_id)) { 177 error_setg(&local_err, "Can't create CPU with id %d in KVM", 178 cpu->vcpu_id); 179 error_append_hint(&local_err, "Adjust the number of cpus to %d " 180 "or try to raise the number of threads per core\n", 181 cpu->vcpu_id * smp_threads / spapr->vsmt); 182 goto err; 183 } 184 185 186 /* Set NUMA node for the threads belonged to core */ 187 cpu->node_id = sc->node_id; 188 189 snprintf(id, sizeof(id), "thread[%d]", i); 190 object_property_add_child(OBJECT(sc), id, obj, &local_err); 191 if (local_err) { 192 goto err; 193 } 194 object_unref(obj); 195 } 196 197 for (j = 0; j < cc->nr_threads; j++) { 198 obj = OBJECT(sc->threads[j]); 199 200 spapr_cpu_core_realize_child(obj, spapr, &local_err); 201 if (local_err) { 202 goto err; 203 } 204 } 205 return; 206 207 err: 208 while (--i >= 0) { 209 obj = OBJECT(sc->threads[i]); 210 object_unparent(obj); 211 } 212 g_free(sc->threads); 213 error_propagate(errp, local_err); 214 } 215 216 static Property spapr_cpu_core_properties[] = { 217 DEFINE_PROP_INT32("node-id", sPAPRCPUCore, node_id, CPU_UNSET_NUMA_NODE_ID), 218 DEFINE_PROP_END_OF_LIST() 219 }; 220 221 static void spapr_cpu_core_class_init(ObjectClass *oc, void *data) 222 { 223 DeviceClass *dc = DEVICE_CLASS(oc); 224 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc); 225 226 dc->realize = spapr_cpu_core_realize; 227 dc->unrealize = spapr_cpu_core_unrealizefn; 228 dc->props = spapr_cpu_core_properties; 229 scc->cpu_type = data; 230 } 231 232 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \ 233 { \ 234 .parent = TYPE_SPAPR_CPU_CORE, \ 235 .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \ 236 .class_init = spapr_cpu_core_class_init, \ 237 .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \ 238 } 239 240 static const TypeInfo spapr_cpu_core_type_infos[] = { 241 { 242 .name = TYPE_SPAPR_CPU_CORE, 243 .parent = TYPE_CPU_CORE, 244 .abstract = true, 245 .instance_size = sizeof(sPAPRCPUCore), 246 .class_size = sizeof(sPAPRCPUCoreClass), 247 }, 248 DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"), 249 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"), 250 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"), 251 DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"), 252 DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"), 253 DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"), 254 DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"), 255 DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"), 256 DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"), 257 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"), 258 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), 259 #ifdef CONFIG_KVM 260 DEFINE_SPAPR_CPU_CORE_TYPE("host"), 261 #endif 262 }; 263 264 DEFINE_TYPES(spapr_cpu_core_type_infos) 265