1 /* 2 * sPAPR CPU core device, acts as container of CPU thread devices. 3 * 4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 #include "hw/cpu/core.h" 10 #include "hw/ppc/spapr_cpu_core.h" 11 #include "target/ppc/cpu.h" 12 #include "hw/ppc/spapr.h" 13 #include "hw/boards.h" 14 #include "qapi/error.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/kvm.h" 17 #include "target/ppc/kvm_ppc.h" 18 #include "hw/ppc/ppc.h" 19 #include "target/ppc/mmu-hash64.h" 20 #include "sysemu/numa.h" 21 #include "sysemu/hw_accel.h" 22 #include "qemu/error-report.h" 23 24 static void spapr_cpu_reset(void *opaque) 25 { 26 PowerPCCPU *cpu = opaque; 27 CPUState *cs = CPU(cpu); 28 CPUPPCState *env = &cpu->env; 29 30 cpu_reset(cs); 31 32 /* All CPUs start halted. CPU0 is unhalted from the machine level 33 * reset code and the rest are explicitly started up by the guest 34 * using an RTAS call */ 35 cs->halted = 1; 36 37 env->spr[SPR_HIOR] = 0; 38 } 39 40 static void spapr_cpu_destroy(PowerPCCPU *cpu) 41 { 42 qemu_unregister_reset(spapr_cpu_reset, cpu); 43 } 44 45 static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, 46 Error **errp) 47 { 48 CPUPPCState *env = &cpu->env; 49 50 /* Set time-base frequency to 512 MHz */ 51 cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); 52 53 /* Enable PAPR mode in TCG or KVM */ 54 cpu_ppc_set_papr(cpu, PPC_VIRTUAL_HYPERVISOR(spapr)); 55 56 qemu_register_reset(spapr_cpu_reset, cpu); 57 spapr_cpu_reset(cpu); 58 } 59 60 /* 61 * Return the sPAPR CPU core type for @model which essentially is the CPU 62 * model specified with -cpu cmdline option. 63 */ 64 const char *spapr_get_cpu_core_type(const char *cpu_type) 65 { 66 int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 67 char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"), 68 len, cpu_type); 69 ObjectClass *oc = object_class_by_name(core_type); 70 71 g_free(core_type); 72 if (!oc) { 73 return NULL; 74 } 75 76 return object_class_get_name(oc); 77 } 78 79 static void spapr_cpu_core_unrealizefn(DeviceState *dev, Error **errp) 80 { 81 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 82 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev)); 83 size_t size = object_type_get_instance_size(scc->cpu_type); 84 CPUCore *cc = CPU_CORE(dev); 85 int i; 86 87 for (i = 0; i < cc->nr_threads; i++) { 88 void *obj = sc->threads + i * size; 89 DeviceState *dev = DEVICE(obj); 90 CPUState *cs = CPU(dev); 91 PowerPCCPU *cpu = POWERPC_CPU(cs); 92 93 spapr_cpu_destroy(cpu); 94 object_unparent(cpu->intc); 95 cpu_remove_sync(cs); 96 object_unparent(obj); 97 } 98 g_free(sc->threads); 99 } 100 101 static void spapr_cpu_core_realize_child(Object *child, 102 sPAPRMachineState *spapr, Error **errp) 103 { 104 Error *local_err = NULL; 105 CPUState *cs = CPU(child); 106 PowerPCCPU *cpu = POWERPC_CPU(cs); 107 Object *obj; 108 109 object_property_set_bool(child, true, "realized", &local_err); 110 if (local_err) { 111 goto error; 112 } 113 114 spapr_cpu_init(spapr, cpu, &local_err); 115 if (local_err) { 116 goto error; 117 } 118 119 obj = object_new(spapr->icp_type); 120 object_property_add_child(child, "icp", obj, &error_abort); 121 object_unref(obj); 122 object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(spapr), 123 &error_abort); 124 object_property_add_const_link(obj, ICP_PROP_CPU, child, &error_abort); 125 object_property_set_bool(obj, true, "realized", &local_err); 126 if (local_err) { 127 goto free_icp; 128 } 129 130 return; 131 132 free_icp: 133 object_unparent(obj); 134 error: 135 error_propagate(errp, local_err); 136 } 137 138 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp) 139 { 140 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user 141 * tries to add a sPAPR CPU core to a non-pseries machine. 142 */ 143 sPAPRMachineState *spapr = 144 (sPAPRMachineState *) object_dynamic_cast(qdev_get_machine(), 145 TYPE_SPAPR_MACHINE); 146 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 147 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev)); 148 CPUCore *cc = CPU_CORE(OBJECT(dev)); 149 size_t size; 150 Error *local_err = NULL; 151 void *obj; 152 int i, j; 153 154 if (!spapr) { 155 error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine"); 156 return; 157 } 158 159 size = object_type_get_instance_size(scc->cpu_type); 160 sc->threads = g_malloc0(size * cc->nr_threads); 161 for (i = 0; i < cc->nr_threads; i++) { 162 char id[32]; 163 CPUState *cs; 164 PowerPCCPU *cpu; 165 166 obj = sc->threads + i * size; 167 168 object_initialize(obj, size, scc->cpu_type); 169 cs = CPU(obj); 170 cpu = POWERPC_CPU(cs); 171 cs->cpu_index = cc->core_id + i; 172 cpu->vcpu_id = (cc->core_id * spapr->vsmt / smp_threads) + i; 173 if (kvm_enabled() && !kvm_vcpu_id_is_valid(cpu->vcpu_id)) { 174 error_setg(&local_err, "Can't create CPU with id %d in KVM", 175 cpu->vcpu_id); 176 error_append_hint(&local_err, "Adjust the number of cpus to %d " 177 "or try to raise the number of threads per core\n", 178 cpu->vcpu_id * smp_threads / spapr->vsmt); 179 goto err; 180 } 181 182 183 /* Set NUMA node for the threads belonged to core */ 184 cpu->node_id = sc->node_id; 185 186 snprintf(id, sizeof(id), "thread[%d]", i); 187 object_property_add_child(OBJECT(sc), id, obj, &local_err); 188 if (local_err) { 189 goto err; 190 } 191 object_unref(obj); 192 } 193 194 for (j = 0; j < cc->nr_threads; j++) { 195 obj = sc->threads + j * size; 196 197 spapr_cpu_core_realize_child(obj, spapr, &local_err); 198 if (local_err) { 199 goto err; 200 } 201 } 202 return; 203 204 err: 205 while (--i >= 0) { 206 obj = sc->threads + i * size; 207 object_unparent(obj); 208 } 209 g_free(sc->threads); 210 error_propagate(errp, local_err); 211 } 212 213 static Property spapr_cpu_core_properties[] = { 214 DEFINE_PROP_INT32("node-id", sPAPRCPUCore, node_id, CPU_UNSET_NUMA_NODE_ID), 215 DEFINE_PROP_END_OF_LIST() 216 }; 217 218 static void spapr_cpu_core_class_init(ObjectClass *oc, void *data) 219 { 220 DeviceClass *dc = DEVICE_CLASS(oc); 221 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc); 222 223 dc->realize = spapr_cpu_core_realize; 224 dc->unrealize = spapr_cpu_core_unrealizefn; 225 dc->props = spapr_cpu_core_properties; 226 scc->cpu_type = data; 227 } 228 229 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \ 230 { \ 231 .parent = TYPE_SPAPR_CPU_CORE, \ 232 .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \ 233 .class_init = spapr_cpu_core_class_init, \ 234 .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \ 235 } 236 237 static const TypeInfo spapr_cpu_core_type_infos[] = { 238 { 239 .name = TYPE_SPAPR_CPU_CORE, 240 .parent = TYPE_CPU_CORE, 241 .abstract = true, 242 .instance_size = sizeof(sPAPRCPUCore), 243 .class_size = sizeof(sPAPRCPUCoreClass), 244 }, 245 DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"), 246 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"), 247 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"), 248 DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"), 249 DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"), 250 DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"), 251 DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"), 252 DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"), 253 DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"), 254 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"), 255 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), 256 #ifdef CONFIG_KVM 257 DEFINE_SPAPR_CPU_CORE_TYPE("host"), 258 #endif 259 }; 260 261 DEFINE_TYPES(spapr_cpu_core_type_infos) 262