1 /* 2 * sPAPR CPU core device, acts as container of CPU thread devices. 3 * 4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/cpu/core.h" 12 #include "hw/ppc/spapr_cpu_core.h" 13 #include "hw/qdev-properties.h" 14 #include "migration/vmstate.h" 15 #include "target/ppc/cpu.h" 16 #include "hw/ppc/spapr.h" 17 #include "qapi/error.h" 18 #include "sysemu/cpus.h" 19 #include "sysemu/kvm.h" 20 #include "target/ppc/kvm_ppc.h" 21 #include "hw/ppc/ppc.h" 22 #include "target/ppc/mmu-hash64.h" 23 #include "target/ppc/power8-pmu.h" 24 #include "sysemu/numa.h" 25 #include "sysemu/reset.h" 26 #include "sysemu/hw_accel.h" 27 #include "qemu/error-report.h" 28 29 static void spapr_reset_vcpu(PowerPCCPU *cpu) 30 { 31 CPUState *cs = CPU(cpu); 32 CPUPPCState *env = &cpu->env; 33 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 34 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 35 target_ulong lpcr; 36 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 37 38 cpu_reset(cs); 39 40 /* 41 * "PowerPC Processor binding to IEEE 1275" defines the initial MSR state 42 * as 32bit (MSR_SF=0) with MSR_ME=1 and MSR_FP=1 in "8.2.1. Initial 43 * Register Values". This can also be found in "LoPAPR 1.1" "C.9.2.1 44 * Initial Register Values". 45 */ 46 env->msr &= ~(1ULL << MSR_SF); 47 env->msr |= (1ULL << MSR_ME) | (1ULL << MSR_FP); 48 49 env->spr[SPR_HIOR] = 0; 50 51 lpcr = env->spr[SPR_LPCR]; 52 53 /* Set emulated LPCR to not send interrupts to hypervisor. Note that 54 * under KVM, the actual HW LPCR will be set differently by KVM itself, 55 * the settings below ensure proper operations with TCG in absence of 56 * a real hypervisor. 57 * 58 * Disable Power-saving mode Exit Cause exceptions for the CPU, so 59 * we don't get spurious wakups before an RTAS start-cpu call. 60 * For the same reason, set PSSCR_EC. 61 */ 62 lpcr &= ~(LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm); 63 lpcr |= LPCR_LPES0 | LPCR_LPES1; 64 env->spr[SPR_PSSCR] |= PSSCR_EC; 65 66 ppc_store_lpcr(cpu, lpcr); 67 68 /* Set a full AMOR so guest can use the AMR as it sees fit */ 69 env->spr[SPR_AMOR] = 0xffffffffffffffffull; 70 71 spapr_cpu->vpa_addr = 0; 72 spapr_cpu->slb_shadow_addr = 0; 73 spapr_cpu->slb_shadow_size = 0; 74 spapr_cpu->dtl_addr = 0; 75 spapr_cpu->dtl_size = 0; 76 77 spapr_caps_cpu_apply(spapr, cpu); 78 79 kvm_check_mmu(cpu, &error_fatal); 80 81 cpu_ppc_tb_reset(env); 82 83 spapr_irq_cpu_intc_reset(spapr, cpu); 84 } 85 86 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, 87 target_ulong r1, target_ulong r3, 88 target_ulong r4) 89 { 90 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 91 CPUPPCState *env = &cpu->env; 92 93 env->nip = nip; 94 env->gpr[1] = r1; 95 env->gpr[3] = r3; 96 env->gpr[4] = r4; 97 kvmppc_set_reg_ppc_online(cpu, 1); 98 CPU(cpu)->halted = 0; 99 /* Enable Power-saving mode Exit Cause exceptions */ 100 ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm); 101 } 102 103 /* 104 * Return the sPAPR CPU core type for @model which essentially is the CPU 105 * model specified with -cpu cmdline option. 106 */ 107 const char *spapr_get_cpu_core_type(const char *cpu_type) 108 { 109 int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 110 char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"), 111 len, cpu_type); 112 ObjectClass *oc = object_class_by_name(core_type); 113 114 g_free(core_type); 115 if (!oc) { 116 return NULL; 117 } 118 119 return object_class_get_name(oc); 120 } 121 122 static bool slb_shadow_needed(void *opaque) 123 { 124 SpaprCpuState *spapr_cpu = opaque; 125 126 return spapr_cpu->slb_shadow_addr != 0; 127 } 128 129 static const VMStateDescription vmstate_spapr_cpu_slb_shadow = { 130 .name = "spapr_cpu/vpa/slb_shadow", 131 .version_id = 1, 132 .minimum_version_id = 1, 133 .needed = slb_shadow_needed, 134 .fields = (const VMStateField[]) { 135 VMSTATE_UINT64(slb_shadow_addr, SpaprCpuState), 136 VMSTATE_UINT64(slb_shadow_size, SpaprCpuState), 137 VMSTATE_END_OF_LIST() 138 } 139 }; 140 141 static bool dtl_needed(void *opaque) 142 { 143 SpaprCpuState *spapr_cpu = opaque; 144 145 return spapr_cpu->dtl_addr != 0; 146 } 147 148 static const VMStateDescription vmstate_spapr_cpu_dtl = { 149 .name = "spapr_cpu/vpa/dtl", 150 .version_id = 1, 151 .minimum_version_id = 1, 152 .needed = dtl_needed, 153 .fields = (const VMStateField[]) { 154 VMSTATE_UINT64(dtl_addr, SpaprCpuState), 155 VMSTATE_UINT64(dtl_size, SpaprCpuState), 156 VMSTATE_END_OF_LIST() 157 } 158 }; 159 160 static bool vpa_needed(void *opaque) 161 { 162 SpaprCpuState *spapr_cpu = opaque; 163 164 return spapr_cpu->vpa_addr != 0; 165 } 166 167 static const VMStateDescription vmstate_spapr_cpu_vpa = { 168 .name = "spapr_cpu/vpa", 169 .version_id = 1, 170 .minimum_version_id = 1, 171 .needed = vpa_needed, 172 .fields = (const VMStateField[]) { 173 VMSTATE_UINT64(vpa_addr, SpaprCpuState), 174 VMSTATE_END_OF_LIST() 175 }, 176 .subsections = (const VMStateDescription * const []) { 177 &vmstate_spapr_cpu_slb_shadow, 178 &vmstate_spapr_cpu_dtl, 179 NULL 180 } 181 }; 182 183 static const VMStateDescription vmstate_spapr_cpu_state = { 184 .name = "spapr_cpu", 185 .version_id = 1, 186 .minimum_version_id = 1, 187 .fields = (const VMStateField[]) { 188 VMSTATE_END_OF_LIST() 189 }, 190 .subsections = (const VMStateDescription * const []) { 191 &vmstate_spapr_cpu_vpa, 192 NULL 193 } 194 }; 195 196 static void spapr_unrealize_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc) 197 { 198 CPUPPCState *env = &cpu->env; 199 200 vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data); 201 spapr_irq_cpu_intc_destroy(SPAPR_MACHINE(qdev_get_machine()), cpu); 202 cpu_ppc_tb_free(env); 203 qdev_unrealize(DEVICE(cpu)); 204 } 205 206 /* 207 * Called when CPUs are hot-plugged. 208 */ 209 static void spapr_cpu_core_reset(DeviceState *dev) 210 { 211 CPUCore *cc = CPU_CORE(dev); 212 SpaprCpuCore *sc = SPAPR_CPU_CORE(dev); 213 int i; 214 215 for (i = 0; i < cc->nr_threads; i++) { 216 spapr_reset_vcpu(sc->threads[i]); 217 } 218 } 219 220 /* 221 * Called by the machine reset. 222 */ 223 static void spapr_cpu_core_reset_handler(void *opaque) 224 { 225 spapr_cpu_core_reset(opaque); 226 } 227 228 static void spapr_delete_vcpu(PowerPCCPU *cpu) 229 { 230 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 231 232 cpu->machine_data = NULL; 233 g_free(spapr_cpu); 234 object_unparent(OBJECT(cpu)); 235 } 236 237 static void spapr_cpu_core_unrealize(DeviceState *dev) 238 { 239 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 240 CPUCore *cc = CPU_CORE(dev); 241 int i; 242 243 for (i = 0; i < cc->nr_threads; i++) { 244 if (sc->threads[i]) { 245 /* 246 * Since this we can get here from the error path of 247 * spapr_cpu_core_realize(), make sure we only unrealize 248 * vCPUs that have already been realized. 249 */ 250 if (qdev_is_realized(DEVICE(sc->threads[i]))) { 251 spapr_unrealize_vcpu(sc->threads[i], sc); 252 } 253 spapr_delete_vcpu(sc->threads[i]); 254 } 255 } 256 g_free(sc->threads); 257 qemu_unregister_reset(spapr_cpu_core_reset_handler, sc); 258 } 259 260 static bool spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr, 261 SpaprCpuCore *sc, int thread_index, Error **errp) 262 { 263 CPUPPCState *env = &cpu->env; 264 CPUState *cs = CPU(cpu); 265 266 if (!qdev_realize(DEVICE(cpu), NULL, errp)) { 267 return false; 268 } 269 270 cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr)); 271 kvmppc_set_papr(cpu); 272 273 env->spr_cb[SPR_PIR].default_value = cs->cpu_index; 274 env->spr_cb[SPR_TIR].default_value = thread_index; 275 276 cpu_ppc_set_1lpar(cpu); 277 278 /* Set time-base frequency to 512 MHz. vhyp must be set first. */ 279 cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); 280 281 if (spapr_irq_cpu_intc_create(spapr, cpu, errp) < 0) { 282 qdev_unrealize(DEVICE(cpu)); 283 return false; 284 } 285 286 vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state, 287 cpu->machine_data); 288 return true; 289 } 290 291 static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp) 292 { 293 SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc); 294 CPUCore *cc = CPU_CORE(sc); 295 g_autoptr(Object) obj = NULL; 296 g_autofree char *id = NULL; 297 CPUState *cs; 298 PowerPCCPU *cpu; 299 CPUPPCState *env; 300 301 obj = object_new(scc->cpu_type); 302 303 cs = CPU(obj); 304 cpu = POWERPC_CPU(obj); 305 env = &cpu->env; 306 /* 307 * All CPUs start halted. CPU0 is unhalted from the machine level reset code 308 * and the rest are explicitly started up by the guest using an RTAS call. 309 */ 310 qdev_prop_set_bit(DEVICE(obj), "start-powered-off", true); 311 cs->cpu_index = cc->core_id + i; 312 if (!spapr_set_vcpu_id(cpu, cs->cpu_index, errp)) { 313 return NULL; 314 } 315 316 env->chip_index = sc->node_id; 317 env->core_index = cc->core_id; 318 319 cpu->node_id = sc->node_id; 320 321 id = g_strdup_printf("thread[%d]", i); 322 object_property_add_child(OBJECT(sc), id, obj); 323 324 cpu->machine_data = g_new0(SpaprCpuState, 1); 325 326 return cpu; 327 } 328 329 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp) 330 { 331 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user 332 * tries to add a sPAPR CPU core to a non-pseries machine. 333 */ 334 SpaprMachineState *spapr = 335 (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(), 336 TYPE_SPAPR_MACHINE); 337 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 338 CPUCore *cc = CPU_CORE(OBJECT(dev)); 339 int i; 340 341 if (!spapr) { 342 error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine"); 343 return; 344 } 345 346 qemu_register_reset(spapr_cpu_core_reset_handler, sc); 347 sc->threads = g_new0(PowerPCCPU *, cc->nr_threads); 348 for (i = 0; i < cc->nr_threads; i++) { 349 PowerPCCPU *cpu; 350 351 cpu = spapr_create_vcpu(sc, i, errp); 352 sc->threads[i] = cpu; 353 if (cpu && cc->nr_threads > 1) { 354 cpu->env.has_smt_siblings = true; 355 } 356 357 if (!cpu || !spapr_realize_vcpu(cpu, spapr, sc, i, errp)) { 358 spapr_cpu_core_unrealize(dev); 359 return; 360 } 361 } 362 } 363 364 static Property spapr_cpu_core_properties[] = { 365 DEFINE_PROP_INT32("node-id", SpaprCpuCore, node_id, CPU_UNSET_NUMA_NODE_ID), 366 DEFINE_PROP_END_OF_LIST() 367 }; 368 369 static void spapr_cpu_core_class_init(ObjectClass *oc, void *data) 370 { 371 DeviceClass *dc = DEVICE_CLASS(oc); 372 SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc); 373 374 dc->realize = spapr_cpu_core_realize; 375 dc->unrealize = spapr_cpu_core_unrealize; 376 device_class_set_legacy_reset(dc, spapr_cpu_core_reset); 377 device_class_set_props(dc, spapr_cpu_core_properties); 378 scc->cpu_type = data; 379 } 380 381 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \ 382 { \ 383 .parent = TYPE_SPAPR_CPU_CORE, \ 384 .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \ 385 .class_init = spapr_cpu_core_class_init, \ 386 .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \ 387 } 388 389 static const TypeInfo spapr_cpu_core_type_infos[] = { 390 { 391 .name = TYPE_SPAPR_CPU_CORE, 392 .parent = TYPE_CPU_CORE, 393 .abstract = true, 394 .instance_size = sizeof(SpaprCpuCore), 395 .class_size = sizeof(SpaprCpuCoreClass), 396 }, 397 DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"), 398 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"), 399 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"), 400 DEFINE_SPAPR_CPU_CORE_TYPE("power5p_v2.1"), 401 DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"), 402 DEFINE_SPAPR_CPU_CORE_TYPE("power7p_v2.1"), 403 DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"), 404 DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"), 405 DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"), 406 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), 407 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"), 408 DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"), 409 DEFINE_SPAPR_CPU_CORE_TYPE("power11_v2.0"), 410 #ifdef CONFIG_KVM 411 DEFINE_SPAPR_CPU_CORE_TYPE("host"), 412 #endif 413 }; 414 415 DEFINE_TYPES(spapr_cpu_core_type_infos) 416