1 /* 2 * sPAPR CPU core device, acts as container of CPU thread devices. 3 * 4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/cpu/core.h" 12 #include "hw/ppc/spapr_cpu_core.h" 13 #include "hw/qdev-properties.h" 14 #include "migration/vmstate.h" 15 #include "target/ppc/cpu.h" 16 #include "hw/ppc/spapr.h" 17 #include "qapi/error.h" 18 #include "sysemu/cpus.h" 19 #include "sysemu/kvm.h" 20 #include "target/ppc/kvm_ppc.h" 21 #include "hw/ppc/ppc.h" 22 #include "target/ppc/mmu-hash64.h" 23 #include "sysemu/numa.h" 24 #include "sysemu/reset.h" 25 #include "sysemu/hw_accel.h" 26 #include "qemu/error-report.h" 27 28 static void spapr_reset_vcpu(PowerPCCPU *cpu) 29 { 30 CPUState *cs = CPU(cpu); 31 CPUPPCState *env = &cpu->env; 32 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 33 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 34 target_ulong lpcr; 35 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 36 37 cpu_reset(cs); 38 39 /* All CPUs start halted. CPU0 is unhalted from the machine level 40 * reset code and the rest are explicitly started up by the guest 41 * using an RTAS call */ 42 cs->halted = 1; 43 44 env->spr[SPR_HIOR] = 0; 45 46 lpcr = env->spr[SPR_LPCR]; 47 48 /* Set emulated LPCR to not send interrupts to hypervisor. Note that 49 * under KVM, the actual HW LPCR will be set differently by KVM itself, 50 * the settings below ensure proper operations with TCG in absence of 51 * a real hypervisor. 52 * 53 * Disable Power-saving mode Exit Cause exceptions for the CPU, so 54 * we don't get spurious wakups before an RTAS start-cpu call. 55 * For the same reason, set PSSCR_EC. 56 */ 57 lpcr &= ~(LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm); 58 lpcr |= LPCR_LPES0 | LPCR_LPES1; 59 env->spr[SPR_PSSCR] |= PSSCR_EC; 60 61 ppc_store_lpcr(cpu, lpcr); 62 63 /* Set a full AMOR so guest can use the AMR as it sees fit */ 64 env->spr[SPR_AMOR] = 0xffffffffffffffffull; 65 66 spapr_cpu->vpa_addr = 0; 67 spapr_cpu->slb_shadow_addr = 0; 68 spapr_cpu->slb_shadow_size = 0; 69 spapr_cpu->dtl_addr = 0; 70 spapr_cpu->dtl_size = 0; 71 72 spapr_caps_cpu_apply(spapr, cpu); 73 74 kvm_check_mmu(cpu, &error_fatal); 75 76 spapr_irq_cpu_intc_reset(spapr, cpu); 77 } 78 79 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3) 80 { 81 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 82 CPUPPCState *env = &cpu->env; 83 84 env->nip = nip; 85 env->gpr[3] = r3; 86 kvmppc_set_reg_ppc_online(cpu, 1); 87 CPU(cpu)->halted = 0; 88 /* Enable Power-saving mode Exit Cause exceptions */ 89 ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm); 90 } 91 92 /* 93 * Return the sPAPR CPU core type for @model which essentially is the CPU 94 * model specified with -cpu cmdline option. 95 */ 96 const char *spapr_get_cpu_core_type(const char *cpu_type) 97 { 98 int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 99 char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"), 100 len, cpu_type); 101 ObjectClass *oc = object_class_by_name(core_type); 102 103 g_free(core_type); 104 if (!oc) { 105 return NULL; 106 } 107 108 return object_class_get_name(oc); 109 } 110 111 static bool slb_shadow_needed(void *opaque) 112 { 113 SpaprCpuState *spapr_cpu = opaque; 114 115 return spapr_cpu->slb_shadow_addr != 0; 116 } 117 118 static const VMStateDescription vmstate_spapr_cpu_slb_shadow = { 119 .name = "spapr_cpu/vpa/slb_shadow", 120 .version_id = 1, 121 .minimum_version_id = 1, 122 .needed = slb_shadow_needed, 123 .fields = (VMStateField[]) { 124 VMSTATE_UINT64(slb_shadow_addr, SpaprCpuState), 125 VMSTATE_UINT64(slb_shadow_size, SpaprCpuState), 126 VMSTATE_END_OF_LIST() 127 } 128 }; 129 130 static bool dtl_needed(void *opaque) 131 { 132 SpaprCpuState *spapr_cpu = opaque; 133 134 return spapr_cpu->dtl_addr != 0; 135 } 136 137 static const VMStateDescription vmstate_spapr_cpu_dtl = { 138 .name = "spapr_cpu/vpa/dtl", 139 .version_id = 1, 140 .minimum_version_id = 1, 141 .needed = dtl_needed, 142 .fields = (VMStateField[]) { 143 VMSTATE_UINT64(dtl_addr, SpaprCpuState), 144 VMSTATE_UINT64(dtl_size, SpaprCpuState), 145 VMSTATE_END_OF_LIST() 146 } 147 }; 148 149 static bool vpa_needed(void *opaque) 150 { 151 SpaprCpuState *spapr_cpu = opaque; 152 153 return spapr_cpu->vpa_addr != 0; 154 } 155 156 static const VMStateDescription vmstate_spapr_cpu_vpa = { 157 .name = "spapr_cpu/vpa", 158 .version_id = 1, 159 .minimum_version_id = 1, 160 .needed = vpa_needed, 161 .fields = (VMStateField[]) { 162 VMSTATE_UINT64(vpa_addr, SpaprCpuState), 163 VMSTATE_END_OF_LIST() 164 }, 165 .subsections = (const VMStateDescription * []) { 166 &vmstate_spapr_cpu_slb_shadow, 167 &vmstate_spapr_cpu_dtl, 168 NULL 169 } 170 }; 171 172 static const VMStateDescription vmstate_spapr_cpu_state = { 173 .name = "spapr_cpu", 174 .version_id = 1, 175 .minimum_version_id = 1, 176 .fields = (VMStateField[]) { 177 VMSTATE_END_OF_LIST() 178 }, 179 .subsections = (const VMStateDescription * []) { 180 &vmstate_spapr_cpu_vpa, 181 NULL 182 } 183 }; 184 185 static void spapr_unrealize_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc) 186 { 187 if (!sc->pre_3_0_migration) { 188 vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data); 189 } 190 spapr_irq_cpu_intc_destroy(SPAPR_MACHINE(qdev_get_machine()), cpu); 191 cpu_remove_sync(CPU(cpu)); 192 object_unparent(OBJECT(cpu)); 193 } 194 195 /* 196 * Called when CPUs are hot-plugged. 197 */ 198 static void spapr_cpu_core_reset(DeviceState *dev) 199 { 200 CPUCore *cc = CPU_CORE(dev); 201 SpaprCpuCore *sc = SPAPR_CPU_CORE(dev); 202 int i; 203 204 for (i = 0; i < cc->nr_threads; i++) { 205 spapr_reset_vcpu(sc->threads[i]); 206 } 207 } 208 209 /* 210 * Called by the machine reset. 211 */ 212 static void spapr_cpu_core_reset_handler(void *opaque) 213 { 214 spapr_cpu_core_reset(opaque); 215 } 216 217 static void spapr_cpu_core_unrealize(DeviceState *dev, Error **errp) 218 { 219 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 220 CPUCore *cc = CPU_CORE(dev); 221 int i; 222 223 qemu_unregister_reset(spapr_cpu_core_reset_handler, sc); 224 225 for (i = 0; i < cc->nr_threads; i++) { 226 spapr_unrealize_vcpu(sc->threads[i], sc); 227 } 228 g_free(sc->threads); 229 } 230 231 static void spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr, 232 SpaprCpuCore *sc, Error **errp) 233 { 234 CPUPPCState *env = &cpu->env; 235 CPUState *cs = CPU(cpu); 236 Error *local_err = NULL; 237 238 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 239 if (local_err) { 240 goto error; 241 } 242 243 /* Set time-base frequency to 512 MHz */ 244 cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); 245 246 cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr)); 247 kvmppc_set_papr(cpu); 248 249 if (spapr_irq_cpu_intc_create(spapr, cpu, &local_err) < 0) { 250 goto error_intc_create; 251 } 252 253 if (!sc->pre_3_0_migration) { 254 vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state, 255 cpu->machine_data); 256 } 257 258 return; 259 260 error_intc_create: 261 cpu_remove_sync(CPU(cpu)); 262 error: 263 error_propagate(errp, local_err); 264 } 265 266 static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp) 267 { 268 SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc); 269 CPUCore *cc = CPU_CORE(sc); 270 Object *obj; 271 char *id; 272 CPUState *cs; 273 PowerPCCPU *cpu; 274 Error *local_err = NULL; 275 276 obj = object_new(scc->cpu_type); 277 278 cs = CPU(obj); 279 cpu = POWERPC_CPU(obj); 280 cs->cpu_index = cc->core_id + i; 281 spapr_set_vcpu_id(cpu, cs->cpu_index, &local_err); 282 if (local_err) { 283 goto err; 284 } 285 286 cpu->node_id = sc->node_id; 287 288 id = g_strdup_printf("thread[%d]", i); 289 object_property_add_child(OBJECT(sc), id, obj, &local_err); 290 g_free(id); 291 if (local_err) { 292 goto err; 293 } 294 295 cpu->machine_data = g_new0(SpaprCpuState, 1); 296 297 object_unref(obj); 298 return cpu; 299 300 err: 301 object_unref(obj); 302 error_propagate(errp, local_err); 303 return NULL; 304 } 305 306 static void spapr_delete_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc) 307 { 308 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 309 310 cpu->machine_data = NULL; 311 g_free(spapr_cpu); 312 object_unparent(OBJECT(cpu)); 313 } 314 315 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp) 316 { 317 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user 318 * tries to add a sPAPR CPU core to a non-pseries machine. 319 */ 320 SpaprMachineState *spapr = 321 (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(), 322 TYPE_SPAPR_MACHINE); 323 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 324 CPUCore *cc = CPU_CORE(OBJECT(dev)); 325 Error *local_err = NULL; 326 int i, j; 327 328 if (!spapr) { 329 error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine"); 330 return; 331 } 332 333 sc->threads = g_new(PowerPCCPU *, cc->nr_threads); 334 for (i = 0; i < cc->nr_threads; i++) { 335 sc->threads[i] = spapr_create_vcpu(sc, i, &local_err); 336 if (local_err) { 337 goto err; 338 } 339 } 340 341 for (j = 0; j < cc->nr_threads; j++) { 342 spapr_realize_vcpu(sc->threads[j], spapr, sc, &local_err); 343 if (local_err) { 344 goto err_unrealize; 345 } 346 } 347 348 qemu_register_reset(spapr_cpu_core_reset_handler, sc); 349 return; 350 351 err_unrealize: 352 while (--j >= 0) { 353 spapr_unrealize_vcpu(sc->threads[j], sc); 354 } 355 err: 356 while (--i >= 0) { 357 spapr_delete_vcpu(sc->threads[i], sc); 358 } 359 g_free(sc->threads); 360 error_propagate(errp, local_err); 361 } 362 363 static Property spapr_cpu_core_properties[] = { 364 DEFINE_PROP_INT32("node-id", SpaprCpuCore, node_id, CPU_UNSET_NUMA_NODE_ID), 365 DEFINE_PROP_BOOL("pre-3.0-migration", SpaprCpuCore, pre_3_0_migration, 366 false), 367 DEFINE_PROP_END_OF_LIST() 368 }; 369 370 static void spapr_cpu_core_class_init(ObjectClass *oc, void *data) 371 { 372 DeviceClass *dc = DEVICE_CLASS(oc); 373 SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc); 374 375 dc->realize = spapr_cpu_core_realize; 376 dc->unrealize = spapr_cpu_core_unrealize; 377 dc->reset = spapr_cpu_core_reset; 378 device_class_set_props(dc, spapr_cpu_core_properties); 379 scc->cpu_type = data; 380 } 381 382 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \ 383 { \ 384 .parent = TYPE_SPAPR_CPU_CORE, \ 385 .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \ 386 .class_init = spapr_cpu_core_class_init, \ 387 .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \ 388 } 389 390 static const TypeInfo spapr_cpu_core_type_infos[] = { 391 { 392 .name = TYPE_SPAPR_CPU_CORE, 393 .parent = TYPE_CPU_CORE, 394 .abstract = true, 395 .instance_size = sizeof(SpaprCpuCore), 396 .class_size = sizeof(SpaprCpuCoreClass), 397 }, 398 DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"), 399 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"), 400 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"), 401 DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"), 402 DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"), 403 DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"), 404 DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"), 405 DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"), 406 DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"), 407 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"), 408 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), 409 #ifdef CONFIG_KVM 410 DEFINE_SPAPR_CPU_CORE_TYPE("host"), 411 #endif 412 }; 413 414 DEFINE_TYPES(spapr_cpu_core_type_infos) 415