1 /* 2 * sPAPR CPU core device, acts as container of CPU thread devices. 3 * 4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 #include "qemu/osdep.h" 10 #include "hw/cpu/core.h" 11 #include "hw/ppc/spapr_cpu_core.h" 12 #include "target/ppc/cpu.h" 13 #include "hw/ppc/spapr.h" 14 #include "hw/ppc/xics.h" /* for icp_create() - to be removed */ 15 #include "hw/boards.h" 16 #include "qapi/error.h" 17 #include "sysemu/cpus.h" 18 #include "sysemu/kvm.h" 19 #include "target/ppc/kvm_ppc.h" 20 #include "hw/ppc/ppc.h" 21 #include "target/ppc/mmu-hash64.h" 22 #include "sysemu/numa.h" 23 #include "sysemu/hw_accel.h" 24 #include "qemu/error-report.h" 25 26 static void spapr_cpu_reset(void *opaque) 27 { 28 PowerPCCPU *cpu = opaque; 29 CPUState *cs = CPU(cpu); 30 CPUPPCState *env = &cpu->env; 31 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 32 sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu); 33 target_ulong lpcr; 34 35 cpu_reset(cs); 36 37 /* Set compatibility mode to match the boot CPU, which was either set 38 * by the machine reset code or by CAS. This should never fail. 39 */ 40 ppc_set_compat(cpu, POWERPC_CPU(first_cpu)->compat_pvr, &error_abort); 41 42 /* All CPUs start halted. CPU0 is unhalted from the machine level 43 * reset code and the rest are explicitly started up by the guest 44 * using an RTAS call */ 45 cs->halted = 1; 46 47 env->spr[SPR_HIOR] = 0; 48 49 lpcr = env->spr[SPR_LPCR]; 50 51 /* Set emulated LPCR to not send interrupts to hypervisor. Note that 52 * under KVM, the actual HW LPCR will be set differently by KVM itself, 53 * the settings below ensure proper operations with TCG in absence of 54 * a real hypervisor. 55 * 56 * Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for 57 * real mode accesses, which thankfully defaults to 0 and isn't 58 * accessible in guest mode. 59 * 60 * Disable Power-saving mode Exit Cause exceptions for the CPU, so 61 * we don't get spurious wakups before an RTAS start-cpu call. 62 */ 63 lpcr &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm); 64 lpcr |= LPCR_LPES0 | LPCR_LPES1; 65 66 /* Set RMLS to the max (ie, 16G) */ 67 lpcr &= ~LPCR_RMLS; 68 lpcr |= 1ull << LPCR_RMLS_SHIFT; 69 70 ppc_store_lpcr(cpu, lpcr); 71 72 /* Set a full AMOR so guest can use the AMR as it sees fit */ 73 env->spr[SPR_AMOR] = 0xffffffffffffffffull; 74 75 spapr_cpu->vpa_addr = 0; 76 spapr_cpu->slb_shadow_addr = 0; 77 spapr_cpu->slb_shadow_size = 0; 78 spapr_cpu->dtl_addr = 0; 79 spapr_cpu->dtl_size = 0; 80 81 spapr_caps_cpu_apply(SPAPR_MACHINE(qdev_get_machine()), cpu); 82 83 kvm_check_mmu(cpu, &error_fatal); 84 } 85 86 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3) 87 { 88 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 89 CPUPPCState *env = &cpu->env; 90 91 env->nip = nip; 92 env->gpr[3] = r3; 93 CPU(cpu)->halted = 0; 94 /* Enable Power-saving mode Exit Cause exceptions */ 95 ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm); 96 } 97 98 /* 99 * Return the sPAPR CPU core type for @model which essentially is the CPU 100 * model specified with -cpu cmdline option. 101 */ 102 const char *spapr_get_cpu_core_type(const char *cpu_type) 103 { 104 int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 105 char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"), 106 len, cpu_type); 107 ObjectClass *oc = object_class_by_name(core_type); 108 109 g_free(core_type); 110 if (!oc) { 111 return NULL; 112 } 113 114 return object_class_get_name(oc); 115 } 116 117 static bool slb_shadow_needed(void *opaque) 118 { 119 sPAPRCPUState *spapr_cpu = opaque; 120 121 return spapr_cpu->slb_shadow_addr != 0; 122 } 123 124 static const VMStateDescription vmstate_spapr_cpu_slb_shadow = { 125 .name = "spapr_cpu/vpa/slb_shadow", 126 .version_id = 1, 127 .minimum_version_id = 1, 128 .needed = slb_shadow_needed, 129 .fields = (VMStateField[]) { 130 VMSTATE_UINT64(slb_shadow_addr, sPAPRCPUState), 131 VMSTATE_UINT64(slb_shadow_size, sPAPRCPUState), 132 VMSTATE_END_OF_LIST() 133 } 134 }; 135 136 static bool dtl_needed(void *opaque) 137 { 138 sPAPRCPUState *spapr_cpu = opaque; 139 140 return spapr_cpu->dtl_addr != 0; 141 } 142 143 static const VMStateDescription vmstate_spapr_cpu_dtl = { 144 .name = "spapr_cpu/vpa/dtl", 145 .version_id = 1, 146 .minimum_version_id = 1, 147 .needed = dtl_needed, 148 .fields = (VMStateField[]) { 149 VMSTATE_UINT64(dtl_addr, sPAPRCPUState), 150 VMSTATE_UINT64(dtl_size, sPAPRCPUState), 151 VMSTATE_END_OF_LIST() 152 } 153 }; 154 155 static bool vpa_needed(void *opaque) 156 { 157 sPAPRCPUState *spapr_cpu = opaque; 158 159 return spapr_cpu->vpa_addr != 0; 160 } 161 162 static const VMStateDescription vmstate_spapr_cpu_vpa = { 163 .name = "spapr_cpu/vpa", 164 .version_id = 1, 165 .minimum_version_id = 1, 166 .needed = vpa_needed, 167 .fields = (VMStateField[]) { 168 VMSTATE_UINT64(vpa_addr, sPAPRCPUState), 169 VMSTATE_END_OF_LIST() 170 }, 171 .subsections = (const VMStateDescription * []) { 172 &vmstate_spapr_cpu_slb_shadow, 173 &vmstate_spapr_cpu_dtl, 174 NULL 175 } 176 }; 177 178 static const VMStateDescription vmstate_spapr_cpu_state = { 179 .name = "spapr_cpu", 180 .version_id = 1, 181 .minimum_version_id = 1, 182 .fields = (VMStateField[]) { 183 VMSTATE_END_OF_LIST() 184 }, 185 .subsections = (const VMStateDescription * []) { 186 &vmstate_spapr_cpu_vpa, 187 NULL 188 } 189 }; 190 191 static void spapr_unrealize_vcpu(PowerPCCPU *cpu, sPAPRCPUCore *sc) 192 { 193 if (!sc->pre_3_0_migration) { 194 vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data); 195 } 196 qemu_unregister_reset(spapr_cpu_reset, cpu); 197 object_unparent(cpu->intc); 198 cpu_remove_sync(CPU(cpu)); 199 object_unparent(OBJECT(cpu)); 200 } 201 202 static void spapr_cpu_core_unrealize(DeviceState *dev, Error **errp) 203 { 204 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 205 CPUCore *cc = CPU_CORE(dev); 206 int i; 207 208 for (i = 0; i < cc->nr_threads; i++) { 209 spapr_unrealize_vcpu(sc->threads[i], sc); 210 } 211 g_free(sc->threads); 212 } 213 214 static void spapr_realize_vcpu(PowerPCCPU *cpu, sPAPRMachineState *spapr, 215 sPAPRCPUCore *sc, Error **errp) 216 { 217 CPUPPCState *env = &cpu->env; 218 CPUState *cs = CPU(cpu); 219 Error *local_err = NULL; 220 221 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 222 if (local_err) { 223 goto error; 224 } 225 226 /* Set time-base frequency to 512 MHz */ 227 cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); 228 229 cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr)); 230 kvmppc_set_papr(cpu); 231 232 qemu_register_reset(spapr_cpu_reset, cpu); 233 spapr_cpu_reset(cpu); 234 235 cpu->intc = icp_create(OBJECT(cpu), spapr->icp_type, XICS_FABRIC(spapr), 236 &local_err); 237 if (local_err) { 238 goto error_unregister; 239 } 240 241 if (!sc->pre_3_0_migration) { 242 vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state, 243 cpu->machine_data); 244 } 245 246 return; 247 248 error_unregister: 249 qemu_unregister_reset(spapr_cpu_reset, cpu); 250 cpu_remove_sync(CPU(cpu)); 251 error: 252 error_propagate(errp, local_err); 253 } 254 255 static PowerPCCPU *spapr_create_vcpu(sPAPRCPUCore *sc, int i, Error **errp) 256 { 257 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc); 258 CPUCore *cc = CPU_CORE(sc); 259 Object *obj; 260 char *id; 261 CPUState *cs; 262 PowerPCCPU *cpu; 263 Error *local_err = NULL; 264 265 obj = object_new(scc->cpu_type); 266 267 cs = CPU(obj); 268 cpu = POWERPC_CPU(obj); 269 cs->cpu_index = cc->core_id + i; 270 spapr_set_vcpu_id(cpu, cs->cpu_index, &local_err); 271 if (local_err) { 272 goto err; 273 } 274 275 cpu->node_id = sc->node_id; 276 277 id = g_strdup_printf("thread[%d]", i); 278 object_property_add_child(OBJECT(sc), id, obj, &local_err); 279 g_free(id); 280 if (local_err) { 281 goto err; 282 } 283 284 cpu->machine_data = g_new0(sPAPRCPUState, 1); 285 286 object_unref(obj); 287 return cpu; 288 289 err: 290 object_unref(obj); 291 error_propagate(errp, local_err); 292 return NULL; 293 } 294 295 static void spapr_delete_vcpu(PowerPCCPU *cpu, sPAPRCPUCore *sc) 296 { 297 sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu); 298 299 cpu->machine_data = NULL; 300 g_free(spapr_cpu); 301 object_unparent(OBJECT(cpu)); 302 } 303 304 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp) 305 { 306 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user 307 * tries to add a sPAPR CPU core to a non-pseries machine. 308 */ 309 sPAPRMachineState *spapr = 310 (sPAPRMachineState *) object_dynamic_cast(qdev_get_machine(), 311 TYPE_SPAPR_MACHINE); 312 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 313 CPUCore *cc = CPU_CORE(OBJECT(dev)); 314 Error *local_err = NULL; 315 int i, j; 316 317 if (!spapr) { 318 error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine"); 319 return; 320 } 321 322 sc->threads = g_new(PowerPCCPU *, cc->nr_threads); 323 for (i = 0; i < cc->nr_threads; i++) { 324 sc->threads[i] = spapr_create_vcpu(sc, i, &local_err); 325 if (local_err) { 326 goto err; 327 } 328 } 329 330 for (j = 0; j < cc->nr_threads; j++) { 331 spapr_realize_vcpu(sc->threads[j], spapr, sc, &local_err); 332 if (local_err) { 333 goto err_unrealize; 334 } 335 } 336 return; 337 338 err_unrealize: 339 while (--j >= 0) { 340 spapr_unrealize_vcpu(sc->threads[j], sc); 341 } 342 err: 343 while (--i >= 0) { 344 spapr_delete_vcpu(sc->threads[i], sc); 345 } 346 g_free(sc->threads); 347 error_propagate(errp, local_err); 348 } 349 350 static Property spapr_cpu_core_properties[] = { 351 DEFINE_PROP_INT32("node-id", sPAPRCPUCore, node_id, CPU_UNSET_NUMA_NODE_ID), 352 DEFINE_PROP_BOOL("pre-3.0-migration", sPAPRCPUCore, pre_3_0_migration, 353 false), 354 DEFINE_PROP_END_OF_LIST() 355 }; 356 357 static void spapr_cpu_core_class_init(ObjectClass *oc, void *data) 358 { 359 DeviceClass *dc = DEVICE_CLASS(oc); 360 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc); 361 362 dc->realize = spapr_cpu_core_realize; 363 dc->unrealize = spapr_cpu_core_unrealize; 364 dc->props = spapr_cpu_core_properties; 365 scc->cpu_type = data; 366 } 367 368 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \ 369 { \ 370 .parent = TYPE_SPAPR_CPU_CORE, \ 371 .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \ 372 .class_init = spapr_cpu_core_class_init, \ 373 .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \ 374 } 375 376 static const TypeInfo spapr_cpu_core_type_infos[] = { 377 { 378 .name = TYPE_SPAPR_CPU_CORE, 379 .parent = TYPE_CPU_CORE, 380 .abstract = true, 381 .instance_size = sizeof(sPAPRCPUCore), 382 .class_size = sizeof(sPAPRCPUCoreClass), 383 }, 384 DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"), 385 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"), 386 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"), 387 DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"), 388 DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"), 389 DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"), 390 DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"), 391 DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"), 392 DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"), 393 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"), 394 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), 395 #ifdef CONFIG_KVM 396 DEFINE_SPAPR_CPU_CORE_TYPE("host"), 397 #endif 398 }; 399 400 DEFINE_TYPES(spapr_cpu_core_type_infos) 401