1 /* 2 * sPAPR CPU core device, acts as container of CPU thread devices. 3 * 4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 #include "qemu/osdep.h" 10 #include "hw/cpu/core.h" 11 #include "hw/ppc/spapr_cpu_core.h" 12 #include "target/ppc/cpu.h" 13 #include "hw/ppc/spapr.h" 14 #include "hw/boards.h" 15 #include "qapi/error.h" 16 #include "sysemu/cpus.h" 17 #include "sysemu/kvm.h" 18 #include "target/ppc/kvm_ppc.h" 19 #include "hw/ppc/ppc.h" 20 #include "target/ppc/mmu-hash64.h" 21 #include "sysemu/numa.h" 22 #include "sysemu/hw_accel.h" 23 #include "qemu/error-report.h" 24 25 static void spapr_cpu_reset(void *opaque) 26 { 27 PowerPCCPU *cpu = opaque; 28 CPUState *cs = CPU(cpu); 29 CPUPPCState *env = &cpu->env; 30 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 31 sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu); 32 target_ulong lpcr; 33 34 cpu_reset(cs); 35 36 /* Set compatibility mode to match the boot CPU, which was either set 37 * by the machine reset code or by CAS. This should never fail. 38 */ 39 ppc_set_compat(cpu, POWERPC_CPU(first_cpu)->compat_pvr, &error_abort); 40 41 /* All CPUs start halted. CPU0 is unhalted from the machine level 42 * reset code and the rest are explicitly started up by the guest 43 * using an RTAS call */ 44 cs->halted = 1; 45 46 env->spr[SPR_HIOR] = 0; 47 48 lpcr = env->spr[SPR_LPCR]; 49 50 /* Set emulated LPCR to not send interrupts to hypervisor. Note that 51 * under KVM, the actual HW LPCR will be set differently by KVM itself, 52 * the settings below ensure proper operations with TCG in absence of 53 * a real hypervisor. 54 * 55 * Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for 56 * real mode accesses, which thankfully defaults to 0 and isn't 57 * accessible in guest mode. 58 * 59 * Disable Power-saving mode Exit Cause exceptions for the CPU, so 60 * we don't get spurious wakups before an RTAS start-cpu call. 61 */ 62 lpcr &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm); 63 lpcr |= LPCR_LPES0 | LPCR_LPES1; 64 65 /* Set RMLS to the max (ie, 16G) */ 66 lpcr &= ~LPCR_RMLS; 67 lpcr |= 1ull << LPCR_RMLS_SHIFT; 68 69 ppc_store_lpcr(cpu, lpcr); 70 71 /* Set a full AMOR so guest can use the AMR as it sees fit */ 72 env->spr[SPR_AMOR] = 0xffffffffffffffffull; 73 74 spapr_cpu->vpa_addr = 0; 75 spapr_cpu->slb_shadow_addr = 0; 76 spapr_cpu->slb_shadow_size = 0; 77 spapr_cpu->dtl_addr = 0; 78 spapr_cpu->dtl_size = 0; 79 80 spapr_caps_cpu_apply(SPAPR_MACHINE(qdev_get_machine()), cpu); 81 82 kvm_check_mmu(cpu, &error_fatal); 83 } 84 85 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3) 86 { 87 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 88 CPUPPCState *env = &cpu->env; 89 90 env->nip = nip; 91 env->gpr[3] = r3; 92 CPU(cpu)->halted = 0; 93 /* Enable Power-saving mode Exit Cause exceptions */ 94 ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm); 95 } 96 97 /* 98 * Return the sPAPR CPU core type for @model which essentially is the CPU 99 * model specified with -cpu cmdline option. 100 */ 101 const char *spapr_get_cpu_core_type(const char *cpu_type) 102 { 103 int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 104 char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"), 105 len, cpu_type); 106 ObjectClass *oc = object_class_by_name(core_type); 107 108 g_free(core_type); 109 if (!oc) { 110 return NULL; 111 } 112 113 return object_class_get_name(oc); 114 } 115 116 static void spapr_unrealize_vcpu(PowerPCCPU *cpu) 117 { 118 qemu_unregister_reset(spapr_cpu_reset, cpu); 119 object_unparent(cpu->intc); 120 cpu_remove_sync(CPU(cpu)); 121 object_unparent(OBJECT(cpu)); 122 } 123 124 static void spapr_cpu_core_unrealize(DeviceState *dev, Error **errp) 125 { 126 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 127 CPUCore *cc = CPU_CORE(dev); 128 int i; 129 130 for (i = 0; i < cc->nr_threads; i++) { 131 spapr_unrealize_vcpu(sc->threads[i]); 132 } 133 g_free(sc->threads); 134 } 135 136 static bool slb_shadow_needed(void *opaque) 137 { 138 sPAPRCPUState *spapr_cpu = opaque; 139 140 return spapr_cpu->slb_shadow_addr != 0; 141 } 142 143 static const VMStateDescription vmstate_spapr_cpu_slb_shadow = { 144 .name = "spapr_cpu/vpa/slb_shadow", 145 .version_id = 1, 146 .minimum_version_id = 1, 147 .needed = slb_shadow_needed, 148 .fields = (VMStateField[]) { 149 VMSTATE_UINT64(slb_shadow_addr, sPAPRCPUState), 150 VMSTATE_UINT64(slb_shadow_size, sPAPRCPUState), 151 VMSTATE_END_OF_LIST() 152 } 153 }; 154 155 static bool dtl_needed(void *opaque) 156 { 157 sPAPRCPUState *spapr_cpu = opaque; 158 159 return spapr_cpu->dtl_addr != 0; 160 } 161 162 static const VMStateDescription vmstate_spapr_cpu_dtl = { 163 .name = "spapr_cpu/vpa/dtl", 164 .version_id = 1, 165 .minimum_version_id = 1, 166 .needed = dtl_needed, 167 .fields = (VMStateField[]) { 168 VMSTATE_UINT64(dtl_addr, sPAPRCPUState), 169 VMSTATE_UINT64(dtl_size, sPAPRCPUState), 170 VMSTATE_END_OF_LIST() 171 } 172 }; 173 174 static bool vpa_needed(void *opaque) 175 { 176 sPAPRCPUState *spapr_cpu = opaque; 177 178 return spapr_cpu->vpa_addr != 0; 179 } 180 181 static const VMStateDescription vmstate_spapr_cpu_vpa = { 182 .name = "spapr_cpu/vpa", 183 .version_id = 1, 184 .minimum_version_id = 1, 185 .needed = vpa_needed, 186 .fields = (VMStateField[]) { 187 VMSTATE_UINT64(vpa_addr, sPAPRCPUState), 188 VMSTATE_END_OF_LIST() 189 }, 190 .subsections = (const VMStateDescription * []) { 191 &vmstate_spapr_cpu_slb_shadow, 192 &vmstate_spapr_cpu_dtl, 193 NULL 194 } 195 }; 196 197 static const VMStateDescription vmstate_spapr_cpu_state = { 198 .name = "spapr_cpu", 199 .version_id = 1, 200 .minimum_version_id = 1, 201 .fields = (VMStateField[]) { 202 VMSTATE_END_OF_LIST() 203 }, 204 .subsections = (const VMStateDescription * []) { 205 &vmstate_spapr_cpu_vpa, 206 NULL 207 } 208 }; 209 210 static void spapr_realize_vcpu(PowerPCCPU *cpu, sPAPRMachineState *spapr, 211 Error **errp) 212 { 213 CPUPPCState *env = &cpu->env; 214 Error *local_err = NULL; 215 216 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 217 if (local_err) { 218 goto error; 219 } 220 221 /* Set time-base frequency to 512 MHz */ 222 cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); 223 224 cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr)); 225 kvmppc_set_papr(cpu); 226 227 qemu_register_reset(spapr_cpu_reset, cpu); 228 spapr_cpu_reset(cpu); 229 230 cpu->intc = icp_create(OBJECT(cpu), spapr->icp_type, XICS_FABRIC(spapr), 231 &local_err); 232 if (local_err) { 233 goto error_unregister; 234 } 235 236 return; 237 238 error_unregister: 239 qemu_unregister_reset(spapr_cpu_reset, cpu); 240 cpu_remove_sync(CPU(cpu)); 241 error: 242 error_propagate(errp, local_err); 243 } 244 245 static PowerPCCPU *spapr_create_vcpu(sPAPRCPUCore *sc, int i, Error **errp) 246 { 247 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc); 248 CPUCore *cc = CPU_CORE(sc); 249 Object *obj; 250 char *id; 251 CPUState *cs; 252 PowerPCCPU *cpu; 253 Error *local_err = NULL; 254 255 obj = object_new(scc->cpu_type); 256 257 cs = CPU(obj); 258 cpu = POWERPC_CPU(obj); 259 cs->cpu_index = cc->core_id + i; 260 spapr_set_vcpu_id(cpu, cs->cpu_index, &local_err); 261 if (local_err) { 262 goto err; 263 } 264 265 cpu->node_id = sc->node_id; 266 267 id = g_strdup_printf("thread[%d]", i); 268 object_property_add_child(OBJECT(sc), id, obj, &local_err); 269 g_free(id); 270 if (local_err) { 271 goto err; 272 } 273 274 cpu->machine_data = g_new0(sPAPRCPUState, 1); 275 if (!sc->pre_3_0_migration) { 276 vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state, 277 cpu->machine_data); 278 } 279 280 object_unref(obj); 281 return cpu; 282 283 err: 284 object_unref(obj); 285 error_propagate(errp, local_err); 286 return NULL; 287 } 288 289 static void spapr_delete_vcpu(PowerPCCPU *cpu, sPAPRCPUCore *sc) 290 { 291 sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu); 292 293 if (!sc->pre_3_0_migration) { 294 vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data); 295 } 296 cpu->machine_data = NULL; 297 g_free(spapr_cpu); 298 object_unparent(OBJECT(cpu)); 299 } 300 301 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp) 302 { 303 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user 304 * tries to add a sPAPR CPU core to a non-pseries machine. 305 */ 306 sPAPRMachineState *spapr = 307 (sPAPRMachineState *) object_dynamic_cast(qdev_get_machine(), 308 TYPE_SPAPR_MACHINE); 309 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 310 CPUCore *cc = CPU_CORE(OBJECT(dev)); 311 Error *local_err = NULL; 312 int i, j; 313 314 if (!spapr) { 315 error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine"); 316 return; 317 } 318 319 sc->threads = g_new(PowerPCCPU *, cc->nr_threads); 320 for (i = 0; i < cc->nr_threads; i++) { 321 sc->threads[i] = spapr_create_vcpu(sc, i, &local_err); 322 if (local_err) { 323 goto err; 324 } 325 } 326 327 for (j = 0; j < cc->nr_threads; j++) { 328 spapr_realize_vcpu(sc->threads[j], spapr, &local_err); 329 if (local_err) { 330 goto err_unrealize; 331 } 332 } 333 return; 334 335 err_unrealize: 336 while (--j >= 0) { 337 spapr_unrealize_vcpu(sc->threads[j]); 338 } 339 err: 340 while (--i >= 0) { 341 spapr_delete_vcpu(sc->threads[i], sc); 342 } 343 g_free(sc->threads); 344 error_propagate(errp, local_err); 345 } 346 347 static Property spapr_cpu_core_properties[] = { 348 DEFINE_PROP_INT32("node-id", sPAPRCPUCore, node_id, CPU_UNSET_NUMA_NODE_ID), 349 DEFINE_PROP_BOOL("pre-3.0-migration", sPAPRCPUCore, pre_3_0_migration, 350 false), 351 DEFINE_PROP_END_OF_LIST() 352 }; 353 354 static void spapr_cpu_core_class_init(ObjectClass *oc, void *data) 355 { 356 DeviceClass *dc = DEVICE_CLASS(oc); 357 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc); 358 359 dc->realize = spapr_cpu_core_realize; 360 dc->unrealize = spapr_cpu_core_unrealize; 361 dc->props = spapr_cpu_core_properties; 362 scc->cpu_type = data; 363 } 364 365 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \ 366 { \ 367 .parent = TYPE_SPAPR_CPU_CORE, \ 368 .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \ 369 .class_init = spapr_cpu_core_class_init, \ 370 .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \ 371 } 372 373 static const TypeInfo spapr_cpu_core_type_infos[] = { 374 { 375 .name = TYPE_SPAPR_CPU_CORE, 376 .parent = TYPE_CPU_CORE, 377 .abstract = true, 378 .instance_size = sizeof(sPAPRCPUCore), 379 .class_size = sizeof(sPAPRCPUCoreClass), 380 }, 381 DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"), 382 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"), 383 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"), 384 DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"), 385 DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"), 386 DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"), 387 DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"), 388 DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"), 389 DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"), 390 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"), 391 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), 392 #ifdef CONFIG_KVM 393 DEFINE_SPAPR_CPU_CORE_TYPE("host"), 394 #endif 395 }; 396 397 DEFINE_TYPES(spapr_cpu_core_type_infos) 398