1 /* 2 * sPAPR CPU core device, acts as container of CPU thread devices. 3 * 4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 #include "qemu/osdep.h" 10 #include "hw/cpu/core.h" 11 #include "hw/ppc/spapr_cpu_core.h" 12 #include "target/ppc/cpu.h" 13 #include "hw/ppc/spapr.h" 14 #include "hw/boards.h" 15 #include "qapi/error.h" 16 #include "sysemu/cpus.h" 17 #include "sysemu/kvm.h" 18 #include "target/ppc/kvm_ppc.h" 19 #include "hw/ppc/ppc.h" 20 #include "target/ppc/mmu-hash64.h" 21 #include "sysemu/numa.h" 22 #include "sysemu/hw_accel.h" 23 #include "qemu/error-report.h" 24 25 static void spapr_cpu_reset(void *opaque) 26 { 27 PowerPCCPU *cpu = opaque; 28 CPUState *cs = CPU(cpu); 29 CPUPPCState *env = &cpu->env; 30 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 31 sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu); 32 target_ulong lpcr; 33 34 cpu_reset(cs); 35 36 /* Set compatibility mode to match the boot CPU, which was either set 37 * by the machine reset code or by CAS. This should never fail. 38 */ 39 ppc_set_compat(cpu, POWERPC_CPU(first_cpu)->compat_pvr, &error_abort); 40 41 /* All CPUs start halted. CPU0 is unhalted from the machine level 42 * reset code and the rest are explicitly started up by the guest 43 * using an RTAS call */ 44 cs->halted = 1; 45 46 env->spr[SPR_HIOR] = 0; 47 48 lpcr = env->spr[SPR_LPCR]; 49 50 /* Set emulated LPCR to not send interrupts to hypervisor. Note that 51 * under KVM, the actual HW LPCR will be set differently by KVM itself, 52 * the settings below ensure proper operations with TCG in absence of 53 * a real hypervisor. 54 * 55 * Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for 56 * real mode accesses, which thankfully defaults to 0 and isn't 57 * accessible in guest mode. 58 * 59 * Disable Power-saving mode Exit Cause exceptions for the CPU, so 60 * we don't get spurious wakups before an RTAS start-cpu call. 61 */ 62 lpcr &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm); 63 lpcr |= LPCR_LPES0 | LPCR_LPES1; 64 65 /* Set RMLS to the max (ie, 16G) */ 66 lpcr &= ~LPCR_RMLS; 67 lpcr |= 1ull << LPCR_RMLS_SHIFT; 68 69 ppc_store_lpcr(cpu, lpcr); 70 71 /* Set a full AMOR so guest can use the AMR as it sees fit */ 72 env->spr[SPR_AMOR] = 0xffffffffffffffffull; 73 74 spapr_cpu->vpa_addr = 0; 75 spapr_cpu->slb_shadow_addr = 0; 76 spapr_cpu->slb_shadow_size = 0; 77 spapr_cpu->dtl_addr = 0; 78 spapr_cpu->dtl_size = 0; 79 } 80 81 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3) 82 { 83 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 84 CPUPPCState *env = &cpu->env; 85 86 env->nip = nip; 87 env->gpr[3] = r3; 88 CPU(cpu)->halted = 0; 89 /* Enable Power-saving mode Exit Cause exceptions */ 90 ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm); 91 } 92 93 /* 94 * Return the sPAPR CPU core type for @model which essentially is the CPU 95 * model specified with -cpu cmdline option. 96 */ 97 const char *spapr_get_cpu_core_type(const char *cpu_type) 98 { 99 int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 100 char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"), 101 len, cpu_type); 102 ObjectClass *oc = object_class_by_name(core_type); 103 104 g_free(core_type); 105 if (!oc) { 106 return NULL; 107 } 108 109 return object_class_get_name(oc); 110 } 111 112 static void spapr_unrealize_vcpu(PowerPCCPU *cpu) 113 { 114 qemu_unregister_reset(spapr_cpu_reset, cpu); 115 object_unparent(cpu->intc); 116 cpu_remove_sync(CPU(cpu)); 117 object_unparent(OBJECT(cpu)); 118 } 119 120 static void spapr_cpu_core_unrealize(DeviceState *dev, Error **errp) 121 { 122 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 123 CPUCore *cc = CPU_CORE(dev); 124 int i; 125 126 for (i = 0; i < cc->nr_threads; i++) { 127 spapr_unrealize_vcpu(sc->threads[i]); 128 } 129 g_free(sc->threads); 130 } 131 132 static void spapr_realize_vcpu(PowerPCCPU *cpu, sPAPRMachineState *spapr, 133 Error **errp) 134 { 135 CPUPPCState *env = &cpu->env; 136 Error *local_err = NULL; 137 138 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 139 if (local_err) { 140 goto error; 141 } 142 143 /* Set time-base frequency to 512 MHz */ 144 cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); 145 146 cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr)); 147 kvmppc_set_papr(cpu); 148 149 qemu_register_reset(spapr_cpu_reset, cpu); 150 spapr_cpu_reset(cpu); 151 152 cpu->intc = icp_create(OBJECT(cpu), spapr->icp_type, XICS_FABRIC(spapr), 153 &local_err); 154 if (local_err) { 155 goto error_unregister; 156 } 157 158 return; 159 160 error_unregister: 161 qemu_unregister_reset(spapr_cpu_reset, cpu); 162 cpu_remove_sync(CPU(cpu)); 163 error: 164 error_propagate(errp, local_err); 165 } 166 167 static PowerPCCPU *spapr_create_vcpu(sPAPRCPUCore *sc, int i, Error **errp) 168 { 169 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc); 170 CPUCore *cc = CPU_CORE(sc); 171 Object *obj; 172 char *id; 173 CPUState *cs; 174 PowerPCCPU *cpu; 175 Error *local_err = NULL; 176 177 obj = object_new(scc->cpu_type); 178 179 cs = CPU(obj); 180 cpu = POWERPC_CPU(obj); 181 cs->cpu_index = cc->core_id + i; 182 spapr_set_vcpu_id(cpu, cs->cpu_index, &local_err); 183 if (local_err) { 184 goto err; 185 } 186 187 cpu->node_id = sc->node_id; 188 189 id = g_strdup_printf("thread[%d]", i); 190 object_property_add_child(OBJECT(sc), id, obj, &local_err); 191 g_free(id); 192 if (local_err) { 193 goto err; 194 } 195 196 cpu->machine_data = g_new0(sPAPRCPUState, 1); 197 198 object_unref(obj); 199 return cpu; 200 201 err: 202 object_unref(obj); 203 error_propagate(errp, local_err); 204 return NULL; 205 } 206 207 static void spapr_delete_vcpu(PowerPCCPU *cpu) 208 { 209 sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu); 210 211 cpu->machine_data = NULL; 212 g_free(spapr_cpu); 213 object_unparent(OBJECT(cpu)); 214 } 215 216 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp) 217 { 218 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user 219 * tries to add a sPAPR CPU core to a non-pseries machine. 220 */ 221 sPAPRMachineState *spapr = 222 (sPAPRMachineState *) object_dynamic_cast(qdev_get_machine(), 223 TYPE_SPAPR_MACHINE); 224 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 225 CPUCore *cc = CPU_CORE(OBJECT(dev)); 226 Error *local_err = NULL; 227 int i, j; 228 229 if (!spapr) { 230 error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine"); 231 return; 232 } 233 234 sc->threads = g_new(PowerPCCPU *, cc->nr_threads); 235 for (i = 0; i < cc->nr_threads; i++) { 236 sc->threads[i] = spapr_create_vcpu(sc, i, &local_err); 237 if (local_err) { 238 goto err; 239 } 240 } 241 242 for (j = 0; j < cc->nr_threads; j++) { 243 spapr_realize_vcpu(sc->threads[j], spapr, &local_err); 244 if (local_err) { 245 goto err_unrealize; 246 } 247 } 248 return; 249 250 err_unrealize: 251 while (--j >= 0) { 252 spapr_unrealize_vcpu(sc->threads[j]); 253 } 254 err: 255 while (--i >= 0) { 256 spapr_delete_vcpu(sc->threads[i]); 257 } 258 g_free(sc->threads); 259 error_propagate(errp, local_err); 260 } 261 262 static Property spapr_cpu_core_properties[] = { 263 DEFINE_PROP_INT32("node-id", sPAPRCPUCore, node_id, CPU_UNSET_NUMA_NODE_ID), 264 DEFINE_PROP_END_OF_LIST() 265 }; 266 267 static void spapr_cpu_core_class_init(ObjectClass *oc, void *data) 268 { 269 DeviceClass *dc = DEVICE_CLASS(oc); 270 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc); 271 272 dc->realize = spapr_cpu_core_realize; 273 dc->unrealize = spapr_cpu_core_unrealize; 274 dc->props = spapr_cpu_core_properties; 275 scc->cpu_type = data; 276 } 277 278 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \ 279 { \ 280 .parent = TYPE_SPAPR_CPU_CORE, \ 281 .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \ 282 .class_init = spapr_cpu_core_class_init, \ 283 .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \ 284 } 285 286 static const TypeInfo spapr_cpu_core_type_infos[] = { 287 { 288 .name = TYPE_SPAPR_CPU_CORE, 289 .parent = TYPE_CPU_CORE, 290 .abstract = true, 291 .instance_size = sizeof(sPAPRCPUCore), 292 .class_size = sizeof(sPAPRCPUCoreClass), 293 }, 294 DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"), 295 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"), 296 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"), 297 DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"), 298 DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"), 299 DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"), 300 DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"), 301 DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"), 302 DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"), 303 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"), 304 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), 305 #ifdef CONFIG_KVM 306 DEFINE_SPAPR_CPU_CORE_TYPE("host"), 307 #endif 308 }; 309 310 DEFINE_TYPES(spapr_cpu_core_type_infos) 311