1 /* 2 * sPAPR CPU core device, acts as container of CPU thread devices. 3 * 4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 #include "hw/cpu/core.h" 10 #include "hw/ppc/spapr_cpu_core.h" 11 #include "target/ppc/cpu.h" 12 #include "hw/ppc/spapr.h" 13 #include "hw/boards.h" 14 #include "qapi/error.h" 15 #include "sysemu/cpus.h" 16 #include "target/ppc/kvm_ppc.h" 17 #include "hw/ppc/ppc.h" 18 #include "target/ppc/mmu-hash64.h" 19 #include "sysemu/numa.h" 20 21 static void spapr_cpu_reset(void *opaque) 22 { 23 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 24 PowerPCCPU *cpu = opaque; 25 CPUState *cs = CPU(cpu); 26 CPUPPCState *env = &cpu->env; 27 28 cpu_reset(cs); 29 30 /* All CPUs start halted. CPU0 is unhalted from the machine level 31 * reset code and the rest are explicitly started up by the guest 32 * using an RTAS call */ 33 cs->halted = 1; 34 35 env->spr[SPR_HIOR] = 0; 36 37 ppc_hash64_set_external_hpt(cpu, spapr->htab, spapr->htab_shift, 38 &error_fatal); 39 } 40 41 static void spapr_cpu_destroy(PowerPCCPU *cpu) 42 { 43 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 44 45 xics_cpu_destroy(spapr->xics, cpu); 46 qemu_unregister_reset(spapr_cpu_reset, cpu); 47 } 48 49 static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, 50 Error **errp) 51 { 52 CPUPPCState *env = &cpu->env; 53 CPUState *cs = CPU(cpu); 54 int i; 55 56 /* Set time-base frequency to 512 MHz */ 57 cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); 58 59 /* Enable PAPR mode in TCG or KVM */ 60 cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr)); 61 cpu_ppc_set_papr(cpu); 62 63 if (cpu->max_compat) { 64 Error *local_err = NULL; 65 66 ppc_set_compat(cpu, cpu->max_compat, &local_err); 67 if (local_err) { 68 error_propagate(errp, local_err); 69 return; 70 } 71 } 72 73 /* Set NUMA node for the added CPUs */ 74 i = numa_get_node_for_cpu(cs->cpu_index); 75 if (i < nb_numa_nodes) { 76 cs->numa_node = i; 77 } 78 79 xics_cpu_setup(spapr->xics, cpu); 80 81 qemu_register_reset(spapr_cpu_reset, cpu); 82 spapr_cpu_reset(cpu); 83 } 84 85 /* 86 * Return the sPAPR CPU core type for @model which essentially is the CPU 87 * model specified with -cpu cmdline option. 88 */ 89 char *spapr_get_cpu_core_type(const char *model) 90 { 91 char *core_type; 92 gchar **model_pieces = g_strsplit(model, ",", 2); 93 94 core_type = g_strdup_printf("%s-%s", model_pieces[0], TYPE_SPAPR_CPU_CORE); 95 96 /* Check whether it exists or whether we have to look up an alias name */ 97 if (!object_class_by_name(core_type)) { 98 const char *realmodel; 99 100 g_free(core_type); 101 core_type = NULL; 102 realmodel = ppc_cpu_lookup_alias(model_pieces[0]); 103 if (realmodel) { 104 core_type = spapr_get_cpu_core_type(realmodel); 105 } 106 } 107 108 g_strfreev(model_pieces); 109 return core_type; 110 } 111 112 static void spapr_cpu_core_unrealizefn(DeviceState *dev, Error **errp) 113 { 114 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 115 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev)); 116 const char *typename = object_class_get_name(scc->cpu_class); 117 size_t size = object_type_get_instance_size(typename); 118 CPUCore *cc = CPU_CORE(dev); 119 int i; 120 121 for (i = 0; i < cc->nr_threads; i++) { 122 void *obj = sc->threads + i * size; 123 DeviceState *dev = DEVICE(obj); 124 CPUState *cs = CPU(dev); 125 PowerPCCPU *cpu = POWERPC_CPU(cs); 126 127 spapr_cpu_destroy(cpu); 128 cpu_remove_sync(cs); 129 object_unparent(obj); 130 } 131 g_free(sc->threads); 132 } 133 134 static void spapr_cpu_core_realize_child(Object *child, Error **errp) 135 { 136 Error *local_err = NULL; 137 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 138 CPUState *cs = CPU(child); 139 PowerPCCPU *cpu = POWERPC_CPU(cs); 140 141 object_property_set_bool(child, true, "realized", &local_err); 142 if (local_err) { 143 error_propagate(errp, local_err); 144 return; 145 } 146 147 spapr_cpu_init(spapr, cpu, &local_err); 148 if (local_err) { 149 error_propagate(errp, local_err); 150 return; 151 } 152 } 153 154 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp) 155 { 156 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 157 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev)); 158 CPUCore *cc = CPU_CORE(OBJECT(dev)); 159 const char *typename = object_class_get_name(scc->cpu_class); 160 size_t size = object_type_get_instance_size(typename); 161 Error *local_err = NULL; 162 void *obj; 163 int i, j; 164 165 sc->threads = g_malloc0(size * cc->nr_threads); 166 for (i = 0; i < cc->nr_threads; i++) { 167 char id[32]; 168 CPUState *cs; 169 170 obj = sc->threads + i * size; 171 172 object_initialize(obj, size, typename); 173 cs = CPU(obj); 174 cs->cpu_index = cc->core_id + i; 175 snprintf(id, sizeof(id), "thread[%d]", i); 176 object_property_add_child(OBJECT(sc), id, obj, &local_err); 177 if (local_err) { 178 goto err; 179 } 180 object_unref(obj); 181 } 182 183 for (j = 0; j < cc->nr_threads; j++) { 184 obj = sc->threads + j * size; 185 186 spapr_cpu_core_realize_child(obj, &local_err); 187 if (local_err) { 188 goto err; 189 } 190 } 191 return; 192 193 err: 194 while (--i >= 0) { 195 obj = sc->threads + i * size; 196 object_unparent(obj); 197 } 198 g_free(sc->threads); 199 error_propagate(errp, local_err); 200 } 201 202 static const char *spapr_core_models[] = { 203 /* 970 */ 204 "970_v2.2", 205 206 /* 970MP variants */ 207 "970MP_v1.0", 208 "970mp_v1.0", 209 "970MP_v1.1", 210 "970mp_v1.1", 211 212 /* POWER5+ */ 213 "POWER5+_v2.1", 214 215 /* POWER7 */ 216 "POWER7_v2.3", 217 218 /* POWER7+ */ 219 "POWER7+_v2.1", 220 221 /* POWER8 */ 222 "POWER8_v2.0", 223 224 /* POWER8E */ 225 "POWER8E_v2.1", 226 227 /* POWER8NVL */ 228 "POWER8NVL_v1.0", 229 }; 230 231 void spapr_cpu_core_class_init(ObjectClass *oc, void *data) 232 { 233 DeviceClass *dc = DEVICE_CLASS(oc); 234 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc); 235 236 dc->realize = spapr_cpu_core_realize; 237 dc->unrealize = spapr_cpu_core_unrealizefn; 238 scc->cpu_class = cpu_class_by_name(TYPE_POWERPC_CPU, data); 239 g_assert(scc->cpu_class); 240 } 241 242 static const TypeInfo spapr_cpu_core_type_info = { 243 .name = TYPE_SPAPR_CPU_CORE, 244 .parent = TYPE_CPU_CORE, 245 .abstract = true, 246 .instance_size = sizeof(sPAPRCPUCore), 247 .class_size = sizeof(sPAPRCPUCoreClass), 248 }; 249 250 static void spapr_cpu_core_register_types(void) 251 { 252 int i; 253 254 type_register_static(&spapr_cpu_core_type_info); 255 256 for (i = 0; i < ARRAY_SIZE(spapr_core_models); i++) { 257 TypeInfo type_info = { 258 .parent = TYPE_SPAPR_CPU_CORE, 259 .instance_size = sizeof(sPAPRCPUCore), 260 .class_init = spapr_cpu_core_class_init, 261 .class_data = (void *) spapr_core_models[i], 262 }; 263 264 type_info.name = g_strdup_printf("%s-" TYPE_SPAPR_CPU_CORE, 265 spapr_core_models[i]); 266 type_register(&type_info); 267 g_free((void *)type_info.name); 268 } 269 } 270 271 type_init(spapr_cpu_core_register_types) 272