1 /* 2 * sPAPR CPU core device, acts as container of CPU thread devices. 3 * 4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/cpu/core.h" 12 #include "hw/ppc/spapr_cpu_core.h" 13 #include "hw/qdev-properties.h" 14 #include "migration/vmstate.h" 15 #include "target/ppc/cpu.h" 16 #include "hw/ppc/spapr.h" 17 #include "qapi/error.h" 18 #include "sysemu/cpus.h" 19 #include "sysemu/kvm.h" 20 #include "target/ppc/kvm_ppc.h" 21 #include "hw/ppc/ppc.h" 22 #include "target/ppc/mmu-hash64.h" 23 #include "sysemu/numa.h" 24 #include "sysemu/reset.h" 25 #include "sysemu/hw_accel.h" 26 #include "qemu/error-report.h" 27 28 static void spapr_cpu_reset(void *opaque) 29 { 30 PowerPCCPU *cpu = opaque; 31 CPUState *cs = CPU(cpu); 32 CPUPPCState *env = &cpu->env; 33 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 34 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 35 target_ulong lpcr; 36 37 cpu_reset(cs); 38 39 /* All CPUs start halted. CPU0 is unhalted from the machine level 40 * reset code and the rest are explicitly started up by the guest 41 * using an RTAS call */ 42 cs->halted = 1; 43 44 /* Set compatibility mode to match the boot CPU, which was either set 45 * by the machine reset code or by CAS. This should never fail. 46 * At startup the value is already set for all the CPUs 47 * but we need this when we hotplug a new CPU 48 */ 49 ppc_set_compat(cpu, POWERPC_CPU(first_cpu)->compat_pvr, &error_abort); 50 51 env->spr[SPR_HIOR] = 0; 52 53 lpcr = env->spr[SPR_LPCR]; 54 55 /* Set emulated LPCR to not send interrupts to hypervisor. Note that 56 * under KVM, the actual HW LPCR will be set differently by KVM itself, 57 * the settings below ensure proper operations with TCG in absence of 58 * a real hypervisor. 59 * 60 * Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for 61 * real mode accesses, which thankfully defaults to 0 and isn't 62 * accessible in guest mode. 63 * 64 * Disable Power-saving mode Exit Cause exceptions for the CPU, so 65 * we don't get spurious wakups before an RTAS start-cpu call. 66 * For the same reason, set PSSCR_EC. 67 */ 68 lpcr &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm); 69 lpcr |= LPCR_LPES0 | LPCR_LPES1; 70 env->spr[SPR_PSSCR] |= PSSCR_EC; 71 72 /* Set RMLS to the max (ie, 16G) */ 73 lpcr &= ~LPCR_RMLS; 74 lpcr |= 1ull << LPCR_RMLS_SHIFT; 75 76 ppc_store_lpcr(cpu, lpcr); 77 78 /* Set a full AMOR so guest can use the AMR as it sees fit */ 79 env->spr[SPR_AMOR] = 0xffffffffffffffffull; 80 81 spapr_cpu->vpa_addr = 0; 82 spapr_cpu->slb_shadow_addr = 0; 83 spapr_cpu->slb_shadow_size = 0; 84 spapr_cpu->dtl_addr = 0; 85 spapr_cpu->dtl_size = 0; 86 87 spapr_caps_cpu_apply(SPAPR_MACHINE(qdev_get_machine()), cpu); 88 89 kvm_check_mmu(cpu, &error_fatal); 90 } 91 92 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3) 93 { 94 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 95 CPUPPCState *env = &cpu->env; 96 97 env->nip = nip; 98 env->gpr[3] = r3; 99 kvmppc_set_reg_ppc_online(cpu, 1); 100 CPU(cpu)->halted = 0; 101 /* Enable Power-saving mode Exit Cause exceptions */ 102 ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm); 103 } 104 105 /* 106 * Return the sPAPR CPU core type for @model which essentially is the CPU 107 * model specified with -cpu cmdline option. 108 */ 109 const char *spapr_get_cpu_core_type(const char *cpu_type) 110 { 111 int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 112 char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"), 113 len, cpu_type); 114 ObjectClass *oc = object_class_by_name(core_type); 115 116 g_free(core_type); 117 if (!oc) { 118 return NULL; 119 } 120 121 return object_class_get_name(oc); 122 } 123 124 static bool slb_shadow_needed(void *opaque) 125 { 126 SpaprCpuState *spapr_cpu = opaque; 127 128 return spapr_cpu->slb_shadow_addr != 0; 129 } 130 131 static const VMStateDescription vmstate_spapr_cpu_slb_shadow = { 132 .name = "spapr_cpu/vpa/slb_shadow", 133 .version_id = 1, 134 .minimum_version_id = 1, 135 .needed = slb_shadow_needed, 136 .fields = (VMStateField[]) { 137 VMSTATE_UINT64(slb_shadow_addr, SpaprCpuState), 138 VMSTATE_UINT64(slb_shadow_size, SpaprCpuState), 139 VMSTATE_END_OF_LIST() 140 } 141 }; 142 143 static bool dtl_needed(void *opaque) 144 { 145 SpaprCpuState *spapr_cpu = opaque; 146 147 return spapr_cpu->dtl_addr != 0; 148 } 149 150 static const VMStateDescription vmstate_spapr_cpu_dtl = { 151 .name = "spapr_cpu/vpa/dtl", 152 .version_id = 1, 153 .minimum_version_id = 1, 154 .needed = dtl_needed, 155 .fields = (VMStateField[]) { 156 VMSTATE_UINT64(dtl_addr, SpaprCpuState), 157 VMSTATE_UINT64(dtl_size, SpaprCpuState), 158 VMSTATE_END_OF_LIST() 159 } 160 }; 161 162 static bool vpa_needed(void *opaque) 163 { 164 SpaprCpuState *spapr_cpu = opaque; 165 166 return spapr_cpu->vpa_addr != 0; 167 } 168 169 static const VMStateDescription vmstate_spapr_cpu_vpa = { 170 .name = "spapr_cpu/vpa", 171 .version_id = 1, 172 .minimum_version_id = 1, 173 .needed = vpa_needed, 174 .fields = (VMStateField[]) { 175 VMSTATE_UINT64(vpa_addr, SpaprCpuState), 176 VMSTATE_END_OF_LIST() 177 }, 178 .subsections = (const VMStateDescription * []) { 179 &vmstate_spapr_cpu_slb_shadow, 180 &vmstate_spapr_cpu_dtl, 181 NULL 182 } 183 }; 184 185 static const VMStateDescription vmstate_spapr_cpu_state = { 186 .name = "spapr_cpu", 187 .version_id = 1, 188 .minimum_version_id = 1, 189 .fields = (VMStateField[]) { 190 VMSTATE_END_OF_LIST() 191 }, 192 .subsections = (const VMStateDescription * []) { 193 &vmstate_spapr_cpu_vpa, 194 NULL 195 } 196 }; 197 198 static void spapr_unrealize_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc) 199 { 200 if (!sc->pre_3_0_migration) { 201 vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data); 202 } 203 qemu_unregister_reset(spapr_cpu_reset, cpu); 204 if (spapr_cpu_state(cpu)->icp) { 205 object_unparent(OBJECT(spapr_cpu_state(cpu)->icp)); 206 } 207 if (spapr_cpu_state(cpu)->tctx) { 208 object_unparent(OBJECT(spapr_cpu_state(cpu)->tctx)); 209 } 210 cpu_remove_sync(CPU(cpu)); 211 object_unparent(OBJECT(cpu)); 212 } 213 214 static void spapr_cpu_core_unrealize(DeviceState *dev, Error **errp) 215 { 216 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 217 CPUCore *cc = CPU_CORE(dev); 218 int i; 219 220 for (i = 0; i < cc->nr_threads; i++) { 221 spapr_unrealize_vcpu(sc->threads[i], sc); 222 } 223 g_free(sc->threads); 224 } 225 226 static void spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr, 227 SpaprCpuCore *sc, Error **errp) 228 { 229 CPUPPCState *env = &cpu->env; 230 CPUState *cs = CPU(cpu); 231 Error *local_err = NULL; 232 233 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 234 if (local_err) { 235 goto error; 236 } 237 238 /* Set time-base frequency to 512 MHz */ 239 cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); 240 241 cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr)); 242 kvmppc_set_papr(cpu); 243 244 qemu_register_reset(spapr_cpu_reset, cpu); 245 spapr_cpu_reset(cpu); 246 247 spapr->irq->cpu_intc_create(spapr, cpu, &local_err); 248 if (local_err) { 249 goto error_unregister; 250 } 251 252 if (!sc->pre_3_0_migration) { 253 vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state, 254 cpu->machine_data); 255 } 256 257 return; 258 259 error_unregister: 260 qemu_unregister_reset(spapr_cpu_reset, cpu); 261 cpu_remove_sync(CPU(cpu)); 262 error: 263 error_propagate(errp, local_err); 264 } 265 266 static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp) 267 { 268 SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc); 269 CPUCore *cc = CPU_CORE(sc); 270 Object *obj; 271 char *id; 272 CPUState *cs; 273 PowerPCCPU *cpu; 274 Error *local_err = NULL; 275 276 obj = object_new(scc->cpu_type); 277 278 cs = CPU(obj); 279 cpu = POWERPC_CPU(obj); 280 cs->cpu_index = cc->core_id + i; 281 spapr_set_vcpu_id(cpu, cs->cpu_index, &local_err); 282 if (local_err) { 283 goto err; 284 } 285 286 cpu->node_id = sc->node_id; 287 288 id = g_strdup_printf("thread[%d]", i); 289 object_property_add_child(OBJECT(sc), id, obj, &local_err); 290 g_free(id); 291 if (local_err) { 292 goto err; 293 } 294 295 cpu->machine_data = g_new0(SpaprCpuState, 1); 296 297 object_unref(obj); 298 return cpu; 299 300 err: 301 object_unref(obj); 302 error_propagate(errp, local_err); 303 return NULL; 304 } 305 306 static void spapr_delete_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc) 307 { 308 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 309 310 cpu->machine_data = NULL; 311 g_free(spapr_cpu); 312 object_unparent(OBJECT(cpu)); 313 } 314 315 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp) 316 { 317 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user 318 * tries to add a sPAPR CPU core to a non-pseries machine. 319 */ 320 SpaprMachineState *spapr = 321 (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(), 322 TYPE_SPAPR_MACHINE); 323 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 324 CPUCore *cc = CPU_CORE(OBJECT(dev)); 325 Error *local_err = NULL; 326 int i, j; 327 328 if (!spapr) { 329 error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine"); 330 return; 331 } 332 333 sc->threads = g_new(PowerPCCPU *, cc->nr_threads); 334 for (i = 0; i < cc->nr_threads; i++) { 335 sc->threads[i] = spapr_create_vcpu(sc, i, &local_err); 336 if (local_err) { 337 goto err; 338 } 339 } 340 341 for (j = 0; j < cc->nr_threads; j++) { 342 spapr_realize_vcpu(sc->threads[j], spapr, sc, &local_err); 343 if (local_err) { 344 goto err_unrealize; 345 } 346 } 347 return; 348 349 err_unrealize: 350 while (--j >= 0) { 351 spapr_unrealize_vcpu(sc->threads[j], sc); 352 } 353 err: 354 while (--i >= 0) { 355 spapr_delete_vcpu(sc->threads[i], sc); 356 } 357 g_free(sc->threads); 358 error_propagate(errp, local_err); 359 } 360 361 static Property spapr_cpu_core_properties[] = { 362 DEFINE_PROP_INT32("node-id", SpaprCpuCore, node_id, CPU_UNSET_NUMA_NODE_ID), 363 DEFINE_PROP_BOOL("pre-3.0-migration", SpaprCpuCore, pre_3_0_migration, 364 false), 365 DEFINE_PROP_END_OF_LIST() 366 }; 367 368 static void spapr_cpu_core_class_init(ObjectClass *oc, void *data) 369 { 370 DeviceClass *dc = DEVICE_CLASS(oc); 371 SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc); 372 373 dc->realize = spapr_cpu_core_realize; 374 dc->unrealize = spapr_cpu_core_unrealize; 375 dc->props = spapr_cpu_core_properties; 376 scc->cpu_type = data; 377 } 378 379 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \ 380 { \ 381 .parent = TYPE_SPAPR_CPU_CORE, \ 382 .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \ 383 .class_init = spapr_cpu_core_class_init, \ 384 .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \ 385 } 386 387 static const TypeInfo spapr_cpu_core_type_infos[] = { 388 { 389 .name = TYPE_SPAPR_CPU_CORE, 390 .parent = TYPE_CPU_CORE, 391 .abstract = true, 392 .instance_size = sizeof(SpaprCpuCore), 393 .class_size = sizeof(SpaprCpuCoreClass), 394 }, 395 DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"), 396 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"), 397 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"), 398 DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"), 399 DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"), 400 DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"), 401 DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"), 402 DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"), 403 DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"), 404 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"), 405 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), 406 #ifdef CONFIG_KVM 407 DEFINE_SPAPR_CPU_CORE_TYPE("host"), 408 #endif 409 }; 410 411 DEFINE_TYPES(spapr_cpu_core_type_infos) 412