1 /* 2 * QEMU PowerPC pSeries Logical Partition capabilities handling 3 * 4 * Copyright (c) 2017 David Gibson, Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/error-report.h" 27 #include "qapi/error.h" 28 #include "qapi/visitor.h" 29 #include "sysemu/hw_accel.h" 30 #include "exec/ram_addr.h" 31 #include "target/ppc/cpu.h" 32 #include "target/ppc/mmu-hash64.h" 33 #include "cpu-models.h" 34 #include "kvm_ppc.h" 35 #include "migration/vmstate.h" 36 #include "sysemu/tcg.h" 37 38 #include "hw/ppc/spapr.h" 39 40 typedef struct SpaprCapPossible { 41 int num; /* size of vals array below */ 42 const char *help; /* help text for vals */ 43 /* 44 * Note: 45 * - because of the way compatibility is determined vals MUST be ordered 46 * such that later options are a superset of all preceding options. 47 * - the order of vals must be preserved, that is their index is important, 48 * however vals may be added to the end of the list so long as the above 49 * point is observed 50 */ 51 const char *vals[]; 52 } SpaprCapPossible; 53 54 typedef struct SpaprCapabilityInfo { 55 const char *name; 56 const char *description; 57 int index; 58 59 /* Getter and Setter Function Pointers */ 60 ObjectPropertyAccessor *get; 61 ObjectPropertyAccessor *set; 62 const char *type; 63 /* Possible values if this is a custom string type */ 64 SpaprCapPossible *possible; 65 /* Make sure the virtual hardware can support this capability */ 66 void (*apply)(SpaprMachineState *spapr, uint8_t val, Error **errp); 67 void (*cpu_apply)(SpaprMachineState *spapr, PowerPCCPU *cpu, 68 uint8_t val, Error **errp); 69 bool (*migrate_needed)(void *opaque); 70 } SpaprCapabilityInfo; 71 72 static void spapr_cap_get_bool(Object *obj, Visitor *v, const char *name, 73 void *opaque, Error **errp) 74 { 75 SpaprCapabilityInfo *cap = opaque; 76 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 77 bool value = spapr_get_cap(spapr, cap->index) == SPAPR_CAP_ON; 78 79 visit_type_bool(v, name, &value, errp); 80 } 81 82 static void spapr_cap_set_bool(Object *obj, Visitor *v, const char *name, 83 void *opaque, Error **errp) 84 { 85 SpaprCapabilityInfo *cap = opaque; 86 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 87 bool value; 88 89 if (!visit_type_bool(v, name, &value, errp)) { 90 return; 91 } 92 93 spapr->cmd_line_caps[cap->index] = true; 94 spapr->eff.caps[cap->index] = value ? SPAPR_CAP_ON : SPAPR_CAP_OFF; 95 } 96 97 98 static void spapr_cap_get_string(Object *obj, Visitor *v, const char *name, 99 void *opaque, Error **errp) 100 { 101 SpaprCapabilityInfo *cap = opaque; 102 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 103 g_autofree char *val = NULL; 104 uint8_t value = spapr_get_cap(spapr, cap->index); 105 106 if (value >= cap->possible->num) { 107 error_setg(errp, "Invalid value (%d) for cap-%s", value, cap->name); 108 return; 109 } 110 111 val = g_strdup(cap->possible->vals[value]); 112 113 visit_type_str(v, name, &val, errp); 114 } 115 116 static void spapr_cap_set_string(Object *obj, Visitor *v, const char *name, 117 void *opaque, Error **errp) 118 { 119 SpaprCapabilityInfo *cap = opaque; 120 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 121 uint8_t i; 122 g_autofree char *val = NULL; 123 124 if (!visit_type_str(v, name, &val, errp)) { 125 return; 126 } 127 128 if (!strcmp(val, "?")) { 129 error_setg(errp, "%s", cap->possible->help); 130 return; 131 } 132 for (i = 0; i < cap->possible->num; i++) { 133 if (!strcasecmp(val, cap->possible->vals[i])) { 134 spapr->cmd_line_caps[cap->index] = true; 135 spapr->eff.caps[cap->index] = i; 136 return; 137 } 138 } 139 140 error_setg(errp, "Invalid capability mode \"%s\" for cap-%s", val, 141 cap->name); 142 } 143 144 static void spapr_cap_get_pagesize(Object *obj, Visitor *v, const char *name, 145 void *opaque, Error **errp) 146 { 147 SpaprCapabilityInfo *cap = opaque; 148 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 149 uint8_t val = spapr_get_cap(spapr, cap->index); 150 uint64_t pagesize = (1ULL << val); 151 152 visit_type_size(v, name, &pagesize, errp); 153 } 154 155 static void spapr_cap_set_pagesize(Object *obj, Visitor *v, const char *name, 156 void *opaque, Error **errp) 157 { 158 SpaprCapabilityInfo *cap = opaque; 159 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 160 uint64_t pagesize; 161 uint8_t val; 162 163 if (!visit_type_size(v, name, &pagesize, errp)) { 164 return; 165 } 166 167 if (!is_power_of_2(pagesize)) { 168 error_setg(errp, "cap-%s must be a power of 2", cap->name); 169 return; 170 } 171 172 val = ctz64(pagesize); 173 spapr->cmd_line_caps[cap->index] = true; 174 spapr->eff.caps[cap->index] = val; 175 } 176 177 static void cap_htm_apply(SpaprMachineState *spapr, uint8_t val, Error **errp) 178 { 179 ERRP_GUARD(); 180 if (!val) { 181 /* TODO: We don't support disabling htm yet */ 182 return; 183 } 184 if (tcg_enabled()) { 185 error_setg(errp, "No Transactional Memory support in TCG"); 186 error_append_hint(errp, "Try appending -machine cap-htm=off\n"); 187 } else if (kvm_enabled() && !kvmppc_has_cap_htm()) { 188 error_setg(errp, 189 "KVM implementation does not support Transactional Memory"); 190 error_append_hint(errp, "Try appending -machine cap-htm=off\n"); 191 } 192 } 193 194 static void cap_vsx_apply(SpaprMachineState *spapr, uint8_t val, Error **errp) 195 { 196 ERRP_GUARD(); 197 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 198 CPUPPCState *env = &cpu->env; 199 200 if (!val) { 201 /* TODO: We don't support disabling vsx yet */ 202 return; 203 } 204 /* Allowable CPUs in spapr_cpu_core.c should already have gotten 205 * rid of anything that doesn't do VMX */ 206 g_assert(env->insns_flags & PPC_ALTIVEC); 207 if (!(env->insns_flags2 & PPC2_VSX)) { 208 error_setg(errp, "VSX support not available"); 209 error_append_hint(errp, "Try appending -machine cap-vsx=off\n"); 210 } 211 } 212 213 static void cap_dfp_apply(SpaprMachineState *spapr, uint8_t val, Error **errp) 214 { 215 ERRP_GUARD(); 216 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 217 CPUPPCState *env = &cpu->env; 218 219 if (!val) { 220 /* TODO: We don't support disabling dfp yet */ 221 return; 222 } 223 if (!(env->insns_flags2 & PPC2_DFP)) { 224 error_setg(errp, "DFP support not available"); 225 error_append_hint(errp, "Try appending -machine cap-dfp=off\n"); 226 } 227 } 228 229 SpaprCapPossible cap_cfpc_possible = { 230 .num = 3, 231 .vals = {"broken", "workaround", "fixed"}, 232 .help = "broken - no protection, workaround - workaround available," 233 " fixed - fixed in hardware", 234 }; 235 236 static void cap_safe_cache_apply(SpaprMachineState *spapr, uint8_t val, 237 Error **errp) 238 { 239 ERRP_GUARD(); 240 uint8_t kvm_val = kvmppc_get_cap_safe_cache(); 241 242 if (tcg_enabled() && val) { 243 /* TCG only supports broken, allow other values and print a warning */ 244 warn_report("TCG doesn't support requested feature, cap-cfpc=%s", 245 cap_cfpc_possible.vals[val]); 246 } else if (kvm_enabled() && (val > kvm_val)) { 247 error_setg(errp, 248 "Requested safe cache capability level not supported by KVM"); 249 error_append_hint(errp, "Try appending -machine cap-cfpc=%s\n", 250 cap_cfpc_possible.vals[kvm_val]); 251 } 252 } 253 254 SpaprCapPossible cap_sbbc_possible = { 255 .num = 3, 256 .vals = {"broken", "workaround", "fixed"}, 257 .help = "broken - no protection, workaround - workaround available," 258 " fixed - fixed in hardware", 259 }; 260 261 static void cap_safe_bounds_check_apply(SpaprMachineState *spapr, uint8_t val, 262 Error **errp) 263 { 264 ERRP_GUARD(); 265 uint8_t kvm_val = kvmppc_get_cap_safe_bounds_check(); 266 267 if (tcg_enabled() && val) { 268 /* TCG only supports broken, allow other values and print a warning */ 269 warn_report("TCG doesn't support requested feature, cap-sbbc=%s", 270 cap_sbbc_possible.vals[val]); 271 } else if (kvm_enabled() && (val > kvm_val)) { 272 error_setg(errp, 273 "Requested safe bounds check capability level not supported by KVM"); 274 error_append_hint(errp, "Try appending -machine cap-sbbc=%s\n", 275 cap_sbbc_possible.vals[kvm_val]); 276 } 277 } 278 279 SpaprCapPossible cap_ibs_possible = { 280 .num = 5, 281 /* Note workaround only maintained for compatibility */ 282 .vals = {"broken", "workaround", "fixed-ibs", "fixed-ccd", "fixed-na"}, 283 .help = "broken - no protection, workaround - count cache flush" 284 ", fixed-ibs - indirect branch serialisation," 285 " fixed-ccd - cache count disabled," 286 " fixed-na - fixed in hardware (no longer applicable)", 287 }; 288 289 static void cap_safe_indirect_branch_apply(SpaprMachineState *spapr, 290 uint8_t val, Error **errp) 291 { 292 ERRP_GUARD(); 293 uint8_t kvm_val = kvmppc_get_cap_safe_indirect_branch(); 294 295 if (tcg_enabled() && val) { 296 /* TCG only supports broken, allow other values and print a warning */ 297 warn_report("TCG doesn't support requested feature, cap-ibs=%s", 298 cap_ibs_possible.vals[val]); 299 } else if (kvm_enabled() && (val > kvm_val)) { 300 error_setg(errp, 301 "Requested safe indirect branch capability level not supported by KVM"); 302 error_append_hint(errp, "Try appending -machine cap-ibs=%s\n", 303 cap_ibs_possible.vals[kvm_val]); 304 } 305 } 306 307 #define VALUE_DESC_TRISTATE " (broken, workaround, fixed)" 308 309 bool spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, 310 Error **errp) 311 { 312 hwaddr maxpagesize = (1ULL << spapr->eff.caps[SPAPR_CAP_HPT_MAXPAGESIZE]); 313 314 if (!kvmppc_hpt_needs_host_contiguous_pages()) { 315 return true; 316 } 317 318 if (maxpagesize > pagesize) { 319 error_setg(errp, 320 "Can't support %"HWADDR_PRIu" kiB guest pages with %" 321 HWADDR_PRIu" kiB host pages with this KVM implementation", 322 maxpagesize >> 10, pagesize >> 10); 323 return false; 324 } 325 326 return true; 327 } 328 329 static void cap_hpt_maxpagesize_apply(SpaprMachineState *spapr, 330 uint8_t val, Error **errp) 331 { 332 if (val < 12) { 333 error_setg(errp, "Require at least 4kiB hpt-max-page-size"); 334 return; 335 } else if (val < 16) { 336 warn_report("Many guests require at least 64kiB hpt-max-page-size"); 337 } 338 339 spapr_check_pagesize(spapr, qemu_minrampagesize(), errp); 340 } 341 342 static bool cap_hpt_maxpagesize_migrate_needed(void *opaque) 343 { 344 return !SPAPR_MACHINE_GET_CLASS(opaque)->pre_4_1_migration; 345 } 346 347 static bool spapr_pagesize_cb(void *opaque, uint32_t seg_pshift, 348 uint32_t pshift) 349 { 350 unsigned maxshift = *((unsigned *)opaque); 351 352 assert(pshift >= seg_pshift); 353 354 /* Don't allow the guest to use pages bigger than the configured 355 * maximum size */ 356 if (pshift > maxshift) { 357 return false; 358 } 359 360 /* For whatever reason, KVM doesn't allow multiple pagesizes 361 * within a segment, *except* for the case of 16M pages in a 4k or 362 * 64k segment. Always exclude other cases, so that TCG and KVM 363 * guests see a consistent environment */ 364 if ((pshift != seg_pshift) && (pshift != 24)) { 365 return false; 366 } 367 368 return true; 369 } 370 371 static void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu, 372 bool (*cb)(void *, uint32_t, uint32_t), 373 void *opaque) 374 { 375 PPCHash64Options *opts = cpu->hash64_opts; 376 int i; 377 int n = 0; 378 bool ci_largepage = false; 379 380 assert(opts); 381 382 n = 0; 383 for (i = 0; i < ARRAY_SIZE(opts->sps); i++) { 384 PPCHash64SegmentPageSizes *sps = &opts->sps[i]; 385 int j; 386 int m = 0; 387 388 assert(n <= i); 389 390 if (!sps->page_shift) { 391 break; 392 } 393 394 for (j = 0; j < ARRAY_SIZE(sps->enc); j++) { 395 PPCHash64PageSize *ps = &sps->enc[j]; 396 397 assert(m <= j); 398 if (!ps->page_shift) { 399 break; 400 } 401 402 if (cb(opaque, sps->page_shift, ps->page_shift)) { 403 if (ps->page_shift >= 16) { 404 ci_largepage = true; 405 } 406 sps->enc[m++] = *ps; 407 } 408 } 409 410 /* Clear rest of the row */ 411 for (j = m; j < ARRAY_SIZE(sps->enc); j++) { 412 memset(&sps->enc[j], 0, sizeof(sps->enc[j])); 413 } 414 415 if (m) { 416 n++; 417 } 418 } 419 420 /* Clear the rest of the table */ 421 for (i = n; i < ARRAY_SIZE(opts->sps); i++) { 422 memset(&opts->sps[i], 0, sizeof(opts->sps[i])); 423 } 424 425 if (!ci_largepage) { 426 opts->flags &= ~PPC_HASH64_CI_LARGEPAGE; 427 } 428 } 429 430 static void cap_hpt_maxpagesize_cpu_apply(SpaprMachineState *spapr, 431 PowerPCCPU *cpu, 432 uint8_t val, Error **errp) 433 { 434 unsigned maxshift = val; 435 436 ppc_hash64_filter_pagesizes(cpu, spapr_pagesize_cb, &maxshift); 437 } 438 439 static void cap_nested_kvm_hv_apply(SpaprMachineState *spapr, 440 uint8_t val, Error **errp) 441 { 442 ERRP_GUARD(); 443 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 444 CPUPPCState *env = &cpu->env; 445 446 if (!val) { 447 /* capability disabled by default */ 448 return; 449 } 450 451 if (!(env->insns_flags2 & PPC2_ISA300)) { 452 error_setg(errp, "Nested-HV only supported on POWER9 and later"); 453 error_append_hint(errp, "Try appending -machine cap-nested-hv=off\n"); 454 return; 455 } 456 457 if (kvm_enabled()) { 458 if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, 459 spapr->max_compat_pvr)) { 460 error_setg(errp, "Nested-HV only supported on POWER9 and later"); 461 error_append_hint(errp, 462 "Try appending -machine max-cpu-compat=power9\n"); 463 return; 464 } 465 466 if (!kvmppc_has_cap_nested_kvm_hv()) { 467 error_setg(errp, 468 "KVM implementation does not support Nested-HV"); 469 error_append_hint(errp, 470 "Try appending -machine cap-nested-hv=off\n"); 471 } else if (kvmppc_set_cap_nested_kvm_hv(val) < 0) { 472 error_setg(errp, "Error enabling cap-nested-hv with KVM"); 473 error_append_hint(errp, 474 "Try appending -machine cap-nested-hv=off\n"); 475 } 476 } else if (tcg_enabled()) { 477 MachineState *ms = MACHINE(spapr); 478 unsigned int smp_threads = ms->smp.threads; 479 480 /* 481 * Nested-HV vCPU env state to L2, so SMT-shared SPR updates, for 482 * example, do not necessarily update the correct SPR value on sibling 483 * threads that are in a different guest/host context. 484 */ 485 if (smp_threads > 1) { 486 error_setg(errp, "TCG does not support nested-HV with SMT"); 487 error_append_hint(errp, "Try appending -machine cap-nested-hv=off " 488 "or use threads=1 with -smp\n"); 489 } 490 if (spapr_nested_api(spapr) && 491 spapr_nested_api(spapr) != NESTED_API_KVM_HV) { 492 error_setg(errp, "Nested-HV APIs are mutually exclusive"); 493 error_append_hint(errp, "Please use either cap-nested-hv or " 494 "cap-nested-papr to proceed.\n"); 495 return; 496 } else { 497 spapr->nested.api = NESTED_API_KVM_HV; 498 } 499 } 500 } 501 502 static void cap_nested_papr_apply(SpaprMachineState *spapr, 503 uint8_t val, Error **errp) 504 { 505 ERRP_GUARD(); 506 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 507 CPUPPCState *env = &cpu->env; 508 509 if (!val) { 510 /* capability disabled by default */ 511 return; 512 } 513 514 if (tcg_enabled()) { 515 if (!(env->insns_flags2 & PPC2_ISA300)) { 516 error_setg(errp, "Nested-PAPR only supported on POWER9 and later"); 517 error_append_hint(errp, 518 "Try appending -machine cap-nested-papr=off\n"); 519 return; 520 } 521 if (spapr_nested_api(spapr) && 522 spapr_nested_api(spapr) != NESTED_API_PAPR) { 523 error_setg(errp, "Nested-HV APIs are mutually exclusive"); 524 error_append_hint(errp, "Please use either cap-nested-hv or " 525 "cap-nested-papr to proceed.\n"); 526 return; 527 } else { 528 spapr->nested.api = NESTED_API_PAPR; 529 } 530 } else if (kvm_enabled()) { 531 error_setg(errp, "KVM implementation does not support Nested-PAPR"); 532 error_append_hint(errp, 533 "Try appending -machine cap-nested-papr=off\n"); 534 } 535 } 536 537 static void cap_large_decr_apply(SpaprMachineState *spapr, 538 uint8_t val, Error **errp) 539 { 540 ERRP_GUARD(); 541 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 542 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 543 544 if (!val) { 545 return; /* Disabled by default */ 546 } 547 548 if (tcg_enabled()) { 549 if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, 550 spapr->max_compat_pvr)) { 551 error_setg(errp, "Large decrementer only supported on POWER9"); 552 error_append_hint(errp, "Try -cpu POWER9\n"); 553 return; 554 } 555 } else if (kvm_enabled()) { 556 int kvm_nr_bits = kvmppc_get_cap_large_decr(); 557 558 if (!kvm_nr_bits) { 559 error_setg(errp, "No large decrementer support"); 560 error_append_hint(errp, 561 "Try appending -machine cap-large-decr=off\n"); 562 } else if (pcc->lrg_decr_bits != kvm_nr_bits) { 563 error_setg(errp, 564 "KVM large decrementer size (%d) differs to model (%d)", 565 kvm_nr_bits, pcc->lrg_decr_bits); 566 error_append_hint(errp, 567 "Try appending -machine cap-large-decr=off\n"); 568 } 569 } 570 } 571 572 static void cap_large_decr_cpu_apply(SpaprMachineState *spapr, 573 PowerPCCPU *cpu, 574 uint8_t val, Error **errp) 575 { 576 ERRP_GUARD(); 577 CPUPPCState *env = &cpu->env; 578 target_ulong lpcr = env->spr[SPR_LPCR]; 579 580 if (kvm_enabled()) { 581 if (kvmppc_enable_cap_large_decr(cpu, val)) { 582 error_setg(errp, "No large decrementer support"); 583 error_append_hint(errp, 584 "Try appending -machine cap-large-decr=off\n"); 585 } 586 } 587 588 if (val) { 589 lpcr |= LPCR_LD; 590 } else { 591 lpcr &= ~LPCR_LD; 592 } 593 ppc_store_lpcr(cpu, lpcr); 594 } 595 596 static void cap_ccf_assist_apply(SpaprMachineState *spapr, uint8_t val, 597 Error **errp) 598 { 599 ERRP_GUARD(); 600 uint8_t kvm_val = kvmppc_get_cap_count_cache_flush_assist(); 601 602 if (tcg_enabled() && val) { 603 /* TCG doesn't implement anything here, but allow with a warning */ 604 warn_report("TCG doesn't support requested feature, cap-ccf-assist=on"); 605 } else if (kvm_enabled() && (val > kvm_val)) { 606 uint8_t kvm_ibs = kvmppc_get_cap_safe_indirect_branch(); 607 608 if (kvm_ibs == SPAPR_CAP_FIXED_CCD) { 609 /* 610 * If we don't have CCF assist on the host, the assist 611 * instruction is a harmless no-op. It won't correctly 612 * implement the cache count flush *but* if we have 613 * count-cache-disabled in the host, that flush is 614 * unnecessary. So, specifically allow this case. This 615 * allows us to have better performance on POWER9 DD2.3, 616 * while still working on POWER9 DD2.2 and POWER8 host 617 * cpus. 618 */ 619 return; 620 } 621 error_setg(errp, 622 "Requested count cache flush assist capability level not supported by KVM"); 623 error_append_hint(errp, "Try appending -machine cap-ccf-assist=off\n"); 624 } 625 } 626 627 static void cap_fwnmi_apply(SpaprMachineState *spapr, uint8_t val, 628 Error **errp) 629 { 630 ERRP_GUARD(); 631 if (!val) { 632 return; /* Disabled by default */ 633 } 634 635 if (kvm_enabled()) { 636 if (!kvmppc_get_fwnmi()) { 637 error_setg(errp, 638 "Firmware Assisted Non-Maskable Interrupts(FWNMI) not supported by KVM."); 639 error_append_hint(errp, "Try appending -machine cap-fwnmi=off\n"); 640 } 641 } 642 } 643 644 static void cap_rpt_invalidate_apply(SpaprMachineState *spapr, 645 uint8_t val, Error **errp) 646 { 647 ERRP_GUARD(); 648 649 if (!val) { 650 /* capability disabled by default */ 651 return; 652 } 653 654 if (tcg_enabled()) { 655 error_setg(errp, "No H_RPT_INVALIDATE support in TCG"); 656 error_append_hint(errp, 657 "Try appending -machine cap-rpt-invalidate=off\n"); 658 } else if (kvm_enabled()) { 659 if (!kvmppc_has_cap_mmu_radix()) { 660 error_setg(errp, "H_RPT_INVALIDATE only supported on Radix"); 661 return; 662 } 663 664 if (!kvmppc_has_cap_rpt_invalidate()) { 665 error_setg(errp, 666 "KVM implementation does not support H_RPT_INVALIDATE"); 667 error_append_hint(errp, 668 "Try appending -machine cap-rpt-invalidate=off\n"); 669 } else { 670 kvmppc_enable_h_rpt_invalidate(); 671 } 672 } 673 } 674 675 static void cap_ail_mode_3_apply(SpaprMachineState *spapr, 676 uint8_t val, Error **errp) 677 { 678 ERRP_GUARD(); 679 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 680 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 681 682 if (!val) { 683 return; 684 } 685 686 if (tcg_enabled()) { 687 /* AIL-3 is only supported on POWER8 and above CPUs. */ 688 if (!(pcc->insns_flags2 & PPC2_ISA207S)) { 689 error_setg(errp, "TCG only supports cap-ail-mode-3 on POWER8 and later CPUs"); 690 error_append_hint(errp, "Try appending -machine cap-ail-mode-3=off\n"); 691 return; 692 } 693 } else if (kvm_enabled()) { 694 if (!kvmppc_supports_ail_3()) { 695 error_setg(errp, "KVM implementation does not support cap-ail-mode-3"); 696 error_append_hint(errp, "Try appending -machine cap-ail-mode-3=off\n"); 697 return; 698 } 699 } 700 } 701 702 SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] = { 703 [SPAPR_CAP_HTM] = { 704 .name = "htm", 705 .description = "Allow Hardware Transactional Memory (HTM)", 706 .index = SPAPR_CAP_HTM, 707 .get = spapr_cap_get_bool, 708 .set = spapr_cap_set_bool, 709 .type = "bool", 710 .apply = cap_htm_apply, 711 }, 712 [SPAPR_CAP_VSX] = { 713 .name = "vsx", 714 .description = "Allow Vector Scalar Extensions (VSX)", 715 .index = SPAPR_CAP_VSX, 716 .get = spapr_cap_get_bool, 717 .set = spapr_cap_set_bool, 718 .type = "bool", 719 .apply = cap_vsx_apply, 720 }, 721 [SPAPR_CAP_DFP] = { 722 .name = "dfp", 723 .description = "Allow Decimal Floating Point (DFP)", 724 .index = SPAPR_CAP_DFP, 725 .get = spapr_cap_get_bool, 726 .set = spapr_cap_set_bool, 727 .type = "bool", 728 .apply = cap_dfp_apply, 729 }, 730 [SPAPR_CAP_CFPC] = { 731 .name = "cfpc", 732 .description = "Cache Flush on Privilege Change" VALUE_DESC_TRISTATE, 733 .index = SPAPR_CAP_CFPC, 734 .get = spapr_cap_get_string, 735 .set = spapr_cap_set_string, 736 .type = "string", 737 .possible = &cap_cfpc_possible, 738 .apply = cap_safe_cache_apply, 739 }, 740 [SPAPR_CAP_SBBC] = { 741 .name = "sbbc", 742 .description = "Speculation Barrier Bounds Checking" VALUE_DESC_TRISTATE, 743 .index = SPAPR_CAP_SBBC, 744 .get = spapr_cap_get_string, 745 .set = spapr_cap_set_string, 746 .type = "string", 747 .possible = &cap_sbbc_possible, 748 .apply = cap_safe_bounds_check_apply, 749 }, 750 [SPAPR_CAP_IBS] = { 751 .name = "ibs", 752 .description = 753 "Indirect Branch Speculation (broken, workaround, fixed-ibs," 754 "fixed-ccd, fixed-na)", 755 .index = SPAPR_CAP_IBS, 756 .get = spapr_cap_get_string, 757 .set = spapr_cap_set_string, 758 .type = "string", 759 .possible = &cap_ibs_possible, 760 .apply = cap_safe_indirect_branch_apply, 761 }, 762 [SPAPR_CAP_HPT_MAXPAGESIZE] = { 763 .name = "hpt-max-page-size", 764 .description = "Maximum page size for Hash Page Table guests", 765 .index = SPAPR_CAP_HPT_MAXPAGESIZE, 766 .get = spapr_cap_get_pagesize, 767 .set = spapr_cap_set_pagesize, 768 .type = "int", 769 .apply = cap_hpt_maxpagesize_apply, 770 .cpu_apply = cap_hpt_maxpagesize_cpu_apply, 771 .migrate_needed = cap_hpt_maxpagesize_migrate_needed, 772 }, 773 [SPAPR_CAP_NESTED_KVM_HV] = { 774 .name = "nested-hv", 775 .description = "Allow Nested KVM-HV", 776 .index = SPAPR_CAP_NESTED_KVM_HV, 777 .get = spapr_cap_get_bool, 778 .set = spapr_cap_set_bool, 779 .type = "bool", 780 .apply = cap_nested_kvm_hv_apply, 781 }, 782 [SPAPR_CAP_NESTED_PAPR] = { 783 .name = "nested-papr", 784 .description = "Allow Nested HV (PAPR API)", 785 .index = SPAPR_CAP_NESTED_PAPR, 786 .get = spapr_cap_get_bool, 787 .set = spapr_cap_set_bool, 788 .type = "bool", 789 .apply = cap_nested_papr_apply, 790 }, 791 [SPAPR_CAP_LARGE_DECREMENTER] = { 792 .name = "large-decr", 793 .description = "Allow Large Decrementer", 794 .index = SPAPR_CAP_LARGE_DECREMENTER, 795 .get = spapr_cap_get_bool, 796 .set = spapr_cap_set_bool, 797 .type = "bool", 798 .apply = cap_large_decr_apply, 799 .cpu_apply = cap_large_decr_cpu_apply, 800 }, 801 [SPAPR_CAP_CCF_ASSIST] = { 802 .name = "ccf-assist", 803 .description = "Count Cache Flush Assist via HW Instruction", 804 .index = SPAPR_CAP_CCF_ASSIST, 805 .get = spapr_cap_get_bool, 806 .set = spapr_cap_set_bool, 807 .type = "bool", 808 .apply = cap_ccf_assist_apply, 809 }, 810 [SPAPR_CAP_FWNMI] = { 811 .name = "fwnmi", 812 .description = "Implements PAPR FWNMI option", 813 .index = SPAPR_CAP_FWNMI, 814 .get = spapr_cap_get_bool, 815 .set = spapr_cap_set_bool, 816 .type = "bool", 817 .apply = cap_fwnmi_apply, 818 }, 819 [SPAPR_CAP_RPT_INVALIDATE] = { 820 .name = "rpt-invalidate", 821 .description = "Allow H_RPT_INVALIDATE", 822 .index = SPAPR_CAP_RPT_INVALIDATE, 823 .get = spapr_cap_get_bool, 824 .set = spapr_cap_set_bool, 825 .type = "bool", 826 .apply = cap_rpt_invalidate_apply, 827 }, 828 [SPAPR_CAP_AIL_MODE_3] = { 829 .name = "ail-mode-3", 830 .description = "Alternate Interrupt Location (AIL) mode 3 support", 831 .index = SPAPR_CAP_AIL_MODE_3, 832 .get = spapr_cap_get_bool, 833 .set = spapr_cap_set_bool, 834 .type = "bool", 835 .apply = cap_ail_mode_3_apply, 836 }, 837 }; 838 839 static SpaprCapabilities default_caps_with_cpu(SpaprMachineState *spapr, 840 const char *cputype) 841 { 842 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 843 SpaprCapabilities caps; 844 845 caps = smc->default_caps; 846 847 if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_3_00, 848 0, spapr->max_compat_pvr)) { 849 caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 850 } 851 852 if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_2_07, 853 0, spapr->max_compat_pvr)) { 854 caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 855 caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 856 caps.caps[SPAPR_CAP_AIL_MODE_3] = SPAPR_CAP_OFF; 857 } 858 859 if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_2_06_PLUS, 860 0, spapr->max_compat_pvr)) { 861 caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 862 } 863 864 if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_2_06, 865 0, spapr->max_compat_pvr)) { 866 caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_OFF; 867 caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_OFF; 868 caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 869 } 870 871 /* This is for pseries-2.12 and older */ 872 if (smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] == 0) { 873 uint8_t mps; 874 875 if (kvmppc_hpt_needs_host_contiguous_pages()) { 876 mps = ctz64(qemu_minrampagesize()); 877 } else { 878 mps = 34; /* allow everything up to 16GiB, i.e. everything */ 879 } 880 881 caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = mps; 882 } 883 884 return caps; 885 } 886 887 int spapr_caps_pre_load(void *opaque) 888 { 889 SpaprMachineState *spapr = opaque; 890 891 /* Set to default so we can tell if this came in with the migration */ 892 spapr->mig = spapr->def; 893 return 0; 894 } 895 896 int spapr_caps_pre_save(void *opaque) 897 { 898 SpaprMachineState *spapr = opaque; 899 900 spapr->mig = spapr->eff; 901 return 0; 902 } 903 904 /* This has to be called from the top-level spapr post_load, not the 905 * caps specific one. Otherwise it wouldn't be called when the source 906 * caps are all defaults, which could still conflict with overridden 907 * caps on the destination */ 908 int spapr_caps_post_migration(SpaprMachineState *spapr) 909 { 910 int i; 911 bool ok = true; 912 SpaprCapabilities dstcaps = spapr->eff; 913 SpaprCapabilities srccaps; 914 915 srccaps = default_caps_with_cpu(spapr, MACHINE(spapr)->cpu_type); 916 for (i = 0; i < SPAPR_CAP_NUM; i++) { 917 /* If not default value then assume came in with the migration */ 918 if (spapr->mig.caps[i] != spapr->def.caps[i]) { 919 srccaps.caps[i] = spapr->mig.caps[i]; 920 } 921 } 922 923 for (i = 0; i < SPAPR_CAP_NUM; i++) { 924 SpaprCapabilityInfo *info = &capability_table[i]; 925 926 if (srccaps.caps[i] > dstcaps.caps[i]) { 927 error_report("cap-%s higher level (%d) in incoming stream than on destination (%d)", 928 info->name, srccaps.caps[i], dstcaps.caps[i]); 929 ok = false; 930 } 931 932 if (srccaps.caps[i] < dstcaps.caps[i]) { 933 warn_report("cap-%s lower level (%d) in incoming stream than on destination (%d)", 934 info->name, srccaps.caps[i], dstcaps.caps[i]); 935 } 936 } 937 938 return ok ? 0 : -EINVAL; 939 } 940 941 /* Used to generate the migration field and needed function for a spapr cap */ 942 #define SPAPR_CAP_MIG_STATE(sname, cap) \ 943 static bool spapr_cap_##sname##_needed(void *opaque) \ 944 { \ 945 SpaprMachineState *spapr = opaque; \ 946 bool (*needed)(void *opaque) = \ 947 capability_table[cap].migrate_needed; \ 948 \ 949 return needed ? needed(opaque) : true && \ 950 spapr->cmd_line_caps[cap] && \ 951 (spapr->eff.caps[cap] != \ 952 spapr->def.caps[cap]); \ 953 } \ 954 \ 955 const VMStateDescription vmstate_spapr_cap_##sname = { \ 956 .name = "spapr/cap/" #sname, \ 957 .version_id = 1, \ 958 .minimum_version_id = 1, \ 959 .needed = spapr_cap_##sname##_needed, \ 960 .fields = (const VMStateField[]) { \ 961 VMSTATE_UINT8(mig.caps[cap], \ 962 SpaprMachineState), \ 963 VMSTATE_END_OF_LIST() \ 964 }, \ 965 } 966 967 SPAPR_CAP_MIG_STATE(htm, SPAPR_CAP_HTM); 968 SPAPR_CAP_MIG_STATE(vsx, SPAPR_CAP_VSX); 969 SPAPR_CAP_MIG_STATE(dfp, SPAPR_CAP_DFP); 970 SPAPR_CAP_MIG_STATE(cfpc, SPAPR_CAP_CFPC); 971 SPAPR_CAP_MIG_STATE(sbbc, SPAPR_CAP_SBBC); 972 SPAPR_CAP_MIG_STATE(ibs, SPAPR_CAP_IBS); 973 SPAPR_CAP_MIG_STATE(hpt_maxpagesize, SPAPR_CAP_HPT_MAXPAGESIZE); 974 SPAPR_CAP_MIG_STATE(nested_kvm_hv, SPAPR_CAP_NESTED_KVM_HV); 975 SPAPR_CAP_MIG_STATE(nested_papr, SPAPR_CAP_NESTED_PAPR); 976 SPAPR_CAP_MIG_STATE(large_decr, SPAPR_CAP_LARGE_DECREMENTER); 977 SPAPR_CAP_MIG_STATE(ccf_assist, SPAPR_CAP_CCF_ASSIST); 978 SPAPR_CAP_MIG_STATE(fwnmi, SPAPR_CAP_FWNMI); 979 SPAPR_CAP_MIG_STATE(rpt_invalidate, SPAPR_CAP_RPT_INVALIDATE); 980 981 void spapr_caps_init(SpaprMachineState *spapr) 982 { 983 SpaprCapabilities default_caps; 984 int i; 985 986 /* Compute the actual set of caps we should run with */ 987 default_caps = default_caps_with_cpu(spapr, MACHINE(spapr)->cpu_type); 988 989 for (i = 0; i < SPAPR_CAP_NUM; i++) { 990 /* Store the defaults */ 991 spapr->def.caps[i] = default_caps.caps[i]; 992 /* If not set on the command line then apply the default value */ 993 if (!spapr->cmd_line_caps[i]) { 994 spapr->eff.caps[i] = default_caps.caps[i]; 995 } 996 } 997 } 998 999 void spapr_caps_apply(SpaprMachineState *spapr) 1000 { 1001 int i; 1002 1003 for (i = 0; i < SPAPR_CAP_NUM; i++) { 1004 SpaprCapabilityInfo *info = &capability_table[i]; 1005 1006 /* 1007 * If the apply function can't set the desired level and thinks it's 1008 * fatal, it should cause that. 1009 */ 1010 info->apply(spapr, spapr->eff.caps[i], &error_fatal); 1011 } 1012 } 1013 1014 void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu) 1015 { 1016 int i; 1017 1018 for (i = 0; i < SPAPR_CAP_NUM; i++) { 1019 SpaprCapabilityInfo *info = &capability_table[i]; 1020 1021 /* 1022 * If the apply function can't set the desired level and thinks it's 1023 * fatal, it should cause that. 1024 */ 1025 if (info->cpu_apply) { 1026 info->cpu_apply(spapr, cpu, spapr->eff.caps[i], &error_fatal); 1027 } 1028 } 1029 } 1030 1031 void spapr_caps_add_properties(SpaprMachineClass *smc) 1032 { 1033 ObjectClass *klass = OBJECT_CLASS(smc); 1034 int i; 1035 1036 for (i = 0; i < ARRAY_SIZE(capability_table); i++) { 1037 SpaprCapabilityInfo *cap = &capability_table[i]; 1038 g_autofree char *name = g_strdup_printf("cap-%s", cap->name); 1039 g_autofree char *desc = g_strdup_printf("%s", cap->description); 1040 1041 object_class_property_add(klass, name, cap->type, 1042 cap->get, cap->set, 1043 NULL, cap); 1044 1045 object_class_property_set_description(klass, name, desc); 1046 } 1047 } 1048