1 /* 2 * QEMU PowerPC pSeries Logical Partition capabilities handling 3 * 4 * Copyright (c) 2017 David Gibson, Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/error-report.h" 27 #include "qapi/error.h" 28 #include "qapi/visitor.h" 29 #include "sysemu/hw_accel.h" 30 #include "exec/ram_addr.h" 31 #include "target/ppc/cpu.h" 32 #include "target/ppc/mmu-hash64.h" 33 #include "cpu-models.h" 34 #include "kvm_ppc.h" 35 #include "migration/vmstate.h" 36 #include "sysemu/tcg.h" 37 38 #include "hw/ppc/spapr.h" 39 40 typedef struct SpaprCapPossible { 41 int num; /* size of vals array below */ 42 const char *help; /* help text for vals */ 43 /* 44 * Note: 45 * - because of the way compatibility is determined vals MUST be ordered 46 * such that later options are a superset of all preceding options. 47 * - the order of vals must be preserved, that is their index is important, 48 * however vals may be added to the end of the list so long as the above 49 * point is observed 50 */ 51 const char *vals[]; 52 } SpaprCapPossible; 53 54 typedef struct SpaprCapabilityInfo { 55 const char *name; 56 const char *description; 57 int index; 58 59 /* Getter and Setter Function Pointers */ 60 ObjectPropertyAccessor *get; 61 ObjectPropertyAccessor *set; 62 const char *type; 63 /* Possible values if this is a custom string type */ 64 SpaprCapPossible *possible; 65 /* Make sure the virtual hardware can support this capability */ 66 void (*apply)(SpaprMachineState *spapr, uint8_t val, Error **errp); 67 void (*cpu_apply)(SpaprMachineState *spapr, PowerPCCPU *cpu, 68 uint8_t val, Error **errp); 69 bool (*migrate_needed)(void *opaque); 70 } SpaprCapabilityInfo; 71 72 static void spapr_cap_get_bool(Object *obj, Visitor *v, const char *name, 73 void *opaque, Error **errp) 74 { 75 SpaprCapabilityInfo *cap = opaque; 76 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 77 bool value = spapr_get_cap(spapr, cap->index) == SPAPR_CAP_ON; 78 79 visit_type_bool(v, name, &value, errp); 80 } 81 82 static void spapr_cap_set_bool(Object *obj, Visitor *v, const char *name, 83 void *opaque, Error **errp) 84 { 85 SpaprCapabilityInfo *cap = opaque; 86 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 87 bool value; 88 89 if (!visit_type_bool(v, name, &value, errp)) { 90 return; 91 } 92 93 spapr->cmd_line_caps[cap->index] = true; 94 spapr->eff.caps[cap->index] = value ? SPAPR_CAP_ON : SPAPR_CAP_OFF; 95 } 96 97 98 static void spapr_cap_get_string(Object *obj, Visitor *v, const char *name, 99 void *opaque, Error **errp) 100 { 101 SpaprCapabilityInfo *cap = opaque; 102 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 103 g_autofree char *val = NULL; 104 uint8_t value = spapr_get_cap(spapr, cap->index); 105 106 if (value >= cap->possible->num) { 107 error_setg(errp, "Invalid value (%d) for cap-%s", value, cap->name); 108 return; 109 } 110 111 val = g_strdup(cap->possible->vals[value]); 112 113 visit_type_str(v, name, &val, errp); 114 } 115 116 static void spapr_cap_set_string(Object *obj, Visitor *v, const char *name, 117 void *opaque, Error **errp) 118 { 119 SpaprCapabilityInfo *cap = opaque; 120 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 121 uint8_t i; 122 g_autofree char *val = NULL; 123 124 if (!visit_type_str(v, name, &val, errp)) { 125 return; 126 } 127 128 if (!strcmp(val, "?")) { 129 error_setg(errp, "%s", cap->possible->help); 130 return; 131 } 132 for (i = 0; i < cap->possible->num; i++) { 133 if (!strcasecmp(val, cap->possible->vals[i])) { 134 spapr->cmd_line_caps[cap->index] = true; 135 spapr->eff.caps[cap->index] = i; 136 return; 137 } 138 } 139 140 error_setg(errp, "Invalid capability mode \"%s\" for cap-%s", val, 141 cap->name); 142 } 143 144 static void spapr_cap_get_pagesize(Object *obj, Visitor *v, const char *name, 145 void *opaque, Error **errp) 146 { 147 SpaprCapabilityInfo *cap = opaque; 148 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 149 uint8_t val = spapr_get_cap(spapr, cap->index); 150 uint64_t pagesize = (1ULL << val); 151 152 visit_type_size(v, name, &pagesize, errp); 153 } 154 155 static void spapr_cap_set_pagesize(Object *obj, Visitor *v, const char *name, 156 void *opaque, Error **errp) 157 { 158 SpaprCapabilityInfo *cap = opaque; 159 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 160 uint64_t pagesize; 161 uint8_t val; 162 163 if (!visit_type_size(v, name, &pagesize, errp)) { 164 return; 165 } 166 167 if (!is_power_of_2(pagesize)) { 168 error_setg(errp, "cap-%s must be a power of 2", cap->name); 169 return; 170 } 171 172 val = ctz64(pagesize); 173 spapr->cmd_line_caps[cap->index] = true; 174 spapr->eff.caps[cap->index] = val; 175 } 176 177 static void cap_htm_apply(SpaprMachineState *spapr, uint8_t val, Error **errp) 178 { 179 ERRP_GUARD(); 180 if (!val) { 181 /* TODO: We don't support disabling htm yet */ 182 return; 183 } 184 if (tcg_enabled()) { 185 error_setg(errp, "No Transactional Memory support in TCG"); 186 error_append_hint(errp, "Try appending -machine cap-htm=off\n"); 187 } else if (kvm_enabled() && !kvmppc_has_cap_htm()) { 188 error_setg(errp, 189 "KVM implementation does not support Transactional Memory"); 190 error_append_hint(errp, "Try appending -machine cap-htm=off\n"); 191 } 192 } 193 194 static void cap_vsx_apply(SpaprMachineState *spapr, uint8_t val, Error **errp) 195 { 196 ERRP_GUARD(); 197 CPUPPCState *env = cpu_env(first_cpu); 198 199 if (!val) { 200 /* TODO: We don't support disabling vsx yet */ 201 return; 202 } 203 /* Allowable CPUs in spapr_cpu_core.c should already have gotten 204 * rid of anything that doesn't do VMX */ 205 g_assert(env->insns_flags & PPC_ALTIVEC); 206 if (!(env->insns_flags2 & PPC2_VSX)) { 207 error_setg(errp, "VSX support not available"); 208 error_append_hint(errp, "Try appending -machine cap-vsx=off\n"); 209 } 210 } 211 212 static void cap_dfp_apply(SpaprMachineState *spapr, uint8_t val, Error **errp) 213 { 214 ERRP_GUARD(); 215 216 if (!val) { 217 /* TODO: We don't support disabling dfp yet */ 218 return; 219 } 220 if (!(cpu_env(first_cpu)->insns_flags2 & PPC2_DFP)) { 221 error_setg(errp, "DFP support not available"); 222 error_append_hint(errp, "Try appending -machine cap-dfp=off\n"); 223 } 224 } 225 226 SpaprCapPossible cap_cfpc_possible = { 227 .num = 3, 228 .vals = {"broken", "workaround", "fixed"}, 229 .help = "broken - no protection, workaround - workaround available," 230 " fixed - fixed in hardware", 231 }; 232 233 static void cap_safe_cache_apply(SpaprMachineState *spapr, uint8_t val, 234 Error **errp) 235 { 236 ERRP_GUARD(); 237 uint8_t kvm_val = kvmppc_get_cap_safe_cache(); 238 239 if (tcg_enabled() && val) { 240 /* TCG only supports broken, allow other values and print a warning */ 241 warn_report("TCG doesn't support requested feature, cap-cfpc=%s", 242 cap_cfpc_possible.vals[val]); 243 } else if (kvm_enabled() && (val > kvm_val)) { 244 error_setg(errp, 245 "Requested safe cache capability level not supported by KVM"); 246 error_append_hint(errp, "Try appending -machine cap-cfpc=%s\n", 247 cap_cfpc_possible.vals[kvm_val]); 248 } 249 } 250 251 SpaprCapPossible cap_sbbc_possible = { 252 .num = 3, 253 .vals = {"broken", "workaround", "fixed"}, 254 .help = "broken - no protection, workaround - workaround available," 255 " fixed - fixed in hardware", 256 }; 257 258 static void cap_safe_bounds_check_apply(SpaprMachineState *spapr, uint8_t val, 259 Error **errp) 260 { 261 ERRP_GUARD(); 262 uint8_t kvm_val = kvmppc_get_cap_safe_bounds_check(); 263 264 if (tcg_enabled() && val) { 265 /* TCG only supports broken, allow other values and print a warning */ 266 warn_report("TCG doesn't support requested feature, cap-sbbc=%s", 267 cap_sbbc_possible.vals[val]); 268 } else if (kvm_enabled() && (val > kvm_val)) { 269 error_setg(errp, 270 "Requested safe bounds check capability level not supported by KVM"); 271 error_append_hint(errp, "Try appending -machine cap-sbbc=%s\n", 272 cap_sbbc_possible.vals[kvm_val]); 273 } 274 } 275 276 SpaprCapPossible cap_ibs_possible = { 277 .num = 5, 278 /* Note workaround only maintained for compatibility */ 279 .vals = {"broken", "workaround", "fixed-ibs", "fixed-ccd", "fixed-na"}, 280 .help = "broken - no protection, workaround - count cache flush" 281 ", fixed-ibs - indirect branch serialisation," 282 " fixed-ccd - cache count disabled," 283 " fixed-na - fixed in hardware (no longer applicable)", 284 }; 285 286 static void cap_safe_indirect_branch_apply(SpaprMachineState *spapr, 287 uint8_t val, Error **errp) 288 { 289 ERRP_GUARD(); 290 uint8_t kvm_val = kvmppc_get_cap_safe_indirect_branch(); 291 292 if (tcg_enabled() && val) { 293 /* TCG only supports broken, allow other values and print a warning */ 294 warn_report("TCG doesn't support requested feature, cap-ibs=%s", 295 cap_ibs_possible.vals[val]); 296 } else if (kvm_enabled() && (val > kvm_val)) { 297 error_setg(errp, 298 "Requested safe indirect branch capability level not supported by KVM"); 299 error_append_hint(errp, "Try appending -machine cap-ibs=%s\n", 300 cap_ibs_possible.vals[kvm_val]); 301 } 302 } 303 304 #define VALUE_DESC_TRISTATE " (broken, workaround, fixed)" 305 306 bool spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, 307 Error **errp) 308 { 309 hwaddr maxpagesize = (1ULL << spapr->eff.caps[SPAPR_CAP_HPT_MAXPAGESIZE]); 310 311 if (!kvmppc_hpt_needs_host_contiguous_pages()) { 312 return true; 313 } 314 315 if (maxpagesize > pagesize) { 316 error_setg(errp, 317 "Can't support %"HWADDR_PRIu" kiB guest pages with %" 318 HWADDR_PRIu" kiB host pages with this KVM implementation", 319 maxpagesize >> 10, pagesize >> 10); 320 return false; 321 } 322 323 return true; 324 } 325 326 static void cap_hpt_maxpagesize_apply(SpaprMachineState *spapr, 327 uint8_t val, Error **errp) 328 { 329 if (val < 12) { 330 error_setg(errp, "Require at least 4kiB hpt-max-page-size"); 331 return; 332 } else if (val < 16) { 333 warn_report("Many guests require at least 64kiB hpt-max-page-size"); 334 } 335 336 spapr_check_pagesize(spapr, qemu_minrampagesize(), errp); 337 } 338 339 static bool cap_hpt_maxpagesize_migrate_needed(void *opaque) 340 { 341 return !SPAPR_MACHINE_GET_CLASS(opaque)->pre_4_1_migration; 342 } 343 344 static bool spapr_pagesize_cb(void *opaque, uint32_t seg_pshift, 345 uint32_t pshift) 346 { 347 unsigned maxshift = *((unsigned *)opaque); 348 349 assert(pshift >= seg_pshift); 350 351 /* Don't allow the guest to use pages bigger than the configured 352 * maximum size */ 353 if (pshift > maxshift) { 354 return false; 355 } 356 357 /* For whatever reason, KVM doesn't allow multiple pagesizes 358 * within a segment, *except* for the case of 16M pages in a 4k or 359 * 64k segment. Always exclude other cases, so that TCG and KVM 360 * guests see a consistent environment */ 361 if ((pshift != seg_pshift) && (pshift != 24)) { 362 return false; 363 } 364 365 return true; 366 } 367 368 static void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu, 369 bool (*cb)(void *, uint32_t, uint32_t), 370 void *opaque) 371 { 372 PPCHash64Options *opts = cpu->hash64_opts; 373 int i; 374 int n = 0; 375 bool ci_largepage = false; 376 377 assert(opts); 378 379 n = 0; 380 for (i = 0; i < ARRAY_SIZE(opts->sps); i++) { 381 PPCHash64SegmentPageSizes *sps = &opts->sps[i]; 382 int j; 383 int m = 0; 384 385 assert(n <= i); 386 387 if (!sps->page_shift) { 388 break; 389 } 390 391 for (j = 0; j < ARRAY_SIZE(sps->enc); j++) { 392 PPCHash64PageSize *ps = &sps->enc[j]; 393 394 assert(m <= j); 395 if (!ps->page_shift) { 396 break; 397 } 398 399 if (cb(opaque, sps->page_shift, ps->page_shift)) { 400 if (ps->page_shift >= 16) { 401 ci_largepage = true; 402 } 403 sps->enc[m++] = *ps; 404 } 405 } 406 407 /* Clear rest of the row */ 408 for (j = m; j < ARRAY_SIZE(sps->enc); j++) { 409 memset(&sps->enc[j], 0, sizeof(sps->enc[j])); 410 } 411 412 if (m) { 413 n++; 414 } 415 } 416 417 /* Clear the rest of the table */ 418 for (i = n; i < ARRAY_SIZE(opts->sps); i++) { 419 memset(&opts->sps[i], 0, sizeof(opts->sps[i])); 420 } 421 422 if (!ci_largepage) { 423 opts->flags &= ~PPC_HASH64_CI_LARGEPAGE; 424 } 425 } 426 427 static void cap_hpt_maxpagesize_cpu_apply(SpaprMachineState *spapr, 428 PowerPCCPU *cpu, 429 uint8_t val, Error **errp) 430 { 431 unsigned maxshift = val; 432 433 ppc_hash64_filter_pagesizes(cpu, spapr_pagesize_cb, &maxshift); 434 } 435 436 static void cap_nested_kvm_hv_apply(SpaprMachineState *spapr, 437 uint8_t val, Error **errp) 438 { 439 ERRP_GUARD(); 440 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 441 CPUPPCState *env = &cpu->env; 442 443 if (!val) { 444 /* capability disabled by default */ 445 return; 446 } 447 448 if (!(env->insns_flags2 & PPC2_ISA300)) { 449 error_setg(errp, "Nested-HV only supported on POWER9 and later"); 450 error_append_hint(errp, "Try appending -machine cap-nested-hv=off\n"); 451 return; 452 } 453 454 if (kvm_enabled()) { 455 if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, 456 spapr->max_compat_pvr)) { 457 error_setg(errp, "Nested-HV only supported on POWER9 and later"); 458 error_append_hint(errp, 459 "Try appending -machine max-cpu-compat=power9\n"); 460 return; 461 } 462 463 if (!kvmppc_has_cap_nested_kvm_hv()) { 464 error_setg(errp, 465 "KVM implementation does not support Nested-HV"); 466 error_append_hint(errp, 467 "Try appending -machine cap-nested-hv=off\n"); 468 } else if (kvmppc_set_cap_nested_kvm_hv(val) < 0) { 469 error_setg(errp, "Error enabling cap-nested-hv with KVM"); 470 error_append_hint(errp, 471 "Try appending -machine cap-nested-hv=off\n"); 472 } 473 } else if (tcg_enabled()) { 474 MachineState *ms = MACHINE(spapr); 475 unsigned int smp_threads = ms->smp.threads; 476 477 /* 478 * Nested-HV vCPU env state to L2, so SMT-shared SPR updates, for 479 * example, do not necessarily update the correct SPR value on sibling 480 * threads that are in a different guest/host context. 481 */ 482 if (smp_threads > 1) { 483 error_setg(errp, "TCG does not support nested-HV with SMT"); 484 error_append_hint(errp, "Try appending -machine cap-nested-hv=off " 485 "or use threads=1 with -smp\n"); 486 } 487 } 488 } 489 490 static void cap_large_decr_apply(SpaprMachineState *spapr, 491 uint8_t val, Error **errp) 492 { 493 ERRP_GUARD(); 494 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 495 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 496 497 if (!val) { 498 return; /* Disabled by default */ 499 } 500 501 if (tcg_enabled()) { 502 if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, 503 spapr->max_compat_pvr)) { 504 error_setg(errp, "Large decrementer only supported on POWER9"); 505 error_append_hint(errp, "Try -cpu POWER9\n"); 506 return; 507 } 508 } else if (kvm_enabled()) { 509 int kvm_nr_bits = kvmppc_get_cap_large_decr(); 510 511 if (!kvm_nr_bits) { 512 error_setg(errp, "No large decrementer support"); 513 error_append_hint(errp, 514 "Try appending -machine cap-large-decr=off\n"); 515 } else if (pcc->lrg_decr_bits != kvm_nr_bits) { 516 error_setg(errp, 517 "KVM large decrementer size (%d) differs to model (%d)", 518 kvm_nr_bits, pcc->lrg_decr_bits); 519 error_append_hint(errp, 520 "Try appending -machine cap-large-decr=off\n"); 521 } 522 } 523 } 524 525 static void cap_large_decr_cpu_apply(SpaprMachineState *spapr, 526 PowerPCCPU *cpu, 527 uint8_t val, Error **errp) 528 { 529 ERRP_GUARD(); 530 CPUPPCState *env = &cpu->env; 531 target_ulong lpcr = env->spr[SPR_LPCR]; 532 533 if (kvm_enabled()) { 534 if (kvmppc_enable_cap_large_decr(cpu, val)) { 535 error_setg(errp, "No large decrementer support"); 536 error_append_hint(errp, 537 "Try appending -machine cap-large-decr=off\n"); 538 } 539 } 540 541 if (val) { 542 lpcr |= LPCR_LD; 543 } else { 544 lpcr &= ~LPCR_LD; 545 } 546 ppc_store_lpcr(cpu, lpcr); 547 } 548 549 static void cap_ccf_assist_apply(SpaprMachineState *spapr, uint8_t val, 550 Error **errp) 551 { 552 ERRP_GUARD(); 553 uint8_t kvm_val = kvmppc_get_cap_count_cache_flush_assist(); 554 555 if (tcg_enabled() && val) { 556 /* TCG doesn't implement anything here, but allow with a warning */ 557 warn_report("TCG doesn't support requested feature, cap-ccf-assist=on"); 558 } else if (kvm_enabled() && (val > kvm_val)) { 559 uint8_t kvm_ibs = kvmppc_get_cap_safe_indirect_branch(); 560 561 if (kvm_ibs == SPAPR_CAP_FIXED_CCD) { 562 /* 563 * If we don't have CCF assist on the host, the assist 564 * instruction is a harmless no-op. It won't correctly 565 * implement the cache count flush *but* if we have 566 * count-cache-disabled in the host, that flush is 567 * unnecessary. So, specifically allow this case. This 568 * allows us to have better performance on POWER9 DD2.3, 569 * while still working on POWER9 DD2.2 and POWER8 host 570 * cpus. 571 */ 572 return; 573 } 574 error_setg(errp, 575 "Requested count cache flush assist capability level not supported by KVM"); 576 error_append_hint(errp, "Try appending -machine cap-ccf-assist=off\n"); 577 } 578 } 579 580 static void cap_fwnmi_apply(SpaprMachineState *spapr, uint8_t val, 581 Error **errp) 582 { 583 ERRP_GUARD(); 584 if (!val) { 585 return; /* Disabled by default */ 586 } 587 588 if (kvm_enabled()) { 589 if (!kvmppc_get_fwnmi()) { 590 error_setg(errp, 591 "Firmware Assisted Non-Maskable Interrupts(FWNMI) not supported by KVM."); 592 error_append_hint(errp, "Try appending -machine cap-fwnmi=off\n"); 593 } 594 } 595 } 596 597 static void cap_rpt_invalidate_apply(SpaprMachineState *spapr, 598 uint8_t val, Error **errp) 599 { 600 ERRP_GUARD(); 601 602 if (!val) { 603 /* capability disabled by default */ 604 return; 605 } 606 607 if (tcg_enabled()) { 608 error_setg(errp, "No H_RPT_INVALIDATE support in TCG"); 609 error_append_hint(errp, 610 "Try appending -machine cap-rpt-invalidate=off\n"); 611 } else if (kvm_enabled()) { 612 if (!kvmppc_has_cap_mmu_radix()) { 613 error_setg(errp, "H_RPT_INVALIDATE only supported on Radix"); 614 return; 615 } 616 617 if (!kvmppc_has_cap_rpt_invalidate()) { 618 error_setg(errp, 619 "KVM implementation does not support H_RPT_INVALIDATE"); 620 error_append_hint(errp, 621 "Try appending -machine cap-rpt-invalidate=off\n"); 622 } else { 623 kvmppc_enable_h_rpt_invalidate(); 624 } 625 } 626 } 627 628 static void cap_ail_mode_3_apply(SpaprMachineState *spapr, 629 uint8_t val, Error **errp) 630 { 631 ERRP_GUARD(); 632 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 633 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 634 635 if (!val) { 636 return; 637 } 638 639 if (tcg_enabled()) { 640 /* AIL-3 is only supported on POWER8 and above CPUs. */ 641 if (!(pcc->insns_flags2 & PPC2_ISA207S)) { 642 error_setg(errp, "TCG only supports cap-ail-mode-3 on POWER8 and later CPUs"); 643 error_append_hint(errp, "Try appending -machine cap-ail-mode-3=off\n"); 644 return; 645 } 646 } else if (kvm_enabled()) { 647 if (!kvmppc_supports_ail_3()) { 648 error_setg(errp, "KVM implementation does not support cap-ail-mode-3"); 649 error_append_hint(errp, "Try appending -machine cap-ail-mode-3=off\n"); 650 return; 651 } 652 } 653 } 654 655 SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] = { 656 [SPAPR_CAP_HTM] = { 657 .name = "htm", 658 .description = "Allow Hardware Transactional Memory (HTM)", 659 .index = SPAPR_CAP_HTM, 660 .get = spapr_cap_get_bool, 661 .set = spapr_cap_set_bool, 662 .type = "bool", 663 .apply = cap_htm_apply, 664 }, 665 [SPAPR_CAP_VSX] = { 666 .name = "vsx", 667 .description = "Allow Vector Scalar Extensions (VSX)", 668 .index = SPAPR_CAP_VSX, 669 .get = spapr_cap_get_bool, 670 .set = spapr_cap_set_bool, 671 .type = "bool", 672 .apply = cap_vsx_apply, 673 }, 674 [SPAPR_CAP_DFP] = { 675 .name = "dfp", 676 .description = "Allow Decimal Floating Point (DFP)", 677 .index = SPAPR_CAP_DFP, 678 .get = spapr_cap_get_bool, 679 .set = spapr_cap_set_bool, 680 .type = "bool", 681 .apply = cap_dfp_apply, 682 }, 683 [SPAPR_CAP_CFPC] = { 684 .name = "cfpc", 685 .description = "Cache Flush on Privilege Change" VALUE_DESC_TRISTATE, 686 .index = SPAPR_CAP_CFPC, 687 .get = spapr_cap_get_string, 688 .set = spapr_cap_set_string, 689 .type = "string", 690 .possible = &cap_cfpc_possible, 691 .apply = cap_safe_cache_apply, 692 }, 693 [SPAPR_CAP_SBBC] = { 694 .name = "sbbc", 695 .description = "Speculation Barrier Bounds Checking" VALUE_DESC_TRISTATE, 696 .index = SPAPR_CAP_SBBC, 697 .get = spapr_cap_get_string, 698 .set = spapr_cap_set_string, 699 .type = "string", 700 .possible = &cap_sbbc_possible, 701 .apply = cap_safe_bounds_check_apply, 702 }, 703 [SPAPR_CAP_IBS] = { 704 .name = "ibs", 705 .description = 706 "Indirect Branch Speculation (broken, workaround, fixed-ibs," 707 "fixed-ccd, fixed-na)", 708 .index = SPAPR_CAP_IBS, 709 .get = spapr_cap_get_string, 710 .set = spapr_cap_set_string, 711 .type = "string", 712 .possible = &cap_ibs_possible, 713 .apply = cap_safe_indirect_branch_apply, 714 }, 715 [SPAPR_CAP_HPT_MAXPAGESIZE] = { 716 .name = "hpt-max-page-size", 717 .description = "Maximum page size for Hash Page Table guests", 718 .index = SPAPR_CAP_HPT_MAXPAGESIZE, 719 .get = spapr_cap_get_pagesize, 720 .set = spapr_cap_set_pagesize, 721 .type = "int", 722 .apply = cap_hpt_maxpagesize_apply, 723 .cpu_apply = cap_hpt_maxpagesize_cpu_apply, 724 .migrate_needed = cap_hpt_maxpagesize_migrate_needed, 725 }, 726 [SPAPR_CAP_NESTED_KVM_HV] = { 727 .name = "nested-hv", 728 .description = "Allow Nested KVM-HV", 729 .index = SPAPR_CAP_NESTED_KVM_HV, 730 .get = spapr_cap_get_bool, 731 .set = spapr_cap_set_bool, 732 .type = "bool", 733 .apply = cap_nested_kvm_hv_apply, 734 }, 735 [SPAPR_CAP_LARGE_DECREMENTER] = { 736 .name = "large-decr", 737 .description = "Allow Large Decrementer", 738 .index = SPAPR_CAP_LARGE_DECREMENTER, 739 .get = spapr_cap_get_bool, 740 .set = spapr_cap_set_bool, 741 .type = "bool", 742 .apply = cap_large_decr_apply, 743 .cpu_apply = cap_large_decr_cpu_apply, 744 }, 745 [SPAPR_CAP_CCF_ASSIST] = { 746 .name = "ccf-assist", 747 .description = "Count Cache Flush Assist via HW Instruction", 748 .index = SPAPR_CAP_CCF_ASSIST, 749 .get = spapr_cap_get_bool, 750 .set = spapr_cap_set_bool, 751 .type = "bool", 752 .apply = cap_ccf_assist_apply, 753 }, 754 [SPAPR_CAP_FWNMI] = { 755 .name = "fwnmi", 756 .description = "Implements PAPR FWNMI option", 757 .index = SPAPR_CAP_FWNMI, 758 .get = spapr_cap_get_bool, 759 .set = spapr_cap_set_bool, 760 .type = "bool", 761 .apply = cap_fwnmi_apply, 762 }, 763 [SPAPR_CAP_RPT_INVALIDATE] = { 764 .name = "rpt-invalidate", 765 .description = "Allow H_RPT_INVALIDATE", 766 .index = SPAPR_CAP_RPT_INVALIDATE, 767 .get = spapr_cap_get_bool, 768 .set = spapr_cap_set_bool, 769 .type = "bool", 770 .apply = cap_rpt_invalidate_apply, 771 }, 772 [SPAPR_CAP_AIL_MODE_3] = { 773 .name = "ail-mode-3", 774 .description = "Alternate Interrupt Location (AIL) mode 3 support", 775 .index = SPAPR_CAP_AIL_MODE_3, 776 .get = spapr_cap_get_bool, 777 .set = spapr_cap_set_bool, 778 .type = "bool", 779 .apply = cap_ail_mode_3_apply, 780 }, 781 }; 782 783 static SpaprCapabilities default_caps_with_cpu(SpaprMachineState *spapr, 784 const char *cputype) 785 { 786 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 787 SpaprCapabilities caps; 788 789 caps = smc->default_caps; 790 791 if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_3_00, 792 0, spapr->max_compat_pvr)) { 793 caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 794 } 795 796 if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_2_07, 797 0, spapr->max_compat_pvr)) { 798 caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 799 caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 800 caps.caps[SPAPR_CAP_AIL_MODE_3] = SPAPR_CAP_OFF; 801 } 802 803 if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_2_06_PLUS, 804 0, spapr->max_compat_pvr)) { 805 caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 806 } 807 808 if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_2_06, 809 0, spapr->max_compat_pvr)) { 810 caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_OFF; 811 caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_OFF; 812 caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 813 } 814 815 /* This is for pseries-2.12 and older */ 816 if (smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] == 0) { 817 uint8_t mps; 818 819 if (kvmppc_hpt_needs_host_contiguous_pages()) { 820 mps = ctz64(qemu_minrampagesize()); 821 } else { 822 mps = 34; /* allow everything up to 16GiB, i.e. everything */ 823 } 824 825 caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = mps; 826 } 827 828 return caps; 829 } 830 831 int spapr_caps_pre_load(void *opaque) 832 { 833 SpaprMachineState *spapr = opaque; 834 835 /* Set to default so we can tell if this came in with the migration */ 836 spapr->mig = spapr->def; 837 return 0; 838 } 839 840 int spapr_caps_pre_save(void *opaque) 841 { 842 SpaprMachineState *spapr = opaque; 843 844 spapr->mig = spapr->eff; 845 return 0; 846 } 847 848 /* This has to be called from the top-level spapr post_load, not the 849 * caps specific one. Otherwise it wouldn't be called when the source 850 * caps are all defaults, which could still conflict with overridden 851 * caps on the destination */ 852 int spapr_caps_post_migration(SpaprMachineState *spapr) 853 { 854 int i; 855 bool ok = true; 856 SpaprCapabilities dstcaps = spapr->eff; 857 SpaprCapabilities srccaps; 858 859 srccaps = default_caps_with_cpu(spapr, MACHINE(spapr)->cpu_type); 860 for (i = 0; i < SPAPR_CAP_NUM; i++) { 861 /* If not default value then assume came in with the migration */ 862 if (spapr->mig.caps[i] != spapr->def.caps[i]) { 863 srccaps.caps[i] = spapr->mig.caps[i]; 864 } 865 } 866 867 for (i = 0; i < SPAPR_CAP_NUM; i++) { 868 SpaprCapabilityInfo *info = &capability_table[i]; 869 870 if (srccaps.caps[i] > dstcaps.caps[i]) { 871 error_report("cap-%s higher level (%d) in incoming stream than on destination (%d)", 872 info->name, srccaps.caps[i], dstcaps.caps[i]); 873 ok = false; 874 } 875 876 if (srccaps.caps[i] < dstcaps.caps[i]) { 877 warn_report("cap-%s lower level (%d) in incoming stream than on destination (%d)", 878 info->name, srccaps.caps[i], dstcaps.caps[i]); 879 } 880 } 881 882 return ok ? 0 : -EINVAL; 883 } 884 885 /* Used to generate the migration field and needed function for a spapr cap */ 886 #define SPAPR_CAP_MIG_STATE(sname, cap) \ 887 static bool spapr_cap_##sname##_needed(void *opaque) \ 888 { \ 889 SpaprMachineState *spapr = opaque; \ 890 bool (*needed)(void *opaque) = \ 891 capability_table[cap].migrate_needed; \ 892 \ 893 return needed ? needed(opaque) : true && \ 894 spapr->cmd_line_caps[cap] && \ 895 (spapr->eff.caps[cap] != \ 896 spapr->def.caps[cap]); \ 897 } \ 898 \ 899 const VMStateDescription vmstate_spapr_cap_##sname = { \ 900 .name = "spapr/cap/" #sname, \ 901 .version_id = 1, \ 902 .minimum_version_id = 1, \ 903 .needed = spapr_cap_##sname##_needed, \ 904 .fields = (const VMStateField[]) { \ 905 VMSTATE_UINT8(mig.caps[cap], \ 906 SpaprMachineState), \ 907 VMSTATE_END_OF_LIST() \ 908 }, \ 909 } 910 911 SPAPR_CAP_MIG_STATE(htm, SPAPR_CAP_HTM); 912 SPAPR_CAP_MIG_STATE(vsx, SPAPR_CAP_VSX); 913 SPAPR_CAP_MIG_STATE(dfp, SPAPR_CAP_DFP); 914 SPAPR_CAP_MIG_STATE(cfpc, SPAPR_CAP_CFPC); 915 SPAPR_CAP_MIG_STATE(sbbc, SPAPR_CAP_SBBC); 916 SPAPR_CAP_MIG_STATE(ibs, SPAPR_CAP_IBS); 917 SPAPR_CAP_MIG_STATE(hpt_maxpagesize, SPAPR_CAP_HPT_MAXPAGESIZE); 918 SPAPR_CAP_MIG_STATE(nested_kvm_hv, SPAPR_CAP_NESTED_KVM_HV); 919 SPAPR_CAP_MIG_STATE(large_decr, SPAPR_CAP_LARGE_DECREMENTER); 920 SPAPR_CAP_MIG_STATE(ccf_assist, SPAPR_CAP_CCF_ASSIST); 921 SPAPR_CAP_MIG_STATE(fwnmi, SPAPR_CAP_FWNMI); 922 SPAPR_CAP_MIG_STATE(rpt_invalidate, SPAPR_CAP_RPT_INVALIDATE); 923 924 void spapr_caps_init(SpaprMachineState *spapr) 925 { 926 SpaprCapabilities default_caps; 927 int i; 928 929 /* Compute the actual set of caps we should run with */ 930 default_caps = default_caps_with_cpu(spapr, MACHINE(spapr)->cpu_type); 931 932 for (i = 0; i < SPAPR_CAP_NUM; i++) { 933 /* Store the defaults */ 934 spapr->def.caps[i] = default_caps.caps[i]; 935 /* If not set on the command line then apply the default value */ 936 if (!spapr->cmd_line_caps[i]) { 937 spapr->eff.caps[i] = default_caps.caps[i]; 938 } 939 } 940 } 941 942 void spapr_caps_apply(SpaprMachineState *spapr) 943 { 944 int i; 945 946 for (i = 0; i < SPAPR_CAP_NUM; i++) { 947 SpaprCapabilityInfo *info = &capability_table[i]; 948 949 /* 950 * If the apply function can't set the desired level and thinks it's 951 * fatal, it should cause that. 952 */ 953 info->apply(spapr, spapr->eff.caps[i], &error_fatal); 954 } 955 } 956 957 void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu) 958 { 959 int i; 960 961 for (i = 0; i < SPAPR_CAP_NUM; i++) { 962 SpaprCapabilityInfo *info = &capability_table[i]; 963 964 /* 965 * If the apply function can't set the desired level and thinks it's 966 * fatal, it should cause that. 967 */ 968 if (info->cpu_apply) { 969 info->cpu_apply(spapr, cpu, spapr->eff.caps[i], &error_fatal); 970 } 971 } 972 } 973 974 void spapr_caps_add_properties(SpaprMachineClass *smc) 975 { 976 ObjectClass *klass = OBJECT_CLASS(smc); 977 int i; 978 979 for (i = 0; i < ARRAY_SIZE(capability_table); i++) { 980 SpaprCapabilityInfo *cap = &capability_table[i]; 981 g_autofree char *name = g_strdup_printf("cap-%s", cap->name); 982 g_autofree char *desc = g_strdup_printf("%s", cap->description); 983 984 object_class_property_add(klass, name, cap->type, 985 cap->get, cap->set, 986 NULL, cap); 987 988 object_class_property_set_description(klass, name, desc); 989 } 990 } 991