1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qapi/error.h" 30 #include "qapi/visitor.h" 31 #include "sysemu/sysemu.h" 32 #include "sysemu/hostmem.h" 33 #include "sysemu/numa.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/reset.h" 36 #include "sysemu/runstate.h" 37 #include "qemu/log.h" 38 #include "hw/fw-path-provider.h" 39 #include "elf.h" 40 #include "net/net.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/cpus.h" 43 #include "sysemu/hw_accel.h" 44 #include "kvm_ppc.h" 45 #include "migration/misc.h" 46 #include "migration/qemu-file-types.h" 47 #include "migration/global_state.h" 48 #include "migration/register.h" 49 #include "migration/blocker.h" 50 #include "mmu-hash64.h" 51 #include "mmu-book3s-v3.h" 52 #include "cpu-models.h" 53 #include "hw/core/cpu.h" 54 55 #include "hw/boards.h" 56 #include "hw/ppc/ppc.h" 57 #include "hw/loader.h" 58 59 #include "hw/ppc/fdt.h" 60 #include "hw/ppc/spapr.h" 61 #include "hw/ppc/spapr_vio.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/pci-host/spapr.h" 64 #include "hw/pci/msi.h" 65 66 #include "hw/pci/pci.h" 67 #include "hw/scsi/scsi.h" 68 #include "hw/virtio/virtio-scsi.h" 69 #include "hw/virtio/vhost-scsi-common.h" 70 71 #include "exec/address-spaces.h" 72 #include "exec/ram_addr.h" 73 #include "hw/usb.h" 74 #include "qemu/config-file.h" 75 #include "qemu/error-report.h" 76 #include "trace.h" 77 #include "hw/nmi.h" 78 #include "hw/intc/intc.h" 79 80 #include "hw/ppc/spapr_cpu_core.h" 81 #include "hw/mem/memory-device.h" 82 #include "hw/ppc/spapr_tpm_proxy.h" 83 84 #include "monitor/monitor.h" 85 86 #include <libfdt.h> 87 88 /* SLOF memory layout: 89 * 90 * SLOF raw image loaded at 0, copies its romfs right below the flat 91 * device-tree, then position SLOF itself 31M below that 92 * 93 * So we set FW_OVERHEAD to 40MB which should account for all of that 94 * and more 95 * 96 * We load our kernel at 4M, leaving space for SLOF initial image 97 */ 98 #define FDT_MAX_SIZE 0x100000 99 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 100 #define FW_MAX_SIZE 0x400000 101 #define FW_FILE_NAME "slof.bin" 102 #define FW_OVERHEAD 0x2800000 103 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 104 105 #define MIN_RMA_SLOF 128UL 106 107 #define PHANDLE_INTC 0x00001111 108 109 /* These two functions implement the VCPU id numbering: one to compute them 110 * all and one to identify thread 0 of a VCORE. Any change to the first one 111 * is likely to have an impact on the second one, so let's keep them close. 112 */ 113 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 114 { 115 MachineState *ms = MACHINE(spapr); 116 unsigned int smp_threads = ms->smp.threads; 117 118 assert(spapr->vsmt); 119 return 120 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 121 } 122 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 123 PowerPCCPU *cpu) 124 { 125 assert(spapr->vsmt); 126 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 127 } 128 129 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 130 { 131 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 132 * and newer QEMUs don't even have them. In both cases, we don't want 133 * to send anything on the wire. 134 */ 135 return false; 136 } 137 138 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 139 .name = "icp/server", 140 .version_id = 1, 141 .minimum_version_id = 1, 142 .needed = pre_2_10_vmstate_dummy_icp_needed, 143 .fields = (VMStateField[]) { 144 VMSTATE_UNUSED(4), /* uint32_t xirr */ 145 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 146 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 147 VMSTATE_END_OF_LIST() 148 }, 149 }; 150 151 static void pre_2_10_vmstate_register_dummy_icp(int i) 152 { 153 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 154 (void *)(uintptr_t) i); 155 } 156 157 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 158 { 159 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 160 (void *)(uintptr_t) i); 161 } 162 163 int spapr_max_server_number(SpaprMachineState *spapr) 164 { 165 MachineState *ms = MACHINE(spapr); 166 167 assert(spapr->vsmt); 168 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 169 } 170 171 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 172 int smt_threads) 173 { 174 int i, ret = 0; 175 uint32_t servers_prop[smt_threads]; 176 uint32_t gservers_prop[smt_threads * 2]; 177 int index = spapr_get_vcpu_id(cpu); 178 179 if (cpu->compat_pvr) { 180 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 181 if (ret < 0) { 182 return ret; 183 } 184 } 185 186 /* Build interrupt servers and gservers properties */ 187 for (i = 0; i < smt_threads; i++) { 188 servers_prop[i] = cpu_to_be32(index + i); 189 /* Hack, direct the group queues back to cpu 0 */ 190 gservers_prop[i*2] = cpu_to_be32(index + i); 191 gservers_prop[i*2 + 1] = 0; 192 } 193 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 194 servers_prop, sizeof(servers_prop)); 195 if (ret < 0) { 196 return ret; 197 } 198 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 199 gservers_prop, sizeof(gservers_prop)); 200 201 return ret; 202 } 203 204 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 205 { 206 int index = spapr_get_vcpu_id(cpu); 207 uint32_t associativity[] = {cpu_to_be32(0x5), 208 cpu_to_be32(0x0), 209 cpu_to_be32(0x0), 210 cpu_to_be32(0x0), 211 cpu_to_be32(cpu->node_id), 212 cpu_to_be32(index)}; 213 214 /* Advertise NUMA via ibm,associativity */ 215 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 216 sizeof(associativity)); 217 } 218 219 /* Populate the "ibm,pa-features" property */ 220 static void spapr_populate_pa_features(SpaprMachineState *spapr, 221 PowerPCCPU *cpu, 222 void *fdt, int offset) 223 { 224 uint8_t pa_features_206[] = { 6, 0, 225 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 226 uint8_t pa_features_207[] = { 24, 0, 227 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 228 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 229 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 230 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 231 uint8_t pa_features_300[] = { 66, 0, 232 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 233 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 234 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 235 /* 6: DS207 */ 236 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 237 /* 16: Vector */ 238 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 239 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 240 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 241 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 242 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 243 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 244 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 245 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 246 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 247 /* 42: PM, 44: PC RA, 46: SC vec'd */ 248 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 249 /* 48: SIMD, 50: QP BFP, 52: String */ 250 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 251 /* 54: DecFP, 56: DecI, 58: SHA */ 252 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 253 /* 60: NM atomic, 62: RNG */ 254 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 255 }; 256 uint8_t *pa_features = NULL; 257 size_t pa_size; 258 259 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 260 pa_features = pa_features_206; 261 pa_size = sizeof(pa_features_206); 262 } 263 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 264 pa_features = pa_features_207; 265 pa_size = sizeof(pa_features_207); 266 } 267 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 268 pa_features = pa_features_300; 269 pa_size = sizeof(pa_features_300); 270 } 271 if (!pa_features) { 272 return; 273 } 274 275 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 276 /* 277 * Note: we keep CI large pages off by default because a 64K capable 278 * guest provisioned with large pages might otherwise try to map a qemu 279 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 280 * even if that qemu runs on a 4k host. 281 * We dd this bit back here if we are confident this is not an issue 282 */ 283 pa_features[3] |= 0x20; 284 } 285 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 286 pa_features[24] |= 0x80; /* Transactional memory support */ 287 } 288 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 289 /* Workaround for broken kernels that attempt (guest) radix 290 * mode when they can't handle it, if they see the radix bit set 291 * in pa-features. So hide it from them. */ 292 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 293 } 294 295 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 296 } 297 298 static hwaddr spapr_node0_size(MachineState *machine) 299 { 300 if (machine->numa_state->num_nodes) { 301 int i; 302 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 303 if (machine->numa_state->nodes[i].node_mem) { 304 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 305 machine->ram_size); 306 } 307 } 308 } 309 return machine->ram_size; 310 } 311 312 static void add_str(GString *s, const gchar *s1) 313 { 314 g_string_append_len(s, s1, strlen(s1) + 1); 315 } 316 317 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 318 hwaddr size) 319 { 320 uint32_t associativity[] = { 321 cpu_to_be32(0x4), /* length */ 322 cpu_to_be32(0x0), cpu_to_be32(0x0), 323 cpu_to_be32(0x0), cpu_to_be32(nodeid) 324 }; 325 char mem_name[32]; 326 uint64_t mem_reg_property[2]; 327 int off; 328 329 mem_reg_property[0] = cpu_to_be64(start); 330 mem_reg_property[1] = cpu_to_be64(size); 331 332 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 333 off = fdt_add_subnode(fdt, 0, mem_name); 334 _FDT(off); 335 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 336 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 337 sizeof(mem_reg_property)))); 338 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 339 sizeof(associativity)))); 340 return off; 341 } 342 343 static int spapr_populate_memory(SpaprMachineState *spapr, void *fdt) 344 { 345 MachineState *machine = MACHINE(spapr); 346 hwaddr mem_start, node_size; 347 int i, nb_nodes = machine->numa_state->num_nodes; 348 NodeInfo *nodes = machine->numa_state->nodes; 349 350 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 351 if (!nodes[i].node_mem) { 352 continue; 353 } 354 if (mem_start >= machine->ram_size) { 355 node_size = 0; 356 } else { 357 node_size = nodes[i].node_mem; 358 if (node_size > machine->ram_size - mem_start) { 359 node_size = machine->ram_size - mem_start; 360 } 361 } 362 if (!mem_start) { 363 /* spapr_machine_init() checks for rma_size <= node0_size 364 * already */ 365 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 366 mem_start += spapr->rma_size; 367 node_size -= spapr->rma_size; 368 } 369 for ( ; node_size; ) { 370 hwaddr sizetmp = pow2floor(node_size); 371 372 /* mem_start != 0 here */ 373 if (ctzl(mem_start) < ctzl(sizetmp)) { 374 sizetmp = 1ULL << ctzl(mem_start); 375 } 376 377 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 378 node_size -= sizetmp; 379 mem_start += sizetmp; 380 } 381 } 382 383 return 0; 384 } 385 386 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 387 SpaprMachineState *spapr) 388 { 389 MachineState *ms = MACHINE(spapr); 390 PowerPCCPU *cpu = POWERPC_CPU(cs); 391 CPUPPCState *env = &cpu->env; 392 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 393 int index = spapr_get_vcpu_id(cpu); 394 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 395 0xffffffff, 0xffffffff}; 396 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 397 : SPAPR_TIMEBASE_FREQ; 398 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 399 uint32_t page_sizes_prop[64]; 400 size_t page_sizes_prop_size; 401 unsigned int smp_threads = ms->smp.threads; 402 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 403 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 404 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 405 SpaprDrc *drc; 406 int drc_index; 407 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 408 int i; 409 410 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 411 if (drc) { 412 drc_index = spapr_drc_index(drc); 413 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 414 } 415 416 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 417 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 418 419 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 420 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 421 env->dcache_line_size))); 422 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 423 env->dcache_line_size))); 424 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 425 env->icache_line_size))); 426 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 427 env->icache_line_size))); 428 429 if (pcc->l1_dcache_size) { 430 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 431 pcc->l1_dcache_size))); 432 } else { 433 warn_report("Unknown L1 dcache size for cpu"); 434 } 435 if (pcc->l1_icache_size) { 436 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 437 pcc->l1_icache_size))); 438 } else { 439 warn_report("Unknown L1 icache size for cpu"); 440 } 441 442 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 443 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 444 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 445 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 446 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 447 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 448 449 if (env->spr_cb[SPR_PURR].oea_read) { 450 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 451 } 452 if (env->spr_cb[SPR_SPURR].oea_read) { 453 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 454 } 455 456 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 457 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 458 segs, sizeof(segs)))); 459 } 460 461 /* Advertise VSX (vector extensions) if available 462 * 1 == VMX / Altivec available 463 * 2 == VSX available 464 * 465 * Only CPUs for which we create core types in spapr_cpu_core.c 466 * are possible, and all of those have VMX */ 467 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 468 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 469 } else { 470 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 471 } 472 473 /* Advertise DFP (Decimal Floating Point) if available 474 * 0 / no property == no DFP 475 * 1 == DFP available */ 476 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 477 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 478 } 479 480 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 481 sizeof(page_sizes_prop)); 482 if (page_sizes_prop_size) { 483 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 484 page_sizes_prop, page_sizes_prop_size))); 485 } 486 487 spapr_populate_pa_features(spapr, cpu, fdt, offset); 488 489 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 490 cs->cpu_index / vcpus_per_socket))); 491 492 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 493 pft_size_prop, sizeof(pft_size_prop)))); 494 495 if (ms->numa_state->num_nodes > 1) { 496 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 497 } 498 499 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 500 501 if (pcc->radix_page_info) { 502 for (i = 0; i < pcc->radix_page_info->count; i++) { 503 radix_AP_encodings[i] = 504 cpu_to_be32(pcc->radix_page_info->entries[i]); 505 } 506 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 507 radix_AP_encodings, 508 pcc->radix_page_info->count * 509 sizeof(radix_AP_encodings[0])))); 510 } 511 512 /* 513 * We set this property to let the guest know that it can use the large 514 * decrementer and its width in bits. 515 */ 516 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 517 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 518 pcc->lrg_decr_bits))); 519 } 520 521 static void spapr_populate_cpus_dt_node(void *fdt, SpaprMachineState *spapr) 522 { 523 CPUState **rev; 524 CPUState *cs; 525 int n_cpus; 526 int cpus_offset; 527 char *nodename; 528 int i; 529 530 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 531 _FDT(cpus_offset); 532 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 533 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 534 535 /* 536 * We walk the CPUs in reverse order to ensure that CPU DT nodes 537 * created by fdt_add_subnode() end up in the right order in FDT 538 * for the guest kernel the enumerate the CPUs correctly. 539 * 540 * The CPU list cannot be traversed in reverse order, so we need 541 * to do extra work. 542 */ 543 n_cpus = 0; 544 rev = NULL; 545 CPU_FOREACH(cs) { 546 rev = g_renew(CPUState *, rev, n_cpus + 1); 547 rev[n_cpus++] = cs; 548 } 549 550 for (i = n_cpus - 1; i >= 0; i--) { 551 CPUState *cs = rev[i]; 552 PowerPCCPU *cpu = POWERPC_CPU(cs); 553 int index = spapr_get_vcpu_id(cpu); 554 DeviceClass *dc = DEVICE_GET_CLASS(cs); 555 int offset; 556 557 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 558 continue; 559 } 560 561 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 562 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 563 g_free(nodename); 564 _FDT(offset); 565 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 566 } 567 568 g_free(rev); 569 } 570 571 static int spapr_rng_populate_dt(void *fdt) 572 { 573 int node; 574 int ret; 575 576 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 577 if (node <= 0) { 578 return -1; 579 } 580 ret = fdt_setprop_string(fdt, node, "device_type", 581 "ibm,platform-facilities"); 582 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 583 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 584 585 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 586 if (node <= 0) { 587 return -1; 588 } 589 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 590 591 return ret ? -1 : 0; 592 } 593 594 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 595 { 596 MemoryDeviceInfoList *info; 597 598 for (info = list; info; info = info->next) { 599 MemoryDeviceInfo *value = info->value; 600 601 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 602 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 603 604 if (addr >= pcdimm_info->addr && 605 addr < (pcdimm_info->addr + pcdimm_info->size)) { 606 return pcdimm_info->node; 607 } 608 } 609 } 610 611 return -1; 612 } 613 614 struct sPAPRDrconfCellV2 { 615 uint32_t seq_lmbs; 616 uint64_t base_addr; 617 uint32_t drc_index; 618 uint32_t aa_index; 619 uint32_t flags; 620 } QEMU_PACKED; 621 622 typedef struct DrconfCellQueue { 623 struct sPAPRDrconfCellV2 cell; 624 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 625 } DrconfCellQueue; 626 627 static DrconfCellQueue * 628 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 629 uint32_t drc_index, uint32_t aa_index, 630 uint32_t flags) 631 { 632 DrconfCellQueue *elem; 633 634 elem = g_malloc0(sizeof(*elem)); 635 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 636 elem->cell.base_addr = cpu_to_be64(base_addr); 637 elem->cell.drc_index = cpu_to_be32(drc_index); 638 elem->cell.aa_index = cpu_to_be32(aa_index); 639 elem->cell.flags = cpu_to_be32(flags); 640 641 return elem; 642 } 643 644 /* ibm,dynamic-memory-v2 */ 645 static int spapr_populate_drmem_v2(SpaprMachineState *spapr, void *fdt, 646 int offset, MemoryDeviceInfoList *dimms) 647 { 648 MachineState *machine = MACHINE(spapr); 649 uint8_t *int_buf, *cur_index; 650 int ret; 651 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 652 uint64_t addr, cur_addr, size; 653 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 654 uint64_t mem_end = machine->device_memory->base + 655 memory_region_size(&machine->device_memory->mr); 656 uint32_t node, buf_len, nr_entries = 0; 657 SpaprDrc *drc; 658 DrconfCellQueue *elem, *next; 659 MemoryDeviceInfoList *info; 660 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 661 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 662 663 /* Entry to cover RAM and the gap area */ 664 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 665 SPAPR_LMB_FLAGS_RESERVED | 666 SPAPR_LMB_FLAGS_DRC_INVALID); 667 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 668 nr_entries++; 669 670 cur_addr = machine->device_memory->base; 671 for (info = dimms; info; info = info->next) { 672 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 673 674 addr = di->addr; 675 size = di->size; 676 node = di->node; 677 678 /* Entry for hot-pluggable area */ 679 if (cur_addr < addr) { 680 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 681 g_assert(drc); 682 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 683 cur_addr, spapr_drc_index(drc), -1, 0); 684 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 685 nr_entries++; 686 } 687 688 /* Entry for DIMM */ 689 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 690 g_assert(drc); 691 elem = spapr_get_drconf_cell(size / lmb_size, addr, 692 spapr_drc_index(drc), node, 693 SPAPR_LMB_FLAGS_ASSIGNED); 694 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 695 nr_entries++; 696 cur_addr = addr + size; 697 } 698 699 /* Entry for remaining hotpluggable area */ 700 if (cur_addr < mem_end) { 701 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 702 g_assert(drc); 703 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 704 cur_addr, spapr_drc_index(drc), -1, 0); 705 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 706 nr_entries++; 707 } 708 709 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 710 int_buf = cur_index = g_malloc0(buf_len); 711 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 712 cur_index += sizeof(nr_entries); 713 714 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 715 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 716 cur_index += sizeof(elem->cell); 717 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 718 g_free(elem); 719 } 720 721 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 722 g_free(int_buf); 723 if (ret < 0) { 724 return -1; 725 } 726 return 0; 727 } 728 729 /* ibm,dynamic-memory */ 730 static int spapr_populate_drmem_v1(SpaprMachineState *spapr, void *fdt, 731 int offset, MemoryDeviceInfoList *dimms) 732 { 733 MachineState *machine = MACHINE(spapr); 734 int i, ret; 735 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 736 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 737 uint32_t nr_lmbs = (machine->device_memory->base + 738 memory_region_size(&machine->device_memory->mr)) / 739 lmb_size; 740 uint32_t *int_buf, *cur_index, buf_len; 741 742 /* 743 * Allocate enough buffer size to fit in ibm,dynamic-memory 744 */ 745 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 746 cur_index = int_buf = g_malloc0(buf_len); 747 int_buf[0] = cpu_to_be32(nr_lmbs); 748 cur_index++; 749 for (i = 0; i < nr_lmbs; i++) { 750 uint64_t addr = i * lmb_size; 751 uint32_t *dynamic_memory = cur_index; 752 753 if (i >= device_lmb_start) { 754 SpaprDrc *drc; 755 756 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 757 g_assert(drc); 758 759 dynamic_memory[0] = cpu_to_be32(addr >> 32); 760 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 761 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 762 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 763 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 764 if (memory_region_present(get_system_memory(), addr)) { 765 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 766 } else { 767 dynamic_memory[5] = cpu_to_be32(0); 768 } 769 } else { 770 /* 771 * LMB information for RMA, boot time RAM and gap b/n RAM and 772 * device memory region -- all these are marked as reserved 773 * and as having no valid DRC. 774 */ 775 dynamic_memory[0] = cpu_to_be32(addr >> 32); 776 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 777 dynamic_memory[2] = cpu_to_be32(0); 778 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 779 dynamic_memory[4] = cpu_to_be32(-1); 780 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 781 SPAPR_LMB_FLAGS_DRC_INVALID); 782 } 783 784 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 785 } 786 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 787 g_free(int_buf); 788 if (ret < 0) { 789 return -1; 790 } 791 return 0; 792 } 793 794 /* 795 * Adds ibm,dynamic-reconfiguration-memory node. 796 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 797 * of this device tree node. 798 */ 799 static int spapr_populate_drconf_memory(SpaprMachineState *spapr, void *fdt) 800 { 801 MachineState *machine = MACHINE(spapr); 802 int nb_numa_nodes = machine->numa_state->num_nodes; 803 int ret, i, offset; 804 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 805 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 806 uint32_t *int_buf, *cur_index, buf_len; 807 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 808 MemoryDeviceInfoList *dimms = NULL; 809 810 /* 811 * Don't create the node if there is no device memory 812 */ 813 if (machine->ram_size == machine->maxram_size) { 814 return 0; 815 } 816 817 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 818 819 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 820 sizeof(prop_lmb_size)); 821 if (ret < 0) { 822 return ret; 823 } 824 825 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 826 if (ret < 0) { 827 return ret; 828 } 829 830 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 831 if (ret < 0) { 832 return ret; 833 } 834 835 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 836 dimms = qmp_memory_device_list(); 837 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 838 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); 839 } else { 840 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); 841 } 842 qapi_free_MemoryDeviceInfoList(dimms); 843 844 if (ret < 0) { 845 return ret; 846 } 847 848 /* ibm,associativity-lookup-arrays */ 849 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 850 cur_index = int_buf = g_malloc0(buf_len); 851 int_buf[0] = cpu_to_be32(nr_nodes); 852 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 853 cur_index += 2; 854 for (i = 0; i < nr_nodes; i++) { 855 uint32_t associativity[] = { 856 cpu_to_be32(0x0), 857 cpu_to_be32(0x0), 858 cpu_to_be32(0x0), 859 cpu_to_be32(i) 860 }; 861 memcpy(cur_index, associativity, sizeof(associativity)); 862 cur_index += 4; 863 } 864 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 865 (cur_index - int_buf) * sizeof(uint32_t)); 866 g_free(int_buf); 867 868 return ret; 869 } 870 871 static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt, 872 SpaprOptionVector *ov5_updates) 873 { 874 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 875 int ret = 0, offset; 876 877 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 878 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 879 g_assert(smc->dr_lmb_enabled); 880 ret = spapr_populate_drconf_memory(spapr, fdt); 881 if (ret) { 882 return ret; 883 } 884 } 885 886 offset = fdt_path_offset(fdt, "/chosen"); 887 if (offset < 0) { 888 offset = fdt_add_subnode(fdt, 0, "chosen"); 889 if (offset < 0) { 890 return offset; 891 } 892 } 893 return spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 894 "ibm,architecture-vec-5"); 895 } 896 897 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 898 { 899 MachineState *ms = MACHINE(spapr); 900 int rtas; 901 GString *hypertas = g_string_sized_new(256); 902 GString *qemu_hypertas = g_string_sized_new(256); 903 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 904 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 905 memory_region_size(&MACHINE(spapr)->device_memory->mr); 906 uint32_t lrdr_capacity[] = { 907 cpu_to_be32(max_device_addr >> 32), 908 cpu_to_be32(max_device_addr & 0xffffffff), 909 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 910 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 911 }; 912 uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0); 913 uint32_t maxdomains[] = { 914 cpu_to_be32(4), 915 maxdomain, 916 maxdomain, 917 maxdomain, 918 cpu_to_be32(spapr->gpu_numa_id), 919 }; 920 921 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 922 923 /* hypertas */ 924 add_str(hypertas, "hcall-pft"); 925 add_str(hypertas, "hcall-term"); 926 add_str(hypertas, "hcall-dabr"); 927 add_str(hypertas, "hcall-interrupt"); 928 add_str(hypertas, "hcall-tce"); 929 add_str(hypertas, "hcall-vio"); 930 add_str(hypertas, "hcall-splpar"); 931 add_str(hypertas, "hcall-join"); 932 add_str(hypertas, "hcall-bulk"); 933 add_str(hypertas, "hcall-set-mode"); 934 add_str(hypertas, "hcall-sprg0"); 935 add_str(hypertas, "hcall-copy"); 936 add_str(hypertas, "hcall-debug"); 937 add_str(hypertas, "hcall-vphn"); 938 add_str(qemu_hypertas, "hcall-memop1"); 939 940 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 941 add_str(hypertas, "hcall-multi-tce"); 942 } 943 944 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 945 add_str(hypertas, "hcall-hpt-resize"); 946 } 947 948 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 949 hypertas->str, hypertas->len)); 950 g_string_free(hypertas, TRUE); 951 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 952 qemu_hypertas->str, qemu_hypertas->len)); 953 g_string_free(qemu_hypertas, TRUE); 954 955 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 956 refpoints, sizeof(refpoints))); 957 958 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 959 maxdomains, sizeof(maxdomains))); 960 961 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 962 RTAS_ERROR_LOG_MAX)); 963 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 964 RTAS_EVENT_SCAN_RATE)); 965 966 g_assert(msi_nonbroken); 967 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 968 969 /* 970 * According to PAPR, rtas ibm,os-term does not guarantee a return 971 * back to the guest cpu. 972 * 973 * While an additional ibm,extended-os-term property indicates 974 * that rtas call return will always occur. Set this property. 975 */ 976 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 977 978 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 979 lrdr_capacity, sizeof(lrdr_capacity))); 980 981 spapr_dt_rtas_tokens(fdt, rtas); 982 } 983 984 /* 985 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 986 * and the XIVE features that the guest may request and thus the valid 987 * values for bytes 23..26 of option vector 5: 988 */ 989 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 990 int chosen) 991 { 992 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 993 994 char val[2 * 4] = { 995 23, 0x00, /* XICS / XIVE mode */ 996 24, 0x00, /* Hash/Radix, filled in below. */ 997 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 998 26, 0x40, /* Radix options: GTSE == yes. */ 999 }; 1000 1001 if (spapr->irq->xics && spapr->irq->xive) { 1002 val[1] = SPAPR_OV5_XIVE_BOTH; 1003 } else if (spapr->irq->xive) { 1004 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 1005 } else { 1006 assert(spapr->irq->xics); 1007 val[1] = SPAPR_OV5_XIVE_LEGACY; 1008 } 1009 1010 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1011 first_ppc_cpu->compat_pvr)) { 1012 /* 1013 * If we're in a pre POWER9 compat mode then the guest should 1014 * do hash and use the legacy interrupt mode 1015 */ 1016 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 1017 val[3] = 0x00; /* Hash */ 1018 } else if (kvm_enabled()) { 1019 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1020 val[3] = 0x80; /* OV5_MMU_BOTH */ 1021 } else if (kvmppc_has_cap_mmu_radix()) { 1022 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1023 } else { 1024 val[3] = 0x00; /* Hash */ 1025 } 1026 } else { 1027 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1028 val[3] = 0xC0; 1029 } 1030 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1031 val, sizeof(val))); 1032 } 1033 1034 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt) 1035 { 1036 MachineState *machine = MACHINE(spapr); 1037 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1038 int chosen; 1039 const char *boot_device = machine->boot_order; 1040 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1041 size_t cb = 0; 1042 char *bootlist = get_boot_devices_list(&cb); 1043 1044 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1045 1046 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1047 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1048 machine->kernel_cmdline)); 1049 } 1050 if (spapr->initrd_size) { 1051 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1052 spapr->initrd_base)); 1053 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1054 spapr->initrd_base + spapr->initrd_size)); 1055 } 1056 1057 if (spapr->kernel_size) { 1058 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 1059 cpu_to_be64(spapr->kernel_size) }; 1060 1061 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1062 &kprop, sizeof(kprop))); 1063 if (spapr->kernel_le) { 1064 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1065 } 1066 } 1067 if (boot_menu) { 1068 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1069 } 1070 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1071 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1072 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1073 1074 if (cb && bootlist) { 1075 int i; 1076 1077 for (i = 0; i < cb; i++) { 1078 if (bootlist[i] == '\n') { 1079 bootlist[i] = ' '; 1080 } 1081 } 1082 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1083 } 1084 1085 if (boot_device && strlen(boot_device)) { 1086 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1087 } 1088 1089 if (!spapr->has_graphics && stdout_path) { 1090 /* 1091 * "linux,stdout-path" and "stdout" properties are deprecated by linux 1092 * kernel. New platforms should only use the "stdout-path" property. Set 1093 * the new property and continue using older property to remain 1094 * compatible with the existing firmware. 1095 */ 1096 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1097 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1098 } 1099 1100 /* We can deal with BAR reallocation just fine, advertise it to the guest */ 1101 if (smc->linux_pci_probe) { 1102 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1103 } 1104 1105 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1106 1107 g_free(stdout_path); 1108 g_free(bootlist); 1109 } 1110 1111 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1112 { 1113 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1114 * KVM to work under pHyp with some guest co-operation */ 1115 int hypervisor; 1116 uint8_t hypercall[16]; 1117 1118 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1119 /* indicate KVM hypercall interface */ 1120 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1121 if (kvmppc_has_cap_fixup_hcalls()) { 1122 /* 1123 * Older KVM versions with older guest kernels were broken 1124 * with the magic page, don't allow the guest to map it. 1125 */ 1126 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1127 sizeof(hypercall))) { 1128 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1129 hypercall, sizeof(hypercall))); 1130 } 1131 } 1132 } 1133 1134 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1135 { 1136 MachineState *machine = MACHINE(spapr); 1137 MachineClass *mc = MACHINE_GET_CLASS(machine); 1138 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1139 int ret; 1140 void *fdt; 1141 SpaprPhbState *phb; 1142 char *buf; 1143 1144 fdt = g_malloc0(space); 1145 _FDT((fdt_create_empty_tree(fdt, space))); 1146 1147 /* Root node */ 1148 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1149 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1150 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1151 1152 /* Guest UUID & Name*/ 1153 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1154 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1155 if (qemu_uuid_set) { 1156 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1157 } 1158 g_free(buf); 1159 1160 if (qemu_get_vm_name()) { 1161 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1162 qemu_get_vm_name())); 1163 } 1164 1165 /* Host Model & Serial Number */ 1166 if (spapr->host_model) { 1167 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1168 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1169 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1170 g_free(buf); 1171 } 1172 1173 if (spapr->host_serial) { 1174 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1175 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1176 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1177 g_free(buf); 1178 } 1179 1180 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1181 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1182 1183 /* /interrupt controller */ 1184 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1185 1186 ret = spapr_populate_memory(spapr, fdt); 1187 if (ret < 0) { 1188 error_report("couldn't setup memory nodes in fdt"); 1189 exit(1); 1190 } 1191 1192 /* /vdevice */ 1193 spapr_dt_vdevice(spapr->vio_bus, fdt); 1194 1195 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1196 ret = spapr_rng_populate_dt(fdt); 1197 if (ret < 0) { 1198 error_report("could not set up rng device in the fdt"); 1199 exit(1); 1200 } 1201 } 1202 1203 QLIST_FOREACH(phb, &spapr->phbs, list) { 1204 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1205 if (ret < 0) { 1206 error_report("couldn't setup PCI devices in fdt"); 1207 exit(1); 1208 } 1209 } 1210 1211 /* cpus */ 1212 spapr_populate_cpus_dt_node(fdt, spapr); 1213 1214 if (smc->dr_lmb_enabled) { 1215 _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1216 } 1217 1218 if (mc->has_hotpluggable_cpus) { 1219 int offset = fdt_path_offset(fdt, "/cpus"); 1220 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1221 if (ret < 0) { 1222 error_report("Couldn't set up CPU DR device tree properties"); 1223 exit(1); 1224 } 1225 } 1226 1227 /* /event-sources */ 1228 spapr_dt_events(spapr, fdt); 1229 1230 /* /rtas */ 1231 spapr_dt_rtas(spapr, fdt); 1232 1233 /* /chosen */ 1234 if (reset) { 1235 spapr_dt_chosen(spapr, fdt); 1236 } 1237 1238 /* /hypervisor */ 1239 if (kvm_enabled()) { 1240 spapr_dt_hypervisor(spapr, fdt); 1241 } 1242 1243 /* Build memory reserve map */ 1244 if (reset) { 1245 if (spapr->kernel_size) { 1246 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1247 } 1248 if (spapr->initrd_size) { 1249 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1250 spapr->initrd_size))); 1251 } 1252 } 1253 1254 /* ibm,client-architecture-support updates */ 1255 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1256 if (ret < 0) { 1257 error_report("couldn't setup CAS properties fdt"); 1258 exit(1); 1259 } 1260 1261 if (smc->dr_phb_enabled) { 1262 ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB); 1263 if (ret < 0) { 1264 error_report("Couldn't set up PHB DR device tree properties"); 1265 exit(1); 1266 } 1267 } 1268 1269 return fdt; 1270 } 1271 1272 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1273 { 1274 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1275 } 1276 1277 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1278 PowerPCCPU *cpu) 1279 { 1280 CPUPPCState *env = &cpu->env; 1281 1282 /* The TCG path should also be holding the BQL at this point */ 1283 g_assert(qemu_mutex_iothread_locked()); 1284 1285 if (msr_pr) { 1286 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1287 env->gpr[3] = H_PRIVILEGE; 1288 } else { 1289 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1290 } 1291 } 1292 1293 struct LPCRSyncState { 1294 target_ulong value; 1295 target_ulong mask; 1296 }; 1297 1298 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1299 { 1300 struct LPCRSyncState *s = arg.host_ptr; 1301 PowerPCCPU *cpu = POWERPC_CPU(cs); 1302 CPUPPCState *env = &cpu->env; 1303 target_ulong lpcr; 1304 1305 cpu_synchronize_state(cs); 1306 lpcr = env->spr[SPR_LPCR]; 1307 lpcr &= ~s->mask; 1308 lpcr |= s->value; 1309 ppc_store_lpcr(cpu, lpcr); 1310 } 1311 1312 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1313 { 1314 CPUState *cs; 1315 struct LPCRSyncState s = { 1316 .value = value, 1317 .mask = mask 1318 }; 1319 CPU_FOREACH(cs) { 1320 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1321 } 1322 } 1323 1324 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1325 { 1326 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1327 1328 /* Copy PATE1:GR into PATE0:HR */ 1329 entry->dw0 = spapr->patb_entry & PATE0_HR; 1330 entry->dw1 = spapr->patb_entry; 1331 } 1332 1333 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1334 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1335 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1336 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1337 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1338 1339 /* 1340 * Get the fd to access the kernel htab, re-opening it if necessary 1341 */ 1342 static int get_htab_fd(SpaprMachineState *spapr) 1343 { 1344 Error *local_err = NULL; 1345 1346 if (spapr->htab_fd >= 0) { 1347 return spapr->htab_fd; 1348 } 1349 1350 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1351 if (spapr->htab_fd < 0) { 1352 error_report_err(local_err); 1353 } 1354 1355 return spapr->htab_fd; 1356 } 1357 1358 void close_htab_fd(SpaprMachineState *spapr) 1359 { 1360 if (spapr->htab_fd >= 0) { 1361 close(spapr->htab_fd); 1362 } 1363 spapr->htab_fd = -1; 1364 } 1365 1366 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1367 { 1368 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1369 1370 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1371 } 1372 1373 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1374 { 1375 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1376 1377 assert(kvm_enabled()); 1378 1379 if (!spapr->htab) { 1380 return 0; 1381 } 1382 1383 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1384 } 1385 1386 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1387 hwaddr ptex, int n) 1388 { 1389 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1390 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1391 1392 if (!spapr->htab) { 1393 /* 1394 * HTAB is controlled by KVM. Fetch into temporary buffer 1395 */ 1396 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1397 kvmppc_read_hptes(hptes, ptex, n); 1398 return hptes; 1399 } 1400 1401 /* 1402 * HTAB is controlled by QEMU. Just point to the internally 1403 * accessible PTEG. 1404 */ 1405 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1406 } 1407 1408 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1409 const ppc_hash_pte64_t *hptes, 1410 hwaddr ptex, int n) 1411 { 1412 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1413 1414 if (!spapr->htab) { 1415 g_free((void *)hptes); 1416 } 1417 1418 /* Nothing to do for qemu managed HPT */ 1419 } 1420 1421 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1422 uint64_t pte0, uint64_t pte1) 1423 { 1424 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1425 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1426 1427 if (!spapr->htab) { 1428 kvmppc_write_hpte(ptex, pte0, pte1); 1429 } else { 1430 if (pte0 & HPTE64_V_VALID) { 1431 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1432 /* 1433 * When setting valid, we write PTE1 first. This ensures 1434 * proper synchronization with the reading code in 1435 * ppc_hash64_pteg_search() 1436 */ 1437 smp_wmb(); 1438 stq_p(spapr->htab + offset, pte0); 1439 } else { 1440 stq_p(spapr->htab + offset, pte0); 1441 /* 1442 * When clearing it we set PTE0 first. This ensures proper 1443 * synchronization with the reading code in 1444 * ppc_hash64_pteg_search() 1445 */ 1446 smp_wmb(); 1447 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1448 } 1449 } 1450 } 1451 1452 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1453 uint64_t pte1) 1454 { 1455 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1456 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1457 1458 if (!spapr->htab) { 1459 /* There should always be a hash table when this is called */ 1460 error_report("spapr_hpte_set_c called with no hash table !"); 1461 return; 1462 } 1463 1464 /* The HW performs a non-atomic byte update */ 1465 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1466 } 1467 1468 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1469 uint64_t pte1) 1470 { 1471 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1472 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1473 1474 if (!spapr->htab) { 1475 /* There should always be a hash table when this is called */ 1476 error_report("spapr_hpte_set_r called with no hash table !"); 1477 return; 1478 } 1479 1480 /* The HW performs a non-atomic byte update */ 1481 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1482 } 1483 1484 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1485 { 1486 int shift; 1487 1488 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1489 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1490 * that's much more than is needed for Linux guests */ 1491 shift = ctz64(pow2ceil(ramsize)) - 7; 1492 shift = MAX(shift, 18); /* Minimum architected size */ 1493 shift = MIN(shift, 46); /* Maximum architected size */ 1494 return shift; 1495 } 1496 1497 void spapr_free_hpt(SpaprMachineState *spapr) 1498 { 1499 g_free(spapr->htab); 1500 spapr->htab = NULL; 1501 spapr->htab_shift = 0; 1502 close_htab_fd(spapr); 1503 } 1504 1505 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 1506 Error **errp) 1507 { 1508 long rc; 1509 1510 /* Clean up any HPT info from a previous boot */ 1511 spapr_free_hpt(spapr); 1512 1513 rc = kvmppc_reset_htab(shift); 1514 if (rc < 0) { 1515 /* kernel-side HPT needed, but couldn't allocate one */ 1516 error_setg_errno(errp, errno, 1517 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1518 shift); 1519 /* This is almost certainly fatal, but if the caller really 1520 * wants to carry on with shift == 0, it's welcome to try */ 1521 } else if (rc > 0) { 1522 /* kernel-side HPT allocated */ 1523 if (rc != shift) { 1524 error_setg(errp, 1525 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1526 shift, rc); 1527 } 1528 1529 spapr->htab_shift = shift; 1530 spapr->htab = NULL; 1531 } else { 1532 /* kernel-side HPT not needed, allocate in userspace instead */ 1533 size_t size = 1ULL << shift; 1534 int i; 1535 1536 spapr->htab = qemu_memalign(size, size); 1537 if (!spapr->htab) { 1538 error_setg_errno(errp, errno, 1539 "Could not allocate HPT of order %d", shift); 1540 return; 1541 } 1542 1543 memset(spapr->htab, 0, size); 1544 spapr->htab_shift = shift; 1545 1546 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1547 DIRTY_HPTE(HPTE(spapr->htab, i)); 1548 } 1549 } 1550 /* We're setting up a hash table, so that means we're not radix */ 1551 spapr->patb_entry = 0; 1552 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1553 } 1554 1555 void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr) 1556 { 1557 int hpt_shift; 1558 1559 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1560 || (spapr->cas_reboot 1561 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1562 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1563 } else { 1564 uint64_t current_ram_size; 1565 1566 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1567 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1568 } 1569 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1570 1571 if (spapr->vrma_adjust) { 1572 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), 1573 spapr->htab_shift); 1574 } 1575 } 1576 1577 static int spapr_reset_drcs(Object *child, void *opaque) 1578 { 1579 SpaprDrc *drc = 1580 (SpaprDrc *) object_dynamic_cast(child, 1581 TYPE_SPAPR_DR_CONNECTOR); 1582 1583 if (drc) { 1584 spapr_drc_reset(drc); 1585 } 1586 1587 return 0; 1588 } 1589 1590 static void spapr_machine_reset(MachineState *machine) 1591 { 1592 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1593 PowerPCCPU *first_ppc_cpu; 1594 hwaddr fdt_addr; 1595 void *fdt; 1596 int rc; 1597 1598 kvmppc_svm_off(&error_fatal); 1599 spapr_caps_apply(spapr); 1600 1601 first_ppc_cpu = POWERPC_CPU(first_cpu); 1602 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1603 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1604 spapr->max_compat_pvr)) { 1605 /* 1606 * If using KVM with radix mode available, VCPUs can be started 1607 * without a HPT because KVM will start them in radix mode. 1608 * Set the GR bit in PATE so that we know there is no HPT. 1609 */ 1610 spapr->patb_entry = PATE1_GR; 1611 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1612 } else { 1613 spapr_setup_hpt_and_vrma(spapr); 1614 } 1615 1616 qemu_devices_reset(); 1617 1618 /* 1619 * If this reset wasn't generated by CAS, we should reset our 1620 * negotiated options and start from scratch 1621 */ 1622 if (!spapr->cas_reboot) { 1623 spapr_ovec_cleanup(spapr->ov5_cas); 1624 spapr->ov5_cas = spapr_ovec_new(); 1625 1626 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1627 } 1628 1629 /* 1630 * This is fixing some of the default configuration of the XIVE 1631 * devices. To be called after the reset of the machine devices. 1632 */ 1633 spapr_irq_reset(spapr, &error_fatal); 1634 1635 /* 1636 * There is no CAS under qtest. Simulate one to please the code that 1637 * depends on spapr->ov5_cas. This is especially needed to test device 1638 * unplug, so we do that before resetting the DRCs. 1639 */ 1640 if (qtest_enabled()) { 1641 spapr_ovec_cleanup(spapr->ov5_cas); 1642 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1643 } 1644 1645 /* DRC reset may cause a device to be unplugged. This will cause troubles 1646 * if this device is used by another device (eg, a running vhost backend 1647 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1648 * situations, we reset DRCs after all devices have been reset. 1649 */ 1650 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1651 1652 spapr_clear_pending_events(spapr); 1653 1654 /* 1655 * We place the device tree and RTAS just below either the top of the RMA, 1656 * or just below 2GB, whichever is lower, so that it can be 1657 * processed with 32-bit real mode code if necessary 1658 */ 1659 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; 1660 1661 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1662 1663 rc = fdt_pack(fdt); 1664 1665 /* Should only fail if we've built a corrupted tree */ 1666 assert(rc == 0); 1667 1668 /* Load the fdt */ 1669 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1670 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1671 g_free(spapr->fdt_blob); 1672 spapr->fdt_size = fdt_totalsize(fdt); 1673 spapr->fdt_initial_size = spapr->fdt_size; 1674 spapr->fdt_blob = fdt; 1675 1676 /* Set up the entry state */ 1677 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); 1678 first_ppc_cpu->env.gpr[5] = 0; 1679 1680 spapr->cas_reboot = false; 1681 1682 spapr->mc_status = -1; 1683 spapr->guest_machine_check_addr = -1; 1684 1685 /* Signal all vCPUs waiting on this condition */ 1686 qemu_cond_broadcast(&spapr->mc_delivery_cond); 1687 1688 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1689 } 1690 1691 static void spapr_create_nvram(SpaprMachineState *spapr) 1692 { 1693 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1694 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1695 1696 if (dinfo) { 1697 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1698 &error_fatal); 1699 } 1700 1701 qdev_init_nofail(dev); 1702 1703 spapr->nvram = (struct SpaprNvram *)dev; 1704 } 1705 1706 static void spapr_rtc_create(SpaprMachineState *spapr) 1707 { 1708 object_initialize_child(OBJECT(spapr), "rtc", 1709 &spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1710 &error_fatal, NULL); 1711 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1712 &error_fatal); 1713 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1714 "date", &error_fatal); 1715 } 1716 1717 /* Returns whether we want to use VGA or not */ 1718 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1719 { 1720 switch (vga_interface_type) { 1721 case VGA_NONE: 1722 return false; 1723 case VGA_DEVICE: 1724 return true; 1725 case VGA_STD: 1726 case VGA_VIRTIO: 1727 case VGA_CIRRUS: 1728 return pci_vga_init(pci_bus) != NULL; 1729 default: 1730 error_setg(errp, 1731 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1732 return false; 1733 } 1734 } 1735 1736 static int spapr_pre_load(void *opaque) 1737 { 1738 int rc; 1739 1740 rc = spapr_caps_pre_load(opaque); 1741 if (rc) { 1742 return rc; 1743 } 1744 1745 return 0; 1746 } 1747 1748 static int spapr_post_load(void *opaque, int version_id) 1749 { 1750 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1751 int err = 0; 1752 1753 err = spapr_caps_post_migration(spapr); 1754 if (err) { 1755 return err; 1756 } 1757 1758 /* 1759 * In earlier versions, there was no separate qdev for the PAPR 1760 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1761 * So when migrating from those versions, poke the incoming offset 1762 * value into the RTC device 1763 */ 1764 if (version_id < 3) { 1765 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1766 if (err) { 1767 return err; 1768 } 1769 } 1770 1771 if (kvm_enabled() && spapr->patb_entry) { 1772 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1773 bool radix = !!(spapr->patb_entry & PATE1_GR); 1774 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1775 1776 /* 1777 * Update LPCR:HR and UPRT as they may not be set properly in 1778 * the stream 1779 */ 1780 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1781 LPCR_HR | LPCR_UPRT); 1782 1783 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1784 if (err) { 1785 error_report("Process table config unsupported by the host"); 1786 return -EINVAL; 1787 } 1788 } 1789 1790 err = spapr_irq_post_load(spapr, version_id); 1791 if (err) { 1792 return err; 1793 } 1794 1795 return err; 1796 } 1797 1798 static int spapr_pre_save(void *opaque) 1799 { 1800 int rc; 1801 1802 rc = spapr_caps_pre_save(opaque); 1803 if (rc) { 1804 return rc; 1805 } 1806 1807 return 0; 1808 } 1809 1810 static bool version_before_3(void *opaque, int version_id) 1811 { 1812 return version_id < 3; 1813 } 1814 1815 static bool spapr_pending_events_needed(void *opaque) 1816 { 1817 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1818 return !QTAILQ_EMPTY(&spapr->pending_events); 1819 } 1820 1821 static const VMStateDescription vmstate_spapr_event_entry = { 1822 .name = "spapr_event_log_entry", 1823 .version_id = 1, 1824 .minimum_version_id = 1, 1825 .fields = (VMStateField[]) { 1826 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1827 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1828 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1829 NULL, extended_length), 1830 VMSTATE_END_OF_LIST() 1831 }, 1832 }; 1833 1834 static const VMStateDescription vmstate_spapr_pending_events = { 1835 .name = "spapr_pending_events", 1836 .version_id = 1, 1837 .minimum_version_id = 1, 1838 .needed = spapr_pending_events_needed, 1839 .fields = (VMStateField[]) { 1840 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1841 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1842 VMSTATE_END_OF_LIST() 1843 }, 1844 }; 1845 1846 static bool spapr_ov5_cas_needed(void *opaque) 1847 { 1848 SpaprMachineState *spapr = opaque; 1849 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1850 bool cas_needed; 1851 1852 /* Prior to the introduction of SpaprOptionVector, we had two option 1853 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1854 * Both of these options encode machine topology into the device-tree 1855 * in such a way that the now-booted OS should still be able to interact 1856 * appropriately with QEMU regardless of what options were actually 1857 * negotiatied on the source side. 1858 * 1859 * As such, we can avoid migrating the CAS-negotiated options if these 1860 * are the only options available on the current machine/platform. 1861 * Since these are the only options available for pseries-2.7 and 1862 * earlier, this allows us to maintain old->new/new->old migration 1863 * compatibility. 1864 * 1865 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1866 * via default pseries-2.8 machines and explicit command-line parameters. 1867 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1868 * of the actual CAS-negotiated values to continue working properly. For 1869 * example, availability of memory unplug depends on knowing whether 1870 * OV5_HP_EVT was negotiated via CAS. 1871 * 1872 * Thus, for any cases where the set of available CAS-negotiatable 1873 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1874 * include the CAS-negotiated options in the migration stream, unless 1875 * if they affect boot time behaviour only. 1876 */ 1877 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1878 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1879 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1880 1881 /* We need extra information if we have any bits outside the mask 1882 * defined above */ 1883 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1884 1885 spapr_ovec_cleanup(ov5_mask); 1886 1887 return cas_needed; 1888 } 1889 1890 static const VMStateDescription vmstate_spapr_ov5_cas = { 1891 .name = "spapr_option_vector_ov5_cas", 1892 .version_id = 1, 1893 .minimum_version_id = 1, 1894 .needed = spapr_ov5_cas_needed, 1895 .fields = (VMStateField[]) { 1896 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1897 vmstate_spapr_ovec, SpaprOptionVector), 1898 VMSTATE_END_OF_LIST() 1899 }, 1900 }; 1901 1902 static bool spapr_patb_entry_needed(void *opaque) 1903 { 1904 SpaprMachineState *spapr = opaque; 1905 1906 return !!spapr->patb_entry; 1907 } 1908 1909 static const VMStateDescription vmstate_spapr_patb_entry = { 1910 .name = "spapr_patb_entry", 1911 .version_id = 1, 1912 .minimum_version_id = 1, 1913 .needed = spapr_patb_entry_needed, 1914 .fields = (VMStateField[]) { 1915 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1916 VMSTATE_END_OF_LIST() 1917 }, 1918 }; 1919 1920 static bool spapr_irq_map_needed(void *opaque) 1921 { 1922 SpaprMachineState *spapr = opaque; 1923 1924 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1925 } 1926 1927 static const VMStateDescription vmstate_spapr_irq_map = { 1928 .name = "spapr_irq_map", 1929 .version_id = 1, 1930 .minimum_version_id = 1, 1931 .needed = spapr_irq_map_needed, 1932 .fields = (VMStateField[]) { 1933 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1934 VMSTATE_END_OF_LIST() 1935 }, 1936 }; 1937 1938 static bool spapr_dtb_needed(void *opaque) 1939 { 1940 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1941 1942 return smc->update_dt_enabled; 1943 } 1944 1945 static int spapr_dtb_pre_load(void *opaque) 1946 { 1947 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1948 1949 g_free(spapr->fdt_blob); 1950 spapr->fdt_blob = NULL; 1951 spapr->fdt_size = 0; 1952 1953 return 0; 1954 } 1955 1956 static const VMStateDescription vmstate_spapr_dtb = { 1957 .name = "spapr_dtb", 1958 .version_id = 1, 1959 .minimum_version_id = 1, 1960 .needed = spapr_dtb_needed, 1961 .pre_load = spapr_dtb_pre_load, 1962 .fields = (VMStateField[]) { 1963 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1964 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1965 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1966 fdt_size), 1967 VMSTATE_END_OF_LIST() 1968 }, 1969 }; 1970 1971 static bool spapr_fwnmi_needed(void *opaque) 1972 { 1973 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1974 1975 return spapr->guest_machine_check_addr != -1; 1976 } 1977 1978 static int spapr_fwnmi_pre_save(void *opaque) 1979 { 1980 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1981 1982 /* 1983 * Check if machine check handling is in progress and print a 1984 * warning message. 1985 */ 1986 if (spapr->mc_status != -1) { 1987 warn_report("A machine check is being handled during migration. The" 1988 "handler may run and log hardware error on the destination"); 1989 } 1990 1991 return 0; 1992 } 1993 1994 static const VMStateDescription vmstate_spapr_machine_check = { 1995 .name = "spapr_machine_check", 1996 .version_id = 1, 1997 .minimum_version_id = 1, 1998 .needed = spapr_fwnmi_needed, 1999 .pre_save = spapr_fwnmi_pre_save, 2000 .fields = (VMStateField[]) { 2001 VMSTATE_UINT64(guest_machine_check_addr, SpaprMachineState), 2002 VMSTATE_INT32(mc_status, SpaprMachineState), 2003 VMSTATE_END_OF_LIST() 2004 }, 2005 }; 2006 2007 static const VMStateDescription vmstate_spapr = { 2008 .name = "spapr", 2009 .version_id = 3, 2010 .minimum_version_id = 1, 2011 .pre_load = spapr_pre_load, 2012 .post_load = spapr_post_load, 2013 .pre_save = spapr_pre_save, 2014 .fields = (VMStateField[]) { 2015 /* used to be @next_irq */ 2016 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2017 2018 /* RTC offset */ 2019 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2020 2021 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2022 VMSTATE_END_OF_LIST() 2023 }, 2024 .subsections = (const VMStateDescription*[]) { 2025 &vmstate_spapr_ov5_cas, 2026 &vmstate_spapr_patb_entry, 2027 &vmstate_spapr_pending_events, 2028 &vmstate_spapr_cap_htm, 2029 &vmstate_spapr_cap_vsx, 2030 &vmstate_spapr_cap_dfp, 2031 &vmstate_spapr_cap_cfpc, 2032 &vmstate_spapr_cap_sbbc, 2033 &vmstate_spapr_cap_ibs, 2034 &vmstate_spapr_cap_hpt_maxpagesize, 2035 &vmstate_spapr_irq_map, 2036 &vmstate_spapr_cap_nested_kvm_hv, 2037 &vmstate_spapr_dtb, 2038 &vmstate_spapr_cap_large_decr, 2039 &vmstate_spapr_cap_ccf_assist, 2040 &vmstate_spapr_cap_fwnmi, 2041 &vmstate_spapr_machine_check, 2042 NULL 2043 } 2044 }; 2045 2046 static int htab_save_setup(QEMUFile *f, void *opaque) 2047 { 2048 SpaprMachineState *spapr = opaque; 2049 2050 /* "Iteration" header */ 2051 if (!spapr->htab_shift) { 2052 qemu_put_be32(f, -1); 2053 } else { 2054 qemu_put_be32(f, spapr->htab_shift); 2055 } 2056 2057 if (spapr->htab) { 2058 spapr->htab_save_index = 0; 2059 spapr->htab_first_pass = true; 2060 } else { 2061 if (spapr->htab_shift) { 2062 assert(kvm_enabled()); 2063 } 2064 } 2065 2066 2067 return 0; 2068 } 2069 2070 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2071 int chunkstart, int n_valid, int n_invalid) 2072 { 2073 qemu_put_be32(f, chunkstart); 2074 qemu_put_be16(f, n_valid); 2075 qemu_put_be16(f, n_invalid); 2076 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2077 HASH_PTE_SIZE_64 * n_valid); 2078 } 2079 2080 static void htab_save_end_marker(QEMUFile *f) 2081 { 2082 qemu_put_be32(f, 0); 2083 qemu_put_be16(f, 0); 2084 qemu_put_be16(f, 0); 2085 } 2086 2087 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2088 int64_t max_ns) 2089 { 2090 bool has_timeout = max_ns != -1; 2091 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2092 int index = spapr->htab_save_index; 2093 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2094 2095 assert(spapr->htab_first_pass); 2096 2097 do { 2098 int chunkstart; 2099 2100 /* Consume invalid HPTEs */ 2101 while ((index < htabslots) 2102 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2103 CLEAN_HPTE(HPTE(spapr->htab, index)); 2104 index++; 2105 } 2106 2107 /* Consume valid HPTEs */ 2108 chunkstart = index; 2109 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2110 && HPTE_VALID(HPTE(spapr->htab, index))) { 2111 CLEAN_HPTE(HPTE(spapr->htab, index)); 2112 index++; 2113 } 2114 2115 if (index > chunkstart) { 2116 int n_valid = index - chunkstart; 2117 2118 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2119 2120 if (has_timeout && 2121 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2122 break; 2123 } 2124 } 2125 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2126 2127 if (index >= htabslots) { 2128 assert(index == htabslots); 2129 index = 0; 2130 spapr->htab_first_pass = false; 2131 } 2132 spapr->htab_save_index = index; 2133 } 2134 2135 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2136 int64_t max_ns) 2137 { 2138 bool final = max_ns < 0; 2139 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2140 int examined = 0, sent = 0; 2141 int index = spapr->htab_save_index; 2142 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2143 2144 assert(!spapr->htab_first_pass); 2145 2146 do { 2147 int chunkstart, invalidstart; 2148 2149 /* Consume non-dirty HPTEs */ 2150 while ((index < htabslots) 2151 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2152 index++; 2153 examined++; 2154 } 2155 2156 chunkstart = index; 2157 /* Consume valid dirty HPTEs */ 2158 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2159 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2160 && HPTE_VALID(HPTE(spapr->htab, index))) { 2161 CLEAN_HPTE(HPTE(spapr->htab, index)); 2162 index++; 2163 examined++; 2164 } 2165 2166 invalidstart = index; 2167 /* Consume invalid dirty HPTEs */ 2168 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2169 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2170 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2171 CLEAN_HPTE(HPTE(spapr->htab, index)); 2172 index++; 2173 examined++; 2174 } 2175 2176 if (index > chunkstart) { 2177 int n_valid = invalidstart - chunkstart; 2178 int n_invalid = index - invalidstart; 2179 2180 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2181 sent += index - chunkstart; 2182 2183 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2184 break; 2185 } 2186 } 2187 2188 if (examined >= htabslots) { 2189 break; 2190 } 2191 2192 if (index >= htabslots) { 2193 assert(index == htabslots); 2194 index = 0; 2195 } 2196 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2197 2198 if (index >= htabslots) { 2199 assert(index == htabslots); 2200 index = 0; 2201 } 2202 2203 spapr->htab_save_index = index; 2204 2205 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2206 } 2207 2208 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2209 #define MAX_KVM_BUF_SIZE 2048 2210 2211 static int htab_save_iterate(QEMUFile *f, void *opaque) 2212 { 2213 SpaprMachineState *spapr = opaque; 2214 int fd; 2215 int rc = 0; 2216 2217 /* Iteration header */ 2218 if (!spapr->htab_shift) { 2219 qemu_put_be32(f, -1); 2220 return 1; 2221 } else { 2222 qemu_put_be32(f, 0); 2223 } 2224 2225 if (!spapr->htab) { 2226 assert(kvm_enabled()); 2227 2228 fd = get_htab_fd(spapr); 2229 if (fd < 0) { 2230 return fd; 2231 } 2232 2233 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2234 if (rc < 0) { 2235 return rc; 2236 } 2237 } else if (spapr->htab_first_pass) { 2238 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2239 } else { 2240 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2241 } 2242 2243 htab_save_end_marker(f); 2244 2245 return rc; 2246 } 2247 2248 static int htab_save_complete(QEMUFile *f, void *opaque) 2249 { 2250 SpaprMachineState *spapr = opaque; 2251 int fd; 2252 2253 /* Iteration header */ 2254 if (!spapr->htab_shift) { 2255 qemu_put_be32(f, -1); 2256 return 0; 2257 } else { 2258 qemu_put_be32(f, 0); 2259 } 2260 2261 if (!spapr->htab) { 2262 int rc; 2263 2264 assert(kvm_enabled()); 2265 2266 fd = get_htab_fd(spapr); 2267 if (fd < 0) { 2268 return fd; 2269 } 2270 2271 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2272 if (rc < 0) { 2273 return rc; 2274 } 2275 } else { 2276 if (spapr->htab_first_pass) { 2277 htab_save_first_pass(f, spapr, -1); 2278 } 2279 htab_save_later_pass(f, spapr, -1); 2280 } 2281 2282 /* End marker */ 2283 htab_save_end_marker(f); 2284 2285 return 0; 2286 } 2287 2288 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2289 { 2290 SpaprMachineState *spapr = opaque; 2291 uint32_t section_hdr; 2292 int fd = -1; 2293 Error *local_err = NULL; 2294 2295 if (version_id < 1 || version_id > 1) { 2296 error_report("htab_load() bad version"); 2297 return -EINVAL; 2298 } 2299 2300 section_hdr = qemu_get_be32(f); 2301 2302 if (section_hdr == -1) { 2303 spapr_free_hpt(spapr); 2304 return 0; 2305 } 2306 2307 if (section_hdr) { 2308 /* First section gives the htab size */ 2309 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2310 if (local_err) { 2311 error_report_err(local_err); 2312 return -EINVAL; 2313 } 2314 return 0; 2315 } 2316 2317 if (!spapr->htab) { 2318 assert(kvm_enabled()); 2319 2320 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2321 if (fd < 0) { 2322 error_report_err(local_err); 2323 return fd; 2324 } 2325 } 2326 2327 while (true) { 2328 uint32_t index; 2329 uint16_t n_valid, n_invalid; 2330 2331 index = qemu_get_be32(f); 2332 n_valid = qemu_get_be16(f); 2333 n_invalid = qemu_get_be16(f); 2334 2335 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2336 /* End of Stream */ 2337 break; 2338 } 2339 2340 if ((index + n_valid + n_invalid) > 2341 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2342 /* Bad index in stream */ 2343 error_report( 2344 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2345 index, n_valid, n_invalid, spapr->htab_shift); 2346 return -EINVAL; 2347 } 2348 2349 if (spapr->htab) { 2350 if (n_valid) { 2351 qemu_get_buffer(f, HPTE(spapr->htab, index), 2352 HASH_PTE_SIZE_64 * n_valid); 2353 } 2354 if (n_invalid) { 2355 memset(HPTE(spapr->htab, index + n_valid), 0, 2356 HASH_PTE_SIZE_64 * n_invalid); 2357 } 2358 } else { 2359 int rc; 2360 2361 assert(fd >= 0); 2362 2363 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2364 if (rc < 0) { 2365 return rc; 2366 } 2367 } 2368 } 2369 2370 if (!spapr->htab) { 2371 assert(fd >= 0); 2372 close(fd); 2373 } 2374 2375 return 0; 2376 } 2377 2378 static void htab_save_cleanup(void *opaque) 2379 { 2380 SpaprMachineState *spapr = opaque; 2381 2382 close_htab_fd(spapr); 2383 } 2384 2385 static SaveVMHandlers savevm_htab_handlers = { 2386 .save_setup = htab_save_setup, 2387 .save_live_iterate = htab_save_iterate, 2388 .save_live_complete_precopy = htab_save_complete, 2389 .save_cleanup = htab_save_cleanup, 2390 .load_state = htab_load, 2391 }; 2392 2393 static void spapr_boot_set(void *opaque, const char *boot_device, 2394 Error **errp) 2395 { 2396 MachineState *machine = MACHINE(opaque); 2397 machine->boot_order = g_strdup(boot_device); 2398 } 2399 2400 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2401 { 2402 MachineState *machine = MACHINE(spapr); 2403 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2404 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2405 int i; 2406 2407 for (i = 0; i < nr_lmbs; i++) { 2408 uint64_t addr; 2409 2410 addr = i * lmb_size + machine->device_memory->base; 2411 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2412 addr / lmb_size); 2413 } 2414 } 2415 2416 /* 2417 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2418 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2419 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2420 */ 2421 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2422 { 2423 int i; 2424 2425 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2426 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2427 " is not aligned to %" PRIu64 " MiB", 2428 machine->ram_size, 2429 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2430 return; 2431 } 2432 2433 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2434 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2435 " is not aligned to %" PRIu64 " MiB", 2436 machine->ram_size, 2437 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2438 return; 2439 } 2440 2441 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2442 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2443 error_setg(errp, 2444 "Node %d memory size 0x%" PRIx64 2445 " is not aligned to %" PRIu64 " MiB", 2446 i, machine->numa_state->nodes[i].node_mem, 2447 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2448 return; 2449 } 2450 } 2451 } 2452 2453 /* find cpu slot in machine->possible_cpus by core_id */ 2454 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2455 { 2456 int index = id / ms->smp.threads; 2457 2458 if (index >= ms->possible_cpus->len) { 2459 return NULL; 2460 } 2461 if (idx) { 2462 *idx = index; 2463 } 2464 return &ms->possible_cpus->cpus[index]; 2465 } 2466 2467 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2468 { 2469 MachineState *ms = MACHINE(spapr); 2470 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2471 Error *local_err = NULL; 2472 bool vsmt_user = !!spapr->vsmt; 2473 int kvm_smt = kvmppc_smt_threads(); 2474 int ret; 2475 unsigned int smp_threads = ms->smp.threads; 2476 2477 if (!kvm_enabled() && (smp_threads > 1)) { 2478 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2479 "on a pseries machine"); 2480 goto out; 2481 } 2482 if (!is_power_of_2(smp_threads)) { 2483 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2484 "machine because it must be a power of 2", smp_threads); 2485 goto out; 2486 } 2487 2488 /* Detemine the VSMT mode to use: */ 2489 if (vsmt_user) { 2490 if (spapr->vsmt < smp_threads) { 2491 error_setg(&local_err, "Cannot support VSMT mode %d" 2492 " because it must be >= threads/core (%d)", 2493 spapr->vsmt, smp_threads); 2494 goto out; 2495 } 2496 /* In this case, spapr->vsmt has been set by the command line */ 2497 } else if (!smc->smp_threads_vsmt) { 2498 /* 2499 * Default VSMT value is tricky, because we need it to be as 2500 * consistent as possible (for migration), but this requires 2501 * changing it for at least some existing cases. We pick 8 as 2502 * the value that we'd get with KVM on POWER8, the 2503 * overwhelmingly common case in production systems. 2504 */ 2505 spapr->vsmt = MAX(8, smp_threads); 2506 } else { 2507 spapr->vsmt = smp_threads; 2508 } 2509 2510 /* KVM: If necessary, set the SMT mode: */ 2511 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2512 ret = kvmppc_set_smt_threads(spapr->vsmt); 2513 if (ret) { 2514 /* Looks like KVM isn't able to change VSMT mode */ 2515 error_setg(&local_err, 2516 "Failed to set KVM's VSMT mode to %d (errno %d)", 2517 spapr->vsmt, ret); 2518 /* We can live with that if the default one is big enough 2519 * for the number of threads, and a submultiple of the one 2520 * we want. In this case we'll waste some vcpu ids, but 2521 * behaviour will be correct */ 2522 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2523 warn_report_err(local_err); 2524 local_err = NULL; 2525 goto out; 2526 } else { 2527 if (!vsmt_user) { 2528 error_append_hint(&local_err, 2529 "On PPC, a VM with %d threads/core" 2530 " on a host with %d threads/core" 2531 " requires the use of VSMT mode %d.\n", 2532 smp_threads, kvm_smt, spapr->vsmt); 2533 } 2534 kvmppc_error_append_smt_possible_hint(&local_err); 2535 goto out; 2536 } 2537 } 2538 } 2539 /* else TCG: nothing to do currently */ 2540 out: 2541 error_propagate(errp, local_err); 2542 } 2543 2544 static void spapr_init_cpus(SpaprMachineState *spapr) 2545 { 2546 MachineState *machine = MACHINE(spapr); 2547 MachineClass *mc = MACHINE_GET_CLASS(machine); 2548 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2549 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2550 const CPUArchIdList *possible_cpus; 2551 unsigned int smp_cpus = machine->smp.cpus; 2552 unsigned int smp_threads = machine->smp.threads; 2553 unsigned int max_cpus = machine->smp.max_cpus; 2554 int boot_cores_nr = smp_cpus / smp_threads; 2555 int i; 2556 2557 possible_cpus = mc->possible_cpu_arch_ids(machine); 2558 if (mc->has_hotpluggable_cpus) { 2559 if (smp_cpus % smp_threads) { 2560 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2561 smp_cpus, smp_threads); 2562 exit(1); 2563 } 2564 if (max_cpus % smp_threads) { 2565 error_report("max_cpus (%u) must be multiple of threads (%u)", 2566 max_cpus, smp_threads); 2567 exit(1); 2568 } 2569 } else { 2570 if (max_cpus != smp_cpus) { 2571 error_report("This machine version does not support CPU hotplug"); 2572 exit(1); 2573 } 2574 boot_cores_nr = possible_cpus->len; 2575 } 2576 2577 if (smc->pre_2_10_has_unused_icps) { 2578 int i; 2579 2580 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2581 /* Dummy entries get deregistered when real ICPState objects 2582 * are registered during CPU core hotplug. 2583 */ 2584 pre_2_10_vmstate_register_dummy_icp(i); 2585 } 2586 } 2587 2588 for (i = 0; i < possible_cpus->len; i++) { 2589 int core_id = i * smp_threads; 2590 2591 if (mc->has_hotpluggable_cpus) { 2592 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2593 spapr_vcpu_id(spapr, core_id)); 2594 } 2595 2596 if (i < boot_cores_nr) { 2597 Object *core = object_new(type); 2598 int nr_threads = smp_threads; 2599 2600 /* Handle the partially filled core for older machine types */ 2601 if ((i + 1) * smp_threads >= smp_cpus) { 2602 nr_threads = smp_cpus - i * smp_threads; 2603 } 2604 2605 object_property_set_int(core, nr_threads, "nr-threads", 2606 &error_fatal); 2607 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2608 &error_fatal); 2609 object_property_set_bool(core, true, "realized", &error_fatal); 2610 2611 object_unref(core); 2612 } 2613 } 2614 } 2615 2616 static PCIHostState *spapr_create_default_phb(void) 2617 { 2618 DeviceState *dev; 2619 2620 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); 2621 qdev_prop_set_uint32(dev, "index", 0); 2622 qdev_init_nofail(dev); 2623 2624 return PCI_HOST_BRIDGE(dev); 2625 } 2626 2627 /* pSeries LPAR / sPAPR hardware init */ 2628 static void spapr_machine_init(MachineState *machine) 2629 { 2630 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2631 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2632 const char *kernel_filename = machine->kernel_filename; 2633 const char *initrd_filename = machine->initrd_filename; 2634 PCIHostState *phb; 2635 int i; 2636 MemoryRegion *sysmem = get_system_memory(); 2637 hwaddr node0_size = spapr_node0_size(machine); 2638 long load_limit, fw_size; 2639 char *filename; 2640 Error *resize_hpt_err = NULL; 2641 2642 msi_nonbroken = true; 2643 2644 QLIST_INIT(&spapr->phbs); 2645 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2646 2647 /* Determine capabilities to run with */ 2648 spapr_caps_init(spapr); 2649 2650 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2651 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2652 /* 2653 * If the user explicitly requested a mode we should either 2654 * supply it, or fail completely (which we do below). But if 2655 * it's not set explicitly, we reset our mode to something 2656 * that works 2657 */ 2658 if (resize_hpt_err) { 2659 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2660 error_free(resize_hpt_err); 2661 resize_hpt_err = NULL; 2662 } else { 2663 spapr->resize_hpt = smc->resize_hpt_default; 2664 } 2665 } 2666 2667 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2668 2669 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2670 /* 2671 * User requested HPT resize, but this host can't supply it. Bail out 2672 */ 2673 error_report_err(resize_hpt_err); 2674 exit(1); 2675 } 2676 2677 spapr->rma_size = node0_size; 2678 2679 /* With KVM, we don't actually know whether KVM supports an 2680 * unbounded RMA (PR KVM) or is limited by the hash table size 2681 * (HV KVM using VRMA), so we always assume the latter 2682 * 2683 * In that case, we also limit the initial allocations for RTAS 2684 * etc... to 256M since we have no way to know what the VRMA size 2685 * is going to be as it depends on the size of the hash table 2686 * which isn't determined yet. 2687 */ 2688 if (kvm_enabled()) { 2689 spapr->vrma_adjust = 1; 2690 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2691 } 2692 2693 /* Actually we don't support unbounded RMA anymore since we added 2694 * proper emulation of HV mode. The max we can get is 16G which 2695 * also happens to be what we configure for PAPR mode so make sure 2696 * we don't do anything bigger than that 2697 */ 2698 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2699 2700 if (spapr->rma_size > node0_size) { 2701 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2702 spapr->rma_size); 2703 exit(1); 2704 } 2705 2706 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2707 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2708 2709 /* 2710 * VSMT must be set in order to be able to compute VCPU ids, ie to 2711 * call spapr_max_server_number() or spapr_vcpu_id(). 2712 */ 2713 spapr_set_vsmt_mode(spapr, &error_fatal); 2714 2715 /* Set up Interrupt Controller before we create the VCPUs */ 2716 spapr_irq_init(spapr, &error_fatal); 2717 2718 /* Set up containers for ibm,client-architecture-support negotiated options 2719 */ 2720 spapr->ov5 = spapr_ovec_new(); 2721 spapr->ov5_cas = spapr_ovec_new(); 2722 2723 if (smc->dr_lmb_enabled) { 2724 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2725 spapr_validate_node_memory(machine, &error_fatal); 2726 } 2727 2728 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2729 2730 /* advertise support for dedicated HP event source to guests */ 2731 if (spapr->use_hotplug_event_source) { 2732 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2733 } 2734 2735 /* advertise support for HPT resizing */ 2736 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2737 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2738 } 2739 2740 /* advertise support for ibm,dyamic-memory-v2 */ 2741 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2742 2743 /* advertise XIVE on POWER9 machines */ 2744 if (spapr->irq->xive) { 2745 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2746 } 2747 2748 /* init CPUs */ 2749 spapr_init_cpus(spapr); 2750 2751 /* 2752 * check we don't have a memory-less/cpu-less NUMA node 2753 * Firmware relies on the existing memory/cpu topology to provide the 2754 * NUMA topology to the kernel. 2755 * And the linux kernel needs to know the NUMA topology at start 2756 * to be able to hotplug CPUs later. 2757 */ 2758 if (machine->numa_state->num_nodes) { 2759 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2760 /* check for memory-less node */ 2761 if (machine->numa_state->nodes[i].node_mem == 0) { 2762 CPUState *cs; 2763 int found = 0; 2764 /* check for cpu-less node */ 2765 CPU_FOREACH(cs) { 2766 PowerPCCPU *cpu = POWERPC_CPU(cs); 2767 if (cpu->node_id == i) { 2768 found = 1; 2769 break; 2770 } 2771 } 2772 /* memory-less and cpu-less node */ 2773 if (!found) { 2774 error_report( 2775 "Memory-less/cpu-less nodes are not supported (node %d)", 2776 i); 2777 exit(1); 2778 } 2779 } 2780 } 2781 2782 } 2783 2784 /* 2785 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. 2786 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is 2787 * called from vPHB reset handler so we initialize the counter here. 2788 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM 2789 * must be equally distant from any other node. 2790 * The final value of spapr->gpu_numa_id is going to be written to 2791 * max-associativity-domains in spapr_build_fdt(). 2792 */ 2793 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes); 2794 2795 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2796 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2797 spapr->max_compat_pvr)) { 2798 /* KVM and TCG always allow GTSE with radix... */ 2799 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2800 } 2801 /* ... but not with hash (currently). */ 2802 2803 if (kvm_enabled()) { 2804 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2805 kvmppc_enable_logical_ci_hcalls(); 2806 kvmppc_enable_set_mode_hcall(); 2807 2808 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2809 kvmppc_enable_clear_ref_mod_hcalls(); 2810 2811 /* Enable H_PAGE_INIT */ 2812 kvmppc_enable_h_page_init(); 2813 } 2814 2815 /* map RAM */ 2816 memory_region_add_subregion(sysmem, 0, machine->ram); 2817 2818 /* always allocate the device memory information */ 2819 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2820 2821 /* initialize hotplug memory address space */ 2822 if (machine->ram_size < machine->maxram_size) { 2823 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2824 /* 2825 * Limit the number of hotpluggable memory slots to half the number 2826 * slots that KVM supports, leaving the other half for PCI and other 2827 * devices. However ensure that number of slots doesn't drop below 32. 2828 */ 2829 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2830 SPAPR_MAX_RAM_SLOTS; 2831 2832 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2833 max_memslots = SPAPR_MAX_RAM_SLOTS; 2834 } 2835 if (machine->ram_slots > max_memslots) { 2836 error_report("Specified number of memory slots %" 2837 PRIu64" exceeds max supported %d", 2838 machine->ram_slots, max_memslots); 2839 exit(1); 2840 } 2841 2842 machine->device_memory->base = ROUND_UP(machine->ram_size, 2843 SPAPR_DEVICE_MEM_ALIGN); 2844 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2845 "device-memory", device_mem_size); 2846 memory_region_add_subregion(sysmem, machine->device_memory->base, 2847 &machine->device_memory->mr); 2848 } 2849 2850 if (smc->dr_lmb_enabled) { 2851 spapr_create_lmb_dr_connectors(spapr); 2852 } 2853 2854 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI_MCE) == SPAPR_CAP_ON) { 2855 /* Create the error string for live migration blocker */ 2856 error_setg(&spapr->fwnmi_migration_blocker, 2857 "A machine check is being handled during migration. The handler" 2858 "may run and log hardware error on the destination"); 2859 } 2860 2861 /* Set up RTAS event infrastructure */ 2862 spapr_events_init(spapr); 2863 2864 /* Set up the RTC RTAS interfaces */ 2865 spapr_rtc_create(spapr); 2866 2867 /* Set up VIO bus */ 2868 spapr->vio_bus = spapr_vio_bus_init(); 2869 2870 for (i = 0; i < serial_max_hds(); i++) { 2871 if (serial_hd(i)) { 2872 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2873 } 2874 } 2875 2876 /* We always have at least the nvram device on VIO */ 2877 spapr_create_nvram(spapr); 2878 2879 /* 2880 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2881 * connectors (described in root DT node's "ibm,drc-types" property) 2882 * are pre-initialized here. additional child connectors (such as 2883 * connectors for a PHBs PCI slots) are added as needed during their 2884 * parent's realization. 2885 */ 2886 if (smc->dr_phb_enabled) { 2887 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2888 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2889 } 2890 } 2891 2892 /* Set up PCI */ 2893 spapr_pci_rtas_init(); 2894 2895 phb = spapr_create_default_phb(); 2896 2897 for (i = 0; i < nb_nics; i++) { 2898 NICInfo *nd = &nd_table[i]; 2899 2900 if (!nd->model) { 2901 nd->model = g_strdup("spapr-vlan"); 2902 } 2903 2904 if (g_str_equal(nd->model, "spapr-vlan") || 2905 g_str_equal(nd->model, "ibmveth")) { 2906 spapr_vlan_create(spapr->vio_bus, nd); 2907 } else { 2908 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2909 } 2910 } 2911 2912 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2913 spapr_vscsi_create(spapr->vio_bus); 2914 } 2915 2916 /* Graphics */ 2917 if (spapr_vga_init(phb->bus, &error_fatal)) { 2918 spapr->has_graphics = true; 2919 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2920 } 2921 2922 if (machine->usb) { 2923 if (smc->use_ohci_by_default) { 2924 pci_create_simple(phb->bus, -1, "pci-ohci"); 2925 } else { 2926 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2927 } 2928 2929 if (spapr->has_graphics) { 2930 USBBus *usb_bus = usb_bus_find(-1); 2931 2932 usb_create_simple(usb_bus, "usb-kbd"); 2933 usb_create_simple(usb_bus, "usb-mouse"); 2934 } 2935 } 2936 2937 if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) { 2938 error_report( 2939 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2940 MIN_RMA_SLOF); 2941 exit(1); 2942 } 2943 2944 if (kernel_filename) { 2945 uint64_t lowaddr = 0; 2946 2947 spapr->kernel_size = load_elf(kernel_filename, NULL, 2948 translate_kernel_address, NULL, 2949 NULL, &lowaddr, NULL, NULL, 1, 2950 PPC_ELF_MACHINE, 0, 0); 2951 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2952 spapr->kernel_size = load_elf(kernel_filename, NULL, 2953 translate_kernel_address, NULL, NULL, 2954 &lowaddr, NULL, NULL, 0, 2955 PPC_ELF_MACHINE, 0, 0); 2956 spapr->kernel_le = spapr->kernel_size > 0; 2957 } 2958 if (spapr->kernel_size < 0) { 2959 error_report("error loading %s: %s", kernel_filename, 2960 load_elf_strerror(spapr->kernel_size)); 2961 exit(1); 2962 } 2963 2964 /* load initrd */ 2965 if (initrd_filename) { 2966 /* Try to locate the initrd in the gap between the kernel 2967 * and the firmware. Add a bit of space just in case 2968 */ 2969 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2970 + 0x1ffff) & ~0xffff; 2971 spapr->initrd_size = load_image_targphys(initrd_filename, 2972 spapr->initrd_base, 2973 load_limit 2974 - spapr->initrd_base); 2975 if (spapr->initrd_size < 0) { 2976 error_report("could not load initial ram disk '%s'", 2977 initrd_filename); 2978 exit(1); 2979 } 2980 } 2981 } 2982 2983 if (bios_name == NULL) { 2984 bios_name = FW_FILE_NAME; 2985 } 2986 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2987 if (!filename) { 2988 error_report("Could not find LPAR firmware '%s'", bios_name); 2989 exit(1); 2990 } 2991 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2992 if (fw_size <= 0) { 2993 error_report("Could not load LPAR firmware '%s'", filename); 2994 exit(1); 2995 } 2996 g_free(filename); 2997 2998 /* FIXME: Should register things through the MachineState's qdev 2999 * interface, this is a legacy from the sPAPREnvironment structure 3000 * which predated MachineState but had a similar function */ 3001 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3002 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3003 &savevm_htab_handlers, spapr); 3004 3005 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine), 3006 &error_fatal); 3007 3008 qemu_register_boot_set(spapr_boot_set, spapr); 3009 3010 /* 3011 * Nothing needs to be done to resume a suspended guest because 3012 * suspending does not change the machine state, so no need for 3013 * a ->wakeup method. 3014 */ 3015 qemu_register_wakeup_support(); 3016 3017 if (kvm_enabled()) { 3018 /* to stop and start vmclock */ 3019 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3020 &spapr->tb); 3021 3022 kvmppc_spapr_enable_inkernel_multitce(); 3023 } 3024 3025 qemu_cond_init(&spapr->mc_delivery_cond); 3026 } 3027 3028 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3029 { 3030 if (!vm_type) { 3031 return 0; 3032 } 3033 3034 if (!strcmp(vm_type, "HV")) { 3035 return 1; 3036 } 3037 3038 if (!strcmp(vm_type, "PR")) { 3039 return 2; 3040 } 3041 3042 error_report("Unknown kvm-type specified '%s'", vm_type); 3043 exit(1); 3044 } 3045 3046 /* 3047 * Implementation of an interface to adjust firmware path 3048 * for the bootindex property handling. 3049 */ 3050 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3051 DeviceState *dev) 3052 { 3053 #define CAST(type, obj, name) \ 3054 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3055 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3056 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3057 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3058 3059 if (d) { 3060 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3061 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3062 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3063 3064 if (spapr) { 3065 /* 3066 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3067 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3068 * 0x8000 | (target << 8) | (bus << 5) | lun 3069 * (see the "Logical unit addressing format" table in SAM5) 3070 */ 3071 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3072 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3073 (uint64_t)id << 48); 3074 } else if (virtio) { 3075 /* 3076 * We use SRP luns of the form 01000000 | (target << 8) | lun 3077 * in the top 32 bits of the 64-bit LUN 3078 * Note: the quote above is from SLOF and it is wrong, 3079 * the actual binding is: 3080 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3081 */ 3082 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3083 if (d->lun >= 256) { 3084 /* Use the LUN "flat space addressing method" */ 3085 id |= 0x4000; 3086 } 3087 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3088 (uint64_t)id << 32); 3089 } else if (usb) { 3090 /* 3091 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3092 * in the top 32 bits of the 64-bit LUN 3093 */ 3094 unsigned usb_port = atoi(usb->port->path); 3095 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3096 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3097 (uint64_t)id << 32); 3098 } 3099 } 3100 3101 /* 3102 * SLOF probes the USB devices, and if it recognizes that the device is a 3103 * storage device, it changes its name to "storage" instead of "usb-host", 3104 * and additionally adds a child node for the SCSI LUN, so the correct 3105 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3106 */ 3107 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3108 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3109 if (usb_host_dev_is_scsi_storage(usbdev)) { 3110 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3111 } 3112 } 3113 3114 if (phb) { 3115 /* Replace "pci" with "pci@800000020000000" */ 3116 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3117 } 3118 3119 if (vsc) { 3120 /* Same logic as virtio above */ 3121 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3122 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3123 } 3124 3125 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3126 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3127 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3128 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3129 } 3130 3131 return NULL; 3132 } 3133 3134 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3135 { 3136 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3137 3138 return g_strdup(spapr->kvm_type); 3139 } 3140 3141 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3142 { 3143 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3144 3145 g_free(spapr->kvm_type); 3146 spapr->kvm_type = g_strdup(value); 3147 } 3148 3149 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3150 { 3151 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3152 3153 return spapr->use_hotplug_event_source; 3154 } 3155 3156 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3157 Error **errp) 3158 { 3159 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3160 3161 spapr->use_hotplug_event_source = value; 3162 } 3163 3164 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3165 { 3166 return true; 3167 } 3168 3169 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3170 { 3171 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3172 3173 switch (spapr->resize_hpt) { 3174 case SPAPR_RESIZE_HPT_DEFAULT: 3175 return g_strdup("default"); 3176 case SPAPR_RESIZE_HPT_DISABLED: 3177 return g_strdup("disabled"); 3178 case SPAPR_RESIZE_HPT_ENABLED: 3179 return g_strdup("enabled"); 3180 case SPAPR_RESIZE_HPT_REQUIRED: 3181 return g_strdup("required"); 3182 } 3183 g_assert_not_reached(); 3184 } 3185 3186 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3187 { 3188 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3189 3190 if (strcmp(value, "default") == 0) { 3191 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3192 } else if (strcmp(value, "disabled") == 0) { 3193 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3194 } else if (strcmp(value, "enabled") == 0) { 3195 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3196 } else if (strcmp(value, "required") == 0) { 3197 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3198 } else { 3199 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3200 } 3201 } 3202 3203 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 3204 void *opaque, Error **errp) 3205 { 3206 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3207 } 3208 3209 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 3210 void *opaque, Error **errp) 3211 { 3212 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3213 } 3214 3215 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3216 { 3217 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3218 3219 if (spapr->irq == &spapr_irq_xics_legacy) { 3220 return g_strdup("legacy"); 3221 } else if (spapr->irq == &spapr_irq_xics) { 3222 return g_strdup("xics"); 3223 } else if (spapr->irq == &spapr_irq_xive) { 3224 return g_strdup("xive"); 3225 } else if (spapr->irq == &spapr_irq_dual) { 3226 return g_strdup("dual"); 3227 } 3228 g_assert_not_reached(); 3229 } 3230 3231 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3232 { 3233 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3234 3235 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3236 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3237 return; 3238 } 3239 3240 /* The legacy IRQ backend can not be set */ 3241 if (strcmp(value, "xics") == 0) { 3242 spapr->irq = &spapr_irq_xics; 3243 } else if (strcmp(value, "xive") == 0) { 3244 spapr->irq = &spapr_irq_xive; 3245 } else if (strcmp(value, "dual") == 0) { 3246 spapr->irq = &spapr_irq_dual; 3247 } else { 3248 error_setg(errp, "Bad value for \"ic-mode\" property"); 3249 } 3250 } 3251 3252 static char *spapr_get_host_model(Object *obj, Error **errp) 3253 { 3254 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3255 3256 return g_strdup(spapr->host_model); 3257 } 3258 3259 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3260 { 3261 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3262 3263 g_free(spapr->host_model); 3264 spapr->host_model = g_strdup(value); 3265 } 3266 3267 static char *spapr_get_host_serial(Object *obj, Error **errp) 3268 { 3269 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3270 3271 return g_strdup(spapr->host_serial); 3272 } 3273 3274 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3275 { 3276 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3277 3278 g_free(spapr->host_serial); 3279 spapr->host_serial = g_strdup(value); 3280 } 3281 3282 static void spapr_instance_init(Object *obj) 3283 { 3284 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3285 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3286 3287 spapr->htab_fd = -1; 3288 spapr->use_hotplug_event_source = true; 3289 object_property_add_str(obj, "kvm-type", 3290 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 3291 object_property_set_description(obj, "kvm-type", 3292 "Specifies the KVM virtualization mode (HV, PR)", 3293 NULL); 3294 object_property_add_bool(obj, "modern-hotplug-events", 3295 spapr_get_modern_hotplug_events, 3296 spapr_set_modern_hotplug_events, 3297 NULL); 3298 object_property_set_description(obj, "modern-hotplug-events", 3299 "Use dedicated hotplug event mechanism in" 3300 " place of standard EPOW events when possible" 3301 " (required for memory hot-unplug support)", 3302 NULL); 3303 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3304 "Maximum permitted CPU compatibility mode", 3305 &error_fatal); 3306 3307 object_property_add_str(obj, "resize-hpt", 3308 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 3309 object_property_set_description(obj, "resize-hpt", 3310 "Resizing of the Hash Page Table (enabled, disabled, required)", 3311 NULL); 3312 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 3313 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 3314 object_property_set_description(obj, "vsmt", 3315 "Virtual SMT: KVM behaves as if this were" 3316 " the host's SMT mode", &error_abort); 3317 object_property_add_bool(obj, "vfio-no-msix-emulation", 3318 spapr_get_msix_emulation, NULL, NULL); 3319 3320 /* The machine class defines the default interrupt controller mode */ 3321 spapr->irq = smc->irq; 3322 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3323 spapr_set_ic_mode, NULL); 3324 object_property_set_description(obj, "ic-mode", 3325 "Specifies the interrupt controller mode (xics, xive, dual)", 3326 NULL); 3327 3328 object_property_add_str(obj, "host-model", 3329 spapr_get_host_model, spapr_set_host_model, 3330 &error_abort); 3331 object_property_set_description(obj, "host-model", 3332 "Host model to advertise in guest device tree", &error_abort); 3333 object_property_add_str(obj, "host-serial", 3334 spapr_get_host_serial, spapr_set_host_serial, 3335 &error_abort); 3336 object_property_set_description(obj, "host-serial", 3337 "Host serial number to advertise in guest device tree", &error_abort); 3338 } 3339 3340 static void spapr_machine_finalizefn(Object *obj) 3341 { 3342 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3343 3344 g_free(spapr->kvm_type); 3345 } 3346 3347 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3348 { 3349 cpu_synchronize_state(cs); 3350 ppc_cpu_do_system_reset(cs); 3351 } 3352 3353 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3354 { 3355 CPUState *cs; 3356 3357 CPU_FOREACH(cs) { 3358 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3359 } 3360 } 3361 3362 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3363 void *fdt, int *fdt_start_offset, Error **errp) 3364 { 3365 uint64_t addr; 3366 uint32_t node; 3367 3368 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3369 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3370 &error_abort); 3371 *fdt_start_offset = spapr_populate_memory_node(fdt, node, addr, 3372 SPAPR_MEMORY_BLOCK_SIZE); 3373 return 0; 3374 } 3375 3376 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3377 bool dedicated_hp_event_source, Error **errp) 3378 { 3379 SpaprDrc *drc; 3380 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3381 int i; 3382 uint64_t addr = addr_start; 3383 bool hotplugged = spapr_drc_hotplugged(dev); 3384 Error *local_err = NULL; 3385 3386 for (i = 0; i < nr_lmbs; i++) { 3387 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3388 addr / SPAPR_MEMORY_BLOCK_SIZE); 3389 g_assert(drc); 3390 3391 spapr_drc_attach(drc, dev, &local_err); 3392 if (local_err) { 3393 while (addr > addr_start) { 3394 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3395 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3396 addr / SPAPR_MEMORY_BLOCK_SIZE); 3397 spapr_drc_detach(drc); 3398 } 3399 error_propagate(errp, local_err); 3400 return; 3401 } 3402 if (!hotplugged) { 3403 spapr_drc_reset(drc); 3404 } 3405 addr += SPAPR_MEMORY_BLOCK_SIZE; 3406 } 3407 /* send hotplug notification to the 3408 * guest only in case of hotplugged memory 3409 */ 3410 if (hotplugged) { 3411 if (dedicated_hp_event_source) { 3412 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3413 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3414 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3415 nr_lmbs, 3416 spapr_drc_index(drc)); 3417 } else { 3418 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3419 nr_lmbs); 3420 } 3421 } 3422 } 3423 3424 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3425 Error **errp) 3426 { 3427 Error *local_err = NULL; 3428 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3429 PCDIMMDevice *dimm = PC_DIMM(dev); 3430 uint64_t size, addr; 3431 3432 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3433 3434 pc_dimm_plug(dimm, MACHINE(ms), &local_err); 3435 if (local_err) { 3436 goto out; 3437 } 3438 3439 addr = object_property_get_uint(OBJECT(dimm), 3440 PC_DIMM_ADDR_PROP, &local_err); 3441 if (local_err) { 3442 goto out_unplug; 3443 } 3444 3445 spapr_add_lmbs(dev, addr, size, spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3446 &local_err); 3447 if (local_err) { 3448 goto out_unplug; 3449 } 3450 3451 return; 3452 3453 out_unplug: 3454 pc_dimm_unplug(dimm, MACHINE(ms)); 3455 out: 3456 error_propagate(errp, local_err); 3457 } 3458 3459 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3460 Error **errp) 3461 { 3462 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3463 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3464 PCDIMMDevice *dimm = PC_DIMM(dev); 3465 Error *local_err = NULL; 3466 uint64_t size; 3467 Object *memdev; 3468 hwaddr pagesize; 3469 3470 if (!smc->dr_lmb_enabled) { 3471 error_setg(errp, "Memory hotplug not supported for this machine"); 3472 return; 3473 } 3474 3475 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3476 if (local_err) { 3477 error_propagate(errp, local_err); 3478 return; 3479 } 3480 3481 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3482 error_setg(errp, "Hotplugged memory size must be a multiple of " 3483 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3484 return; 3485 } 3486 3487 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3488 &error_abort); 3489 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3490 spapr_check_pagesize(spapr, pagesize, &local_err); 3491 if (local_err) { 3492 error_propagate(errp, local_err); 3493 return; 3494 } 3495 3496 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3497 } 3498 3499 struct SpaprDimmState { 3500 PCDIMMDevice *dimm; 3501 uint32_t nr_lmbs; 3502 QTAILQ_ENTRY(SpaprDimmState) next; 3503 }; 3504 3505 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3506 PCDIMMDevice *dimm) 3507 { 3508 SpaprDimmState *dimm_state = NULL; 3509 3510 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3511 if (dimm_state->dimm == dimm) { 3512 break; 3513 } 3514 } 3515 return dimm_state; 3516 } 3517 3518 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3519 uint32_t nr_lmbs, 3520 PCDIMMDevice *dimm) 3521 { 3522 SpaprDimmState *ds = NULL; 3523 3524 /* 3525 * If this request is for a DIMM whose removal had failed earlier 3526 * (due to guest's refusal to remove the LMBs), we would have this 3527 * dimm already in the pending_dimm_unplugs list. In that 3528 * case don't add again. 3529 */ 3530 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3531 if (!ds) { 3532 ds = g_malloc0(sizeof(SpaprDimmState)); 3533 ds->nr_lmbs = nr_lmbs; 3534 ds->dimm = dimm; 3535 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3536 } 3537 return ds; 3538 } 3539 3540 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3541 SpaprDimmState *dimm_state) 3542 { 3543 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3544 g_free(dimm_state); 3545 } 3546 3547 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3548 PCDIMMDevice *dimm) 3549 { 3550 SpaprDrc *drc; 3551 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3552 &error_abort); 3553 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3554 uint32_t avail_lmbs = 0; 3555 uint64_t addr_start, addr; 3556 int i; 3557 3558 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3559 &error_abort); 3560 3561 addr = addr_start; 3562 for (i = 0; i < nr_lmbs; i++) { 3563 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3564 addr / SPAPR_MEMORY_BLOCK_SIZE); 3565 g_assert(drc); 3566 if (drc->dev) { 3567 avail_lmbs++; 3568 } 3569 addr += SPAPR_MEMORY_BLOCK_SIZE; 3570 } 3571 3572 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3573 } 3574 3575 /* Callback to be called during DRC release. */ 3576 void spapr_lmb_release(DeviceState *dev) 3577 { 3578 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3579 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3580 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3581 3582 /* This information will get lost if a migration occurs 3583 * during the unplug process. In this case recover it. */ 3584 if (ds == NULL) { 3585 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3586 g_assert(ds); 3587 /* The DRC being examined by the caller at least must be counted */ 3588 g_assert(ds->nr_lmbs); 3589 } 3590 3591 if (--ds->nr_lmbs) { 3592 return; 3593 } 3594 3595 /* 3596 * Now that all the LMBs have been removed by the guest, call the 3597 * unplug handler chain. This can never fail. 3598 */ 3599 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3600 object_unparent(OBJECT(dev)); 3601 } 3602 3603 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3604 { 3605 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3606 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3607 3608 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3609 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3610 spapr_pending_dimm_unplugs_remove(spapr, ds); 3611 } 3612 3613 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3614 DeviceState *dev, Error **errp) 3615 { 3616 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3617 Error *local_err = NULL; 3618 PCDIMMDevice *dimm = PC_DIMM(dev); 3619 uint32_t nr_lmbs; 3620 uint64_t size, addr_start, addr; 3621 int i; 3622 SpaprDrc *drc; 3623 3624 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3625 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3626 3627 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3628 &local_err); 3629 if (local_err) { 3630 goto out; 3631 } 3632 3633 /* 3634 * An existing pending dimm state for this DIMM means that there is an 3635 * unplug operation in progress, waiting for the spapr_lmb_release 3636 * callback to complete the job (BQL can't cover that far). In this case, 3637 * bail out to avoid detaching DRCs that were already released. 3638 */ 3639 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3640 error_setg(&local_err, 3641 "Memory unplug already in progress for device %s", 3642 dev->id); 3643 goto out; 3644 } 3645 3646 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3647 3648 addr = addr_start; 3649 for (i = 0; i < nr_lmbs; i++) { 3650 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3651 addr / SPAPR_MEMORY_BLOCK_SIZE); 3652 g_assert(drc); 3653 3654 spapr_drc_detach(drc); 3655 addr += SPAPR_MEMORY_BLOCK_SIZE; 3656 } 3657 3658 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3659 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3660 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3661 nr_lmbs, spapr_drc_index(drc)); 3662 out: 3663 error_propagate(errp, local_err); 3664 } 3665 3666 /* Callback to be called during DRC release. */ 3667 void spapr_core_release(DeviceState *dev) 3668 { 3669 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3670 3671 /* Call the unplug handler chain. This can never fail. */ 3672 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3673 object_unparent(OBJECT(dev)); 3674 } 3675 3676 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3677 { 3678 MachineState *ms = MACHINE(hotplug_dev); 3679 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3680 CPUCore *cc = CPU_CORE(dev); 3681 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3682 3683 if (smc->pre_2_10_has_unused_icps) { 3684 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3685 int i; 3686 3687 for (i = 0; i < cc->nr_threads; i++) { 3688 CPUState *cs = CPU(sc->threads[i]); 3689 3690 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3691 } 3692 } 3693 3694 assert(core_slot); 3695 core_slot->cpu = NULL; 3696 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3697 } 3698 3699 static 3700 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3701 Error **errp) 3702 { 3703 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3704 int index; 3705 SpaprDrc *drc; 3706 CPUCore *cc = CPU_CORE(dev); 3707 3708 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3709 error_setg(errp, "Unable to find CPU core with core-id: %d", 3710 cc->core_id); 3711 return; 3712 } 3713 if (index == 0) { 3714 error_setg(errp, "Boot CPU core may not be unplugged"); 3715 return; 3716 } 3717 3718 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3719 spapr_vcpu_id(spapr, cc->core_id)); 3720 g_assert(drc); 3721 3722 if (!spapr_drc_unplug_requested(drc)) { 3723 spapr_drc_detach(drc); 3724 spapr_hotplug_req_remove_by_index(drc); 3725 } 3726 } 3727 3728 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3729 void *fdt, int *fdt_start_offset, Error **errp) 3730 { 3731 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3732 CPUState *cs = CPU(core->threads[0]); 3733 PowerPCCPU *cpu = POWERPC_CPU(cs); 3734 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3735 int id = spapr_get_vcpu_id(cpu); 3736 char *nodename; 3737 int offset; 3738 3739 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3740 offset = fdt_add_subnode(fdt, 0, nodename); 3741 g_free(nodename); 3742 3743 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3744 3745 *fdt_start_offset = offset; 3746 return 0; 3747 } 3748 3749 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3750 Error **errp) 3751 { 3752 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3753 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3754 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3755 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3756 CPUCore *cc = CPU_CORE(dev); 3757 CPUState *cs; 3758 SpaprDrc *drc; 3759 Error *local_err = NULL; 3760 CPUArchId *core_slot; 3761 int index; 3762 bool hotplugged = spapr_drc_hotplugged(dev); 3763 int i; 3764 3765 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3766 if (!core_slot) { 3767 error_setg(errp, "Unable to find CPU core with core-id: %d", 3768 cc->core_id); 3769 return; 3770 } 3771 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3772 spapr_vcpu_id(spapr, cc->core_id)); 3773 3774 g_assert(drc || !mc->has_hotpluggable_cpus); 3775 3776 if (drc) { 3777 spapr_drc_attach(drc, dev, &local_err); 3778 if (local_err) { 3779 error_propagate(errp, local_err); 3780 return; 3781 } 3782 3783 if (hotplugged) { 3784 /* 3785 * Send hotplug notification interrupt to the guest only 3786 * in case of hotplugged CPUs. 3787 */ 3788 spapr_hotplug_req_add_by_index(drc); 3789 } else { 3790 spapr_drc_reset(drc); 3791 } 3792 } 3793 3794 core_slot->cpu = OBJECT(dev); 3795 3796 if (smc->pre_2_10_has_unused_icps) { 3797 for (i = 0; i < cc->nr_threads; i++) { 3798 cs = CPU(core->threads[i]); 3799 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3800 } 3801 } 3802 3803 /* 3804 * Set compatibility mode to match the boot CPU, which was either set 3805 * by the machine reset code or by CAS. 3806 */ 3807 if (hotplugged) { 3808 for (i = 0; i < cc->nr_threads; i++) { 3809 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3810 &local_err); 3811 if (local_err) { 3812 error_propagate(errp, local_err); 3813 return; 3814 } 3815 } 3816 } 3817 } 3818 3819 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3820 Error **errp) 3821 { 3822 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3823 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3824 Error *local_err = NULL; 3825 CPUCore *cc = CPU_CORE(dev); 3826 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3827 const char *type = object_get_typename(OBJECT(dev)); 3828 CPUArchId *core_slot; 3829 int index; 3830 unsigned int smp_threads = machine->smp.threads; 3831 3832 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3833 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3834 goto out; 3835 } 3836 3837 if (strcmp(base_core_type, type)) { 3838 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3839 goto out; 3840 } 3841 3842 if (cc->core_id % smp_threads) { 3843 error_setg(&local_err, "invalid core id %d", cc->core_id); 3844 goto out; 3845 } 3846 3847 /* 3848 * In general we should have homogeneous threads-per-core, but old 3849 * (pre hotplug support) machine types allow the last core to have 3850 * reduced threads as a compatibility hack for when we allowed 3851 * total vcpus not a multiple of threads-per-core. 3852 */ 3853 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3854 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3855 cc->nr_threads, smp_threads); 3856 goto out; 3857 } 3858 3859 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3860 if (!core_slot) { 3861 error_setg(&local_err, "core id %d out of range", cc->core_id); 3862 goto out; 3863 } 3864 3865 if (core_slot->cpu) { 3866 error_setg(&local_err, "core %d already populated", cc->core_id); 3867 goto out; 3868 } 3869 3870 numa_cpu_pre_plug(core_slot, dev, &local_err); 3871 3872 out: 3873 error_propagate(errp, local_err); 3874 } 3875 3876 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3877 void *fdt, int *fdt_start_offset, Error **errp) 3878 { 3879 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3880 int intc_phandle; 3881 3882 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3883 if (intc_phandle <= 0) { 3884 return -1; 3885 } 3886 3887 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3888 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3889 return -1; 3890 } 3891 3892 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3893 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3894 3895 return 0; 3896 } 3897 3898 static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3899 Error **errp) 3900 { 3901 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3902 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3903 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3904 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3905 3906 if (dev->hotplugged && !smc->dr_phb_enabled) { 3907 error_setg(errp, "PHB hotplug not supported for this machine"); 3908 return; 3909 } 3910 3911 if (sphb->index == (uint32_t)-1) { 3912 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3913 return; 3914 } 3915 3916 /* 3917 * This will check that sphb->index doesn't exceed the maximum number of 3918 * PHBs for the current machine type. 3919 */ 3920 smc->phb_placement(spapr, sphb->index, 3921 &sphb->buid, &sphb->io_win_addr, 3922 &sphb->mem_win_addr, &sphb->mem64_win_addr, 3923 windows_supported, sphb->dma_liobn, 3924 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 3925 errp); 3926 } 3927 3928 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3929 Error **errp) 3930 { 3931 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3932 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3933 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3934 SpaprDrc *drc; 3935 bool hotplugged = spapr_drc_hotplugged(dev); 3936 Error *local_err = NULL; 3937 3938 if (!smc->dr_phb_enabled) { 3939 return; 3940 } 3941 3942 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3943 /* hotplug hooks should check it's enabled before getting this far */ 3944 assert(drc); 3945 3946 spapr_drc_attach(drc, DEVICE(dev), &local_err); 3947 if (local_err) { 3948 error_propagate(errp, local_err); 3949 return; 3950 } 3951 3952 if (hotplugged) { 3953 spapr_hotplug_req_add_by_index(drc); 3954 } else { 3955 spapr_drc_reset(drc); 3956 } 3957 } 3958 3959 void spapr_phb_release(DeviceState *dev) 3960 { 3961 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3962 3963 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3964 object_unparent(OBJECT(dev)); 3965 } 3966 3967 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3968 { 3969 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3970 } 3971 3972 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 3973 DeviceState *dev, Error **errp) 3974 { 3975 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3976 SpaprDrc *drc; 3977 3978 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3979 assert(drc); 3980 3981 if (!spapr_drc_unplug_requested(drc)) { 3982 spapr_drc_detach(drc); 3983 spapr_hotplug_req_remove_by_index(drc); 3984 } 3985 } 3986 3987 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3988 Error **errp) 3989 { 3990 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3991 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 3992 3993 if (spapr->tpm_proxy != NULL) { 3994 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 3995 return; 3996 } 3997 3998 spapr->tpm_proxy = tpm_proxy; 3999 } 4000 4001 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4002 { 4003 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4004 4005 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 4006 object_unparent(OBJECT(dev)); 4007 spapr->tpm_proxy = NULL; 4008 } 4009 4010 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4011 DeviceState *dev, Error **errp) 4012 { 4013 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4014 spapr_memory_plug(hotplug_dev, dev, errp); 4015 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4016 spapr_core_plug(hotplug_dev, dev, errp); 4017 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4018 spapr_phb_plug(hotplug_dev, dev, errp); 4019 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4020 spapr_tpm_proxy_plug(hotplug_dev, dev, errp); 4021 } 4022 } 4023 4024 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4025 DeviceState *dev, Error **errp) 4026 { 4027 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4028 spapr_memory_unplug(hotplug_dev, dev); 4029 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4030 spapr_core_unplug(hotplug_dev, dev); 4031 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4032 spapr_phb_unplug(hotplug_dev, dev); 4033 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4034 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4035 } 4036 } 4037 4038 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4039 DeviceState *dev, Error **errp) 4040 { 4041 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4042 MachineClass *mc = MACHINE_GET_CLASS(sms); 4043 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4044 4045 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4046 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 4047 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4048 } else { 4049 /* NOTE: this means there is a window after guest reset, prior to 4050 * CAS negotiation, where unplug requests will fail due to the 4051 * capability not being detected yet. This is a bit different than 4052 * the case with PCI unplug, where the events will be queued and 4053 * eventually handled by the guest after boot 4054 */ 4055 error_setg(errp, "Memory hot unplug not supported for this guest"); 4056 } 4057 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4058 if (!mc->has_hotpluggable_cpus) { 4059 error_setg(errp, "CPU hot unplug not supported on this machine"); 4060 return; 4061 } 4062 spapr_core_unplug_request(hotplug_dev, dev, errp); 4063 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4064 if (!smc->dr_phb_enabled) { 4065 error_setg(errp, "PHB hot unplug not supported on this machine"); 4066 return; 4067 } 4068 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4069 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4070 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4071 } 4072 } 4073 4074 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4075 DeviceState *dev, Error **errp) 4076 { 4077 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4078 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4079 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4080 spapr_core_pre_plug(hotplug_dev, dev, errp); 4081 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4082 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4083 } 4084 } 4085 4086 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4087 DeviceState *dev) 4088 { 4089 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4090 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4091 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4092 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4093 return HOTPLUG_HANDLER(machine); 4094 } 4095 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4096 PCIDevice *pcidev = PCI_DEVICE(dev); 4097 PCIBus *root = pci_device_root_bus(pcidev); 4098 SpaprPhbState *phb = 4099 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4100 TYPE_SPAPR_PCI_HOST_BRIDGE); 4101 4102 if (phb) { 4103 return HOTPLUG_HANDLER(phb); 4104 } 4105 } 4106 return NULL; 4107 } 4108 4109 static CpuInstanceProperties 4110 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4111 { 4112 CPUArchId *core_slot; 4113 MachineClass *mc = MACHINE_GET_CLASS(machine); 4114 4115 /* make sure possible_cpu are intialized */ 4116 mc->possible_cpu_arch_ids(machine); 4117 /* get CPU core slot containing thread that matches cpu_index */ 4118 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4119 assert(core_slot); 4120 return core_slot->props; 4121 } 4122 4123 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4124 { 4125 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4126 } 4127 4128 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4129 { 4130 int i; 4131 unsigned int smp_threads = machine->smp.threads; 4132 unsigned int smp_cpus = machine->smp.cpus; 4133 const char *core_type; 4134 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4135 MachineClass *mc = MACHINE_GET_CLASS(machine); 4136 4137 if (!mc->has_hotpluggable_cpus) { 4138 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4139 } 4140 if (machine->possible_cpus) { 4141 assert(machine->possible_cpus->len == spapr_max_cores); 4142 return machine->possible_cpus; 4143 } 4144 4145 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4146 if (!core_type) { 4147 error_report("Unable to find sPAPR CPU Core definition"); 4148 exit(1); 4149 } 4150 4151 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4152 sizeof(CPUArchId) * spapr_max_cores); 4153 machine->possible_cpus->len = spapr_max_cores; 4154 for (i = 0; i < machine->possible_cpus->len; i++) { 4155 int core_id = i * smp_threads; 4156 4157 machine->possible_cpus->cpus[i].type = core_type; 4158 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4159 machine->possible_cpus->cpus[i].arch_id = core_id; 4160 machine->possible_cpus->cpus[i].props.has_core_id = true; 4161 machine->possible_cpus->cpus[i].props.core_id = core_id; 4162 } 4163 return machine->possible_cpus; 4164 } 4165 4166 static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4167 uint64_t *buid, hwaddr *pio, 4168 hwaddr *mmio32, hwaddr *mmio64, 4169 unsigned n_dma, uint32_t *liobns, 4170 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4171 { 4172 /* 4173 * New-style PHB window placement. 4174 * 4175 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4176 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4177 * windows. 4178 * 4179 * Some guest kernels can't work with MMIO windows above 1<<46 4180 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4181 * 4182 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4183 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4184 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4185 * 1TiB 64-bit MMIO windows for each PHB. 4186 */ 4187 const uint64_t base_buid = 0x800000020000000ULL; 4188 int i; 4189 4190 /* Sanity check natural alignments */ 4191 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4192 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4193 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4194 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4195 /* Sanity check bounds */ 4196 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4197 SPAPR_PCI_MEM32_WIN_SIZE); 4198 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4199 SPAPR_PCI_MEM64_WIN_SIZE); 4200 4201 if (index >= SPAPR_MAX_PHBS) { 4202 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4203 SPAPR_MAX_PHBS - 1); 4204 return; 4205 } 4206 4207 *buid = base_buid + index; 4208 for (i = 0; i < n_dma; ++i) { 4209 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4210 } 4211 4212 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4213 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4214 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4215 4216 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4217 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4218 } 4219 4220 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4221 { 4222 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4223 4224 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4225 } 4226 4227 static void spapr_ics_resend(XICSFabric *dev) 4228 { 4229 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4230 4231 ics_resend(spapr->ics); 4232 } 4233 4234 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4235 { 4236 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4237 4238 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4239 } 4240 4241 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4242 Monitor *mon) 4243 { 4244 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4245 4246 spapr_irq_print_info(spapr, mon); 4247 monitor_printf(mon, "irqchip: %s\n", 4248 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4249 } 4250 4251 /* 4252 * This is a XIVE only operation 4253 */ 4254 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4255 uint8_t nvt_blk, uint32_t nvt_idx, 4256 bool cam_ignore, uint8_t priority, 4257 uint32_t logic_serv, XiveTCTXMatch *match) 4258 { 4259 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4260 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4261 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4262 int count; 4263 4264 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4265 priority, logic_serv, match); 4266 if (count < 0) { 4267 return count; 4268 } 4269 4270 /* 4271 * When we implement the save and restore of the thread interrupt 4272 * contexts in the enter/exit CPU handlers of the machine and the 4273 * escalations in QEMU, we should be able to handle non dispatched 4274 * vCPUs. 4275 * 4276 * Until this is done, the sPAPR machine should find at least one 4277 * matching context always. 4278 */ 4279 if (count == 0) { 4280 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4281 nvt_blk, nvt_idx); 4282 } 4283 4284 return count; 4285 } 4286 4287 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4288 { 4289 return cpu->vcpu_id; 4290 } 4291 4292 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4293 { 4294 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4295 MachineState *ms = MACHINE(spapr); 4296 int vcpu_id; 4297 4298 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4299 4300 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4301 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4302 error_append_hint(errp, "Adjust the number of cpus to %d " 4303 "or try to raise the number of threads per core\n", 4304 vcpu_id * ms->smp.threads / spapr->vsmt); 4305 return; 4306 } 4307 4308 cpu->vcpu_id = vcpu_id; 4309 } 4310 4311 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4312 { 4313 CPUState *cs; 4314 4315 CPU_FOREACH(cs) { 4316 PowerPCCPU *cpu = POWERPC_CPU(cs); 4317 4318 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4319 return cpu; 4320 } 4321 } 4322 4323 return NULL; 4324 } 4325 4326 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4327 { 4328 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4329 4330 /* These are only called by TCG, KVM maintains dispatch state */ 4331 4332 spapr_cpu->prod = false; 4333 if (spapr_cpu->vpa_addr) { 4334 CPUState *cs = CPU(cpu); 4335 uint32_t dispatch; 4336 4337 dispatch = ldl_be_phys(cs->as, 4338 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4339 dispatch++; 4340 if ((dispatch & 1) != 0) { 4341 qemu_log_mask(LOG_GUEST_ERROR, 4342 "VPA: incorrect dispatch counter value for " 4343 "dispatched partition %u, correcting.\n", dispatch); 4344 dispatch++; 4345 } 4346 stl_be_phys(cs->as, 4347 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4348 } 4349 } 4350 4351 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4352 { 4353 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4354 4355 if (spapr_cpu->vpa_addr) { 4356 CPUState *cs = CPU(cpu); 4357 uint32_t dispatch; 4358 4359 dispatch = ldl_be_phys(cs->as, 4360 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4361 dispatch++; 4362 if ((dispatch & 1) != 1) { 4363 qemu_log_mask(LOG_GUEST_ERROR, 4364 "VPA: incorrect dispatch counter value for " 4365 "preempted partition %u, correcting.\n", dispatch); 4366 dispatch++; 4367 } 4368 stl_be_phys(cs->as, 4369 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4370 } 4371 } 4372 4373 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4374 { 4375 MachineClass *mc = MACHINE_CLASS(oc); 4376 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4377 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4378 NMIClass *nc = NMI_CLASS(oc); 4379 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4380 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4381 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4382 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4383 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4384 4385 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4386 mc->ignore_boot_device_suffixes = true; 4387 4388 /* 4389 * We set up the default / latest behaviour here. The class_init 4390 * functions for the specific versioned machine types can override 4391 * these details for backwards compatibility 4392 */ 4393 mc->init = spapr_machine_init; 4394 mc->reset = spapr_machine_reset; 4395 mc->block_default_type = IF_SCSI; 4396 mc->max_cpus = 1024; 4397 mc->no_parallel = 1; 4398 mc->default_boot_order = ""; 4399 mc->default_ram_size = 512 * MiB; 4400 mc->default_ram_id = "ppc_spapr.ram"; 4401 mc->default_display = "std"; 4402 mc->kvm_type = spapr_kvm_type; 4403 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4404 mc->pci_allow_0_address = true; 4405 assert(!mc->get_hotplug_handler); 4406 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4407 hc->pre_plug = spapr_machine_device_pre_plug; 4408 hc->plug = spapr_machine_device_plug; 4409 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4410 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4411 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4412 hc->unplug_request = spapr_machine_device_unplug_request; 4413 hc->unplug = spapr_machine_device_unplug; 4414 4415 smc->dr_lmb_enabled = true; 4416 smc->update_dt_enabled = true; 4417 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4418 mc->has_hotpluggable_cpus = true; 4419 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4420 fwc->get_dev_path = spapr_get_fw_dev_path; 4421 nc->nmi_monitor_handler = spapr_nmi; 4422 smc->phb_placement = spapr_phb_placement; 4423 vhc->hypercall = emulate_spapr_hypercall; 4424 vhc->hpt_mask = spapr_hpt_mask; 4425 vhc->map_hptes = spapr_map_hptes; 4426 vhc->unmap_hptes = spapr_unmap_hptes; 4427 vhc->hpte_set_c = spapr_hpte_set_c; 4428 vhc->hpte_set_r = spapr_hpte_set_r; 4429 vhc->get_pate = spapr_get_pate; 4430 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4431 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4432 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4433 xic->ics_get = spapr_ics_get; 4434 xic->ics_resend = spapr_ics_resend; 4435 xic->icp_get = spapr_icp_get; 4436 ispc->print_info = spapr_pic_print_info; 4437 /* Force NUMA node memory size to be a multiple of 4438 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4439 * in which LMBs are represented and hot-added 4440 */ 4441 mc->numa_mem_align_shift = 28; 4442 mc->numa_mem_supported = true; 4443 mc->auto_enable_numa = true; 4444 4445 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4446 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4447 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4448 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4449 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4450 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4451 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4452 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4453 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4454 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4455 smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] = SPAPR_CAP_ON; 4456 spapr_caps_add_properties(smc, &error_abort); 4457 smc->irq = &spapr_irq_dual; 4458 smc->dr_phb_enabled = true; 4459 smc->linux_pci_probe = true; 4460 smc->smp_threads_vsmt = true; 4461 smc->nr_xirqs = SPAPR_NR_XIRQS; 4462 xfc->match_nvt = spapr_match_nvt; 4463 } 4464 4465 static const TypeInfo spapr_machine_info = { 4466 .name = TYPE_SPAPR_MACHINE, 4467 .parent = TYPE_MACHINE, 4468 .abstract = true, 4469 .instance_size = sizeof(SpaprMachineState), 4470 .instance_init = spapr_instance_init, 4471 .instance_finalize = spapr_machine_finalizefn, 4472 .class_size = sizeof(SpaprMachineClass), 4473 .class_init = spapr_machine_class_init, 4474 .interfaces = (InterfaceInfo[]) { 4475 { TYPE_FW_PATH_PROVIDER }, 4476 { TYPE_NMI }, 4477 { TYPE_HOTPLUG_HANDLER }, 4478 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4479 { TYPE_XICS_FABRIC }, 4480 { TYPE_INTERRUPT_STATS_PROVIDER }, 4481 { TYPE_XIVE_FABRIC }, 4482 { } 4483 }, 4484 }; 4485 4486 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4487 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4488 void *data) \ 4489 { \ 4490 MachineClass *mc = MACHINE_CLASS(oc); \ 4491 spapr_machine_##suffix##_class_options(mc); \ 4492 if (latest) { \ 4493 mc->alias = "pseries"; \ 4494 mc->is_default = 1; \ 4495 } \ 4496 } \ 4497 static const TypeInfo spapr_machine_##suffix##_info = { \ 4498 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4499 .parent = TYPE_SPAPR_MACHINE, \ 4500 .class_init = spapr_machine_##suffix##_class_init, \ 4501 }; \ 4502 static void spapr_machine_register_##suffix(void) \ 4503 { \ 4504 type_register(&spapr_machine_##suffix##_info); \ 4505 } \ 4506 type_init(spapr_machine_register_##suffix) 4507 4508 /* 4509 * pseries-5.0 4510 */ 4511 static void spapr_machine_5_0_class_options(MachineClass *mc) 4512 { 4513 /* Defaults for the latest behaviour inherited from the base class */ 4514 } 4515 4516 DEFINE_SPAPR_MACHINE(5_0, "5.0", true); 4517 4518 /* 4519 * pseries-4.2 4520 */ 4521 static void spapr_machine_4_2_class_options(MachineClass *mc) 4522 { 4523 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4524 4525 spapr_machine_5_0_class_options(mc); 4526 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4527 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4528 smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] = SPAPR_CAP_OFF; 4529 } 4530 4531 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4532 4533 /* 4534 * pseries-4.1 4535 */ 4536 static void spapr_machine_4_1_class_options(MachineClass *mc) 4537 { 4538 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4539 static GlobalProperty compat[] = { 4540 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4541 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4542 }; 4543 4544 spapr_machine_4_2_class_options(mc); 4545 smc->linux_pci_probe = false; 4546 smc->smp_threads_vsmt = false; 4547 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4548 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4549 } 4550 4551 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4552 4553 /* 4554 * pseries-4.0 4555 */ 4556 static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4557 uint64_t *buid, hwaddr *pio, 4558 hwaddr *mmio32, hwaddr *mmio64, 4559 unsigned n_dma, uint32_t *liobns, 4560 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4561 { 4562 spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns, 4563 nv2gpa, nv2atsd, errp); 4564 *nv2gpa = 0; 4565 *nv2atsd = 0; 4566 } 4567 4568 static void spapr_machine_4_0_class_options(MachineClass *mc) 4569 { 4570 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4571 4572 spapr_machine_4_1_class_options(mc); 4573 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4574 smc->phb_placement = phb_placement_4_0; 4575 smc->irq = &spapr_irq_xics; 4576 smc->pre_4_1_migration = true; 4577 } 4578 4579 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4580 4581 /* 4582 * pseries-3.1 4583 */ 4584 static void spapr_machine_3_1_class_options(MachineClass *mc) 4585 { 4586 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4587 4588 spapr_machine_4_0_class_options(mc); 4589 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4590 4591 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4592 smc->update_dt_enabled = false; 4593 smc->dr_phb_enabled = false; 4594 smc->broken_host_serial_model = true; 4595 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4596 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4597 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4598 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4599 } 4600 4601 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4602 4603 /* 4604 * pseries-3.0 4605 */ 4606 4607 static void spapr_machine_3_0_class_options(MachineClass *mc) 4608 { 4609 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4610 4611 spapr_machine_3_1_class_options(mc); 4612 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4613 4614 smc->legacy_irq_allocation = true; 4615 smc->nr_xirqs = 0x400; 4616 smc->irq = &spapr_irq_xics_legacy; 4617 } 4618 4619 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4620 4621 /* 4622 * pseries-2.12 4623 */ 4624 static void spapr_machine_2_12_class_options(MachineClass *mc) 4625 { 4626 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4627 static GlobalProperty compat[] = { 4628 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4629 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4630 }; 4631 4632 spapr_machine_3_0_class_options(mc); 4633 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4634 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4635 4636 /* We depend on kvm_enabled() to choose a default value for the 4637 * hpt-max-page-size capability. Of course we can't do it here 4638 * because this is too early and the HW accelerator isn't initialzed 4639 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4640 */ 4641 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4642 } 4643 4644 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4645 4646 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4647 { 4648 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4649 4650 spapr_machine_2_12_class_options(mc); 4651 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4652 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4653 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4654 } 4655 4656 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4657 4658 /* 4659 * pseries-2.11 4660 */ 4661 4662 static void spapr_machine_2_11_class_options(MachineClass *mc) 4663 { 4664 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4665 4666 spapr_machine_2_12_class_options(mc); 4667 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4668 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4669 } 4670 4671 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4672 4673 /* 4674 * pseries-2.10 4675 */ 4676 4677 static void spapr_machine_2_10_class_options(MachineClass *mc) 4678 { 4679 spapr_machine_2_11_class_options(mc); 4680 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4681 } 4682 4683 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4684 4685 /* 4686 * pseries-2.9 4687 */ 4688 4689 static void spapr_machine_2_9_class_options(MachineClass *mc) 4690 { 4691 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4692 static GlobalProperty compat[] = { 4693 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4694 }; 4695 4696 spapr_machine_2_10_class_options(mc); 4697 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4698 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4699 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4700 smc->pre_2_10_has_unused_icps = true; 4701 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4702 } 4703 4704 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4705 4706 /* 4707 * pseries-2.8 4708 */ 4709 4710 static void spapr_machine_2_8_class_options(MachineClass *mc) 4711 { 4712 static GlobalProperty compat[] = { 4713 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4714 }; 4715 4716 spapr_machine_2_9_class_options(mc); 4717 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4718 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4719 mc->numa_mem_align_shift = 23; 4720 } 4721 4722 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4723 4724 /* 4725 * pseries-2.7 4726 */ 4727 4728 static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4729 uint64_t *buid, hwaddr *pio, 4730 hwaddr *mmio32, hwaddr *mmio64, 4731 unsigned n_dma, uint32_t *liobns, 4732 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4733 { 4734 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4735 const uint64_t base_buid = 0x800000020000000ULL; 4736 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4737 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4738 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4739 const uint32_t max_index = 255; 4740 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4741 4742 uint64_t ram_top = MACHINE(spapr)->ram_size; 4743 hwaddr phb0_base, phb_base; 4744 int i; 4745 4746 /* Do we have device memory? */ 4747 if (MACHINE(spapr)->maxram_size > ram_top) { 4748 /* Can't just use maxram_size, because there may be an 4749 * alignment gap between normal and device memory regions 4750 */ 4751 ram_top = MACHINE(spapr)->device_memory->base + 4752 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4753 } 4754 4755 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4756 4757 if (index > max_index) { 4758 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4759 max_index); 4760 return; 4761 } 4762 4763 *buid = base_buid + index; 4764 for (i = 0; i < n_dma; ++i) { 4765 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4766 } 4767 4768 phb_base = phb0_base + index * phb_spacing; 4769 *pio = phb_base + pio_offset; 4770 *mmio32 = phb_base + mmio_offset; 4771 /* 4772 * We don't set the 64-bit MMIO window, relying on the PHB's 4773 * fallback behaviour of automatically splitting a large "32-bit" 4774 * window into contiguous 32-bit and 64-bit windows 4775 */ 4776 4777 *nv2gpa = 0; 4778 *nv2atsd = 0; 4779 } 4780 4781 static void spapr_machine_2_7_class_options(MachineClass *mc) 4782 { 4783 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4784 static GlobalProperty compat[] = { 4785 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4786 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4787 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4788 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4789 }; 4790 4791 spapr_machine_2_8_class_options(mc); 4792 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4793 mc->default_machine_opts = "modern-hotplug-events=off"; 4794 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4795 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4796 smc->phb_placement = phb_placement_2_7; 4797 } 4798 4799 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4800 4801 /* 4802 * pseries-2.6 4803 */ 4804 4805 static void spapr_machine_2_6_class_options(MachineClass *mc) 4806 { 4807 static GlobalProperty compat[] = { 4808 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4809 }; 4810 4811 spapr_machine_2_7_class_options(mc); 4812 mc->has_hotpluggable_cpus = false; 4813 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4814 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4815 } 4816 4817 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4818 4819 /* 4820 * pseries-2.5 4821 */ 4822 4823 static void spapr_machine_2_5_class_options(MachineClass *mc) 4824 { 4825 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4826 static GlobalProperty compat[] = { 4827 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4828 }; 4829 4830 spapr_machine_2_6_class_options(mc); 4831 smc->use_ohci_by_default = true; 4832 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4833 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4834 } 4835 4836 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4837 4838 /* 4839 * pseries-2.4 4840 */ 4841 4842 static void spapr_machine_2_4_class_options(MachineClass *mc) 4843 { 4844 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4845 4846 spapr_machine_2_5_class_options(mc); 4847 smc->dr_lmb_enabled = false; 4848 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4849 } 4850 4851 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4852 4853 /* 4854 * pseries-2.3 4855 */ 4856 4857 static void spapr_machine_2_3_class_options(MachineClass *mc) 4858 { 4859 static GlobalProperty compat[] = { 4860 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4861 }; 4862 spapr_machine_2_4_class_options(mc); 4863 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4864 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4865 } 4866 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4867 4868 /* 4869 * pseries-2.2 4870 */ 4871 4872 static void spapr_machine_2_2_class_options(MachineClass *mc) 4873 { 4874 static GlobalProperty compat[] = { 4875 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4876 }; 4877 4878 spapr_machine_2_3_class_options(mc); 4879 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4880 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4881 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4882 } 4883 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4884 4885 /* 4886 * pseries-2.1 4887 */ 4888 4889 static void spapr_machine_2_1_class_options(MachineClass *mc) 4890 { 4891 spapr_machine_2_2_class_options(mc); 4892 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4893 } 4894 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4895 4896 static void spapr_machine_register_types(void) 4897 { 4898 type_register_static(&spapr_machine_info); 4899 } 4900 4901 type_init(spapr_machine_register_types) 4902