1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/numa.h" 31 #include "hw/hw.h" 32 #include "qemu/log.h" 33 #include "hw/fw-path-provider.h" 34 #include "elf.h" 35 #include "net/net.h" 36 #include "sysemu/device_tree.h" 37 #include "sysemu/block-backend.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/hw_accel.h" 40 #include "kvm_ppc.h" 41 #include "migration/migration.h" 42 #include "mmu-hash64.h" 43 #include "qom/cpu.h" 44 45 #include "hw/boards.h" 46 #include "hw/ppc/ppc.h" 47 #include "hw/loader.h" 48 49 #include "hw/ppc/fdt.h" 50 #include "hw/ppc/spapr.h" 51 #include "hw/ppc/spapr_vio.h" 52 #include "hw/pci-host/spapr.h" 53 #include "hw/ppc/xics.h" 54 #include "hw/pci/msi.h" 55 56 #include "hw/pci/pci.h" 57 #include "hw/scsi/scsi.h" 58 #include "hw/virtio/virtio-scsi.h" 59 60 #include "exec/address-spaces.h" 61 #include "hw/usb.h" 62 #include "qemu/config-file.h" 63 #include "qemu/error-report.h" 64 #include "trace.h" 65 #include "hw/nmi.h" 66 67 #include "hw/compat.h" 68 #include "qemu/cutils.h" 69 #include "hw/ppc/spapr_cpu_core.h" 70 #include "qmp-commands.h" 71 72 #include <libfdt.h> 73 74 /* SLOF memory layout: 75 * 76 * SLOF raw image loaded at 0, copies its romfs right below the flat 77 * device-tree, then position SLOF itself 31M below that 78 * 79 * So we set FW_OVERHEAD to 40MB which should account for all of that 80 * and more 81 * 82 * We load our kernel at 4M, leaving space for SLOF initial image 83 */ 84 #define FDT_MAX_SIZE 0x100000 85 #define RTAS_MAX_SIZE 0x10000 86 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 87 #define FW_MAX_SIZE 0x400000 88 #define FW_FILE_NAME "slof.bin" 89 #define FW_OVERHEAD 0x2800000 90 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 91 92 #define MIN_RMA_SLOF 128UL 93 94 #define PHANDLE_XICP 0x00001111 95 96 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 97 98 static XICSState *try_create_xics(sPAPRMachineState *spapr, 99 const char *type, const char *type_ics, 100 const char *type_icp, int nr_servers, 101 int nr_irqs, Error **errp) 102 { 103 Error *err = NULL, *local_err = NULL; 104 XICSState *xics; 105 ICSState *ics = NULL; 106 int i; 107 108 xics = XICS_COMMON(object_new(type)); 109 qdev_set_parent_bus(DEVICE(xics), sysbus_get_default()); 110 object_property_set_bool(OBJECT(xics), true, "realized", &err); 111 if (err) { 112 goto error; 113 } 114 115 ics = ICS_SIMPLE(object_new(type_ics)); 116 object_property_add_child(OBJECT(spapr), "ics", OBJECT(ics), NULL); 117 object_property_set_int(OBJECT(ics), nr_irqs, "nr-irqs", &err); 118 object_property_add_const_link(OBJECT(ics), "xics", OBJECT(xics), NULL); 119 object_property_set_bool(OBJECT(ics), true, "realized", &local_err); 120 error_propagate(&err, local_err); 121 if (err) { 122 goto error; 123 } 124 QLIST_INSERT_HEAD(&xics->ics, ics, list); 125 126 xics->ss = g_malloc0(nr_servers * sizeof(ICPState)); 127 xics->nr_servers = nr_servers; 128 129 for (i = 0; i < nr_servers; i++) { 130 ICPState *icp = &xics->ss[i]; 131 132 object_initialize(icp, sizeof(*icp), type_icp); 133 object_property_add_child(OBJECT(xics), "icp[*]", OBJECT(icp), NULL); 134 object_property_add_const_link(OBJECT(icp), "xics", OBJECT(xics), NULL); 135 object_property_set_bool(OBJECT(icp), true, "realized", &err); 136 if (err) { 137 goto error; 138 } 139 object_unref(OBJECT(icp)); 140 } 141 142 spapr->ics = ics; 143 return xics; 144 145 error: 146 error_propagate(errp, err); 147 if (ics) { 148 object_unparent(OBJECT(ics)); 149 } 150 object_unparent(OBJECT(xics)); 151 return NULL; 152 } 153 154 static XICSState *xics_system_init(MachineState *machine, 155 int nr_servers, int nr_irqs, Error **errp) 156 { 157 XICSState *xics = NULL; 158 159 if (kvm_enabled()) { 160 Error *err = NULL; 161 162 if (machine_kernel_irqchip_allowed(machine)) { 163 xics = try_create_xics(SPAPR_MACHINE(machine), 164 TYPE_XICS_SPAPR_KVM, TYPE_ICS_KVM, 165 TYPE_KVM_ICP, nr_servers, nr_irqs, &err); 166 } 167 if (machine_kernel_irqchip_required(machine) && !xics) { 168 error_reportf_err(err, 169 "kernel_irqchip requested but unavailable: "); 170 } else { 171 error_free(err); 172 } 173 } 174 175 if (!xics) { 176 xics = try_create_xics(SPAPR_MACHINE(machine), 177 TYPE_XICS_SPAPR, TYPE_ICS_SIMPLE, 178 TYPE_ICP, nr_servers, nr_irqs, errp); 179 } 180 181 return xics; 182 } 183 184 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 185 int smt_threads) 186 { 187 int i, ret = 0; 188 uint32_t servers_prop[smt_threads]; 189 uint32_t gservers_prop[smt_threads * 2]; 190 int index = ppc_get_vcpu_dt_id(cpu); 191 192 if (cpu->compat_pvr) { 193 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 194 if (ret < 0) { 195 return ret; 196 } 197 } 198 199 /* Build interrupt servers and gservers properties */ 200 for (i = 0; i < smt_threads; i++) { 201 servers_prop[i] = cpu_to_be32(index + i); 202 /* Hack, direct the group queues back to cpu 0 */ 203 gservers_prop[i*2] = cpu_to_be32(index + i); 204 gservers_prop[i*2 + 1] = 0; 205 } 206 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 207 servers_prop, sizeof(servers_prop)); 208 if (ret < 0) { 209 return ret; 210 } 211 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 212 gservers_prop, sizeof(gservers_prop)); 213 214 return ret; 215 } 216 217 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs) 218 { 219 int ret = 0; 220 PowerPCCPU *cpu = POWERPC_CPU(cs); 221 int index = ppc_get_vcpu_dt_id(cpu); 222 uint32_t associativity[] = {cpu_to_be32(0x5), 223 cpu_to_be32(0x0), 224 cpu_to_be32(0x0), 225 cpu_to_be32(0x0), 226 cpu_to_be32(cs->numa_node), 227 cpu_to_be32(index)}; 228 229 /* Advertise NUMA via ibm,associativity */ 230 if (nb_numa_nodes > 1) { 231 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 232 sizeof(associativity)); 233 } 234 235 return ret; 236 } 237 238 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 239 { 240 int ret = 0, offset, cpus_offset; 241 CPUState *cs; 242 char cpu_model[32]; 243 int smt = kvmppc_smt_threads(); 244 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 245 246 CPU_FOREACH(cs) { 247 PowerPCCPU *cpu = POWERPC_CPU(cs); 248 DeviceClass *dc = DEVICE_GET_CLASS(cs); 249 int index = ppc_get_vcpu_dt_id(cpu); 250 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 251 252 if ((index % smt) != 0) { 253 continue; 254 } 255 256 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 257 258 cpus_offset = fdt_path_offset(fdt, "/cpus"); 259 if (cpus_offset < 0) { 260 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 261 "cpus"); 262 if (cpus_offset < 0) { 263 return cpus_offset; 264 } 265 } 266 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 267 if (offset < 0) { 268 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 269 if (offset < 0) { 270 return offset; 271 } 272 } 273 274 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 275 pft_size_prop, sizeof(pft_size_prop)); 276 if (ret < 0) { 277 return ret; 278 } 279 280 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs); 281 if (ret < 0) { 282 return ret; 283 } 284 285 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 286 if (ret < 0) { 287 return ret; 288 } 289 } 290 return ret; 291 } 292 293 static hwaddr spapr_node0_size(void) 294 { 295 MachineState *machine = MACHINE(qdev_get_machine()); 296 297 if (nb_numa_nodes) { 298 int i; 299 for (i = 0; i < nb_numa_nodes; ++i) { 300 if (numa_info[i].node_mem) { 301 return MIN(pow2floor(numa_info[i].node_mem), 302 machine->ram_size); 303 } 304 } 305 } 306 return machine->ram_size; 307 } 308 309 static void add_str(GString *s, const gchar *s1) 310 { 311 g_string_append_len(s, s1, strlen(s1) + 1); 312 } 313 314 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 315 hwaddr size) 316 { 317 uint32_t associativity[] = { 318 cpu_to_be32(0x4), /* length */ 319 cpu_to_be32(0x0), cpu_to_be32(0x0), 320 cpu_to_be32(0x0), cpu_to_be32(nodeid) 321 }; 322 char mem_name[32]; 323 uint64_t mem_reg_property[2]; 324 int off; 325 326 mem_reg_property[0] = cpu_to_be64(start); 327 mem_reg_property[1] = cpu_to_be64(size); 328 329 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 330 off = fdt_add_subnode(fdt, 0, mem_name); 331 _FDT(off); 332 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 333 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 334 sizeof(mem_reg_property)))); 335 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 336 sizeof(associativity)))); 337 return off; 338 } 339 340 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 341 { 342 MachineState *machine = MACHINE(spapr); 343 hwaddr mem_start, node_size; 344 int i, nb_nodes = nb_numa_nodes; 345 NodeInfo *nodes = numa_info; 346 NodeInfo ramnode; 347 348 /* No NUMA nodes, assume there is just one node with whole RAM */ 349 if (!nb_numa_nodes) { 350 nb_nodes = 1; 351 ramnode.node_mem = machine->ram_size; 352 nodes = &ramnode; 353 } 354 355 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 356 if (!nodes[i].node_mem) { 357 continue; 358 } 359 if (mem_start >= machine->ram_size) { 360 node_size = 0; 361 } else { 362 node_size = nodes[i].node_mem; 363 if (node_size > machine->ram_size - mem_start) { 364 node_size = machine->ram_size - mem_start; 365 } 366 } 367 if (!mem_start) { 368 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 369 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 370 mem_start += spapr->rma_size; 371 node_size -= spapr->rma_size; 372 } 373 for ( ; node_size; ) { 374 hwaddr sizetmp = pow2floor(node_size); 375 376 /* mem_start != 0 here */ 377 if (ctzl(mem_start) < ctzl(sizetmp)) { 378 sizetmp = 1ULL << ctzl(mem_start); 379 } 380 381 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 382 node_size -= sizetmp; 383 mem_start += sizetmp; 384 } 385 } 386 387 return 0; 388 } 389 390 /* Populate the "ibm,pa-features" property */ 391 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset) 392 { 393 uint8_t pa_features_206[] = { 6, 0, 394 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 395 uint8_t pa_features_207[] = { 24, 0, 396 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 397 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 398 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 399 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 400 uint8_t *pa_features; 401 size_t pa_size; 402 403 switch (env->mmu_model) { 404 case POWERPC_MMU_2_06: 405 case POWERPC_MMU_2_06a: 406 pa_features = pa_features_206; 407 pa_size = sizeof(pa_features_206); 408 break; 409 case POWERPC_MMU_2_07: 410 case POWERPC_MMU_2_07a: 411 pa_features = pa_features_207; 412 pa_size = sizeof(pa_features_207); 413 break; 414 default: 415 return; 416 } 417 418 if (env->ci_large_pages) { 419 /* 420 * Note: we keep CI large pages off by default because a 64K capable 421 * guest provisioned with large pages might otherwise try to map a qemu 422 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 423 * even if that qemu runs on a 4k host. 424 * We dd this bit back here if we are confident this is not an issue 425 */ 426 pa_features[3] |= 0x20; 427 } 428 if (kvmppc_has_cap_htm() && pa_size > 24) { 429 pa_features[24] |= 0x80; /* Transactional memory support */ 430 } 431 432 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 433 } 434 435 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 436 sPAPRMachineState *spapr) 437 { 438 PowerPCCPU *cpu = POWERPC_CPU(cs); 439 CPUPPCState *env = &cpu->env; 440 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 441 int index = ppc_get_vcpu_dt_id(cpu); 442 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 443 0xffffffff, 0xffffffff}; 444 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 445 : SPAPR_TIMEBASE_FREQ; 446 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 447 uint32_t page_sizes_prop[64]; 448 size_t page_sizes_prop_size; 449 uint32_t vcpus_per_socket = smp_threads * smp_cores; 450 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 451 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 452 sPAPRDRConnector *drc; 453 sPAPRDRConnectorClass *drck; 454 int drc_index; 455 456 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index); 457 if (drc) { 458 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 459 drc_index = drck->get_index(drc); 460 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 461 } 462 463 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 464 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 465 466 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 467 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 468 env->dcache_line_size))); 469 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 470 env->dcache_line_size))); 471 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 472 env->icache_line_size))); 473 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 474 env->icache_line_size))); 475 476 if (pcc->l1_dcache_size) { 477 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 478 pcc->l1_dcache_size))); 479 } else { 480 error_report("Warning: Unknown L1 dcache size for cpu"); 481 } 482 if (pcc->l1_icache_size) { 483 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 484 pcc->l1_icache_size))); 485 } else { 486 error_report("Warning: Unknown L1 icache size for cpu"); 487 } 488 489 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 490 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 491 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 492 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 493 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 494 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 495 496 if (env->spr_cb[SPR_PURR].oea_read) { 497 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 498 } 499 500 if (env->mmu_model & POWERPC_MMU_1TSEG) { 501 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 502 segs, sizeof(segs)))); 503 } 504 505 /* Advertise VMX/VSX (vector extensions) if available 506 * 0 / no property == no vector extensions 507 * 1 == VMX / Altivec available 508 * 2 == VSX available */ 509 if (env->insns_flags & PPC_ALTIVEC) { 510 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 511 512 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 513 } 514 515 /* Advertise DFP (Decimal Floating Point) if available 516 * 0 / no property == no DFP 517 * 1 == DFP available */ 518 if (env->insns_flags2 & PPC2_DFP) { 519 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 520 } 521 522 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 523 sizeof(page_sizes_prop)); 524 if (page_sizes_prop_size) { 525 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 526 page_sizes_prop, page_sizes_prop_size))); 527 } 528 529 spapr_populate_pa_features(env, fdt, offset); 530 531 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 532 cs->cpu_index / vcpus_per_socket))); 533 534 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 535 pft_size_prop, sizeof(pft_size_prop)))); 536 537 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs)); 538 539 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 540 } 541 542 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 543 { 544 CPUState *cs; 545 int cpus_offset; 546 char *nodename; 547 int smt = kvmppc_smt_threads(); 548 549 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 550 _FDT(cpus_offset); 551 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 552 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 553 554 /* 555 * We walk the CPUs in reverse order to ensure that CPU DT nodes 556 * created by fdt_add_subnode() end up in the right order in FDT 557 * for the guest kernel the enumerate the CPUs correctly. 558 */ 559 CPU_FOREACH_REVERSE(cs) { 560 PowerPCCPU *cpu = POWERPC_CPU(cs); 561 int index = ppc_get_vcpu_dt_id(cpu); 562 DeviceClass *dc = DEVICE_GET_CLASS(cs); 563 int offset; 564 565 if ((index % smt) != 0) { 566 continue; 567 } 568 569 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 570 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 571 g_free(nodename); 572 _FDT(offset); 573 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 574 } 575 576 } 577 578 /* 579 * Adds ibm,dynamic-reconfiguration-memory node. 580 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 581 * of this device tree node. 582 */ 583 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 584 { 585 MachineState *machine = MACHINE(spapr); 586 int ret, i, offset; 587 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 588 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 589 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 590 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 591 memory_region_size(&spapr->hotplug_memory.mr)) / 592 lmb_size; 593 uint32_t *int_buf, *cur_index, buf_len; 594 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 595 596 /* 597 * Don't create the node if there is no hotpluggable memory 598 */ 599 if (machine->ram_size == machine->maxram_size) { 600 return 0; 601 } 602 603 /* 604 * Allocate enough buffer size to fit in ibm,dynamic-memory 605 * or ibm,associativity-lookup-arrays 606 */ 607 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 608 * sizeof(uint32_t); 609 cur_index = int_buf = g_malloc0(buf_len); 610 611 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 612 613 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 614 sizeof(prop_lmb_size)); 615 if (ret < 0) { 616 goto out; 617 } 618 619 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 620 if (ret < 0) { 621 goto out; 622 } 623 624 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 625 if (ret < 0) { 626 goto out; 627 } 628 629 /* ibm,dynamic-memory */ 630 int_buf[0] = cpu_to_be32(nr_lmbs); 631 cur_index++; 632 for (i = 0; i < nr_lmbs; i++) { 633 uint64_t addr = i * lmb_size; 634 uint32_t *dynamic_memory = cur_index; 635 636 if (i >= hotplug_lmb_start) { 637 sPAPRDRConnector *drc; 638 sPAPRDRConnectorClass *drck; 639 640 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i); 641 g_assert(drc); 642 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 643 644 dynamic_memory[0] = cpu_to_be32(addr >> 32); 645 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 646 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); 647 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 648 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); 649 if (memory_region_present(get_system_memory(), addr)) { 650 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 651 } else { 652 dynamic_memory[5] = cpu_to_be32(0); 653 } 654 } else { 655 /* 656 * LMB information for RMA, boot time RAM and gap b/n RAM and 657 * hotplug memory region -- all these are marked as reserved 658 * and as having no valid DRC. 659 */ 660 dynamic_memory[0] = cpu_to_be32(addr >> 32); 661 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 662 dynamic_memory[2] = cpu_to_be32(0); 663 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 664 dynamic_memory[4] = cpu_to_be32(-1); 665 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 666 SPAPR_LMB_FLAGS_DRC_INVALID); 667 } 668 669 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 670 } 671 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 672 if (ret < 0) { 673 goto out; 674 } 675 676 /* ibm,associativity-lookup-arrays */ 677 cur_index = int_buf; 678 int_buf[0] = cpu_to_be32(nr_nodes); 679 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 680 cur_index += 2; 681 for (i = 0; i < nr_nodes; i++) { 682 uint32_t associativity[] = { 683 cpu_to_be32(0x0), 684 cpu_to_be32(0x0), 685 cpu_to_be32(0x0), 686 cpu_to_be32(i) 687 }; 688 memcpy(cur_index, associativity, sizeof(associativity)); 689 cur_index += 4; 690 } 691 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 692 (cur_index - int_buf) * sizeof(uint32_t)); 693 out: 694 g_free(int_buf); 695 return ret; 696 } 697 698 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 699 sPAPROptionVector *ov5_updates) 700 { 701 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 702 int ret = 0, offset; 703 704 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 705 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 706 g_assert(smc->dr_lmb_enabled); 707 ret = spapr_populate_drconf_memory(spapr, fdt); 708 if (ret) { 709 goto out; 710 } 711 } 712 713 offset = fdt_path_offset(fdt, "/chosen"); 714 if (offset < 0) { 715 offset = fdt_add_subnode(fdt, 0, "chosen"); 716 if (offset < 0) { 717 return offset; 718 } 719 } 720 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 721 "ibm,architecture-vec-5"); 722 723 out: 724 return ret; 725 } 726 727 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 728 target_ulong addr, target_ulong size, 729 sPAPROptionVector *ov5_updates) 730 { 731 void *fdt, *fdt_skel; 732 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 733 734 size -= sizeof(hdr); 735 736 /* Create sceleton */ 737 fdt_skel = g_malloc0(size); 738 _FDT((fdt_create(fdt_skel, size))); 739 _FDT((fdt_begin_node(fdt_skel, ""))); 740 _FDT((fdt_end_node(fdt_skel))); 741 _FDT((fdt_finish(fdt_skel))); 742 fdt = g_malloc0(size); 743 _FDT((fdt_open_into(fdt_skel, fdt, size))); 744 g_free(fdt_skel); 745 746 /* Fixup cpu nodes */ 747 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 748 749 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 750 return -1; 751 } 752 753 /* Pack resulting tree */ 754 _FDT((fdt_pack(fdt))); 755 756 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 757 trace_spapr_cas_failed(size); 758 return -1; 759 } 760 761 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 762 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 763 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 764 g_free(fdt); 765 766 return 0; 767 } 768 769 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 770 { 771 int rtas; 772 GString *hypertas = g_string_sized_new(256); 773 GString *qemu_hypertas = g_string_sized_new(256); 774 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 775 uint64_t max_hotplug_addr = spapr->hotplug_memory.base + 776 memory_region_size(&spapr->hotplug_memory.mr); 777 uint32_t lrdr_capacity[] = { 778 cpu_to_be32(max_hotplug_addr >> 32), 779 cpu_to_be32(max_hotplug_addr & 0xffffffff), 780 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 781 cpu_to_be32(max_cpus / smp_threads), 782 }; 783 784 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 785 786 /* hypertas */ 787 add_str(hypertas, "hcall-pft"); 788 add_str(hypertas, "hcall-term"); 789 add_str(hypertas, "hcall-dabr"); 790 add_str(hypertas, "hcall-interrupt"); 791 add_str(hypertas, "hcall-tce"); 792 add_str(hypertas, "hcall-vio"); 793 add_str(hypertas, "hcall-splpar"); 794 add_str(hypertas, "hcall-bulk"); 795 add_str(hypertas, "hcall-set-mode"); 796 add_str(hypertas, "hcall-sprg0"); 797 add_str(hypertas, "hcall-copy"); 798 add_str(hypertas, "hcall-debug"); 799 add_str(qemu_hypertas, "hcall-memop1"); 800 801 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 802 add_str(hypertas, "hcall-multi-tce"); 803 } 804 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 805 hypertas->str, hypertas->len)); 806 g_string_free(hypertas, TRUE); 807 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 808 qemu_hypertas->str, qemu_hypertas->len)); 809 g_string_free(qemu_hypertas, TRUE); 810 811 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 812 refpoints, sizeof(refpoints))); 813 814 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 815 RTAS_ERROR_LOG_MAX)); 816 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 817 RTAS_EVENT_SCAN_RATE)); 818 819 if (msi_nonbroken) { 820 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 821 } 822 823 /* 824 * According to PAPR, rtas ibm,os-term does not guarantee a return 825 * back to the guest cpu. 826 * 827 * While an additional ibm,extended-os-term property indicates 828 * that rtas call return will always occur. Set this property. 829 */ 830 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 831 832 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 833 lrdr_capacity, sizeof(lrdr_capacity))); 834 835 spapr_dt_rtas_tokens(fdt, rtas); 836 } 837 838 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 839 { 840 MachineState *machine = MACHINE(spapr); 841 int chosen; 842 const char *boot_device = machine->boot_order; 843 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 844 size_t cb = 0; 845 char *bootlist = get_boot_devices_list(&cb, true); 846 847 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 848 849 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 850 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 851 spapr->initrd_base)); 852 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 853 spapr->initrd_base + spapr->initrd_size)); 854 855 if (spapr->kernel_size) { 856 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 857 cpu_to_be64(spapr->kernel_size) }; 858 859 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 860 &kprop, sizeof(kprop))); 861 if (spapr->kernel_le) { 862 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 863 } 864 } 865 if (boot_menu) { 866 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 867 } 868 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 869 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 870 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 871 872 if (cb && bootlist) { 873 int i; 874 875 for (i = 0; i < cb; i++) { 876 if (bootlist[i] == '\n') { 877 bootlist[i] = ' '; 878 } 879 } 880 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 881 } 882 883 if (boot_device && strlen(boot_device)) { 884 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 885 } 886 887 if (!spapr->has_graphics && stdout_path) { 888 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 889 } 890 891 g_free(stdout_path); 892 g_free(bootlist); 893 } 894 895 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 896 { 897 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 898 * KVM to work under pHyp with some guest co-operation */ 899 int hypervisor; 900 uint8_t hypercall[16]; 901 902 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 903 /* indicate KVM hypercall interface */ 904 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 905 if (kvmppc_has_cap_fixup_hcalls()) { 906 /* 907 * Older KVM versions with older guest kernels were broken 908 * with the magic page, don't allow the guest to map it. 909 */ 910 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 911 sizeof(hypercall))) { 912 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 913 hypercall, sizeof(hypercall))); 914 } 915 } 916 } 917 918 static void *spapr_build_fdt(sPAPRMachineState *spapr, 919 hwaddr rtas_addr, 920 hwaddr rtas_size) 921 { 922 MachineState *machine = MACHINE(qdev_get_machine()); 923 MachineClass *mc = MACHINE_GET_CLASS(machine); 924 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 925 int ret; 926 void *fdt; 927 sPAPRPHBState *phb; 928 char *buf; 929 930 fdt = g_malloc0(FDT_MAX_SIZE); 931 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 932 933 /* Root node */ 934 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 935 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 936 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 937 938 /* 939 * Add info to guest to indentify which host is it being run on 940 * and what is the uuid of the guest 941 */ 942 if (kvmppc_get_host_model(&buf)) { 943 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 944 g_free(buf); 945 } 946 if (kvmppc_get_host_serial(&buf)) { 947 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 948 g_free(buf); 949 } 950 951 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 952 953 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 954 if (qemu_uuid_set) { 955 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 956 } 957 g_free(buf); 958 959 if (qemu_get_vm_name()) { 960 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 961 qemu_get_vm_name())); 962 } 963 964 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 965 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 966 967 /* /interrupt controller */ 968 spapr_dt_xics(spapr->xics, fdt, PHANDLE_XICP); 969 970 ret = spapr_populate_memory(spapr, fdt); 971 if (ret < 0) { 972 error_report("couldn't setup memory nodes in fdt"); 973 exit(1); 974 } 975 976 /* /vdevice */ 977 spapr_dt_vdevice(spapr->vio_bus, fdt); 978 979 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 980 ret = spapr_rng_populate_dt(fdt); 981 if (ret < 0) { 982 error_report("could not set up rng device in the fdt"); 983 exit(1); 984 } 985 } 986 987 QLIST_FOREACH(phb, &spapr->phbs, list) { 988 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 989 if (ret < 0) { 990 error_report("couldn't setup PCI devices in fdt"); 991 exit(1); 992 } 993 } 994 995 /* cpus */ 996 spapr_populate_cpus_dt_node(fdt, spapr); 997 998 if (smc->dr_lmb_enabled) { 999 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1000 } 1001 1002 if (mc->has_hotpluggable_cpus) { 1003 int offset = fdt_path_offset(fdt, "/cpus"); 1004 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1005 SPAPR_DR_CONNECTOR_TYPE_CPU); 1006 if (ret < 0) { 1007 error_report("Couldn't set up CPU DR device tree properties"); 1008 exit(1); 1009 } 1010 } 1011 1012 /* /event-sources */ 1013 spapr_dt_events(spapr, fdt); 1014 1015 /* /rtas */ 1016 spapr_dt_rtas(spapr, fdt); 1017 1018 /* /chosen */ 1019 spapr_dt_chosen(spapr, fdt); 1020 1021 /* /hypervisor */ 1022 if (kvm_enabled()) { 1023 spapr_dt_hypervisor(spapr, fdt); 1024 } 1025 1026 /* Build memory reserve map */ 1027 if (spapr->kernel_size) { 1028 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1029 } 1030 if (spapr->initrd_size) { 1031 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1032 } 1033 1034 /* ibm,client-architecture-support updates */ 1035 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1036 if (ret < 0) { 1037 error_report("couldn't setup CAS properties fdt"); 1038 exit(1); 1039 } 1040 1041 return fdt; 1042 } 1043 1044 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1045 { 1046 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1047 } 1048 1049 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1050 PowerPCCPU *cpu) 1051 { 1052 CPUPPCState *env = &cpu->env; 1053 1054 /* The TCG path should also be holding the BQL at this point */ 1055 g_assert(qemu_mutex_iothread_locked()); 1056 1057 if (msr_pr) { 1058 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1059 env->gpr[3] = H_PRIVILEGE; 1060 } else { 1061 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1062 } 1063 } 1064 1065 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1066 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1067 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1068 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1069 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1070 1071 /* 1072 * Get the fd to access the kernel htab, re-opening it if necessary 1073 */ 1074 static int get_htab_fd(sPAPRMachineState *spapr) 1075 { 1076 if (spapr->htab_fd >= 0) { 1077 return spapr->htab_fd; 1078 } 1079 1080 spapr->htab_fd = kvmppc_get_htab_fd(false); 1081 if (spapr->htab_fd < 0) { 1082 error_report("Unable to open fd for reading hash table from KVM: %s", 1083 strerror(errno)); 1084 } 1085 1086 return spapr->htab_fd; 1087 } 1088 1089 static void close_htab_fd(sPAPRMachineState *spapr) 1090 { 1091 if (spapr->htab_fd >= 0) { 1092 close(spapr->htab_fd); 1093 } 1094 spapr->htab_fd = -1; 1095 } 1096 1097 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1098 { 1099 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1100 1101 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1102 } 1103 1104 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1105 hwaddr ptex, int n) 1106 { 1107 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1108 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1109 1110 if (!spapr->htab) { 1111 /* 1112 * HTAB is controlled by KVM. Fetch into temporary buffer 1113 */ 1114 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1115 kvmppc_read_hptes(hptes, ptex, n); 1116 return hptes; 1117 } 1118 1119 /* 1120 * HTAB is controlled by QEMU. Just point to the internally 1121 * accessible PTEG. 1122 */ 1123 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1124 } 1125 1126 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1127 const ppc_hash_pte64_t *hptes, 1128 hwaddr ptex, int n) 1129 { 1130 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1131 1132 if (!spapr->htab) { 1133 g_free((void *)hptes); 1134 } 1135 1136 /* Nothing to do for qemu managed HPT */ 1137 } 1138 1139 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1140 uint64_t pte0, uint64_t pte1) 1141 { 1142 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1143 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1144 1145 if (!spapr->htab) { 1146 kvmppc_write_hpte(ptex, pte0, pte1); 1147 } else { 1148 stq_p(spapr->htab + offset, pte0); 1149 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1150 } 1151 } 1152 1153 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1154 { 1155 int shift; 1156 1157 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1158 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1159 * that's much more than is needed for Linux guests */ 1160 shift = ctz64(pow2ceil(ramsize)) - 7; 1161 shift = MAX(shift, 18); /* Minimum architected size */ 1162 shift = MIN(shift, 46); /* Maximum architected size */ 1163 return shift; 1164 } 1165 1166 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1167 Error **errp) 1168 { 1169 long rc; 1170 1171 /* Clean up any HPT info from a previous boot */ 1172 g_free(spapr->htab); 1173 spapr->htab = NULL; 1174 spapr->htab_shift = 0; 1175 close_htab_fd(spapr); 1176 1177 rc = kvmppc_reset_htab(shift); 1178 if (rc < 0) { 1179 /* kernel-side HPT needed, but couldn't allocate one */ 1180 error_setg_errno(errp, errno, 1181 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1182 shift); 1183 /* This is almost certainly fatal, but if the caller really 1184 * wants to carry on with shift == 0, it's welcome to try */ 1185 } else if (rc > 0) { 1186 /* kernel-side HPT allocated */ 1187 if (rc != shift) { 1188 error_setg(errp, 1189 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1190 shift, rc); 1191 } 1192 1193 spapr->htab_shift = shift; 1194 spapr->htab = NULL; 1195 } else { 1196 /* kernel-side HPT not needed, allocate in userspace instead */ 1197 size_t size = 1ULL << shift; 1198 int i; 1199 1200 spapr->htab = qemu_memalign(size, size); 1201 if (!spapr->htab) { 1202 error_setg_errno(errp, errno, 1203 "Could not allocate HPT of order %d", shift); 1204 return; 1205 } 1206 1207 memset(spapr->htab, 0, size); 1208 spapr->htab_shift = shift; 1209 1210 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1211 DIRTY_HPTE(HPTE(spapr->htab, i)); 1212 } 1213 } 1214 } 1215 1216 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1217 { 1218 bool matched = false; 1219 1220 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1221 matched = true; 1222 } 1223 1224 if (!matched) { 1225 error_report("Device %s is not supported by this machine yet.", 1226 qdev_fw_name(DEVICE(sbdev))); 1227 exit(1); 1228 } 1229 } 1230 1231 static void ppc_spapr_reset(void) 1232 { 1233 MachineState *machine = MACHINE(qdev_get_machine()); 1234 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1235 PowerPCCPU *first_ppc_cpu; 1236 uint32_t rtas_limit; 1237 hwaddr rtas_addr, fdt_addr; 1238 void *fdt; 1239 int rc; 1240 1241 /* Check for unknown sysbus devices */ 1242 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1243 1244 /* Allocate and/or reset the hash page table */ 1245 spapr_reallocate_hpt(spapr, 1246 spapr_hpt_shift_for_ramsize(machine->maxram_size), 1247 &error_fatal); 1248 1249 /* Update the RMA size if necessary */ 1250 if (spapr->vrma_adjust) { 1251 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 1252 spapr->htab_shift); 1253 } 1254 1255 qemu_devices_reset(); 1256 1257 /* 1258 * We place the device tree and RTAS just below either the top of the RMA, 1259 * or just below 2GB, whichever is lowere, so that it can be 1260 * processed with 32-bit real mode code if necessary 1261 */ 1262 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1263 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1264 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1265 1266 /* if this reset wasn't generated by CAS, we should reset our 1267 * negotiated options and start from scratch */ 1268 if (!spapr->cas_reboot) { 1269 spapr_ovec_cleanup(spapr->ov5_cas); 1270 spapr->ov5_cas = spapr_ovec_new(); 1271 } 1272 1273 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1274 1275 spapr_load_rtas(spapr, fdt, rtas_addr); 1276 1277 rc = fdt_pack(fdt); 1278 1279 /* Should only fail if we've built a corrupted tree */ 1280 assert(rc == 0); 1281 1282 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1283 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1284 fdt_totalsize(fdt), FDT_MAX_SIZE); 1285 exit(1); 1286 } 1287 1288 /* Load the fdt */ 1289 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1290 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1291 g_free(fdt); 1292 1293 /* Set up the entry state */ 1294 first_ppc_cpu = POWERPC_CPU(first_cpu); 1295 first_ppc_cpu->env.gpr[3] = fdt_addr; 1296 first_ppc_cpu->env.gpr[5] = 0; 1297 first_cpu->halted = 0; 1298 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1299 1300 spapr->cas_reboot = false; 1301 } 1302 1303 static void spapr_create_nvram(sPAPRMachineState *spapr) 1304 { 1305 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1306 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1307 1308 if (dinfo) { 1309 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1310 &error_fatal); 1311 } 1312 1313 qdev_init_nofail(dev); 1314 1315 spapr->nvram = (struct sPAPRNVRAM *)dev; 1316 } 1317 1318 static void spapr_rtc_create(sPAPRMachineState *spapr) 1319 { 1320 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC); 1321 1322 qdev_init_nofail(dev); 1323 spapr->rtc = dev; 1324 1325 object_property_add_alias(qdev_get_machine(), "rtc-time", 1326 OBJECT(spapr->rtc), "date", NULL); 1327 } 1328 1329 /* Returns whether we want to use VGA or not */ 1330 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1331 { 1332 switch (vga_interface_type) { 1333 case VGA_NONE: 1334 return false; 1335 case VGA_DEVICE: 1336 return true; 1337 case VGA_STD: 1338 case VGA_VIRTIO: 1339 return pci_vga_init(pci_bus) != NULL; 1340 default: 1341 error_setg(errp, 1342 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1343 return false; 1344 } 1345 } 1346 1347 static int spapr_post_load(void *opaque, int version_id) 1348 { 1349 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1350 int err = 0; 1351 1352 /* In earlier versions, there was no separate qdev for the PAPR 1353 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1354 * So when migrating from those versions, poke the incoming offset 1355 * value into the RTC device */ 1356 if (version_id < 3) { 1357 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset); 1358 } 1359 1360 return err; 1361 } 1362 1363 static bool version_before_3(void *opaque, int version_id) 1364 { 1365 return version_id < 3; 1366 } 1367 1368 static bool spapr_ov5_cas_needed(void *opaque) 1369 { 1370 sPAPRMachineState *spapr = opaque; 1371 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1372 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1373 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1374 bool cas_needed; 1375 1376 /* Prior to the introduction of sPAPROptionVector, we had two option 1377 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1378 * Both of these options encode machine topology into the device-tree 1379 * in such a way that the now-booted OS should still be able to interact 1380 * appropriately with QEMU regardless of what options were actually 1381 * negotiatied on the source side. 1382 * 1383 * As such, we can avoid migrating the CAS-negotiated options if these 1384 * are the only options available on the current machine/platform. 1385 * Since these are the only options available for pseries-2.7 and 1386 * earlier, this allows us to maintain old->new/new->old migration 1387 * compatibility. 1388 * 1389 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1390 * via default pseries-2.8 machines and explicit command-line parameters. 1391 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1392 * of the actual CAS-negotiated values to continue working properly. For 1393 * example, availability of memory unplug depends on knowing whether 1394 * OV5_HP_EVT was negotiated via CAS. 1395 * 1396 * Thus, for any cases where the set of available CAS-negotiatable 1397 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1398 * include the CAS-negotiated options in the migration stream. 1399 */ 1400 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1401 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1402 1403 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1404 * the mask itself since in the future it's possible "legacy" bits may be 1405 * removed via machine options, which could generate a false positive 1406 * that breaks migration. 1407 */ 1408 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1409 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1410 1411 spapr_ovec_cleanup(ov5_mask); 1412 spapr_ovec_cleanup(ov5_legacy); 1413 spapr_ovec_cleanup(ov5_removed); 1414 1415 return cas_needed; 1416 } 1417 1418 static const VMStateDescription vmstate_spapr_ov5_cas = { 1419 .name = "spapr_option_vector_ov5_cas", 1420 .version_id = 1, 1421 .minimum_version_id = 1, 1422 .needed = spapr_ov5_cas_needed, 1423 .fields = (VMStateField[]) { 1424 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1425 vmstate_spapr_ovec, sPAPROptionVector), 1426 VMSTATE_END_OF_LIST() 1427 }, 1428 }; 1429 1430 static const VMStateDescription vmstate_spapr = { 1431 .name = "spapr", 1432 .version_id = 3, 1433 .minimum_version_id = 1, 1434 .post_load = spapr_post_load, 1435 .fields = (VMStateField[]) { 1436 /* used to be @next_irq */ 1437 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1438 1439 /* RTC offset */ 1440 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1441 1442 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1443 VMSTATE_END_OF_LIST() 1444 }, 1445 .subsections = (const VMStateDescription*[]) { 1446 &vmstate_spapr_ov5_cas, 1447 NULL 1448 } 1449 }; 1450 1451 static int htab_save_setup(QEMUFile *f, void *opaque) 1452 { 1453 sPAPRMachineState *spapr = opaque; 1454 1455 /* "Iteration" header */ 1456 qemu_put_be32(f, spapr->htab_shift); 1457 1458 if (spapr->htab) { 1459 spapr->htab_save_index = 0; 1460 spapr->htab_first_pass = true; 1461 } else { 1462 assert(kvm_enabled()); 1463 } 1464 1465 1466 return 0; 1467 } 1468 1469 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1470 int64_t max_ns) 1471 { 1472 bool has_timeout = max_ns != -1; 1473 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1474 int index = spapr->htab_save_index; 1475 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1476 1477 assert(spapr->htab_first_pass); 1478 1479 do { 1480 int chunkstart; 1481 1482 /* Consume invalid HPTEs */ 1483 while ((index < htabslots) 1484 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1485 index++; 1486 CLEAN_HPTE(HPTE(spapr->htab, index)); 1487 } 1488 1489 /* Consume valid HPTEs */ 1490 chunkstart = index; 1491 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1492 && HPTE_VALID(HPTE(spapr->htab, index))) { 1493 index++; 1494 CLEAN_HPTE(HPTE(spapr->htab, index)); 1495 } 1496 1497 if (index > chunkstart) { 1498 int n_valid = index - chunkstart; 1499 1500 qemu_put_be32(f, chunkstart); 1501 qemu_put_be16(f, n_valid); 1502 qemu_put_be16(f, 0); 1503 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1504 HASH_PTE_SIZE_64 * n_valid); 1505 1506 if (has_timeout && 1507 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1508 break; 1509 } 1510 } 1511 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1512 1513 if (index >= htabslots) { 1514 assert(index == htabslots); 1515 index = 0; 1516 spapr->htab_first_pass = false; 1517 } 1518 spapr->htab_save_index = index; 1519 } 1520 1521 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1522 int64_t max_ns) 1523 { 1524 bool final = max_ns < 0; 1525 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1526 int examined = 0, sent = 0; 1527 int index = spapr->htab_save_index; 1528 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1529 1530 assert(!spapr->htab_first_pass); 1531 1532 do { 1533 int chunkstart, invalidstart; 1534 1535 /* Consume non-dirty HPTEs */ 1536 while ((index < htabslots) 1537 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1538 index++; 1539 examined++; 1540 } 1541 1542 chunkstart = index; 1543 /* Consume valid dirty HPTEs */ 1544 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1545 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1546 && HPTE_VALID(HPTE(spapr->htab, index))) { 1547 CLEAN_HPTE(HPTE(spapr->htab, index)); 1548 index++; 1549 examined++; 1550 } 1551 1552 invalidstart = index; 1553 /* Consume invalid dirty HPTEs */ 1554 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1555 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1556 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1557 CLEAN_HPTE(HPTE(spapr->htab, index)); 1558 index++; 1559 examined++; 1560 } 1561 1562 if (index > chunkstart) { 1563 int n_valid = invalidstart - chunkstart; 1564 int n_invalid = index - invalidstart; 1565 1566 qemu_put_be32(f, chunkstart); 1567 qemu_put_be16(f, n_valid); 1568 qemu_put_be16(f, n_invalid); 1569 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1570 HASH_PTE_SIZE_64 * n_valid); 1571 sent += index - chunkstart; 1572 1573 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1574 break; 1575 } 1576 } 1577 1578 if (examined >= htabslots) { 1579 break; 1580 } 1581 1582 if (index >= htabslots) { 1583 assert(index == htabslots); 1584 index = 0; 1585 } 1586 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1587 1588 if (index >= htabslots) { 1589 assert(index == htabslots); 1590 index = 0; 1591 } 1592 1593 spapr->htab_save_index = index; 1594 1595 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1596 } 1597 1598 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1599 #define MAX_KVM_BUF_SIZE 2048 1600 1601 static int htab_save_iterate(QEMUFile *f, void *opaque) 1602 { 1603 sPAPRMachineState *spapr = opaque; 1604 int fd; 1605 int rc = 0; 1606 1607 /* Iteration header */ 1608 qemu_put_be32(f, 0); 1609 1610 if (!spapr->htab) { 1611 assert(kvm_enabled()); 1612 1613 fd = get_htab_fd(spapr); 1614 if (fd < 0) { 1615 return fd; 1616 } 1617 1618 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1619 if (rc < 0) { 1620 return rc; 1621 } 1622 } else if (spapr->htab_first_pass) { 1623 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1624 } else { 1625 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1626 } 1627 1628 /* End marker */ 1629 qemu_put_be32(f, 0); 1630 qemu_put_be16(f, 0); 1631 qemu_put_be16(f, 0); 1632 1633 return rc; 1634 } 1635 1636 static int htab_save_complete(QEMUFile *f, void *opaque) 1637 { 1638 sPAPRMachineState *spapr = opaque; 1639 int fd; 1640 1641 /* Iteration header */ 1642 qemu_put_be32(f, 0); 1643 1644 if (!spapr->htab) { 1645 int rc; 1646 1647 assert(kvm_enabled()); 1648 1649 fd = get_htab_fd(spapr); 1650 if (fd < 0) { 1651 return fd; 1652 } 1653 1654 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 1655 if (rc < 0) { 1656 return rc; 1657 } 1658 } else { 1659 if (spapr->htab_first_pass) { 1660 htab_save_first_pass(f, spapr, -1); 1661 } 1662 htab_save_later_pass(f, spapr, -1); 1663 } 1664 1665 /* End marker */ 1666 qemu_put_be32(f, 0); 1667 qemu_put_be16(f, 0); 1668 qemu_put_be16(f, 0); 1669 1670 return 0; 1671 } 1672 1673 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1674 { 1675 sPAPRMachineState *spapr = opaque; 1676 uint32_t section_hdr; 1677 int fd = -1; 1678 1679 if (version_id < 1 || version_id > 1) { 1680 error_report("htab_load() bad version"); 1681 return -EINVAL; 1682 } 1683 1684 section_hdr = qemu_get_be32(f); 1685 1686 if (section_hdr) { 1687 Error *local_err = NULL; 1688 1689 /* First section gives the htab size */ 1690 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 1691 if (local_err) { 1692 error_report_err(local_err); 1693 return -EINVAL; 1694 } 1695 return 0; 1696 } 1697 1698 if (!spapr->htab) { 1699 assert(kvm_enabled()); 1700 1701 fd = kvmppc_get_htab_fd(true); 1702 if (fd < 0) { 1703 error_report("Unable to open fd to restore KVM hash table: %s", 1704 strerror(errno)); 1705 } 1706 } 1707 1708 while (true) { 1709 uint32_t index; 1710 uint16_t n_valid, n_invalid; 1711 1712 index = qemu_get_be32(f); 1713 n_valid = qemu_get_be16(f); 1714 n_invalid = qemu_get_be16(f); 1715 1716 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1717 /* End of Stream */ 1718 break; 1719 } 1720 1721 if ((index + n_valid + n_invalid) > 1722 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1723 /* Bad index in stream */ 1724 error_report( 1725 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 1726 index, n_valid, n_invalid, spapr->htab_shift); 1727 return -EINVAL; 1728 } 1729 1730 if (spapr->htab) { 1731 if (n_valid) { 1732 qemu_get_buffer(f, HPTE(spapr->htab, index), 1733 HASH_PTE_SIZE_64 * n_valid); 1734 } 1735 if (n_invalid) { 1736 memset(HPTE(spapr->htab, index + n_valid), 0, 1737 HASH_PTE_SIZE_64 * n_invalid); 1738 } 1739 } else { 1740 int rc; 1741 1742 assert(fd >= 0); 1743 1744 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1745 if (rc < 0) { 1746 return rc; 1747 } 1748 } 1749 } 1750 1751 if (!spapr->htab) { 1752 assert(fd >= 0); 1753 close(fd); 1754 } 1755 1756 return 0; 1757 } 1758 1759 static void htab_cleanup(void *opaque) 1760 { 1761 sPAPRMachineState *spapr = opaque; 1762 1763 close_htab_fd(spapr); 1764 } 1765 1766 static SaveVMHandlers savevm_htab_handlers = { 1767 .save_live_setup = htab_save_setup, 1768 .save_live_iterate = htab_save_iterate, 1769 .save_live_complete_precopy = htab_save_complete, 1770 .cleanup = htab_cleanup, 1771 .load_state = htab_load, 1772 }; 1773 1774 static void spapr_boot_set(void *opaque, const char *boot_device, 1775 Error **errp) 1776 { 1777 MachineState *machine = MACHINE(qdev_get_machine()); 1778 machine->boot_order = g_strdup(boot_device); 1779 } 1780 1781 /* 1782 * Reset routine for LMB DR devices. 1783 * 1784 * Unlike PCI DR devices, LMB DR devices explicitly register this reset 1785 * routine. Reset for PCI DR devices will be handled by PHB reset routine 1786 * when it walks all its children devices. LMB devices reset occurs 1787 * as part of spapr_ppc_reset(). 1788 */ 1789 static void spapr_drc_reset(void *opaque) 1790 { 1791 sPAPRDRConnector *drc = opaque; 1792 DeviceState *d = DEVICE(drc); 1793 1794 if (d) { 1795 device_reset(d); 1796 } 1797 } 1798 1799 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 1800 { 1801 MachineState *machine = MACHINE(spapr); 1802 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 1803 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 1804 int i; 1805 1806 for (i = 0; i < nr_lmbs; i++) { 1807 sPAPRDRConnector *drc; 1808 uint64_t addr; 1809 1810 addr = i * lmb_size + spapr->hotplug_memory.base; 1811 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB, 1812 addr/lmb_size); 1813 qemu_register_reset(spapr_drc_reset, drc); 1814 } 1815 } 1816 1817 /* 1818 * If RAM size, maxmem size and individual node mem sizes aren't aligned 1819 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 1820 * since we can't support such unaligned sizes with DRCONF_MEMORY. 1821 */ 1822 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 1823 { 1824 int i; 1825 1826 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1827 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 1828 " is not aligned to %llu MiB", 1829 machine->ram_size, 1830 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1831 return; 1832 } 1833 1834 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1835 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 1836 " is not aligned to %llu MiB", 1837 machine->ram_size, 1838 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1839 return; 1840 } 1841 1842 for (i = 0; i < nb_numa_nodes; i++) { 1843 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 1844 error_setg(errp, 1845 "Node %d memory size 0x%" PRIx64 1846 " is not aligned to %llu MiB", 1847 i, numa_info[i].node_mem, 1848 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1849 return; 1850 } 1851 } 1852 } 1853 1854 /* find cpu slot in machine->possible_cpus by core_id */ 1855 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 1856 { 1857 int index = id / smp_threads; 1858 1859 if (index >= ms->possible_cpus->len) { 1860 return NULL; 1861 } 1862 if (idx) { 1863 *idx = index; 1864 } 1865 return &ms->possible_cpus->cpus[index]; 1866 } 1867 1868 static void spapr_init_cpus(sPAPRMachineState *spapr) 1869 { 1870 MachineState *machine = MACHINE(spapr); 1871 MachineClass *mc = MACHINE_GET_CLASS(machine); 1872 char *type = spapr_get_cpu_core_type(machine->cpu_model); 1873 int smt = kvmppc_smt_threads(); 1874 const CPUArchIdList *possible_cpus; 1875 int boot_cores_nr = smp_cpus / smp_threads; 1876 int i; 1877 1878 if (!type) { 1879 error_report("Unable to find sPAPR CPU Core definition"); 1880 exit(1); 1881 } 1882 1883 possible_cpus = mc->possible_cpu_arch_ids(machine); 1884 if (mc->has_hotpluggable_cpus) { 1885 if (smp_cpus % smp_threads) { 1886 error_report("smp_cpus (%u) must be multiple of threads (%u)", 1887 smp_cpus, smp_threads); 1888 exit(1); 1889 } 1890 if (max_cpus % smp_threads) { 1891 error_report("max_cpus (%u) must be multiple of threads (%u)", 1892 max_cpus, smp_threads); 1893 exit(1); 1894 } 1895 } else { 1896 if (max_cpus != smp_cpus) { 1897 error_report("This machine version does not support CPU hotplug"); 1898 exit(1); 1899 } 1900 boot_cores_nr = possible_cpus->len; 1901 } 1902 1903 for (i = 0; i < possible_cpus->len; i++) { 1904 int core_id = i * smp_threads; 1905 1906 if (mc->has_hotpluggable_cpus) { 1907 sPAPRDRConnector *drc = 1908 spapr_dr_connector_new(OBJECT(spapr), 1909 SPAPR_DR_CONNECTOR_TYPE_CPU, 1910 (core_id / smp_threads) * smt); 1911 1912 qemu_register_reset(spapr_drc_reset, drc); 1913 } 1914 1915 if (i < boot_cores_nr) { 1916 Object *core = object_new(type); 1917 int nr_threads = smp_threads; 1918 1919 /* Handle the partially filled core for older machine types */ 1920 if ((i + 1) * smp_threads >= smp_cpus) { 1921 nr_threads = smp_cpus - i * smp_threads; 1922 } 1923 1924 object_property_set_int(core, nr_threads, "nr-threads", 1925 &error_fatal); 1926 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 1927 &error_fatal); 1928 object_property_set_bool(core, true, "realized", &error_fatal); 1929 } 1930 } 1931 g_free(type); 1932 } 1933 1934 /* pSeries LPAR / sPAPR hardware init */ 1935 static void ppc_spapr_init(MachineState *machine) 1936 { 1937 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1938 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1939 const char *kernel_filename = machine->kernel_filename; 1940 const char *initrd_filename = machine->initrd_filename; 1941 PCIHostState *phb; 1942 int i; 1943 MemoryRegion *sysmem = get_system_memory(); 1944 MemoryRegion *ram = g_new(MemoryRegion, 1); 1945 MemoryRegion *rma_region; 1946 void *rma = NULL; 1947 hwaddr rma_alloc_size; 1948 hwaddr node0_size = spapr_node0_size(); 1949 long load_limit, fw_size; 1950 char *filename; 1951 int smt = kvmppc_smt_threads(); 1952 1953 msi_nonbroken = true; 1954 1955 QLIST_INIT(&spapr->phbs); 1956 1957 /* Allocate RMA if necessary */ 1958 rma_alloc_size = kvmppc_alloc_rma(&rma); 1959 1960 if (rma_alloc_size == -1) { 1961 error_report("Unable to create RMA"); 1962 exit(1); 1963 } 1964 1965 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1966 spapr->rma_size = rma_alloc_size; 1967 } else { 1968 spapr->rma_size = node0_size; 1969 1970 /* With KVM, we don't actually know whether KVM supports an 1971 * unbounded RMA (PR KVM) or is limited by the hash table size 1972 * (HV KVM using VRMA), so we always assume the latter 1973 * 1974 * In that case, we also limit the initial allocations for RTAS 1975 * etc... to 256M since we have no way to know what the VRMA size 1976 * is going to be as it depends on the size of the hash table 1977 * isn't determined yet. 1978 */ 1979 if (kvm_enabled()) { 1980 spapr->vrma_adjust = 1; 1981 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1982 } 1983 1984 /* Actually we don't support unbounded RMA anymore since we 1985 * added proper emulation of HV mode. The max we can get is 1986 * 16G which also happens to be what we configure for PAPR 1987 * mode so make sure we don't do anything bigger than that 1988 */ 1989 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 1990 } 1991 1992 if (spapr->rma_size > node0_size) { 1993 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 1994 spapr->rma_size); 1995 exit(1); 1996 } 1997 1998 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 1999 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2000 2001 /* Set up Interrupt Controller before we create the VCPUs */ 2002 spapr->xics = xics_system_init(machine, 2003 DIV_ROUND_UP(max_cpus * smt, smp_threads), 2004 XICS_IRQS_SPAPR, &error_fatal); 2005 2006 /* Set up containers for ibm,client-set-architecture negotiated options */ 2007 spapr->ov5 = spapr_ovec_new(); 2008 spapr->ov5_cas = spapr_ovec_new(); 2009 2010 if (smc->dr_lmb_enabled) { 2011 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2012 spapr_validate_node_memory(machine, &error_fatal); 2013 } 2014 2015 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2016 2017 /* advertise support for dedicated HP event source to guests */ 2018 if (spapr->use_hotplug_event_source) { 2019 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2020 } 2021 2022 /* init CPUs */ 2023 if (machine->cpu_model == NULL) { 2024 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu; 2025 } 2026 2027 ppc_cpu_parse_features(machine->cpu_model); 2028 2029 spapr_init_cpus(spapr); 2030 2031 if (kvm_enabled()) { 2032 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2033 kvmppc_enable_logical_ci_hcalls(); 2034 kvmppc_enable_set_mode_hcall(); 2035 2036 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2037 kvmppc_enable_clear_ref_mod_hcalls(); 2038 } 2039 2040 /* allocate RAM */ 2041 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2042 machine->ram_size); 2043 memory_region_add_subregion(sysmem, 0, ram); 2044 2045 if (rma_alloc_size && rma) { 2046 rma_region = g_new(MemoryRegion, 1); 2047 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 2048 rma_alloc_size, rma); 2049 vmstate_register_ram_global(rma_region); 2050 memory_region_add_subregion(sysmem, 0, rma_region); 2051 } 2052 2053 /* initialize hotplug memory address space */ 2054 if (machine->ram_size < machine->maxram_size) { 2055 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 2056 /* 2057 * Limit the number of hotpluggable memory slots to half the number 2058 * slots that KVM supports, leaving the other half for PCI and other 2059 * devices. However ensure that number of slots doesn't drop below 32. 2060 */ 2061 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2062 SPAPR_MAX_RAM_SLOTS; 2063 2064 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2065 max_memslots = SPAPR_MAX_RAM_SLOTS; 2066 } 2067 if (machine->ram_slots > max_memslots) { 2068 error_report("Specified number of memory slots %" 2069 PRIu64" exceeds max supported %d", 2070 machine->ram_slots, max_memslots); 2071 exit(1); 2072 } 2073 2074 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 2075 SPAPR_HOTPLUG_MEM_ALIGN); 2076 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 2077 "hotplug-memory", hotplug_mem_size); 2078 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 2079 &spapr->hotplug_memory.mr); 2080 } 2081 2082 if (smc->dr_lmb_enabled) { 2083 spapr_create_lmb_dr_connectors(spapr); 2084 } 2085 2086 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2087 if (!filename) { 2088 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2089 exit(1); 2090 } 2091 spapr->rtas_size = get_image_size(filename); 2092 if (spapr->rtas_size < 0) { 2093 error_report("Could not get size of LPAR rtas '%s'", filename); 2094 exit(1); 2095 } 2096 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2097 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2098 error_report("Could not load LPAR rtas '%s'", filename); 2099 exit(1); 2100 } 2101 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2102 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2103 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2104 exit(1); 2105 } 2106 g_free(filename); 2107 2108 /* Set up RTAS event infrastructure */ 2109 spapr_events_init(spapr); 2110 2111 /* Set up the RTC RTAS interfaces */ 2112 spapr_rtc_create(spapr); 2113 2114 /* Set up VIO bus */ 2115 spapr->vio_bus = spapr_vio_bus_init(); 2116 2117 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 2118 if (serial_hds[i]) { 2119 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 2120 } 2121 } 2122 2123 /* We always have at least the nvram device on VIO */ 2124 spapr_create_nvram(spapr); 2125 2126 /* Set up PCI */ 2127 spapr_pci_rtas_init(); 2128 2129 phb = spapr_create_phb(spapr, 0); 2130 2131 for (i = 0; i < nb_nics; i++) { 2132 NICInfo *nd = &nd_table[i]; 2133 2134 if (!nd->model) { 2135 nd->model = g_strdup("ibmveth"); 2136 } 2137 2138 if (strcmp(nd->model, "ibmveth") == 0) { 2139 spapr_vlan_create(spapr->vio_bus, nd); 2140 } else { 2141 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2142 } 2143 } 2144 2145 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2146 spapr_vscsi_create(spapr->vio_bus); 2147 } 2148 2149 /* Graphics */ 2150 if (spapr_vga_init(phb->bus, &error_fatal)) { 2151 spapr->has_graphics = true; 2152 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2153 } 2154 2155 if (machine->usb) { 2156 if (smc->use_ohci_by_default) { 2157 pci_create_simple(phb->bus, -1, "pci-ohci"); 2158 } else { 2159 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2160 } 2161 2162 if (spapr->has_graphics) { 2163 USBBus *usb_bus = usb_bus_find(-1); 2164 2165 usb_create_simple(usb_bus, "usb-kbd"); 2166 usb_create_simple(usb_bus, "usb-mouse"); 2167 } 2168 } 2169 2170 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 2171 error_report( 2172 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2173 MIN_RMA_SLOF); 2174 exit(1); 2175 } 2176 2177 if (kernel_filename) { 2178 uint64_t lowaddr = 0; 2179 2180 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2181 NULL, NULL, &lowaddr, NULL, 1, 2182 PPC_ELF_MACHINE, 0, 0); 2183 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2184 spapr->kernel_size = load_elf(kernel_filename, 2185 translate_kernel_address, NULL, NULL, 2186 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2187 0, 0); 2188 spapr->kernel_le = spapr->kernel_size > 0; 2189 } 2190 if (spapr->kernel_size < 0) { 2191 error_report("error loading %s: %s", kernel_filename, 2192 load_elf_strerror(spapr->kernel_size)); 2193 exit(1); 2194 } 2195 2196 /* load initrd */ 2197 if (initrd_filename) { 2198 /* Try to locate the initrd in the gap between the kernel 2199 * and the firmware. Add a bit of space just in case 2200 */ 2201 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2202 + 0x1ffff) & ~0xffff; 2203 spapr->initrd_size = load_image_targphys(initrd_filename, 2204 spapr->initrd_base, 2205 load_limit 2206 - spapr->initrd_base); 2207 if (spapr->initrd_size < 0) { 2208 error_report("could not load initial ram disk '%s'", 2209 initrd_filename); 2210 exit(1); 2211 } 2212 } 2213 } 2214 2215 if (bios_name == NULL) { 2216 bios_name = FW_FILE_NAME; 2217 } 2218 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2219 if (!filename) { 2220 error_report("Could not find LPAR firmware '%s'", bios_name); 2221 exit(1); 2222 } 2223 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2224 if (fw_size <= 0) { 2225 error_report("Could not load LPAR firmware '%s'", filename); 2226 exit(1); 2227 } 2228 g_free(filename); 2229 2230 /* FIXME: Should register things through the MachineState's qdev 2231 * interface, this is a legacy from the sPAPREnvironment structure 2232 * which predated MachineState but had a similar function */ 2233 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2234 register_savevm_live(NULL, "spapr/htab", -1, 1, 2235 &savevm_htab_handlers, spapr); 2236 2237 /* used by RTAS */ 2238 QTAILQ_INIT(&spapr->ccs_list); 2239 qemu_register_reset(spapr_ccs_reset_hook, spapr); 2240 2241 qemu_register_boot_set(spapr_boot_set, spapr); 2242 2243 /* to stop and start vmclock */ 2244 if (kvm_enabled()) { 2245 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2246 &spapr->tb); 2247 } 2248 } 2249 2250 static int spapr_kvm_type(const char *vm_type) 2251 { 2252 if (!vm_type) { 2253 return 0; 2254 } 2255 2256 if (!strcmp(vm_type, "HV")) { 2257 return 1; 2258 } 2259 2260 if (!strcmp(vm_type, "PR")) { 2261 return 2; 2262 } 2263 2264 error_report("Unknown kvm-type specified '%s'", vm_type); 2265 exit(1); 2266 } 2267 2268 /* 2269 * Implementation of an interface to adjust firmware path 2270 * for the bootindex property handling. 2271 */ 2272 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2273 DeviceState *dev) 2274 { 2275 #define CAST(type, obj, name) \ 2276 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2277 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2278 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2279 2280 if (d) { 2281 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2282 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2283 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2284 2285 if (spapr) { 2286 /* 2287 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2288 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2289 * in the top 16 bits of the 64-bit LUN 2290 */ 2291 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2292 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2293 (uint64_t)id << 48); 2294 } else if (virtio) { 2295 /* 2296 * We use SRP luns of the form 01000000 | (target << 8) | lun 2297 * in the top 32 bits of the 64-bit LUN 2298 * Note: the quote above is from SLOF and it is wrong, 2299 * the actual binding is: 2300 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2301 */ 2302 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2303 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2304 (uint64_t)id << 32); 2305 } else if (usb) { 2306 /* 2307 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2308 * in the top 32 bits of the 64-bit LUN 2309 */ 2310 unsigned usb_port = atoi(usb->port->path); 2311 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2312 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2313 (uint64_t)id << 32); 2314 } 2315 } 2316 2317 /* 2318 * SLOF probes the USB devices, and if it recognizes that the device is a 2319 * storage device, it changes its name to "storage" instead of "usb-host", 2320 * and additionally adds a child node for the SCSI LUN, so the correct 2321 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2322 */ 2323 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2324 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2325 if (usb_host_dev_is_scsi_storage(usbdev)) { 2326 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2327 } 2328 } 2329 2330 if (phb) { 2331 /* Replace "pci" with "pci@800000020000000" */ 2332 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2333 } 2334 2335 return NULL; 2336 } 2337 2338 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2339 { 2340 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2341 2342 return g_strdup(spapr->kvm_type); 2343 } 2344 2345 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2346 { 2347 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2348 2349 g_free(spapr->kvm_type); 2350 spapr->kvm_type = g_strdup(value); 2351 } 2352 2353 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2354 { 2355 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2356 2357 return spapr->use_hotplug_event_source; 2358 } 2359 2360 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2361 Error **errp) 2362 { 2363 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2364 2365 spapr->use_hotplug_event_source = value; 2366 } 2367 2368 static void spapr_machine_initfn(Object *obj) 2369 { 2370 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2371 2372 spapr->htab_fd = -1; 2373 spapr->use_hotplug_event_source = true; 2374 object_property_add_str(obj, "kvm-type", 2375 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2376 object_property_set_description(obj, "kvm-type", 2377 "Specifies the KVM virtualization mode (HV, PR)", 2378 NULL); 2379 object_property_add_bool(obj, "modern-hotplug-events", 2380 spapr_get_modern_hotplug_events, 2381 spapr_set_modern_hotplug_events, 2382 NULL); 2383 object_property_set_description(obj, "modern-hotplug-events", 2384 "Use dedicated hotplug event mechanism in" 2385 " place of standard EPOW events when possible" 2386 " (required for memory hot-unplug support)", 2387 NULL); 2388 } 2389 2390 static void spapr_machine_finalizefn(Object *obj) 2391 { 2392 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2393 2394 g_free(spapr->kvm_type); 2395 } 2396 2397 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 2398 { 2399 cpu_synchronize_state(cs); 2400 ppc_cpu_do_system_reset(cs); 2401 } 2402 2403 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2404 { 2405 CPUState *cs; 2406 2407 CPU_FOREACH(cs) { 2408 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 2409 } 2410 } 2411 2412 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2413 uint32_t node, bool dedicated_hp_event_source, 2414 Error **errp) 2415 { 2416 sPAPRDRConnector *drc; 2417 sPAPRDRConnectorClass *drck; 2418 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2419 int i, fdt_offset, fdt_size; 2420 void *fdt; 2421 uint64_t addr = addr_start; 2422 2423 for (i = 0; i < nr_lmbs; i++) { 2424 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2425 addr/SPAPR_MEMORY_BLOCK_SIZE); 2426 g_assert(drc); 2427 2428 fdt = create_device_tree(&fdt_size); 2429 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2430 SPAPR_MEMORY_BLOCK_SIZE); 2431 2432 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2433 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); 2434 addr += SPAPR_MEMORY_BLOCK_SIZE; 2435 if (!dev->hotplugged) { 2436 /* guests expect coldplugged LMBs to be pre-allocated */ 2437 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); 2438 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); 2439 } 2440 } 2441 /* send hotplug notification to the 2442 * guest only in case of hotplugged memory 2443 */ 2444 if (dev->hotplugged) { 2445 if (dedicated_hp_event_source) { 2446 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2447 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2448 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2449 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2450 nr_lmbs, 2451 drck->get_index(drc)); 2452 } else { 2453 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 2454 nr_lmbs); 2455 } 2456 } 2457 } 2458 2459 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2460 uint32_t node, Error **errp) 2461 { 2462 Error *local_err = NULL; 2463 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2464 PCDIMMDevice *dimm = PC_DIMM(dev); 2465 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2466 MemoryRegion *mr = ddc->get_memory_region(dimm); 2467 uint64_t align = memory_region_get_alignment(mr); 2468 uint64_t size = memory_region_size(mr); 2469 uint64_t addr; 2470 char *mem_dev; 2471 2472 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 2473 error_setg(&local_err, "Hotplugged memory size must be a multiple of " 2474 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); 2475 goto out; 2476 } 2477 2478 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); 2479 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { 2480 error_setg(&local_err, "Memory backend has bad page size. " 2481 "Use 'memory-backend-file' with correct mem-path."); 2482 goto out; 2483 } 2484 2485 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 2486 if (local_err) { 2487 goto out; 2488 } 2489 2490 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2491 if (local_err) { 2492 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2493 goto out; 2494 } 2495 2496 spapr_add_lmbs(dev, addr, size, node, 2497 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 2498 &error_abort); 2499 2500 out: 2501 error_propagate(errp, local_err); 2502 } 2503 2504 typedef struct sPAPRDIMMState { 2505 uint32_t nr_lmbs; 2506 } sPAPRDIMMState; 2507 2508 static void spapr_lmb_release(DeviceState *dev, void *opaque) 2509 { 2510 sPAPRDIMMState *ds = (sPAPRDIMMState *)opaque; 2511 HotplugHandler *hotplug_ctrl; 2512 2513 if (--ds->nr_lmbs) { 2514 return; 2515 } 2516 2517 g_free(ds); 2518 2519 /* 2520 * Now that all the LMBs have been removed by the guest, call the 2521 * pc-dimm unplug handler to cleanup up the pc-dimm device. 2522 */ 2523 hotplug_ctrl = qdev_get_hotplug_handler(dev); 2524 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2525 } 2526 2527 static void spapr_del_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2528 Error **errp) 2529 { 2530 sPAPRDRConnector *drc; 2531 sPAPRDRConnectorClass *drck; 2532 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 2533 int i; 2534 sPAPRDIMMState *ds = g_malloc0(sizeof(sPAPRDIMMState)); 2535 uint64_t addr = addr_start; 2536 2537 ds->nr_lmbs = nr_lmbs; 2538 for (i = 0; i < nr_lmbs; i++) { 2539 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2540 addr / SPAPR_MEMORY_BLOCK_SIZE); 2541 g_assert(drc); 2542 2543 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2544 drck->detach(drc, dev, spapr_lmb_release, ds, errp); 2545 addr += SPAPR_MEMORY_BLOCK_SIZE; 2546 } 2547 2548 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2549 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2550 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2551 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2552 nr_lmbs, 2553 drck->get_index(drc)); 2554 } 2555 2556 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2557 Error **errp) 2558 { 2559 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2560 PCDIMMDevice *dimm = PC_DIMM(dev); 2561 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2562 MemoryRegion *mr = ddc->get_memory_region(dimm); 2563 2564 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2565 object_unparent(OBJECT(dev)); 2566 } 2567 2568 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 2569 DeviceState *dev, Error **errp) 2570 { 2571 Error *local_err = NULL; 2572 PCDIMMDevice *dimm = PC_DIMM(dev); 2573 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2574 MemoryRegion *mr = ddc->get_memory_region(dimm); 2575 uint64_t size = memory_region_size(mr); 2576 uint64_t addr; 2577 2578 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2579 if (local_err) { 2580 goto out; 2581 } 2582 2583 spapr_del_lmbs(dev, addr, size, &error_abort); 2584 out: 2585 error_propagate(errp, local_err); 2586 } 2587 2588 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 2589 sPAPRMachineState *spapr) 2590 { 2591 PowerPCCPU *cpu = POWERPC_CPU(cs); 2592 DeviceClass *dc = DEVICE_GET_CLASS(cs); 2593 int id = ppc_get_vcpu_dt_id(cpu); 2594 void *fdt; 2595 int offset, fdt_size; 2596 char *nodename; 2597 2598 fdt = create_device_tree(&fdt_size); 2599 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 2600 offset = fdt_add_subnode(fdt, 0, nodename); 2601 2602 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 2603 g_free(nodename); 2604 2605 *fdt_offset = offset; 2606 return fdt; 2607 } 2608 2609 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2610 Error **errp) 2611 { 2612 MachineState *ms = MACHINE(qdev_get_machine()); 2613 CPUCore *cc = CPU_CORE(dev); 2614 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 2615 2616 core_slot->cpu = NULL; 2617 object_unparent(OBJECT(dev)); 2618 } 2619 2620 static void spapr_core_release(DeviceState *dev, void *opaque) 2621 { 2622 HotplugHandler *hotplug_ctrl; 2623 2624 hotplug_ctrl = qdev_get_hotplug_handler(dev); 2625 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2626 } 2627 2628 static 2629 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 2630 Error **errp) 2631 { 2632 int index; 2633 sPAPRDRConnector *drc; 2634 sPAPRDRConnectorClass *drck; 2635 Error *local_err = NULL; 2636 CPUCore *cc = CPU_CORE(dev); 2637 int smt = kvmppc_smt_threads(); 2638 2639 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 2640 error_setg(errp, "Unable to find CPU core with core-id: %d", 2641 cc->core_id); 2642 return; 2643 } 2644 if (index == 0) { 2645 error_setg(errp, "Boot CPU core may not be unplugged"); 2646 return; 2647 } 2648 2649 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt); 2650 g_assert(drc); 2651 2652 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2653 drck->detach(drc, dev, spapr_core_release, NULL, &local_err); 2654 if (local_err) { 2655 error_propagate(errp, local_err); 2656 return; 2657 } 2658 2659 spapr_hotplug_req_remove_by_index(drc); 2660 } 2661 2662 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2663 Error **errp) 2664 { 2665 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 2666 MachineClass *mc = MACHINE_GET_CLASS(spapr); 2667 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 2668 CPUCore *cc = CPU_CORE(dev); 2669 CPUState *cs = CPU(core->threads); 2670 sPAPRDRConnector *drc; 2671 Error *local_err = NULL; 2672 void *fdt = NULL; 2673 int fdt_offset = 0; 2674 int smt = kvmppc_smt_threads(); 2675 CPUArchId *core_slot; 2676 int index; 2677 2678 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 2679 if (!core_slot) { 2680 error_setg(errp, "Unable to find CPU core with core-id: %d", 2681 cc->core_id); 2682 return; 2683 } 2684 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt); 2685 2686 g_assert(drc || !mc->has_hotpluggable_cpus); 2687 2688 /* 2689 * Setup CPU DT entries only for hotplugged CPUs. For boot time or 2690 * coldplugged CPUs DT entries are setup in spapr_build_fdt(). 2691 */ 2692 if (dev->hotplugged) { 2693 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 2694 } 2695 2696 if (drc) { 2697 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2698 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err); 2699 if (local_err) { 2700 g_free(fdt); 2701 error_propagate(errp, local_err); 2702 return; 2703 } 2704 } 2705 2706 if (dev->hotplugged) { 2707 /* 2708 * Send hotplug notification interrupt to the guest only in case 2709 * of hotplugged CPUs. 2710 */ 2711 spapr_hotplug_req_add_by_index(drc); 2712 } else { 2713 /* 2714 * Set the right DRC states for cold plugged CPU. 2715 */ 2716 if (drc) { 2717 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2718 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); 2719 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); 2720 } 2721 } 2722 core_slot->cpu = OBJECT(dev); 2723 } 2724 2725 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2726 Error **errp) 2727 { 2728 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 2729 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 2730 Error *local_err = NULL; 2731 CPUCore *cc = CPU_CORE(dev); 2732 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model); 2733 const char *type = object_get_typename(OBJECT(dev)); 2734 CPUArchId *core_slot; 2735 int index; 2736 2737 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 2738 error_setg(&local_err, "CPU hotplug not supported for this machine"); 2739 goto out; 2740 } 2741 2742 if (strcmp(base_core_type, type)) { 2743 error_setg(&local_err, "CPU core type should be %s", base_core_type); 2744 goto out; 2745 } 2746 2747 if (cc->core_id % smp_threads) { 2748 error_setg(&local_err, "invalid core id %d", cc->core_id); 2749 goto out; 2750 } 2751 2752 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 2753 if (!core_slot) { 2754 error_setg(&local_err, "core id %d out of range", cc->core_id); 2755 goto out; 2756 } 2757 2758 if (core_slot->cpu) { 2759 error_setg(&local_err, "core %d already populated", cc->core_id); 2760 goto out; 2761 } 2762 2763 out: 2764 g_free(base_core_type); 2765 error_propagate(errp, local_err); 2766 } 2767 2768 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 2769 DeviceState *dev, Error **errp) 2770 { 2771 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 2772 2773 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2774 int node; 2775 2776 if (!smc->dr_lmb_enabled) { 2777 error_setg(errp, "Memory hotplug not supported for this machine"); 2778 return; 2779 } 2780 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 2781 if (*errp) { 2782 return; 2783 } 2784 if (node < 0 || node >= MAX_NODES) { 2785 error_setg(errp, "Invaild node %d", node); 2786 return; 2787 } 2788 2789 /* 2790 * Currently PowerPC kernel doesn't allow hot-adding memory to 2791 * memory-less node, but instead will silently add the memory 2792 * to the first node that has some memory. This causes two 2793 * unexpected behaviours for the user. 2794 * 2795 * - Memory gets hotplugged to a different node than what the user 2796 * specified. 2797 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 2798 * to memory-less node, a reboot will set things accordingly 2799 * and the previously hotplugged memory now ends in the right node. 2800 * This appears as if some memory moved from one node to another. 2801 * 2802 * So until kernel starts supporting memory hotplug to memory-less 2803 * nodes, just prevent such attempts upfront in QEMU. 2804 */ 2805 if (nb_numa_nodes && !numa_info[node].node_mem) { 2806 error_setg(errp, "Can't hotplug memory to memory-less node %d", 2807 node); 2808 return; 2809 } 2810 2811 spapr_memory_plug(hotplug_dev, dev, node, errp); 2812 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2813 spapr_core_plug(hotplug_dev, dev, errp); 2814 } 2815 } 2816 2817 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 2818 DeviceState *dev, Error **errp) 2819 { 2820 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 2821 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 2822 2823 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2824 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 2825 spapr_memory_unplug(hotplug_dev, dev, errp); 2826 } else { 2827 error_setg(errp, "Memory hot unplug not supported for this guest"); 2828 } 2829 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2830 if (!mc->has_hotpluggable_cpus) { 2831 error_setg(errp, "CPU hot unplug not supported on this machine"); 2832 return; 2833 } 2834 spapr_core_unplug(hotplug_dev, dev, errp); 2835 } 2836 } 2837 2838 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 2839 DeviceState *dev, Error **errp) 2840 { 2841 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 2842 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 2843 2844 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2845 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 2846 spapr_memory_unplug_request(hotplug_dev, dev, errp); 2847 } else { 2848 /* NOTE: this means there is a window after guest reset, prior to 2849 * CAS negotiation, where unplug requests will fail due to the 2850 * capability not being detected yet. This is a bit different than 2851 * the case with PCI unplug, where the events will be queued and 2852 * eventually handled by the guest after boot 2853 */ 2854 error_setg(errp, "Memory hot unplug not supported for this guest"); 2855 } 2856 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2857 if (!mc->has_hotpluggable_cpus) { 2858 error_setg(errp, "CPU hot unplug not supported on this machine"); 2859 return; 2860 } 2861 spapr_core_unplug_request(hotplug_dev, dev, errp); 2862 } 2863 } 2864 2865 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 2866 DeviceState *dev, Error **errp) 2867 { 2868 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2869 spapr_core_pre_plug(hotplug_dev, dev, errp); 2870 } 2871 } 2872 2873 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 2874 DeviceState *dev) 2875 { 2876 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2877 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2878 return HOTPLUG_HANDLER(machine); 2879 } 2880 return NULL; 2881 } 2882 2883 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index) 2884 { 2885 /* Allocate to NUMA nodes on a "socket" basis (not that concept of 2886 * socket means much for the paravirtualized PAPR platform) */ 2887 return cpu_index / smp_threads / smp_cores; 2888 } 2889 2890 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 2891 { 2892 int i; 2893 int spapr_max_cores = max_cpus / smp_threads; 2894 MachineClass *mc = MACHINE_GET_CLASS(machine); 2895 2896 if (!mc->has_hotpluggable_cpus) { 2897 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 2898 } 2899 if (machine->possible_cpus) { 2900 assert(machine->possible_cpus->len == spapr_max_cores); 2901 return machine->possible_cpus; 2902 } 2903 2904 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2905 sizeof(CPUArchId) * spapr_max_cores); 2906 machine->possible_cpus->len = spapr_max_cores; 2907 for (i = 0; i < machine->possible_cpus->len; i++) { 2908 int core_id = i * smp_threads; 2909 2910 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 2911 machine->possible_cpus->cpus[i].arch_id = core_id; 2912 machine->possible_cpus->cpus[i].props.has_core_id = true; 2913 machine->possible_cpus->cpus[i].props.core_id = core_id; 2914 /* TODO: add 'has_node/node' here to describe 2915 to which node core belongs */ 2916 } 2917 return machine->possible_cpus; 2918 } 2919 2920 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 2921 uint64_t *buid, hwaddr *pio, 2922 hwaddr *mmio32, hwaddr *mmio64, 2923 unsigned n_dma, uint32_t *liobns, Error **errp) 2924 { 2925 /* 2926 * New-style PHB window placement. 2927 * 2928 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 2929 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 2930 * windows. 2931 * 2932 * Some guest kernels can't work with MMIO windows above 1<<46 2933 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 2934 * 2935 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 2936 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 2937 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 2938 * 1TiB 64-bit MMIO windows for each PHB. 2939 */ 2940 const uint64_t base_buid = 0x800000020000000ULL; 2941 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 2942 SPAPR_PCI_MEM64_WIN_SIZE - 1) 2943 int i; 2944 2945 /* Sanity check natural alignments */ 2946 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 2947 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 2948 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 2949 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 2950 /* Sanity check bounds */ 2951 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 2952 SPAPR_PCI_MEM32_WIN_SIZE); 2953 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 2954 SPAPR_PCI_MEM64_WIN_SIZE); 2955 2956 if (index >= SPAPR_MAX_PHBS) { 2957 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 2958 SPAPR_MAX_PHBS - 1); 2959 return; 2960 } 2961 2962 *buid = base_buid + index; 2963 for (i = 0; i < n_dma; ++i) { 2964 liobns[i] = SPAPR_PCI_LIOBN(index, i); 2965 } 2966 2967 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 2968 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 2969 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 2970 } 2971 2972 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 2973 { 2974 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 2975 2976 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 2977 } 2978 2979 static void spapr_ics_resend(XICSFabric *dev) 2980 { 2981 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 2982 2983 ics_resend(spapr->ics); 2984 } 2985 2986 static void spapr_machine_class_init(ObjectClass *oc, void *data) 2987 { 2988 MachineClass *mc = MACHINE_CLASS(oc); 2989 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 2990 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 2991 NMIClass *nc = NMI_CLASS(oc); 2992 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2993 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 2994 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2995 2996 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 2997 2998 /* 2999 * We set up the default / latest behaviour here. The class_init 3000 * functions for the specific versioned machine types can override 3001 * these details for backwards compatibility 3002 */ 3003 mc->init = ppc_spapr_init; 3004 mc->reset = ppc_spapr_reset; 3005 mc->block_default_type = IF_SCSI; 3006 mc->max_cpus = 1024; 3007 mc->no_parallel = 1; 3008 mc->default_boot_order = ""; 3009 mc->default_ram_size = 512 * M_BYTE; 3010 mc->kvm_type = spapr_kvm_type; 3011 mc->has_dynamic_sysbus = true; 3012 mc->pci_allow_0_address = true; 3013 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3014 hc->pre_plug = spapr_machine_device_pre_plug; 3015 hc->plug = spapr_machine_device_plug; 3016 hc->unplug = spapr_machine_device_unplug; 3017 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id; 3018 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3019 hc->unplug_request = spapr_machine_device_unplug_request; 3020 3021 smc->dr_lmb_enabled = true; 3022 smc->tcg_default_cpu = "POWER8"; 3023 mc->has_hotpluggable_cpus = true; 3024 fwc->get_dev_path = spapr_get_fw_dev_path; 3025 nc->nmi_monitor_handler = spapr_nmi; 3026 smc->phb_placement = spapr_phb_placement; 3027 vhc->hypercall = emulate_spapr_hypercall; 3028 vhc->hpt_mask = spapr_hpt_mask; 3029 vhc->map_hptes = spapr_map_hptes; 3030 vhc->unmap_hptes = spapr_unmap_hptes; 3031 vhc->store_hpte = spapr_store_hpte; 3032 xic->ics_get = spapr_ics_get; 3033 xic->ics_resend = spapr_ics_resend; 3034 } 3035 3036 static const TypeInfo spapr_machine_info = { 3037 .name = TYPE_SPAPR_MACHINE, 3038 .parent = TYPE_MACHINE, 3039 .abstract = true, 3040 .instance_size = sizeof(sPAPRMachineState), 3041 .instance_init = spapr_machine_initfn, 3042 .instance_finalize = spapr_machine_finalizefn, 3043 .class_size = sizeof(sPAPRMachineClass), 3044 .class_init = spapr_machine_class_init, 3045 .interfaces = (InterfaceInfo[]) { 3046 { TYPE_FW_PATH_PROVIDER }, 3047 { TYPE_NMI }, 3048 { TYPE_HOTPLUG_HANDLER }, 3049 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 3050 { TYPE_XICS_FABRIC }, 3051 { } 3052 }, 3053 }; 3054 3055 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 3056 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 3057 void *data) \ 3058 { \ 3059 MachineClass *mc = MACHINE_CLASS(oc); \ 3060 spapr_machine_##suffix##_class_options(mc); \ 3061 if (latest) { \ 3062 mc->alias = "pseries"; \ 3063 mc->is_default = 1; \ 3064 } \ 3065 } \ 3066 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 3067 { \ 3068 MachineState *machine = MACHINE(obj); \ 3069 spapr_machine_##suffix##_instance_options(machine); \ 3070 } \ 3071 static const TypeInfo spapr_machine_##suffix##_info = { \ 3072 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 3073 .parent = TYPE_SPAPR_MACHINE, \ 3074 .class_init = spapr_machine_##suffix##_class_init, \ 3075 .instance_init = spapr_machine_##suffix##_instance_init, \ 3076 }; \ 3077 static void spapr_machine_register_##suffix(void) \ 3078 { \ 3079 type_register(&spapr_machine_##suffix##_info); \ 3080 } \ 3081 type_init(spapr_machine_register_##suffix) 3082 3083 /* 3084 * pseries-2.9 3085 */ 3086 static void spapr_machine_2_9_instance_options(MachineState *machine) 3087 { 3088 } 3089 3090 static void spapr_machine_2_9_class_options(MachineClass *mc) 3091 { 3092 /* Defaults for the latest behaviour inherited from the base class */ 3093 } 3094 3095 DEFINE_SPAPR_MACHINE(2_9, "2.9", true); 3096 3097 /* 3098 * pseries-2.8 3099 */ 3100 #define SPAPR_COMPAT_2_8 \ 3101 HW_COMPAT_2_8 3102 3103 static void spapr_machine_2_8_instance_options(MachineState *machine) 3104 { 3105 spapr_machine_2_9_instance_options(machine); 3106 } 3107 3108 static void spapr_machine_2_8_class_options(MachineClass *mc) 3109 { 3110 spapr_machine_2_9_class_options(mc); 3111 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 3112 } 3113 3114 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 3115 3116 /* 3117 * pseries-2.7 3118 */ 3119 #define SPAPR_COMPAT_2_7 \ 3120 HW_COMPAT_2_7 \ 3121 { \ 3122 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3123 .property = "mem_win_size", \ 3124 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 3125 }, \ 3126 { \ 3127 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3128 .property = "mem64_win_size", \ 3129 .value = "0", \ 3130 }, \ 3131 { \ 3132 .driver = TYPE_POWERPC_CPU, \ 3133 .property = "pre-2.8-migration", \ 3134 .value = "on", \ 3135 }, \ 3136 { \ 3137 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3138 .property = "pre-2.8-migration", \ 3139 .value = "on", \ 3140 }, 3141 3142 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 3143 uint64_t *buid, hwaddr *pio, 3144 hwaddr *mmio32, hwaddr *mmio64, 3145 unsigned n_dma, uint32_t *liobns, Error **errp) 3146 { 3147 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 3148 const uint64_t base_buid = 0x800000020000000ULL; 3149 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 3150 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 3151 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 3152 const uint32_t max_index = 255; 3153 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 3154 3155 uint64_t ram_top = MACHINE(spapr)->ram_size; 3156 hwaddr phb0_base, phb_base; 3157 int i; 3158 3159 /* Do we have hotpluggable memory? */ 3160 if (MACHINE(spapr)->maxram_size > ram_top) { 3161 /* Can't just use maxram_size, because there may be an 3162 * alignment gap between normal and hotpluggable memory 3163 * regions */ 3164 ram_top = spapr->hotplug_memory.base + 3165 memory_region_size(&spapr->hotplug_memory.mr); 3166 } 3167 3168 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 3169 3170 if (index > max_index) { 3171 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 3172 max_index); 3173 return; 3174 } 3175 3176 *buid = base_buid + index; 3177 for (i = 0; i < n_dma; ++i) { 3178 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3179 } 3180 3181 phb_base = phb0_base + index * phb_spacing; 3182 *pio = phb_base + pio_offset; 3183 *mmio32 = phb_base + mmio_offset; 3184 /* 3185 * We don't set the 64-bit MMIO window, relying on the PHB's 3186 * fallback behaviour of automatically splitting a large "32-bit" 3187 * window into contiguous 32-bit and 64-bit windows 3188 */ 3189 } 3190 3191 static void spapr_machine_2_7_instance_options(MachineState *machine) 3192 { 3193 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 3194 3195 spapr_machine_2_8_instance_options(machine); 3196 spapr->use_hotplug_event_source = false; 3197 } 3198 3199 static void spapr_machine_2_7_class_options(MachineClass *mc) 3200 { 3201 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3202 3203 spapr_machine_2_8_class_options(mc); 3204 smc->tcg_default_cpu = "POWER7"; 3205 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 3206 smc->phb_placement = phb_placement_2_7; 3207 } 3208 3209 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 3210 3211 /* 3212 * pseries-2.6 3213 */ 3214 #define SPAPR_COMPAT_2_6 \ 3215 HW_COMPAT_2_6 \ 3216 { \ 3217 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3218 .property = "ddw",\ 3219 .value = stringify(off),\ 3220 }, 3221 3222 static void spapr_machine_2_6_instance_options(MachineState *machine) 3223 { 3224 spapr_machine_2_7_instance_options(machine); 3225 } 3226 3227 static void spapr_machine_2_6_class_options(MachineClass *mc) 3228 { 3229 spapr_machine_2_7_class_options(mc); 3230 mc->has_hotpluggable_cpus = false; 3231 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 3232 } 3233 3234 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 3235 3236 /* 3237 * pseries-2.5 3238 */ 3239 #define SPAPR_COMPAT_2_5 \ 3240 HW_COMPAT_2_5 \ 3241 { \ 3242 .driver = "spapr-vlan", \ 3243 .property = "use-rx-buffer-pools", \ 3244 .value = "off", \ 3245 }, 3246 3247 static void spapr_machine_2_5_instance_options(MachineState *machine) 3248 { 3249 spapr_machine_2_6_instance_options(machine); 3250 } 3251 3252 static void spapr_machine_2_5_class_options(MachineClass *mc) 3253 { 3254 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3255 3256 spapr_machine_2_6_class_options(mc); 3257 smc->use_ohci_by_default = true; 3258 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 3259 } 3260 3261 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 3262 3263 /* 3264 * pseries-2.4 3265 */ 3266 #define SPAPR_COMPAT_2_4 \ 3267 HW_COMPAT_2_4 3268 3269 static void spapr_machine_2_4_instance_options(MachineState *machine) 3270 { 3271 spapr_machine_2_5_instance_options(machine); 3272 } 3273 3274 static void spapr_machine_2_4_class_options(MachineClass *mc) 3275 { 3276 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3277 3278 spapr_machine_2_5_class_options(mc); 3279 smc->dr_lmb_enabled = false; 3280 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 3281 } 3282 3283 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 3284 3285 /* 3286 * pseries-2.3 3287 */ 3288 #define SPAPR_COMPAT_2_3 \ 3289 HW_COMPAT_2_3 \ 3290 {\ 3291 .driver = "spapr-pci-host-bridge",\ 3292 .property = "dynamic-reconfiguration",\ 3293 .value = "off",\ 3294 }, 3295 3296 static void spapr_machine_2_3_instance_options(MachineState *machine) 3297 { 3298 spapr_machine_2_4_instance_options(machine); 3299 savevm_skip_section_footers(); 3300 global_state_set_optional(); 3301 savevm_skip_configuration(); 3302 } 3303 3304 static void spapr_machine_2_3_class_options(MachineClass *mc) 3305 { 3306 spapr_machine_2_4_class_options(mc); 3307 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 3308 } 3309 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 3310 3311 /* 3312 * pseries-2.2 3313 */ 3314 3315 #define SPAPR_COMPAT_2_2 \ 3316 HW_COMPAT_2_2 \ 3317 {\ 3318 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3319 .property = "mem_win_size",\ 3320 .value = "0x20000000",\ 3321 }, 3322 3323 static void spapr_machine_2_2_instance_options(MachineState *machine) 3324 { 3325 spapr_machine_2_3_instance_options(machine); 3326 machine->suppress_vmdesc = true; 3327 } 3328 3329 static void spapr_machine_2_2_class_options(MachineClass *mc) 3330 { 3331 spapr_machine_2_3_class_options(mc); 3332 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 3333 } 3334 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 3335 3336 /* 3337 * pseries-2.1 3338 */ 3339 #define SPAPR_COMPAT_2_1 \ 3340 HW_COMPAT_2_1 3341 3342 static void spapr_machine_2_1_instance_options(MachineState *machine) 3343 { 3344 spapr_machine_2_2_instance_options(machine); 3345 } 3346 3347 static void spapr_machine_2_1_class_options(MachineClass *mc) 3348 { 3349 spapr_machine_2_2_class_options(mc); 3350 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 3351 } 3352 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 3353 3354 static void spapr_machine_register_types(void) 3355 { 3356 type_register_static(&spapr_machine_info); 3357 } 3358 3359 type_init(spapr_machine_register_types) 3360