1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qapi/error.h" 30 #include "qapi/visitor.h" 31 #include "sysemu/sysemu.h" 32 #include "sysemu/hostmem.h" 33 #include "sysemu/numa.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/reset.h" 36 #include "sysemu/runstate.h" 37 #include "qemu/log.h" 38 #include "hw/fw-path-provider.h" 39 #include "elf.h" 40 #include "net/net.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/cpus.h" 43 #include "sysemu/hw_accel.h" 44 #include "kvm_ppc.h" 45 #include "migration/misc.h" 46 #include "migration/qemu-file-types.h" 47 #include "migration/global_state.h" 48 #include "migration/register.h" 49 #include "migration/blocker.h" 50 #include "mmu-hash64.h" 51 #include "mmu-book3s-v3.h" 52 #include "cpu-models.h" 53 #include "hw/core/cpu.h" 54 55 #include "hw/boards.h" 56 #include "hw/ppc/ppc.h" 57 #include "hw/loader.h" 58 59 #include "hw/ppc/fdt.h" 60 #include "hw/ppc/spapr.h" 61 #include "hw/ppc/spapr_vio.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/pci-host/spapr.h" 64 #include "hw/pci/msi.h" 65 66 #include "hw/pci/pci.h" 67 #include "hw/scsi/scsi.h" 68 #include "hw/virtio/virtio-scsi.h" 69 #include "hw/virtio/vhost-scsi-common.h" 70 71 #include "exec/address-spaces.h" 72 #include "exec/ram_addr.h" 73 #include "hw/usb.h" 74 #include "qemu/config-file.h" 75 #include "qemu/error-report.h" 76 #include "trace.h" 77 #include "hw/nmi.h" 78 #include "hw/intc/intc.h" 79 80 #include "hw/ppc/spapr_cpu_core.h" 81 #include "hw/mem/memory-device.h" 82 #include "hw/ppc/spapr_tpm_proxy.h" 83 #include "hw/ppc/spapr_nvdimm.h" 84 #include "hw/ppc/spapr_numa.h" 85 86 #include "monitor/monitor.h" 87 88 #include <libfdt.h> 89 90 /* SLOF memory layout: 91 * 92 * SLOF raw image loaded at 0, copies its romfs right below the flat 93 * device-tree, then position SLOF itself 31M below that 94 * 95 * So we set FW_OVERHEAD to 40MB which should account for all of that 96 * and more 97 * 98 * We load our kernel at 4M, leaving space for SLOF initial image 99 */ 100 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 101 #define FW_MAX_SIZE 0x400000 102 #define FW_FILE_NAME "slof.bin" 103 #define FW_OVERHEAD 0x2800000 104 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 105 106 #define MIN_RMA_SLOF (128 * MiB) 107 108 #define PHANDLE_INTC 0x00001111 109 110 /* These two functions implement the VCPU id numbering: one to compute them 111 * all and one to identify thread 0 of a VCORE. Any change to the first one 112 * is likely to have an impact on the second one, so let's keep them close. 113 */ 114 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 115 { 116 MachineState *ms = MACHINE(spapr); 117 unsigned int smp_threads = ms->smp.threads; 118 119 assert(spapr->vsmt); 120 return 121 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 122 } 123 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 124 PowerPCCPU *cpu) 125 { 126 assert(spapr->vsmt); 127 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 128 } 129 130 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 131 { 132 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 133 * and newer QEMUs don't even have them. In both cases, we don't want 134 * to send anything on the wire. 135 */ 136 return false; 137 } 138 139 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 140 .name = "icp/server", 141 .version_id = 1, 142 .minimum_version_id = 1, 143 .needed = pre_2_10_vmstate_dummy_icp_needed, 144 .fields = (VMStateField[]) { 145 VMSTATE_UNUSED(4), /* uint32_t xirr */ 146 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 147 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 148 VMSTATE_END_OF_LIST() 149 }, 150 }; 151 152 static void pre_2_10_vmstate_register_dummy_icp(int i) 153 { 154 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 155 (void *)(uintptr_t) i); 156 } 157 158 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 159 { 160 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 161 (void *)(uintptr_t) i); 162 } 163 164 int spapr_max_server_number(SpaprMachineState *spapr) 165 { 166 MachineState *ms = MACHINE(spapr); 167 168 assert(spapr->vsmt); 169 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 170 } 171 172 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 173 int smt_threads) 174 { 175 int i, ret = 0; 176 uint32_t servers_prop[smt_threads]; 177 uint32_t gservers_prop[smt_threads * 2]; 178 int index = spapr_get_vcpu_id(cpu); 179 180 if (cpu->compat_pvr) { 181 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 182 if (ret < 0) { 183 return ret; 184 } 185 } 186 187 /* Build interrupt servers and gservers properties */ 188 for (i = 0; i < smt_threads; i++) { 189 servers_prop[i] = cpu_to_be32(index + i); 190 /* Hack, direct the group queues back to cpu 0 */ 191 gservers_prop[i*2] = cpu_to_be32(index + i); 192 gservers_prop[i*2 + 1] = 0; 193 } 194 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 195 servers_prop, sizeof(servers_prop)); 196 if (ret < 0) { 197 return ret; 198 } 199 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 200 gservers_prop, sizeof(gservers_prop)); 201 202 return ret; 203 } 204 205 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 206 { 207 int index = spapr_get_vcpu_id(cpu); 208 uint32_t associativity[] = {cpu_to_be32(0x5), 209 cpu_to_be32(0x0), 210 cpu_to_be32(0x0), 211 cpu_to_be32(0x0), 212 cpu_to_be32(cpu->node_id), 213 cpu_to_be32(index)}; 214 215 /* Advertise NUMA via ibm,associativity */ 216 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 217 sizeof(associativity)); 218 } 219 220 static void spapr_dt_pa_features(SpaprMachineState *spapr, 221 PowerPCCPU *cpu, 222 void *fdt, int offset) 223 { 224 uint8_t pa_features_206[] = { 6, 0, 225 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 226 uint8_t pa_features_207[] = { 24, 0, 227 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 228 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 229 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 230 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 231 uint8_t pa_features_300[] = { 66, 0, 232 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 233 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 234 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 235 /* 6: DS207 */ 236 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 237 /* 16: Vector */ 238 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 239 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 240 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 241 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 242 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 243 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 244 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 245 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 246 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 247 /* 42: PM, 44: PC RA, 46: SC vec'd */ 248 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 249 /* 48: SIMD, 50: QP BFP, 52: String */ 250 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 251 /* 54: DecFP, 56: DecI, 58: SHA */ 252 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 253 /* 60: NM atomic, 62: RNG */ 254 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 255 }; 256 uint8_t *pa_features = NULL; 257 size_t pa_size; 258 259 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 260 pa_features = pa_features_206; 261 pa_size = sizeof(pa_features_206); 262 } 263 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 264 pa_features = pa_features_207; 265 pa_size = sizeof(pa_features_207); 266 } 267 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 268 pa_features = pa_features_300; 269 pa_size = sizeof(pa_features_300); 270 } 271 if (!pa_features) { 272 return; 273 } 274 275 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 276 /* 277 * Note: we keep CI large pages off by default because a 64K capable 278 * guest provisioned with large pages might otherwise try to map a qemu 279 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 280 * even if that qemu runs on a 4k host. 281 * We dd this bit back here if we are confident this is not an issue 282 */ 283 pa_features[3] |= 0x20; 284 } 285 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 286 pa_features[24] |= 0x80; /* Transactional memory support */ 287 } 288 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 289 /* Workaround for broken kernels that attempt (guest) radix 290 * mode when they can't handle it, if they see the radix bit set 291 * in pa-features. So hide it from them. */ 292 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 293 } 294 295 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 296 } 297 298 static hwaddr spapr_node0_size(MachineState *machine) 299 { 300 if (machine->numa_state->num_nodes) { 301 int i; 302 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 303 if (machine->numa_state->nodes[i].node_mem) { 304 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 305 machine->ram_size); 306 } 307 } 308 } 309 return machine->ram_size; 310 } 311 312 static void add_str(GString *s, const gchar *s1) 313 { 314 g_string_append_len(s, s1, strlen(s1) + 1); 315 } 316 317 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 318 hwaddr start, hwaddr size) 319 { 320 char mem_name[32]; 321 uint64_t mem_reg_property[2]; 322 int off; 323 324 mem_reg_property[0] = cpu_to_be64(start); 325 mem_reg_property[1] = cpu_to_be64(size); 326 327 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 328 off = fdt_add_subnode(fdt, 0, mem_name); 329 _FDT(off); 330 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 331 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 332 sizeof(mem_reg_property)))); 333 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 334 return off; 335 } 336 337 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 338 { 339 MemoryDeviceInfoList *info; 340 341 for (info = list; info; info = info->next) { 342 MemoryDeviceInfo *value = info->value; 343 344 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 345 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 346 347 if (addr >= pcdimm_info->addr && 348 addr < (pcdimm_info->addr + pcdimm_info->size)) { 349 return pcdimm_info->node; 350 } 351 } 352 } 353 354 return -1; 355 } 356 357 struct sPAPRDrconfCellV2 { 358 uint32_t seq_lmbs; 359 uint64_t base_addr; 360 uint32_t drc_index; 361 uint32_t aa_index; 362 uint32_t flags; 363 } QEMU_PACKED; 364 365 typedef struct DrconfCellQueue { 366 struct sPAPRDrconfCellV2 cell; 367 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 368 } DrconfCellQueue; 369 370 static DrconfCellQueue * 371 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 372 uint32_t drc_index, uint32_t aa_index, 373 uint32_t flags) 374 { 375 DrconfCellQueue *elem; 376 377 elem = g_malloc0(sizeof(*elem)); 378 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 379 elem->cell.base_addr = cpu_to_be64(base_addr); 380 elem->cell.drc_index = cpu_to_be32(drc_index); 381 elem->cell.aa_index = cpu_to_be32(aa_index); 382 elem->cell.flags = cpu_to_be32(flags); 383 384 return elem; 385 } 386 387 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 388 int offset, MemoryDeviceInfoList *dimms) 389 { 390 MachineState *machine = MACHINE(spapr); 391 uint8_t *int_buf, *cur_index; 392 int ret; 393 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 394 uint64_t addr, cur_addr, size; 395 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 396 uint64_t mem_end = machine->device_memory->base + 397 memory_region_size(&machine->device_memory->mr); 398 uint32_t node, buf_len, nr_entries = 0; 399 SpaprDrc *drc; 400 DrconfCellQueue *elem, *next; 401 MemoryDeviceInfoList *info; 402 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 403 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 404 405 /* Entry to cover RAM and the gap area */ 406 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 407 SPAPR_LMB_FLAGS_RESERVED | 408 SPAPR_LMB_FLAGS_DRC_INVALID); 409 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 410 nr_entries++; 411 412 cur_addr = machine->device_memory->base; 413 for (info = dimms; info; info = info->next) { 414 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 415 416 addr = di->addr; 417 size = di->size; 418 node = di->node; 419 420 /* 421 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 422 * area is marked hotpluggable in the next iteration for the bigger 423 * chunk including the NVDIMM occupied area. 424 */ 425 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 426 continue; 427 428 /* Entry for hot-pluggable area */ 429 if (cur_addr < addr) { 430 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 431 g_assert(drc); 432 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 433 cur_addr, spapr_drc_index(drc), -1, 0); 434 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 435 nr_entries++; 436 } 437 438 /* Entry for DIMM */ 439 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 440 g_assert(drc); 441 elem = spapr_get_drconf_cell(size / lmb_size, addr, 442 spapr_drc_index(drc), node, 443 (SPAPR_LMB_FLAGS_ASSIGNED | 444 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 445 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 446 nr_entries++; 447 cur_addr = addr + size; 448 } 449 450 /* Entry for remaining hotpluggable area */ 451 if (cur_addr < mem_end) { 452 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 453 g_assert(drc); 454 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 455 cur_addr, spapr_drc_index(drc), -1, 0); 456 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 457 nr_entries++; 458 } 459 460 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 461 int_buf = cur_index = g_malloc0(buf_len); 462 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 463 cur_index += sizeof(nr_entries); 464 465 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 466 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 467 cur_index += sizeof(elem->cell); 468 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 469 g_free(elem); 470 } 471 472 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 473 g_free(int_buf); 474 if (ret < 0) { 475 return -1; 476 } 477 return 0; 478 } 479 480 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 481 int offset, MemoryDeviceInfoList *dimms) 482 { 483 MachineState *machine = MACHINE(spapr); 484 int i, ret; 485 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 486 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 487 uint32_t nr_lmbs = (machine->device_memory->base + 488 memory_region_size(&machine->device_memory->mr)) / 489 lmb_size; 490 uint32_t *int_buf, *cur_index, buf_len; 491 492 /* 493 * Allocate enough buffer size to fit in ibm,dynamic-memory 494 */ 495 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 496 cur_index = int_buf = g_malloc0(buf_len); 497 int_buf[0] = cpu_to_be32(nr_lmbs); 498 cur_index++; 499 for (i = 0; i < nr_lmbs; i++) { 500 uint64_t addr = i * lmb_size; 501 uint32_t *dynamic_memory = cur_index; 502 503 if (i >= device_lmb_start) { 504 SpaprDrc *drc; 505 506 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 507 g_assert(drc); 508 509 dynamic_memory[0] = cpu_to_be32(addr >> 32); 510 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 511 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 512 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 513 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 514 if (memory_region_present(get_system_memory(), addr)) { 515 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 516 } else { 517 dynamic_memory[5] = cpu_to_be32(0); 518 } 519 } else { 520 /* 521 * LMB information for RMA, boot time RAM and gap b/n RAM and 522 * device memory region -- all these are marked as reserved 523 * and as having no valid DRC. 524 */ 525 dynamic_memory[0] = cpu_to_be32(addr >> 32); 526 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 527 dynamic_memory[2] = cpu_to_be32(0); 528 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 529 dynamic_memory[4] = cpu_to_be32(-1); 530 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 531 SPAPR_LMB_FLAGS_DRC_INVALID); 532 } 533 534 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 535 } 536 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 537 g_free(int_buf); 538 if (ret < 0) { 539 return -1; 540 } 541 return 0; 542 } 543 544 /* 545 * Adds ibm,dynamic-reconfiguration-memory node. 546 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 547 * of this device tree node. 548 */ 549 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 550 void *fdt) 551 { 552 MachineState *machine = MACHINE(spapr); 553 int nb_numa_nodes = machine->numa_state->num_nodes; 554 int ret, i, offset; 555 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 556 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 557 cpu_to_be32(lmb_size & 0xffffffff)}; 558 uint32_t *int_buf, *cur_index, buf_len; 559 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 560 MemoryDeviceInfoList *dimms = NULL; 561 562 /* 563 * Don't create the node if there is no device memory 564 */ 565 if (machine->ram_size == machine->maxram_size) { 566 return 0; 567 } 568 569 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 570 571 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 572 sizeof(prop_lmb_size)); 573 if (ret < 0) { 574 return ret; 575 } 576 577 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 578 if (ret < 0) { 579 return ret; 580 } 581 582 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 583 if (ret < 0) { 584 return ret; 585 } 586 587 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 588 dimms = qmp_memory_device_list(); 589 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 590 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 591 } else { 592 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 593 } 594 qapi_free_MemoryDeviceInfoList(dimms); 595 596 if (ret < 0) { 597 return ret; 598 } 599 600 /* ibm,associativity-lookup-arrays */ 601 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 602 cur_index = int_buf = g_malloc0(buf_len); 603 int_buf[0] = cpu_to_be32(nr_nodes); 604 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 605 cur_index += 2; 606 for (i = 0; i < nr_nodes; i++) { 607 uint32_t associativity[] = { 608 cpu_to_be32(0x0), 609 cpu_to_be32(0x0), 610 cpu_to_be32(0x0), 611 cpu_to_be32(i) 612 }; 613 memcpy(cur_index, associativity, sizeof(associativity)); 614 cur_index += 4; 615 } 616 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 617 (cur_index - int_buf) * sizeof(uint32_t)); 618 g_free(int_buf); 619 620 return ret; 621 } 622 623 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 624 { 625 MachineState *machine = MACHINE(spapr); 626 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 627 hwaddr mem_start, node_size; 628 int i, nb_nodes = machine->numa_state->num_nodes; 629 NodeInfo *nodes = machine->numa_state->nodes; 630 631 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 632 if (!nodes[i].node_mem) { 633 continue; 634 } 635 if (mem_start >= machine->ram_size) { 636 node_size = 0; 637 } else { 638 node_size = nodes[i].node_mem; 639 if (node_size > machine->ram_size - mem_start) { 640 node_size = machine->ram_size - mem_start; 641 } 642 } 643 if (!mem_start) { 644 /* spapr_machine_init() checks for rma_size <= node0_size 645 * already */ 646 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 647 mem_start += spapr->rma_size; 648 node_size -= spapr->rma_size; 649 } 650 for ( ; node_size; ) { 651 hwaddr sizetmp = pow2floor(node_size); 652 653 /* mem_start != 0 here */ 654 if (ctzl(mem_start) < ctzl(sizetmp)) { 655 sizetmp = 1ULL << ctzl(mem_start); 656 } 657 658 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 659 node_size -= sizetmp; 660 mem_start += sizetmp; 661 } 662 } 663 664 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 665 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 666 int ret; 667 668 g_assert(smc->dr_lmb_enabled); 669 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 670 if (ret) { 671 return ret; 672 } 673 } 674 675 return 0; 676 } 677 678 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 679 SpaprMachineState *spapr) 680 { 681 MachineState *ms = MACHINE(spapr); 682 PowerPCCPU *cpu = POWERPC_CPU(cs); 683 CPUPPCState *env = &cpu->env; 684 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 685 int index = spapr_get_vcpu_id(cpu); 686 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 687 0xffffffff, 0xffffffff}; 688 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 689 : SPAPR_TIMEBASE_FREQ; 690 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 691 uint32_t page_sizes_prop[64]; 692 size_t page_sizes_prop_size; 693 unsigned int smp_threads = ms->smp.threads; 694 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 695 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 696 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 697 SpaprDrc *drc; 698 int drc_index; 699 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 700 int i; 701 702 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 703 if (drc) { 704 drc_index = spapr_drc_index(drc); 705 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 706 } 707 708 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 709 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 710 711 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 712 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 713 env->dcache_line_size))); 714 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 715 env->dcache_line_size))); 716 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 717 env->icache_line_size))); 718 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 719 env->icache_line_size))); 720 721 if (pcc->l1_dcache_size) { 722 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 723 pcc->l1_dcache_size))); 724 } else { 725 warn_report("Unknown L1 dcache size for cpu"); 726 } 727 if (pcc->l1_icache_size) { 728 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 729 pcc->l1_icache_size))); 730 } else { 731 warn_report("Unknown L1 icache size for cpu"); 732 } 733 734 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 735 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 736 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 737 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 738 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 739 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 740 741 if (env->spr_cb[SPR_PURR].oea_read) { 742 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 743 } 744 if (env->spr_cb[SPR_SPURR].oea_read) { 745 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 746 } 747 748 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 749 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 750 segs, sizeof(segs)))); 751 } 752 753 /* Advertise VSX (vector extensions) if available 754 * 1 == VMX / Altivec available 755 * 2 == VSX available 756 * 757 * Only CPUs for which we create core types in spapr_cpu_core.c 758 * are possible, and all of those have VMX */ 759 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 760 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 761 } else { 762 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 763 } 764 765 /* Advertise DFP (Decimal Floating Point) if available 766 * 0 / no property == no DFP 767 * 1 == DFP available */ 768 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 769 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 770 } 771 772 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 773 sizeof(page_sizes_prop)); 774 if (page_sizes_prop_size) { 775 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 776 page_sizes_prop, page_sizes_prop_size))); 777 } 778 779 spapr_dt_pa_features(spapr, cpu, fdt, offset); 780 781 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 782 cs->cpu_index / vcpus_per_socket))); 783 784 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 785 pft_size_prop, sizeof(pft_size_prop)))); 786 787 if (ms->numa_state->num_nodes > 1) { 788 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 789 } 790 791 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 792 793 if (pcc->radix_page_info) { 794 for (i = 0; i < pcc->radix_page_info->count; i++) { 795 radix_AP_encodings[i] = 796 cpu_to_be32(pcc->radix_page_info->entries[i]); 797 } 798 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 799 radix_AP_encodings, 800 pcc->radix_page_info->count * 801 sizeof(radix_AP_encodings[0])))); 802 } 803 804 /* 805 * We set this property to let the guest know that it can use the large 806 * decrementer and its width in bits. 807 */ 808 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 809 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 810 pcc->lrg_decr_bits))); 811 } 812 813 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 814 { 815 CPUState **rev; 816 CPUState *cs; 817 int n_cpus; 818 int cpus_offset; 819 char *nodename; 820 int i; 821 822 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 823 _FDT(cpus_offset); 824 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 825 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 826 827 /* 828 * We walk the CPUs in reverse order to ensure that CPU DT nodes 829 * created by fdt_add_subnode() end up in the right order in FDT 830 * for the guest kernel the enumerate the CPUs correctly. 831 * 832 * The CPU list cannot be traversed in reverse order, so we need 833 * to do extra work. 834 */ 835 n_cpus = 0; 836 rev = NULL; 837 CPU_FOREACH(cs) { 838 rev = g_renew(CPUState *, rev, n_cpus + 1); 839 rev[n_cpus++] = cs; 840 } 841 842 for (i = n_cpus - 1; i >= 0; i--) { 843 CPUState *cs = rev[i]; 844 PowerPCCPU *cpu = POWERPC_CPU(cs); 845 int index = spapr_get_vcpu_id(cpu); 846 DeviceClass *dc = DEVICE_GET_CLASS(cs); 847 int offset; 848 849 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 850 continue; 851 } 852 853 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 854 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 855 g_free(nodename); 856 _FDT(offset); 857 spapr_dt_cpu(cs, fdt, offset, spapr); 858 } 859 860 g_free(rev); 861 } 862 863 static int spapr_dt_rng(void *fdt) 864 { 865 int node; 866 int ret; 867 868 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 869 if (node <= 0) { 870 return -1; 871 } 872 ret = fdt_setprop_string(fdt, node, "device_type", 873 "ibm,platform-facilities"); 874 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 875 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 876 877 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 878 if (node <= 0) { 879 return -1; 880 } 881 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 882 883 return ret ? -1 : 0; 884 } 885 886 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 887 { 888 MachineState *ms = MACHINE(spapr); 889 int rtas; 890 GString *hypertas = g_string_sized_new(256); 891 GString *qemu_hypertas = g_string_sized_new(256); 892 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 893 memory_region_size(&MACHINE(spapr)->device_memory->mr); 894 uint32_t lrdr_capacity[] = { 895 cpu_to_be32(max_device_addr >> 32), 896 cpu_to_be32(max_device_addr & 0xffffffff), 897 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 898 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 899 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 900 }; 901 902 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 903 904 /* hypertas */ 905 add_str(hypertas, "hcall-pft"); 906 add_str(hypertas, "hcall-term"); 907 add_str(hypertas, "hcall-dabr"); 908 add_str(hypertas, "hcall-interrupt"); 909 add_str(hypertas, "hcall-tce"); 910 add_str(hypertas, "hcall-vio"); 911 add_str(hypertas, "hcall-splpar"); 912 add_str(hypertas, "hcall-join"); 913 add_str(hypertas, "hcall-bulk"); 914 add_str(hypertas, "hcall-set-mode"); 915 add_str(hypertas, "hcall-sprg0"); 916 add_str(hypertas, "hcall-copy"); 917 add_str(hypertas, "hcall-debug"); 918 add_str(hypertas, "hcall-vphn"); 919 add_str(qemu_hypertas, "hcall-memop1"); 920 921 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 922 add_str(hypertas, "hcall-multi-tce"); 923 } 924 925 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 926 add_str(hypertas, "hcall-hpt-resize"); 927 } 928 929 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 930 hypertas->str, hypertas->len)); 931 g_string_free(hypertas, TRUE); 932 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 933 qemu_hypertas->str, qemu_hypertas->len)); 934 g_string_free(qemu_hypertas, TRUE); 935 936 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 937 938 /* 939 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 940 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 941 * 942 * The system reset requirements are driven by existing Linux and PowerVM 943 * implementation which (contrary to PAPR) saves r3 in the error log 944 * structure like machine check, so Linux expects to find the saved r3 945 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 946 * does not look at the error value). 947 * 948 * System reset interrupts are not subject to interlock like machine 949 * check, so this memory area could be corrupted if the sreset is 950 * interrupted by a machine check (or vice versa) if it was shared. To 951 * prevent this, system reset uses per-CPU areas for the sreset save 952 * area. A system reset that interrupts a system reset handler could 953 * still overwrite this area, but Linux doesn't try to recover in that 954 * case anyway. 955 * 956 * The extra 8 bytes is required because Linux's FWNMI error log check 957 * is off-by-one. 958 */ 959 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_ERROR_LOG_MAX + 960 ms->smp.max_cpus * sizeof(uint64_t)*2 + sizeof(uint64_t))); 961 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 962 RTAS_ERROR_LOG_MAX)); 963 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 964 RTAS_EVENT_SCAN_RATE)); 965 966 g_assert(msi_nonbroken); 967 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 968 969 /* 970 * According to PAPR, rtas ibm,os-term does not guarantee a return 971 * back to the guest cpu. 972 * 973 * While an additional ibm,extended-os-term property indicates 974 * that rtas call return will always occur. Set this property. 975 */ 976 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 977 978 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 979 lrdr_capacity, sizeof(lrdr_capacity))); 980 981 spapr_dt_rtas_tokens(fdt, rtas); 982 } 983 984 /* 985 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 986 * and the XIVE features that the guest may request and thus the valid 987 * values for bytes 23..26 of option vector 5: 988 */ 989 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 990 int chosen) 991 { 992 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 993 994 char val[2 * 4] = { 995 23, 0x00, /* XICS / XIVE mode */ 996 24, 0x00, /* Hash/Radix, filled in below. */ 997 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 998 26, 0x40, /* Radix options: GTSE == yes. */ 999 }; 1000 1001 if (spapr->irq->xics && spapr->irq->xive) { 1002 val[1] = SPAPR_OV5_XIVE_BOTH; 1003 } else if (spapr->irq->xive) { 1004 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 1005 } else { 1006 assert(spapr->irq->xics); 1007 val[1] = SPAPR_OV5_XIVE_LEGACY; 1008 } 1009 1010 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1011 first_ppc_cpu->compat_pvr)) { 1012 /* 1013 * If we're in a pre POWER9 compat mode then the guest should 1014 * do hash and use the legacy interrupt mode 1015 */ 1016 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 1017 val[3] = 0x00; /* Hash */ 1018 } else if (kvm_enabled()) { 1019 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1020 val[3] = 0x80; /* OV5_MMU_BOTH */ 1021 } else if (kvmppc_has_cap_mmu_radix()) { 1022 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1023 } else { 1024 val[3] = 0x00; /* Hash */ 1025 } 1026 } else { 1027 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1028 val[3] = 0xC0; 1029 } 1030 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1031 val, sizeof(val))); 1032 } 1033 1034 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1035 { 1036 MachineState *machine = MACHINE(spapr); 1037 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1038 int chosen; 1039 1040 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1041 1042 if (reset) { 1043 const char *boot_device = machine->boot_order; 1044 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1045 size_t cb = 0; 1046 char *bootlist = get_boot_devices_list(&cb); 1047 1048 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1049 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1050 machine->kernel_cmdline)); 1051 } 1052 1053 if (spapr->initrd_size) { 1054 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1055 spapr->initrd_base)); 1056 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1057 spapr->initrd_base + spapr->initrd_size)); 1058 } 1059 1060 if (spapr->kernel_size) { 1061 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1062 cpu_to_be64(spapr->kernel_size) }; 1063 1064 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1065 &kprop, sizeof(kprop))); 1066 if (spapr->kernel_le) { 1067 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1068 } 1069 } 1070 if (boot_menu) { 1071 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1072 } 1073 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1074 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1075 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1076 1077 if (cb && bootlist) { 1078 int i; 1079 1080 for (i = 0; i < cb; i++) { 1081 if (bootlist[i] == '\n') { 1082 bootlist[i] = ' '; 1083 } 1084 } 1085 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1086 } 1087 1088 if (boot_device && strlen(boot_device)) { 1089 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1090 } 1091 1092 if (!spapr->has_graphics && stdout_path) { 1093 /* 1094 * "linux,stdout-path" and "stdout" properties are 1095 * deprecated by linux kernel. New platforms should only 1096 * use the "stdout-path" property. Set the new property 1097 * and continue using older property to remain compatible 1098 * with the existing firmware. 1099 */ 1100 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1101 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1102 } 1103 1104 /* 1105 * We can deal with BAR reallocation just fine, advertise it 1106 * to the guest 1107 */ 1108 if (smc->linux_pci_probe) { 1109 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1110 } 1111 1112 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1113 1114 g_free(stdout_path); 1115 g_free(bootlist); 1116 } 1117 1118 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1119 } 1120 1121 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1122 { 1123 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1124 * KVM to work under pHyp with some guest co-operation */ 1125 int hypervisor; 1126 uint8_t hypercall[16]; 1127 1128 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1129 /* indicate KVM hypercall interface */ 1130 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1131 if (kvmppc_has_cap_fixup_hcalls()) { 1132 /* 1133 * Older KVM versions with older guest kernels were broken 1134 * with the magic page, don't allow the guest to map it. 1135 */ 1136 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1137 sizeof(hypercall))) { 1138 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1139 hypercall, sizeof(hypercall))); 1140 } 1141 } 1142 } 1143 1144 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1145 { 1146 MachineState *machine = MACHINE(spapr); 1147 MachineClass *mc = MACHINE_GET_CLASS(machine); 1148 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1149 int ret; 1150 void *fdt; 1151 SpaprPhbState *phb; 1152 char *buf; 1153 1154 fdt = g_malloc0(space); 1155 _FDT((fdt_create_empty_tree(fdt, space))); 1156 1157 /* Root node */ 1158 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1159 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1160 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1161 1162 /* Guest UUID & Name*/ 1163 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1164 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1165 if (qemu_uuid_set) { 1166 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1167 } 1168 g_free(buf); 1169 1170 if (qemu_get_vm_name()) { 1171 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1172 qemu_get_vm_name())); 1173 } 1174 1175 /* Host Model & Serial Number */ 1176 if (spapr->host_model) { 1177 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1178 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1179 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1180 g_free(buf); 1181 } 1182 1183 if (spapr->host_serial) { 1184 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1185 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1186 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1187 g_free(buf); 1188 } 1189 1190 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1191 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1192 1193 /* /interrupt controller */ 1194 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1195 1196 ret = spapr_dt_memory(spapr, fdt); 1197 if (ret < 0) { 1198 error_report("couldn't setup memory nodes in fdt"); 1199 exit(1); 1200 } 1201 1202 /* /vdevice */ 1203 spapr_dt_vdevice(spapr->vio_bus, fdt); 1204 1205 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1206 ret = spapr_dt_rng(fdt); 1207 if (ret < 0) { 1208 error_report("could not set up rng device in the fdt"); 1209 exit(1); 1210 } 1211 } 1212 1213 QLIST_FOREACH(phb, &spapr->phbs, list) { 1214 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1215 if (ret < 0) { 1216 error_report("couldn't setup PCI devices in fdt"); 1217 exit(1); 1218 } 1219 } 1220 1221 spapr_dt_cpus(fdt, spapr); 1222 1223 if (smc->dr_lmb_enabled) { 1224 _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1225 } 1226 1227 if (mc->has_hotpluggable_cpus) { 1228 int offset = fdt_path_offset(fdt, "/cpus"); 1229 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1230 if (ret < 0) { 1231 error_report("Couldn't set up CPU DR device tree properties"); 1232 exit(1); 1233 } 1234 } 1235 1236 /* /event-sources */ 1237 spapr_dt_events(spapr, fdt); 1238 1239 /* /rtas */ 1240 spapr_dt_rtas(spapr, fdt); 1241 1242 /* /chosen */ 1243 spapr_dt_chosen(spapr, fdt, reset); 1244 1245 /* /hypervisor */ 1246 if (kvm_enabled()) { 1247 spapr_dt_hypervisor(spapr, fdt); 1248 } 1249 1250 /* Build memory reserve map */ 1251 if (reset) { 1252 if (spapr->kernel_size) { 1253 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1254 spapr->kernel_size))); 1255 } 1256 if (spapr->initrd_size) { 1257 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1258 spapr->initrd_size))); 1259 } 1260 } 1261 1262 if (smc->dr_phb_enabled) { 1263 ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB); 1264 if (ret < 0) { 1265 error_report("Couldn't set up PHB DR device tree properties"); 1266 exit(1); 1267 } 1268 } 1269 1270 /* NVDIMM devices */ 1271 if (mc->nvdimm_supported) { 1272 spapr_dt_persistent_memory(spapr, fdt); 1273 } 1274 1275 return fdt; 1276 } 1277 1278 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1279 { 1280 SpaprMachineState *spapr = opaque; 1281 1282 return (addr & 0x0fffffff) + spapr->kernel_addr; 1283 } 1284 1285 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1286 PowerPCCPU *cpu) 1287 { 1288 CPUPPCState *env = &cpu->env; 1289 1290 /* The TCG path should also be holding the BQL at this point */ 1291 g_assert(qemu_mutex_iothread_locked()); 1292 1293 if (msr_pr) { 1294 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1295 env->gpr[3] = H_PRIVILEGE; 1296 } else { 1297 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1298 } 1299 } 1300 1301 struct LPCRSyncState { 1302 target_ulong value; 1303 target_ulong mask; 1304 }; 1305 1306 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1307 { 1308 struct LPCRSyncState *s = arg.host_ptr; 1309 PowerPCCPU *cpu = POWERPC_CPU(cs); 1310 CPUPPCState *env = &cpu->env; 1311 target_ulong lpcr; 1312 1313 cpu_synchronize_state(cs); 1314 lpcr = env->spr[SPR_LPCR]; 1315 lpcr &= ~s->mask; 1316 lpcr |= s->value; 1317 ppc_store_lpcr(cpu, lpcr); 1318 } 1319 1320 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1321 { 1322 CPUState *cs; 1323 struct LPCRSyncState s = { 1324 .value = value, 1325 .mask = mask 1326 }; 1327 CPU_FOREACH(cs) { 1328 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1329 } 1330 } 1331 1332 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1333 { 1334 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1335 1336 /* Copy PATE1:GR into PATE0:HR */ 1337 entry->dw0 = spapr->patb_entry & PATE0_HR; 1338 entry->dw1 = spapr->patb_entry; 1339 } 1340 1341 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1342 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1343 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1344 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1345 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1346 1347 /* 1348 * Get the fd to access the kernel htab, re-opening it if necessary 1349 */ 1350 static int get_htab_fd(SpaprMachineState *spapr) 1351 { 1352 Error *local_err = NULL; 1353 1354 if (spapr->htab_fd >= 0) { 1355 return spapr->htab_fd; 1356 } 1357 1358 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1359 if (spapr->htab_fd < 0) { 1360 error_report_err(local_err); 1361 } 1362 1363 return spapr->htab_fd; 1364 } 1365 1366 void close_htab_fd(SpaprMachineState *spapr) 1367 { 1368 if (spapr->htab_fd >= 0) { 1369 close(spapr->htab_fd); 1370 } 1371 spapr->htab_fd = -1; 1372 } 1373 1374 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1375 { 1376 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1377 1378 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1379 } 1380 1381 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1382 { 1383 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1384 1385 assert(kvm_enabled()); 1386 1387 if (!spapr->htab) { 1388 return 0; 1389 } 1390 1391 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1392 } 1393 1394 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1395 hwaddr ptex, int n) 1396 { 1397 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1398 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1399 1400 if (!spapr->htab) { 1401 /* 1402 * HTAB is controlled by KVM. Fetch into temporary buffer 1403 */ 1404 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1405 kvmppc_read_hptes(hptes, ptex, n); 1406 return hptes; 1407 } 1408 1409 /* 1410 * HTAB is controlled by QEMU. Just point to the internally 1411 * accessible PTEG. 1412 */ 1413 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1414 } 1415 1416 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1417 const ppc_hash_pte64_t *hptes, 1418 hwaddr ptex, int n) 1419 { 1420 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1421 1422 if (!spapr->htab) { 1423 g_free((void *)hptes); 1424 } 1425 1426 /* Nothing to do for qemu managed HPT */ 1427 } 1428 1429 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1430 uint64_t pte0, uint64_t pte1) 1431 { 1432 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1433 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1434 1435 if (!spapr->htab) { 1436 kvmppc_write_hpte(ptex, pte0, pte1); 1437 } else { 1438 if (pte0 & HPTE64_V_VALID) { 1439 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1440 /* 1441 * When setting valid, we write PTE1 first. This ensures 1442 * proper synchronization with the reading code in 1443 * ppc_hash64_pteg_search() 1444 */ 1445 smp_wmb(); 1446 stq_p(spapr->htab + offset, pte0); 1447 } else { 1448 stq_p(spapr->htab + offset, pte0); 1449 /* 1450 * When clearing it we set PTE0 first. This ensures proper 1451 * synchronization with the reading code in 1452 * ppc_hash64_pteg_search() 1453 */ 1454 smp_wmb(); 1455 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1456 } 1457 } 1458 } 1459 1460 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1461 uint64_t pte1) 1462 { 1463 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1464 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1465 1466 if (!spapr->htab) { 1467 /* There should always be a hash table when this is called */ 1468 error_report("spapr_hpte_set_c called with no hash table !"); 1469 return; 1470 } 1471 1472 /* The HW performs a non-atomic byte update */ 1473 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1474 } 1475 1476 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1477 uint64_t pte1) 1478 { 1479 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1480 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1481 1482 if (!spapr->htab) { 1483 /* There should always be a hash table when this is called */ 1484 error_report("spapr_hpte_set_r called with no hash table !"); 1485 return; 1486 } 1487 1488 /* The HW performs a non-atomic byte update */ 1489 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1490 } 1491 1492 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1493 { 1494 int shift; 1495 1496 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1497 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1498 * that's much more than is needed for Linux guests */ 1499 shift = ctz64(pow2ceil(ramsize)) - 7; 1500 shift = MAX(shift, 18); /* Minimum architected size */ 1501 shift = MIN(shift, 46); /* Maximum architected size */ 1502 return shift; 1503 } 1504 1505 void spapr_free_hpt(SpaprMachineState *spapr) 1506 { 1507 g_free(spapr->htab); 1508 spapr->htab = NULL; 1509 spapr->htab_shift = 0; 1510 close_htab_fd(spapr); 1511 } 1512 1513 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 1514 Error **errp) 1515 { 1516 long rc; 1517 1518 /* Clean up any HPT info from a previous boot */ 1519 spapr_free_hpt(spapr); 1520 1521 rc = kvmppc_reset_htab(shift); 1522 if (rc < 0) { 1523 /* kernel-side HPT needed, but couldn't allocate one */ 1524 error_setg_errno(errp, errno, 1525 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1526 shift); 1527 /* This is almost certainly fatal, but if the caller really 1528 * wants to carry on with shift == 0, it's welcome to try */ 1529 } else if (rc > 0) { 1530 /* kernel-side HPT allocated */ 1531 if (rc != shift) { 1532 error_setg(errp, 1533 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1534 shift, rc); 1535 } 1536 1537 spapr->htab_shift = shift; 1538 spapr->htab = NULL; 1539 } else { 1540 /* kernel-side HPT not needed, allocate in userspace instead */ 1541 size_t size = 1ULL << shift; 1542 int i; 1543 1544 spapr->htab = qemu_memalign(size, size); 1545 if (!spapr->htab) { 1546 error_setg_errno(errp, errno, 1547 "Could not allocate HPT of order %d", shift); 1548 return; 1549 } 1550 1551 memset(spapr->htab, 0, size); 1552 spapr->htab_shift = shift; 1553 1554 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1555 DIRTY_HPTE(HPTE(spapr->htab, i)); 1556 } 1557 } 1558 /* We're setting up a hash table, so that means we're not radix */ 1559 spapr->patb_entry = 0; 1560 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1561 } 1562 1563 void spapr_setup_hpt(SpaprMachineState *spapr) 1564 { 1565 int hpt_shift; 1566 1567 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1568 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1569 } else { 1570 uint64_t current_ram_size; 1571 1572 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1573 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1574 } 1575 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1576 1577 if (kvm_enabled()) { 1578 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1579 1580 /* Check our RMA fits in the possible VRMA */ 1581 if (vrma_limit < spapr->rma_size) { 1582 error_report("Unable to create %" HWADDR_PRIu 1583 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1584 spapr->rma_size / MiB, vrma_limit / MiB); 1585 exit(EXIT_FAILURE); 1586 } 1587 } 1588 } 1589 1590 static int spapr_reset_drcs(Object *child, void *opaque) 1591 { 1592 SpaprDrc *drc = 1593 (SpaprDrc *) object_dynamic_cast(child, 1594 TYPE_SPAPR_DR_CONNECTOR); 1595 1596 if (drc) { 1597 spapr_drc_reset(drc); 1598 } 1599 1600 return 0; 1601 } 1602 1603 static void spapr_machine_reset(MachineState *machine) 1604 { 1605 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1606 PowerPCCPU *first_ppc_cpu; 1607 hwaddr fdt_addr; 1608 void *fdt; 1609 int rc; 1610 1611 kvmppc_svm_off(&error_fatal); 1612 spapr_caps_apply(spapr); 1613 1614 first_ppc_cpu = POWERPC_CPU(first_cpu); 1615 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1616 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1617 spapr->max_compat_pvr)) { 1618 /* 1619 * If using KVM with radix mode available, VCPUs can be started 1620 * without a HPT because KVM will start them in radix mode. 1621 * Set the GR bit in PATE so that we know there is no HPT. 1622 */ 1623 spapr->patb_entry = PATE1_GR; 1624 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1625 } else { 1626 spapr_setup_hpt(spapr); 1627 } 1628 1629 qemu_devices_reset(); 1630 1631 spapr_ovec_cleanup(spapr->ov5_cas); 1632 spapr->ov5_cas = spapr_ovec_new(); 1633 1634 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1635 1636 /* 1637 * This is fixing some of the default configuration of the XIVE 1638 * devices. To be called after the reset of the machine devices. 1639 */ 1640 spapr_irq_reset(spapr, &error_fatal); 1641 1642 /* 1643 * There is no CAS under qtest. Simulate one to please the code that 1644 * depends on spapr->ov5_cas. This is especially needed to test device 1645 * unplug, so we do that before resetting the DRCs. 1646 */ 1647 if (qtest_enabled()) { 1648 spapr_ovec_cleanup(spapr->ov5_cas); 1649 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1650 } 1651 1652 /* DRC reset may cause a device to be unplugged. This will cause troubles 1653 * if this device is used by another device (eg, a running vhost backend 1654 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1655 * situations, we reset DRCs after all devices have been reset. 1656 */ 1657 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1658 1659 spapr_clear_pending_events(spapr); 1660 1661 /* 1662 * We place the device tree and RTAS just below either the top of the RMA, 1663 * or just below 2GB, whichever is lower, so that it can be 1664 * processed with 32-bit real mode code if necessary 1665 */ 1666 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; 1667 1668 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1669 1670 rc = fdt_pack(fdt); 1671 1672 /* Should only fail if we've built a corrupted tree */ 1673 assert(rc == 0); 1674 1675 /* Load the fdt */ 1676 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1677 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1678 g_free(spapr->fdt_blob); 1679 spapr->fdt_size = fdt_totalsize(fdt); 1680 spapr->fdt_initial_size = spapr->fdt_size; 1681 spapr->fdt_blob = fdt; 1682 1683 /* Set up the entry state */ 1684 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0); 1685 first_ppc_cpu->env.gpr[5] = 0; 1686 1687 spapr->fwnmi_system_reset_addr = -1; 1688 spapr->fwnmi_machine_check_addr = -1; 1689 spapr->fwnmi_machine_check_interlock = -1; 1690 1691 /* Signal all vCPUs waiting on this condition */ 1692 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1693 1694 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1695 } 1696 1697 static void spapr_create_nvram(SpaprMachineState *spapr) 1698 { 1699 DeviceState *dev = qdev_new("spapr-nvram"); 1700 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1701 1702 if (dinfo) { 1703 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1704 &error_fatal); 1705 } 1706 1707 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1708 1709 spapr->nvram = (struct SpaprNvram *)dev; 1710 } 1711 1712 static void spapr_rtc_create(SpaprMachineState *spapr) 1713 { 1714 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1715 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1716 &error_fatal, NULL); 1717 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1718 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1719 "date"); 1720 } 1721 1722 /* Returns whether we want to use VGA or not */ 1723 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1724 { 1725 switch (vga_interface_type) { 1726 case VGA_NONE: 1727 return false; 1728 case VGA_DEVICE: 1729 return true; 1730 case VGA_STD: 1731 case VGA_VIRTIO: 1732 case VGA_CIRRUS: 1733 return pci_vga_init(pci_bus) != NULL; 1734 default: 1735 error_setg(errp, 1736 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1737 return false; 1738 } 1739 } 1740 1741 static int spapr_pre_load(void *opaque) 1742 { 1743 int rc; 1744 1745 rc = spapr_caps_pre_load(opaque); 1746 if (rc) { 1747 return rc; 1748 } 1749 1750 return 0; 1751 } 1752 1753 static int spapr_post_load(void *opaque, int version_id) 1754 { 1755 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1756 int err = 0; 1757 1758 err = spapr_caps_post_migration(spapr); 1759 if (err) { 1760 return err; 1761 } 1762 1763 /* 1764 * In earlier versions, there was no separate qdev for the PAPR 1765 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1766 * So when migrating from those versions, poke the incoming offset 1767 * value into the RTC device 1768 */ 1769 if (version_id < 3) { 1770 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1771 if (err) { 1772 return err; 1773 } 1774 } 1775 1776 if (kvm_enabled() && spapr->patb_entry) { 1777 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1778 bool radix = !!(spapr->patb_entry & PATE1_GR); 1779 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1780 1781 /* 1782 * Update LPCR:HR and UPRT as they may not be set properly in 1783 * the stream 1784 */ 1785 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1786 LPCR_HR | LPCR_UPRT); 1787 1788 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1789 if (err) { 1790 error_report("Process table config unsupported by the host"); 1791 return -EINVAL; 1792 } 1793 } 1794 1795 err = spapr_irq_post_load(spapr, version_id); 1796 if (err) { 1797 return err; 1798 } 1799 1800 return err; 1801 } 1802 1803 static int spapr_pre_save(void *opaque) 1804 { 1805 int rc; 1806 1807 rc = spapr_caps_pre_save(opaque); 1808 if (rc) { 1809 return rc; 1810 } 1811 1812 return 0; 1813 } 1814 1815 static bool version_before_3(void *opaque, int version_id) 1816 { 1817 return version_id < 3; 1818 } 1819 1820 static bool spapr_pending_events_needed(void *opaque) 1821 { 1822 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1823 return !QTAILQ_EMPTY(&spapr->pending_events); 1824 } 1825 1826 static const VMStateDescription vmstate_spapr_event_entry = { 1827 .name = "spapr_event_log_entry", 1828 .version_id = 1, 1829 .minimum_version_id = 1, 1830 .fields = (VMStateField[]) { 1831 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1832 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1833 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1834 NULL, extended_length), 1835 VMSTATE_END_OF_LIST() 1836 }, 1837 }; 1838 1839 static const VMStateDescription vmstate_spapr_pending_events = { 1840 .name = "spapr_pending_events", 1841 .version_id = 1, 1842 .minimum_version_id = 1, 1843 .needed = spapr_pending_events_needed, 1844 .fields = (VMStateField[]) { 1845 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1846 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1847 VMSTATE_END_OF_LIST() 1848 }, 1849 }; 1850 1851 static bool spapr_ov5_cas_needed(void *opaque) 1852 { 1853 SpaprMachineState *spapr = opaque; 1854 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1855 bool cas_needed; 1856 1857 /* Prior to the introduction of SpaprOptionVector, we had two option 1858 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1859 * Both of these options encode machine topology into the device-tree 1860 * in such a way that the now-booted OS should still be able to interact 1861 * appropriately with QEMU regardless of what options were actually 1862 * negotiatied on the source side. 1863 * 1864 * As such, we can avoid migrating the CAS-negotiated options if these 1865 * are the only options available on the current machine/platform. 1866 * Since these are the only options available for pseries-2.7 and 1867 * earlier, this allows us to maintain old->new/new->old migration 1868 * compatibility. 1869 * 1870 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1871 * via default pseries-2.8 machines and explicit command-line parameters. 1872 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1873 * of the actual CAS-negotiated values to continue working properly. For 1874 * example, availability of memory unplug depends on knowing whether 1875 * OV5_HP_EVT was negotiated via CAS. 1876 * 1877 * Thus, for any cases where the set of available CAS-negotiatable 1878 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1879 * include the CAS-negotiated options in the migration stream, unless 1880 * if they affect boot time behaviour only. 1881 */ 1882 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1883 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1884 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1885 1886 /* We need extra information if we have any bits outside the mask 1887 * defined above */ 1888 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1889 1890 spapr_ovec_cleanup(ov5_mask); 1891 1892 return cas_needed; 1893 } 1894 1895 static const VMStateDescription vmstate_spapr_ov5_cas = { 1896 .name = "spapr_option_vector_ov5_cas", 1897 .version_id = 1, 1898 .minimum_version_id = 1, 1899 .needed = spapr_ov5_cas_needed, 1900 .fields = (VMStateField[]) { 1901 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1902 vmstate_spapr_ovec, SpaprOptionVector), 1903 VMSTATE_END_OF_LIST() 1904 }, 1905 }; 1906 1907 static bool spapr_patb_entry_needed(void *opaque) 1908 { 1909 SpaprMachineState *spapr = opaque; 1910 1911 return !!spapr->patb_entry; 1912 } 1913 1914 static const VMStateDescription vmstate_spapr_patb_entry = { 1915 .name = "spapr_patb_entry", 1916 .version_id = 1, 1917 .minimum_version_id = 1, 1918 .needed = spapr_patb_entry_needed, 1919 .fields = (VMStateField[]) { 1920 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1921 VMSTATE_END_OF_LIST() 1922 }, 1923 }; 1924 1925 static bool spapr_irq_map_needed(void *opaque) 1926 { 1927 SpaprMachineState *spapr = opaque; 1928 1929 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1930 } 1931 1932 static const VMStateDescription vmstate_spapr_irq_map = { 1933 .name = "spapr_irq_map", 1934 .version_id = 1, 1935 .minimum_version_id = 1, 1936 .needed = spapr_irq_map_needed, 1937 .fields = (VMStateField[]) { 1938 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1939 VMSTATE_END_OF_LIST() 1940 }, 1941 }; 1942 1943 static bool spapr_dtb_needed(void *opaque) 1944 { 1945 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1946 1947 return smc->update_dt_enabled; 1948 } 1949 1950 static int spapr_dtb_pre_load(void *opaque) 1951 { 1952 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1953 1954 g_free(spapr->fdt_blob); 1955 spapr->fdt_blob = NULL; 1956 spapr->fdt_size = 0; 1957 1958 return 0; 1959 } 1960 1961 static const VMStateDescription vmstate_spapr_dtb = { 1962 .name = "spapr_dtb", 1963 .version_id = 1, 1964 .minimum_version_id = 1, 1965 .needed = spapr_dtb_needed, 1966 .pre_load = spapr_dtb_pre_load, 1967 .fields = (VMStateField[]) { 1968 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1969 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1970 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1971 fdt_size), 1972 VMSTATE_END_OF_LIST() 1973 }, 1974 }; 1975 1976 static bool spapr_fwnmi_needed(void *opaque) 1977 { 1978 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1979 1980 return spapr->fwnmi_machine_check_addr != -1; 1981 } 1982 1983 static int spapr_fwnmi_pre_save(void *opaque) 1984 { 1985 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1986 1987 /* 1988 * Check if machine check handling is in progress and print a 1989 * warning message. 1990 */ 1991 if (spapr->fwnmi_machine_check_interlock != -1) { 1992 warn_report("A machine check is being handled during migration. The" 1993 "handler may run and log hardware error on the destination"); 1994 } 1995 1996 return 0; 1997 } 1998 1999 static const VMStateDescription vmstate_spapr_fwnmi = { 2000 .name = "spapr_fwnmi", 2001 .version_id = 1, 2002 .minimum_version_id = 1, 2003 .needed = spapr_fwnmi_needed, 2004 .pre_save = spapr_fwnmi_pre_save, 2005 .fields = (VMStateField[]) { 2006 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 2007 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 2008 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 2009 VMSTATE_END_OF_LIST() 2010 }, 2011 }; 2012 2013 static const VMStateDescription vmstate_spapr = { 2014 .name = "spapr", 2015 .version_id = 3, 2016 .minimum_version_id = 1, 2017 .pre_load = spapr_pre_load, 2018 .post_load = spapr_post_load, 2019 .pre_save = spapr_pre_save, 2020 .fields = (VMStateField[]) { 2021 /* used to be @next_irq */ 2022 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2023 2024 /* RTC offset */ 2025 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2026 2027 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2028 VMSTATE_END_OF_LIST() 2029 }, 2030 .subsections = (const VMStateDescription*[]) { 2031 &vmstate_spapr_ov5_cas, 2032 &vmstate_spapr_patb_entry, 2033 &vmstate_spapr_pending_events, 2034 &vmstate_spapr_cap_htm, 2035 &vmstate_spapr_cap_vsx, 2036 &vmstate_spapr_cap_dfp, 2037 &vmstate_spapr_cap_cfpc, 2038 &vmstate_spapr_cap_sbbc, 2039 &vmstate_spapr_cap_ibs, 2040 &vmstate_spapr_cap_hpt_maxpagesize, 2041 &vmstate_spapr_irq_map, 2042 &vmstate_spapr_cap_nested_kvm_hv, 2043 &vmstate_spapr_dtb, 2044 &vmstate_spapr_cap_large_decr, 2045 &vmstate_spapr_cap_ccf_assist, 2046 &vmstate_spapr_cap_fwnmi, 2047 &vmstate_spapr_fwnmi, 2048 NULL 2049 } 2050 }; 2051 2052 static int htab_save_setup(QEMUFile *f, void *opaque) 2053 { 2054 SpaprMachineState *spapr = opaque; 2055 2056 /* "Iteration" header */ 2057 if (!spapr->htab_shift) { 2058 qemu_put_be32(f, -1); 2059 } else { 2060 qemu_put_be32(f, spapr->htab_shift); 2061 } 2062 2063 if (spapr->htab) { 2064 spapr->htab_save_index = 0; 2065 spapr->htab_first_pass = true; 2066 } else { 2067 if (spapr->htab_shift) { 2068 assert(kvm_enabled()); 2069 } 2070 } 2071 2072 2073 return 0; 2074 } 2075 2076 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2077 int chunkstart, int n_valid, int n_invalid) 2078 { 2079 qemu_put_be32(f, chunkstart); 2080 qemu_put_be16(f, n_valid); 2081 qemu_put_be16(f, n_invalid); 2082 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2083 HASH_PTE_SIZE_64 * n_valid); 2084 } 2085 2086 static void htab_save_end_marker(QEMUFile *f) 2087 { 2088 qemu_put_be32(f, 0); 2089 qemu_put_be16(f, 0); 2090 qemu_put_be16(f, 0); 2091 } 2092 2093 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2094 int64_t max_ns) 2095 { 2096 bool has_timeout = max_ns != -1; 2097 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2098 int index = spapr->htab_save_index; 2099 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2100 2101 assert(spapr->htab_first_pass); 2102 2103 do { 2104 int chunkstart; 2105 2106 /* Consume invalid HPTEs */ 2107 while ((index < htabslots) 2108 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2109 CLEAN_HPTE(HPTE(spapr->htab, index)); 2110 index++; 2111 } 2112 2113 /* Consume valid HPTEs */ 2114 chunkstart = index; 2115 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2116 && HPTE_VALID(HPTE(spapr->htab, index))) { 2117 CLEAN_HPTE(HPTE(spapr->htab, index)); 2118 index++; 2119 } 2120 2121 if (index > chunkstart) { 2122 int n_valid = index - chunkstart; 2123 2124 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2125 2126 if (has_timeout && 2127 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2128 break; 2129 } 2130 } 2131 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2132 2133 if (index >= htabslots) { 2134 assert(index == htabslots); 2135 index = 0; 2136 spapr->htab_first_pass = false; 2137 } 2138 spapr->htab_save_index = index; 2139 } 2140 2141 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2142 int64_t max_ns) 2143 { 2144 bool final = max_ns < 0; 2145 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2146 int examined = 0, sent = 0; 2147 int index = spapr->htab_save_index; 2148 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2149 2150 assert(!spapr->htab_first_pass); 2151 2152 do { 2153 int chunkstart, invalidstart; 2154 2155 /* Consume non-dirty HPTEs */ 2156 while ((index < htabslots) 2157 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2158 index++; 2159 examined++; 2160 } 2161 2162 chunkstart = index; 2163 /* Consume valid dirty HPTEs */ 2164 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2165 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2166 && HPTE_VALID(HPTE(spapr->htab, index))) { 2167 CLEAN_HPTE(HPTE(spapr->htab, index)); 2168 index++; 2169 examined++; 2170 } 2171 2172 invalidstart = index; 2173 /* Consume invalid dirty HPTEs */ 2174 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2175 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2176 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2177 CLEAN_HPTE(HPTE(spapr->htab, index)); 2178 index++; 2179 examined++; 2180 } 2181 2182 if (index > chunkstart) { 2183 int n_valid = invalidstart - chunkstart; 2184 int n_invalid = index - invalidstart; 2185 2186 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2187 sent += index - chunkstart; 2188 2189 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2190 break; 2191 } 2192 } 2193 2194 if (examined >= htabslots) { 2195 break; 2196 } 2197 2198 if (index >= htabslots) { 2199 assert(index == htabslots); 2200 index = 0; 2201 } 2202 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2203 2204 if (index >= htabslots) { 2205 assert(index == htabslots); 2206 index = 0; 2207 } 2208 2209 spapr->htab_save_index = index; 2210 2211 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2212 } 2213 2214 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2215 #define MAX_KVM_BUF_SIZE 2048 2216 2217 static int htab_save_iterate(QEMUFile *f, void *opaque) 2218 { 2219 SpaprMachineState *spapr = opaque; 2220 int fd; 2221 int rc = 0; 2222 2223 /* Iteration header */ 2224 if (!spapr->htab_shift) { 2225 qemu_put_be32(f, -1); 2226 return 1; 2227 } else { 2228 qemu_put_be32(f, 0); 2229 } 2230 2231 if (!spapr->htab) { 2232 assert(kvm_enabled()); 2233 2234 fd = get_htab_fd(spapr); 2235 if (fd < 0) { 2236 return fd; 2237 } 2238 2239 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2240 if (rc < 0) { 2241 return rc; 2242 } 2243 } else if (spapr->htab_first_pass) { 2244 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2245 } else { 2246 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2247 } 2248 2249 htab_save_end_marker(f); 2250 2251 return rc; 2252 } 2253 2254 static int htab_save_complete(QEMUFile *f, void *opaque) 2255 { 2256 SpaprMachineState *spapr = opaque; 2257 int fd; 2258 2259 /* Iteration header */ 2260 if (!spapr->htab_shift) { 2261 qemu_put_be32(f, -1); 2262 return 0; 2263 } else { 2264 qemu_put_be32(f, 0); 2265 } 2266 2267 if (!spapr->htab) { 2268 int rc; 2269 2270 assert(kvm_enabled()); 2271 2272 fd = get_htab_fd(spapr); 2273 if (fd < 0) { 2274 return fd; 2275 } 2276 2277 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2278 if (rc < 0) { 2279 return rc; 2280 } 2281 } else { 2282 if (spapr->htab_first_pass) { 2283 htab_save_first_pass(f, spapr, -1); 2284 } 2285 htab_save_later_pass(f, spapr, -1); 2286 } 2287 2288 /* End marker */ 2289 htab_save_end_marker(f); 2290 2291 return 0; 2292 } 2293 2294 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2295 { 2296 SpaprMachineState *spapr = opaque; 2297 uint32_t section_hdr; 2298 int fd = -1; 2299 Error *local_err = NULL; 2300 2301 if (version_id < 1 || version_id > 1) { 2302 error_report("htab_load() bad version"); 2303 return -EINVAL; 2304 } 2305 2306 section_hdr = qemu_get_be32(f); 2307 2308 if (section_hdr == -1) { 2309 spapr_free_hpt(spapr); 2310 return 0; 2311 } 2312 2313 if (section_hdr) { 2314 /* First section gives the htab size */ 2315 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2316 if (local_err) { 2317 error_report_err(local_err); 2318 return -EINVAL; 2319 } 2320 return 0; 2321 } 2322 2323 if (!spapr->htab) { 2324 assert(kvm_enabled()); 2325 2326 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2327 if (fd < 0) { 2328 error_report_err(local_err); 2329 return fd; 2330 } 2331 } 2332 2333 while (true) { 2334 uint32_t index; 2335 uint16_t n_valid, n_invalid; 2336 2337 index = qemu_get_be32(f); 2338 n_valid = qemu_get_be16(f); 2339 n_invalid = qemu_get_be16(f); 2340 2341 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2342 /* End of Stream */ 2343 break; 2344 } 2345 2346 if ((index + n_valid + n_invalid) > 2347 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2348 /* Bad index in stream */ 2349 error_report( 2350 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2351 index, n_valid, n_invalid, spapr->htab_shift); 2352 return -EINVAL; 2353 } 2354 2355 if (spapr->htab) { 2356 if (n_valid) { 2357 qemu_get_buffer(f, HPTE(spapr->htab, index), 2358 HASH_PTE_SIZE_64 * n_valid); 2359 } 2360 if (n_invalid) { 2361 memset(HPTE(spapr->htab, index + n_valid), 0, 2362 HASH_PTE_SIZE_64 * n_invalid); 2363 } 2364 } else { 2365 int rc; 2366 2367 assert(fd >= 0); 2368 2369 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2370 if (rc < 0) { 2371 return rc; 2372 } 2373 } 2374 } 2375 2376 if (!spapr->htab) { 2377 assert(fd >= 0); 2378 close(fd); 2379 } 2380 2381 return 0; 2382 } 2383 2384 static void htab_save_cleanup(void *opaque) 2385 { 2386 SpaprMachineState *spapr = opaque; 2387 2388 close_htab_fd(spapr); 2389 } 2390 2391 static SaveVMHandlers savevm_htab_handlers = { 2392 .save_setup = htab_save_setup, 2393 .save_live_iterate = htab_save_iterate, 2394 .save_live_complete_precopy = htab_save_complete, 2395 .save_cleanup = htab_save_cleanup, 2396 .load_state = htab_load, 2397 }; 2398 2399 static void spapr_boot_set(void *opaque, const char *boot_device, 2400 Error **errp) 2401 { 2402 MachineState *machine = MACHINE(opaque); 2403 machine->boot_order = g_strdup(boot_device); 2404 } 2405 2406 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2407 { 2408 MachineState *machine = MACHINE(spapr); 2409 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2410 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2411 int i; 2412 2413 for (i = 0; i < nr_lmbs; i++) { 2414 uint64_t addr; 2415 2416 addr = i * lmb_size + machine->device_memory->base; 2417 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2418 addr / lmb_size); 2419 } 2420 } 2421 2422 /* 2423 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2424 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2425 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2426 */ 2427 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2428 { 2429 int i; 2430 2431 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2432 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2433 " is not aligned to %" PRIu64 " MiB", 2434 machine->ram_size, 2435 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2436 return; 2437 } 2438 2439 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2440 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2441 " is not aligned to %" PRIu64 " MiB", 2442 machine->ram_size, 2443 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2444 return; 2445 } 2446 2447 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2448 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2449 error_setg(errp, 2450 "Node %d memory size 0x%" PRIx64 2451 " is not aligned to %" PRIu64 " MiB", 2452 i, machine->numa_state->nodes[i].node_mem, 2453 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2454 return; 2455 } 2456 } 2457 } 2458 2459 /* find cpu slot in machine->possible_cpus by core_id */ 2460 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2461 { 2462 int index = id / ms->smp.threads; 2463 2464 if (index >= ms->possible_cpus->len) { 2465 return NULL; 2466 } 2467 if (idx) { 2468 *idx = index; 2469 } 2470 return &ms->possible_cpus->cpus[index]; 2471 } 2472 2473 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2474 { 2475 MachineState *ms = MACHINE(spapr); 2476 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2477 Error *local_err = NULL; 2478 bool vsmt_user = !!spapr->vsmt; 2479 int kvm_smt = kvmppc_smt_threads(); 2480 int ret; 2481 unsigned int smp_threads = ms->smp.threads; 2482 2483 if (!kvm_enabled() && (smp_threads > 1)) { 2484 error_setg(errp, "TCG cannot support more than 1 thread/core " 2485 "on a pseries machine"); 2486 return; 2487 } 2488 if (!is_power_of_2(smp_threads)) { 2489 error_setg(errp, "Cannot support %d threads/core on a pseries " 2490 "machine because it must be a power of 2", smp_threads); 2491 return; 2492 } 2493 2494 /* Detemine the VSMT mode to use: */ 2495 if (vsmt_user) { 2496 if (spapr->vsmt < smp_threads) { 2497 error_setg(errp, "Cannot support VSMT mode %d" 2498 " because it must be >= threads/core (%d)", 2499 spapr->vsmt, smp_threads); 2500 return; 2501 } 2502 /* In this case, spapr->vsmt has been set by the command line */ 2503 } else if (!smc->smp_threads_vsmt) { 2504 /* 2505 * Default VSMT value is tricky, because we need it to be as 2506 * consistent as possible (for migration), but this requires 2507 * changing it for at least some existing cases. We pick 8 as 2508 * the value that we'd get with KVM on POWER8, the 2509 * overwhelmingly common case in production systems. 2510 */ 2511 spapr->vsmt = MAX(8, smp_threads); 2512 } else { 2513 spapr->vsmt = smp_threads; 2514 } 2515 2516 /* KVM: If necessary, set the SMT mode: */ 2517 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2518 ret = kvmppc_set_smt_threads(spapr->vsmt); 2519 if (ret) { 2520 /* Looks like KVM isn't able to change VSMT mode */ 2521 error_setg(&local_err, 2522 "Failed to set KVM's VSMT mode to %d (errno %d)", 2523 spapr->vsmt, ret); 2524 /* We can live with that if the default one is big enough 2525 * for the number of threads, and a submultiple of the one 2526 * we want. In this case we'll waste some vcpu ids, but 2527 * behaviour will be correct */ 2528 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2529 warn_report_err(local_err); 2530 } else { 2531 if (!vsmt_user) { 2532 error_append_hint(&local_err, 2533 "On PPC, a VM with %d threads/core" 2534 " on a host with %d threads/core" 2535 " requires the use of VSMT mode %d.\n", 2536 smp_threads, kvm_smt, spapr->vsmt); 2537 } 2538 kvmppc_error_append_smt_possible_hint(&local_err); 2539 error_propagate(errp, local_err); 2540 } 2541 } 2542 } 2543 /* else TCG: nothing to do currently */ 2544 } 2545 2546 static void spapr_init_cpus(SpaprMachineState *spapr) 2547 { 2548 MachineState *machine = MACHINE(spapr); 2549 MachineClass *mc = MACHINE_GET_CLASS(machine); 2550 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2551 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2552 const CPUArchIdList *possible_cpus; 2553 unsigned int smp_cpus = machine->smp.cpus; 2554 unsigned int smp_threads = machine->smp.threads; 2555 unsigned int max_cpus = machine->smp.max_cpus; 2556 int boot_cores_nr = smp_cpus / smp_threads; 2557 int i; 2558 2559 possible_cpus = mc->possible_cpu_arch_ids(machine); 2560 if (mc->has_hotpluggable_cpus) { 2561 if (smp_cpus % smp_threads) { 2562 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2563 smp_cpus, smp_threads); 2564 exit(1); 2565 } 2566 if (max_cpus % smp_threads) { 2567 error_report("max_cpus (%u) must be multiple of threads (%u)", 2568 max_cpus, smp_threads); 2569 exit(1); 2570 } 2571 } else { 2572 if (max_cpus != smp_cpus) { 2573 error_report("This machine version does not support CPU hotplug"); 2574 exit(1); 2575 } 2576 boot_cores_nr = possible_cpus->len; 2577 } 2578 2579 if (smc->pre_2_10_has_unused_icps) { 2580 int i; 2581 2582 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2583 /* Dummy entries get deregistered when real ICPState objects 2584 * are registered during CPU core hotplug. 2585 */ 2586 pre_2_10_vmstate_register_dummy_icp(i); 2587 } 2588 } 2589 2590 for (i = 0; i < possible_cpus->len; i++) { 2591 int core_id = i * smp_threads; 2592 2593 if (mc->has_hotpluggable_cpus) { 2594 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2595 spapr_vcpu_id(spapr, core_id)); 2596 } 2597 2598 if (i < boot_cores_nr) { 2599 Object *core = object_new(type); 2600 int nr_threads = smp_threads; 2601 2602 /* Handle the partially filled core for older machine types */ 2603 if ((i + 1) * smp_threads >= smp_cpus) { 2604 nr_threads = smp_cpus - i * smp_threads; 2605 } 2606 2607 object_property_set_int(core, "nr-threads", nr_threads, 2608 &error_fatal); 2609 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2610 &error_fatal); 2611 qdev_realize(DEVICE(core), NULL, &error_fatal); 2612 2613 object_unref(core); 2614 } 2615 } 2616 } 2617 2618 static PCIHostState *spapr_create_default_phb(void) 2619 { 2620 DeviceState *dev; 2621 2622 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2623 qdev_prop_set_uint32(dev, "index", 0); 2624 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2625 2626 return PCI_HOST_BRIDGE(dev); 2627 } 2628 2629 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2630 { 2631 MachineState *machine = MACHINE(spapr); 2632 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2633 hwaddr rma_size = machine->ram_size; 2634 hwaddr node0_size = spapr_node0_size(machine); 2635 2636 /* RMA has to fit in the first NUMA node */ 2637 rma_size = MIN(rma_size, node0_size); 2638 2639 /* 2640 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2641 * never exceed that 2642 */ 2643 rma_size = MIN(rma_size, 1 * TiB); 2644 2645 /* 2646 * Clamp the RMA size based on machine type. This is for 2647 * migration compatibility with older qemu versions, which limited 2648 * the RMA size for complicated and mostly bad reasons. 2649 */ 2650 if (smc->rma_limit) { 2651 rma_size = MIN(rma_size, smc->rma_limit); 2652 } 2653 2654 if (rma_size < MIN_RMA_SLOF) { 2655 error_setg(errp, 2656 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2657 "ldMiB guest RMA (Real Mode Area memory)", 2658 MIN_RMA_SLOF / MiB); 2659 return 0; 2660 } 2661 2662 return rma_size; 2663 } 2664 2665 /* pSeries LPAR / sPAPR hardware init */ 2666 static void spapr_machine_init(MachineState *machine) 2667 { 2668 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2669 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2670 MachineClass *mc = MACHINE_GET_CLASS(machine); 2671 const char *kernel_filename = machine->kernel_filename; 2672 const char *initrd_filename = machine->initrd_filename; 2673 PCIHostState *phb; 2674 int i; 2675 MemoryRegion *sysmem = get_system_memory(); 2676 long load_limit, fw_size; 2677 char *filename; 2678 Error *resize_hpt_err = NULL; 2679 2680 msi_nonbroken = true; 2681 2682 QLIST_INIT(&spapr->phbs); 2683 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2684 2685 /* Determine capabilities to run with */ 2686 spapr_caps_init(spapr); 2687 2688 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2689 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2690 /* 2691 * If the user explicitly requested a mode we should either 2692 * supply it, or fail completely (which we do below). But if 2693 * it's not set explicitly, we reset our mode to something 2694 * that works 2695 */ 2696 if (resize_hpt_err) { 2697 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2698 error_free(resize_hpt_err); 2699 resize_hpt_err = NULL; 2700 } else { 2701 spapr->resize_hpt = smc->resize_hpt_default; 2702 } 2703 } 2704 2705 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2706 2707 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2708 /* 2709 * User requested HPT resize, but this host can't supply it. Bail out 2710 */ 2711 error_report_err(resize_hpt_err); 2712 exit(1); 2713 } 2714 error_free(resize_hpt_err); 2715 2716 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2717 2718 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2719 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2720 2721 /* 2722 * VSMT must be set in order to be able to compute VCPU ids, ie to 2723 * call spapr_max_server_number() or spapr_vcpu_id(). 2724 */ 2725 spapr_set_vsmt_mode(spapr, &error_fatal); 2726 2727 /* Set up Interrupt Controller before we create the VCPUs */ 2728 spapr_irq_init(spapr, &error_fatal); 2729 2730 /* Set up containers for ibm,client-architecture-support negotiated options 2731 */ 2732 spapr->ov5 = spapr_ovec_new(); 2733 spapr->ov5_cas = spapr_ovec_new(); 2734 2735 if (smc->dr_lmb_enabled) { 2736 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2737 spapr_validate_node_memory(machine, &error_fatal); 2738 } 2739 2740 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2741 2742 /* advertise support for dedicated HP event source to guests */ 2743 if (spapr->use_hotplug_event_source) { 2744 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2745 } 2746 2747 /* advertise support for HPT resizing */ 2748 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2749 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2750 } 2751 2752 /* advertise support for ibm,dyamic-memory-v2 */ 2753 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2754 2755 /* advertise XIVE on POWER9 machines */ 2756 if (spapr->irq->xive) { 2757 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2758 } 2759 2760 /* init CPUs */ 2761 spapr_init_cpus(spapr); 2762 2763 /* 2764 * check we don't have a memory-less/cpu-less NUMA node 2765 * Firmware relies on the existing memory/cpu topology to provide the 2766 * NUMA topology to the kernel. 2767 * And the linux kernel needs to know the NUMA topology at start 2768 * to be able to hotplug CPUs later. 2769 */ 2770 if (machine->numa_state->num_nodes) { 2771 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2772 /* check for memory-less node */ 2773 if (machine->numa_state->nodes[i].node_mem == 0) { 2774 CPUState *cs; 2775 int found = 0; 2776 /* check for cpu-less node */ 2777 CPU_FOREACH(cs) { 2778 PowerPCCPU *cpu = POWERPC_CPU(cs); 2779 if (cpu->node_id == i) { 2780 found = 1; 2781 break; 2782 } 2783 } 2784 /* memory-less and cpu-less node */ 2785 if (!found) { 2786 error_report( 2787 "Memory-less/cpu-less nodes are not supported (node %d)", 2788 i); 2789 exit(1); 2790 } 2791 } 2792 } 2793 2794 } 2795 2796 /* 2797 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. 2798 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is 2799 * called from vPHB reset handler so we initialize the counter here. 2800 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM 2801 * must be equally distant from any other node. 2802 * The final value of spapr->gpu_numa_id is going to be written to 2803 * max-associativity-domains in spapr_build_fdt(). 2804 */ 2805 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes); 2806 2807 /* Init numa_assoc_array */ 2808 spapr_numa_associativity_init(spapr, machine); 2809 2810 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2811 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2812 spapr->max_compat_pvr)) { 2813 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2814 /* KVM and TCG always allow GTSE with radix... */ 2815 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2816 } 2817 /* ... but not with hash (currently). */ 2818 2819 if (kvm_enabled()) { 2820 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2821 kvmppc_enable_logical_ci_hcalls(); 2822 kvmppc_enable_set_mode_hcall(); 2823 2824 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2825 kvmppc_enable_clear_ref_mod_hcalls(); 2826 2827 /* Enable H_PAGE_INIT */ 2828 kvmppc_enable_h_page_init(); 2829 } 2830 2831 /* map RAM */ 2832 memory_region_add_subregion(sysmem, 0, machine->ram); 2833 2834 /* always allocate the device memory information */ 2835 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2836 2837 /* initialize hotplug memory address space */ 2838 if (machine->ram_size < machine->maxram_size) { 2839 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2840 /* 2841 * Limit the number of hotpluggable memory slots to half the number 2842 * slots that KVM supports, leaving the other half for PCI and other 2843 * devices. However ensure that number of slots doesn't drop below 32. 2844 */ 2845 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2846 SPAPR_MAX_RAM_SLOTS; 2847 2848 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2849 max_memslots = SPAPR_MAX_RAM_SLOTS; 2850 } 2851 if (machine->ram_slots > max_memslots) { 2852 error_report("Specified number of memory slots %" 2853 PRIu64" exceeds max supported %d", 2854 machine->ram_slots, max_memslots); 2855 exit(1); 2856 } 2857 2858 machine->device_memory->base = ROUND_UP(machine->ram_size, 2859 SPAPR_DEVICE_MEM_ALIGN); 2860 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2861 "device-memory", device_mem_size); 2862 memory_region_add_subregion(sysmem, machine->device_memory->base, 2863 &machine->device_memory->mr); 2864 } 2865 2866 if (smc->dr_lmb_enabled) { 2867 spapr_create_lmb_dr_connectors(spapr); 2868 } 2869 2870 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { 2871 /* Create the error string for live migration blocker */ 2872 error_setg(&spapr->fwnmi_migration_blocker, 2873 "A machine check is being handled during migration. The handler" 2874 "may run and log hardware error on the destination"); 2875 } 2876 2877 if (mc->nvdimm_supported) { 2878 spapr_create_nvdimm_dr_connectors(spapr); 2879 } 2880 2881 /* Set up RTAS event infrastructure */ 2882 spapr_events_init(spapr); 2883 2884 /* Set up the RTC RTAS interfaces */ 2885 spapr_rtc_create(spapr); 2886 2887 /* Set up VIO bus */ 2888 spapr->vio_bus = spapr_vio_bus_init(); 2889 2890 for (i = 0; i < serial_max_hds(); i++) { 2891 if (serial_hd(i)) { 2892 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2893 } 2894 } 2895 2896 /* We always have at least the nvram device on VIO */ 2897 spapr_create_nvram(spapr); 2898 2899 /* 2900 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2901 * connectors (described in root DT node's "ibm,drc-types" property) 2902 * are pre-initialized here. additional child connectors (such as 2903 * connectors for a PHBs PCI slots) are added as needed during their 2904 * parent's realization. 2905 */ 2906 if (smc->dr_phb_enabled) { 2907 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2908 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2909 } 2910 } 2911 2912 /* Set up PCI */ 2913 spapr_pci_rtas_init(); 2914 2915 phb = spapr_create_default_phb(); 2916 2917 for (i = 0; i < nb_nics; i++) { 2918 NICInfo *nd = &nd_table[i]; 2919 2920 if (!nd->model) { 2921 nd->model = g_strdup("spapr-vlan"); 2922 } 2923 2924 if (g_str_equal(nd->model, "spapr-vlan") || 2925 g_str_equal(nd->model, "ibmveth")) { 2926 spapr_vlan_create(spapr->vio_bus, nd); 2927 } else { 2928 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2929 } 2930 } 2931 2932 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2933 spapr_vscsi_create(spapr->vio_bus); 2934 } 2935 2936 /* Graphics */ 2937 if (spapr_vga_init(phb->bus, &error_fatal)) { 2938 spapr->has_graphics = true; 2939 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2940 } 2941 2942 if (machine->usb) { 2943 if (smc->use_ohci_by_default) { 2944 pci_create_simple(phb->bus, -1, "pci-ohci"); 2945 } else { 2946 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2947 } 2948 2949 if (spapr->has_graphics) { 2950 USBBus *usb_bus = usb_bus_find(-1); 2951 2952 usb_create_simple(usb_bus, "usb-kbd"); 2953 usb_create_simple(usb_bus, "usb-mouse"); 2954 } 2955 } 2956 2957 if (kernel_filename) { 2958 uint64_t lowaddr = 0; 2959 2960 spapr->kernel_size = load_elf(kernel_filename, NULL, 2961 translate_kernel_address, spapr, 2962 NULL, &lowaddr, NULL, NULL, 1, 2963 PPC_ELF_MACHINE, 0, 0); 2964 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2965 spapr->kernel_size = load_elf(kernel_filename, NULL, 2966 translate_kernel_address, spapr, NULL, 2967 &lowaddr, NULL, NULL, 0, 2968 PPC_ELF_MACHINE, 2969 0, 0); 2970 spapr->kernel_le = spapr->kernel_size > 0; 2971 } 2972 if (spapr->kernel_size < 0) { 2973 error_report("error loading %s: %s", kernel_filename, 2974 load_elf_strerror(spapr->kernel_size)); 2975 exit(1); 2976 } 2977 2978 /* load initrd */ 2979 if (initrd_filename) { 2980 /* Try to locate the initrd in the gap between the kernel 2981 * and the firmware. Add a bit of space just in case 2982 */ 2983 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 2984 + 0x1ffff) & ~0xffff; 2985 spapr->initrd_size = load_image_targphys(initrd_filename, 2986 spapr->initrd_base, 2987 load_limit 2988 - spapr->initrd_base); 2989 if (spapr->initrd_size < 0) { 2990 error_report("could not load initial ram disk '%s'", 2991 initrd_filename); 2992 exit(1); 2993 } 2994 } 2995 } 2996 2997 if (bios_name == NULL) { 2998 bios_name = FW_FILE_NAME; 2999 } 3000 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 3001 if (!filename) { 3002 error_report("Could not find LPAR firmware '%s'", bios_name); 3003 exit(1); 3004 } 3005 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 3006 if (fw_size <= 0) { 3007 error_report("Could not load LPAR firmware '%s'", filename); 3008 exit(1); 3009 } 3010 g_free(filename); 3011 3012 /* FIXME: Should register things through the MachineState's qdev 3013 * interface, this is a legacy from the sPAPREnvironment structure 3014 * which predated MachineState but had a similar function */ 3015 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3016 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3017 &savevm_htab_handlers, spapr); 3018 3019 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 3020 3021 qemu_register_boot_set(spapr_boot_set, spapr); 3022 3023 /* 3024 * Nothing needs to be done to resume a suspended guest because 3025 * suspending does not change the machine state, so no need for 3026 * a ->wakeup method. 3027 */ 3028 qemu_register_wakeup_support(); 3029 3030 if (kvm_enabled()) { 3031 /* to stop and start vmclock */ 3032 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3033 &spapr->tb); 3034 3035 kvmppc_spapr_enable_inkernel_multitce(); 3036 } 3037 3038 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3039 } 3040 3041 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3042 { 3043 if (!vm_type) { 3044 return 0; 3045 } 3046 3047 if (!strcmp(vm_type, "HV")) { 3048 return 1; 3049 } 3050 3051 if (!strcmp(vm_type, "PR")) { 3052 return 2; 3053 } 3054 3055 error_report("Unknown kvm-type specified '%s'", vm_type); 3056 exit(1); 3057 } 3058 3059 /* 3060 * Implementation of an interface to adjust firmware path 3061 * for the bootindex property handling. 3062 */ 3063 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3064 DeviceState *dev) 3065 { 3066 #define CAST(type, obj, name) \ 3067 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3068 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3069 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3070 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3071 3072 if (d) { 3073 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3074 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3075 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3076 3077 if (spapr) { 3078 /* 3079 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3080 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3081 * 0x8000 | (target << 8) | (bus << 5) | lun 3082 * (see the "Logical unit addressing format" table in SAM5) 3083 */ 3084 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3085 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3086 (uint64_t)id << 48); 3087 } else if (virtio) { 3088 /* 3089 * We use SRP luns of the form 01000000 | (target << 8) | lun 3090 * in the top 32 bits of the 64-bit LUN 3091 * Note: the quote above is from SLOF and it is wrong, 3092 * the actual binding is: 3093 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3094 */ 3095 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3096 if (d->lun >= 256) { 3097 /* Use the LUN "flat space addressing method" */ 3098 id |= 0x4000; 3099 } 3100 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3101 (uint64_t)id << 32); 3102 } else if (usb) { 3103 /* 3104 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3105 * in the top 32 bits of the 64-bit LUN 3106 */ 3107 unsigned usb_port = atoi(usb->port->path); 3108 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3109 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3110 (uint64_t)id << 32); 3111 } 3112 } 3113 3114 /* 3115 * SLOF probes the USB devices, and if it recognizes that the device is a 3116 * storage device, it changes its name to "storage" instead of "usb-host", 3117 * and additionally adds a child node for the SCSI LUN, so the correct 3118 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3119 */ 3120 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3121 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3122 if (usb_host_dev_is_scsi_storage(usbdev)) { 3123 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3124 } 3125 } 3126 3127 if (phb) { 3128 /* Replace "pci" with "pci@800000020000000" */ 3129 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3130 } 3131 3132 if (vsc) { 3133 /* Same logic as virtio above */ 3134 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3135 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3136 } 3137 3138 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3139 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3140 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3141 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3142 } 3143 3144 return NULL; 3145 } 3146 3147 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3148 { 3149 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3150 3151 return g_strdup(spapr->kvm_type); 3152 } 3153 3154 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3155 { 3156 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3157 3158 g_free(spapr->kvm_type); 3159 spapr->kvm_type = g_strdup(value); 3160 } 3161 3162 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3163 { 3164 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3165 3166 return spapr->use_hotplug_event_source; 3167 } 3168 3169 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3170 Error **errp) 3171 { 3172 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3173 3174 spapr->use_hotplug_event_source = value; 3175 } 3176 3177 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3178 { 3179 return true; 3180 } 3181 3182 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3183 { 3184 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3185 3186 switch (spapr->resize_hpt) { 3187 case SPAPR_RESIZE_HPT_DEFAULT: 3188 return g_strdup("default"); 3189 case SPAPR_RESIZE_HPT_DISABLED: 3190 return g_strdup("disabled"); 3191 case SPAPR_RESIZE_HPT_ENABLED: 3192 return g_strdup("enabled"); 3193 case SPAPR_RESIZE_HPT_REQUIRED: 3194 return g_strdup("required"); 3195 } 3196 g_assert_not_reached(); 3197 } 3198 3199 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3200 { 3201 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3202 3203 if (strcmp(value, "default") == 0) { 3204 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3205 } else if (strcmp(value, "disabled") == 0) { 3206 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3207 } else if (strcmp(value, "enabled") == 0) { 3208 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3209 } else if (strcmp(value, "required") == 0) { 3210 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3211 } else { 3212 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3213 } 3214 } 3215 3216 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3217 { 3218 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3219 3220 if (spapr->irq == &spapr_irq_xics_legacy) { 3221 return g_strdup("legacy"); 3222 } else if (spapr->irq == &spapr_irq_xics) { 3223 return g_strdup("xics"); 3224 } else if (spapr->irq == &spapr_irq_xive) { 3225 return g_strdup("xive"); 3226 } else if (spapr->irq == &spapr_irq_dual) { 3227 return g_strdup("dual"); 3228 } 3229 g_assert_not_reached(); 3230 } 3231 3232 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3233 { 3234 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3235 3236 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3237 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3238 return; 3239 } 3240 3241 /* The legacy IRQ backend can not be set */ 3242 if (strcmp(value, "xics") == 0) { 3243 spapr->irq = &spapr_irq_xics; 3244 } else if (strcmp(value, "xive") == 0) { 3245 spapr->irq = &spapr_irq_xive; 3246 } else if (strcmp(value, "dual") == 0) { 3247 spapr->irq = &spapr_irq_dual; 3248 } else { 3249 error_setg(errp, "Bad value for \"ic-mode\" property"); 3250 } 3251 } 3252 3253 static char *spapr_get_host_model(Object *obj, Error **errp) 3254 { 3255 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3256 3257 return g_strdup(spapr->host_model); 3258 } 3259 3260 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3261 { 3262 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3263 3264 g_free(spapr->host_model); 3265 spapr->host_model = g_strdup(value); 3266 } 3267 3268 static char *spapr_get_host_serial(Object *obj, Error **errp) 3269 { 3270 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3271 3272 return g_strdup(spapr->host_serial); 3273 } 3274 3275 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3276 { 3277 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3278 3279 g_free(spapr->host_serial); 3280 spapr->host_serial = g_strdup(value); 3281 } 3282 3283 static void spapr_instance_init(Object *obj) 3284 { 3285 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3286 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3287 3288 spapr->htab_fd = -1; 3289 spapr->use_hotplug_event_source = true; 3290 object_property_add_str(obj, "kvm-type", 3291 spapr_get_kvm_type, spapr_set_kvm_type); 3292 object_property_set_description(obj, "kvm-type", 3293 "Specifies the KVM virtualization mode (HV, PR)"); 3294 object_property_add_bool(obj, "modern-hotplug-events", 3295 spapr_get_modern_hotplug_events, 3296 spapr_set_modern_hotplug_events); 3297 object_property_set_description(obj, "modern-hotplug-events", 3298 "Use dedicated hotplug event mechanism in" 3299 " place of standard EPOW events when possible" 3300 " (required for memory hot-unplug support)"); 3301 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3302 "Maximum permitted CPU compatibility mode"); 3303 3304 object_property_add_str(obj, "resize-hpt", 3305 spapr_get_resize_hpt, spapr_set_resize_hpt); 3306 object_property_set_description(obj, "resize-hpt", 3307 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3308 object_property_add_uint32_ptr(obj, "vsmt", 3309 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3310 object_property_set_description(obj, "vsmt", 3311 "Virtual SMT: KVM behaves as if this were" 3312 " the host's SMT mode"); 3313 3314 object_property_add_bool(obj, "vfio-no-msix-emulation", 3315 spapr_get_msix_emulation, NULL); 3316 3317 object_property_add_uint64_ptr(obj, "kernel-addr", 3318 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3319 object_property_set_description(obj, "kernel-addr", 3320 stringify(KERNEL_LOAD_ADDR) 3321 " for -kernel is the default"); 3322 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3323 /* The machine class defines the default interrupt controller mode */ 3324 spapr->irq = smc->irq; 3325 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3326 spapr_set_ic_mode); 3327 object_property_set_description(obj, "ic-mode", 3328 "Specifies the interrupt controller mode (xics, xive, dual)"); 3329 3330 object_property_add_str(obj, "host-model", 3331 spapr_get_host_model, spapr_set_host_model); 3332 object_property_set_description(obj, "host-model", 3333 "Host model to advertise in guest device tree"); 3334 object_property_add_str(obj, "host-serial", 3335 spapr_get_host_serial, spapr_set_host_serial); 3336 object_property_set_description(obj, "host-serial", 3337 "Host serial number to advertise in guest device tree"); 3338 } 3339 3340 static void spapr_machine_finalizefn(Object *obj) 3341 { 3342 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3343 3344 g_free(spapr->kvm_type); 3345 } 3346 3347 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3348 { 3349 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3350 PowerPCCPU *cpu = POWERPC_CPU(cs); 3351 CPUPPCState *env = &cpu->env; 3352 3353 cpu_synchronize_state(cs); 3354 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3355 if (spapr->fwnmi_system_reset_addr != -1) { 3356 uint64_t rtas_addr, addr; 3357 3358 /* get rtas addr from fdt */ 3359 rtas_addr = spapr_get_rtas_addr(); 3360 if (!rtas_addr) { 3361 qemu_system_guest_panicked(NULL); 3362 return; 3363 } 3364 3365 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3366 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3367 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3368 env->gpr[3] = addr; 3369 } 3370 ppc_cpu_do_system_reset(cs); 3371 if (spapr->fwnmi_system_reset_addr != -1) { 3372 env->nip = spapr->fwnmi_system_reset_addr; 3373 } 3374 } 3375 3376 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3377 { 3378 CPUState *cs; 3379 3380 CPU_FOREACH(cs) { 3381 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3382 } 3383 } 3384 3385 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3386 void *fdt, int *fdt_start_offset, Error **errp) 3387 { 3388 uint64_t addr; 3389 uint32_t node; 3390 3391 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3392 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3393 &error_abort); 3394 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3395 SPAPR_MEMORY_BLOCK_SIZE); 3396 return 0; 3397 } 3398 3399 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3400 bool dedicated_hp_event_source, Error **errp) 3401 { 3402 SpaprDrc *drc; 3403 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3404 int i; 3405 uint64_t addr = addr_start; 3406 bool hotplugged = spapr_drc_hotplugged(dev); 3407 Error *local_err = NULL; 3408 3409 for (i = 0; i < nr_lmbs; i++) { 3410 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3411 addr / SPAPR_MEMORY_BLOCK_SIZE); 3412 g_assert(drc); 3413 3414 spapr_drc_attach(drc, dev, &local_err); 3415 if (local_err) { 3416 while (addr > addr_start) { 3417 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3418 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3419 addr / SPAPR_MEMORY_BLOCK_SIZE); 3420 spapr_drc_detach(drc); 3421 } 3422 error_propagate(errp, local_err); 3423 return; 3424 } 3425 if (!hotplugged) { 3426 spapr_drc_reset(drc); 3427 } 3428 addr += SPAPR_MEMORY_BLOCK_SIZE; 3429 } 3430 /* send hotplug notification to the 3431 * guest only in case of hotplugged memory 3432 */ 3433 if (hotplugged) { 3434 if (dedicated_hp_event_source) { 3435 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3436 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3437 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3438 nr_lmbs, 3439 spapr_drc_index(drc)); 3440 } else { 3441 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3442 nr_lmbs); 3443 } 3444 } 3445 } 3446 3447 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3448 Error **errp) 3449 { 3450 Error *local_err = NULL; 3451 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3452 PCDIMMDevice *dimm = PC_DIMM(dev); 3453 uint64_t size, addr, slot; 3454 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3455 3456 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3457 3458 pc_dimm_plug(dimm, MACHINE(ms), &local_err); 3459 if (local_err) { 3460 goto out; 3461 } 3462 3463 if (!is_nvdimm) { 3464 addr = object_property_get_uint(OBJECT(dimm), 3465 PC_DIMM_ADDR_PROP, &local_err); 3466 if (local_err) { 3467 goto out_unplug; 3468 } 3469 spapr_add_lmbs(dev, addr, size, 3470 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3471 &local_err); 3472 } else { 3473 slot = object_property_get_uint(OBJECT(dimm), 3474 PC_DIMM_SLOT_PROP, &local_err); 3475 if (local_err) { 3476 goto out_unplug; 3477 } 3478 spapr_add_nvdimm(dev, slot, &local_err); 3479 } 3480 3481 if (local_err) { 3482 goto out_unplug; 3483 } 3484 3485 return; 3486 3487 out_unplug: 3488 pc_dimm_unplug(dimm, MACHINE(ms)); 3489 out: 3490 error_propagate(errp, local_err); 3491 } 3492 3493 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3494 Error **errp) 3495 { 3496 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3497 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3498 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3499 PCDIMMDevice *dimm = PC_DIMM(dev); 3500 Error *local_err = NULL; 3501 uint64_t size; 3502 Object *memdev; 3503 hwaddr pagesize; 3504 3505 if (!smc->dr_lmb_enabled) { 3506 error_setg(errp, "Memory hotplug not supported for this machine"); 3507 return; 3508 } 3509 3510 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3511 if (local_err) { 3512 error_propagate(errp, local_err); 3513 return; 3514 } 3515 3516 if (is_nvdimm) { 3517 spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, &local_err); 3518 if (local_err) { 3519 error_propagate(errp, local_err); 3520 return; 3521 } 3522 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3523 error_setg(errp, "Hotplugged memory size must be a multiple of " 3524 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3525 return; 3526 } 3527 3528 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3529 &error_abort); 3530 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3531 spapr_check_pagesize(spapr, pagesize, &local_err); 3532 if (local_err) { 3533 error_propagate(errp, local_err); 3534 return; 3535 } 3536 3537 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3538 } 3539 3540 struct SpaprDimmState { 3541 PCDIMMDevice *dimm; 3542 uint32_t nr_lmbs; 3543 QTAILQ_ENTRY(SpaprDimmState) next; 3544 }; 3545 3546 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3547 PCDIMMDevice *dimm) 3548 { 3549 SpaprDimmState *dimm_state = NULL; 3550 3551 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3552 if (dimm_state->dimm == dimm) { 3553 break; 3554 } 3555 } 3556 return dimm_state; 3557 } 3558 3559 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3560 uint32_t nr_lmbs, 3561 PCDIMMDevice *dimm) 3562 { 3563 SpaprDimmState *ds = NULL; 3564 3565 /* 3566 * If this request is for a DIMM whose removal had failed earlier 3567 * (due to guest's refusal to remove the LMBs), we would have this 3568 * dimm already in the pending_dimm_unplugs list. In that 3569 * case don't add again. 3570 */ 3571 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3572 if (!ds) { 3573 ds = g_malloc0(sizeof(SpaprDimmState)); 3574 ds->nr_lmbs = nr_lmbs; 3575 ds->dimm = dimm; 3576 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3577 } 3578 return ds; 3579 } 3580 3581 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3582 SpaprDimmState *dimm_state) 3583 { 3584 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3585 g_free(dimm_state); 3586 } 3587 3588 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3589 PCDIMMDevice *dimm) 3590 { 3591 SpaprDrc *drc; 3592 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3593 &error_abort); 3594 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3595 uint32_t avail_lmbs = 0; 3596 uint64_t addr_start, addr; 3597 int i; 3598 3599 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3600 &error_abort); 3601 3602 addr = addr_start; 3603 for (i = 0; i < nr_lmbs; i++) { 3604 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3605 addr / SPAPR_MEMORY_BLOCK_SIZE); 3606 g_assert(drc); 3607 if (drc->dev) { 3608 avail_lmbs++; 3609 } 3610 addr += SPAPR_MEMORY_BLOCK_SIZE; 3611 } 3612 3613 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3614 } 3615 3616 /* Callback to be called during DRC release. */ 3617 void spapr_lmb_release(DeviceState *dev) 3618 { 3619 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3620 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3621 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3622 3623 /* This information will get lost if a migration occurs 3624 * during the unplug process. In this case recover it. */ 3625 if (ds == NULL) { 3626 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3627 g_assert(ds); 3628 /* The DRC being examined by the caller at least must be counted */ 3629 g_assert(ds->nr_lmbs); 3630 } 3631 3632 if (--ds->nr_lmbs) { 3633 return; 3634 } 3635 3636 /* 3637 * Now that all the LMBs have been removed by the guest, call the 3638 * unplug handler chain. This can never fail. 3639 */ 3640 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3641 object_unparent(OBJECT(dev)); 3642 } 3643 3644 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3645 { 3646 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3647 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3648 3649 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3650 qdev_unrealize(dev); 3651 spapr_pending_dimm_unplugs_remove(spapr, ds); 3652 } 3653 3654 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3655 DeviceState *dev, Error **errp) 3656 { 3657 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3658 Error *local_err = NULL; 3659 PCDIMMDevice *dimm = PC_DIMM(dev); 3660 uint32_t nr_lmbs; 3661 uint64_t size, addr_start, addr; 3662 int i; 3663 SpaprDrc *drc; 3664 3665 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3666 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3667 return; 3668 } 3669 3670 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3671 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3672 3673 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3674 &local_err); 3675 if (local_err) { 3676 error_propagate(errp, local_err); 3677 return; 3678 } 3679 3680 /* 3681 * An existing pending dimm state for this DIMM means that there is an 3682 * unplug operation in progress, waiting for the spapr_lmb_release 3683 * callback to complete the job (BQL can't cover that far). In this case, 3684 * bail out to avoid detaching DRCs that were already released. 3685 */ 3686 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3687 error_setg(errp, "Memory unplug already in progress for device %s", 3688 dev->id); 3689 return; 3690 } 3691 3692 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3693 3694 addr = addr_start; 3695 for (i = 0; i < nr_lmbs; i++) { 3696 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3697 addr / SPAPR_MEMORY_BLOCK_SIZE); 3698 g_assert(drc); 3699 3700 spapr_drc_detach(drc); 3701 addr += SPAPR_MEMORY_BLOCK_SIZE; 3702 } 3703 3704 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3705 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3706 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3707 nr_lmbs, spapr_drc_index(drc)); 3708 } 3709 3710 /* Callback to be called during DRC release. */ 3711 void spapr_core_release(DeviceState *dev) 3712 { 3713 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3714 3715 /* Call the unplug handler chain. This can never fail. */ 3716 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3717 object_unparent(OBJECT(dev)); 3718 } 3719 3720 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3721 { 3722 MachineState *ms = MACHINE(hotplug_dev); 3723 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3724 CPUCore *cc = CPU_CORE(dev); 3725 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3726 3727 if (smc->pre_2_10_has_unused_icps) { 3728 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3729 int i; 3730 3731 for (i = 0; i < cc->nr_threads; i++) { 3732 CPUState *cs = CPU(sc->threads[i]); 3733 3734 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3735 } 3736 } 3737 3738 assert(core_slot); 3739 core_slot->cpu = NULL; 3740 qdev_unrealize(dev); 3741 } 3742 3743 static 3744 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3745 Error **errp) 3746 { 3747 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3748 int index; 3749 SpaprDrc *drc; 3750 CPUCore *cc = CPU_CORE(dev); 3751 3752 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3753 error_setg(errp, "Unable to find CPU core with core-id: %d", 3754 cc->core_id); 3755 return; 3756 } 3757 if (index == 0) { 3758 error_setg(errp, "Boot CPU core may not be unplugged"); 3759 return; 3760 } 3761 3762 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3763 spapr_vcpu_id(spapr, cc->core_id)); 3764 g_assert(drc); 3765 3766 if (!spapr_drc_unplug_requested(drc)) { 3767 spapr_drc_detach(drc); 3768 spapr_hotplug_req_remove_by_index(drc); 3769 } 3770 } 3771 3772 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3773 void *fdt, int *fdt_start_offset, Error **errp) 3774 { 3775 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3776 CPUState *cs = CPU(core->threads[0]); 3777 PowerPCCPU *cpu = POWERPC_CPU(cs); 3778 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3779 int id = spapr_get_vcpu_id(cpu); 3780 char *nodename; 3781 int offset; 3782 3783 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3784 offset = fdt_add_subnode(fdt, 0, nodename); 3785 g_free(nodename); 3786 3787 spapr_dt_cpu(cs, fdt, offset, spapr); 3788 3789 *fdt_start_offset = offset; 3790 return 0; 3791 } 3792 3793 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3794 Error **errp) 3795 { 3796 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3797 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3798 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3799 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3800 CPUCore *cc = CPU_CORE(dev); 3801 CPUState *cs; 3802 SpaprDrc *drc; 3803 Error *local_err = NULL; 3804 CPUArchId *core_slot; 3805 int index; 3806 bool hotplugged = spapr_drc_hotplugged(dev); 3807 int i; 3808 3809 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3810 if (!core_slot) { 3811 error_setg(errp, "Unable to find CPU core with core-id: %d", 3812 cc->core_id); 3813 return; 3814 } 3815 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3816 spapr_vcpu_id(spapr, cc->core_id)); 3817 3818 g_assert(drc || !mc->has_hotpluggable_cpus); 3819 3820 if (drc) { 3821 spapr_drc_attach(drc, dev, &local_err); 3822 if (local_err) { 3823 error_propagate(errp, local_err); 3824 return; 3825 } 3826 3827 if (hotplugged) { 3828 /* 3829 * Send hotplug notification interrupt to the guest only 3830 * in case of hotplugged CPUs. 3831 */ 3832 spapr_hotplug_req_add_by_index(drc); 3833 } else { 3834 spapr_drc_reset(drc); 3835 } 3836 } 3837 3838 core_slot->cpu = OBJECT(dev); 3839 3840 if (smc->pre_2_10_has_unused_icps) { 3841 for (i = 0; i < cc->nr_threads; i++) { 3842 cs = CPU(core->threads[i]); 3843 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3844 } 3845 } 3846 3847 /* 3848 * Set compatibility mode to match the boot CPU, which was either set 3849 * by the machine reset code or by CAS. 3850 */ 3851 if (hotplugged) { 3852 for (i = 0; i < cc->nr_threads; i++) { 3853 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3854 &local_err); 3855 if (local_err) { 3856 error_propagate(errp, local_err); 3857 return; 3858 } 3859 } 3860 } 3861 } 3862 3863 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3864 Error **errp) 3865 { 3866 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3867 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3868 CPUCore *cc = CPU_CORE(dev); 3869 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3870 const char *type = object_get_typename(OBJECT(dev)); 3871 CPUArchId *core_slot; 3872 int index; 3873 unsigned int smp_threads = machine->smp.threads; 3874 3875 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3876 error_setg(errp, "CPU hotplug not supported for this machine"); 3877 return; 3878 } 3879 3880 if (strcmp(base_core_type, type)) { 3881 error_setg(errp, "CPU core type should be %s", base_core_type); 3882 return; 3883 } 3884 3885 if (cc->core_id % smp_threads) { 3886 error_setg(errp, "invalid core id %d", cc->core_id); 3887 return; 3888 } 3889 3890 /* 3891 * In general we should have homogeneous threads-per-core, but old 3892 * (pre hotplug support) machine types allow the last core to have 3893 * reduced threads as a compatibility hack for when we allowed 3894 * total vcpus not a multiple of threads-per-core. 3895 */ 3896 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3897 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 3898 smp_threads); 3899 return; 3900 } 3901 3902 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3903 if (!core_slot) { 3904 error_setg(errp, "core id %d out of range", cc->core_id); 3905 return; 3906 } 3907 3908 if (core_slot->cpu) { 3909 error_setg(errp, "core %d already populated", cc->core_id); 3910 return; 3911 } 3912 3913 numa_cpu_pre_plug(core_slot, dev, errp); 3914 } 3915 3916 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3917 void *fdt, int *fdt_start_offset, Error **errp) 3918 { 3919 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3920 int intc_phandle; 3921 3922 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3923 if (intc_phandle <= 0) { 3924 return -1; 3925 } 3926 3927 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3928 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3929 return -1; 3930 } 3931 3932 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3933 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3934 3935 return 0; 3936 } 3937 3938 static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3939 Error **errp) 3940 { 3941 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3942 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3943 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3944 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3945 3946 if (dev->hotplugged && !smc->dr_phb_enabled) { 3947 error_setg(errp, "PHB hotplug not supported for this machine"); 3948 return; 3949 } 3950 3951 if (sphb->index == (uint32_t)-1) { 3952 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3953 return; 3954 } 3955 3956 /* 3957 * This will check that sphb->index doesn't exceed the maximum number of 3958 * PHBs for the current machine type. 3959 */ 3960 smc->phb_placement(spapr, sphb->index, 3961 &sphb->buid, &sphb->io_win_addr, 3962 &sphb->mem_win_addr, &sphb->mem64_win_addr, 3963 windows_supported, sphb->dma_liobn, 3964 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 3965 errp); 3966 } 3967 3968 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3969 Error **errp) 3970 { 3971 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3972 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3973 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3974 SpaprDrc *drc; 3975 bool hotplugged = spapr_drc_hotplugged(dev); 3976 Error *local_err = NULL; 3977 3978 if (!smc->dr_phb_enabled) { 3979 return; 3980 } 3981 3982 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3983 /* hotplug hooks should check it's enabled before getting this far */ 3984 assert(drc); 3985 3986 spapr_drc_attach(drc, dev, &local_err); 3987 if (local_err) { 3988 error_propagate(errp, local_err); 3989 return; 3990 } 3991 3992 if (hotplugged) { 3993 spapr_hotplug_req_add_by_index(drc); 3994 } else { 3995 spapr_drc_reset(drc); 3996 } 3997 } 3998 3999 void spapr_phb_release(DeviceState *dev) 4000 { 4001 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4002 4003 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4004 object_unparent(OBJECT(dev)); 4005 } 4006 4007 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4008 { 4009 qdev_unrealize(dev); 4010 } 4011 4012 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4013 DeviceState *dev, Error **errp) 4014 { 4015 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4016 SpaprDrc *drc; 4017 4018 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4019 assert(drc); 4020 4021 if (!spapr_drc_unplug_requested(drc)) { 4022 spapr_drc_detach(drc); 4023 spapr_hotplug_req_remove_by_index(drc); 4024 } 4025 } 4026 4027 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4028 Error **errp) 4029 { 4030 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4031 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4032 4033 if (spapr->tpm_proxy != NULL) { 4034 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4035 return; 4036 } 4037 4038 spapr->tpm_proxy = tpm_proxy; 4039 } 4040 4041 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4042 { 4043 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4044 4045 qdev_unrealize(dev); 4046 object_unparent(OBJECT(dev)); 4047 spapr->tpm_proxy = NULL; 4048 } 4049 4050 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4051 DeviceState *dev, Error **errp) 4052 { 4053 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4054 spapr_memory_plug(hotplug_dev, dev, errp); 4055 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4056 spapr_core_plug(hotplug_dev, dev, errp); 4057 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4058 spapr_phb_plug(hotplug_dev, dev, errp); 4059 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4060 spapr_tpm_proxy_plug(hotplug_dev, dev, errp); 4061 } 4062 } 4063 4064 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4065 DeviceState *dev, Error **errp) 4066 { 4067 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4068 spapr_memory_unplug(hotplug_dev, dev); 4069 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4070 spapr_core_unplug(hotplug_dev, dev); 4071 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4072 spapr_phb_unplug(hotplug_dev, dev); 4073 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4074 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4075 } 4076 } 4077 4078 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4079 DeviceState *dev, Error **errp) 4080 { 4081 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4082 MachineClass *mc = MACHINE_GET_CLASS(sms); 4083 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4084 4085 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4086 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 4087 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4088 } else { 4089 /* NOTE: this means there is a window after guest reset, prior to 4090 * CAS negotiation, where unplug requests will fail due to the 4091 * capability not being detected yet. This is a bit different than 4092 * the case with PCI unplug, where the events will be queued and 4093 * eventually handled by the guest after boot 4094 */ 4095 error_setg(errp, "Memory hot unplug not supported for this guest"); 4096 } 4097 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4098 if (!mc->has_hotpluggable_cpus) { 4099 error_setg(errp, "CPU hot unplug not supported on this machine"); 4100 return; 4101 } 4102 spapr_core_unplug_request(hotplug_dev, dev, errp); 4103 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4104 if (!smc->dr_phb_enabled) { 4105 error_setg(errp, "PHB hot unplug not supported on this machine"); 4106 return; 4107 } 4108 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4109 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4110 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4111 } 4112 } 4113 4114 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4115 DeviceState *dev, Error **errp) 4116 { 4117 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4118 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4119 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4120 spapr_core_pre_plug(hotplug_dev, dev, errp); 4121 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4122 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4123 } 4124 } 4125 4126 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4127 DeviceState *dev) 4128 { 4129 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4130 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4131 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4132 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4133 return HOTPLUG_HANDLER(machine); 4134 } 4135 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4136 PCIDevice *pcidev = PCI_DEVICE(dev); 4137 PCIBus *root = pci_device_root_bus(pcidev); 4138 SpaprPhbState *phb = 4139 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4140 TYPE_SPAPR_PCI_HOST_BRIDGE); 4141 4142 if (phb) { 4143 return HOTPLUG_HANDLER(phb); 4144 } 4145 } 4146 return NULL; 4147 } 4148 4149 static CpuInstanceProperties 4150 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4151 { 4152 CPUArchId *core_slot; 4153 MachineClass *mc = MACHINE_GET_CLASS(machine); 4154 4155 /* make sure possible_cpu are intialized */ 4156 mc->possible_cpu_arch_ids(machine); 4157 /* get CPU core slot containing thread that matches cpu_index */ 4158 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4159 assert(core_slot); 4160 return core_slot->props; 4161 } 4162 4163 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4164 { 4165 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4166 } 4167 4168 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4169 { 4170 int i; 4171 unsigned int smp_threads = machine->smp.threads; 4172 unsigned int smp_cpus = machine->smp.cpus; 4173 const char *core_type; 4174 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4175 MachineClass *mc = MACHINE_GET_CLASS(machine); 4176 4177 if (!mc->has_hotpluggable_cpus) { 4178 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4179 } 4180 if (machine->possible_cpus) { 4181 assert(machine->possible_cpus->len == spapr_max_cores); 4182 return machine->possible_cpus; 4183 } 4184 4185 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4186 if (!core_type) { 4187 error_report("Unable to find sPAPR CPU Core definition"); 4188 exit(1); 4189 } 4190 4191 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4192 sizeof(CPUArchId) * spapr_max_cores); 4193 machine->possible_cpus->len = spapr_max_cores; 4194 for (i = 0; i < machine->possible_cpus->len; i++) { 4195 int core_id = i * smp_threads; 4196 4197 machine->possible_cpus->cpus[i].type = core_type; 4198 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4199 machine->possible_cpus->cpus[i].arch_id = core_id; 4200 machine->possible_cpus->cpus[i].props.has_core_id = true; 4201 machine->possible_cpus->cpus[i].props.core_id = core_id; 4202 } 4203 return machine->possible_cpus; 4204 } 4205 4206 static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4207 uint64_t *buid, hwaddr *pio, 4208 hwaddr *mmio32, hwaddr *mmio64, 4209 unsigned n_dma, uint32_t *liobns, 4210 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4211 { 4212 /* 4213 * New-style PHB window placement. 4214 * 4215 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4216 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4217 * windows. 4218 * 4219 * Some guest kernels can't work with MMIO windows above 1<<46 4220 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4221 * 4222 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4223 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4224 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4225 * 1TiB 64-bit MMIO windows for each PHB. 4226 */ 4227 const uint64_t base_buid = 0x800000020000000ULL; 4228 int i; 4229 4230 /* Sanity check natural alignments */ 4231 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4232 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4233 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4234 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4235 /* Sanity check bounds */ 4236 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4237 SPAPR_PCI_MEM32_WIN_SIZE); 4238 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4239 SPAPR_PCI_MEM64_WIN_SIZE); 4240 4241 if (index >= SPAPR_MAX_PHBS) { 4242 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4243 SPAPR_MAX_PHBS - 1); 4244 return; 4245 } 4246 4247 *buid = base_buid + index; 4248 for (i = 0; i < n_dma; ++i) { 4249 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4250 } 4251 4252 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4253 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4254 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4255 4256 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4257 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4258 } 4259 4260 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4261 { 4262 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4263 4264 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4265 } 4266 4267 static void spapr_ics_resend(XICSFabric *dev) 4268 { 4269 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4270 4271 ics_resend(spapr->ics); 4272 } 4273 4274 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4275 { 4276 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4277 4278 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4279 } 4280 4281 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4282 Monitor *mon) 4283 { 4284 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4285 4286 spapr_irq_print_info(spapr, mon); 4287 monitor_printf(mon, "irqchip: %s\n", 4288 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4289 } 4290 4291 /* 4292 * This is a XIVE only operation 4293 */ 4294 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4295 uint8_t nvt_blk, uint32_t nvt_idx, 4296 bool cam_ignore, uint8_t priority, 4297 uint32_t logic_serv, XiveTCTXMatch *match) 4298 { 4299 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4300 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4301 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4302 int count; 4303 4304 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4305 priority, logic_serv, match); 4306 if (count < 0) { 4307 return count; 4308 } 4309 4310 /* 4311 * When we implement the save and restore of the thread interrupt 4312 * contexts in the enter/exit CPU handlers of the machine and the 4313 * escalations in QEMU, we should be able to handle non dispatched 4314 * vCPUs. 4315 * 4316 * Until this is done, the sPAPR machine should find at least one 4317 * matching context always. 4318 */ 4319 if (count == 0) { 4320 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4321 nvt_blk, nvt_idx); 4322 } 4323 4324 return count; 4325 } 4326 4327 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4328 { 4329 return cpu->vcpu_id; 4330 } 4331 4332 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4333 { 4334 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4335 MachineState *ms = MACHINE(spapr); 4336 int vcpu_id; 4337 4338 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4339 4340 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4341 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4342 error_append_hint(errp, "Adjust the number of cpus to %d " 4343 "or try to raise the number of threads per core\n", 4344 vcpu_id * ms->smp.threads / spapr->vsmt); 4345 return; 4346 } 4347 4348 cpu->vcpu_id = vcpu_id; 4349 } 4350 4351 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4352 { 4353 CPUState *cs; 4354 4355 CPU_FOREACH(cs) { 4356 PowerPCCPU *cpu = POWERPC_CPU(cs); 4357 4358 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4359 return cpu; 4360 } 4361 } 4362 4363 return NULL; 4364 } 4365 4366 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4367 { 4368 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4369 4370 /* These are only called by TCG, KVM maintains dispatch state */ 4371 4372 spapr_cpu->prod = false; 4373 if (spapr_cpu->vpa_addr) { 4374 CPUState *cs = CPU(cpu); 4375 uint32_t dispatch; 4376 4377 dispatch = ldl_be_phys(cs->as, 4378 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4379 dispatch++; 4380 if ((dispatch & 1) != 0) { 4381 qemu_log_mask(LOG_GUEST_ERROR, 4382 "VPA: incorrect dispatch counter value for " 4383 "dispatched partition %u, correcting.\n", dispatch); 4384 dispatch++; 4385 } 4386 stl_be_phys(cs->as, 4387 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4388 } 4389 } 4390 4391 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4392 { 4393 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4394 4395 if (spapr_cpu->vpa_addr) { 4396 CPUState *cs = CPU(cpu); 4397 uint32_t dispatch; 4398 4399 dispatch = ldl_be_phys(cs->as, 4400 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4401 dispatch++; 4402 if ((dispatch & 1) != 1) { 4403 qemu_log_mask(LOG_GUEST_ERROR, 4404 "VPA: incorrect dispatch counter value for " 4405 "preempted partition %u, correcting.\n", dispatch); 4406 dispatch++; 4407 } 4408 stl_be_phys(cs->as, 4409 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4410 } 4411 } 4412 4413 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4414 { 4415 MachineClass *mc = MACHINE_CLASS(oc); 4416 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4417 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4418 NMIClass *nc = NMI_CLASS(oc); 4419 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4420 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4421 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4422 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4423 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4424 4425 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4426 mc->ignore_boot_device_suffixes = true; 4427 4428 /* 4429 * We set up the default / latest behaviour here. The class_init 4430 * functions for the specific versioned machine types can override 4431 * these details for backwards compatibility 4432 */ 4433 mc->init = spapr_machine_init; 4434 mc->reset = spapr_machine_reset; 4435 mc->block_default_type = IF_SCSI; 4436 mc->max_cpus = 1024; 4437 mc->no_parallel = 1; 4438 mc->default_boot_order = ""; 4439 mc->default_ram_size = 512 * MiB; 4440 mc->default_ram_id = "ppc_spapr.ram"; 4441 mc->default_display = "std"; 4442 mc->kvm_type = spapr_kvm_type; 4443 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4444 mc->pci_allow_0_address = true; 4445 assert(!mc->get_hotplug_handler); 4446 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4447 hc->pre_plug = spapr_machine_device_pre_plug; 4448 hc->plug = spapr_machine_device_plug; 4449 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4450 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4451 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4452 hc->unplug_request = spapr_machine_device_unplug_request; 4453 hc->unplug = spapr_machine_device_unplug; 4454 4455 smc->dr_lmb_enabled = true; 4456 smc->update_dt_enabled = true; 4457 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4458 mc->has_hotpluggable_cpus = true; 4459 mc->nvdimm_supported = true; 4460 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4461 fwc->get_dev_path = spapr_get_fw_dev_path; 4462 nc->nmi_monitor_handler = spapr_nmi; 4463 smc->phb_placement = spapr_phb_placement; 4464 vhc->hypercall = emulate_spapr_hypercall; 4465 vhc->hpt_mask = spapr_hpt_mask; 4466 vhc->map_hptes = spapr_map_hptes; 4467 vhc->unmap_hptes = spapr_unmap_hptes; 4468 vhc->hpte_set_c = spapr_hpte_set_c; 4469 vhc->hpte_set_r = spapr_hpte_set_r; 4470 vhc->get_pate = spapr_get_pate; 4471 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4472 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4473 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4474 xic->ics_get = spapr_ics_get; 4475 xic->ics_resend = spapr_ics_resend; 4476 xic->icp_get = spapr_icp_get; 4477 ispc->print_info = spapr_pic_print_info; 4478 /* Force NUMA node memory size to be a multiple of 4479 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4480 * in which LMBs are represented and hot-added 4481 */ 4482 mc->numa_mem_align_shift = 28; 4483 mc->auto_enable_numa = true; 4484 4485 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4486 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4487 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4488 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4489 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4490 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4491 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4492 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4493 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4494 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4495 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4496 spapr_caps_add_properties(smc); 4497 smc->irq = &spapr_irq_dual; 4498 smc->dr_phb_enabled = true; 4499 smc->linux_pci_probe = true; 4500 smc->smp_threads_vsmt = true; 4501 smc->nr_xirqs = SPAPR_NR_XIRQS; 4502 xfc->match_nvt = spapr_match_nvt; 4503 } 4504 4505 static const TypeInfo spapr_machine_info = { 4506 .name = TYPE_SPAPR_MACHINE, 4507 .parent = TYPE_MACHINE, 4508 .abstract = true, 4509 .instance_size = sizeof(SpaprMachineState), 4510 .instance_init = spapr_instance_init, 4511 .instance_finalize = spapr_machine_finalizefn, 4512 .class_size = sizeof(SpaprMachineClass), 4513 .class_init = spapr_machine_class_init, 4514 .interfaces = (InterfaceInfo[]) { 4515 { TYPE_FW_PATH_PROVIDER }, 4516 { TYPE_NMI }, 4517 { TYPE_HOTPLUG_HANDLER }, 4518 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4519 { TYPE_XICS_FABRIC }, 4520 { TYPE_INTERRUPT_STATS_PROVIDER }, 4521 { TYPE_XIVE_FABRIC }, 4522 { } 4523 }, 4524 }; 4525 4526 static void spapr_machine_latest_class_options(MachineClass *mc) 4527 { 4528 mc->alias = "pseries"; 4529 mc->is_default = true; 4530 } 4531 4532 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4533 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4534 void *data) \ 4535 { \ 4536 MachineClass *mc = MACHINE_CLASS(oc); \ 4537 spapr_machine_##suffix##_class_options(mc); \ 4538 if (latest) { \ 4539 spapr_machine_latest_class_options(mc); \ 4540 } \ 4541 } \ 4542 static const TypeInfo spapr_machine_##suffix##_info = { \ 4543 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4544 .parent = TYPE_SPAPR_MACHINE, \ 4545 .class_init = spapr_machine_##suffix##_class_init, \ 4546 }; \ 4547 static void spapr_machine_register_##suffix(void) \ 4548 { \ 4549 type_register(&spapr_machine_##suffix##_info); \ 4550 } \ 4551 type_init(spapr_machine_register_##suffix) 4552 4553 /* 4554 * pseries-5.2 4555 */ 4556 static void spapr_machine_5_2_class_options(MachineClass *mc) 4557 { 4558 /* Defaults for the latest behaviour inherited from the base class */ 4559 } 4560 4561 DEFINE_SPAPR_MACHINE(5_2, "5.2", true); 4562 4563 /* 4564 * pseries-5.1 4565 */ 4566 static void spapr_machine_5_1_class_options(MachineClass *mc) 4567 { 4568 spapr_machine_5_2_class_options(mc); 4569 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4570 } 4571 4572 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4573 4574 /* 4575 * pseries-5.0 4576 */ 4577 static void spapr_machine_5_0_class_options(MachineClass *mc) 4578 { 4579 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4580 static GlobalProperty compat[] = { 4581 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4582 }; 4583 4584 spapr_machine_5_1_class_options(mc); 4585 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4586 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4587 mc->numa_mem_supported = true; 4588 smc->pre_5_1_assoc_refpoints = true; 4589 } 4590 4591 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4592 4593 /* 4594 * pseries-4.2 4595 */ 4596 static void spapr_machine_4_2_class_options(MachineClass *mc) 4597 { 4598 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4599 4600 spapr_machine_5_0_class_options(mc); 4601 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4602 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4603 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4604 smc->rma_limit = 16 * GiB; 4605 mc->nvdimm_supported = false; 4606 } 4607 4608 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4609 4610 /* 4611 * pseries-4.1 4612 */ 4613 static void spapr_machine_4_1_class_options(MachineClass *mc) 4614 { 4615 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4616 static GlobalProperty compat[] = { 4617 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4618 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4619 }; 4620 4621 spapr_machine_4_2_class_options(mc); 4622 smc->linux_pci_probe = false; 4623 smc->smp_threads_vsmt = false; 4624 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4625 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4626 } 4627 4628 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4629 4630 /* 4631 * pseries-4.0 4632 */ 4633 static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4634 uint64_t *buid, hwaddr *pio, 4635 hwaddr *mmio32, hwaddr *mmio64, 4636 unsigned n_dma, uint32_t *liobns, 4637 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4638 { 4639 spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns, 4640 nv2gpa, nv2atsd, errp); 4641 *nv2gpa = 0; 4642 *nv2atsd = 0; 4643 } 4644 4645 static void spapr_machine_4_0_class_options(MachineClass *mc) 4646 { 4647 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4648 4649 spapr_machine_4_1_class_options(mc); 4650 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4651 smc->phb_placement = phb_placement_4_0; 4652 smc->irq = &spapr_irq_xics; 4653 smc->pre_4_1_migration = true; 4654 } 4655 4656 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4657 4658 /* 4659 * pseries-3.1 4660 */ 4661 static void spapr_machine_3_1_class_options(MachineClass *mc) 4662 { 4663 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4664 4665 spapr_machine_4_0_class_options(mc); 4666 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4667 4668 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4669 smc->update_dt_enabled = false; 4670 smc->dr_phb_enabled = false; 4671 smc->broken_host_serial_model = true; 4672 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4673 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4674 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4675 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4676 } 4677 4678 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4679 4680 /* 4681 * pseries-3.0 4682 */ 4683 4684 static void spapr_machine_3_0_class_options(MachineClass *mc) 4685 { 4686 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4687 4688 spapr_machine_3_1_class_options(mc); 4689 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4690 4691 smc->legacy_irq_allocation = true; 4692 smc->nr_xirqs = 0x400; 4693 smc->irq = &spapr_irq_xics_legacy; 4694 } 4695 4696 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4697 4698 /* 4699 * pseries-2.12 4700 */ 4701 static void spapr_machine_2_12_class_options(MachineClass *mc) 4702 { 4703 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4704 static GlobalProperty compat[] = { 4705 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4706 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4707 }; 4708 4709 spapr_machine_3_0_class_options(mc); 4710 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4711 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4712 4713 /* We depend on kvm_enabled() to choose a default value for the 4714 * hpt-max-page-size capability. Of course we can't do it here 4715 * because this is too early and the HW accelerator isn't initialzed 4716 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4717 */ 4718 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4719 } 4720 4721 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4722 4723 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4724 { 4725 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4726 4727 spapr_machine_2_12_class_options(mc); 4728 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4729 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4730 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4731 } 4732 4733 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4734 4735 /* 4736 * pseries-2.11 4737 */ 4738 4739 static void spapr_machine_2_11_class_options(MachineClass *mc) 4740 { 4741 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4742 4743 spapr_machine_2_12_class_options(mc); 4744 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4745 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4746 } 4747 4748 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4749 4750 /* 4751 * pseries-2.10 4752 */ 4753 4754 static void spapr_machine_2_10_class_options(MachineClass *mc) 4755 { 4756 spapr_machine_2_11_class_options(mc); 4757 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4758 } 4759 4760 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4761 4762 /* 4763 * pseries-2.9 4764 */ 4765 4766 static void spapr_machine_2_9_class_options(MachineClass *mc) 4767 { 4768 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4769 static GlobalProperty compat[] = { 4770 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4771 }; 4772 4773 spapr_machine_2_10_class_options(mc); 4774 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4775 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4776 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4777 smc->pre_2_10_has_unused_icps = true; 4778 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4779 } 4780 4781 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4782 4783 /* 4784 * pseries-2.8 4785 */ 4786 4787 static void spapr_machine_2_8_class_options(MachineClass *mc) 4788 { 4789 static GlobalProperty compat[] = { 4790 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4791 }; 4792 4793 spapr_machine_2_9_class_options(mc); 4794 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4795 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4796 mc->numa_mem_align_shift = 23; 4797 } 4798 4799 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4800 4801 /* 4802 * pseries-2.7 4803 */ 4804 4805 static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4806 uint64_t *buid, hwaddr *pio, 4807 hwaddr *mmio32, hwaddr *mmio64, 4808 unsigned n_dma, uint32_t *liobns, 4809 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4810 { 4811 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4812 const uint64_t base_buid = 0x800000020000000ULL; 4813 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4814 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4815 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4816 const uint32_t max_index = 255; 4817 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4818 4819 uint64_t ram_top = MACHINE(spapr)->ram_size; 4820 hwaddr phb0_base, phb_base; 4821 int i; 4822 4823 /* Do we have device memory? */ 4824 if (MACHINE(spapr)->maxram_size > ram_top) { 4825 /* Can't just use maxram_size, because there may be an 4826 * alignment gap between normal and device memory regions 4827 */ 4828 ram_top = MACHINE(spapr)->device_memory->base + 4829 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4830 } 4831 4832 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4833 4834 if (index > max_index) { 4835 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4836 max_index); 4837 return; 4838 } 4839 4840 *buid = base_buid + index; 4841 for (i = 0; i < n_dma; ++i) { 4842 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4843 } 4844 4845 phb_base = phb0_base + index * phb_spacing; 4846 *pio = phb_base + pio_offset; 4847 *mmio32 = phb_base + mmio_offset; 4848 /* 4849 * We don't set the 64-bit MMIO window, relying on the PHB's 4850 * fallback behaviour of automatically splitting a large "32-bit" 4851 * window into contiguous 32-bit and 64-bit windows 4852 */ 4853 4854 *nv2gpa = 0; 4855 *nv2atsd = 0; 4856 } 4857 4858 static void spapr_machine_2_7_class_options(MachineClass *mc) 4859 { 4860 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4861 static GlobalProperty compat[] = { 4862 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4863 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4864 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4865 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4866 }; 4867 4868 spapr_machine_2_8_class_options(mc); 4869 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4870 mc->default_machine_opts = "modern-hotplug-events=off"; 4871 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4872 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4873 smc->phb_placement = phb_placement_2_7; 4874 } 4875 4876 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4877 4878 /* 4879 * pseries-2.6 4880 */ 4881 4882 static void spapr_machine_2_6_class_options(MachineClass *mc) 4883 { 4884 static GlobalProperty compat[] = { 4885 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4886 }; 4887 4888 spapr_machine_2_7_class_options(mc); 4889 mc->has_hotpluggable_cpus = false; 4890 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4891 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4892 } 4893 4894 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4895 4896 /* 4897 * pseries-2.5 4898 */ 4899 4900 static void spapr_machine_2_5_class_options(MachineClass *mc) 4901 { 4902 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4903 static GlobalProperty compat[] = { 4904 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4905 }; 4906 4907 spapr_machine_2_6_class_options(mc); 4908 smc->use_ohci_by_default = true; 4909 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4910 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4911 } 4912 4913 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4914 4915 /* 4916 * pseries-2.4 4917 */ 4918 4919 static void spapr_machine_2_4_class_options(MachineClass *mc) 4920 { 4921 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4922 4923 spapr_machine_2_5_class_options(mc); 4924 smc->dr_lmb_enabled = false; 4925 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4926 } 4927 4928 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4929 4930 /* 4931 * pseries-2.3 4932 */ 4933 4934 static void spapr_machine_2_3_class_options(MachineClass *mc) 4935 { 4936 static GlobalProperty compat[] = { 4937 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4938 }; 4939 spapr_machine_2_4_class_options(mc); 4940 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4941 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4942 } 4943 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4944 4945 /* 4946 * pseries-2.2 4947 */ 4948 4949 static void spapr_machine_2_2_class_options(MachineClass *mc) 4950 { 4951 static GlobalProperty compat[] = { 4952 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4953 }; 4954 4955 spapr_machine_2_3_class_options(mc); 4956 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4957 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4958 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4959 } 4960 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4961 4962 /* 4963 * pseries-2.1 4964 */ 4965 4966 static void spapr_machine_2_1_class_options(MachineClass *mc) 4967 { 4968 spapr_machine_2_2_class_options(mc); 4969 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4970 } 4971 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4972 4973 static void spapr_machine_register_types(void) 4974 { 4975 type_register_static(&spapr_machine_info); 4976 } 4977 4978 type_init(spapr_machine_register_types) 4979