1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qapi/error.h" 30 #include "qapi/visitor.h" 31 #include "sysemu/sysemu.h" 32 #include "sysemu/hostmem.h" 33 #include "sysemu/numa.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/reset.h" 36 #include "sysemu/runstate.h" 37 #include "qemu/log.h" 38 #include "hw/fw-path-provider.h" 39 #include "elf.h" 40 #include "net/net.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/cpus.h" 43 #include "sysemu/hw_accel.h" 44 #include "kvm_ppc.h" 45 #include "migration/misc.h" 46 #include "migration/qemu-file-types.h" 47 #include "migration/global_state.h" 48 #include "migration/register.h" 49 #include "migration/blocker.h" 50 #include "mmu-hash64.h" 51 #include "mmu-book3s-v3.h" 52 #include "cpu-models.h" 53 #include "hw/core/cpu.h" 54 55 #include "hw/boards.h" 56 #include "hw/ppc/ppc.h" 57 #include "hw/loader.h" 58 59 #include "hw/ppc/fdt.h" 60 #include "hw/ppc/spapr.h" 61 #include "hw/ppc/spapr_vio.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/pci-host/spapr.h" 64 #include "hw/pci/msi.h" 65 66 #include "hw/pci/pci.h" 67 #include "hw/scsi/scsi.h" 68 #include "hw/virtio/virtio-scsi.h" 69 #include "hw/virtio/vhost-scsi-common.h" 70 71 #include "exec/address-spaces.h" 72 #include "exec/ram_addr.h" 73 #include "hw/usb.h" 74 #include "qemu/config-file.h" 75 #include "qemu/error-report.h" 76 #include "trace.h" 77 #include "hw/nmi.h" 78 #include "hw/intc/intc.h" 79 80 #include "hw/ppc/spapr_cpu_core.h" 81 #include "hw/mem/memory-device.h" 82 #include "hw/ppc/spapr_tpm_proxy.h" 83 #include "hw/ppc/spapr_nvdimm.h" 84 85 #include "monitor/monitor.h" 86 87 #include <libfdt.h> 88 89 /* SLOF memory layout: 90 * 91 * SLOF raw image loaded at 0, copies its romfs right below the flat 92 * device-tree, then position SLOF itself 31M below that 93 * 94 * So we set FW_OVERHEAD to 40MB which should account for all of that 95 * and more 96 * 97 * We load our kernel at 4M, leaving space for SLOF initial image 98 */ 99 #define FDT_MAX_SIZE 0x100000 100 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 101 #define FW_MAX_SIZE 0x400000 102 #define FW_FILE_NAME "slof.bin" 103 #define FW_OVERHEAD 0x2800000 104 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 105 106 #define MIN_RMA_SLOF 128UL 107 108 #define PHANDLE_INTC 0x00001111 109 110 /* These two functions implement the VCPU id numbering: one to compute them 111 * all and one to identify thread 0 of a VCORE. Any change to the first one 112 * is likely to have an impact on the second one, so let's keep them close. 113 */ 114 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 115 { 116 MachineState *ms = MACHINE(spapr); 117 unsigned int smp_threads = ms->smp.threads; 118 119 assert(spapr->vsmt); 120 return 121 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 122 } 123 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 124 PowerPCCPU *cpu) 125 { 126 assert(spapr->vsmt); 127 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 128 } 129 130 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 131 { 132 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 133 * and newer QEMUs don't even have them. In both cases, we don't want 134 * to send anything on the wire. 135 */ 136 return false; 137 } 138 139 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 140 .name = "icp/server", 141 .version_id = 1, 142 .minimum_version_id = 1, 143 .needed = pre_2_10_vmstate_dummy_icp_needed, 144 .fields = (VMStateField[]) { 145 VMSTATE_UNUSED(4), /* uint32_t xirr */ 146 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 147 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 148 VMSTATE_END_OF_LIST() 149 }, 150 }; 151 152 static void pre_2_10_vmstate_register_dummy_icp(int i) 153 { 154 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 155 (void *)(uintptr_t) i); 156 } 157 158 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 159 { 160 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 161 (void *)(uintptr_t) i); 162 } 163 164 int spapr_max_server_number(SpaprMachineState *spapr) 165 { 166 MachineState *ms = MACHINE(spapr); 167 168 assert(spapr->vsmt); 169 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 170 } 171 172 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 173 int smt_threads) 174 { 175 int i, ret = 0; 176 uint32_t servers_prop[smt_threads]; 177 uint32_t gservers_prop[smt_threads * 2]; 178 int index = spapr_get_vcpu_id(cpu); 179 180 if (cpu->compat_pvr) { 181 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 182 if (ret < 0) { 183 return ret; 184 } 185 } 186 187 /* Build interrupt servers and gservers properties */ 188 for (i = 0; i < smt_threads; i++) { 189 servers_prop[i] = cpu_to_be32(index + i); 190 /* Hack, direct the group queues back to cpu 0 */ 191 gservers_prop[i*2] = cpu_to_be32(index + i); 192 gservers_prop[i*2 + 1] = 0; 193 } 194 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 195 servers_prop, sizeof(servers_prop)); 196 if (ret < 0) { 197 return ret; 198 } 199 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 200 gservers_prop, sizeof(gservers_prop)); 201 202 return ret; 203 } 204 205 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 206 { 207 int index = spapr_get_vcpu_id(cpu); 208 uint32_t associativity[] = {cpu_to_be32(0x5), 209 cpu_to_be32(0x0), 210 cpu_to_be32(0x0), 211 cpu_to_be32(0x0), 212 cpu_to_be32(cpu->node_id), 213 cpu_to_be32(index)}; 214 215 /* Advertise NUMA via ibm,associativity */ 216 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 217 sizeof(associativity)); 218 } 219 220 /* Populate the "ibm,pa-features" property */ 221 static void spapr_populate_pa_features(SpaprMachineState *spapr, 222 PowerPCCPU *cpu, 223 void *fdt, int offset) 224 { 225 uint8_t pa_features_206[] = { 6, 0, 226 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 227 uint8_t pa_features_207[] = { 24, 0, 228 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 229 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 230 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 231 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 232 uint8_t pa_features_300[] = { 66, 0, 233 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 234 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 235 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 236 /* 6: DS207 */ 237 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 238 /* 16: Vector */ 239 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 240 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 241 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 242 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 243 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 244 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 245 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 246 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 247 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 248 /* 42: PM, 44: PC RA, 46: SC vec'd */ 249 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 250 /* 48: SIMD, 50: QP BFP, 52: String */ 251 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 252 /* 54: DecFP, 56: DecI, 58: SHA */ 253 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 254 /* 60: NM atomic, 62: RNG */ 255 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 256 }; 257 uint8_t *pa_features = NULL; 258 size_t pa_size; 259 260 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 261 pa_features = pa_features_206; 262 pa_size = sizeof(pa_features_206); 263 } 264 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 265 pa_features = pa_features_207; 266 pa_size = sizeof(pa_features_207); 267 } 268 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 269 pa_features = pa_features_300; 270 pa_size = sizeof(pa_features_300); 271 } 272 if (!pa_features) { 273 return; 274 } 275 276 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 277 /* 278 * Note: we keep CI large pages off by default because a 64K capable 279 * guest provisioned with large pages might otherwise try to map a qemu 280 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 281 * even if that qemu runs on a 4k host. 282 * We dd this bit back here if we are confident this is not an issue 283 */ 284 pa_features[3] |= 0x20; 285 } 286 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 287 pa_features[24] |= 0x80; /* Transactional memory support */ 288 } 289 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 290 /* Workaround for broken kernels that attempt (guest) radix 291 * mode when they can't handle it, if they see the radix bit set 292 * in pa-features. So hide it from them. */ 293 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 294 } 295 296 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 297 } 298 299 static hwaddr spapr_node0_size(MachineState *machine) 300 { 301 if (machine->numa_state->num_nodes) { 302 int i; 303 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 304 if (machine->numa_state->nodes[i].node_mem) { 305 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 306 machine->ram_size); 307 } 308 } 309 } 310 return machine->ram_size; 311 } 312 313 static void add_str(GString *s, const gchar *s1) 314 { 315 g_string_append_len(s, s1, strlen(s1) + 1); 316 } 317 318 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 319 hwaddr size) 320 { 321 uint32_t associativity[] = { 322 cpu_to_be32(0x4), /* length */ 323 cpu_to_be32(0x0), cpu_to_be32(0x0), 324 cpu_to_be32(0x0), cpu_to_be32(nodeid) 325 }; 326 char mem_name[32]; 327 uint64_t mem_reg_property[2]; 328 int off; 329 330 mem_reg_property[0] = cpu_to_be64(start); 331 mem_reg_property[1] = cpu_to_be64(size); 332 333 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 334 off = fdt_add_subnode(fdt, 0, mem_name); 335 _FDT(off); 336 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 337 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 338 sizeof(mem_reg_property)))); 339 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 340 sizeof(associativity)))); 341 return off; 342 } 343 344 static int spapr_populate_memory(SpaprMachineState *spapr, void *fdt) 345 { 346 MachineState *machine = MACHINE(spapr); 347 hwaddr mem_start, node_size; 348 int i, nb_nodes = machine->numa_state->num_nodes; 349 NodeInfo *nodes = machine->numa_state->nodes; 350 351 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 352 if (!nodes[i].node_mem) { 353 continue; 354 } 355 if (mem_start >= machine->ram_size) { 356 node_size = 0; 357 } else { 358 node_size = nodes[i].node_mem; 359 if (node_size > machine->ram_size - mem_start) { 360 node_size = machine->ram_size - mem_start; 361 } 362 } 363 if (!mem_start) { 364 /* spapr_machine_init() checks for rma_size <= node0_size 365 * already */ 366 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 367 mem_start += spapr->rma_size; 368 node_size -= spapr->rma_size; 369 } 370 for ( ; node_size; ) { 371 hwaddr sizetmp = pow2floor(node_size); 372 373 /* mem_start != 0 here */ 374 if (ctzl(mem_start) < ctzl(sizetmp)) { 375 sizetmp = 1ULL << ctzl(mem_start); 376 } 377 378 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 379 node_size -= sizetmp; 380 mem_start += sizetmp; 381 } 382 } 383 384 return 0; 385 } 386 387 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 388 SpaprMachineState *spapr) 389 { 390 MachineState *ms = MACHINE(spapr); 391 PowerPCCPU *cpu = POWERPC_CPU(cs); 392 CPUPPCState *env = &cpu->env; 393 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 394 int index = spapr_get_vcpu_id(cpu); 395 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 396 0xffffffff, 0xffffffff}; 397 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 398 : SPAPR_TIMEBASE_FREQ; 399 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 400 uint32_t page_sizes_prop[64]; 401 size_t page_sizes_prop_size; 402 unsigned int smp_threads = ms->smp.threads; 403 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 404 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 405 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 406 SpaprDrc *drc; 407 int drc_index; 408 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 409 int i; 410 411 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 412 if (drc) { 413 drc_index = spapr_drc_index(drc); 414 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 415 } 416 417 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 418 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 419 420 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 421 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 422 env->dcache_line_size))); 423 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 424 env->dcache_line_size))); 425 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 426 env->icache_line_size))); 427 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 428 env->icache_line_size))); 429 430 if (pcc->l1_dcache_size) { 431 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 432 pcc->l1_dcache_size))); 433 } else { 434 warn_report("Unknown L1 dcache size for cpu"); 435 } 436 if (pcc->l1_icache_size) { 437 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 438 pcc->l1_icache_size))); 439 } else { 440 warn_report("Unknown L1 icache size for cpu"); 441 } 442 443 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 444 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 445 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 446 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 447 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 448 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 449 450 if (env->spr_cb[SPR_PURR].oea_read) { 451 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 452 } 453 if (env->spr_cb[SPR_SPURR].oea_read) { 454 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 455 } 456 457 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 458 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 459 segs, sizeof(segs)))); 460 } 461 462 /* Advertise VSX (vector extensions) if available 463 * 1 == VMX / Altivec available 464 * 2 == VSX available 465 * 466 * Only CPUs for which we create core types in spapr_cpu_core.c 467 * are possible, and all of those have VMX */ 468 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 469 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 470 } else { 471 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 472 } 473 474 /* Advertise DFP (Decimal Floating Point) if available 475 * 0 / no property == no DFP 476 * 1 == DFP available */ 477 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 478 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 479 } 480 481 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 482 sizeof(page_sizes_prop)); 483 if (page_sizes_prop_size) { 484 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 485 page_sizes_prop, page_sizes_prop_size))); 486 } 487 488 spapr_populate_pa_features(spapr, cpu, fdt, offset); 489 490 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 491 cs->cpu_index / vcpus_per_socket))); 492 493 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 494 pft_size_prop, sizeof(pft_size_prop)))); 495 496 if (ms->numa_state->num_nodes > 1) { 497 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 498 } 499 500 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 501 502 if (pcc->radix_page_info) { 503 for (i = 0; i < pcc->radix_page_info->count; i++) { 504 radix_AP_encodings[i] = 505 cpu_to_be32(pcc->radix_page_info->entries[i]); 506 } 507 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 508 radix_AP_encodings, 509 pcc->radix_page_info->count * 510 sizeof(radix_AP_encodings[0])))); 511 } 512 513 /* 514 * We set this property to let the guest know that it can use the large 515 * decrementer and its width in bits. 516 */ 517 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 518 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 519 pcc->lrg_decr_bits))); 520 } 521 522 static void spapr_populate_cpus_dt_node(void *fdt, SpaprMachineState *spapr) 523 { 524 CPUState **rev; 525 CPUState *cs; 526 int n_cpus; 527 int cpus_offset; 528 char *nodename; 529 int i; 530 531 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 532 _FDT(cpus_offset); 533 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 534 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 535 536 /* 537 * We walk the CPUs in reverse order to ensure that CPU DT nodes 538 * created by fdt_add_subnode() end up in the right order in FDT 539 * for the guest kernel the enumerate the CPUs correctly. 540 * 541 * The CPU list cannot be traversed in reverse order, so we need 542 * to do extra work. 543 */ 544 n_cpus = 0; 545 rev = NULL; 546 CPU_FOREACH(cs) { 547 rev = g_renew(CPUState *, rev, n_cpus + 1); 548 rev[n_cpus++] = cs; 549 } 550 551 for (i = n_cpus - 1; i >= 0; i--) { 552 CPUState *cs = rev[i]; 553 PowerPCCPU *cpu = POWERPC_CPU(cs); 554 int index = spapr_get_vcpu_id(cpu); 555 DeviceClass *dc = DEVICE_GET_CLASS(cs); 556 int offset; 557 558 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 559 continue; 560 } 561 562 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 563 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 564 g_free(nodename); 565 _FDT(offset); 566 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 567 } 568 569 g_free(rev); 570 } 571 572 static int spapr_rng_populate_dt(void *fdt) 573 { 574 int node; 575 int ret; 576 577 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 578 if (node <= 0) { 579 return -1; 580 } 581 ret = fdt_setprop_string(fdt, node, "device_type", 582 "ibm,platform-facilities"); 583 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 584 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 585 586 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 587 if (node <= 0) { 588 return -1; 589 } 590 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 591 592 return ret ? -1 : 0; 593 } 594 595 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 596 { 597 MemoryDeviceInfoList *info; 598 599 for (info = list; info; info = info->next) { 600 MemoryDeviceInfo *value = info->value; 601 602 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 603 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 604 605 if (addr >= pcdimm_info->addr && 606 addr < (pcdimm_info->addr + pcdimm_info->size)) { 607 return pcdimm_info->node; 608 } 609 } 610 } 611 612 return -1; 613 } 614 615 struct sPAPRDrconfCellV2 { 616 uint32_t seq_lmbs; 617 uint64_t base_addr; 618 uint32_t drc_index; 619 uint32_t aa_index; 620 uint32_t flags; 621 } QEMU_PACKED; 622 623 typedef struct DrconfCellQueue { 624 struct sPAPRDrconfCellV2 cell; 625 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 626 } DrconfCellQueue; 627 628 static DrconfCellQueue * 629 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 630 uint32_t drc_index, uint32_t aa_index, 631 uint32_t flags) 632 { 633 DrconfCellQueue *elem; 634 635 elem = g_malloc0(sizeof(*elem)); 636 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 637 elem->cell.base_addr = cpu_to_be64(base_addr); 638 elem->cell.drc_index = cpu_to_be32(drc_index); 639 elem->cell.aa_index = cpu_to_be32(aa_index); 640 elem->cell.flags = cpu_to_be32(flags); 641 642 return elem; 643 } 644 645 /* ibm,dynamic-memory-v2 */ 646 static int spapr_populate_drmem_v2(SpaprMachineState *spapr, void *fdt, 647 int offset, MemoryDeviceInfoList *dimms) 648 { 649 MachineState *machine = MACHINE(spapr); 650 uint8_t *int_buf, *cur_index; 651 int ret; 652 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 653 uint64_t addr, cur_addr, size; 654 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 655 uint64_t mem_end = machine->device_memory->base + 656 memory_region_size(&machine->device_memory->mr); 657 uint32_t node, buf_len, nr_entries = 0; 658 SpaprDrc *drc; 659 DrconfCellQueue *elem, *next; 660 MemoryDeviceInfoList *info; 661 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 662 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 663 664 /* Entry to cover RAM and the gap area */ 665 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 666 SPAPR_LMB_FLAGS_RESERVED | 667 SPAPR_LMB_FLAGS_DRC_INVALID); 668 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 669 nr_entries++; 670 671 cur_addr = machine->device_memory->base; 672 for (info = dimms; info; info = info->next) { 673 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 674 675 addr = di->addr; 676 size = di->size; 677 node = di->node; 678 679 /* 680 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 681 * area is marked hotpluggable in the next iteration for the bigger 682 * chunk including the NVDIMM occupied area. 683 */ 684 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 685 continue; 686 687 /* Entry for hot-pluggable area */ 688 if (cur_addr < addr) { 689 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 690 g_assert(drc); 691 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 692 cur_addr, spapr_drc_index(drc), -1, 0); 693 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 694 nr_entries++; 695 } 696 697 /* Entry for DIMM */ 698 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 699 g_assert(drc); 700 elem = spapr_get_drconf_cell(size / lmb_size, addr, 701 spapr_drc_index(drc), node, 702 SPAPR_LMB_FLAGS_ASSIGNED); 703 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 704 nr_entries++; 705 cur_addr = addr + size; 706 } 707 708 /* Entry for remaining hotpluggable area */ 709 if (cur_addr < mem_end) { 710 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 711 g_assert(drc); 712 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 713 cur_addr, spapr_drc_index(drc), -1, 0); 714 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 715 nr_entries++; 716 } 717 718 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 719 int_buf = cur_index = g_malloc0(buf_len); 720 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 721 cur_index += sizeof(nr_entries); 722 723 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 724 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 725 cur_index += sizeof(elem->cell); 726 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 727 g_free(elem); 728 } 729 730 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 731 g_free(int_buf); 732 if (ret < 0) { 733 return -1; 734 } 735 return 0; 736 } 737 738 /* ibm,dynamic-memory */ 739 static int spapr_populate_drmem_v1(SpaprMachineState *spapr, void *fdt, 740 int offset, MemoryDeviceInfoList *dimms) 741 { 742 MachineState *machine = MACHINE(spapr); 743 int i, ret; 744 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 745 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 746 uint32_t nr_lmbs = (machine->device_memory->base + 747 memory_region_size(&machine->device_memory->mr)) / 748 lmb_size; 749 uint32_t *int_buf, *cur_index, buf_len; 750 751 /* 752 * Allocate enough buffer size to fit in ibm,dynamic-memory 753 */ 754 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 755 cur_index = int_buf = g_malloc0(buf_len); 756 int_buf[0] = cpu_to_be32(nr_lmbs); 757 cur_index++; 758 for (i = 0; i < nr_lmbs; i++) { 759 uint64_t addr = i * lmb_size; 760 uint32_t *dynamic_memory = cur_index; 761 762 if (i >= device_lmb_start) { 763 SpaprDrc *drc; 764 765 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 766 g_assert(drc); 767 768 dynamic_memory[0] = cpu_to_be32(addr >> 32); 769 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 770 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 771 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 772 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 773 if (memory_region_present(get_system_memory(), addr)) { 774 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 775 } else { 776 dynamic_memory[5] = cpu_to_be32(0); 777 } 778 } else { 779 /* 780 * LMB information for RMA, boot time RAM and gap b/n RAM and 781 * device memory region -- all these are marked as reserved 782 * and as having no valid DRC. 783 */ 784 dynamic_memory[0] = cpu_to_be32(addr >> 32); 785 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 786 dynamic_memory[2] = cpu_to_be32(0); 787 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 788 dynamic_memory[4] = cpu_to_be32(-1); 789 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 790 SPAPR_LMB_FLAGS_DRC_INVALID); 791 } 792 793 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 794 } 795 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 796 g_free(int_buf); 797 if (ret < 0) { 798 return -1; 799 } 800 return 0; 801 } 802 803 /* 804 * Adds ibm,dynamic-reconfiguration-memory node. 805 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 806 * of this device tree node. 807 */ 808 static int spapr_populate_drconf_memory(SpaprMachineState *spapr, void *fdt) 809 { 810 MachineState *machine = MACHINE(spapr); 811 int nb_numa_nodes = machine->numa_state->num_nodes; 812 int ret, i, offset; 813 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 814 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 815 uint32_t *int_buf, *cur_index, buf_len; 816 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 817 MemoryDeviceInfoList *dimms = NULL; 818 819 /* 820 * Don't create the node if there is no device memory 821 */ 822 if (machine->ram_size == machine->maxram_size) { 823 return 0; 824 } 825 826 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 827 828 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 829 sizeof(prop_lmb_size)); 830 if (ret < 0) { 831 return ret; 832 } 833 834 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 835 if (ret < 0) { 836 return ret; 837 } 838 839 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 840 if (ret < 0) { 841 return ret; 842 } 843 844 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 845 dimms = qmp_memory_device_list(); 846 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 847 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); 848 } else { 849 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); 850 } 851 qapi_free_MemoryDeviceInfoList(dimms); 852 853 if (ret < 0) { 854 return ret; 855 } 856 857 /* ibm,associativity-lookup-arrays */ 858 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 859 cur_index = int_buf = g_malloc0(buf_len); 860 int_buf[0] = cpu_to_be32(nr_nodes); 861 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 862 cur_index += 2; 863 for (i = 0; i < nr_nodes; i++) { 864 uint32_t associativity[] = { 865 cpu_to_be32(0x0), 866 cpu_to_be32(0x0), 867 cpu_to_be32(0x0), 868 cpu_to_be32(i) 869 }; 870 memcpy(cur_index, associativity, sizeof(associativity)); 871 cur_index += 4; 872 } 873 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 874 (cur_index - int_buf) * sizeof(uint32_t)); 875 g_free(int_buf); 876 877 return ret; 878 } 879 880 static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt, 881 SpaprOptionVector *ov5_updates) 882 { 883 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 884 int ret = 0, offset; 885 886 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 887 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 888 g_assert(smc->dr_lmb_enabled); 889 ret = spapr_populate_drconf_memory(spapr, fdt); 890 if (ret) { 891 return ret; 892 } 893 } 894 895 offset = fdt_path_offset(fdt, "/chosen"); 896 if (offset < 0) { 897 offset = fdt_add_subnode(fdt, 0, "chosen"); 898 if (offset < 0) { 899 return offset; 900 } 901 } 902 return spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 903 "ibm,architecture-vec-5"); 904 } 905 906 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 907 { 908 MachineState *ms = MACHINE(spapr); 909 int rtas; 910 GString *hypertas = g_string_sized_new(256); 911 GString *qemu_hypertas = g_string_sized_new(256); 912 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 913 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 914 memory_region_size(&MACHINE(spapr)->device_memory->mr); 915 uint32_t lrdr_capacity[] = { 916 cpu_to_be32(max_device_addr >> 32), 917 cpu_to_be32(max_device_addr & 0xffffffff), 918 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 919 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 920 }; 921 uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0); 922 uint32_t maxdomains[] = { 923 cpu_to_be32(4), 924 maxdomain, 925 maxdomain, 926 maxdomain, 927 cpu_to_be32(spapr->gpu_numa_id), 928 }; 929 930 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 931 932 /* hypertas */ 933 add_str(hypertas, "hcall-pft"); 934 add_str(hypertas, "hcall-term"); 935 add_str(hypertas, "hcall-dabr"); 936 add_str(hypertas, "hcall-interrupt"); 937 add_str(hypertas, "hcall-tce"); 938 add_str(hypertas, "hcall-vio"); 939 add_str(hypertas, "hcall-splpar"); 940 add_str(hypertas, "hcall-join"); 941 add_str(hypertas, "hcall-bulk"); 942 add_str(hypertas, "hcall-set-mode"); 943 add_str(hypertas, "hcall-sprg0"); 944 add_str(hypertas, "hcall-copy"); 945 add_str(hypertas, "hcall-debug"); 946 add_str(hypertas, "hcall-vphn"); 947 add_str(qemu_hypertas, "hcall-memop1"); 948 949 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 950 add_str(hypertas, "hcall-multi-tce"); 951 } 952 953 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 954 add_str(hypertas, "hcall-hpt-resize"); 955 } 956 957 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 958 hypertas->str, hypertas->len)); 959 g_string_free(hypertas, TRUE); 960 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 961 qemu_hypertas->str, qemu_hypertas->len)); 962 g_string_free(qemu_hypertas, TRUE); 963 964 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 965 refpoints, sizeof(refpoints))); 966 967 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 968 maxdomains, sizeof(maxdomains))); 969 970 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 971 RTAS_ERROR_LOG_MAX)); 972 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 973 RTAS_EVENT_SCAN_RATE)); 974 975 g_assert(msi_nonbroken); 976 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 977 978 /* 979 * According to PAPR, rtas ibm,os-term does not guarantee a return 980 * back to the guest cpu. 981 * 982 * While an additional ibm,extended-os-term property indicates 983 * that rtas call return will always occur. Set this property. 984 */ 985 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 986 987 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 988 lrdr_capacity, sizeof(lrdr_capacity))); 989 990 spapr_dt_rtas_tokens(fdt, rtas); 991 } 992 993 /* 994 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 995 * and the XIVE features that the guest may request and thus the valid 996 * values for bytes 23..26 of option vector 5: 997 */ 998 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 999 int chosen) 1000 { 1001 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1002 1003 char val[2 * 4] = { 1004 23, 0x00, /* XICS / XIVE mode */ 1005 24, 0x00, /* Hash/Radix, filled in below. */ 1006 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1007 26, 0x40, /* Radix options: GTSE == yes. */ 1008 }; 1009 1010 if (spapr->irq->xics && spapr->irq->xive) { 1011 val[1] = SPAPR_OV5_XIVE_BOTH; 1012 } else if (spapr->irq->xive) { 1013 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 1014 } else { 1015 assert(spapr->irq->xics); 1016 val[1] = SPAPR_OV5_XIVE_LEGACY; 1017 } 1018 1019 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1020 first_ppc_cpu->compat_pvr)) { 1021 /* 1022 * If we're in a pre POWER9 compat mode then the guest should 1023 * do hash and use the legacy interrupt mode 1024 */ 1025 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 1026 val[3] = 0x00; /* Hash */ 1027 } else if (kvm_enabled()) { 1028 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1029 val[3] = 0x80; /* OV5_MMU_BOTH */ 1030 } else if (kvmppc_has_cap_mmu_radix()) { 1031 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1032 } else { 1033 val[3] = 0x00; /* Hash */ 1034 } 1035 } else { 1036 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1037 val[3] = 0xC0; 1038 } 1039 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1040 val, sizeof(val))); 1041 } 1042 1043 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt) 1044 { 1045 MachineState *machine = MACHINE(spapr); 1046 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1047 int chosen; 1048 const char *boot_device = machine->boot_order; 1049 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1050 size_t cb = 0; 1051 char *bootlist = get_boot_devices_list(&cb); 1052 1053 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1054 1055 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1056 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1057 machine->kernel_cmdline)); 1058 } 1059 if (spapr->initrd_size) { 1060 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1061 spapr->initrd_base)); 1062 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1063 spapr->initrd_base + spapr->initrd_size)); 1064 } 1065 1066 if (spapr->kernel_size) { 1067 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 1068 cpu_to_be64(spapr->kernel_size) }; 1069 1070 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1071 &kprop, sizeof(kprop))); 1072 if (spapr->kernel_le) { 1073 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1074 } 1075 } 1076 if (boot_menu) { 1077 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1078 } 1079 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1080 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1081 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1082 1083 if (cb && bootlist) { 1084 int i; 1085 1086 for (i = 0; i < cb; i++) { 1087 if (bootlist[i] == '\n') { 1088 bootlist[i] = ' '; 1089 } 1090 } 1091 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1092 } 1093 1094 if (boot_device && strlen(boot_device)) { 1095 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1096 } 1097 1098 if (!spapr->has_graphics && stdout_path) { 1099 /* 1100 * "linux,stdout-path" and "stdout" properties are deprecated by linux 1101 * kernel. New platforms should only use the "stdout-path" property. Set 1102 * the new property and continue using older property to remain 1103 * compatible with the existing firmware. 1104 */ 1105 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1106 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1107 } 1108 1109 /* We can deal with BAR reallocation just fine, advertise it to the guest */ 1110 if (smc->linux_pci_probe) { 1111 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1112 } 1113 1114 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1115 1116 g_free(stdout_path); 1117 g_free(bootlist); 1118 } 1119 1120 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1121 { 1122 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1123 * KVM to work under pHyp with some guest co-operation */ 1124 int hypervisor; 1125 uint8_t hypercall[16]; 1126 1127 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1128 /* indicate KVM hypercall interface */ 1129 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1130 if (kvmppc_has_cap_fixup_hcalls()) { 1131 /* 1132 * Older KVM versions with older guest kernels were broken 1133 * with the magic page, don't allow the guest to map it. 1134 */ 1135 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1136 sizeof(hypercall))) { 1137 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1138 hypercall, sizeof(hypercall))); 1139 } 1140 } 1141 } 1142 1143 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1144 { 1145 MachineState *machine = MACHINE(spapr); 1146 MachineClass *mc = MACHINE_GET_CLASS(machine); 1147 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1148 int ret; 1149 void *fdt; 1150 SpaprPhbState *phb; 1151 char *buf; 1152 1153 fdt = g_malloc0(space); 1154 _FDT((fdt_create_empty_tree(fdt, space))); 1155 1156 /* Root node */ 1157 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1158 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1159 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1160 1161 /* Guest UUID & Name*/ 1162 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1163 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1164 if (qemu_uuid_set) { 1165 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1166 } 1167 g_free(buf); 1168 1169 if (qemu_get_vm_name()) { 1170 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1171 qemu_get_vm_name())); 1172 } 1173 1174 /* Host Model & Serial Number */ 1175 if (spapr->host_model) { 1176 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1177 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1178 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1179 g_free(buf); 1180 } 1181 1182 if (spapr->host_serial) { 1183 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1184 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1185 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1186 g_free(buf); 1187 } 1188 1189 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1190 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1191 1192 /* /interrupt controller */ 1193 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1194 1195 ret = spapr_populate_memory(spapr, fdt); 1196 if (ret < 0) { 1197 error_report("couldn't setup memory nodes in fdt"); 1198 exit(1); 1199 } 1200 1201 /* /vdevice */ 1202 spapr_dt_vdevice(spapr->vio_bus, fdt); 1203 1204 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1205 ret = spapr_rng_populate_dt(fdt); 1206 if (ret < 0) { 1207 error_report("could not set up rng device in the fdt"); 1208 exit(1); 1209 } 1210 } 1211 1212 QLIST_FOREACH(phb, &spapr->phbs, list) { 1213 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1214 if (ret < 0) { 1215 error_report("couldn't setup PCI devices in fdt"); 1216 exit(1); 1217 } 1218 } 1219 1220 /* cpus */ 1221 spapr_populate_cpus_dt_node(fdt, spapr); 1222 1223 if (smc->dr_lmb_enabled) { 1224 _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1225 } 1226 1227 if (mc->has_hotpluggable_cpus) { 1228 int offset = fdt_path_offset(fdt, "/cpus"); 1229 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1230 if (ret < 0) { 1231 error_report("Couldn't set up CPU DR device tree properties"); 1232 exit(1); 1233 } 1234 } 1235 1236 /* /event-sources */ 1237 spapr_dt_events(spapr, fdt); 1238 1239 /* /rtas */ 1240 spapr_dt_rtas(spapr, fdt); 1241 1242 /* /chosen */ 1243 if (reset) { 1244 spapr_dt_chosen(spapr, fdt); 1245 } 1246 1247 /* /hypervisor */ 1248 if (kvm_enabled()) { 1249 spapr_dt_hypervisor(spapr, fdt); 1250 } 1251 1252 /* Build memory reserve map */ 1253 if (reset) { 1254 if (spapr->kernel_size) { 1255 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1256 } 1257 if (spapr->initrd_size) { 1258 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1259 spapr->initrd_size))); 1260 } 1261 } 1262 1263 /* ibm,client-architecture-support updates */ 1264 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1265 if (ret < 0) { 1266 error_report("couldn't setup CAS properties fdt"); 1267 exit(1); 1268 } 1269 1270 if (smc->dr_phb_enabled) { 1271 ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB); 1272 if (ret < 0) { 1273 error_report("Couldn't set up PHB DR device tree properties"); 1274 exit(1); 1275 } 1276 } 1277 1278 /* NVDIMM devices */ 1279 if (mc->nvdimm_supported) { 1280 spapr_dt_persistent_memory(fdt); 1281 } 1282 1283 return fdt; 1284 } 1285 1286 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1287 { 1288 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1289 } 1290 1291 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1292 PowerPCCPU *cpu) 1293 { 1294 CPUPPCState *env = &cpu->env; 1295 1296 /* The TCG path should also be holding the BQL at this point */ 1297 g_assert(qemu_mutex_iothread_locked()); 1298 1299 if (msr_pr) { 1300 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1301 env->gpr[3] = H_PRIVILEGE; 1302 } else { 1303 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1304 } 1305 } 1306 1307 struct LPCRSyncState { 1308 target_ulong value; 1309 target_ulong mask; 1310 }; 1311 1312 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1313 { 1314 struct LPCRSyncState *s = arg.host_ptr; 1315 PowerPCCPU *cpu = POWERPC_CPU(cs); 1316 CPUPPCState *env = &cpu->env; 1317 target_ulong lpcr; 1318 1319 cpu_synchronize_state(cs); 1320 lpcr = env->spr[SPR_LPCR]; 1321 lpcr &= ~s->mask; 1322 lpcr |= s->value; 1323 ppc_store_lpcr(cpu, lpcr); 1324 } 1325 1326 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1327 { 1328 CPUState *cs; 1329 struct LPCRSyncState s = { 1330 .value = value, 1331 .mask = mask 1332 }; 1333 CPU_FOREACH(cs) { 1334 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1335 } 1336 } 1337 1338 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1339 { 1340 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1341 1342 /* Copy PATE1:GR into PATE0:HR */ 1343 entry->dw0 = spapr->patb_entry & PATE0_HR; 1344 entry->dw1 = spapr->patb_entry; 1345 } 1346 1347 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1348 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1349 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1350 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1351 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1352 1353 /* 1354 * Get the fd to access the kernel htab, re-opening it if necessary 1355 */ 1356 static int get_htab_fd(SpaprMachineState *spapr) 1357 { 1358 Error *local_err = NULL; 1359 1360 if (spapr->htab_fd >= 0) { 1361 return spapr->htab_fd; 1362 } 1363 1364 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1365 if (spapr->htab_fd < 0) { 1366 error_report_err(local_err); 1367 } 1368 1369 return spapr->htab_fd; 1370 } 1371 1372 void close_htab_fd(SpaprMachineState *spapr) 1373 { 1374 if (spapr->htab_fd >= 0) { 1375 close(spapr->htab_fd); 1376 } 1377 spapr->htab_fd = -1; 1378 } 1379 1380 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1381 { 1382 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1383 1384 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1385 } 1386 1387 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1388 { 1389 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1390 1391 assert(kvm_enabled()); 1392 1393 if (!spapr->htab) { 1394 return 0; 1395 } 1396 1397 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1398 } 1399 1400 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1401 hwaddr ptex, int n) 1402 { 1403 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1404 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1405 1406 if (!spapr->htab) { 1407 /* 1408 * HTAB is controlled by KVM. Fetch into temporary buffer 1409 */ 1410 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1411 kvmppc_read_hptes(hptes, ptex, n); 1412 return hptes; 1413 } 1414 1415 /* 1416 * HTAB is controlled by QEMU. Just point to the internally 1417 * accessible PTEG. 1418 */ 1419 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1420 } 1421 1422 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1423 const ppc_hash_pte64_t *hptes, 1424 hwaddr ptex, int n) 1425 { 1426 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1427 1428 if (!spapr->htab) { 1429 g_free((void *)hptes); 1430 } 1431 1432 /* Nothing to do for qemu managed HPT */ 1433 } 1434 1435 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1436 uint64_t pte0, uint64_t pte1) 1437 { 1438 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1439 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1440 1441 if (!spapr->htab) { 1442 kvmppc_write_hpte(ptex, pte0, pte1); 1443 } else { 1444 if (pte0 & HPTE64_V_VALID) { 1445 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1446 /* 1447 * When setting valid, we write PTE1 first. This ensures 1448 * proper synchronization with the reading code in 1449 * ppc_hash64_pteg_search() 1450 */ 1451 smp_wmb(); 1452 stq_p(spapr->htab + offset, pte0); 1453 } else { 1454 stq_p(spapr->htab + offset, pte0); 1455 /* 1456 * When clearing it we set PTE0 first. This ensures proper 1457 * synchronization with the reading code in 1458 * ppc_hash64_pteg_search() 1459 */ 1460 smp_wmb(); 1461 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1462 } 1463 } 1464 } 1465 1466 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1467 uint64_t pte1) 1468 { 1469 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1470 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1471 1472 if (!spapr->htab) { 1473 /* There should always be a hash table when this is called */ 1474 error_report("spapr_hpte_set_c called with no hash table !"); 1475 return; 1476 } 1477 1478 /* The HW performs a non-atomic byte update */ 1479 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1480 } 1481 1482 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1483 uint64_t pte1) 1484 { 1485 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1486 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1487 1488 if (!spapr->htab) { 1489 /* There should always be a hash table when this is called */ 1490 error_report("spapr_hpte_set_r called with no hash table !"); 1491 return; 1492 } 1493 1494 /* The HW performs a non-atomic byte update */ 1495 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1496 } 1497 1498 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1499 { 1500 int shift; 1501 1502 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1503 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1504 * that's much more than is needed for Linux guests */ 1505 shift = ctz64(pow2ceil(ramsize)) - 7; 1506 shift = MAX(shift, 18); /* Minimum architected size */ 1507 shift = MIN(shift, 46); /* Maximum architected size */ 1508 return shift; 1509 } 1510 1511 void spapr_free_hpt(SpaprMachineState *spapr) 1512 { 1513 g_free(spapr->htab); 1514 spapr->htab = NULL; 1515 spapr->htab_shift = 0; 1516 close_htab_fd(spapr); 1517 } 1518 1519 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 1520 Error **errp) 1521 { 1522 long rc; 1523 1524 /* Clean up any HPT info from a previous boot */ 1525 spapr_free_hpt(spapr); 1526 1527 rc = kvmppc_reset_htab(shift); 1528 if (rc < 0) { 1529 /* kernel-side HPT needed, but couldn't allocate one */ 1530 error_setg_errno(errp, errno, 1531 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1532 shift); 1533 /* This is almost certainly fatal, but if the caller really 1534 * wants to carry on with shift == 0, it's welcome to try */ 1535 } else if (rc > 0) { 1536 /* kernel-side HPT allocated */ 1537 if (rc != shift) { 1538 error_setg(errp, 1539 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1540 shift, rc); 1541 } 1542 1543 spapr->htab_shift = shift; 1544 spapr->htab = NULL; 1545 } else { 1546 /* kernel-side HPT not needed, allocate in userspace instead */ 1547 size_t size = 1ULL << shift; 1548 int i; 1549 1550 spapr->htab = qemu_memalign(size, size); 1551 if (!spapr->htab) { 1552 error_setg_errno(errp, errno, 1553 "Could not allocate HPT of order %d", shift); 1554 return; 1555 } 1556 1557 memset(spapr->htab, 0, size); 1558 spapr->htab_shift = shift; 1559 1560 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1561 DIRTY_HPTE(HPTE(spapr->htab, i)); 1562 } 1563 } 1564 /* We're setting up a hash table, so that means we're not radix */ 1565 spapr->patb_entry = 0; 1566 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1567 } 1568 1569 void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr) 1570 { 1571 int hpt_shift; 1572 1573 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1574 || (spapr->cas_reboot 1575 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1576 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1577 } else { 1578 uint64_t current_ram_size; 1579 1580 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1581 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1582 } 1583 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1584 1585 if (spapr->vrma_adjust) { 1586 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), 1587 spapr->htab_shift); 1588 } 1589 } 1590 1591 static int spapr_reset_drcs(Object *child, void *opaque) 1592 { 1593 SpaprDrc *drc = 1594 (SpaprDrc *) object_dynamic_cast(child, 1595 TYPE_SPAPR_DR_CONNECTOR); 1596 1597 if (drc) { 1598 spapr_drc_reset(drc); 1599 } 1600 1601 return 0; 1602 } 1603 1604 static void spapr_machine_reset(MachineState *machine) 1605 { 1606 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1607 PowerPCCPU *first_ppc_cpu; 1608 hwaddr fdt_addr; 1609 void *fdt; 1610 int rc; 1611 1612 kvmppc_svm_off(&error_fatal); 1613 spapr_caps_apply(spapr); 1614 1615 first_ppc_cpu = POWERPC_CPU(first_cpu); 1616 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1617 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1618 spapr->max_compat_pvr)) { 1619 /* 1620 * If using KVM with radix mode available, VCPUs can be started 1621 * without a HPT because KVM will start them in radix mode. 1622 * Set the GR bit in PATE so that we know there is no HPT. 1623 */ 1624 spapr->patb_entry = PATE1_GR; 1625 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1626 } else { 1627 spapr_setup_hpt_and_vrma(spapr); 1628 } 1629 1630 qemu_devices_reset(); 1631 1632 /* 1633 * If this reset wasn't generated by CAS, we should reset our 1634 * negotiated options and start from scratch 1635 */ 1636 if (!spapr->cas_reboot) { 1637 spapr_ovec_cleanup(spapr->ov5_cas); 1638 spapr->ov5_cas = spapr_ovec_new(); 1639 1640 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1641 } 1642 1643 /* 1644 * This is fixing some of the default configuration of the XIVE 1645 * devices. To be called after the reset of the machine devices. 1646 */ 1647 spapr_irq_reset(spapr, &error_fatal); 1648 1649 /* 1650 * There is no CAS under qtest. Simulate one to please the code that 1651 * depends on spapr->ov5_cas. This is especially needed to test device 1652 * unplug, so we do that before resetting the DRCs. 1653 */ 1654 if (qtest_enabled()) { 1655 spapr_ovec_cleanup(spapr->ov5_cas); 1656 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1657 } 1658 1659 /* DRC reset may cause a device to be unplugged. This will cause troubles 1660 * if this device is used by another device (eg, a running vhost backend 1661 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1662 * situations, we reset DRCs after all devices have been reset. 1663 */ 1664 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1665 1666 spapr_clear_pending_events(spapr); 1667 1668 /* 1669 * We place the device tree and RTAS just below either the top of the RMA, 1670 * or just below 2GB, whichever is lower, so that it can be 1671 * processed with 32-bit real mode code if necessary 1672 */ 1673 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; 1674 1675 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1676 1677 rc = fdt_pack(fdt); 1678 1679 /* Should only fail if we've built a corrupted tree */ 1680 assert(rc == 0); 1681 1682 /* Load the fdt */ 1683 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1684 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1685 g_free(spapr->fdt_blob); 1686 spapr->fdt_size = fdt_totalsize(fdt); 1687 spapr->fdt_initial_size = spapr->fdt_size; 1688 spapr->fdt_blob = fdt; 1689 1690 /* Set up the entry state */ 1691 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); 1692 first_ppc_cpu->env.gpr[5] = 0; 1693 1694 spapr->cas_reboot = false; 1695 1696 spapr->mc_status = -1; 1697 spapr->guest_machine_check_addr = -1; 1698 1699 /* Signal all vCPUs waiting on this condition */ 1700 qemu_cond_broadcast(&spapr->mc_delivery_cond); 1701 1702 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1703 } 1704 1705 static void spapr_create_nvram(SpaprMachineState *spapr) 1706 { 1707 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1708 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1709 1710 if (dinfo) { 1711 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1712 &error_fatal); 1713 } 1714 1715 qdev_init_nofail(dev); 1716 1717 spapr->nvram = (struct SpaprNvram *)dev; 1718 } 1719 1720 static void spapr_rtc_create(SpaprMachineState *spapr) 1721 { 1722 object_initialize_child(OBJECT(spapr), "rtc", 1723 &spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1724 &error_fatal, NULL); 1725 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1726 &error_fatal); 1727 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1728 "date", &error_fatal); 1729 } 1730 1731 /* Returns whether we want to use VGA or not */ 1732 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1733 { 1734 switch (vga_interface_type) { 1735 case VGA_NONE: 1736 return false; 1737 case VGA_DEVICE: 1738 return true; 1739 case VGA_STD: 1740 case VGA_VIRTIO: 1741 case VGA_CIRRUS: 1742 return pci_vga_init(pci_bus) != NULL; 1743 default: 1744 error_setg(errp, 1745 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1746 return false; 1747 } 1748 } 1749 1750 static int spapr_pre_load(void *opaque) 1751 { 1752 int rc; 1753 1754 rc = spapr_caps_pre_load(opaque); 1755 if (rc) { 1756 return rc; 1757 } 1758 1759 return 0; 1760 } 1761 1762 static int spapr_post_load(void *opaque, int version_id) 1763 { 1764 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1765 int err = 0; 1766 1767 err = spapr_caps_post_migration(spapr); 1768 if (err) { 1769 return err; 1770 } 1771 1772 /* 1773 * In earlier versions, there was no separate qdev for the PAPR 1774 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1775 * So when migrating from those versions, poke the incoming offset 1776 * value into the RTC device 1777 */ 1778 if (version_id < 3) { 1779 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1780 if (err) { 1781 return err; 1782 } 1783 } 1784 1785 if (kvm_enabled() && spapr->patb_entry) { 1786 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1787 bool radix = !!(spapr->patb_entry & PATE1_GR); 1788 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1789 1790 /* 1791 * Update LPCR:HR and UPRT as they may not be set properly in 1792 * the stream 1793 */ 1794 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1795 LPCR_HR | LPCR_UPRT); 1796 1797 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1798 if (err) { 1799 error_report("Process table config unsupported by the host"); 1800 return -EINVAL; 1801 } 1802 } 1803 1804 err = spapr_irq_post_load(spapr, version_id); 1805 if (err) { 1806 return err; 1807 } 1808 1809 return err; 1810 } 1811 1812 static int spapr_pre_save(void *opaque) 1813 { 1814 int rc; 1815 1816 rc = spapr_caps_pre_save(opaque); 1817 if (rc) { 1818 return rc; 1819 } 1820 1821 return 0; 1822 } 1823 1824 static bool version_before_3(void *opaque, int version_id) 1825 { 1826 return version_id < 3; 1827 } 1828 1829 static bool spapr_pending_events_needed(void *opaque) 1830 { 1831 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1832 return !QTAILQ_EMPTY(&spapr->pending_events); 1833 } 1834 1835 static const VMStateDescription vmstate_spapr_event_entry = { 1836 .name = "spapr_event_log_entry", 1837 .version_id = 1, 1838 .minimum_version_id = 1, 1839 .fields = (VMStateField[]) { 1840 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1841 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1842 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1843 NULL, extended_length), 1844 VMSTATE_END_OF_LIST() 1845 }, 1846 }; 1847 1848 static const VMStateDescription vmstate_spapr_pending_events = { 1849 .name = "spapr_pending_events", 1850 .version_id = 1, 1851 .minimum_version_id = 1, 1852 .needed = spapr_pending_events_needed, 1853 .fields = (VMStateField[]) { 1854 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1855 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1856 VMSTATE_END_OF_LIST() 1857 }, 1858 }; 1859 1860 static bool spapr_ov5_cas_needed(void *opaque) 1861 { 1862 SpaprMachineState *spapr = opaque; 1863 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1864 bool cas_needed; 1865 1866 /* Prior to the introduction of SpaprOptionVector, we had two option 1867 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1868 * Both of these options encode machine topology into the device-tree 1869 * in such a way that the now-booted OS should still be able to interact 1870 * appropriately with QEMU regardless of what options were actually 1871 * negotiatied on the source side. 1872 * 1873 * As such, we can avoid migrating the CAS-negotiated options if these 1874 * are the only options available on the current machine/platform. 1875 * Since these are the only options available for pseries-2.7 and 1876 * earlier, this allows us to maintain old->new/new->old migration 1877 * compatibility. 1878 * 1879 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1880 * via default pseries-2.8 machines and explicit command-line parameters. 1881 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1882 * of the actual CAS-negotiated values to continue working properly. For 1883 * example, availability of memory unplug depends on knowing whether 1884 * OV5_HP_EVT was negotiated via CAS. 1885 * 1886 * Thus, for any cases where the set of available CAS-negotiatable 1887 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1888 * include the CAS-negotiated options in the migration stream, unless 1889 * if they affect boot time behaviour only. 1890 */ 1891 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1892 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1893 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1894 1895 /* We need extra information if we have any bits outside the mask 1896 * defined above */ 1897 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1898 1899 spapr_ovec_cleanup(ov5_mask); 1900 1901 return cas_needed; 1902 } 1903 1904 static const VMStateDescription vmstate_spapr_ov5_cas = { 1905 .name = "spapr_option_vector_ov5_cas", 1906 .version_id = 1, 1907 .minimum_version_id = 1, 1908 .needed = spapr_ov5_cas_needed, 1909 .fields = (VMStateField[]) { 1910 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1911 vmstate_spapr_ovec, SpaprOptionVector), 1912 VMSTATE_END_OF_LIST() 1913 }, 1914 }; 1915 1916 static bool spapr_patb_entry_needed(void *opaque) 1917 { 1918 SpaprMachineState *spapr = opaque; 1919 1920 return !!spapr->patb_entry; 1921 } 1922 1923 static const VMStateDescription vmstate_spapr_patb_entry = { 1924 .name = "spapr_patb_entry", 1925 .version_id = 1, 1926 .minimum_version_id = 1, 1927 .needed = spapr_patb_entry_needed, 1928 .fields = (VMStateField[]) { 1929 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1930 VMSTATE_END_OF_LIST() 1931 }, 1932 }; 1933 1934 static bool spapr_irq_map_needed(void *opaque) 1935 { 1936 SpaprMachineState *spapr = opaque; 1937 1938 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1939 } 1940 1941 static const VMStateDescription vmstate_spapr_irq_map = { 1942 .name = "spapr_irq_map", 1943 .version_id = 1, 1944 .minimum_version_id = 1, 1945 .needed = spapr_irq_map_needed, 1946 .fields = (VMStateField[]) { 1947 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1948 VMSTATE_END_OF_LIST() 1949 }, 1950 }; 1951 1952 static bool spapr_dtb_needed(void *opaque) 1953 { 1954 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1955 1956 return smc->update_dt_enabled; 1957 } 1958 1959 static int spapr_dtb_pre_load(void *opaque) 1960 { 1961 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1962 1963 g_free(spapr->fdt_blob); 1964 spapr->fdt_blob = NULL; 1965 spapr->fdt_size = 0; 1966 1967 return 0; 1968 } 1969 1970 static const VMStateDescription vmstate_spapr_dtb = { 1971 .name = "spapr_dtb", 1972 .version_id = 1, 1973 .minimum_version_id = 1, 1974 .needed = spapr_dtb_needed, 1975 .pre_load = spapr_dtb_pre_load, 1976 .fields = (VMStateField[]) { 1977 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1978 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1979 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1980 fdt_size), 1981 VMSTATE_END_OF_LIST() 1982 }, 1983 }; 1984 1985 static bool spapr_fwnmi_needed(void *opaque) 1986 { 1987 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1988 1989 return spapr->guest_machine_check_addr != -1; 1990 } 1991 1992 static int spapr_fwnmi_pre_save(void *opaque) 1993 { 1994 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1995 1996 /* 1997 * Check if machine check handling is in progress and print a 1998 * warning message. 1999 */ 2000 if (spapr->mc_status != -1) { 2001 warn_report("A machine check is being handled during migration. The" 2002 "handler may run and log hardware error on the destination"); 2003 } 2004 2005 return 0; 2006 } 2007 2008 static const VMStateDescription vmstate_spapr_machine_check = { 2009 .name = "spapr_machine_check", 2010 .version_id = 1, 2011 .minimum_version_id = 1, 2012 .needed = spapr_fwnmi_needed, 2013 .pre_save = spapr_fwnmi_pre_save, 2014 .fields = (VMStateField[]) { 2015 VMSTATE_UINT64(guest_machine_check_addr, SpaprMachineState), 2016 VMSTATE_INT32(mc_status, SpaprMachineState), 2017 VMSTATE_END_OF_LIST() 2018 }, 2019 }; 2020 2021 static const VMStateDescription vmstate_spapr = { 2022 .name = "spapr", 2023 .version_id = 3, 2024 .minimum_version_id = 1, 2025 .pre_load = spapr_pre_load, 2026 .post_load = spapr_post_load, 2027 .pre_save = spapr_pre_save, 2028 .fields = (VMStateField[]) { 2029 /* used to be @next_irq */ 2030 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2031 2032 /* RTC offset */ 2033 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2034 2035 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2036 VMSTATE_END_OF_LIST() 2037 }, 2038 .subsections = (const VMStateDescription*[]) { 2039 &vmstate_spapr_ov5_cas, 2040 &vmstate_spapr_patb_entry, 2041 &vmstate_spapr_pending_events, 2042 &vmstate_spapr_cap_htm, 2043 &vmstate_spapr_cap_vsx, 2044 &vmstate_spapr_cap_dfp, 2045 &vmstate_spapr_cap_cfpc, 2046 &vmstate_spapr_cap_sbbc, 2047 &vmstate_spapr_cap_ibs, 2048 &vmstate_spapr_cap_hpt_maxpagesize, 2049 &vmstate_spapr_irq_map, 2050 &vmstate_spapr_cap_nested_kvm_hv, 2051 &vmstate_spapr_dtb, 2052 &vmstate_spapr_cap_large_decr, 2053 &vmstate_spapr_cap_ccf_assist, 2054 &vmstate_spapr_cap_fwnmi, 2055 &vmstate_spapr_machine_check, 2056 NULL 2057 } 2058 }; 2059 2060 static int htab_save_setup(QEMUFile *f, void *opaque) 2061 { 2062 SpaprMachineState *spapr = opaque; 2063 2064 /* "Iteration" header */ 2065 if (!spapr->htab_shift) { 2066 qemu_put_be32(f, -1); 2067 } else { 2068 qemu_put_be32(f, spapr->htab_shift); 2069 } 2070 2071 if (spapr->htab) { 2072 spapr->htab_save_index = 0; 2073 spapr->htab_first_pass = true; 2074 } else { 2075 if (spapr->htab_shift) { 2076 assert(kvm_enabled()); 2077 } 2078 } 2079 2080 2081 return 0; 2082 } 2083 2084 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2085 int chunkstart, int n_valid, int n_invalid) 2086 { 2087 qemu_put_be32(f, chunkstart); 2088 qemu_put_be16(f, n_valid); 2089 qemu_put_be16(f, n_invalid); 2090 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2091 HASH_PTE_SIZE_64 * n_valid); 2092 } 2093 2094 static void htab_save_end_marker(QEMUFile *f) 2095 { 2096 qemu_put_be32(f, 0); 2097 qemu_put_be16(f, 0); 2098 qemu_put_be16(f, 0); 2099 } 2100 2101 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2102 int64_t max_ns) 2103 { 2104 bool has_timeout = max_ns != -1; 2105 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2106 int index = spapr->htab_save_index; 2107 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2108 2109 assert(spapr->htab_first_pass); 2110 2111 do { 2112 int chunkstart; 2113 2114 /* Consume invalid HPTEs */ 2115 while ((index < htabslots) 2116 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2117 CLEAN_HPTE(HPTE(spapr->htab, index)); 2118 index++; 2119 } 2120 2121 /* Consume valid HPTEs */ 2122 chunkstart = index; 2123 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2124 && HPTE_VALID(HPTE(spapr->htab, index))) { 2125 CLEAN_HPTE(HPTE(spapr->htab, index)); 2126 index++; 2127 } 2128 2129 if (index > chunkstart) { 2130 int n_valid = index - chunkstart; 2131 2132 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2133 2134 if (has_timeout && 2135 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2136 break; 2137 } 2138 } 2139 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2140 2141 if (index >= htabslots) { 2142 assert(index == htabslots); 2143 index = 0; 2144 spapr->htab_first_pass = false; 2145 } 2146 spapr->htab_save_index = index; 2147 } 2148 2149 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2150 int64_t max_ns) 2151 { 2152 bool final = max_ns < 0; 2153 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2154 int examined = 0, sent = 0; 2155 int index = spapr->htab_save_index; 2156 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2157 2158 assert(!spapr->htab_first_pass); 2159 2160 do { 2161 int chunkstart, invalidstart; 2162 2163 /* Consume non-dirty HPTEs */ 2164 while ((index < htabslots) 2165 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2166 index++; 2167 examined++; 2168 } 2169 2170 chunkstart = index; 2171 /* Consume valid dirty HPTEs */ 2172 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2173 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2174 && HPTE_VALID(HPTE(spapr->htab, index))) { 2175 CLEAN_HPTE(HPTE(spapr->htab, index)); 2176 index++; 2177 examined++; 2178 } 2179 2180 invalidstart = index; 2181 /* Consume invalid dirty HPTEs */ 2182 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2183 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2184 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2185 CLEAN_HPTE(HPTE(spapr->htab, index)); 2186 index++; 2187 examined++; 2188 } 2189 2190 if (index > chunkstart) { 2191 int n_valid = invalidstart - chunkstart; 2192 int n_invalid = index - invalidstart; 2193 2194 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2195 sent += index - chunkstart; 2196 2197 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2198 break; 2199 } 2200 } 2201 2202 if (examined >= htabslots) { 2203 break; 2204 } 2205 2206 if (index >= htabslots) { 2207 assert(index == htabslots); 2208 index = 0; 2209 } 2210 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2211 2212 if (index >= htabslots) { 2213 assert(index == htabslots); 2214 index = 0; 2215 } 2216 2217 spapr->htab_save_index = index; 2218 2219 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2220 } 2221 2222 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2223 #define MAX_KVM_BUF_SIZE 2048 2224 2225 static int htab_save_iterate(QEMUFile *f, void *opaque) 2226 { 2227 SpaprMachineState *spapr = opaque; 2228 int fd; 2229 int rc = 0; 2230 2231 /* Iteration header */ 2232 if (!spapr->htab_shift) { 2233 qemu_put_be32(f, -1); 2234 return 1; 2235 } else { 2236 qemu_put_be32(f, 0); 2237 } 2238 2239 if (!spapr->htab) { 2240 assert(kvm_enabled()); 2241 2242 fd = get_htab_fd(spapr); 2243 if (fd < 0) { 2244 return fd; 2245 } 2246 2247 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2248 if (rc < 0) { 2249 return rc; 2250 } 2251 } else if (spapr->htab_first_pass) { 2252 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2253 } else { 2254 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2255 } 2256 2257 htab_save_end_marker(f); 2258 2259 return rc; 2260 } 2261 2262 static int htab_save_complete(QEMUFile *f, void *opaque) 2263 { 2264 SpaprMachineState *spapr = opaque; 2265 int fd; 2266 2267 /* Iteration header */ 2268 if (!spapr->htab_shift) { 2269 qemu_put_be32(f, -1); 2270 return 0; 2271 } else { 2272 qemu_put_be32(f, 0); 2273 } 2274 2275 if (!spapr->htab) { 2276 int rc; 2277 2278 assert(kvm_enabled()); 2279 2280 fd = get_htab_fd(spapr); 2281 if (fd < 0) { 2282 return fd; 2283 } 2284 2285 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2286 if (rc < 0) { 2287 return rc; 2288 } 2289 } else { 2290 if (spapr->htab_first_pass) { 2291 htab_save_first_pass(f, spapr, -1); 2292 } 2293 htab_save_later_pass(f, spapr, -1); 2294 } 2295 2296 /* End marker */ 2297 htab_save_end_marker(f); 2298 2299 return 0; 2300 } 2301 2302 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2303 { 2304 SpaprMachineState *spapr = opaque; 2305 uint32_t section_hdr; 2306 int fd = -1; 2307 Error *local_err = NULL; 2308 2309 if (version_id < 1 || version_id > 1) { 2310 error_report("htab_load() bad version"); 2311 return -EINVAL; 2312 } 2313 2314 section_hdr = qemu_get_be32(f); 2315 2316 if (section_hdr == -1) { 2317 spapr_free_hpt(spapr); 2318 return 0; 2319 } 2320 2321 if (section_hdr) { 2322 /* First section gives the htab size */ 2323 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2324 if (local_err) { 2325 error_report_err(local_err); 2326 return -EINVAL; 2327 } 2328 return 0; 2329 } 2330 2331 if (!spapr->htab) { 2332 assert(kvm_enabled()); 2333 2334 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2335 if (fd < 0) { 2336 error_report_err(local_err); 2337 return fd; 2338 } 2339 } 2340 2341 while (true) { 2342 uint32_t index; 2343 uint16_t n_valid, n_invalid; 2344 2345 index = qemu_get_be32(f); 2346 n_valid = qemu_get_be16(f); 2347 n_invalid = qemu_get_be16(f); 2348 2349 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2350 /* End of Stream */ 2351 break; 2352 } 2353 2354 if ((index + n_valid + n_invalid) > 2355 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2356 /* Bad index in stream */ 2357 error_report( 2358 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2359 index, n_valid, n_invalid, spapr->htab_shift); 2360 return -EINVAL; 2361 } 2362 2363 if (spapr->htab) { 2364 if (n_valid) { 2365 qemu_get_buffer(f, HPTE(spapr->htab, index), 2366 HASH_PTE_SIZE_64 * n_valid); 2367 } 2368 if (n_invalid) { 2369 memset(HPTE(spapr->htab, index + n_valid), 0, 2370 HASH_PTE_SIZE_64 * n_invalid); 2371 } 2372 } else { 2373 int rc; 2374 2375 assert(fd >= 0); 2376 2377 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2378 if (rc < 0) { 2379 return rc; 2380 } 2381 } 2382 } 2383 2384 if (!spapr->htab) { 2385 assert(fd >= 0); 2386 close(fd); 2387 } 2388 2389 return 0; 2390 } 2391 2392 static void htab_save_cleanup(void *opaque) 2393 { 2394 SpaprMachineState *spapr = opaque; 2395 2396 close_htab_fd(spapr); 2397 } 2398 2399 static SaveVMHandlers savevm_htab_handlers = { 2400 .save_setup = htab_save_setup, 2401 .save_live_iterate = htab_save_iterate, 2402 .save_live_complete_precopy = htab_save_complete, 2403 .save_cleanup = htab_save_cleanup, 2404 .load_state = htab_load, 2405 }; 2406 2407 static void spapr_boot_set(void *opaque, const char *boot_device, 2408 Error **errp) 2409 { 2410 MachineState *machine = MACHINE(opaque); 2411 machine->boot_order = g_strdup(boot_device); 2412 } 2413 2414 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2415 { 2416 MachineState *machine = MACHINE(spapr); 2417 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2418 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2419 int i; 2420 2421 for (i = 0; i < nr_lmbs; i++) { 2422 uint64_t addr; 2423 2424 addr = i * lmb_size + machine->device_memory->base; 2425 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2426 addr / lmb_size); 2427 } 2428 } 2429 2430 /* 2431 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2432 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2433 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2434 */ 2435 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2436 { 2437 int i; 2438 2439 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2440 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2441 " is not aligned to %" PRIu64 " MiB", 2442 machine->ram_size, 2443 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2444 return; 2445 } 2446 2447 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2448 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2449 " is not aligned to %" PRIu64 " MiB", 2450 machine->ram_size, 2451 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2452 return; 2453 } 2454 2455 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2456 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2457 error_setg(errp, 2458 "Node %d memory size 0x%" PRIx64 2459 " is not aligned to %" PRIu64 " MiB", 2460 i, machine->numa_state->nodes[i].node_mem, 2461 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2462 return; 2463 } 2464 } 2465 } 2466 2467 /* find cpu slot in machine->possible_cpus by core_id */ 2468 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2469 { 2470 int index = id / ms->smp.threads; 2471 2472 if (index >= ms->possible_cpus->len) { 2473 return NULL; 2474 } 2475 if (idx) { 2476 *idx = index; 2477 } 2478 return &ms->possible_cpus->cpus[index]; 2479 } 2480 2481 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2482 { 2483 MachineState *ms = MACHINE(spapr); 2484 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2485 Error *local_err = NULL; 2486 bool vsmt_user = !!spapr->vsmt; 2487 int kvm_smt = kvmppc_smt_threads(); 2488 int ret; 2489 unsigned int smp_threads = ms->smp.threads; 2490 2491 if (!kvm_enabled() && (smp_threads > 1)) { 2492 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2493 "on a pseries machine"); 2494 goto out; 2495 } 2496 if (!is_power_of_2(smp_threads)) { 2497 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2498 "machine because it must be a power of 2", smp_threads); 2499 goto out; 2500 } 2501 2502 /* Detemine the VSMT mode to use: */ 2503 if (vsmt_user) { 2504 if (spapr->vsmt < smp_threads) { 2505 error_setg(&local_err, "Cannot support VSMT mode %d" 2506 " because it must be >= threads/core (%d)", 2507 spapr->vsmt, smp_threads); 2508 goto out; 2509 } 2510 /* In this case, spapr->vsmt has been set by the command line */ 2511 } else if (!smc->smp_threads_vsmt) { 2512 /* 2513 * Default VSMT value is tricky, because we need it to be as 2514 * consistent as possible (for migration), but this requires 2515 * changing it for at least some existing cases. We pick 8 as 2516 * the value that we'd get with KVM on POWER8, the 2517 * overwhelmingly common case in production systems. 2518 */ 2519 spapr->vsmt = MAX(8, smp_threads); 2520 } else { 2521 spapr->vsmt = smp_threads; 2522 } 2523 2524 /* KVM: If necessary, set the SMT mode: */ 2525 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2526 ret = kvmppc_set_smt_threads(spapr->vsmt); 2527 if (ret) { 2528 /* Looks like KVM isn't able to change VSMT mode */ 2529 error_setg(&local_err, 2530 "Failed to set KVM's VSMT mode to %d (errno %d)", 2531 spapr->vsmt, ret); 2532 /* We can live with that if the default one is big enough 2533 * for the number of threads, and a submultiple of the one 2534 * we want. In this case we'll waste some vcpu ids, but 2535 * behaviour will be correct */ 2536 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2537 warn_report_err(local_err); 2538 local_err = NULL; 2539 goto out; 2540 } else { 2541 if (!vsmt_user) { 2542 error_append_hint(&local_err, 2543 "On PPC, a VM with %d threads/core" 2544 " on a host with %d threads/core" 2545 " requires the use of VSMT mode %d.\n", 2546 smp_threads, kvm_smt, spapr->vsmt); 2547 } 2548 kvmppc_error_append_smt_possible_hint(&local_err); 2549 goto out; 2550 } 2551 } 2552 } 2553 /* else TCG: nothing to do currently */ 2554 out: 2555 error_propagate(errp, local_err); 2556 } 2557 2558 static void spapr_init_cpus(SpaprMachineState *spapr) 2559 { 2560 MachineState *machine = MACHINE(spapr); 2561 MachineClass *mc = MACHINE_GET_CLASS(machine); 2562 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2563 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2564 const CPUArchIdList *possible_cpus; 2565 unsigned int smp_cpus = machine->smp.cpus; 2566 unsigned int smp_threads = machine->smp.threads; 2567 unsigned int max_cpus = machine->smp.max_cpus; 2568 int boot_cores_nr = smp_cpus / smp_threads; 2569 int i; 2570 2571 possible_cpus = mc->possible_cpu_arch_ids(machine); 2572 if (mc->has_hotpluggable_cpus) { 2573 if (smp_cpus % smp_threads) { 2574 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2575 smp_cpus, smp_threads); 2576 exit(1); 2577 } 2578 if (max_cpus % smp_threads) { 2579 error_report("max_cpus (%u) must be multiple of threads (%u)", 2580 max_cpus, smp_threads); 2581 exit(1); 2582 } 2583 } else { 2584 if (max_cpus != smp_cpus) { 2585 error_report("This machine version does not support CPU hotplug"); 2586 exit(1); 2587 } 2588 boot_cores_nr = possible_cpus->len; 2589 } 2590 2591 if (smc->pre_2_10_has_unused_icps) { 2592 int i; 2593 2594 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2595 /* Dummy entries get deregistered when real ICPState objects 2596 * are registered during CPU core hotplug. 2597 */ 2598 pre_2_10_vmstate_register_dummy_icp(i); 2599 } 2600 } 2601 2602 for (i = 0; i < possible_cpus->len; i++) { 2603 int core_id = i * smp_threads; 2604 2605 if (mc->has_hotpluggable_cpus) { 2606 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2607 spapr_vcpu_id(spapr, core_id)); 2608 } 2609 2610 if (i < boot_cores_nr) { 2611 Object *core = object_new(type); 2612 int nr_threads = smp_threads; 2613 2614 /* Handle the partially filled core for older machine types */ 2615 if ((i + 1) * smp_threads >= smp_cpus) { 2616 nr_threads = smp_cpus - i * smp_threads; 2617 } 2618 2619 object_property_set_int(core, nr_threads, "nr-threads", 2620 &error_fatal); 2621 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2622 &error_fatal); 2623 object_property_set_bool(core, true, "realized", &error_fatal); 2624 2625 object_unref(core); 2626 } 2627 } 2628 } 2629 2630 static PCIHostState *spapr_create_default_phb(void) 2631 { 2632 DeviceState *dev; 2633 2634 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); 2635 qdev_prop_set_uint32(dev, "index", 0); 2636 qdev_init_nofail(dev); 2637 2638 return PCI_HOST_BRIDGE(dev); 2639 } 2640 2641 /* pSeries LPAR / sPAPR hardware init */ 2642 static void spapr_machine_init(MachineState *machine) 2643 { 2644 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2645 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2646 MachineClass *mc = MACHINE_GET_CLASS(machine); 2647 const char *kernel_filename = machine->kernel_filename; 2648 const char *initrd_filename = machine->initrd_filename; 2649 PCIHostState *phb; 2650 int i; 2651 MemoryRegion *sysmem = get_system_memory(); 2652 MemoryRegion *ram = g_new(MemoryRegion, 1); 2653 hwaddr node0_size = spapr_node0_size(machine); 2654 long load_limit, fw_size; 2655 char *filename; 2656 Error *resize_hpt_err = NULL; 2657 2658 msi_nonbroken = true; 2659 2660 QLIST_INIT(&spapr->phbs); 2661 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2662 2663 /* Determine capabilities to run with */ 2664 spapr_caps_init(spapr); 2665 2666 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2667 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2668 /* 2669 * If the user explicitly requested a mode we should either 2670 * supply it, or fail completely (which we do below). But if 2671 * it's not set explicitly, we reset our mode to something 2672 * that works 2673 */ 2674 if (resize_hpt_err) { 2675 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2676 error_free(resize_hpt_err); 2677 resize_hpt_err = NULL; 2678 } else { 2679 spapr->resize_hpt = smc->resize_hpt_default; 2680 } 2681 } 2682 2683 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2684 2685 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2686 /* 2687 * User requested HPT resize, but this host can't supply it. Bail out 2688 */ 2689 error_report_err(resize_hpt_err); 2690 exit(1); 2691 } 2692 2693 spapr->rma_size = node0_size; 2694 2695 /* With KVM, we don't actually know whether KVM supports an 2696 * unbounded RMA (PR KVM) or is limited by the hash table size 2697 * (HV KVM using VRMA), so we always assume the latter 2698 * 2699 * In that case, we also limit the initial allocations for RTAS 2700 * etc... to 256M since we have no way to know what the VRMA size 2701 * is going to be as it depends on the size of the hash table 2702 * which isn't determined yet. 2703 */ 2704 if (kvm_enabled()) { 2705 spapr->vrma_adjust = 1; 2706 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2707 } 2708 2709 /* Actually we don't support unbounded RMA anymore since we added 2710 * proper emulation of HV mode. The max we can get is 16G which 2711 * also happens to be what we configure for PAPR mode so make sure 2712 * we don't do anything bigger than that 2713 */ 2714 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2715 2716 if (spapr->rma_size > node0_size) { 2717 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2718 spapr->rma_size); 2719 exit(1); 2720 } 2721 2722 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2723 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2724 2725 /* 2726 * VSMT must be set in order to be able to compute VCPU ids, ie to 2727 * call spapr_max_server_number() or spapr_vcpu_id(). 2728 */ 2729 spapr_set_vsmt_mode(spapr, &error_fatal); 2730 2731 /* Set up Interrupt Controller before we create the VCPUs */ 2732 spapr_irq_init(spapr, &error_fatal); 2733 2734 /* Set up containers for ibm,client-architecture-support negotiated options 2735 */ 2736 spapr->ov5 = spapr_ovec_new(); 2737 spapr->ov5_cas = spapr_ovec_new(); 2738 2739 if (smc->dr_lmb_enabled) { 2740 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2741 spapr_validate_node_memory(machine, &error_fatal); 2742 } 2743 2744 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2745 2746 /* advertise support for dedicated HP event source to guests */ 2747 if (spapr->use_hotplug_event_source) { 2748 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2749 } 2750 2751 /* advertise support for HPT resizing */ 2752 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2753 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2754 } 2755 2756 /* advertise support for ibm,dyamic-memory-v2 */ 2757 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2758 2759 /* advertise XIVE on POWER9 machines */ 2760 if (spapr->irq->xive) { 2761 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2762 } 2763 2764 /* init CPUs */ 2765 spapr_init_cpus(spapr); 2766 2767 /* 2768 * check we don't have a memory-less/cpu-less NUMA node 2769 * Firmware relies on the existing memory/cpu topology to provide the 2770 * NUMA topology to the kernel. 2771 * And the linux kernel needs to know the NUMA topology at start 2772 * to be able to hotplug CPUs later. 2773 */ 2774 if (machine->numa_state->num_nodes) { 2775 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2776 /* check for memory-less node */ 2777 if (machine->numa_state->nodes[i].node_mem == 0) { 2778 CPUState *cs; 2779 int found = 0; 2780 /* check for cpu-less node */ 2781 CPU_FOREACH(cs) { 2782 PowerPCCPU *cpu = POWERPC_CPU(cs); 2783 if (cpu->node_id == i) { 2784 found = 1; 2785 break; 2786 } 2787 } 2788 /* memory-less and cpu-less node */ 2789 if (!found) { 2790 error_report( 2791 "Memory-less/cpu-less nodes are not supported (node %d)", 2792 i); 2793 exit(1); 2794 } 2795 } 2796 } 2797 2798 } 2799 2800 /* 2801 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. 2802 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is 2803 * called from vPHB reset handler so we initialize the counter here. 2804 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM 2805 * must be equally distant from any other node. 2806 * The final value of spapr->gpu_numa_id is going to be written to 2807 * max-associativity-domains in spapr_build_fdt(). 2808 */ 2809 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes); 2810 2811 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2812 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2813 spapr->max_compat_pvr)) { 2814 /* KVM and TCG always allow GTSE with radix... */ 2815 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2816 } 2817 /* ... but not with hash (currently). */ 2818 2819 if (kvm_enabled()) { 2820 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2821 kvmppc_enable_logical_ci_hcalls(); 2822 kvmppc_enable_set_mode_hcall(); 2823 2824 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2825 kvmppc_enable_clear_ref_mod_hcalls(); 2826 2827 /* Enable H_PAGE_INIT */ 2828 kvmppc_enable_h_page_init(); 2829 } 2830 2831 /* allocate RAM */ 2832 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2833 machine->ram_size); 2834 memory_region_add_subregion(sysmem, 0, ram); 2835 2836 /* always allocate the device memory information */ 2837 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2838 2839 /* initialize hotplug memory address space */ 2840 if (machine->ram_size < machine->maxram_size) { 2841 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2842 /* 2843 * Limit the number of hotpluggable memory slots to half the number 2844 * slots that KVM supports, leaving the other half for PCI and other 2845 * devices. However ensure that number of slots doesn't drop below 32. 2846 */ 2847 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2848 SPAPR_MAX_RAM_SLOTS; 2849 2850 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2851 max_memslots = SPAPR_MAX_RAM_SLOTS; 2852 } 2853 if (machine->ram_slots > max_memslots) { 2854 error_report("Specified number of memory slots %" 2855 PRIu64" exceeds max supported %d", 2856 machine->ram_slots, max_memslots); 2857 exit(1); 2858 } 2859 2860 machine->device_memory->base = ROUND_UP(machine->ram_size, 2861 SPAPR_DEVICE_MEM_ALIGN); 2862 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2863 "device-memory", device_mem_size); 2864 memory_region_add_subregion(sysmem, machine->device_memory->base, 2865 &machine->device_memory->mr); 2866 } 2867 2868 if (smc->dr_lmb_enabled) { 2869 spapr_create_lmb_dr_connectors(spapr); 2870 } 2871 2872 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI_MCE) == SPAPR_CAP_ON) { 2873 /* Create the error string for live migration blocker */ 2874 error_setg(&spapr->fwnmi_migration_blocker, 2875 "A machine check is being handled during migration. The handler" 2876 "may run and log hardware error on the destination"); 2877 } 2878 2879 if (mc->nvdimm_supported) { 2880 spapr_create_nvdimm_dr_connectors(spapr); 2881 } 2882 2883 /* Set up RTAS event infrastructure */ 2884 spapr_events_init(spapr); 2885 2886 /* Set up the RTC RTAS interfaces */ 2887 spapr_rtc_create(spapr); 2888 2889 /* Set up VIO bus */ 2890 spapr->vio_bus = spapr_vio_bus_init(); 2891 2892 for (i = 0; i < serial_max_hds(); i++) { 2893 if (serial_hd(i)) { 2894 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2895 } 2896 } 2897 2898 /* We always have at least the nvram device on VIO */ 2899 spapr_create_nvram(spapr); 2900 2901 /* 2902 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2903 * connectors (described in root DT node's "ibm,drc-types" property) 2904 * are pre-initialized here. additional child connectors (such as 2905 * connectors for a PHBs PCI slots) are added as needed during their 2906 * parent's realization. 2907 */ 2908 if (smc->dr_phb_enabled) { 2909 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2910 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2911 } 2912 } 2913 2914 /* Set up PCI */ 2915 spapr_pci_rtas_init(); 2916 2917 phb = spapr_create_default_phb(); 2918 2919 for (i = 0; i < nb_nics; i++) { 2920 NICInfo *nd = &nd_table[i]; 2921 2922 if (!nd->model) { 2923 nd->model = g_strdup("spapr-vlan"); 2924 } 2925 2926 if (g_str_equal(nd->model, "spapr-vlan") || 2927 g_str_equal(nd->model, "ibmveth")) { 2928 spapr_vlan_create(spapr->vio_bus, nd); 2929 } else { 2930 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2931 } 2932 } 2933 2934 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2935 spapr_vscsi_create(spapr->vio_bus); 2936 } 2937 2938 /* Graphics */ 2939 if (spapr_vga_init(phb->bus, &error_fatal)) { 2940 spapr->has_graphics = true; 2941 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2942 } 2943 2944 if (machine->usb) { 2945 if (smc->use_ohci_by_default) { 2946 pci_create_simple(phb->bus, -1, "pci-ohci"); 2947 } else { 2948 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2949 } 2950 2951 if (spapr->has_graphics) { 2952 USBBus *usb_bus = usb_bus_find(-1); 2953 2954 usb_create_simple(usb_bus, "usb-kbd"); 2955 usb_create_simple(usb_bus, "usb-mouse"); 2956 } 2957 } 2958 2959 if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) { 2960 error_report( 2961 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2962 MIN_RMA_SLOF); 2963 exit(1); 2964 } 2965 2966 if (kernel_filename) { 2967 uint64_t lowaddr = 0; 2968 2969 spapr->kernel_size = load_elf(kernel_filename, NULL, 2970 translate_kernel_address, NULL, 2971 NULL, &lowaddr, NULL, NULL, 1, 2972 PPC_ELF_MACHINE, 0, 0); 2973 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2974 spapr->kernel_size = load_elf(kernel_filename, NULL, 2975 translate_kernel_address, NULL, NULL, 2976 &lowaddr, NULL, NULL, 0, 2977 PPC_ELF_MACHINE, 0, 0); 2978 spapr->kernel_le = spapr->kernel_size > 0; 2979 } 2980 if (spapr->kernel_size < 0) { 2981 error_report("error loading %s: %s", kernel_filename, 2982 load_elf_strerror(spapr->kernel_size)); 2983 exit(1); 2984 } 2985 2986 /* load initrd */ 2987 if (initrd_filename) { 2988 /* Try to locate the initrd in the gap between the kernel 2989 * and the firmware. Add a bit of space just in case 2990 */ 2991 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2992 + 0x1ffff) & ~0xffff; 2993 spapr->initrd_size = load_image_targphys(initrd_filename, 2994 spapr->initrd_base, 2995 load_limit 2996 - spapr->initrd_base); 2997 if (spapr->initrd_size < 0) { 2998 error_report("could not load initial ram disk '%s'", 2999 initrd_filename); 3000 exit(1); 3001 } 3002 } 3003 } 3004 3005 if (bios_name == NULL) { 3006 bios_name = FW_FILE_NAME; 3007 } 3008 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 3009 if (!filename) { 3010 error_report("Could not find LPAR firmware '%s'", bios_name); 3011 exit(1); 3012 } 3013 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 3014 if (fw_size <= 0) { 3015 error_report("Could not load LPAR firmware '%s'", filename); 3016 exit(1); 3017 } 3018 g_free(filename); 3019 3020 /* FIXME: Should register things through the MachineState's qdev 3021 * interface, this is a legacy from the sPAPREnvironment structure 3022 * which predated MachineState but had a similar function */ 3023 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3024 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3025 &savevm_htab_handlers, spapr); 3026 3027 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine), 3028 &error_fatal); 3029 3030 qemu_register_boot_set(spapr_boot_set, spapr); 3031 3032 /* 3033 * Nothing needs to be done to resume a suspended guest because 3034 * suspending does not change the machine state, so no need for 3035 * a ->wakeup method. 3036 */ 3037 qemu_register_wakeup_support(); 3038 3039 if (kvm_enabled()) { 3040 /* to stop and start vmclock */ 3041 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3042 &spapr->tb); 3043 3044 kvmppc_spapr_enable_inkernel_multitce(); 3045 } 3046 3047 qemu_cond_init(&spapr->mc_delivery_cond); 3048 } 3049 3050 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3051 { 3052 if (!vm_type) { 3053 return 0; 3054 } 3055 3056 if (!strcmp(vm_type, "HV")) { 3057 return 1; 3058 } 3059 3060 if (!strcmp(vm_type, "PR")) { 3061 return 2; 3062 } 3063 3064 error_report("Unknown kvm-type specified '%s'", vm_type); 3065 exit(1); 3066 } 3067 3068 /* 3069 * Implementation of an interface to adjust firmware path 3070 * for the bootindex property handling. 3071 */ 3072 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3073 DeviceState *dev) 3074 { 3075 #define CAST(type, obj, name) \ 3076 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3077 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3078 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3079 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3080 3081 if (d) { 3082 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3083 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3084 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3085 3086 if (spapr) { 3087 /* 3088 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3089 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3090 * 0x8000 | (target << 8) | (bus << 5) | lun 3091 * (see the "Logical unit addressing format" table in SAM5) 3092 */ 3093 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3094 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3095 (uint64_t)id << 48); 3096 } else if (virtio) { 3097 /* 3098 * We use SRP luns of the form 01000000 | (target << 8) | lun 3099 * in the top 32 bits of the 64-bit LUN 3100 * Note: the quote above is from SLOF and it is wrong, 3101 * the actual binding is: 3102 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3103 */ 3104 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3105 if (d->lun >= 256) { 3106 /* Use the LUN "flat space addressing method" */ 3107 id |= 0x4000; 3108 } 3109 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3110 (uint64_t)id << 32); 3111 } else if (usb) { 3112 /* 3113 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3114 * in the top 32 bits of the 64-bit LUN 3115 */ 3116 unsigned usb_port = atoi(usb->port->path); 3117 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3118 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3119 (uint64_t)id << 32); 3120 } 3121 } 3122 3123 /* 3124 * SLOF probes the USB devices, and if it recognizes that the device is a 3125 * storage device, it changes its name to "storage" instead of "usb-host", 3126 * and additionally adds a child node for the SCSI LUN, so the correct 3127 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3128 */ 3129 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3130 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3131 if (usb_host_dev_is_scsi_storage(usbdev)) { 3132 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3133 } 3134 } 3135 3136 if (phb) { 3137 /* Replace "pci" with "pci@800000020000000" */ 3138 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3139 } 3140 3141 if (vsc) { 3142 /* Same logic as virtio above */ 3143 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3144 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3145 } 3146 3147 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3148 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3149 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3150 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3151 } 3152 3153 return NULL; 3154 } 3155 3156 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3157 { 3158 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3159 3160 return g_strdup(spapr->kvm_type); 3161 } 3162 3163 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3164 { 3165 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3166 3167 g_free(spapr->kvm_type); 3168 spapr->kvm_type = g_strdup(value); 3169 } 3170 3171 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3172 { 3173 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3174 3175 return spapr->use_hotplug_event_source; 3176 } 3177 3178 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3179 Error **errp) 3180 { 3181 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3182 3183 spapr->use_hotplug_event_source = value; 3184 } 3185 3186 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3187 { 3188 return true; 3189 } 3190 3191 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3192 { 3193 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3194 3195 switch (spapr->resize_hpt) { 3196 case SPAPR_RESIZE_HPT_DEFAULT: 3197 return g_strdup("default"); 3198 case SPAPR_RESIZE_HPT_DISABLED: 3199 return g_strdup("disabled"); 3200 case SPAPR_RESIZE_HPT_ENABLED: 3201 return g_strdup("enabled"); 3202 case SPAPR_RESIZE_HPT_REQUIRED: 3203 return g_strdup("required"); 3204 } 3205 g_assert_not_reached(); 3206 } 3207 3208 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3209 { 3210 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3211 3212 if (strcmp(value, "default") == 0) { 3213 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3214 } else if (strcmp(value, "disabled") == 0) { 3215 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3216 } else if (strcmp(value, "enabled") == 0) { 3217 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3218 } else if (strcmp(value, "required") == 0) { 3219 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3220 } else { 3221 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3222 } 3223 } 3224 3225 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 3226 void *opaque, Error **errp) 3227 { 3228 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3229 } 3230 3231 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 3232 void *opaque, Error **errp) 3233 { 3234 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3235 } 3236 3237 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3238 { 3239 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3240 3241 if (spapr->irq == &spapr_irq_xics_legacy) { 3242 return g_strdup("legacy"); 3243 } else if (spapr->irq == &spapr_irq_xics) { 3244 return g_strdup("xics"); 3245 } else if (spapr->irq == &spapr_irq_xive) { 3246 return g_strdup("xive"); 3247 } else if (spapr->irq == &spapr_irq_dual) { 3248 return g_strdup("dual"); 3249 } 3250 g_assert_not_reached(); 3251 } 3252 3253 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3254 { 3255 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3256 3257 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3258 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3259 return; 3260 } 3261 3262 /* The legacy IRQ backend can not be set */ 3263 if (strcmp(value, "xics") == 0) { 3264 spapr->irq = &spapr_irq_xics; 3265 } else if (strcmp(value, "xive") == 0) { 3266 spapr->irq = &spapr_irq_xive; 3267 } else if (strcmp(value, "dual") == 0) { 3268 spapr->irq = &spapr_irq_dual; 3269 } else { 3270 error_setg(errp, "Bad value for \"ic-mode\" property"); 3271 } 3272 } 3273 3274 static char *spapr_get_host_model(Object *obj, Error **errp) 3275 { 3276 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3277 3278 return g_strdup(spapr->host_model); 3279 } 3280 3281 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3282 { 3283 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3284 3285 g_free(spapr->host_model); 3286 spapr->host_model = g_strdup(value); 3287 } 3288 3289 static char *spapr_get_host_serial(Object *obj, Error **errp) 3290 { 3291 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3292 3293 return g_strdup(spapr->host_serial); 3294 } 3295 3296 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3297 { 3298 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3299 3300 g_free(spapr->host_serial); 3301 spapr->host_serial = g_strdup(value); 3302 } 3303 3304 static void spapr_instance_init(Object *obj) 3305 { 3306 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3307 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3308 3309 spapr->htab_fd = -1; 3310 spapr->use_hotplug_event_source = true; 3311 object_property_add_str(obj, "kvm-type", 3312 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 3313 object_property_set_description(obj, "kvm-type", 3314 "Specifies the KVM virtualization mode (HV, PR)", 3315 NULL); 3316 object_property_add_bool(obj, "modern-hotplug-events", 3317 spapr_get_modern_hotplug_events, 3318 spapr_set_modern_hotplug_events, 3319 NULL); 3320 object_property_set_description(obj, "modern-hotplug-events", 3321 "Use dedicated hotplug event mechanism in" 3322 " place of standard EPOW events when possible" 3323 " (required for memory hot-unplug support)", 3324 NULL); 3325 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3326 "Maximum permitted CPU compatibility mode", 3327 &error_fatal); 3328 3329 object_property_add_str(obj, "resize-hpt", 3330 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 3331 object_property_set_description(obj, "resize-hpt", 3332 "Resizing of the Hash Page Table (enabled, disabled, required)", 3333 NULL); 3334 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 3335 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 3336 object_property_set_description(obj, "vsmt", 3337 "Virtual SMT: KVM behaves as if this were" 3338 " the host's SMT mode", &error_abort); 3339 object_property_add_bool(obj, "vfio-no-msix-emulation", 3340 spapr_get_msix_emulation, NULL, NULL); 3341 3342 /* The machine class defines the default interrupt controller mode */ 3343 spapr->irq = smc->irq; 3344 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3345 spapr_set_ic_mode, NULL); 3346 object_property_set_description(obj, "ic-mode", 3347 "Specifies the interrupt controller mode (xics, xive, dual)", 3348 NULL); 3349 3350 object_property_add_str(obj, "host-model", 3351 spapr_get_host_model, spapr_set_host_model, 3352 &error_abort); 3353 object_property_set_description(obj, "host-model", 3354 "Host model to advertise in guest device tree", &error_abort); 3355 object_property_add_str(obj, "host-serial", 3356 spapr_get_host_serial, spapr_set_host_serial, 3357 &error_abort); 3358 object_property_set_description(obj, "host-serial", 3359 "Host serial number to advertise in guest device tree", &error_abort); 3360 } 3361 3362 static void spapr_machine_finalizefn(Object *obj) 3363 { 3364 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3365 3366 g_free(spapr->kvm_type); 3367 } 3368 3369 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3370 { 3371 cpu_synchronize_state(cs); 3372 ppc_cpu_do_system_reset(cs); 3373 } 3374 3375 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3376 { 3377 CPUState *cs; 3378 3379 CPU_FOREACH(cs) { 3380 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3381 } 3382 } 3383 3384 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3385 void *fdt, int *fdt_start_offset, Error **errp) 3386 { 3387 uint64_t addr; 3388 uint32_t node; 3389 3390 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3391 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3392 &error_abort); 3393 *fdt_start_offset = spapr_populate_memory_node(fdt, node, addr, 3394 SPAPR_MEMORY_BLOCK_SIZE); 3395 return 0; 3396 } 3397 3398 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3399 bool dedicated_hp_event_source, Error **errp) 3400 { 3401 SpaprDrc *drc; 3402 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3403 int i; 3404 uint64_t addr = addr_start; 3405 bool hotplugged = spapr_drc_hotplugged(dev); 3406 Error *local_err = NULL; 3407 3408 for (i = 0; i < nr_lmbs; i++) { 3409 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3410 addr / SPAPR_MEMORY_BLOCK_SIZE); 3411 g_assert(drc); 3412 3413 spapr_drc_attach(drc, dev, &local_err); 3414 if (local_err) { 3415 while (addr > addr_start) { 3416 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3417 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3418 addr / SPAPR_MEMORY_BLOCK_SIZE); 3419 spapr_drc_detach(drc); 3420 } 3421 error_propagate(errp, local_err); 3422 return; 3423 } 3424 if (!hotplugged) { 3425 spapr_drc_reset(drc); 3426 } 3427 addr += SPAPR_MEMORY_BLOCK_SIZE; 3428 } 3429 /* send hotplug notification to the 3430 * guest only in case of hotplugged memory 3431 */ 3432 if (hotplugged) { 3433 if (dedicated_hp_event_source) { 3434 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3435 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3436 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3437 nr_lmbs, 3438 spapr_drc_index(drc)); 3439 } else { 3440 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3441 nr_lmbs); 3442 } 3443 } 3444 } 3445 3446 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3447 Error **errp) 3448 { 3449 Error *local_err = NULL; 3450 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3451 PCDIMMDevice *dimm = PC_DIMM(dev); 3452 uint64_t size, addr, slot; 3453 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3454 3455 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3456 3457 pc_dimm_plug(dimm, MACHINE(ms), &local_err); 3458 if (local_err) { 3459 goto out; 3460 } 3461 3462 if (!is_nvdimm) { 3463 addr = object_property_get_uint(OBJECT(dimm), 3464 PC_DIMM_ADDR_PROP, &local_err); 3465 if (local_err) { 3466 goto out_unplug; 3467 } 3468 spapr_add_lmbs(dev, addr, size, 3469 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3470 &local_err); 3471 } else { 3472 slot = object_property_get_uint(OBJECT(dimm), 3473 PC_DIMM_SLOT_PROP, &local_err); 3474 if (local_err) { 3475 goto out_unplug; 3476 } 3477 spapr_add_nvdimm(dev, slot, &local_err); 3478 } 3479 3480 if (local_err) { 3481 goto out_unplug; 3482 } 3483 3484 return; 3485 3486 out_unplug: 3487 pc_dimm_unplug(dimm, MACHINE(ms)); 3488 out: 3489 error_propagate(errp, local_err); 3490 } 3491 3492 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3493 Error **errp) 3494 { 3495 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3496 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3497 const MachineClass *mc = MACHINE_CLASS(smc); 3498 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3499 PCDIMMDevice *dimm = PC_DIMM(dev); 3500 Error *local_err = NULL; 3501 uint64_t size; 3502 Object *memdev; 3503 hwaddr pagesize; 3504 3505 if (!smc->dr_lmb_enabled) { 3506 error_setg(errp, "Memory hotplug not supported for this machine"); 3507 return; 3508 } 3509 3510 if (is_nvdimm && !mc->nvdimm_supported) { 3511 error_setg(errp, "NVDIMM hotplug not supported for this machine"); 3512 return; 3513 } 3514 3515 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3516 if (local_err) { 3517 error_propagate(errp, local_err); 3518 return; 3519 } 3520 3521 if (!is_nvdimm && size % SPAPR_MEMORY_BLOCK_SIZE) { 3522 error_setg(errp, "Hotplugged memory size must be a multiple of " 3523 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3524 return; 3525 } else if (is_nvdimm) { 3526 spapr_nvdimm_validate_opts(NVDIMM(dev), size, &local_err); 3527 if (local_err) { 3528 error_propagate(errp, local_err); 3529 return; 3530 } 3531 } 3532 3533 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3534 &error_abort); 3535 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3536 spapr_check_pagesize(spapr, pagesize, &local_err); 3537 if (local_err) { 3538 error_propagate(errp, local_err); 3539 return; 3540 } 3541 3542 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3543 } 3544 3545 struct SpaprDimmState { 3546 PCDIMMDevice *dimm; 3547 uint32_t nr_lmbs; 3548 QTAILQ_ENTRY(SpaprDimmState) next; 3549 }; 3550 3551 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3552 PCDIMMDevice *dimm) 3553 { 3554 SpaprDimmState *dimm_state = NULL; 3555 3556 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3557 if (dimm_state->dimm == dimm) { 3558 break; 3559 } 3560 } 3561 return dimm_state; 3562 } 3563 3564 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3565 uint32_t nr_lmbs, 3566 PCDIMMDevice *dimm) 3567 { 3568 SpaprDimmState *ds = NULL; 3569 3570 /* 3571 * If this request is for a DIMM whose removal had failed earlier 3572 * (due to guest's refusal to remove the LMBs), we would have this 3573 * dimm already in the pending_dimm_unplugs list. In that 3574 * case don't add again. 3575 */ 3576 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3577 if (!ds) { 3578 ds = g_malloc0(sizeof(SpaprDimmState)); 3579 ds->nr_lmbs = nr_lmbs; 3580 ds->dimm = dimm; 3581 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3582 } 3583 return ds; 3584 } 3585 3586 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3587 SpaprDimmState *dimm_state) 3588 { 3589 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3590 g_free(dimm_state); 3591 } 3592 3593 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3594 PCDIMMDevice *dimm) 3595 { 3596 SpaprDrc *drc; 3597 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3598 &error_abort); 3599 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3600 uint32_t avail_lmbs = 0; 3601 uint64_t addr_start, addr; 3602 int i; 3603 3604 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3605 &error_abort); 3606 3607 addr = addr_start; 3608 for (i = 0; i < nr_lmbs; i++) { 3609 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3610 addr / SPAPR_MEMORY_BLOCK_SIZE); 3611 g_assert(drc); 3612 if (drc->dev) { 3613 avail_lmbs++; 3614 } 3615 addr += SPAPR_MEMORY_BLOCK_SIZE; 3616 } 3617 3618 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3619 } 3620 3621 /* Callback to be called during DRC release. */ 3622 void spapr_lmb_release(DeviceState *dev) 3623 { 3624 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3625 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3626 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3627 3628 /* This information will get lost if a migration occurs 3629 * during the unplug process. In this case recover it. */ 3630 if (ds == NULL) { 3631 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3632 g_assert(ds); 3633 /* The DRC being examined by the caller at least must be counted */ 3634 g_assert(ds->nr_lmbs); 3635 } 3636 3637 if (--ds->nr_lmbs) { 3638 return; 3639 } 3640 3641 /* 3642 * Now that all the LMBs have been removed by the guest, call the 3643 * unplug handler chain. This can never fail. 3644 */ 3645 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3646 object_unparent(OBJECT(dev)); 3647 } 3648 3649 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3650 { 3651 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3652 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3653 3654 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3655 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3656 spapr_pending_dimm_unplugs_remove(spapr, ds); 3657 } 3658 3659 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3660 DeviceState *dev, Error **errp) 3661 { 3662 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3663 Error *local_err = NULL; 3664 PCDIMMDevice *dimm = PC_DIMM(dev); 3665 uint32_t nr_lmbs; 3666 uint64_t size, addr_start, addr; 3667 int i; 3668 SpaprDrc *drc; 3669 3670 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3671 error_setg(&local_err, 3672 "nvdimm device hot unplug is not supported yet."); 3673 goto out; 3674 } 3675 3676 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3677 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3678 3679 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3680 &local_err); 3681 if (local_err) { 3682 goto out; 3683 } 3684 3685 /* 3686 * An existing pending dimm state for this DIMM means that there is an 3687 * unplug operation in progress, waiting for the spapr_lmb_release 3688 * callback to complete the job (BQL can't cover that far). In this case, 3689 * bail out to avoid detaching DRCs that were already released. 3690 */ 3691 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3692 error_setg(&local_err, 3693 "Memory unplug already in progress for device %s", 3694 dev->id); 3695 goto out; 3696 } 3697 3698 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3699 3700 addr = addr_start; 3701 for (i = 0; i < nr_lmbs; i++) { 3702 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3703 addr / SPAPR_MEMORY_BLOCK_SIZE); 3704 g_assert(drc); 3705 3706 spapr_drc_detach(drc); 3707 addr += SPAPR_MEMORY_BLOCK_SIZE; 3708 } 3709 3710 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3711 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3712 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3713 nr_lmbs, spapr_drc_index(drc)); 3714 out: 3715 error_propagate(errp, local_err); 3716 } 3717 3718 /* Callback to be called during DRC release. */ 3719 void spapr_core_release(DeviceState *dev) 3720 { 3721 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3722 3723 /* Call the unplug handler chain. This can never fail. */ 3724 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3725 object_unparent(OBJECT(dev)); 3726 } 3727 3728 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3729 { 3730 MachineState *ms = MACHINE(hotplug_dev); 3731 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3732 CPUCore *cc = CPU_CORE(dev); 3733 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3734 3735 if (smc->pre_2_10_has_unused_icps) { 3736 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3737 int i; 3738 3739 for (i = 0; i < cc->nr_threads; i++) { 3740 CPUState *cs = CPU(sc->threads[i]); 3741 3742 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3743 } 3744 } 3745 3746 assert(core_slot); 3747 core_slot->cpu = NULL; 3748 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3749 } 3750 3751 static 3752 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3753 Error **errp) 3754 { 3755 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3756 int index; 3757 SpaprDrc *drc; 3758 CPUCore *cc = CPU_CORE(dev); 3759 3760 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3761 error_setg(errp, "Unable to find CPU core with core-id: %d", 3762 cc->core_id); 3763 return; 3764 } 3765 if (index == 0) { 3766 error_setg(errp, "Boot CPU core may not be unplugged"); 3767 return; 3768 } 3769 3770 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3771 spapr_vcpu_id(spapr, cc->core_id)); 3772 g_assert(drc); 3773 3774 if (!spapr_drc_unplug_requested(drc)) { 3775 spapr_drc_detach(drc); 3776 spapr_hotplug_req_remove_by_index(drc); 3777 } 3778 } 3779 3780 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3781 void *fdt, int *fdt_start_offset, Error **errp) 3782 { 3783 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3784 CPUState *cs = CPU(core->threads[0]); 3785 PowerPCCPU *cpu = POWERPC_CPU(cs); 3786 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3787 int id = spapr_get_vcpu_id(cpu); 3788 char *nodename; 3789 int offset; 3790 3791 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3792 offset = fdt_add_subnode(fdt, 0, nodename); 3793 g_free(nodename); 3794 3795 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3796 3797 *fdt_start_offset = offset; 3798 return 0; 3799 } 3800 3801 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3802 Error **errp) 3803 { 3804 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3805 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3806 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3807 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3808 CPUCore *cc = CPU_CORE(dev); 3809 CPUState *cs; 3810 SpaprDrc *drc; 3811 Error *local_err = NULL; 3812 CPUArchId *core_slot; 3813 int index; 3814 bool hotplugged = spapr_drc_hotplugged(dev); 3815 int i; 3816 3817 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3818 if (!core_slot) { 3819 error_setg(errp, "Unable to find CPU core with core-id: %d", 3820 cc->core_id); 3821 return; 3822 } 3823 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3824 spapr_vcpu_id(spapr, cc->core_id)); 3825 3826 g_assert(drc || !mc->has_hotpluggable_cpus); 3827 3828 if (drc) { 3829 spapr_drc_attach(drc, dev, &local_err); 3830 if (local_err) { 3831 error_propagate(errp, local_err); 3832 return; 3833 } 3834 3835 if (hotplugged) { 3836 /* 3837 * Send hotplug notification interrupt to the guest only 3838 * in case of hotplugged CPUs. 3839 */ 3840 spapr_hotplug_req_add_by_index(drc); 3841 } else { 3842 spapr_drc_reset(drc); 3843 } 3844 } 3845 3846 core_slot->cpu = OBJECT(dev); 3847 3848 if (smc->pre_2_10_has_unused_icps) { 3849 for (i = 0; i < cc->nr_threads; i++) { 3850 cs = CPU(core->threads[i]); 3851 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3852 } 3853 } 3854 3855 /* 3856 * Set compatibility mode to match the boot CPU, which was either set 3857 * by the machine reset code or by CAS. 3858 */ 3859 if (hotplugged) { 3860 for (i = 0; i < cc->nr_threads; i++) { 3861 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3862 &local_err); 3863 if (local_err) { 3864 error_propagate(errp, local_err); 3865 return; 3866 } 3867 } 3868 } 3869 } 3870 3871 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3872 Error **errp) 3873 { 3874 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3875 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3876 Error *local_err = NULL; 3877 CPUCore *cc = CPU_CORE(dev); 3878 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3879 const char *type = object_get_typename(OBJECT(dev)); 3880 CPUArchId *core_slot; 3881 int index; 3882 unsigned int smp_threads = machine->smp.threads; 3883 3884 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3885 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3886 goto out; 3887 } 3888 3889 if (strcmp(base_core_type, type)) { 3890 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3891 goto out; 3892 } 3893 3894 if (cc->core_id % smp_threads) { 3895 error_setg(&local_err, "invalid core id %d", cc->core_id); 3896 goto out; 3897 } 3898 3899 /* 3900 * In general we should have homogeneous threads-per-core, but old 3901 * (pre hotplug support) machine types allow the last core to have 3902 * reduced threads as a compatibility hack for when we allowed 3903 * total vcpus not a multiple of threads-per-core. 3904 */ 3905 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3906 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3907 cc->nr_threads, smp_threads); 3908 goto out; 3909 } 3910 3911 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3912 if (!core_slot) { 3913 error_setg(&local_err, "core id %d out of range", cc->core_id); 3914 goto out; 3915 } 3916 3917 if (core_slot->cpu) { 3918 error_setg(&local_err, "core %d already populated", cc->core_id); 3919 goto out; 3920 } 3921 3922 numa_cpu_pre_plug(core_slot, dev, &local_err); 3923 3924 out: 3925 error_propagate(errp, local_err); 3926 } 3927 3928 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3929 void *fdt, int *fdt_start_offset, Error **errp) 3930 { 3931 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3932 int intc_phandle; 3933 3934 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3935 if (intc_phandle <= 0) { 3936 return -1; 3937 } 3938 3939 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3940 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3941 return -1; 3942 } 3943 3944 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3945 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3946 3947 return 0; 3948 } 3949 3950 static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3951 Error **errp) 3952 { 3953 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3954 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3955 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3956 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3957 3958 if (dev->hotplugged && !smc->dr_phb_enabled) { 3959 error_setg(errp, "PHB hotplug not supported for this machine"); 3960 return; 3961 } 3962 3963 if (sphb->index == (uint32_t)-1) { 3964 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3965 return; 3966 } 3967 3968 /* 3969 * This will check that sphb->index doesn't exceed the maximum number of 3970 * PHBs for the current machine type. 3971 */ 3972 smc->phb_placement(spapr, sphb->index, 3973 &sphb->buid, &sphb->io_win_addr, 3974 &sphb->mem_win_addr, &sphb->mem64_win_addr, 3975 windows_supported, sphb->dma_liobn, 3976 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 3977 errp); 3978 } 3979 3980 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3981 Error **errp) 3982 { 3983 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3984 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3985 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3986 SpaprDrc *drc; 3987 bool hotplugged = spapr_drc_hotplugged(dev); 3988 Error *local_err = NULL; 3989 3990 if (!smc->dr_phb_enabled) { 3991 return; 3992 } 3993 3994 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3995 /* hotplug hooks should check it's enabled before getting this far */ 3996 assert(drc); 3997 3998 spapr_drc_attach(drc, DEVICE(dev), &local_err); 3999 if (local_err) { 4000 error_propagate(errp, local_err); 4001 return; 4002 } 4003 4004 if (hotplugged) { 4005 spapr_hotplug_req_add_by_index(drc); 4006 } else { 4007 spapr_drc_reset(drc); 4008 } 4009 } 4010 4011 void spapr_phb_release(DeviceState *dev) 4012 { 4013 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4014 4015 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4016 object_unparent(OBJECT(dev)); 4017 } 4018 4019 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4020 { 4021 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 4022 } 4023 4024 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4025 DeviceState *dev, Error **errp) 4026 { 4027 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4028 SpaprDrc *drc; 4029 4030 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4031 assert(drc); 4032 4033 if (!spapr_drc_unplug_requested(drc)) { 4034 spapr_drc_detach(drc); 4035 spapr_hotplug_req_remove_by_index(drc); 4036 } 4037 } 4038 4039 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4040 Error **errp) 4041 { 4042 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4043 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4044 4045 if (spapr->tpm_proxy != NULL) { 4046 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4047 return; 4048 } 4049 4050 spapr->tpm_proxy = tpm_proxy; 4051 } 4052 4053 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4054 { 4055 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4056 4057 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 4058 object_unparent(OBJECT(dev)); 4059 spapr->tpm_proxy = NULL; 4060 } 4061 4062 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4063 DeviceState *dev, Error **errp) 4064 { 4065 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4066 spapr_memory_plug(hotplug_dev, dev, errp); 4067 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4068 spapr_core_plug(hotplug_dev, dev, errp); 4069 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4070 spapr_phb_plug(hotplug_dev, dev, errp); 4071 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4072 spapr_tpm_proxy_plug(hotplug_dev, dev, errp); 4073 } 4074 } 4075 4076 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4077 DeviceState *dev, Error **errp) 4078 { 4079 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4080 spapr_memory_unplug(hotplug_dev, dev); 4081 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4082 spapr_core_unplug(hotplug_dev, dev); 4083 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4084 spapr_phb_unplug(hotplug_dev, dev); 4085 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4086 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4087 } 4088 } 4089 4090 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4091 DeviceState *dev, Error **errp) 4092 { 4093 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4094 MachineClass *mc = MACHINE_GET_CLASS(sms); 4095 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4096 4097 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4098 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 4099 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4100 } else { 4101 /* NOTE: this means there is a window after guest reset, prior to 4102 * CAS negotiation, where unplug requests will fail due to the 4103 * capability not being detected yet. This is a bit different than 4104 * the case with PCI unplug, where the events will be queued and 4105 * eventually handled by the guest after boot 4106 */ 4107 error_setg(errp, "Memory hot unplug not supported for this guest"); 4108 } 4109 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4110 if (!mc->has_hotpluggable_cpus) { 4111 error_setg(errp, "CPU hot unplug not supported on this machine"); 4112 return; 4113 } 4114 spapr_core_unplug_request(hotplug_dev, dev, errp); 4115 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4116 if (!smc->dr_phb_enabled) { 4117 error_setg(errp, "PHB hot unplug not supported on this machine"); 4118 return; 4119 } 4120 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4121 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4122 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4123 } 4124 } 4125 4126 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4127 DeviceState *dev, Error **errp) 4128 { 4129 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4130 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4131 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4132 spapr_core_pre_plug(hotplug_dev, dev, errp); 4133 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4134 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4135 } 4136 } 4137 4138 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4139 DeviceState *dev) 4140 { 4141 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4142 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4143 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4144 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4145 return HOTPLUG_HANDLER(machine); 4146 } 4147 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4148 PCIDevice *pcidev = PCI_DEVICE(dev); 4149 PCIBus *root = pci_device_root_bus(pcidev); 4150 SpaprPhbState *phb = 4151 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4152 TYPE_SPAPR_PCI_HOST_BRIDGE); 4153 4154 if (phb) { 4155 return HOTPLUG_HANDLER(phb); 4156 } 4157 } 4158 return NULL; 4159 } 4160 4161 static CpuInstanceProperties 4162 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4163 { 4164 CPUArchId *core_slot; 4165 MachineClass *mc = MACHINE_GET_CLASS(machine); 4166 4167 /* make sure possible_cpu are intialized */ 4168 mc->possible_cpu_arch_ids(machine); 4169 /* get CPU core slot containing thread that matches cpu_index */ 4170 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4171 assert(core_slot); 4172 return core_slot->props; 4173 } 4174 4175 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4176 { 4177 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4178 } 4179 4180 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4181 { 4182 int i; 4183 unsigned int smp_threads = machine->smp.threads; 4184 unsigned int smp_cpus = machine->smp.cpus; 4185 const char *core_type; 4186 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4187 MachineClass *mc = MACHINE_GET_CLASS(machine); 4188 4189 if (!mc->has_hotpluggable_cpus) { 4190 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4191 } 4192 if (machine->possible_cpus) { 4193 assert(machine->possible_cpus->len == spapr_max_cores); 4194 return machine->possible_cpus; 4195 } 4196 4197 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4198 if (!core_type) { 4199 error_report("Unable to find sPAPR CPU Core definition"); 4200 exit(1); 4201 } 4202 4203 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4204 sizeof(CPUArchId) * spapr_max_cores); 4205 machine->possible_cpus->len = spapr_max_cores; 4206 for (i = 0; i < machine->possible_cpus->len; i++) { 4207 int core_id = i * smp_threads; 4208 4209 machine->possible_cpus->cpus[i].type = core_type; 4210 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4211 machine->possible_cpus->cpus[i].arch_id = core_id; 4212 machine->possible_cpus->cpus[i].props.has_core_id = true; 4213 machine->possible_cpus->cpus[i].props.core_id = core_id; 4214 } 4215 return machine->possible_cpus; 4216 } 4217 4218 static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4219 uint64_t *buid, hwaddr *pio, 4220 hwaddr *mmio32, hwaddr *mmio64, 4221 unsigned n_dma, uint32_t *liobns, 4222 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4223 { 4224 /* 4225 * New-style PHB window placement. 4226 * 4227 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4228 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4229 * windows. 4230 * 4231 * Some guest kernels can't work with MMIO windows above 1<<46 4232 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4233 * 4234 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4235 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4236 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4237 * 1TiB 64-bit MMIO windows for each PHB. 4238 */ 4239 const uint64_t base_buid = 0x800000020000000ULL; 4240 int i; 4241 4242 /* Sanity check natural alignments */ 4243 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4244 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4245 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4246 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4247 /* Sanity check bounds */ 4248 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4249 SPAPR_PCI_MEM32_WIN_SIZE); 4250 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4251 SPAPR_PCI_MEM64_WIN_SIZE); 4252 4253 if (index >= SPAPR_MAX_PHBS) { 4254 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4255 SPAPR_MAX_PHBS - 1); 4256 return; 4257 } 4258 4259 *buid = base_buid + index; 4260 for (i = 0; i < n_dma; ++i) { 4261 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4262 } 4263 4264 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4265 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4266 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4267 4268 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4269 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4270 } 4271 4272 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4273 { 4274 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4275 4276 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4277 } 4278 4279 static void spapr_ics_resend(XICSFabric *dev) 4280 { 4281 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4282 4283 ics_resend(spapr->ics); 4284 } 4285 4286 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4287 { 4288 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4289 4290 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4291 } 4292 4293 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4294 Monitor *mon) 4295 { 4296 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4297 4298 spapr_irq_print_info(spapr, mon); 4299 monitor_printf(mon, "irqchip: %s\n", 4300 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4301 } 4302 4303 /* 4304 * This is a XIVE only operation 4305 */ 4306 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4307 uint8_t nvt_blk, uint32_t nvt_idx, 4308 bool cam_ignore, uint8_t priority, 4309 uint32_t logic_serv, XiveTCTXMatch *match) 4310 { 4311 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4312 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4313 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4314 int count; 4315 4316 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4317 priority, logic_serv, match); 4318 if (count < 0) { 4319 return count; 4320 } 4321 4322 /* 4323 * When we implement the save and restore of the thread interrupt 4324 * contexts in the enter/exit CPU handlers of the machine and the 4325 * escalations in QEMU, we should be able to handle non dispatched 4326 * vCPUs. 4327 * 4328 * Until this is done, the sPAPR machine should find at least one 4329 * matching context always. 4330 */ 4331 if (count == 0) { 4332 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4333 nvt_blk, nvt_idx); 4334 } 4335 4336 return count; 4337 } 4338 4339 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4340 { 4341 return cpu->vcpu_id; 4342 } 4343 4344 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4345 { 4346 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4347 MachineState *ms = MACHINE(spapr); 4348 int vcpu_id; 4349 4350 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4351 4352 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4353 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4354 error_append_hint(errp, "Adjust the number of cpus to %d " 4355 "or try to raise the number of threads per core\n", 4356 vcpu_id * ms->smp.threads / spapr->vsmt); 4357 return; 4358 } 4359 4360 cpu->vcpu_id = vcpu_id; 4361 } 4362 4363 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4364 { 4365 CPUState *cs; 4366 4367 CPU_FOREACH(cs) { 4368 PowerPCCPU *cpu = POWERPC_CPU(cs); 4369 4370 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4371 return cpu; 4372 } 4373 } 4374 4375 return NULL; 4376 } 4377 4378 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4379 { 4380 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4381 4382 /* These are only called by TCG, KVM maintains dispatch state */ 4383 4384 spapr_cpu->prod = false; 4385 if (spapr_cpu->vpa_addr) { 4386 CPUState *cs = CPU(cpu); 4387 uint32_t dispatch; 4388 4389 dispatch = ldl_be_phys(cs->as, 4390 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4391 dispatch++; 4392 if ((dispatch & 1) != 0) { 4393 qemu_log_mask(LOG_GUEST_ERROR, 4394 "VPA: incorrect dispatch counter value for " 4395 "dispatched partition %u, correcting.\n", dispatch); 4396 dispatch++; 4397 } 4398 stl_be_phys(cs->as, 4399 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4400 } 4401 } 4402 4403 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4404 { 4405 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4406 4407 if (spapr_cpu->vpa_addr) { 4408 CPUState *cs = CPU(cpu); 4409 uint32_t dispatch; 4410 4411 dispatch = ldl_be_phys(cs->as, 4412 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4413 dispatch++; 4414 if ((dispatch & 1) != 1) { 4415 qemu_log_mask(LOG_GUEST_ERROR, 4416 "VPA: incorrect dispatch counter value for " 4417 "preempted partition %u, correcting.\n", dispatch); 4418 dispatch++; 4419 } 4420 stl_be_phys(cs->as, 4421 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4422 } 4423 } 4424 4425 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4426 { 4427 MachineClass *mc = MACHINE_CLASS(oc); 4428 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4429 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4430 NMIClass *nc = NMI_CLASS(oc); 4431 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4432 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4433 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4434 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4435 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4436 4437 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4438 mc->ignore_boot_device_suffixes = true; 4439 4440 /* 4441 * We set up the default / latest behaviour here. The class_init 4442 * functions for the specific versioned machine types can override 4443 * these details for backwards compatibility 4444 */ 4445 mc->init = spapr_machine_init; 4446 mc->reset = spapr_machine_reset; 4447 mc->block_default_type = IF_SCSI; 4448 mc->max_cpus = 1024; 4449 mc->no_parallel = 1; 4450 mc->default_boot_order = ""; 4451 mc->default_ram_size = 512 * MiB; 4452 mc->default_display = "std"; 4453 mc->kvm_type = spapr_kvm_type; 4454 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4455 mc->pci_allow_0_address = true; 4456 assert(!mc->get_hotplug_handler); 4457 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4458 hc->pre_plug = spapr_machine_device_pre_plug; 4459 hc->plug = spapr_machine_device_plug; 4460 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4461 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4462 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4463 hc->unplug_request = spapr_machine_device_unplug_request; 4464 hc->unplug = spapr_machine_device_unplug; 4465 4466 smc->dr_lmb_enabled = true; 4467 smc->update_dt_enabled = true; 4468 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4469 mc->has_hotpluggable_cpus = true; 4470 mc->nvdimm_supported = true; 4471 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4472 fwc->get_dev_path = spapr_get_fw_dev_path; 4473 nc->nmi_monitor_handler = spapr_nmi; 4474 smc->phb_placement = spapr_phb_placement; 4475 vhc->hypercall = emulate_spapr_hypercall; 4476 vhc->hpt_mask = spapr_hpt_mask; 4477 vhc->map_hptes = spapr_map_hptes; 4478 vhc->unmap_hptes = spapr_unmap_hptes; 4479 vhc->hpte_set_c = spapr_hpte_set_c; 4480 vhc->hpte_set_r = spapr_hpte_set_r; 4481 vhc->get_pate = spapr_get_pate; 4482 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4483 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4484 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4485 xic->ics_get = spapr_ics_get; 4486 xic->ics_resend = spapr_ics_resend; 4487 xic->icp_get = spapr_icp_get; 4488 ispc->print_info = spapr_pic_print_info; 4489 /* Force NUMA node memory size to be a multiple of 4490 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4491 * in which LMBs are represented and hot-added 4492 */ 4493 mc->numa_mem_align_shift = 28; 4494 mc->numa_mem_supported = true; 4495 mc->auto_enable_numa = true; 4496 4497 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4498 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4499 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4500 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4501 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4502 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4503 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4504 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4505 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4506 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4507 smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] = SPAPR_CAP_ON; 4508 spapr_caps_add_properties(smc, &error_abort); 4509 smc->irq = &spapr_irq_dual; 4510 smc->dr_phb_enabled = true; 4511 smc->linux_pci_probe = true; 4512 smc->smp_threads_vsmt = true; 4513 smc->nr_xirqs = SPAPR_NR_XIRQS; 4514 xfc->match_nvt = spapr_match_nvt; 4515 } 4516 4517 static const TypeInfo spapr_machine_info = { 4518 .name = TYPE_SPAPR_MACHINE, 4519 .parent = TYPE_MACHINE, 4520 .abstract = true, 4521 .instance_size = sizeof(SpaprMachineState), 4522 .instance_init = spapr_instance_init, 4523 .instance_finalize = spapr_machine_finalizefn, 4524 .class_size = sizeof(SpaprMachineClass), 4525 .class_init = spapr_machine_class_init, 4526 .interfaces = (InterfaceInfo[]) { 4527 { TYPE_FW_PATH_PROVIDER }, 4528 { TYPE_NMI }, 4529 { TYPE_HOTPLUG_HANDLER }, 4530 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4531 { TYPE_XICS_FABRIC }, 4532 { TYPE_INTERRUPT_STATS_PROVIDER }, 4533 { TYPE_XIVE_FABRIC }, 4534 { } 4535 }, 4536 }; 4537 4538 static void spapr_machine_latest_class_options(MachineClass *mc) 4539 { 4540 mc->alias = "pseries"; 4541 mc->is_default = 1; 4542 } 4543 4544 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4545 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4546 void *data) \ 4547 { \ 4548 MachineClass *mc = MACHINE_CLASS(oc); \ 4549 spapr_machine_##suffix##_class_options(mc); \ 4550 if (latest) { \ 4551 spapr_machine_latest_class_options(mc); \ 4552 } \ 4553 } \ 4554 static const TypeInfo spapr_machine_##suffix##_info = { \ 4555 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4556 .parent = TYPE_SPAPR_MACHINE, \ 4557 .class_init = spapr_machine_##suffix##_class_init, \ 4558 }; \ 4559 static void spapr_machine_register_##suffix(void) \ 4560 { \ 4561 type_register(&spapr_machine_##suffix##_info); \ 4562 } \ 4563 type_init(spapr_machine_register_##suffix) 4564 4565 /* 4566 * pseries-5.0 4567 */ 4568 static void spapr_machine_5_0_class_options(MachineClass *mc) 4569 { 4570 /* Defaults for the latest behaviour inherited from the base class */ 4571 } 4572 4573 DEFINE_SPAPR_MACHINE(5_0, "5.0", true); 4574 4575 /* 4576 * pseries-4.2 4577 */ 4578 static void spapr_machine_4_2_class_options(MachineClass *mc) 4579 { 4580 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4581 4582 spapr_machine_5_0_class_options(mc); 4583 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4584 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4585 smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] = SPAPR_CAP_OFF; 4586 mc->nvdimm_supported = false; 4587 } 4588 4589 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4590 4591 /* 4592 * pseries-4.1 4593 */ 4594 static void spapr_machine_4_1_class_options(MachineClass *mc) 4595 { 4596 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4597 static GlobalProperty compat[] = { 4598 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4599 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4600 }; 4601 4602 spapr_machine_4_2_class_options(mc); 4603 smc->linux_pci_probe = false; 4604 smc->smp_threads_vsmt = false; 4605 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4606 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4607 } 4608 4609 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4610 4611 /* 4612 * pseries-4.0 4613 */ 4614 static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4615 uint64_t *buid, hwaddr *pio, 4616 hwaddr *mmio32, hwaddr *mmio64, 4617 unsigned n_dma, uint32_t *liobns, 4618 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4619 { 4620 spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns, 4621 nv2gpa, nv2atsd, errp); 4622 *nv2gpa = 0; 4623 *nv2atsd = 0; 4624 } 4625 4626 static void spapr_machine_4_0_class_options(MachineClass *mc) 4627 { 4628 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4629 4630 spapr_machine_4_1_class_options(mc); 4631 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4632 smc->phb_placement = phb_placement_4_0; 4633 smc->irq = &spapr_irq_xics; 4634 smc->pre_4_1_migration = true; 4635 } 4636 4637 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4638 4639 /* 4640 * pseries-3.1 4641 */ 4642 static void spapr_machine_3_1_class_options(MachineClass *mc) 4643 { 4644 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4645 4646 spapr_machine_4_0_class_options(mc); 4647 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4648 4649 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4650 smc->update_dt_enabled = false; 4651 smc->dr_phb_enabled = false; 4652 smc->broken_host_serial_model = true; 4653 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4654 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4655 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4656 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4657 } 4658 4659 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4660 4661 /* 4662 * pseries-3.0 4663 */ 4664 4665 static void spapr_machine_3_0_class_options(MachineClass *mc) 4666 { 4667 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4668 4669 spapr_machine_3_1_class_options(mc); 4670 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4671 4672 smc->legacy_irq_allocation = true; 4673 smc->nr_xirqs = 0x400; 4674 smc->irq = &spapr_irq_xics_legacy; 4675 } 4676 4677 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4678 4679 /* 4680 * pseries-2.12 4681 */ 4682 static void spapr_machine_2_12_class_options(MachineClass *mc) 4683 { 4684 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4685 static GlobalProperty compat[] = { 4686 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4687 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4688 }; 4689 4690 spapr_machine_3_0_class_options(mc); 4691 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4692 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4693 4694 /* We depend on kvm_enabled() to choose a default value for the 4695 * hpt-max-page-size capability. Of course we can't do it here 4696 * because this is too early and the HW accelerator isn't initialzed 4697 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4698 */ 4699 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4700 } 4701 4702 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4703 4704 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4705 { 4706 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4707 4708 spapr_machine_2_12_class_options(mc); 4709 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4710 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4711 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4712 } 4713 4714 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4715 4716 /* 4717 * pseries-2.11 4718 */ 4719 4720 static void spapr_machine_2_11_class_options(MachineClass *mc) 4721 { 4722 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4723 4724 spapr_machine_2_12_class_options(mc); 4725 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4726 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4727 } 4728 4729 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4730 4731 /* 4732 * pseries-2.10 4733 */ 4734 4735 static void spapr_machine_2_10_class_options(MachineClass *mc) 4736 { 4737 spapr_machine_2_11_class_options(mc); 4738 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4739 } 4740 4741 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4742 4743 /* 4744 * pseries-2.9 4745 */ 4746 4747 static void spapr_machine_2_9_class_options(MachineClass *mc) 4748 { 4749 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4750 static GlobalProperty compat[] = { 4751 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4752 }; 4753 4754 spapr_machine_2_10_class_options(mc); 4755 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4756 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4757 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4758 smc->pre_2_10_has_unused_icps = true; 4759 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4760 } 4761 4762 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4763 4764 /* 4765 * pseries-2.8 4766 */ 4767 4768 static void spapr_machine_2_8_class_options(MachineClass *mc) 4769 { 4770 static GlobalProperty compat[] = { 4771 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4772 }; 4773 4774 spapr_machine_2_9_class_options(mc); 4775 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4776 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4777 mc->numa_mem_align_shift = 23; 4778 } 4779 4780 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4781 4782 /* 4783 * pseries-2.7 4784 */ 4785 4786 static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4787 uint64_t *buid, hwaddr *pio, 4788 hwaddr *mmio32, hwaddr *mmio64, 4789 unsigned n_dma, uint32_t *liobns, 4790 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4791 { 4792 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4793 const uint64_t base_buid = 0x800000020000000ULL; 4794 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4795 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4796 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4797 const uint32_t max_index = 255; 4798 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4799 4800 uint64_t ram_top = MACHINE(spapr)->ram_size; 4801 hwaddr phb0_base, phb_base; 4802 int i; 4803 4804 /* Do we have device memory? */ 4805 if (MACHINE(spapr)->maxram_size > ram_top) { 4806 /* Can't just use maxram_size, because there may be an 4807 * alignment gap between normal and device memory regions 4808 */ 4809 ram_top = MACHINE(spapr)->device_memory->base + 4810 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4811 } 4812 4813 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4814 4815 if (index > max_index) { 4816 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4817 max_index); 4818 return; 4819 } 4820 4821 *buid = base_buid + index; 4822 for (i = 0; i < n_dma; ++i) { 4823 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4824 } 4825 4826 phb_base = phb0_base + index * phb_spacing; 4827 *pio = phb_base + pio_offset; 4828 *mmio32 = phb_base + mmio_offset; 4829 /* 4830 * We don't set the 64-bit MMIO window, relying on the PHB's 4831 * fallback behaviour of automatically splitting a large "32-bit" 4832 * window into contiguous 32-bit and 64-bit windows 4833 */ 4834 4835 *nv2gpa = 0; 4836 *nv2atsd = 0; 4837 } 4838 4839 static void spapr_machine_2_7_class_options(MachineClass *mc) 4840 { 4841 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4842 static GlobalProperty compat[] = { 4843 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4844 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4845 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4846 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4847 }; 4848 4849 spapr_machine_2_8_class_options(mc); 4850 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4851 mc->default_machine_opts = "modern-hotplug-events=off"; 4852 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4853 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4854 smc->phb_placement = phb_placement_2_7; 4855 } 4856 4857 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4858 4859 /* 4860 * pseries-2.6 4861 */ 4862 4863 static void spapr_machine_2_6_class_options(MachineClass *mc) 4864 { 4865 static GlobalProperty compat[] = { 4866 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4867 }; 4868 4869 spapr_machine_2_7_class_options(mc); 4870 mc->has_hotpluggable_cpus = false; 4871 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4872 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4873 } 4874 4875 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4876 4877 /* 4878 * pseries-2.5 4879 */ 4880 4881 static void spapr_machine_2_5_class_options(MachineClass *mc) 4882 { 4883 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4884 static GlobalProperty compat[] = { 4885 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4886 }; 4887 4888 spapr_machine_2_6_class_options(mc); 4889 smc->use_ohci_by_default = true; 4890 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4891 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4892 } 4893 4894 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4895 4896 /* 4897 * pseries-2.4 4898 */ 4899 4900 static void spapr_machine_2_4_class_options(MachineClass *mc) 4901 { 4902 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4903 4904 spapr_machine_2_5_class_options(mc); 4905 smc->dr_lmb_enabled = false; 4906 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4907 } 4908 4909 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4910 4911 /* 4912 * pseries-2.3 4913 */ 4914 4915 static void spapr_machine_2_3_class_options(MachineClass *mc) 4916 { 4917 static GlobalProperty compat[] = { 4918 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4919 }; 4920 spapr_machine_2_4_class_options(mc); 4921 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4922 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4923 } 4924 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4925 4926 /* 4927 * pseries-2.2 4928 */ 4929 4930 static void spapr_machine_2_2_class_options(MachineClass *mc) 4931 { 4932 static GlobalProperty compat[] = { 4933 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4934 }; 4935 4936 spapr_machine_2_3_class_options(mc); 4937 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4938 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4939 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4940 } 4941 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4942 4943 /* 4944 * pseries-2.1 4945 */ 4946 4947 static void spapr_machine_2_1_class_options(MachineClass *mc) 4948 { 4949 spapr_machine_2_2_class_options(mc); 4950 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4951 } 4952 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4953 4954 static void spapr_machine_register_types(void) 4955 { 4956 type_register_static(&spapr_machine_info); 4957 } 4958 4959 type_init(spapr_machine_register_types) 4960