1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/numa.h" 32 #include "sysemu/qtest.h" 33 #include "hw/hw.h" 34 #include "qemu/log.h" 35 #include "hw/fw-path-provider.h" 36 #include "elf.h" 37 #include "net/net.h" 38 #include "sysemu/device_tree.h" 39 #include "sysemu/cpus.h" 40 #include "sysemu/hw_accel.h" 41 #include "kvm_ppc.h" 42 #include "migration/misc.h" 43 #include "migration/global_state.h" 44 #include "migration/register.h" 45 #include "mmu-hash64.h" 46 #include "mmu-book3s-v3.h" 47 #include "cpu-models.h" 48 #include "qom/cpu.h" 49 50 #include "hw/boards.h" 51 #include "hw/ppc/ppc.h" 52 #include "hw/loader.h" 53 54 #include "hw/ppc/fdt.h" 55 #include "hw/ppc/spapr.h" 56 #include "hw/ppc/spapr_vio.h" 57 #include "hw/pci-host/spapr.h" 58 #include "hw/pci/msi.h" 59 60 #include "hw/pci/pci.h" 61 #include "hw/scsi/scsi.h" 62 #include "hw/virtio/virtio-scsi.h" 63 #include "hw/virtio/vhost-scsi-common.h" 64 65 #include "exec/address-spaces.h" 66 #include "exec/ram_addr.h" 67 #include "hw/usb.h" 68 #include "qemu/config-file.h" 69 #include "qemu/error-report.h" 70 #include "trace.h" 71 #include "hw/nmi.h" 72 #include "hw/intc/intc.h" 73 74 #include "qemu/cutils.h" 75 #include "hw/ppc/spapr_cpu_core.h" 76 #include "hw/mem/memory-device.h" 77 78 #include <libfdt.h> 79 80 /* SLOF memory layout: 81 * 82 * SLOF raw image loaded at 0, copies its romfs right below the flat 83 * device-tree, then position SLOF itself 31M below that 84 * 85 * So we set FW_OVERHEAD to 40MB which should account for all of that 86 * and more 87 * 88 * We load our kernel at 4M, leaving space for SLOF initial image 89 */ 90 #define FDT_MAX_SIZE 0x100000 91 #define RTAS_MAX_SIZE 0x10000 92 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 93 #define FW_MAX_SIZE 0x400000 94 #define FW_FILE_NAME "slof.bin" 95 #define FW_OVERHEAD 0x2800000 96 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 97 98 #define MIN_RMA_SLOF 128UL 99 100 #define PHANDLE_INTC 0x00001111 101 102 /* These two functions implement the VCPU id numbering: one to compute them 103 * all and one to identify thread 0 of a VCORE. Any change to the first one 104 * is likely to have an impact on the second one, so let's keep them close. 105 */ 106 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 107 { 108 assert(spapr->vsmt); 109 return 110 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 111 } 112 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 113 PowerPCCPU *cpu) 114 { 115 assert(spapr->vsmt); 116 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 117 } 118 119 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 120 { 121 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 122 * and newer QEMUs don't even have them. In both cases, we don't want 123 * to send anything on the wire. 124 */ 125 return false; 126 } 127 128 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 129 .name = "icp/server", 130 .version_id = 1, 131 .minimum_version_id = 1, 132 .needed = pre_2_10_vmstate_dummy_icp_needed, 133 .fields = (VMStateField[]) { 134 VMSTATE_UNUSED(4), /* uint32_t xirr */ 135 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 136 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 137 VMSTATE_END_OF_LIST() 138 }, 139 }; 140 141 static void pre_2_10_vmstate_register_dummy_icp(int i) 142 { 143 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 144 (void *)(uintptr_t) i); 145 } 146 147 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 148 { 149 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 150 (void *)(uintptr_t) i); 151 } 152 153 int spapr_max_server_number(SpaprMachineState *spapr) 154 { 155 assert(spapr->vsmt); 156 return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads); 157 } 158 159 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 160 int smt_threads) 161 { 162 int i, ret = 0; 163 uint32_t servers_prop[smt_threads]; 164 uint32_t gservers_prop[smt_threads * 2]; 165 int index = spapr_get_vcpu_id(cpu); 166 167 if (cpu->compat_pvr) { 168 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 169 if (ret < 0) { 170 return ret; 171 } 172 } 173 174 /* Build interrupt servers and gservers properties */ 175 for (i = 0; i < smt_threads; i++) { 176 servers_prop[i] = cpu_to_be32(index + i); 177 /* Hack, direct the group queues back to cpu 0 */ 178 gservers_prop[i*2] = cpu_to_be32(index + i); 179 gservers_prop[i*2 + 1] = 0; 180 } 181 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 182 servers_prop, sizeof(servers_prop)); 183 if (ret < 0) { 184 return ret; 185 } 186 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 187 gservers_prop, sizeof(gservers_prop)); 188 189 return ret; 190 } 191 192 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 193 { 194 int index = spapr_get_vcpu_id(cpu); 195 uint32_t associativity[] = {cpu_to_be32(0x5), 196 cpu_to_be32(0x0), 197 cpu_to_be32(0x0), 198 cpu_to_be32(0x0), 199 cpu_to_be32(cpu->node_id), 200 cpu_to_be32(index)}; 201 202 /* Advertise NUMA via ibm,associativity */ 203 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 204 sizeof(associativity)); 205 } 206 207 /* Populate the "ibm,pa-features" property */ 208 static void spapr_populate_pa_features(SpaprMachineState *spapr, 209 PowerPCCPU *cpu, 210 void *fdt, int offset, 211 bool legacy_guest) 212 { 213 uint8_t pa_features_206[] = { 6, 0, 214 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 215 uint8_t pa_features_207[] = { 24, 0, 216 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 217 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 218 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 219 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 220 uint8_t pa_features_300[] = { 66, 0, 221 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 222 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 223 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 224 /* 6: DS207 */ 225 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 226 /* 16: Vector */ 227 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 228 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 229 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 230 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 231 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 232 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 233 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 234 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 235 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 236 /* 42: PM, 44: PC RA, 46: SC vec'd */ 237 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 238 /* 48: SIMD, 50: QP BFP, 52: String */ 239 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 240 /* 54: DecFP, 56: DecI, 58: SHA */ 241 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 242 /* 60: NM atomic, 62: RNG */ 243 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 244 }; 245 uint8_t *pa_features = NULL; 246 size_t pa_size; 247 248 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 249 pa_features = pa_features_206; 250 pa_size = sizeof(pa_features_206); 251 } 252 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 253 pa_features = pa_features_207; 254 pa_size = sizeof(pa_features_207); 255 } 256 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 257 pa_features = pa_features_300; 258 pa_size = sizeof(pa_features_300); 259 } 260 if (!pa_features) { 261 return; 262 } 263 264 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 265 /* 266 * Note: we keep CI large pages off by default because a 64K capable 267 * guest provisioned with large pages might otherwise try to map a qemu 268 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 269 * even if that qemu runs on a 4k host. 270 * We dd this bit back here if we are confident this is not an issue 271 */ 272 pa_features[3] |= 0x20; 273 } 274 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 275 pa_features[24] |= 0x80; /* Transactional memory support */ 276 } 277 if (legacy_guest && pa_size > 40) { 278 /* Workaround for broken kernels that attempt (guest) radix 279 * mode when they can't handle it, if they see the radix bit set 280 * in pa-features. So hide it from them. */ 281 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 282 } 283 284 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 285 } 286 287 static int spapr_fixup_cpu_dt(void *fdt, SpaprMachineState *spapr) 288 { 289 int ret = 0, offset, cpus_offset; 290 CPUState *cs; 291 char cpu_model[32]; 292 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 293 294 CPU_FOREACH(cs) { 295 PowerPCCPU *cpu = POWERPC_CPU(cs); 296 DeviceClass *dc = DEVICE_GET_CLASS(cs); 297 int index = spapr_get_vcpu_id(cpu); 298 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 299 300 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 301 continue; 302 } 303 304 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 305 306 cpus_offset = fdt_path_offset(fdt, "/cpus"); 307 if (cpus_offset < 0) { 308 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 309 if (cpus_offset < 0) { 310 return cpus_offset; 311 } 312 } 313 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 314 if (offset < 0) { 315 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 316 if (offset < 0) { 317 return offset; 318 } 319 } 320 321 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 322 pft_size_prop, sizeof(pft_size_prop)); 323 if (ret < 0) { 324 return ret; 325 } 326 327 if (nb_numa_nodes > 1) { 328 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); 329 if (ret < 0) { 330 return ret; 331 } 332 } 333 334 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 335 if (ret < 0) { 336 return ret; 337 } 338 339 spapr_populate_pa_features(spapr, cpu, fdt, offset, 340 spapr->cas_legacy_guest_workaround); 341 } 342 return ret; 343 } 344 345 static hwaddr spapr_node0_size(MachineState *machine) 346 { 347 if (nb_numa_nodes) { 348 int i; 349 for (i = 0; i < nb_numa_nodes; ++i) { 350 if (numa_info[i].node_mem) { 351 return MIN(pow2floor(numa_info[i].node_mem), 352 machine->ram_size); 353 } 354 } 355 } 356 return machine->ram_size; 357 } 358 359 static void add_str(GString *s, const gchar *s1) 360 { 361 g_string_append_len(s, s1, strlen(s1) + 1); 362 } 363 364 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 365 hwaddr size) 366 { 367 uint32_t associativity[] = { 368 cpu_to_be32(0x4), /* length */ 369 cpu_to_be32(0x0), cpu_to_be32(0x0), 370 cpu_to_be32(0x0), cpu_to_be32(nodeid) 371 }; 372 char mem_name[32]; 373 uint64_t mem_reg_property[2]; 374 int off; 375 376 mem_reg_property[0] = cpu_to_be64(start); 377 mem_reg_property[1] = cpu_to_be64(size); 378 379 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 380 off = fdt_add_subnode(fdt, 0, mem_name); 381 _FDT(off); 382 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 383 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 384 sizeof(mem_reg_property)))); 385 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 386 sizeof(associativity)))); 387 return off; 388 } 389 390 static int spapr_populate_memory(SpaprMachineState *spapr, void *fdt) 391 { 392 MachineState *machine = MACHINE(spapr); 393 hwaddr mem_start, node_size; 394 int i, nb_nodes = nb_numa_nodes; 395 NodeInfo *nodes = numa_info; 396 NodeInfo ramnode; 397 398 /* No NUMA nodes, assume there is just one node with whole RAM */ 399 if (!nb_numa_nodes) { 400 nb_nodes = 1; 401 ramnode.node_mem = machine->ram_size; 402 nodes = &ramnode; 403 } 404 405 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 406 if (!nodes[i].node_mem) { 407 continue; 408 } 409 if (mem_start >= machine->ram_size) { 410 node_size = 0; 411 } else { 412 node_size = nodes[i].node_mem; 413 if (node_size > machine->ram_size - mem_start) { 414 node_size = machine->ram_size - mem_start; 415 } 416 } 417 if (!mem_start) { 418 /* spapr_machine_init() checks for rma_size <= node0_size 419 * already */ 420 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 421 mem_start += spapr->rma_size; 422 node_size -= spapr->rma_size; 423 } 424 for ( ; node_size; ) { 425 hwaddr sizetmp = pow2floor(node_size); 426 427 /* mem_start != 0 here */ 428 if (ctzl(mem_start) < ctzl(sizetmp)) { 429 sizetmp = 1ULL << ctzl(mem_start); 430 } 431 432 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 433 node_size -= sizetmp; 434 mem_start += sizetmp; 435 } 436 } 437 438 return 0; 439 } 440 441 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 442 SpaprMachineState *spapr) 443 { 444 PowerPCCPU *cpu = POWERPC_CPU(cs); 445 CPUPPCState *env = &cpu->env; 446 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 447 int index = spapr_get_vcpu_id(cpu); 448 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 449 0xffffffff, 0xffffffff}; 450 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 451 : SPAPR_TIMEBASE_FREQ; 452 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 453 uint32_t page_sizes_prop[64]; 454 size_t page_sizes_prop_size; 455 uint32_t vcpus_per_socket = smp_threads * smp_cores; 456 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 457 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 458 SpaprDrc *drc; 459 int drc_index; 460 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 461 int i; 462 463 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 464 if (drc) { 465 drc_index = spapr_drc_index(drc); 466 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 467 } 468 469 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 470 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 471 472 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 473 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 474 env->dcache_line_size))); 475 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 476 env->dcache_line_size))); 477 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 478 env->icache_line_size))); 479 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 480 env->icache_line_size))); 481 482 if (pcc->l1_dcache_size) { 483 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 484 pcc->l1_dcache_size))); 485 } else { 486 warn_report("Unknown L1 dcache size for cpu"); 487 } 488 if (pcc->l1_icache_size) { 489 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 490 pcc->l1_icache_size))); 491 } else { 492 warn_report("Unknown L1 icache size for cpu"); 493 } 494 495 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 496 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 497 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 498 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 499 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 500 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 501 502 if (env->spr_cb[SPR_PURR].oea_read) { 503 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 504 } 505 506 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 507 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 508 segs, sizeof(segs)))); 509 } 510 511 /* Advertise VSX (vector extensions) if available 512 * 1 == VMX / Altivec available 513 * 2 == VSX available 514 * 515 * Only CPUs for which we create core types in spapr_cpu_core.c 516 * are possible, and all of those have VMX */ 517 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 518 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 519 } else { 520 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 521 } 522 523 /* Advertise DFP (Decimal Floating Point) if available 524 * 0 / no property == no DFP 525 * 1 == DFP available */ 526 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 527 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 528 } 529 530 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 531 sizeof(page_sizes_prop)); 532 if (page_sizes_prop_size) { 533 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 534 page_sizes_prop, page_sizes_prop_size))); 535 } 536 537 spapr_populate_pa_features(spapr, cpu, fdt, offset, false); 538 539 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 540 cs->cpu_index / vcpus_per_socket))); 541 542 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 543 pft_size_prop, sizeof(pft_size_prop)))); 544 545 if (nb_numa_nodes > 1) { 546 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 547 } 548 549 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 550 551 if (pcc->radix_page_info) { 552 for (i = 0; i < pcc->radix_page_info->count; i++) { 553 radix_AP_encodings[i] = 554 cpu_to_be32(pcc->radix_page_info->entries[i]); 555 } 556 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 557 radix_AP_encodings, 558 pcc->radix_page_info->count * 559 sizeof(radix_AP_encodings[0])))); 560 } 561 562 /* 563 * We set this property to let the guest know that it can use the large 564 * decrementer and its width in bits. 565 */ 566 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 567 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 568 pcc->lrg_decr_bits))); 569 } 570 571 static void spapr_populate_cpus_dt_node(void *fdt, SpaprMachineState *spapr) 572 { 573 CPUState **rev; 574 CPUState *cs; 575 int n_cpus; 576 int cpus_offset; 577 char *nodename; 578 int i; 579 580 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 581 _FDT(cpus_offset); 582 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 583 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 584 585 /* 586 * We walk the CPUs in reverse order to ensure that CPU DT nodes 587 * created by fdt_add_subnode() end up in the right order in FDT 588 * for the guest kernel the enumerate the CPUs correctly. 589 * 590 * The CPU list cannot be traversed in reverse order, so we need 591 * to do extra work. 592 */ 593 n_cpus = 0; 594 rev = NULL; 595 CPU_FOREACH(cs) { 596 rev = g_renew(CPUState *, rev, n_cpus + 1); 597 rev[n_cpus++] = cs; 598 } 599 600 for (i = n_cpus - 1; i >= 0; i--) { 601 CPUState *cs = rev[i]; 602 PowerPCCPU *cpu = POWERPC_CPU(cs); 603 int index = spapr_get_vcpu_id(cpu); 604 DeviceClass *dc = DEVICE_GET_CLASS(cs); 605 int offset; 606 607 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 608 continue; 609 } 610 611 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 612 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 613 g_free(nodename); 614 _FDT(offset); 615 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 616 } 617 618 g_free(rev); 619 } 620 621 static int spapr_rng_populate_dt(void *fdt) 622 { 623 int node; 624 int ret; 625 626 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 627 if (node <= 0) { 628 return -1; 629 } 630 ret = fdt_setprop_string(fdt, node, "device_type", 631 "ibm,platform-facilities"); 632 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 633 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 634 635 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 636 if (node <= 0) { 637 return -1; 638 } 639 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 640 641 return ret ? -1 : 0; 642 } 643 644 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 645 { 646 MemoryDeviceInfoList *info; 647 648 for (info = list; info; info = info->next) { 649 MemoryDeviceInfo *value = info->value; 650 651 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 652 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 653 654 if (addr >= pcdimm_info->addr && 655 addr < (pcdimm_info->addr + pcdimm_info->size)) { 656 return pcdimm_info->node; 657 } 658 } 659 } 660 661 return -1; 662 } 663 664 struct sPAPRDrconfCellV2 { 665 uint32_t seq_lmbs; 666 uint64_t base_addr; 667 uint32_t drc_index; 668 uint32_t aa_index; 669 uint32_t flags; 670 } QEMU_PACKED; 671 672 typedef struct DrconfCellQueue { 673 struct sPAPRDrconfCellV2 cell; 674 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 675 } DrconfCellQueue; 676 677 static DrconfCellQueue * 678 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 679 uint32_t drc_index, uint32_t aa_index, 680 uint32_t flags) 681 { 682 DrconfCellQueue *elem; 683 684 elem = g_malloc0(sizeof(*elem)); 685 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 686 elem->cell.base_addr = cpu_to_be64(base_addr); 687 elem->cell.drc_index = cpu_to_be32(drc_index); 688 elem->cell.aa_index = cpu_to_be32(aa_index); 689 elem->cell.flags = cpu_to_be32(flags); 690 691 return elem; 692 } 693 694 /* ibm,dynamic-memory-v2 */ 695 static int spapr_populate_drmem_v2(SpaprMachineState *spapr, void *fdt, 696 int offset, MemoryDeviceInfoList *dimms) 697 { 698 MachineState *machine = MACHINE(spapr); 699 uint8_t *int_buf, *cur_index; 700 int ret; 701 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 702 uint64_t addr, cur_addr, size; 703 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 704 uint64_t mem_end = machine->device_memory->base + 705 memory_region_size(&machine->device_memory->mr); 706 uint32_t node, buf_len, nr_entries = 0; 707 SpaprDrc *drc; 708 DrconfCellQueue *elem, *next; 709 MemoryDeviceInfoList *info; 710 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 711 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 712 713 /* Entry to cover RAM and the gap area */ 714 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 715 SPAPR_LMB_FLAGS_RESERVED | 716 SPAPR_LMB_FLAGS_DRC_INVALID); 717 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 718 nr_entries++; 719 720 cur_addr = machine->device_memory->base; 721 for (info = dimms; info; info = info->next) { 722 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 723 724 addr = di->addr; 725 size = di->size; 726 node = di->node; 727 728 /* Entry for hot-pluggable area */ 729 if (cur_addr < addr) { 730 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 731 g_assert(drc); 732 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 733 cur_addr, spapr_drc_index(drc), -1, 0); 734 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 735 nr_entries++; 736 } 737 738 /* Entry for DIMM */ 739 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 740 g_assert(drc); 741 elem = spapr_get_drconf_cell(size / lmb_size, addr, 742 spapr_drc_index(drc), node, 743 SPAPR_LMB_FLAGS_ASSIGNED); 744 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 745 nr_entries++; 746 cur_addr = addr + size; 747 } 748 749 /* Entry for remaining hotpluggable area */ 750 if (cur_addr < mem_end) { 751 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 752 g_assert(drc); 753 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 754 cur_addr, spapr_drc_index(drc), -1, 0); 755 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 756 nr_entries++; 757 } 758 759 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 760 int_buf = cur_index = g_malloc0(buf_len); 761 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 762 cur_index += sizeof(nr_entries); 763 764 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 765 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 766 cur_index += sizeof(elem->cell); 767 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 768 g_free(elem); 769 } 770 771 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 772 g_free(int_buf); 773 if (ret < 0) { 774 return -1; 775 } 776 return 0; 777 } 778 779 /* ibm,dynamic-memory */ 780 static int spapr_populate_drmem_v1(SpaprMachineState *spapr, void *fdt, 781 int offset, MemoryDeviceInfoList *dimms) 782 { 783 MachineState *machine = MACHINE(spapr); 784 int i, ret; 785 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 786 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 787 uint32_t nr_lmbs = (machine->device_memory->base + 788 memory_region_size(&machine->device_memory->mr)) / 789 lmb_size; 790 uint32_t *int_buf, *cur_index, buf_len; 791 792 /* 793 * Allocate enough buffer size to fit in ibm,dynamic-memory 794 */ 795 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 796 cur_index = int_buf = g_malloc0(buf_len); 797 int_buf[0] = cpu_to_be32(nr_lmbs); 798 cur_index++; 799 for (i = 0; i < nr_lmbs; i++) { 800 uint64_t addr = i * lmb_size; 801 uint32_t *dynamic_memory = cur_index; 802 803 if (i >= device_lmb_start) { 804 SpaprDrc *drc; 805 806 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 807 g_assert(drc); 808 809 dynamic_memory[0] = cpu_to_be32(addr >> 32); 810 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 811 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 812 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 813 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 814 if (memory_region_present(get_system_memory(), addr)) { 815 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 816 } else { 817 dynamic_memory[5] = cpu_to_be32(0); 818 } 819 } else { 820 /* 821 * LMB information for RMA, boot time RAM and gap b/n RAM and 822 * device memory region -- all these are marked as reserved 823 * and as having no valid DRC. 824 */ 825 dynamic_memory[0] = cpu_to_be32(addr >> 32); 826 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 827 dynamic_memory[2] = cpu_to_be32(0); 828 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 829 dynamic_memory[4] = cpu_to_be32(-1); 830 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 831 SPAPR_LMB_FLAGS_DRC_INVALID); 832 } 833 834 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 835 } 836 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 837 g_free(int_buf); 838 if (ret < 0) { 839 return -1; 840 } 841 return 0; 842 } 843 844 /* 845 * Adds ibm,dynamic-reconfiguration-memory node. 846 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 847 * of this device tree node. 848 */ 849 static int spapr_populate_drconf_memory(SpaprMachineState *spapr, void *fdt) 850 { 851 MachineState *machine = MACHINE(spapr); 852 int ret, i, offset; 853 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 854 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 855 uint32_t *int_buf, *cur_index, buf_len; 856 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 857 MemoryDeviceInfoList *dimms = NULL; 858 859 /* 860 * Don't create the node if there is no device memory 861 */ 862 if (machine->ram_size == machine->maxram_size) { 863 return 0; 864 } 865 866 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 867 868 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 869 sizeof(prop_lmb_size)); 870 if (ret < 0) { 871 return ret; 872 } 873 874 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 875 if (ret < 0) { 876 return ret; 877 } 878 879 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 880 if (ret < 0) { 881 return ret; 882 } 883 884 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 885 dimms = qmp_memory_device_list(); 886 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 887 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); 888 } else { 889 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); 890 } 891 qapi_free_MemoryDeviceInfoList(dimms); 892 893 if (ret < 0) { 894 return ret; 895 } 896 897 /* ibm,associativity-lookup-arrays */ 898 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 899 cur_index = int_buf = g_malloc0(buf_len); 900 int_buf[0] = cpu_to_be32(nr_nodes); 901 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 902 cur_index += 2; 903 for (i = 0; i < nr_nodes; i++) { 904 uint32_t associativity[] = { 905 cpu_to_be32(0x0), 906 cpu_to_be32(0x0), 907 cpu_to_be32(0x0), 908 cpu_to_be32(i) 909 }; 910 memcpy(cur_index, associativity, sizeof(associativity)); 911 cur_index += 4; 912 } 913 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 914 (cur_index - int_buf) * sizeof(uint32_t)); 915 g_free(int_buf); 916 917 return ret; 918 } 919 920 static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt, 921 SpaprOptionVector *ov5_updates) 922 { 923 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 924 int ret = 0, offset; 925 926 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 927 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 928 g_assert(smc->dr_lmb_enabled); 929 ret = spapr_populate_drconf_memory(spapr, fdt); 930 if (ret) { 931 goto out; 932 } 933 } 934 935 offset = fdt_path_offset(fdt, "/chosen"); 936 if (offset < 0) { 937 offset = fdt_add_subnode(fdt, 0, "chosen"); 938 if (offset < 0) { 939 return offset; 940 } 941 } 942 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 943 "ibm,architecture-vec-5"); 944 945 out: 946 return ret; 947 } 948 949 static bool spapr_hotplugged_dev_before_cas(void) 950 { 951 Object *drc_container, *obj; 952 ObjectProperty *prop; 953 ObjectPropertyIterator iter; 954 955 drc_container = container_get(object_get_root(), "/dr-connector"); 956 object_property_iter_init(&iter, drc_container); 957 while ((prop = object_property_iter_next(&iter))) { 958 if (!strstart(prop->type, "link<", NULL)) { 959 continue; 960 } 961 obj = object_property_get_link(drc_container, prop->name, NULL); 962 if (spapr_drc_needed(obj)) { 963 return true; 964 } 965 } 966 return false; 967 } 968 969 int spapr_h_cas_compose_response(SpaprMachineState *spapr, 970 target_ulong addr, target_ulong size, 971 SpaprOptionVector *ov5_updates) 972 { 973 void *fdt, *fdt_skel; 974 SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 975 976 if (spapr_hotplugged_dev_before_cas()) { 977 return 1; 978 } 979 980 if (size < sizeof(hdr) || size > FW_MAX_SIZE) { 981 error_report("SLOF provided an unexpected CAS buffer size " 982 TARGET_FMT_lu " (min: %zu, max: %u)", 983 size, sizeof(hdr), FW_MAX_SIZE); 984 exit(EXIT_FAILURE); 985 } 986 987 size -= sizeof(hdr); 988 989 /* Create skeleton */ 990 fdt_skel = g_malloc0(size); 991 _FDT((fdt_create(fdt_skel, size))); 992 _FDT((fdt_finish_reservemap(fdt_skel))); 993 _FDT((fdt_begin_node(fdt_skel, ""))); 994 _FDT((fdt_end_node(fdt_skel))); 995 _FDT((fdt_finish(fdt_skel))); 996 fdt = g_malloc0(size); 997 _FDT((fdt_open_into(fdt_skel, fdt, size))); 998 g_free(fdt_skel); 999 1000 /* Fixup cpu nodes */ 1001 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 1002 1003 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 1004 return -1; 1005 } 1006 1007 /* Pack resulting tree */ 1008 _FDT((fdt_pack(fdt))); 1009 1010 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 1011 trace_spapr_cas_failed(size); 1012 return -1; 1013 } 1014 1015 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 1016 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 1017 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 1018 g_free(fdt); 1019 1020 return 0; 1021 } 1022 1023 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 1024 { 1025 int rtas; 1026 GString *hypertas = g_string_sized_new(256); 1027 GString *qemu_hypertas = g_string_sized_new(256); 1028 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 1029 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 1030 memory_region_size(&MACHINE(spapr)->device_memory->mr); 1031 uint32_t lrdr_capacity[] = { 1032 cpu_to_be32(max_device_addr >> 32), 1033 cpu_to_be32(max_device_addr & 0xffffffff), 1034 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 1035 cpu_to_be32(max_cpus / smp_threads), 1036 }; 1037 uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0); 1038 uint32_t maxdomains[] = { 1039 cpu_to_be32(4), 1040 maxdomain, 1041 maxdomain, 1042 maxdomain, 1043 cpu_to_be32(spapr->gpu_numa_id), 1044 }; 1045 1046 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 1047 1048 /* hypertas */ 1049 add_str(hypertas, "hcall-pft"); 1050 add_str(hypertas, "hcall-term"); 1051 add_str(hypertas, "hcall-dabr"); 1052 add_str(hypertas, "hcall-interrupt"); 1053 add_str(hypertas, "hcall-tce"); 1054 add_str(hypertas, "hcall-vio"); 1055 add_str(hypertas, "hcall-splpar"); 1056 add_str(hypertas, "hcall-bulk"); 1057 add_str(hypertas, "hcall-set-mode"); 1058 add_str(hypertas, "hcall-sprg0"); 1059 add_str(hypertas, "hcall-copy"); 1060 add_str(hypertas, "hcall-debug"); 1061 add_str(hypertas, "hcall-vphn"); 1062 add_str(qemu_hypertas, "hcall-memop1"); 1063 1064 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 1065 add_str(hypertas, "hcall-multi-tce"); 1066 } 1067 1068 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 1069 add_str(hypertas, "hcall-hpt-resize"); 1070 } 1071 1072 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 1073 hypertas->str, hypertas->len)); 1074 g_string_free(hypertas, TRUE); 1075 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 1076 qemu_hypertas->str, qemu_hypertas->len)); 1077 g_string_free(qemu_hypertas, TRUE); 1078 1079 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 1080 refpoints, sizeof(refpoints))); 1081 1082 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 1083 maxdomains, sizeof(maxdomains))); 1084 1085 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 1086 RTAS_ERROR_LOG_MAX)); 1087 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 1088 RTAS_EVENT_SCAN_RATE)); 1089 1090 g_assert(msi_nonbroken); 1091 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 1092 1093 /* 1094 * According to PAPR, rtas ibm,os-term does not guarantee a return 1095 * back to the guest cpu. 1096 * 1097 * While an additional ibm,extended-os-term property indicates 1098 * that rtas call return will always occur. Set this property. 1099 */ 1100 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 1101 1102 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 1103 lrdr_capacity, sizeof(lrdr_capacity))); 1104 1105 spapr_dt_rtas_tokens(fdt, rtas); 1106 } 1107 1108 /* 1109 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 1110 * and the XIVE features that the guest may request and thus the valid 1111 * values for bytes 23..26 of option vector 5: 1112 */ 1113 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 1114 int chosen) 1115 { 1116 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1117 1118 char val[2 * 4] = { 1119 23, spapr->irq->ov5, /* Xive mode. */ 1120 24, 0x00, /* Hash/Radix, filled in below. */ 1121 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1122 26, 0x40, /* Radix options: GTSE == yes. */ 1123 }; 1124 1125 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1126 first_ppc_cpu->compat_pvr)) { 1127 /* 1128 * If we're in a pre POWER9 compat mode then the guest should 1129 * do hash and use the legacy interrupt mode 1130 */ 1131 val[1] = 0x00; /* XICS */ 1132 val[3] = 0x00; /* Hash */ 1133 } else if (kvm_enabled()) { 1134 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1135 val[3] = 0x80; /* OV5_MMU_BOTH */ 1136 } else if (kvmppc_has_cap_mmu_radix()) { 1137 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1138 } else { 1139 val[3] = 0x00; /* Hash */ 1140 } 1141 } else { 1142 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1143 val[3] = 0xC0; 1144 } 1145 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1146 val, sizeof(val))); 1147 } 1148 1149 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt) 1150 { 1151 MachineState *machine = MACHINE(spapr); 1152 int chosen; 1153 const char *boot_device = machine->boot_order; 1154 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1155 size_t cb = 0; 1156 char *bootlist = get_boot_devices_list(&cb); 1157 1158 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1159 1160 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 1161 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1162 spapr->initrd_base)); 1163 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1164 spapr->initrd_base + spapr->initrd_size)); 1165 1166 if (spapr->kernel_size) { 1167 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 1168 cpu_to_be64(spapr->kernel_size) }; 1169 1170 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1171 &kprop, sizeof(kprop))); 1172 if (spapr->kernel_le) { 1173 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1174 } 1175 } 1176 if (boot_menu) { 1177 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1178 } 1179 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1180 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1181 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1182 1183 if (cb && bootlist) { 1184 int i; 1185 1186 for (i = 0; i < cb; i++) { 1187 if (bootlist[i] == '\n') { 1188 bootlist[i] = ' '; 1189 } 1190 } 1191 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1192 } 1193 1194 if (boot_device && strlen(boot_device)) { 1195 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1196 } 1197 1198 if (!spapr->has_graphics && stdout_path) { 1199 /* 1200 * "linux,stdout-path" and "stdout" properties are deprecated by linux 1201 * kernel. New platforms should only use the "stdout-path" property. Set 1202 * the new property and continue using older property to remain 1203 * compatible with the existing firmware. 1204 */ 1205 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1206 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1207 } 1208 1209 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1210 1211 g_free(stdout_path); 1212 g_free(bootlist); 1213 } 1214 1215 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1216 { 1217 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1218 * KVM to work under pHyp with some guest co-operation */ 1219 int hypervisor; 1220 uint8_t hypercall[16]; 1221 1222 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1223 /* indicate KVM hypercall interface */ 1224 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1225 if (kvmppc_has_cap_fixup_hcalls()) { 1226 /* 1227 * Older KVM versions with older guest kernels were broken 1228 * with the magic page, don't allow the guest to map it. 1229 */ 1230 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1231 sizeof(hypercall))) { 1232 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1233 hypercall, sizeof(hypercall))); 1234 } 1235 } 1236 } 1237 1238 static void *spapr_build_fdt(SpaprMachineState *spapr) 1239 { 1240 MachineState *machine = MACHINE(spapr); 1241 MachineClass *mc = MACHINE_GET_CLASS(machine); 1242 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1243 int ret; 1244 void *fdt; 1245 SpaprPhbState *phb; 1246 char *buf; 1247 1248 fdt = g_malloc0(FDT_MAX_SIZE); 1249 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 1250 1251 /* Root node */ 1252 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1253 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1254 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1255 1256 /* Guest UUID & Name*/ 1257 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1258 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1259 if (qemu_uuid_set) { 1260 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1261 } 1262 g_free(buf); 1263 1264 if (qemu_get_vm_name()) { 1265 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1266 qemu_get_vm_name())); 1267 } 1268 1269 /* Host Model & Serial Number */ 1270 if (spapr->host_model) { 1271 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1272 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1273 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1274 g_free(buf); 1275 } 1276 1277 if (spapr->host_serial) { 1278 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1279 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1280 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1281 g_free(buf); 1282 } 1283 1284 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1285 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1286 1287 /* /interrupt controller */ 1288 spapr->irq->dt_populate(spapr, spapr_max_server_number(spapr), fdt, 1289 PHANDLE_INTC); 1290 1291 ret = spapr_populate_memory(spapr, fdt); 1292 if (ret < 0) { 1293 error_report("couldn't setup memory nodes in fdt"); 1294 exit(1); 1295 } 1296 1297 /* /vdevice */ 1298 spapr_dt_vdevice(spapr->vio_bus, fdt); 1299 1300 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1301 ret = spapr_rng_populate_dt(fdt); 1302 if (ret < 0) { 1303 error_report("could not set up rng device in the fdt"); 1304 exit(1); 1305 } 1306 } 1307 1308 QLIST_FOREACH(phb, &spapr->phbs, list) { 1309 ret = spapr_populate_pci_dt(phb, PHANDLE_INTC, fdt, 1310 spapr->irq->nr_msis, NULL); 1311 if (ret < 0) { 1312 error_report("couldn't setup PCI devices in fdt"); 1313 exit(1); 1314 } 1315 } 1316 1317 /* cpus */ 1318 spapr_populate_cpus_dt_node(fdt, spapr); 1319 1320 if (smc->dr_lmb_enabled) { 1321 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1322 } 1323 1324 if (mc->has_hotpluggable_cpus) { 1325 int offset = fdt_path_offset(fdt, "/cpus"); 1326 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1327 SPAPR_DR_CONNECTOR_TYPE_CPU); 1328 if (ret < 0) { 1329 error_report("Couldn't set up CPU DR device tree properties"); 1330 exit(1); 1331 } 1332 } 1333 1334 /* /event-sources */ 1335 spapr_dt_events(spapr, fdt); 1336 1337 /* /rtas */ 1338 spapr_dt_rtas(spapr, fdt); 1339 1340 /* /chosen */ 1341 spapr_dt_chosen(spapr, fdt); 1342 1343 /* /hypervisor */ 1344 if (kvm_enabled()) { 1345 spapr_dt_hypervisor(spapr, fdt); 1346 } 1347 1348 /* Build memory reserve map */ 1349 if (spapr->kernel_size) { 1350 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1351 } 1352 if (spapr->initrd_size) { 1353 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1354 } 1355 1356 /* ibm,client-architecture-support updates */ 1357 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1358 if (ret < 0) { 1359 error_report("couldn't setup CAS properties fdt"); 1360 exit(1); 1361 } 1362 1363 if (smc->dr_phb_enabled) { 1364 ret = spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB); 1365 if (ret < 0) { 1366 error_report("Couldn't set up PHB DR device tree properties"); 1367 exit(1); 1368 } 1369 } 1370 1371 return fdt; 1372 } 1373 1374 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1375 { 1376 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1377 } 1378 1379 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1380 PowerPCCPU *cpu) 1381 { 1382 CPUPPCState *env = &cpu->env; 1383 1384 /* The TCG path should also be holding the BQL at this point */ 1385 g_assert(qemu_mutex_iothread_locked()); 1386 1387 if (msr_pr) { 1388 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1389 env->gpr[3] = H_PRIVILEGE; 1390 } else { 1391 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1392 } 1393 } 1394 1395 struct LPCRSyncState { 1396 target_ulong value; 1397 target_ulong mask; 1398 }; 1399 1400 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1401 { 1402 struct LPCRSyncState *s = arg.host_ptr; 1403 PowerPCCPU *cpu = POWERPC_CPU(cs); 1404 CPUPPCState *env = &cpu->env; 1405 target_ulong lpcr; 1406 1407 cpu_synchronize_state(cs); 1408 lpcr = env->spr[SPR_LPCR]; 1409 lpcr &= ~s->mask; 1410 lpcr |= s->value; 1411 ppc_store_lpcr(cpu, lpcr); 1412 } 1413 1414 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1415 { 1416 CPUState *cs; 1417 struct LPCRSyncState s = { 1418 .value = value, 1419 .mask = mask 1420 }; 1421 CPU_FOREACH(cs) { 1422 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1423 } 1424 } 1425 1426 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1427 { 1428 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1429 1430 /* Copy PATE1:GR into PATE0:HR */ 1431 entry->dw0 = spapr->patb_entry & PATE0_HR; 1432 entry->dw1 = spapr->patb_entry; 1433 } 1434 1435 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1436 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1437 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1438 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1439 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1440 1441 /* 1442 * Get the fd to access the kernel htab, re-opening it if necessary 1443 */ 1444 static int get_htab_fd(SpaprMachineState *spapr) 1445 { 1446 Error *local_err = NULL; 1447 1448 if (spapr->htab_fd >= 0) { 1449 return spapr->htab_fd; 1450 } 1451 1452 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1453 if (spapr->htab_fd < 0) { 1454 error_report_err(local_err); 1455 } 1456 1457 return spapr->htab_fd; 1458 } 1459 1460 void close_htab_fd(SpaprMachineState *spapr) 1461 { 1462 if (spapr->htab_fd >= 0) { 1463 close(spapr->htab_fd); 1464 } 1465 spapr->htab_fd = -1; 1466 } 1467 1468 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1469 { 1470 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1471 1472 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1473 } 1474 1475 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1476 { 1477 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1478 1479 assert(kvm_enabled()); 1480 1481 if (!spapr->htab) { 1482 return 0; 1483 } 1484 1485 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1486 } 1487 1488 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1489 hwaddr ptex, int n) 1490 { 1491 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1492 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1493 1494 if (!spapr->htab) { 1495 /* 1496 * HTAB is controlled by KVM. Fetch into temporary buffer 1497 */ 1498 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1499 kvmppc_read_hptes(hptes, ptex, n); 1500 return hptes; 1501 } 1502 1503 /* 1504 * HTAB is controlled by QEMU. Just point to the internally 1505 * accessible PTEG. 1506 */ 1507 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1508 } 1509 1510 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1511 const ppc_hash_pte64_t *hptes, 1512 hwaddr ptex, int n) 1513 { 1514 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1515 1516 if (!spapr->htab) { 1517 g_free((void *)hptes); 1518 } 1519 1520 /* Nothing to do for qemu managed HPT */ 1521 } 1522 1523 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1524 uint64_t pte0, uint64_t pte1) 1525 { 1526 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1527 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1528 1529 if (!spapr->htab) { 1530 kvmppc_write_hpte(ptex, pte0, pte1); 1531 } else { 1532 if (pte0 & HPTE64_V_VALID) { 1533 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1534 /* 1535 * When setting valid, we write PTE1 first. This ensures 1536 * proper synchronization with the reading code in 1537 * ppc_hash64_pteg_search() 1538 */ 1539 smp_wmb(); 1540 stq_p(spapr->htab + offset, pte0); 1541 } else { 1542 stq_p(spapr->htab + offset, pte0); 1543 /* 1544 * When clearing it we set PTE0 first. This ensures proper 1545 * synchronization with the reading code in 1546 * ppc_hash64_pteg_search() 1547 */ 1548 smp_wmb(); 1549 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1550 } 1551 } 1552 } 1553 1554 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1555 { 1556 int shift; 1557 1558 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1559 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1560 * that's much more than is needed for Linux guests */ 1561 shift = ctz64(pow2ceil(ramsize)) - 7; 1562 shift = MAX(shift, 18); /* Minimum architected size */ 1563 shift = MIN(shift, 46); /* Maximum architected size */ 1564 return shift; 1565 } 1566 1567 void spapr_free_hpt(SpaprMachineState *spapr) 1568 { 1569 g_free(spapr->htab); 1570 spapr->htab = NULL; 1571 spapr->htab_shift = 0; 1572 close_htab_fd(spapr); 1573 } 1574 1575 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 1576 Error **errp) 1577 { 1578 long rc; 1579 1580 /* Clean up any HPT info from a previous boot */ 1581 spapr_free_hpt(spapr); 1582 1583 rc = kvmppc_reset_htab(shift); 1584 if (rc < 0) { 1585 /* kernel-side HPT needed, but couldn't allocate one */ 1586 error_setg_errno(errp, errno, 1587 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1588 shift); 1589 /* This is almost certainly fatal, but if the caller really 1590 * wants to carry on with shift == 0, it's welcome to try */ 1591 } else if (rc > 0) { 1592 /* kernel-side HPT allocated */ 1593 if (rc != shift) { 1594 error_setg(errp, 1595 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1596 shift, rc); 1597 } 1598 1599 spapr->htab_shift = shift; 1600 spapr->htab = NULL; 1601 } else { 1602 /* kernel-side HPT not needed, allocate in userspace instead */ 1603 size_t size = 1ULL << shift; 1604 int i; 1605 1606 spapr->htab = qemu_memalign(size, size); 1607 if (!spapr->htab) { 1608 error_setg_errno(errp, errno, 1609 "Could not allocate HPT of order %d", shift); 1610 return; 1611 } 1612 1613 memset(spapr->htab, 0, size); 1614 spapr->htab_shift = shift; 1615 1616 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1617 DIRTY_HPTE(HPTE(spapr->htab, i)); 1618 } 1619 } 1620 /* We're setting up a hash table, so that means we're not radix */ 1621 spapr->patb_entry = 0; 1622 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1623 } 1624 1625 void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr) 1626 { 1627 int hpt_shift; 1628 1629 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1630 || (spapr->cas_reboot 1631 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1632 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1633 } else { 1634 uint64_t current_ram_size; 1635 1636 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1637 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1638 } 1639 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1640 1641 if (spapr->vrma_adjust) { 1642 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), 1643 spapr->htab_shift); 1644 } 1645 } 1646 1647 static int spapr_reset_drcs(Object *child, void *opaque) 1648 { 1649 SpaprDrc *drc = 1650 (SpaprDrc *) object_dynamic_cast(child, 1651 TYPE_SPAPR_DR_CONNECTOR); 1652 1653 if (drc) { 1654 spapr_drc_reset(drc); 1655 } 1656 1657 return 0; 1658 } 1659 1660 static void spapr_machine_reset(void) 1661 { 1662 MachineState *machine = MACHINE(qdev_get_machine()); 1663 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1664 PowerPCCPU *first_ppc_cpu; 1665 uint32_t rtas_limit; 1666 hwaddr rtas_addr, fdt_addr; 1667 void *fdt; 1668 int rc; 1669 1670 spapr_caps_apply(spapr); 1671 1672 first_ppc_cpu = POWERPC_CPU(first_cpu); 1673 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1674 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1675 spapr->max_compat_pvr)) { 1676 /* 1677 * If using KVM with radix mode available, VCPUs can be started 1678 * without a HPT because KVM will start them in radix mode. 1679 * Set the GR bit in PATE so that we know there is no HPT. 1680 */ 1681 spapr->patb_entry = PATE1_GR; 1682 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1683 } else { 1684 spapr_setup_hpt_and_vrma(spapr); 1685 } 1686 1687 /* 1688 * If this reset wasn't generated by CAS, we should reset our 1689 * negotiated options and start from scratch 1690 */ 1691 if (!spapr->cas_reboot) { 1692 spapr_ovec_cleanup(spapr->ov5_cas); 1693 spapr->ov5_cas = spapr_ovec_new(); 1694 1695 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal); 1696 } 1697 1698 if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 1699 spapr_irq_msi_reset(spapr); 1700 } 1701 1702 /* 1703 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. 1704 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is 1705 * called from vPHB reset handler so we initialize the counter here. 1706 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM 1707 * must be equally distant from any other node. 1708 * The final value of spapr->gpu_numa_id is going to be written to 1709 * max-associativity-domains in spapr_build_fdt(). 1710 */ 1711 spapr->gpu_numa_id = MAX(1, nb_numa_nodes); 1712 qemu_devices_reset(); 1713 1714 /* 1715 * This is fixing some of the default configuration of the XIVE 1716 * devices. To be called after the reset of the machine devices. 1717 */ 1718 spapr_irq_reset(spapr, &error_fatal); 1719 1720 /* 1721 * There is no CAS under qtest. Simulate one to please the code that 1722 * depends on spapr->ov5_cas. This is especially needed to test device 1723 * unplug, so we do that before resetting the DRCs. 1724 */ 1725 if (qtest_enabled()) { 1726 spapr_ovec_cleanup(spapr->ov5_cas); 1727 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1728 } 1729 1730 /* DRC reset may cause a device to be unplugged. This will cause troubles 1731 * if this device is used by another device (eg, a running vhost backend 1732 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1733 * situations, we reset DRCs after all devices have been reset. 1734 */ 1735 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1736 1737 spapr_clear_pending_events(spapr); 1738 1739 /* 1740 * We place the device tree and RTAS just below either the top of the RMA, 1741 * or just below 2GB, whichever is lower, so that it can be 1742 * processed with 32-bit real mode code if necessary 1743 */ 1744 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1745 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1746 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1747 1748 fdt = spapr_build_fdt(spapr); 1749 1750 spapr_load_rtas(spapr, fdt, rtas_addr); 1751 1752 rc = fdt_pack(fdt); 1753 1754 /* Should only fail if we've built a corrupted tree */ 1755 assert(rc == 0); 1756 1757 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1758 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1759 fdt_totalsize(fdt), FDT_MAX_SIZE); 1760 exit(1); 1761 } 1762 1763 /* Load the fdt */ 1764 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1765 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1766 g_free(spapr->fdt_blob); 1767 spapr->fdt_size = fdt_totalsize(fdt); 1768 spapr->fdt_initial_size = spapr->fdt_size; 1769 spapr->fdt_blob = fdt; 1770 1771 /* Set up the entry state */ 1772 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); 1773 first_ppc_cpu->env.gpr[5] = 0; 1774 1775 spapr->cas_reboot = false; 1776 } 1777 1778 static void spapr_create_nvram(SpaprMachineState *spapr) 1779 { 1780 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1781 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1782 1783 if (dinfo) { 1784 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1785 &error_fatal); 1786 } 1787 1788 qdev_init_nofail(dev); 1789 1790 spapr->nvram = (struct SpaprNvram *)dev; 1791 } 1792 1793 static void spapr_rtc_create(SpaprMachineState *spapr) 1794 { 1795 object_initialize_child(OBJECT(spapr), "rtc", 1796 &spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1797 &error_fatal, NULL); 1798 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1799 &error_fatal); 1800 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1801 "date", &error_fatal); 1802 } 1803 1804 /* Returns whether we want to use VGA or not */ 1805 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1806 { 1807 switch (vga_interface_type) { 1808 case VGA_NONE: 1809 return false; 1810 case VGA_DEVICE: 1811 return true; 1812 case VGA_STD: 1813 case VGA_VIRTIO: 1814 case VGA_CIRRUS: 1815 return pci_vga_init(pci_bus) != NULL; 1816 default: 1817 error_setg(errp, 1818 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1819 return false; 1820 } 1821 } 1822 1823 static int spapr_pre_load(void *opaque) 1824 { 1825 int rc; 1826 1827 rc = spapr_caps_pre_load(opaque); 1828 if (rc) { 1829 return rc; 1830 } 1831 1832 return 0; 1833 } 1834 1835 static int spapr_post_load(void *opaque, int version_id) 1836 { 1837 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1838 int err = 0; 1839 1840 err = spapr_caps_post_migration(spapr); 1841 if (err) { 1842 return err; 1843 } 1844 1845 /* 1846 * In earlier versions, there was no separate qdev for the PAPR 1847 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1848 * So when migrating from those versions, poke the incoming offset 1849 * value into the RTC device 1850 */ 1851 if (version_id < 3) { 1852 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1853 if (err) { 1854 return err; 1855 } 1856 } 1857 1858 if (kvm_enabled() && spapr->patb_entry) { 1859 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1860 bool radix = !!(spapr->patb_entry & PATE1_GR); 1861 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1862 1863 /* 1864 * Update LPCR:HR and UPRT as they may not be set properly in 1865 * the stream 1866 */ 1867 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1868 LPCR_HR | LPCR_UPRT); 1869 1870 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1871 if (err) { 1872 error_report("Process table config unsupported by the host"); 1873 return -EINVAL; 1874 } 1875 } 1876 1877 err = spapr_irq_post_load(spapr, version_id); 1878 if (err) { 1879 return err; 1880 } 1881 1882 return err; 1883 } 1884 1885 static int spapr_pre_save(void *opaque) 1886 { 1887 int rc; 1888 1889 rc = spapr_caps_pre_save(opaque); 1890 if (rc) { 1891 return rc; 1892 } 1893 1894 return 0; 1895 } 1896 1897 static bool version_before_3(void *opaque, int version_id) 1898 { 1899 return version_id < 3; 1900 } 1901 1902 static bool spapr_pending_events_needed(void *opaque) 1903 { 1904 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1905 return !QTAILQ_EMPTY(&spapr->pending_events); 1906 } 1907 1908 static const VMStateDescription vmstate_spapr_event_entry = { 1909 .name = "spapr_event_log_entry", 1910 .version_id = 1, 1911 .minimum_version_id = 1, 1912 .fields = (VMStateField[]) { 1913 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1914 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1915 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1916 NULL, extended_length), 1917 VMSTATE_END_OF_LIST() 1918 }, 1919 }; 1920 1921 static const VMStateDescription vmstate_spapr_pending_events = { 1922 .name = "spapr_pending_events", 1923 .version_id = 1, 1924 .minimum_version_id = 1, 1925 .needed = spapr_pending_events_needed, 1926 .fields = (VMStateField[]) { 1927 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1928 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1929 VMSTATE_END_OF_LIST() 1930 }, 1931 }; 1932 1933 static bool spapr_ov5_cas_needed(void *opaque) 1934 { 1935 SpaprMachineState *spapr = opaque; 1936 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1937 SpaprOptionVector *ov5_legacy = spapr_ovec_new(); 1938 SpaprOptionVector *ov5_removed = spapr_ovec_new(); 1939 bool cas_needed; 1940 1941 /* Prior to the introduction of SpaprOptionVector, we had two option 1942 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1943 * Both of these options encode machine topology into the device-tree 1944 * in such a way that the now-booted OS should still be able to interact 1945 * appropriately with QEMU regardless of what options were actually 1946 * negotiatied on the source side. 1947 * 1948 * As such, we can avoid migrating the CAS-negotiated options if these 1949 * are the only options available on the current machine/platform. 1950 * Since these are the only options available for pseries-2.7 and 1951 * earlier, this allows us to maintain old->new/new->old migration 1952 * compatibility. 1953 * 1954 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1955 * via default pseries-2.8 machines and explicit command-line parameters. 1956 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1957 * of the actual CAS-negotiated values to continue working properly. For 1958 * example, availability of memory unplug depends on knowing whether 1959 * OV5_HP_EVT was negotiated via CAS. 1960 * 1961 * Thus, for any cases where the set of available CAS-negotiatable 1962 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1963 * include the CAS-negotiated options in the migration stream, unless 1964 * if they affect boot time behaviour only. 1965 */ 1966 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1967 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1968 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1969 1970 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1971 * the mask itself since in the future it's possible "legacy" bits may be 1972 * removed via machine options, which could generate a false positive 1973 * that breaks migration. 1974 */ 1975 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1976 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1977 1978 spapr_ovec_cleanup(ov5_mask); 1979 spapr_ovec_cleanup(ov5_legacy); 1980 spapr_ovec_cleanup(ov5_removed); 1981 1982 return cas_needed; 1983 } 1984 1985 static const VMStateDescription vmstate_spapr_ov5_cas = { 1986 .name = "spapr_option_vector_ov5_cas", 1987 .version_id = 1, 1988 .minimum_version_id = 1, 1989 .needed = spapr_ov5_cas_needed, 1990 .fields = (VMStateField[]) { 1991 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1992 vmstate_spapr_ovec, SpaprOptionVector), 1993 VMSTATE_END_OF_LIST() 1994 }, 1995 }; 1996 1997 static bool spapr_patb_entry_needed(void *opaque) 1998 { 1999 SpaprMachineState *spapr = opaque; 2000 2001 return !!spapr->patb_entry; 2002 } 2003 2004 static const VMStateDescription vmstate_spapr_patb_entry = { 2005 .name = "spapr_patb_entry", 2006 .version_id = 1, 2007 .minimum_version_id = 1, 2008 .needed = spapr_patb_entry_needed, 2009 .fields = (VMStateField[]) { 2010 VMSTATE_UINT64(patb_entry, SpaprMachineState), 2011 VMSTATE_END_OF_LIST() 2012 }, 2013 }; 2014 2015 static bool spapr_irq_map_needed(void *opaque) 2016 { 2017 SpaprMachineState *spapr = opaque; 2018 2019 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 2020 } 2021 2022 static const VMStateDescription vmstate_spapr_irq_map = { 2023 .name = "spapr_irq_map", 2024 .version_id = 1, 2025 .minimum_version_id = 1, 2026 .needed = spapr_irq_map_needed, 2027 .fields = (VMStateField[]) { 2028 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 2029 VMSTATE_END_OF_LIST() 2030 }, 2031 }; 2032 2033 static bool spapr_dtb_needed(void *opaque) 2034 { 2035 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 2036 2037 return smc->update_dt_enabled; 2038 } 2039 2040 static int spapr_dtb_pre_load(void *opaque) 2041 { 2042 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2043 2044 g_free(spapr->fdt_blob); 2045 spapr->fdt_blob = NULL; 2046 spapr->fdt_size = 0; 2047 2048 return 0; 2049 } 2050 2051 static const VMStateDescription vmstate_spapr_dtb = { 2052 .name = "spapr_dtb", 2053 .version_id = 1, 2054 .minimum_version_id = 1, 2055 .needed = spapr_dtb_needed, 2056 .pre_load = spapr_dtb_pre_load, 2057 .fields = (VMStateField[]) { 2058 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 2059 VMSTATE_UINT32(fdt_size, SpaprMachineState), 2060 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 2061 fdt_size), 2062 VMSTATE_END_OF_LIST() 2063 }, 2064 }; 2065 2066 static const VMStateDescription vmstate_spapr = { 2067 .name = "spapr", 2068 .version_id = 3, 2069 .minimum_version_id = 1, 2070 .pre_load = spapr_pre_load, 2071 .post_load = spapr_post_load, 2072 .pre_save = spapr_pre_save, 2073 .fields = (VMStateField[]) { 2074 /* used to be @next_irq */ 2075 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2076 2077 /* RTC offset */ 2078 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2079 2080 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2081 VMSTATE_END_OF_LIST() 2082 }, 2083 .subsections = (const VMStateDescription*[]) { 2084 &vmstate_spapr_ov5_cas, 2085 &vmstate_spapr_patb_entry, 2086 &vmstate_spapr_pending_events, 2087 &vmstate_spapr_cap_htm, 2088 &vmstate_spapr_cap_vsx, 2089 &vmstate_spapr_cap_dfp, 2090 &vmstate_spapr_cap_cfpc, 2091 &vmstate_spapr_cap_sbbc, 2092 &vmstate_spapr_cap_ibs, 2093 &vmstate_spapr_irq_map, 2094 &vmstate_spapr_cap_nested_kvm_hv, 2095 &vmstate_spapr_dtb, 2096 &vmstate_spapr_cap_large_decr, 2097 &vmstate_spapr_cap_ccf_assist, 2098 NULL 2099 } 2100 }; 2101 2102 static int htab_save_setup(QEMUFile *f, void *opaque) 2103 { 2104 SpaprMachineState *spapr = opaque; 2105 2106 /* "Iteration" header */ 2107 if (!spapr->htab_shift) { 2108 qemu_put_be32(f, -1); 2109 } else { 2110 qemu_put_be32(f, spapr->htab_shift); 2111 } 2112 2113 if (spapr->htab) { 2114 spapr->htab_save_index = 0; 2115 spapr->htab_first_pass = true; 2116 } else { 2117 if (spapr->htab_shift) { 2118 assert(kvm_enabled()); 2119 } 2120 } 2121 2122 2123 return 0; 2124 } 2125 2126 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2127 int chunkstart, int n_valid, int n_invalid) 2128 { 2129 qemu_put_be32(f, chunkstart); 2130 qemu_put_be16(f, n_valid); 2131 qemu_put_be16(f, n_invalid); 2132 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2133 HASH_PTE_SIZE_64 * n_valid); 2134 } 2135 2136 static void htab_save_end_marker(QEMUFile *f) 2137 { 2138 qemu_put_be32(f, 0); 2139 qemu_put_be16(f, 0); 2140 qemu_put_be16(f, 0); 2141 } 2142 2143 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2144 int64_t max_ns) 2145 { 2146 bool has_timeout = max_ns != -1; 2147 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2148 int index = spapr->htab_save_index; 2149 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2150 2151 assert(spapr->htab_first_pass); 2152 2153 do { 2154 int chunkstart; 2155 2156 /* Consume invalid HPTEs */ 2157 while ((index < htabslots) 2158 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2159 CLEAN_HPTE(HPTE(spapr->htab, index)); 2160 index++; 2161 } 2162 2163 /* Consume valid HPTEs */ 2164 chunkstart = index; 2165 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2166 && HPTE_VALID(HPTE(spapr->htab, index))) { 2167 CLEAN_HPTE(HPTE(spapr->htab, index)); 2168 index++; 2169 } 2170 2171 if (index > chunkstart) { 2172 int n_valid = index - chunkstart; 2173 2174 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2175 2176 if (has_timeout && 2177 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2178 break; 2179 } 2180 } 2181 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2182 2183 if (index >= htabslots) { 2184 assert(index == htabslots); 2185 index = 0; 2186 spapr->htab_first_pass = false; 2187 } 2188 spapr->htab_save_index = index; 2189 } 2190 2191 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2192 int64_t max_ns) 2193 { 2194 bool final = max_ns < 0; 2195 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2196 int examined = 0, sent = 0; 2197 int index = spapr->htab_save_index; 2198 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2199 2200 assert(!spapr->htab_first_pass); 2201 2202 do { 2203 int chunkstart, invalidstart; 2204 2205 /* Consume non-dirty HPTEs */ 2206 while ((index < htabslots) 2207 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2208 index++; 2209 examined++; 2210 } 2211 2212 chunkstart = index; 2213 /* Consume valid dirty HPTEs */ 2214 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2215 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2216 && HPTE_VALID(HPTE(spapr->htab, index))) { 2217 CLEAN_HPTE(HPTE(spapr->htab, index)); 2218 index++; 2219 examined++; 2220 } 2221 2222 invalidstart = index; 2223 /* Consume invalid dirty HPTEs */ 2224 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2225 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2226 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2227 CLEAN_HPTE(HPTE(spapr->htab, index)); 2228 index++; 2229 examined++; 2230 } 2231 2232 if (index > chunkstart) { 2233 int n_valid = invalidstart - chunkstart; 2234 int n_invalid = index - invalidstart; 2235 2236 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2237 sent += index - chunkstart; 2238 2239 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2240 break; 2241 } 2242 } 2243 2244 if (examined >= htabslots) { 2245 break; 2246 } 2247 2248 if (index >= htabslots) { 2249 assert(index == htabslots); 2250 index = 0; 2251 } 2252 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2253 2254 if (index >= htabslots) { 2255 assert(index == htabslots); 2256 index = 0; 2257 } 2258 2259 spapr->htab_save_index = index; 2260 2261 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2262 } 2263 2264 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2265 #define MAX_KVM_BUF_SIZE 2048 2266 2267 static int htab_save_iterate(QEMUFile *f, void *opaque) 2268 { 2269 SpaprMachineState *spapr = opaque; 2270 int fd; 2271 int rc = 0; 2272 2273 /* Iteration header */ 2274 if (!spapr->htab_shift) { 2275 qemu_put_be32(f, -1); 2276 return 1; 2277 } else { 2278 qemu_put_be32(f, 0); 2279 } 2280 2281 if (!spapr->htab) { 2282 assert(kvm_enabled()); 2283 2284 fd = get_htab_fd(spapr); 2285 if (fd < 0) { 2286 return fd; 2287 } 2288 2289 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2290 if (rc < 0) { 2291 return rc; 2292 } 2293 } else if (spapr->htab_first_pass) { 2294 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2295 } else { 2296 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2297 } 2298 2299 htab_save_end_marker(f); 2300 2301 return rc; 2302 } 2303 2304 static int htab_save_complete(QEMUFile *f, void *opaque) 2305 { 2306 SpaprMachineState *spapr = opaque; 2307 int fd; 2308 2309 /* Iteration header */ 2310 if (!spapr->htab_shift) { 2311 qemu_put_be32(f, -1); 2312 return 0; 2313 } else { 2314 qemu_put_be32(f, 0); 2315 } 2316 2317 if (!spapr->htab) { 2318 int rc; 2319 2320 assert(kvm_enabled()); 2321 2322 fd = get_htab_fd(spapr); 2323 if (fd < 0) { 2324 return fd; 2325 } 2326 2327 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2328 if (rc < 0) { 2329 return rc; 2330 } 2331 } else { 2332 if (spapr->htab_first_pass) { 2333 htab_save_first_pass(f, spapr, -1); 2334 } 2335 htab_save_later_pass(f, spapr, -1); 2336 } 2337 2338 /* End marker */ 2339 htab_save_end_marker(f); 2340 2341 return 0; 2342 } 2343 2344 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2345 { 2346 SpaprMachineState *spapr = opaque; 2347 uint32_t section_hdr; 2348 int fd = -1; 2349 Error *local_err = NULL; 2350 2351 if (version_id < 1 || version_id > 1) { 2352 error_report("htab_load() bad version"); 2353 return -EINVAL; 2354 } 2355 2356 section_hdr = qemu_get_be32(f); 2357 2358 if (section_hdr == -1) { 2359 spapr_free_hpt(spapr); 2360 return 0; 2361 } 2362 2363 if (section_hdr) { 2364 /* First section gives the htab size */ 2365 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2366 if (local_err) { 2367 error_report_err(local_err); 2368 return -EINVAL; 2369 } 2370 return 0; 2371 } 2372 2373 if (!spapr->htab) { 2374 assert(kvm_enabled()); 2375 2376 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2377 if (fd < 0) { 2378 error_report_err(local_err); 2379 return fd; 2380 } 2381 } 2382 2383 while (true) { 2384 uint32_t index; 2385 uint16_t n_valid, n_invalid; 2386 2387 index = qemu_get_be32(f); 2388 n_valid = qemu_get_be16(f); 2389 n_invalid = qemu_get_be16(f); 2390 2391 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2392 /* End of Stream */ 2393 break; 2394 } 2395 2396 if ((index + n_valid + n_invalid) > 2397 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2398 /* Bad index in stream */ 2399 error_report( 2400 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2401 index, n_valid, n_invalid, spapr->htab_shift); 2402 return -EINVAL; 2403 } 2404 2405 if (spapr->htab) { 2406 if (n_valid) { 2407 qemu_get_buffer(f, HPTE(spapr->htab, index), 2408 HASH_PTE_SIZE_64 * n_valid); 2409 } 2410 if (n_invalid) { 2411 memset(HPTE(spapr->htab, index + n_valid), 0, 2412 HASH_PTE_SIZE_64 * n_invalid); 2413 } 2414 } else { 2415 int rc; 2416 2417 assert(fd >= 0); 2418 2419 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2420 if (rc < 0) { 2421 return rc; 2422 } 2423 } 2424 } 2425 2426 if (!spapr->htab) { 2427 assert(fd >= 0); 2428 close(fd); 2429 } 2430 2431 return 0; 2432 } 2433 2434 static void htab_save_cleanup(void *opaque) 2435 { 2436 SpaprMachineState *spapr = opaque; 2437 2438 close_htab_fd(spapr); 2439 } 2440 2441 static SaveVMHandlers savevm_htab_handlers = { 2442 .save_setup = htab_save_setup, 2443 .save_live_iterate = htab_save_iterate, 2444 .save_live_complete_precopy = htab_save_complete, 2445 .save_cleanup = htab_save_cleanup, 2446 .load_state = htab_load, 2447 }; 2448 2449 static void spapr_boot_set(void *opaque, const char *boot_device, 2450 Error **errp) 2451 { 2452 MachineState *machine = MACHINE(opaque); 2453 machine->boot_order = g_strdup(boot_device); 2454 } 2455 2456 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2457 { 2458 MachineState *machine = MACHINE(spapr); 2459 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2460 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2461 int i; 2462 2463 for (i = 0; i < nr_lmbs; i++) { 2464 uint64_t addr; 2465 2466 addr = i * lmb_size + machine->device_memory->base; 2467 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2468 addr / lmb_size); 2469 } 2470 } 2471 2472 /* 2473 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2474 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2475 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2476 */ 2477 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2478 { 2479 int i; 2480 2481 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2482 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2483 " is not aligned to %" PRIu64 " MiB", 2484 machine->ram_size, 2485 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2486 return; 2487 } 2488 2489 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2490 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2491 " is not aligned to %" PRIu64 " MiB", 2492 machine->ram_size, 2493 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2494 return; 2495 } 2496 2497 for (i = 0; i < nb_numa_nodes; i++) { 2498 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2499 error_setg(errp, 2500 "Node %d memory size 0x%" PRIx64 2501 " is not aligned to %" PRIu64 " MiB", 2502 i, numa_info[i].node_mem, 2503 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2504 return; 2505 } 2506 } 2507 } 2508 2509 /* find cpu slot in machine->possible_cpus by core_id */ 2510 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2511 { 2512 int index = id / smp_threads; 2513 2514 if (index >= ms->possible_cpus->len) { 2515 return NULL; 2516 } 2517 if (idx) { 2518 *idx = index; 2519 } 2520 return &ms->possible_cpus->cpus[index]; 2521 } 2522 2523 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2524 { 2525 Error *local_err = NULL; 2526 bool vsmt_user = !!spapr->vsmt; 2527 int kvm_smt = kvmppc_smt_threads(); 2528 int ret; 2529 2530 if (!kvm_enabled() && (smp_threads > 1)) { 2531 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2532 "on a pseries machine"); 2533 goto out; 2534 } 2535 if (!is_power_of_2(smp_threads)) { 2536 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2537 "machine because it must be a power of 2", smp_threads); 2538 goto out; 2539 } 2540 2541 /* Detemine the VSMT mode to use: */ 2542 if (vsmt_user) { 2543 if (spapr->vsmt < smp_threads) { 2544 error_setg(&local_err, "Cannot support VSMT mode %d" 2545 " because it must be >= threads/core (%d)", 2546 spapr->vsmt, smp_threads); 2547 goto out; 2548 } 2549 /* In this case, spapr->vsmt has been set by the command line */ 2550 } else { 2551 /* 2552 * Default VSMT value is tricky, because we need it to be as 2553 * consistent as possible (for migration), but this requires 2554 * changing it for at least some existing cases. We pick 8 as 2555 * the value that we'd get with KVM on POWER8, the 2556 * overwhelmingly common case in production systems. 2557 */ 2558 spapr->vsmt = MAX(8, smp_threads); 2559 } 2560 2561 /* KVM: If necessary, set the SMT mode: */ 2562 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2563 ret = kvmppc_set_smt_threads(spapr->vsmt); 2564 if (ret) { 2565 /* Looks like KVM isn't able to change VSMT mode */ 2566 error_setg(&local_err, 2567 "Failed to set KVM's VSMT mode to %d (errno %d)", 2568 spapr->vsmt, ret); 2569 /* We can live with that if the default one is big enough 2570 * for the number of threads, and a submultiple of the one 2571 * we want. In this case we'll waste some vcpu ids, but 2572 * behaviour will be correct */ 2573 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2574 warn_report_err(local_err); 2575 local_err = NULL; 2576 goto out; 2577 } else { 2578 if (!vsmt_user) { 2579 error_append_hint(&local_err, 2580 "On PPC, a VM with %d threads/core" 2581 " on a host with %d threads/core" 2582 " requires the use of VSMT mode %d.\n", 2583 smp_threads, kvm_smt, spapr->vsmt); 2584 } 2585 kvmppc_hint_smt_possible(&local_err); 2586 goto out; 2587 } 2588 } 2589 } 2590 /* else TCG: nothing to do currently */ 2591 out: 2592 error_propagate(errp, local_err); 2593 } 2594 2595 static void spapr_init_cpus(SpaprMachineState *spapr) 2596 { 2597 MachineState *machine = MACHINE(spapr); 2598 MachineClass *mc = MACHINE_GET_CLASS(machine); 2599 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2600 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2601 const CPUArchIdList *possible_cpus; 2602 int boot_cores_nr = smp_cpus / smp_threads; 2603 int i; 2604 2605 possible_cpus = mc->possible_cpu_arch_ids(machine); 2606 if (mc->has_hotpluggable_cpus) { 2607 if (smp_cpus % smp_threads) { 2608 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2609 smp_cpus, smp_threads); 2610 exit(1); 2611 } 2612 if (max_cpus % smp_threads) { 2613 error_report("max_cpus (%u) must be multiple of threads (%u)", 2614 max_cpus, smp_threads); 2615 exit(1); 2616 } 2617 } else { 2618 if (max_cpus != smp_cpus) { 2619 error_report("This machine version does not support CPU hotplug"); 2620 exit(1); 2621 } 2622 boot_cores_nr = possible_cpus->len; 2623 } 2624 2625 if (smc->pre_2_10_has_unused_icps) { 2626 int i; 2627 2628 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2629 /* Dummy entries get deregistered when real ICPState objects 2630 * are registered during CPU core hotplug. 2631 */ 2632 pre_2_10_vmstate_register_dummy_icp(i); 2633 } 2634 } 2635 2636 for (i = 0; i < possible_cpus->len; i++) { 2637 int core_id = i * smp_threads; 2638 2639 if (mc->has_hotpluggable_cpus) { 2640 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2641 spapr_vcpu_id(spapr, core_id)); 2642 } 2643 2644 if (i < boot_cores_nr) { 2645 Object *core = object_new(type); 2646 int nr_threads = smp_threads; 2647 2648 /* Handle the partially filled core for older machine types */ 2649 if ((i + 1) * smp_threads >= smp_cpus) { 2650 nr_threads = smp_cpus - i * smp_threads; 2651 } 2652 2653 object_property_set_int(core, nr_threads, "nr-threads", 2654 &error_fatal); 2655 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2656 &error_fatal); 2657 object_property_set_bool(core, true, "realized", &error_fatal); 2658 2659 object_unref(core); 2660 } 2661 } 2662 } 2663 2664 static PCIHostState *spapr_create_default_phb(void) 2665 { 2666 DeviceState *dev; 2667 2668 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); 2669 qdev_prop_set_uint32(dev, "index", 0); 2670 qdev_init_nofail(dev); 2671 2672 return PCI_HOST_BRIDGE(dev); 2673 } 2674 2675 /* pSeries LPAR / sPAPR hardware init */ 2676 static void spapr_machine_init(MachineState *machine) 2677 { 2678 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2679 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2680 const char *kernel_filename = machine->kernel_filename; 2681 const char *initrd_filename = machine->initrd_filename; 2682 PCIHostState *phb; 2683 int i; 2684 MemoryRegion *sysmem = get_system_memory(); 2685 MemoryRegion *ram = g_new(MemoryRegion, 1); 2686 hwaddr node0_size = spapr_node0_size(machine); 2687 long load_limit, fw_size; 2688 char *filename; 2689 Error *resize_hpt_err = NULL; 2690 2691 msi_nonbroken = true; 2692 2693 QLIST_INIT(&spapr->phbs); 2694 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2695 2696 /* Determine capabilities to run with */ 2697 spapr_caps_init(spapr); 2698 2699 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2700 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2701 /* 2702 * If the user explicitly requested a mode we should either 2703 * supply it, or fail completely (which we do below). But if 2704 * it's not set explicitly, we reset our mode to something 2705 * that works 2706 */ 2707 if (resize_hpt_err) { 2708 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2709 error_free(resize_hpt_err); 2710 resize_hpt_err = NULL; 2711 } else { 2712 spapr->resize_hpt = smc->resize_hpt_default; 2713 } 2714 } 2715 2716 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2717 2718 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2719 /* 2720 * User requested HPT resize, but this host can't supply it. Bail out 2721 */ 2722 error_report_err(resize_hpt_err); 2723 exit(1); 2724 } 2725 2726 spapr->rma_size = node0_size; 2727 2728 /* With KVM, we don't actually know whether KVM supports an 2729 * unbounded RMA (PR KVM) or is limited by the hash table size 2730 * (HV KVM using VRMA), so we always assume the latter 2731 * 2732 * In that case, we also limit the initial allocations for RTAS 2733 * etc... to 256M since we have no way to know what the VRMA size 2734 * is going to be as it depends on the size of the hash table 2735 * which isn't determined yet. 2736 */ 2737 if (kvm_enabled()) { 2738 spapr->vrma_adjust = 1; 2739 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2740 } 2741 2742 /* Actually we don't support unbounded RMA anymore since we added 2743 * proper emulation of HV mode. The max we can get is 16G which 2744 * also happens to be what we configure for PAPR mode so make sure 2745 * we don't do anything bigger than that 2746 */ 2747 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2748 2749 if (spapr->rma_size > node0_size) { 2750 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2751 spapr->rma_size); 2752 exit(1); 2753 } 2754 2755 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2756 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2757 2758 /* 2759 * VSMT must be set in order to be able to compute VCPU ids, ie to 2760 * call spapr_max_server_number() or spapr_vcpu_id(). 2761 */ 2762 spapr_set_vsmt_mode(spapr, &error_fatal); 2763 2764 /* Set up Interrupt Controller before we create the VCPUs */ 2765 spapr_irq_init(spapr, &error_fatal); 2766 2767 /* Set up containers for ibm,client-architecture-support negotiated options 2768 */ 2769 spapr->ov5 = spapr_ovec_new(); 2770 spapr->ov5_cas = spapr_ovec_new(); 2771 2772 if (smc->dr_lmb_enabled) { 2773 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2774 spapr_validate_node_memory(machine, &error_fatal); 2775 } 2776 2777 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2778 2779 /* advertise support for dedicated HP event source to guests */ 2780 if (spapr->use_hotplug_event_source) { 2781 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2782 } 2783 2784 /* advertise support for HPT resizing */ 2785 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2786 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2787 } 2788 2789 /* advertise support for ibm,dyamic-memory-v2 */ 2790 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2791 2792 /* advertise XIVE on POWER9 machines */ 2793 if (spapr->irq->ov5 & (SPAPR_OV5_XIVE_EXPLOIT | SPAPR_OV5_XIVE_BOTH)) { 2794 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2795 } 2796 2797 /* init CPUs */ 2798 spapr_init_cpus(spapr); 2799 2800 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2801 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2802 spapr->max_compat_pvr)) { 2803 /* KVM and TCG always allow GTSE with radix... */ 2804 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2805 } 2806 /* ... but not with hash (currently). */ 2807 2808 if (kvm_enabled()) { 2809 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2810 kvmppc_enable_logical_ci_hcalls(); 2811 kvmppc_enable_set_mode_hcall(); 2812 2813 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2814 kvmppc_enable_clear_ref_mod_hcalls(); 2815 2816 /* Enable H_PAGE_INIT */ 2817 kvmppc_enable_h_page_init(); 2818 } 2819 2820 /* allocate RAM */ 2821 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2822 machine->ram_size); 2823 memory_region_add_subregion(sysmem, 0, ram); 2824 2825 /* always allocate the device memory information */ 2826 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2827 2828 /* initialize hotplug memory address space */ 2829 if (machine->ram_size < machine->maxram_size) { 2830 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2831 /* 2832 * Limit the number of hotpluggable memory slots to half the number 2833 * slots that KVM supports, leaving the other half for PCI and other 2834 * devices. However ensure that number of slots doesn't drop below 32. 2835 */ 2836 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2837 SPAPR_MAX_RAM_SLOTS; 2838 2839 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2840 max_memslots = SPAPR_MAX_RAM_SLOTS; 2841 } 2842 if (machine->ram_slots > max_memslots) { 2843 error_report("Specified number of memory slots %" 2844 PRIu64" exceeds max supported %d", 2845 machine->ram_slots, max_memslots); 2846 exit(1); 2847 } 2848 2849 machine->device_memory->base = ROUND_UP(machine->ram_size, 2850 SPAPR_DEVICE_MEM_ALIGN); 2851 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2852 "device-memory", device_mem_size); 2853 memory_region_add_subregion(sysmem, machine->device_memory->base, 2854 &machine->device_memory->mr); 2855 } 2856 2857 if (smc->dr_lmb_enabled) { 2858 spapr_create_lmb_dr_connectors(spapr); 2859 } 2860 2861 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2862 if (!filename) { 2863 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2864 exit(1); 2865 } 2866 spapr->rtas_size = get_image_size(filename); 2867 if (spapr->rtas_size < 0) { 2868 error_report("Could not get size of LPAR rtas '%s'", filename); 2869 exit(1); 2870 } 2871 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2872 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2873 error_report("Could not load LPAR rtas '%s'", filename); 2874 exit(1); 2875 } 2876 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2877 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2878 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2879 exit(1); 2880 } 2881 g_free(filename); 2882 2883 /* Set up RTAS event infrastructure */ 2884 spapr_events_init(spapr); 2885 2886 /* Set up the RTC RTAS interfaces */ 2887 spapr_rtc_create(spapr); 2888 2889 /* Set up VIO bus */ 2890 spapr->vio_bus = spapr_vio_bus_init(); 2891 2892 for (i = 0; i < serial_max_hds(); i++) { 2893 if (serial_hd(i)) { 2894 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2895 } 2896 } 2897 2898 /* We always have at least the nvram device on VIO */ 2899 spapr_create_nvram(spapr); 2900 2901 /* 2902 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2903 * connectors (described in root DT node's "ibm,drc-types" property) 2904 * are pre-initialized here. additional child connectors (such as 2905 * connectors for a PHBs PCI slots) are added as needed during their 2906 * parent's realization. 2907 */ 2908 if (smc->dr_phb_enabled) { 2909 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2910 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2911 } 2912 } 2913 2914 /* Set up PCI */ 2915 spapr_pci_rtas_init(); 2916 2917 phb = spapr_create_default_phb(); 2918 2919 for (i = 0; i < nb_nics; i++) { 2920 NICInfo *nd = &nd_table[i]; 2921 2922 if (!nd->model) { 2923 nd->model = g_strdup("spapr-vlan"); 2924 } 2925 2926 if (g_str_equal(nd->model, "spapr-vlan") || 2927 g_str_equal(nd->model, "ibmveth")) { 2928 spapr_vlan_create(spapr->vio_bus, nd); 2929 } else { 2930 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2931 } 2932 } 2933 2934 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2935 spapr_vscsi_create(spapr->vio_bus); 2936 } 2937 2938 /* Graphics */ 2939 if (spapr_vga_init(phb->bus, &error_fatal)) { 2940 spapr->has_graphics = true; 2941 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2942 } 2943 2944 if (machine->usb) { 2945 if (smc->use_ohci_by_default) { 2946 pci_create_simple(phb->bus, -1, "pci-ohci"); 2947 } else { 2948 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2949 } 2950 2951 if (spapr->has_graphics) { 2952 USBBus *usb_bus = usb_bus_find(-1); 2953 2954 usb_create_simple(usb_bus, "usb-kbd"); 2955 usb_create_simple(usb_bus, "usb-mouse"); 2956 } 2957 } 2958 2959 if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) { 2960 error_report( 2961 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2962 MIN_RMA_SLOF); 2963 exit(1); 2964 } 2965 2966 if (kernel_filename) { 2967 uint64_t lowaddr = 0; 2968 2969 spapr->kernel_size = load_elf(kernel_filename, NULL, 2970 translate_kernel_address, NULL, 2971 NULL, &lowaddr, NULL, 1, 2972 PPC_ELF_MACHINE, 0, 0); 2973 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2974 spapr->kernel_size = load_elf(kernel_filename, NULL, 2975 translate_kernel_address, NULL, NULL, 2976 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2977 0, 0); 2978 spapr->kernel_le = spapr->kernel_size > 0; 2979 } 2980 if (spapr->kernel_size < 0) { 2981 error_report("error loading %s: %s", kernel_filename, 2982 load_elf_strerror(spapr->kernel_size)); 2983 exit(1); 2984 } 2985 2986 /* load initrd */ 2987 if (initrd_filename) { 2988 /* Try to locate the initrd in the gap between the kernel 2989 * and the firmware. Add a bit of space just in case 2990 */ 2991 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2992 + 0x1ffff) & ~0xffff; 2993 spapr->initrd_size = load_image_targphys(initrd_filename, 2994 spapr->initrd_base, 2995 load_limit 2996 - spapr->initrd_base); 2997 if (spapr->initrd_size < 0) { 2998 error_report("could not load initial ram disk '%s'", 2999 initrd_filename); 3000 exit(1); 3001 } 3002 } 3003 } 3004 3005 if (bios_name == NULL) { 3006 bios_name = FW_FILE_NAME; 3007 } 3008 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 3009 if (!filename) { 3010 error_report("Could not find LPAR firmware '%s'", bios_name); 3011 exit(1); 3012 } 3013 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 3014 if (fw_size <= 0) { 3015 error_report("Could not load LPAR firmware '%s'", filename); 3016 exit(1); 3017 } 3018 g_free(filename); 3019 3020 /* FIXME: Should register things through the MachineState's qdev 3021 * interface, this is a legacy from the sPAPREnvironment structure 3022 * which predated MachineState but had a similar function */ 3023 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3024 register_savevm_live(NULL, "spapr/htab", -1, 1, 3025 &savevm_htab_handlers, spapr); 3026 3027 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine), 3028 &error_fatal); 3029 3030 qemu_register_boot_set(spapr_boot_set, spapr); 3031 3032 if (kvm_enabled()) { 3033 /* to stop and start vmclock */ 3034 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3035 &spapr->tb); 3036 3037 kvmppc_spapr_enable_inkernel_multitce(); 3038 } 3039 } 3040 3041 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3042 { 3043 if (!vm_type) { 3044 return 0; 3045 } 3046 3047 if (!strcmp(vm_type, "HV")) { 3048 return 1; 3049 } 3050 3051 if (!strcmp(vm_type, "PR")) { 3052 return 2; 3053 } 3054 3055 error_report("Unknown kvm-type specified '%s'", vm_type); 3056 exit(1); 3057 } 3058 3059 /* 3060 * Implementation of an interface to adjust firmware path 3061 * for the bootindex property handling. 3062 */ 3063 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3064 DeviceState *dev) 3065 { 3066 #define CAST(type, obj, name) \ 3067 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3068 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3069 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3070 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3071 3072 if (d) { 3073 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3074 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3075 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3076 3077 if (spapr) { 3078 /* 3079 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3080 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3081 * 0x8000 | (target << 8) | (bus << 5) | lun 3082 * (see the "Logical unit addressing format" table in SAM5) 3083 */ 3084 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3085 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3086 (uint64_t)id << 48); 3087 } else if (virtio) { 3088 /* 3089 * We use SRP luns of the form 01000000 | (target << 8) | lun 3090 * in the top 32 bits of the 64-bit LUN 3091 * Note: the quote above is from SLOF and it is wrong, 3092 * the actual binding is: 3093 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3094 */ 3095 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3096 if (d->lun >= 256) { 3097 /* Use the LUN "flat space addressing method" */ 3098 id |= 0x4000; 3099 } 3100 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3101 (uint64_t)id << 32); 3102 } else if (usb) { 3103 /* 3104 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3105 * in the top 32 bits of the 64-bit LUN 3106 */ 3107 unsigned usb_port = atoi(usb->port->path); 3108 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3109 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3110 (uint64_t)id << 32); 3111 } 3112 } 3113 3114 /* 3115 * SLOF probes the USB devices, and if it recognizes that the device is a 3116 * storage device, it changes its name to "storage" instead of "usb-host", 3117 * and additionally adds a child node for the SCSI LUN, so the correct 3118 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3119 */ 3120 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3121 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3122 if (usb_host_dev_is_scsi_storage(usbdev)) { 3123 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3124 } 3125 } 3126 3127 if (phb) { 3128 /* Replace "pci" with "pci@800000020000000" */ 3129 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3130 } 3131 3132 if (vsc) { 3133 /* Same logic as virtio above */ 3134 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3135 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3136 } 3137 3138 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3139 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3140 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3141 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3142 } 3143 3144 return NULL; 3145 } 3146 3147 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3148 { 3149 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3150 3151 return g_strdup(spapr->kvm_type); 3152 } 3153 3154 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3155 { 3156 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3157 3158 g_free(spapr->kvm_type); 3159 spapr->kvm_type = g_strdup(value); 3160 } 3161 3162 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3163 { 3164 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3165 3166 return spapr->use_hotplug_event_source; 3167 } 3168 3169 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3170 Error **errp) 3171 { 3172 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3173 3174 spapr->use_hotplug_event_source = value; 3175 } 3176 3177 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3178 { 3179 return true; 3180 } 3181 3182 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3183 { 3184 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3185 3186 switch (spapr->resize_hpt) { 3187 case SPAPR_RESIZE_HPT_DEFAULT: 3188 return g_strdup("default"); 3189 case SPAPR_RESIZE_HPT_DISABLED: 3190 return g_strdup("disabled"); 3191 case SPAPR_RESIZE_HPT_ENABLED: 3192 return g_strdup("enabled"); 3193 case SPAPR_RESIZE_HPT_REQUIRED: 3194 return g_strdup("required"); 3195 } 3196 g_assert_not_reached(); 3197 } 3198 3199 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3200 { 3201 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3202 3203 if (strcmp(value, "default") == 0) { 3204 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3205 } else if (strcmp(value, "disabled") == 0) { 3206 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3207 } else if (strcmp(value, "enabled") == 0) { 3208 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3209 } else if (strcmp(value, "required") == 0) { 3210 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3211 } else { 3212 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3213 } 3214 } 3215 3216 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 3217 void *opaque, Error **errp) 3218 { 3219 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3220 } 3221 3222 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 3223 void *opaque, Error **errp) 3224 { 3225 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3226 } 3227 3228 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3229 { 3230 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3231 3232 if (spapr->irq == &spapr_irq_xics_legacy) { 3233 return g_strdup("legacy"); 3234 } else if (spapr->irq == &spapr_irq_xics) { 3235 return g_strdup("xics"); 3236 } else if (spapr->irq == &spapr_irq_xive) { 3237 return g_strdup("xive"); 3238 } else if (spapr->irq == &spapr_irq_dual) { 3239 return g_strdup("dual"); 3240 } 3241 g_assert_not_reached(); 3242 } 3243 3244 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3245 { 3246 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3247 3248 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3249 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3250 return; 3251 } 3252 3253 /* The legacy IRQ backend can not be set */ 3254 if (strcmp(value, "xics") == 0) { 3255 spapr->irq = &spapr_irq_xics; 3256 } else if (strcmp(value, "xive") == 0) { 3257 spapr->irq = &spapr_irq_xive; 3258 } else if (strcmp(value, "dual") == 0) { 3259 spapr->irq = &spapr_irq_dual; 3260 } else { 3261 error_setg(errp, "Bad value for \"ic-mode\" property"); 3262 } 3263 } 3264 3265 static char *spapr_get_host_model(Object *obj, Error **errp) 3266 { 3267 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3268 3269 return g_strdup(spapr->host_model); 3270 } 3271 3272 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3273 { 3274 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3275 3276 g_free(spapr->host_model); 3277 spapr->host_model = g_strdup(value); 3278 } 3279 3280 static char *spapr_get_host_serial(Object *obj, Error **errp) 3281 { 3282 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3283 3284 return g_strdup(spapr->host_serial); 3285 } 3286 3287 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3288 { 3289 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3290 3291 g_free(spapr->host_serial); 3292 spapr->host_serial = g_strdup(value); 3293 } 3294 3295 static void spapr_instance_init(Object *obj) 3296 { 3297 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3298 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3299 3300 spapr->htab_fd = -1; 3301 spapr->use_hotplug_event_source = true; 3302 object_property_add_str(obj, "kvm-type", 3303 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 3304 object_property_set_description(obj, "kvm-type", 3305 "Specifies the KVM virtualization mode (HV, PR)", 3306 NULL); 3307 object_property_add_bool(obj, "modern-hotplug-events", 3308 spapr_get_modern_hotplug_events, 3309 spapr_set_modern_hotplug_events, 3310 NULL); 3311 object_property_set_description(obj, "modern-hotplug-events", 3312 "Use dedicated hotplug event mechanism in" 3313 " place of standard EPOW events when possible" 3314 " (required for memory hot-unplug support)", 3315 NULL); 3316 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3317 "Maximum permitted CPU compatibility mode", 3318 &error_fatal); 3319 3320 object_property_add_str(obj, "resize-hpt", 3321 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 3322 object_property_set_description(obj, "resize-hpt", 3323 "Resizing of the Hash Page Table (enabled, disabled, required)", 3324 NULL); 3325 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 3326 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 3327 object_property_set_description(obj, "vsmt", 3328 "Virtual SMT: KVM behaves as if this were" 3329 " the host's SMT mode", &error_abort); 3330 object_property_add_bool(obj, "vfio-no-msix-emulation", 3331 spapr_get_msix_emulation, NULL, NULL); 3332 3333 /* The machine class defines the default interrupt controller mode */ 3334 spapr->irq = smc->irq; 3335 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3336 spapr_set_ic_mode, NULL); 3337 object_property_set_description(obj, "ic-mode", 3338 "Specifies the interrupt controller mode (xics, xive, dual)", 3339 NULL); 3340 3341 object_property_add_str(obj, "host-model", 3342 spapr_get_host_model, spapr_set_host_model, 3343 &error_abort); 3344 object_property_set_description(obj, "host-model", 3345 "Host model to advertise in guest device tree", &error_abort); 3346 object_property_add_str(obj, "host-serial", 3347 spapr_get_host_serial, spapr_set_host_serial, 3348 &error_abort); 3349 object_property_set_description(obj, "host-serial", 3350 "Host serial number to advertise in guest device tree", &error_abort); 3351 } 3352 3353 static void spapr_machine_finalizefn(Object *obj) 3354 { 3355 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3356 3357 g_free(spapr->kvm_type); 3358 } 3359 3360 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3361 { 3362 cpu_synchronize_state(cs); 3363 ppc_cpu_do_system_reset(cs); 3364 } 3365 3366 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3367 { 3368 CPUState *cs; 3369 3370 CPU_FOREACH(cs) { 3371 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3372 } 3373 } 3374 3375 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3376 void *fdt, int *fdt_start_offset, Error **errp) 3377 { 3378 uint64_t addr; 3379 uint32_t node; 3380 3381 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3382 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3383 &error_abort); 3384 *fdt_start_offset = spapr_populate_memory_node(fdt, node, addr, 3385 SPAPR_MEMORY_BLOCK_SIZE); 3386 return 0; 3387 } 3388 3389 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3390 bool dedicated_hp_event_source, Error **errp) 3391 { 3392 SpaprDrc *drc; 3393 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3394 int i; 3395 uint64_t addr = addr_start; 3396 bool hotplugged = spapr_drc_hotplugged(dev); 3397 Error *local_err = NULL; 3398 3399 for (i = 0; i < nr_lmbs; i++) { 3400 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3401 addr / SPAPR_MEMORY_BLOCK_SIZE); 3402 g_assert(drc); 3403 3404 spapr_drc_attach(drc, dev, &local_err); 3405 if (local_err) { 3406 while (addr > addr_start) { 3407 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3408 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3409 addr / SPAPR_MEMORY_BLOCK_SIZE); 3410 spapr_drc_detach(drc); 3411 } 3412 error_propagate(errp, local_err); 3413 return; 3414 } 3415 if (!hotplugged) { 3416 spapr_drc_reset(drc); 3417 } 3418 addr += SPAPR_MEMORY_BLOCK_SIZE; 3419 } 3420 /* send hotplug notification to the 3421 * guest only in case of hotplugged memory 3422 */ 3423 if (hotplugged) { 3424 if (dedicated_hp_event_source) { 3425 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3426 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3427 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3428 nr_lmbs, 3429 spapr_drc_index(drc)); 3430 } else { 3431 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3432 nr_lmbs); 3433 } 3434 } 3435 } 3436 3437 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3438 Error **errp) 3439 { 3440 Error *local_err = NULL; 3441 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3442 PCDIMMDevice *dimm = PC_DIMM(dev); 3443 uint64_t size, addr; 3444 3445 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3446 3447 pc_dimm_plug(dimm, MACHINE(ms), &local_err); 3448 if (local_err) { 3449 goto out; 3450 } 3451 3452 addr = object_property_get_uint(OBJECT(dimm), 3453 PC_DIMM_ADDR_PROP, &local_err); 3454 if (local_err) { 3455 goto out_unplug; 3456 } 3457 3458 spapr_add_lmbs(dev, addr, size, spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3459 &local_err); 3460 if (local_err) { 3461 goto out_unplug; 3462 } 3463 3464 return; 3465 3466 out_unplug: 3467 pc_dimm_unplug(dimm, MACHINE(ms)); 3468 out: 3469 error_propagate(errp, local_err); 3470 } 3471 3472 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3473 Error **errp) 3474 { 3475 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3476 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3477 PCDIMMDevice *dimm = PC_DIMM(dev); 3478 Error *local_err = NULL; 3479 uint64_t size; 3480 Object *memdev; 3481 hwaddr pagesize; 3482 3483 if (!smc->dr_lmb_enabled) { 3484 error_setg(errp, "Memory hotplug not supported for this machine"); 3485 return; 3486 } 3487 3488 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3489 if (local_err) { 3490 error_propagate(errp, local_err); 3491 return; 3492 } 3493 3494 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3495 error_setg(errp, "Hotplugged memory size must be a multiple of " 3496 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3497 return; 3498 } 3499 3500 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3501 &error_abort); 3502 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3503 spapr_check_pagesize(spapr, pagesize, &local_err); 3504 if (local_err) { 3505 error_propagate(errp, local_err); 3506 return; 3507 } 3508 3509 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3510 } 3511 3512 struct SpaprDimmState { 3513 PCDIMMDevice *dimm; 3514 uint32_t nr_lmbs; 3515 QTAILQ_ENTRY(SpaprDimmState) next; 3516 }; 3517 3518 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3519 PCDIMMDevice *dimm) 3520 { 3521 SpaprDimmState *dimm_state = NULL; 3522 3523 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3524 if (dimm_state->dimm == dimm) { 3525 break; 3526 } 3527 } 3528 return dimm_state; 3529 } 3530 3531 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3532 uint32_t nr_lmbs, 3533 PCDIMMDevice *dimm) 3534 { 3535 SpaprDimmState *ds = NULL; 3536 3537 /* 3538 * If this request is for a DIMM whose removal had failed earlier 3539 * (due to guest's refusal to remove the LMBs), we would have this 3540 * dimm already in the pending_dimm_unplugs list. In that 3541 * case don't add again. 3542 */ 3543 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3544 if (!ds) { 3545 ds = g_malloc0(sizeof(SpaprDimmState)); 3546 ds->nr_lmbs = nr_lmbs; 3547 ds->dimm = dimm; 3548 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3549 } 3550 return ds; 3551 } 3552 3553 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3554 SpaprDimmState *dimm_state) 3555 { 3556 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3557 g_free(dimm_state); 3558 } 3559 3560 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3561 PCDIMMDevice *dimm) 3562 { 3563 SpaprDrc *drc; 3564 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3565 &error_abort); 3566 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3567 uint32_t avail_lmbs = 0; 3568 uint64_t addr_start, addr; 3569 int i; 3570 3571 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3572 &error_abort); 3573 3574 addr = addr_start; 3575 for (i = 0; i < nr_lmbs; i++) { 3576 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3577 addr / SPAPR_MEMORY_BLOCK_SIZE); 3578 g_assert(drc); 3579 if (drc->dev) { 3580 avail_lmbs++; 3581 } 3582 addr += SPAPR_MEMORY_BLOCK_SIZE; 3583 } 3584 3585 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3586 } 3587 3588 /* Callback to be called during DRC release. */ 3589 void spapr_lmb_release(DeviceState *dev) 3590 { 3591 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3592 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3593 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3594 3595 /* This information will get lost if a migration occurs 3596 * during the unplug process. In this case recover it. */ 3597 if (ds == NULL) { 3598 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3599 g_assert(ds); 3600 /* The DRC being examined by the caller at least must be counted */ 3601 g_assert(ds->nr_lmbs); 3602 } 3603 3604 if (--ds->nr_lmbs) { 3605 return; 3606 } 3607 3608 /* 3609 * Now that all the LMBs have been removed by the guest, call the 3610 * unplug handler chain. This can never fail. 3611 */ 3612 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3613 object_unparent(OBJECT(dev)); 3614 } 3615 3616 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3617 { 3618 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3619 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3620 3621 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3622 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3623 spapr_pending_dimm_unplugs_remove(spapr, ds); 3624 } 3625 3626 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3627 DeviceState *dev, Error **errp) 3628 { 3629 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3630 Error *local_err = NULL; 3631 PCDIMMDevice *dimm = PC_DIMM(dev); 3632 uint32_t nr_lmbs; 3633 uint64_t size, addr_start, addr; 3634 int i; 3635 SpaprDrc *drc; 3636 3637 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3638 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3639 3640 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3641 &local_err); 3642 if (local_err) { 3643 goto out; 3644 } 3645 3646 /* 3647 * An existing pending dimm state for this DIMM means that there is an 3648 * unplug operation in progress, waiting for the spapr_lmb_release 3649 * callback to complete the job (BQL can't cover that far). In this case, 3650 * bail out to avoid detaching DRCs that were already released. 3651 */ 3652 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3653 error_setg(&local_err, 3654 "Memory unplug already in progress for device %s", 3655 dev->id); 3656 goto out; 3657 } 3658 3659 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3660 3661 addr = addr_start; 3662 for (i = 0; i < nr_lmbs; i++) { 3663 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3664 addr / SPAPR_MEMORY_BLOCK_SIZE); 3665 g_assert(drc); 3666 3667 spapr_drc_detach(drc); 3668 addr += SPAPR_MEMORY_BLOCK_SIZE; 3669 } 3670 3671 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3672 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3673 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3674 nr_lmbs, spapr_drc_index(drc)); 3675 out: 3676 error_propagate(errp, local_err); 3677 } 3678 3679 /* Callback to be called during DRC release. */ 3680 void spapr_core_release(DeviceState *dev) 3681 { 3682 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3683 3684 /* Call the unplug handler chain. This can never fail. */ 3685 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3686 object_unparent(OBJECT(dev)); 3687 } 3688 3689 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3690 { 3691 MachineState *ms = MACHINE(hotplug_dev); 3692 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3693 CPUCore *cc = CPU_CORE(dev); 3694 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3695 3696 if (smc->pre_2_10_has_unused_icps) { 3697 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3698 int i; 3699 3700 for (i = 0; i < cc->nr_threads; i++) { 3701 CPUState *cs = CPU(sc->threads[i]); 3702 3703 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3704 } 3705 } 3706 3707 assert(core_slot); 3708 core_slot->cpu = NULL; 3709 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3710 } 3711 3712 static 3713 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3714 Error **errp) 3715 { 3716 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3717 int index; 3718 SpaprDrc *drc; 3719 CPUCore *cc = CPU_CORE(dev); 3720 3721 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3722 error_setg(errp, "Unable to find CPU core with core-id: %d", 3723 cc->core_id); 3724 return; 3725 } 3726 if (index == 0) { 3727 error_setg(errp, "Boot CPU core may not be unplugged"); 3728 return; 3729 } 3730 3731 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3732 spapr_vcpu_id(spapr, cc->core_id)); 3733 g_assert(drc); 3734 3735 spapr_drc_detach(drc); 3736 3737 spapr_hotplug_req_remove_by_index(drc); 3738 } 3739 3740 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3741 void *fdt, int *fdt_start_offset, Error **errp) 3742 { 3743 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3744 CPUState *cs = CPU(core->threads[0]); 3745 PowerPCCPU *cpu = POWERPC_CPU(cs); 3746 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3747 int id = spapr_get_vcpu_id(cpu); 3748 char *nodename; 3749 int offset; 3750 3751 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3752 offset = fdt_add_subnode(fdt, 0, nodename); 3753 g_free(nodename); 3754 3755 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3756 3757 *fdt_start_offset = offset; 3758 return 0; 3759 } 3760 3761 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3762 Error **errp) 3763 { 3764 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3765 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3766 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3767 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3768 CPUCore *cc = CPU_CORE(dev); 3769 CPUState *cs; 3770 SpaprDrc *drc; 3771 Error *local_err = NULL; 3772 CPUArchId *core_slot; 3773 int index; 3774 bool hotplugged = spapr_drc_hotplugged(dev); 3775 3776 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3777 if (!core_slot) { 3778 error_setg(errp, "Unable to find CPU core with core-id: %d", 3779 cc->core_id); 3780 return; 3781 } 3782 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3783 spapr_vcpu_id(spapr, cc->core_id)); 3784 3785 g_assert(drc || !mc->has_hotpluggable_cpus); 3786 3787 if (drc) { 3788 spapr_drc_attach(drc, dev, &local_err); 3789 if (local_err) { 3790 error_propagate(errp, local_err); 3791 return; 3792 } 3793 3794 if (hotplugged) { 3795 /* 3796 * Send hotplug notification interrupt to the guest only 3797 * in case of hotplugged CPUs. 3798 */ 3799 spapr_hotplug_req_add_by_index(drc); 3800 } else { 3801 spapr_drc_reset(drc); 3802 } 3803 } 3804 3805 core_slot->cpu = OBJECT(dev); 3806 3807 if (smc->pre_2_10_has_unused_icps) { 3808 int i; 3809 3810 for (i = 0; i < cc->nr_threads; i++) { 3811 cs = CPU(core->threads[i]); 3812 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3813 } 3814 } 3815 } 3816 3817 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3818 Error **errp) 3819 { 3820 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3821 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3822 Error *local_err = NULL; 3823 CPUCore *cc = CPU_CORE(dev); 3824 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3825 const char *type = object_get_typename(OBJECT(dev)); 3826 CPUArchId *core_slot; 3827 int index; 3828 3829 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3830 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3831 goto out; 3832 } 3833 3834 if (strcmp(base_core_type, type)) { 3835 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3836 goto out; 3837 } 3838 3839 if (cc->core_id % smp_threads) { 3840 error_setg(&local_err, "invalid core id %d", cc->core_id); 3841 goto out; 3842 } 3843 3844 /* 3845 * In general we should have homogeneous threads-per-core, but old 3846 * (pre hotplug support) machine types allow the last core to have 3847 * reduced threads as a compatibility hack for when we allowed 3848 * total vcpus not a multiple of threads-per-core. 3849 */ 3850 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3851 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3852 cc->nr_threads, smp_threads); 3853 goto out; 3854 } 3855 3856 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3857 if (!core_slot) { 3858 error_setg(&local_err, "core id %d out of range", cc->core_id); 3859 goto out; 3860 } 3861 3862 if (core_slot->cpu) { 3863 error_setg(&local_err, "core %d already populated", cc->core_id); 3864 goto out; 3865 } 3866 3867 numa_cpu_pre_plug(core_slot, dev, &local_err); 3868 3869 out: 3870 error_propagate(errp, local_err); 3871 } 3872 3873 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3874 void *fdt, int *fdt_start_offset, Error **errp) 3875 { 3876 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3877 int intc_phandle; 3878 3879 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3880 if (intc_phandle <= 0) { 3881 return -1; 3882 } 3883 3884 if (spapr_populate_pci_dt(sphb, intc_phandle, fdt, spapr->irq->nr_msis, 3885 fdt_start_offset)) { 3886 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3887 return -1; 3888 } 3889 3890 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3891 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3892 3893 return 0; 3894 } 3895 3896 static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3897 Error **errp) 3898 { 3899 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3900 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3901 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3902 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3903 3904 if (dev->hotplugged && !smc->dr_phb_enabled) { 3905 error_setg(errp, "PHB hotplug not supported for this machine"); 3906 return; 3907 } 3908 3909 if (sphb->index == (uint32_t)-1) { 3910 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3911 return; 3912 } 3913 3914 /* 3915 * This will check that sphb->index doesn't exceed the maximum number of 3916 * PHBs for the current machine type. 3917 */ 3918 smc->phb_placement(spapr, sphb->index, 3919 &sphb->buid, &sphb->io_win_addr, 3920 &sphb->mem_win_addr, &sphb->mem64_win_addr, 3921 windows_supported, sphb->dma_liobn, 3922 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 3923 errp); 3924 } 3925 3926 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3927 Error **errp) 3928 { 3929 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3930 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3931 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3932 SpaprDrc *drc; 3933 bool hotplugged = spapr_drc_hotplugged(dev); 3934 Error *local_err = NULL; 3935 3936 if (!smc->dr_phb_enabled) { 3937 return; 3938 } 3939 3940 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3941 /* hotplug hooks should check it's enabled before getting this far */ 3942 assert(drc); 3943 3944 spapr_drc_attach(drc, DEVICE(dev), &local_err); 3945 if (local_err) { 3946 error_propagate(errp, local_err); 3947 return; 3948 } 3949 3950 if (hotplugged) { 3951 spapr_hotplug_req_add_by_index(drc); 3952 } else { 3953 spapr_drc_reset(drc); 3954 } 3955 } 3956 3957 void spapr_phb_release(DeviceState *dev) 3958 { 3959 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3960 3961 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3962 object_unparent(OBJECT(dev)); 3963 } 3964 3965 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3966 { 3967 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 3968 } 3969 3970 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 3971 DeviceState *dev, Error **errp) 3972 { 3973 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3974 SpaprDrc *drc; 3975 3976 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3977 assert(drc); 3978 3979 if (!spapr_drc_unplug_requested(drc)) { 3980 spapr_drc_detach(drc); 3981 spapr_hotplug_req_remove_by_index(drc); 3982 } 3983 } 3984 3985 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 3986 DeviceState *dev, Error **errp) 3987 { 3988 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3989 spapr_memory_plug(hotplug_dev, dev, errp); 3990 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3991 spapr_core_plug(hotplug_dev, dev, errp); 3992 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 3993 spapr_phb_plug(hotplug_dev, dev, errp); 3994 } 3995 } 3996 3997 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 3998 DeviceState *dev, Error **errp) 3999 { 4000 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4001 spapr_memory_unplug(hotplug_dev, dev); 4002 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4003 spapr_core_unplug(hotplug_dev, dev); 4004 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4005 spapr_phb_unplug(hotplug_dev, dev); 4006 } 4007 } 4008 4009 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4010 DeviceState *dev, Error **errp) 4011 { 4012 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4013 MachineClass *mc = MACHINE_GET_CLASS(sms); 4014 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4015 4016 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4017 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 4018 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4019 } else { 4020 /* NOTE: this means there is a window after guest reset, prior to 4021 * CAS negotiation, where unplug requests will fail due to the 4022 * capability not being detected yet. This is a bit different than 4023 * the case with PCI unplug, where the events will be queued and 4024 * eventually handled by the guest after boot 4025 */ 4026 error_setg(errp, "Memory hot unplug not supported for this guest"); 4027 } 4028 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4029 if (!mc->has_hotpluggable_cpus) { 4030 error_setg(errp, "CPU hot unplug not supported on this machine"); 4031 return; 4032 } 4033 spapr_core_unplug_request(hotplug_dev, dev, errp); 4034 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4035 if (!smc->dr_phb_enabled) { 4036 error_setg(errp, "PHB hot unplug not supported on this machine"); 4037 return; 4038 } 4039 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4040 } 4041 } 4042 4043 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4044 DeviceState *dev, Error **errp) 4045 { 4046 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4047 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4048 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4049 spapr_core_pre_plug(hotplug_dev, dev, errp); 4050 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4051 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4052 } 4053 } 4054 4055 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4056 DeviceState *dev) 4057 { 4058 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4059 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4060 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4061 return HOTPLUG_HANDLER(machine); 4062 } 4063 return NULL; 4064 } 4065 4066 static CpuInstanceProperties 4067 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4068 { 4069 CPUArchId *core_slot; 4070 MachineClass *mc = MACHINE_GET_CLASS(machine); 4071 4072 /* make sure possible_cpu are intialized */ 4073 mc->possible_cpu_arch_ids(machine); 4074 /* get CPU core slot containing thread that matches cpu_index */ 4075 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4076 assert(core_slot); 4077 return core_slot->props; 4078 } 4079 4080 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4081 { 4082 return idx / smp_cores % nb_numa_nodes; 4083 } 4084 4085 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4086 { 4087 int i; 4088 const char *core_type; 4089 int spapr_max_cores = max_cpus / smp_threads; 4090 MachineClass *mc = MACHINE_GET_CLASS(machine); 4091 4092 if (!mc->has_hotpluggable_cpus) { 4093 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4094 } 4095 if (machine->possible_cpus) { 4096 assert(machine->possible_cpus->len == spapr_max_cores); 4097 return machine->possible_cpus; 4098 } 4099 4100 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4101 if (!core_type) { 4102 error_report("Unable to find sPAPR CPU Core definition"); 4103 exit(1); 4104 } 4105 4106 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4107 sizeof(CPUArchId) * spapr_max_cores); 4108 machine->possible_cpus->len = spapr_max_cores; 4109 for (i = 0; i < machine->possible_cpus->len; i++) { 4110 int core_id = i * smp_threads; 4111 4112 machine->possible_cpus->cpus[i].type = core_type; 4113 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4114 machine->possible_cpus->cpus[i].arch_id = core_id; 4115 machine->possible_cpus->cpus[i].props.has_core_id = true; 4116 machine->possible_cpus->cpus[i].props.core_id = core_id; 4117 } 4118 return machine->possible_cpus; 4119 } 4120 4121 static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4122 uint64_t *buid, hwaddr *pio, 4123 hwaddr *mmio32, hwaddr *mmio64, 4124 unsigned n_dma, uint32_t *liobns, 4125 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4126 { 4127 /* 4128 * New-style PHB window placement. 4129 * 4130 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4131 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4132 * windows. 4133 * 4134 * Some guest kernels can't work with MMIO windows above 1<<46 4135 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4136 * 4137 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4138 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4139 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4140 * 1TiB 64-bit MMIO windows for each PHB. 4141 */ 4142 const uint64_t base_buid = 0x800000020000000ULL; 4143 int i; 4144 4145 /* Sanity check natural alignments */ 4146 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4147 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4148 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4149 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4150 /* Sanity check bounds */ 4151 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4152 SPAPR_PCI_MEM32_WIN_SIZE); 4153 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4154 SPAPR_PCI_MEM64_WIN_SIZE); 4155 4156 if (index >= SPAPR_MAX_PHBS) { 4157 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4158 SPAPR_MAX_PHBS - 1); 4159 return; 4160 } 4161 4162 *buid = base_buid + index; 4163 for (i = 0; i < n_dma; ++i) { 4164 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4165 } 4166 4167 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4168 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4169 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4170 4171 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4172 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4173 } 4174 4175 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4176 { 4177 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4178 4179 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4180 } 4181 4182 static void spapr_ics_resend(XICSFabric *dev) 4183 { 4184 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4185 4186 ics_resend(spapr->ics); 4187 } 4188 4189 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4190 { 4191 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4192 4193 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4194 } 4195 4196 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4197 Monitor *mon) 4198 { 4199 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4200 4201 spapr->irq->print_info(spapr, mon); 4202 } 4203 4204 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4205 { 4206 return cpu->vcpu_id; 4207 } 4208 4209 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4210 { 4211 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4212 int vcpu_id; 4213 4214 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4215 4216 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4217 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4218 error_append_hint(errp, "Adjust the number of cpus to %d " 4219 "or try to raise the number of threads per core\n", 4220 vcpu_id * smp_threads / spapr->vsmt); 4221 return; 4222 } 4223 4224 cpu->vcpu_id = vcpu_id; 4225 } 4226 4227 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4228 { 4229 CPUState *cs; 4230 4231 CPU_FOREACH(cs) { 4232 PowerPCCPU *cpu = POWERPC_CPU(cs); 4233 4234 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4235 return cpu; 4236 } 4237 } 4238 4239 return NULL; 4240 } 4241 4242 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4243 { 4244 MachineClass *mc = MACHINE_CLASS(oc); 4245 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4246 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4247 NMIClass *nc = NMI_CLASS(oc); 4248 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4249 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4250 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4251 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4252 4253 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4254 mc->ignore_boot_device_suffixes = true; 4255 4256 /* 4257 * We set up the default / latest behaviour here. The class_init 4258 * functions for the specific versioned machine types can override 4259 * these details for backwards compatibility 4260 */ 4261 mc->init = spapr_machine_init; 4262 mc->reset = spapr_machine_reset; 4263 mc->block_default_type = IF_SCSI; 4264 mc->max_cpus = 1024; 4265 mc->no_parallel = 1; 4266 mc->default_boot_order = ""; 4267 mc->default_ram_size = 512 * MiB; 4268 mc->default_display = "std"; 4269 mc->kvm_type = spapr_kvm_type; 4270 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4271 mc->pci_allow_0_address = true; 4272 assert(!mc->get_hotplug_handler); 4273 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4274 hc->pre_plug = spapr_machine_device_pre_plug; 4275 hc->plug = spapr_machine_device_plug; 4276 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4277 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4278 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4279 hc->unplug_request = spapr_machine_device_unplug_request; 4280 hc->unplug = spapr_machine_device_unplug; 4281 4282 smc->dr_lmb_enabled = true; 4283 smc->update_dt_enabled = true; 4284 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4285 mc->has_hotpluggable_cpus = true; 4286 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4287 fwc->get_dev_path = spapr_get_fw_dev_path; 4288 nc->nmi_monitor_handler = spapr_nmi; 4289 smc->phb_placement = spapr_phb_placement; 4290 vhc->hypercall = emulate_spapr_hypercall; 4291 vhc->hpt_mask = spapr_hpt_mask; 4292 vhc->map_hptes = spapr_map_hptes; 4293 vhc->unmap_hptes = spapr_unmap_hptes; 4294 vhc->store_hpte = spapr_store_hpte; 4295 vhc->get_pate = spapr_get_pate; 4296 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4297 xic->ics_get = spapr_ics_get; 4298 xic->ics_resend = spapr_ics_resend; 4299 xic->icp_get = spapr_icp_get; 4300 ispc->print_info = spapr_pic_print_info; 4301 /* Force NUMA node memory size to be a multiple of 4302 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4303 * in which LMBs are represented and hot-added 4304 */ 4305 mc->numa_mem_align_shift = 28; 4306 4307 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4308 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4309 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4310 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4311 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4312 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4313 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4314 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4315 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4316 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4317 spapr_caps_add_properties(smc, &error_abort); 4318 smc->irq = &spapr_irq_xics; 4319 smc->dr_phb_enabled = true; 4320 } 4321 4322 static const TypeInfo spapr_machine_info = { 4323 .name = TYPE_SPAPR_MACHINE, 4324 .parent = TYPE_MACHINE, 4325 .abstract = true, 4326 .instance_size = sizeof(SpaprMachineState), 4327 .instance_init = spapr_instance_init, 4328 .instance_finalize = spapr_machine_finalizefn, 4329 .class_size = sizeof(SpaprMachineClass), 4330 .class_init = spapr_machine_class_init, 4331 .interfaces = (InterfaceInfo[]) { 4332 { TYPE_FW_PATH_PROVIDER }, 4333 { TYPE_NMI }, 4334 { TYPE_HOTPLUG_HANDLER }, 4335 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4336 { TYPE_XICS_FABRIC }, 4337 { TYPE_INTERRUPT_STATS_PROVIDER }, 4338 { } 4339 }, 4340 }; 4341 4342 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4343 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4344 void *data) \ 4345 { \ 4346 MachineClass *mc = MACHINE_CLASS(oc); \ 4347 spapr_machine_##suffix##_class_options(mc); \ 4348 if (latest) { \ 4349 mc->alias = "pseries"; \ 4350 mc->is_default = 1; \ 4351 } \ 4352 } \ 4353 static const TypeInfo spapr_machine_##suffix##_info = { \ 4354 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4355 .parent = TYPE_SPAPR_MACHINE, \ 4356 .class_init = spapr_machine_##suffix##_class_init, \ 4357 }; \ 4358 static void spapr_machine_register_##suffix(void) \ 4359 { \ 4360 type_register(&spapr_machine_##suffix##_info); \ 4361 } \ 4362 type_init(spapr_machine_register_##suffix) 4363 4364 /* 4365 * pseries-4.0 4366 */ 4367 static void spapr_machine_4_0_class_options(MachineClass *mc) 4368 { 4369 /* Defaults for the latest behaviour inherited from the base class */ 4370 } 4371 4372 DEFINE_SPAPR_MACHINE(4_0, "4.0", true); 4373 4374 /* 4375 * pseries-3.1 4376 */ 4377 static void phb_placement_3_1(SpaprMachineState *spapr, uint32_t index, 4378 uint64_t *buid, hwaddr *pio, 4379 hwaddr *mmio32, hwaddr *mmio64, 4380 unsigned n_dma, uint32_t *liobns, 4381 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4382 { 4383 spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns, 4384 nv2gpa, nv2atsd, errp); 4385 *nv2gpa = 0; 4386 *nv2atsd = 0; 4387 } 4388 4389 static void spapr_machine_3_1_class_options(MachineClass *mc) 4390 { 4391 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4392 4393 spapr_machine_4_0_class_options(mc); 4394 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4395 4396 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4397 smc->update_dt_enabled = false; 4398 smc->dr_phb_enabled = false; 4399 smc->broken_host_serial_model = true; 4400 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4401 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4402 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4403 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4404 smc->phb_placement = phb_placement_3_1; 4405 } 4406 4407 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4408 4409 /* 4410 * pseries-3.0 4411 */ 4412 4413 static void spapr_machine_3_0_class_options(MachineClass *mc) 4414 { 4415 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4416 4417 spapr_machine_3_1_class_options(mc); 4418 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4419 4420 smc->legacy_irq_allocation = true; 4421 smc->irq = &spapr_irq_xics_legacy; 4422 } 4423 4424 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4425 4426 /* 4427 * pseries-2.12 4428 */ 4429 static void spapr_machine_2_12_class_options(MachineClass *mc) 4430 { 4431 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4432 static GlobalProperty compat[] = { 4433 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4434 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4435 }; 4436 4437 spapr_machine_3_0_class_options(mc); 4438 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4439 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4440 4441 /* We depend on kvm_enabled() to choose a default value for the 4442 * hpt-max-page-size capability. Of course we can't do it here 4443 * because this is too early and the HW accelerator isn't initialzed 4444 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4445 */ 4446 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4447 } 4448 4449 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4450 4451 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4452 { 4453 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4454 4455 spapr_machine_2_12_class_options(mc); 4456 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4457 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4458 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4459 } 4460 4461 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4462 4463 /* 4464 * pseries-2.11 4465 */ 4466 4467 static void spapr_machine_2_11_class_options(MachineClass *mc) 4468 { 4469 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4470 4471 spapr_machine_2_12_class_options(mc); 4472 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4473 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4474 } 4475 4476 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4477 4478 /* 4479 * pseries-2.10 4480 */ 4481 4482 static void spapr_machine_2_10_class_options(MachineClass *mc) 4483 { 4484 spapr_machine_2_11_class_options(mc); 4485 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4486 } 4487 4488 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4489 4490 /* 4491 * pseries-2.9 4492 */ 4493 4494 static void spapr_machine_2_9_class_options(MachineClass *mc) 4495 { 4496 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4497 static GlobalProperty compat[] = { 4498 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4499 }; 4500 4501 spapr_machine_2_10_class_options(mc); 4502 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4503 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4504 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4505 smc->pre_2_10_has_unused_icps = true; 4506 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4507 } 4508 4509 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4510 4511 /* 4512 * pseries-2.8 4513 */ 4514 4515 static void spapr_machine_2_8_class_options(MachineClass *mc) 4516 { 4517 static GlobalProperty compat[] = { 4518 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4519 }; 4520 4521 spapr_machine_2_9_class_options(mc); 4522 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4523 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4524 mc->numa_mem_align_shift = 23; 4525 } 4526 4527 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4528 4529 /* 4530 * pseries-2.7 4531 */ 4532 4533 static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4534 uint64_t *buid, hwaddr *pio, 4535 hwaddr *mmio32, hwaddr *mmio64, 4536 unsigned n_dma, uint32_t *liobns, 4537 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4538 { 4539 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4540 const uint64_t base_buid = 0x800000020000000ULL; 4541 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4542 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4543 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4544 const uint32_t max_index = 255; 4545 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4546 4547 uint64_t ram_top = MACHINE(spapr)->ram_size; 4548 hwaddr phb0_base, phb_base; 4549 int i; 4550 4551 /* Do we have device memory? */ 4552 if (MACHINE(spapr)->maxram_size > ram_top) { 4553 /* Can't just use maxram_size, because there may be an 4554 * alignment gap between normal and device memory regions 4555 */ 4556 ram_top = MACHINE(spapr)->device_memory->base + 4557 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4558 } 4559 4560 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4561 4562 if (index > max_index) { 4563 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4564 max_index); 4565 return; 4566 } 4567 4568 *buid = base_buid + index; 4569 for (i = 0; i < n_dma; ++i) { 4570 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4571 } 4572 4573 phb_base = phb0_base + index * phb_spacing; 4574 *pio = phb_base + pio_offset; 4575 *mmio32 = phb_base + mmio_offset; 4576 /* 4577 * We don't set the 64-bit MMIO window, relying on the PHB's 4578 * fallback behaviour of automatically splitting a large "32-bit" 4579 * window into contiguous 32-bit and 64-bit windows 4580 */ 4581 4582 *nv2gpa = 0; 4583 *nv2atsd = 0; 4584 } 4585 4586 static void spapr_machine_2_7_class_options(MachineClass *mc) 4587 { 4588 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4589 static GlobalProperty compat[] = { 4590 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4591 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4592 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4593 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4594 }; 4595 4596 spapr_machine_2_8_class_options(mc); 4597 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4598 mc->default_machine_opts = "modern-hotplug-events=off"; 4599 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4600 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4601 smc->phb_placement = phb_placement_2_7; 4602 } 4603 4604 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4605 4606 /* 4607 * pseries-2.6 4608 */ 4609 4610 static void spapr_machine_2_6_class_options(MachineClass *mc) 4611 { 4612 static GlobalProperty compat[] = { 4613 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4614 }; 4615 4616 spapr_machine_2_7_class_options(mc); 4617 mc->has_hotpluggable_cpus = false; 4618 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4619 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4620 } 4621 4622 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4623 4624 /* 4625 * pseries-2.5 4626 */ 4627 4628 static void spapr_machine_2_5_class_options(MachineClass *mc) 4629 { 4630 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4631 static GlobalProperty compat[] = { 4632 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4633 }; 4634 4635 spapr_machine_2_6_class_options(mc); 4636 smc->use_ohci_by_default = true; 4637 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4638 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4639 } 4640 4641 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4642 4643 /* 4644 * pseries-2.4 4645 */ 4646 4647 static void spapr_machine_2_4_class_options(MachineClass *mc) 4648 { 4649 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4650 4651 spapr_machine_2_5_class_options(mc); 4652 smc->dr_lmb_enabled = false; 4653 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4654 } 4655 4656 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4657 4658 /* 4659 * pseries-2.3 4660 */ 4661 4662 static void spapr_machine_2_3_class_options(MachineClass *mc) 4663 { 4664 static GlobalProperty compat[] = { 4665 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4666 }; 4667 spapr_machine_2_4_class_options(mc); 4668 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4669 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4670 } 4671 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4672 4673 /* 4674 * pseries-2.2 4675 */ 4676 4677 static void spapr_machine_2_2_class_options(MachineClass *mc) 4678 { 4679 static GlobalProperty compat[] = { 4680 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4681 }; 4682 4683 spapr_machine_2_3_class_options(mc); 4684 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4685 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4686 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4687 } 4688 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4689 4690 /* 4691 * pseries-2.1 4692 */ 4693 4694 static void spapr_machine_2_1_class_options(MachineClass *mc) 4695 { 4696 spapr_machine_2_2_class_options(mc); 4697 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4698 } 4699 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4700 4701 static void spapr_machine_register_types(void) 4702 { 4703 type_register_static(&spapr_machine_info); 4704 } 4705 4706 type_init(spapr_machine_register_types) 4707