1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu/datadir.h" 29 #include "qemu/memalign.h" 30 #include "qemu/guest-random.h" 31 #include "qapi/error.h" 32 #include "qapi/qapi-events-machine.h" 33 #include "qapi/qapi-events-qdev.h" 34 #include "qapi/visitor.h" 35 #include "sysemu/sysemu.h" 36 #include "sysemu/hostmem.h" 37 #include "sysemu/numa.h" 38 #include "sysemu/qtest.h" 39 #include "sysemu/reset.h" 40 #include "sysemu/runstate.h" 41 #include "qemu/log.h" 42 #include "hw/fw-path-provider.h" 43 #include "elf.h" 44 #include "net/net.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/cpus.h" 47 #include "sysemu/hw_accel.h" 48 #include "kvm_ppc.h" 49 #include "migration/misc.h" 50 #include "migration/qemu-file-types.h" 51 #include "migration/global_state.h" 52 #include "migration/register.h" 53 #include "migration/blocker.h" 54 #include "mmu-hash64.h" 55 #include "mmu-book3s-v3.h" 56 #include "cpu-models.h" 57 #include "hw/core/cpu.h" 58 59 #include "hw/ppc/ppc.h" 60 #include "hw/loader.h" 61 62 #include "hw/ppc/fdt.h" 63 #include "hw/ppc/spapr.h" 64 #include "hw/ppc/spapr_nested.h" 65 #include "hw/ppc/spapr_vio.h" 66 #include "hw/ppc/vof.h" 67 #include "hw/qdev-properties.h" 68 #include "hw/pci-host/spapr.h" 69 #include "hw/pci/msi.h" 70 71 #include "hw/pci/pci.h" 72 #include "hw/scsi/scsi.h" 73 #include "hw/virtio/virtio-scsi.h" 74 #include "hw/virtio/vhost-scsi-common.h" 75 76 #include "exec/ram_addr.h" 77 #include "hw/usb.h" 78 #include "qemu/config-file.h" 79 #include "qemu/error-report.h" 80 #include "trace.h" 81 #include "hw/nmi.h" 82 #include "hw/intc/intc.h" 83 84 #include "hw/ppc/spapr_cpu_core.h" 85 #include "hw/mem/memory-device.h" 86 #include "hw/ppc/spapr_tpm_proxy.h" 87 #include "hw/ppc/spapr_nvdimm.h" 88 #include "hw/ppc/spapr_numa.h" 89 #include "hw/ppc/pef.h" 90 91 #include "monitor/monitor.h" 92 93 #include <libfdt.h> 94 95 /* SLOF memory layout: 96 * 97 * SLOF raw image loaded at 0, copies its romfs right below the flat 98 * device-tree, then position SLOF itself 31M below that 99 * 100 * So we set FW_OVERHEAD to 40MB which should account for all of that 101 * and more 102 * 103 * We load our kernel at 4M, leaving space for SLOF initial image 104 */ 105 #define FDT_MAX_ADDR 0x80000000 /* FDT must stay below that */ 106 #define FW_MAX_SIZE 0x400000 107 #define FW_FILE_NAME "slof.bin" 108 #define FW_FILE_NAME_VOF "vof.bin" 109 #define FW_OVERHEAD 0x2800000 110 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 111 112 #define MIN_RMA_SLOF (128 * MiB) 113 114 #define PHANDLE_INTC 0x00001111 115 116 /* These two functions implement the VCPU id numbering: one to compute them 117 * all and one to identify thread 0 of a VCORE. Any change to the first one 118 * is likely to have an impact on the second one, so let's keep them close. 119 */ 120 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 121 { 122 MachineState *ms = MACHINE(spapr); 123 unsigned int smp_threads = ms->smp.threads; 124 125 assert(spapr->vsmt); 126 return 127 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 128 } 129 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 130 PowerPCCPU *cpu) 131 { 132 assert(spapr->vsmt); 133 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 134 } 135 136 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 137 { 138 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 139 * and newer QEMUs don't even have them. In both cases, we don't want 140 * to send anything on the wire. 141 */ 142 return false; 143 } 144 145 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 146 /* 147 * Hack ahead. We can't have two devices with the same name and 148 * instance id. So I rename this to pass make check. 149 * Real help from people who knows the hardware is needed. 150 */ 151 .name = "icp/server", 152 .version_id = 1, 153 .minimum_version_id = 1, 154 .needed = pre_2_10_vmstate_dummy_icp_needed, 155 .fields = (const VMStateField[]) { 156 VMSTATE_UNUSED(4), /* uint32_t xirr */ 157 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 158 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 159 VMSTATE_END_OF_LIST() 160 }, 161 }; 162 163 /* 164 * See comment in hw/intc/xics.c:icp_realize() 165 * 166 * You have to remove vmstate_replace_hack_for_ppc() when you remove 167 * the machine types that need the following function. 168 */ 169 static void pre_2_10_vmstate_register_dummy_icp(int i) 170 { 171 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 172 (void *)(uintptr_t) i); 173 } 174 175 /* 176 * See comment in hw/intc/xics.c:icp_realize() 177 * 178 * You have to remove vmstate_replace_hack_for_ppc() when you remove 179 * the machine types that need the following function. 180 */ 181 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 182 { 183 /* 184 * This used to be: 185 * 186 * vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 187 * (void *)(uintptr_t) i); 188 */ 189 } 190 191 int spapr_max_server_number(SpaprMachineState *spapr) 192 { 193 MachineState *ms = MACHINE(spapr); 194 195 assert(spapr->vsmt); 196 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 197 } 198 199 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 200 int smt_threads) 201 { 202 int i, ret = 0; 203 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads); 204 g_autofree uint32_t *gservers_prop = g_new(uint32_t, smt_threads * 2); 205 int index = spapr_get_vcpu_id(cpu); 206 207 if (cpu->compat_pvr) { 208 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 209 if (ret < 0) { 210 return ret; 211 } 212 } 213 214 /* Build interrupt servers and gservers properties */ 215 for (i = 0; i < smt_threads; i++) { 216 servers_prop[i] = cpu_to_be32(index + i); 217 /* Hack, direct the group queues back to cpu 0 */ 218 gservers_prop[i*2] = cpu_to_be32(index + i); 219 gservers_prop[i*2 + 1] = 0; 220 } 221 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 222 servers_prop, sizeof(*servers_prop) * smt_threads); 223 if (ret < 0) { 224 return ret; 225 } 226 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 227 gservers_prop, sizeof(*gservers_prop) * smt_threads * 2); 228 229 return ret; 230 } 231 232 static void spapr_dt_pa_features(SpaprMachineState *spapr, 233 PowerPCCPU *cpu, 234 void *fdt, int offset) 235 { 236 /* 237 * SSO (SAO) ordering is supported on KVM and thread=single hosts, 238 * but not MTTCG, so disable it. To advertise it, a cap would have 239 * to be added, or support implemented for MTTCG. 240 * 241 * Copy/paste is not supported by TCG, so it is not advertised. KVM 242 * can execute them but it has no accelerator drivers which are usable, 243 * so there isn't much need for it anyway. 244 */ 245 246 /* These should be kept in sync with pnv */ 247 uint8_t pa_features_206[] = { 6, 0, 248 0xf6, 0x1f, 0xc7, 0x00, 0x00, 0xc0 }; 249 uint8_t pa_features_207[] = { 24, 0, 250 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, 251 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 252 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 253 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 254 uint8_t pa_features_300[] = { 66, 0, 255 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 256 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 257 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 258 /* 6: DS207 */ 259 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 260 /* 16: Vector */ 261 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 262 /* 18: Vec. Scalar, 20: Vec. XOR */ 263 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 264 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 265 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 266 /* 32: LE atomic, 34: EBB + ext EBB */ 267 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 268 /* 40: Radix MMU */ 269 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 270 /* 42: PM, 44: PC RA, 46: SC vec'd */ 271 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 272 /* 48: SIMD, 50: QP BFP, 52: String */ 273 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 274 /* 54: DecFP, 56: DecI, 58: SHA */ 275 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 276 /* 60: NM atomic, 62: RNG */ 277 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 278 }; 279 /* 3.1 removes SAO, HTM support */ 280 uint8_t pa_features_31[] = { 74, 0, 281 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 282 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 283 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 284 /* 6: DS207 */ 285 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 286 /* 16: Vector */ 287 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 288 /* 18: Vec. Scalar, 20: Vec. XOR */ 289 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 290 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 291 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 292 /* 32: LE atomic, 34: EBB + ext EBB */ 293 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 294 /* 40: Radix MMU */ 295 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 296 /* 42: PM, 44: PC RA, 46: SC vec'd */ 297 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 298 /* 48: SIMD, 50: QP BFP, 52: String */ 299 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 300 /* 54: DecFP, 56: DecI, 58: SHA */ 301 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 302 /* 60: NM atomic, 62: RNG */ 303 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 304 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */ 305 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */ 306 /* 72: [P]HASHST/[P]HASHCHK */ 307 0x80, 0x00, /* 72 - 73 */ 308 }; 309 uint8_t *pa_features = NULL; 310 size_t pa_size; 311 312 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 313 pa_features = pa_features_206; 314 pa_size = sizeof(pa_features_206); 315 } 316 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 317 pa_features = pa_features_207; 318 pa_size = sizeof(pa_features_207); 319 } 320 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 321 pa_features = pa_features_300; 322 pa_size = sizeof(pa_features_300); 323 } 324 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10, 0, cpu->compat_pvr)) { 325 pa_features = pa_features_31; 326 pa_size = sizeof(pa_features_31); 327 } 328 if (!pa_features) { 329 return; 330 } 331 332 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 333 /* 334 * Note: we keep CI large pages off by default because a 64K capable 335 * guest provisioned with large pages might otherwise try to map a qemu 336 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 337 * even if that qemu runs on a 4k host. 338 * We dd this bit back here if we are confident this is not an issue 339 */ 340 pa_features[3] |= 0x20; 341 } 342 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 343 pa_features[24] |= 0x80; /* Transactional memory support */ 344 } 345 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 346 /* Workaround for broken kernels that attempt (guest) radix 347 * mode when they can't handle it, if they see the radix bit set 348 * in pa-features. So hide it from them. */ 349 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 350 } 351 352 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 353 } 354 355 static hwaddr spapr_node0_size(MachineState *machine) 356 { 357 if (machine->numa_state->num_nodes) { 358 int i; 359 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 360 if (machine->numa_state->nodes[i].node_mem) { 361 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 362 machine->ram_size); 363 } 364 } 365 } 366 return machine->ram_size; 367 } 368 369 static void add_str(GString *s, const gchar *s1) 370 { 371 g_string_append_len(s, s1, strlen(s1) + 1); 372 } 373 374 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 375 hwaddr start, hwaddr size) 376 { 377 char mem_name[32]; 378 uint64_t mem_reg_property[2]; 379 int off; 380 381 mem_reg_property[0] = cpu_to_be64(start); 382 mem_reg_property[1] = cpu_to_be64(size); 383 384 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 385 off = fdt_add_subnode(fdt, 0, mem_name); 386 _FDT(off); 387 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 388 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 389 sizeof(mem_reg_property)))); 390 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 391 return off; 392 } 393 394 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 395 { 396 MemoryDeviceInfoList *info; 397 398 for (info = list; info; info = info->next) { 399 MemoryDeviceInfo *value = info->value; 400 401 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 402 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 403 404 if (addr >= pcdimm_info->addr && 405 addr < (pcdimm_info->addr + pcdimm_info->size)) { 406 return pcdimm_info->node; 407 } 408 } 409 } 410 411 return -1; 412 } 413 414 struct sPAPRDrconfCellV2 { 415 uint32_t seq_lmbs; 416 uint64_t base_addr; 417 uint32_t drc_index; 418 uint32_t aa_index; 419 uint32_t flags; 420 } QEMU_PACKED; 421 422 typedef struct DrconfCellQueue { 423 struct sPAPRDrconfCellV2 cell; 424 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 425 } DrconfCellQueue; 426 427 static DrconfCellQueue * 428 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 429 uint32_t drc_index, uint32_t aa_index, 430 uint32_t flags) 431 { 432 DrconfCellQueue *elem; 433 434 elem = g_malloc0(sizeof(*elem)); 435 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 436 elem->cell.base_addr = cpu_to_be64(base_addr); 437 elem->cell.drc_index = cpu_to_be32(drc_index); 438 elem->cell.aa_index = cpu_to_be32(aa_index); 439 elem->cell.flags = cpu_to_be32(flags); 440 441 return elem; 442 } 443 444 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 445 int offset, MemoryDeviceInfoList *dimms) 446 { 447 MachineState *machine = MACHINE(spapr); 448 uint8_t *int_buf, *cur_index; 449 int ret; 450 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 451 uint64_t addr, cur_addr, size; 452 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 453 uint64_t mem_end = machine->device_memory->base + 454 memory_region_size(&machine->device_memory->mr); 455 uint32_t node, buf_len, nr_entries = 0; 456 SpaprDrc *drc; 457 DrconfCellQueue *elem, *next; 458 MemoryDeviceInfoList *info; 459 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 460 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 461 462 /* Entry to cover RAM and the gap area */ 463 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 464 SPAPR_LMB_FLAGS_RESERVED | 465 SPAPR_LMB_FLAGS_DRC_INVALID); 466 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 467 nr_entries++; 468 469 cur_addr = machine->device_memory->base; 470 for (info = dimms; info; info = info->next) { 471 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 472 473 addr = di->addr; 474 size = di->size; 475 node = di->node; 476 477 /* 478 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 479 * area is marked hotpluggable in the next iteration for the bigger 480 * chunk including the NVDIMM occupied area. 481 */ 482 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 483 continue; 484 485 /* Entry for hot-pluggable area */ 486 if (cur_addr < addr) { 487 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 488 g_assert(drc); 489 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 490 cur_addr, spapr_drc_index(drc), -1, 0); 491 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 492 nr_entries++; 493 } 494 495 /* Entry for DIMM */ 496 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 497 g_assert(drc); 498 elem = spapr_get_drconf_cell(size / lmb_size, addr, 499 spapr_drc_index(drc), node, 500 (SPAPR_LMB_FLAGS_ASSIGNED | 501 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 502 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 503 nr_entries++; 504 cur_addr = addr + size; 505 } 506 507 /* Entry for remaining hotpluggable area */ 508 if (cur_addr < mem_end) { 509 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 510 g_assert(drc); 511 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 512 cur_addr, spapr_drc_index(drc), -1, 0); 513 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 514 nr_entries++; 515 } 516 517 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 518 int_buf = cur_index = g_malloc0(buf_len); 519 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 520 cur_index += sizeof(nr_entries); 521 522 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 523 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 524 cur_index += sizeof(elem->cell); 525 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 526 g_free(elem); 527 } 528 529 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 530 g_free(int_buf); 531 if (ret < 0) { 532 return -1; 533 } 534 return 0; 535 } 536 537 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 538 int offset, MemoryDeviceInfoList *dimms) 539 { 540 MachineState *machine = MACHINE(spapr); 541 int i, ret; 542 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 543 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 544 uint32_t nr_lmbs = (machine->device_memory->base + 545 memory_region_size(&machine->device_memory->mr)) / 546 lmb_size; 547 uint32_t *int_buf, *cur_index, buf_len; 548 549 /* 550 * Allocate enough buffer size to fit in ibm,dynamic-memory 551 */ 552 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 553 cur_index = int_buf = g_malloc0(buf_len); 554 int_buf[0] = cpu_to_be32(nr_lmbs); 555 cur_index++; 556 for (i = 0; i < nr_lmbs; i++) { 557 uint64_t addr = i * lmb_size; 558 uint32_t *dynamic_memory = cur_index; 559 560 if (i >= device_lmb_start) { 561 SpaprDrc *drc; 562 563 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 564 g_assert(drc); 565 566 dynamic_memory[0] = cpu_to_be32(addr >> 32); 567 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 568 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 569 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 570 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 571 if (memory_region_present(get_system_memory(), addr)) { 572 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 573 } else { 574 dynamic_memory[5] = cpu_to_be32(0); 575 } 576 } else { 577 /* 578 * LMB information for RMA, boot time RAM and gap b/n RAM and 579 * device memory region -- all these are marked as reserved 580 * and as having no valid DRC. 581 */ 582 dynamic_memory[0] = cpu_to_be32(addr >> 32); 583 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 584 dynamic_memory[2] = cpu_to_be32(0); 585 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 586 dynamic_memory[4] = cpu_to_be32(-1); 587 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 588 SPAPR_LMB_FLAGS_DRC_INVALID); 589 } 590 591 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 592 } 593 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 594 g_free(int_buf); 595 if (ret < 0) { 596 return -1; 597 } 598 return 0; 599 } 600 601 /* 602 * Adds ibm,dynamic-reconfiguration-memory node. 603 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 604 * of this device tree node. 605 */ 606 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 607 void *fdt) 608 { 609 MachineState *machine = MACHINE(spapr); 610 int ret, offset; 611 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 612 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 613 cpu_to_be32(lmb_size & 0xffffffff)}; 614 MemoryDeviceInfoList *dimms = NULL; 615 616 /* Don't create the node if there is no device memory. */ 617 if (!machine->device_memory) { 618 return 0; 619 } 620 621 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 622 623 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 624 sizeof(prop_lmb_size)); 625 if (ret < 0) { 626 return ret; 627 } 628 629 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 630 if (ret < 0) { 631 return ret; 632 } 633 634 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 635 if (ret < 0) { 636 return ret; 637 } 638 639 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 640 dimms = qmp_memory_device_list(); 641 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 642 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 643 } else { 644 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 645 } 646 qapi_free_MemoryDeviceInfoList(dimms); 647 648 if (ret < 0) { 649 return ret; 650 } 651 652 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 653 654 return ret; 655 } 656 657 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 658 { 659 MachineState *machine = MACHINE(spapr); 660 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 661 hwaddr mem_start, node_size; 662 int i, nb_nodes = machine->numa_state->num_nodes; 663 NodeInfo *nodes = machine->numa_state->nodes; 664 665 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 666 if (!nodes[i].node_mem) { 667 continue; 668 } 669 if (mem_start >= machine->ram_size) { 670 node_size = 0; 671 } else { 672 node_size = nodes[i].node_mem; 673 if (node_size > machine->ram_size - mem_start) { 674 node_size = machine->ram_size - mem_start; 675 } 676 } 677 if (!mem_start) { 678 /* spapr_machine_init() checks for rma_size <= node0_size 679 * already */ 680 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 681 mem_start += spapr->rma_size; 682 node_size -= spapr->rma_size; 683 } 684 for ( ; node_size; ) { 685 hwaddr sizetmp = pow2floor(node_size); 686 687 /* mem_start != 0 here */ 688 if (ctzl(mem_start) < ctzl(sizetmp)) { 689 sizetmp = 1ULL << ctzl(mem_start); 690 } 691 692 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 693 node_size -= sizetmp; 694 mem_start += sizetmp; 695 } 696 } 697 698 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 699 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 700 int ret; 701 702 g_assert(smc->dr_lmb_enabled); 703 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 704 if (ret) { 705 return ret; 706 } 707 } 708 709 return 0; 710 } 711 712 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 713 SpaprMachineState *spapr) 714 { 715 MachineState *ms = MACHINE(spapr); 716 PowerPCCPU *cpu = POWERPC_CPU(cs); 717 CPUPPCState *env = &cpu->env; 718 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 719 int index = spapr_get_vcpu_id(cpu); 720 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 721 0xffffffff, 0xffffffff}; 722 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 723 : SPAPR_TIMEBASE_FREQ; 724 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 725 uint32_t page_sizes_prop[64]; 726 size_t page_sizes_prop_size; 727 unsigned int smp_threads = ms->smp.threads; 728 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 729 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 730 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 731 SpaprDrc *drc; 732 int drc_index; 733 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 734 int i; 735 736 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 737 if (drc) { 738 drc_index = spapr_drc_index(drc); 739 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 740 } 741 742 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 743 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 744 745 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 746 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 747 env->dcache_line_size))); 748 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 749 env->dcache_line_size))); 750 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 751 env->icache_line_size))); 752 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 753 env->icache_line_size))); 754 755 if (pcc->l1_dcache_size) { 756 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 757 pcc->l1_dcache_size))); 758 } else { 759 warn_report("Unknown L1 dcache size for cpu"); 760 } 761 if (pcc->l1_icache_size) { 762 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 763 pcc->l1_icache_size))); 764 } else { 765 warn_report("Unknown L1 icache size for cpu"); 766 } 767 768 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 769 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 770 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 771 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 772 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 773 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 774 775 if (ppc_has_spr(cpu, SPR_PURR)) { 776 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 777 } 778 if (ppc_has_spr(cpu, SPR_PURR)) { 779 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 780 } 781 782 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 783 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 784 segs, sizeof(segs)))); 785 } 786 787 /* Advertise VSX (vector extensions) if available 788 * 1 == VMX / Altivec available 789 * 2 == VSX available 790 * 791 * Only CPUs for which we create core types in spapr_cpu_core.c 792 * are possible, and all of those have VMX */ 793 if (env->insns_flags & PPC_ALTIVEC) { 794 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 795 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 796 } else { 797 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 798 } 799 } 800 801 /* Advertise DFP (Decimal Floating Point) if available 802 * 0 / no property == no DFP 803 * 1 == DFP available */ 804 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 805 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 806 } 807 808 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 809 sizeof(page_sizes_prop)); 810 if (page_sizes_prop_size) { 811 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 812 page_sizes_prop, page_sizes_prop_size))); 813 } 814 815 spapr_dt_pa_features(spapr, cpu, fdt, offset); 816 817 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 818 cs->cpu_index / vcpus_per_socket))); 819 820 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 821 pft_size_prop, sizeof(pft_size_prop)))); 822 823 if (ms->numa_state->num_nodes > 1) { 824 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 825 } 826 827 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 828 829 if (pcc->radix_page_info) { 830 for (i = 0; i < pcc->radix_page_info->count; i++) { 831 radix_AP_encodings[i] = 832 cpu_to_be32(pcc->radix_page_info->entries[i]); 833 } 834 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 835 radix_AP_encodings, 836 pcc->radix_page_info->count * 837 sizeof(radix_AP_encodings[0])))); 838 } 839 840 /* 841 * We set this property to let the guest know that it can use the large 842 * decrementer and its width in bits. 843 */ 844 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 845 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 846 pcc->lrg_decr_bits))); 847 } 848 849 static void spapr_dt_one_cpu(void *fdt, SpaprMachineState *spapr, CPUState *cs, 850 int cpus_offset) 851 { 852 PowerPCCPU *cpu = POWERPC_CPU(cs); 853 int index = spapr_get_vcpu_id(cpu); 854 DeviceClass *dc = DEVICE_GET_CLASS(cs); 855 g_autofree char *nodename = NULL; 856 int offset; 857 858 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 859 return; 860 } 861 862 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 863 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 864 _FDT(offset); 865 spapr_dt_cpu(cs, fdt, offset, spapr); 866 } 867 868 869 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 870 { 871 CPUState **rev; 872 CPUState *cs; 873 int n_cpus; 874 int cpus_offset; 875 int i; 876 877 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 878 _FDT(cpus_offset); 879 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 880 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 881 882 /* 883 * We walk the CPUs in reverse order to ensure that CPU DT nodes 884 * created by fdt_add_subnode() end up in the right order in FDT 885 * for the guest kernel the enumerate the CPUs correctly. 886 * 887 * The CPU list cannot be traversed in reverse order, so we need 888 * to do extra work. 889 */ 890 n_cpus = 0; 891 rev = NULL; 892 CPU_FOREACH(cs) { 893 rev = g_renew(CPUState *, rev, n_cpus + 1); 894 rev[n_cpus++] = cs; 895 } 896 897 for (i = n_cpus - 1; i >= 0; i--) { 898 spapr_dt_one_cpu(fdt, spapr, rev[i], cpus_offset); 899 } 900 901 g_free(rev); 902 } 903 904 static int spapr_dt_rng(void *fdt) 905 { 906 int node; 907 int ret; 908 909 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 910 if (node <= 0) { 911 return -1; 912 } 913 ret = fdt_setprop_string(fdt, node, "device_type", 914 "ibm,platform-facilities"); 915 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 916 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 917 918 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 919 if (node <= 0) { 920 return -1; 921 } 922 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 923 924 return ret ? -1 : 0; 925 } 926 927 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 928 { 929 MachineState *ms = MACHINE(spapr); 930 int rtas; 931 GString *hypertas = g_string_sized_new(256); 932 GString *qemu_hypertas = g_string_sized_new(256); 933 uint32_t lrdr_capacity[] = { 934 0, 935 0, 936 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 937 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 938 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 939 }; 940 941 /* Do we have device memory? */ 942 if (MACHINE(spapr)->device_memory) { 943 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 944 memory_region_size(&MACHINE(spapr)->device_memory->mr); 945 946 lrdr_capacity[0] = cpu_to_be32(max_device_addr >> 32); 947 lrdr_capacity[1] = cpu_to_be32(max_device_addr & 0xffffffff); 948 } 949 950 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 951 952 /* hypertas */ 953 add_str(hypertas, "hcall-pft"); 954 add_str(hypertas, "hcall-term"); 955 add_str(hypertas, "hcall-dabr"); 956 add_str(hypertas, "hcall-interrupt"); 957 add_str(hypertas, "hcall-tce"); 958 add_str(hypertas, "hcall-vio"); 959 add_str(hypertas, "hcall-splpar"); 960 add_str(hypertas, "hcall-join"); 961 add_str(hypertas, "hcall-bulk"); 962 add_str(hypertas, "hcall-set-mode"); 963 add_str(hypertas, "hcall-sprg0"); 964 add_str(hypertas, "hcall-copy"); 965 add_str(hypertas, "hcall-debug"); 966 add_str(hypertas, "hcall-vphn"); 967 if (spapr_get_cap(spapr, SPAPR_CAP_RPT_INVALIDATE) == SPAPR_CAP_ON) { 968 add_str(hypertas, "hcall-rpt-invalidate"); 969 } 970 971 add_str(qemu_hypertas, "hcall-memop1"); 972 973 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 974 add_str(hypertas, "hcall-multi-tce"); 975 } 976 977 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 978 add_str(hypertas, "hcall-hpt-resize"); 979 } 980 981 add_str(hypertas, "hcall-watchdog"); 982 983 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 984 hypertas->str, hypertas->len)); 985 g_string_free(hypertas, TRUE); 986 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 987 qemu_hypertas->str, qemu_hypertas->len)); 988 g_string_free(qemu_hypertas, TRUE); 989 990 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 991 992 /* 993 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 994 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 995 * 996 * The system reset requirements are driven by existing Linux and PowerVM 997 * implementation which (contrary to PAPR) saves r3 in the error log 998 * structure like machine check, so Linux expects to find the saved r3 999 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 1000 * does not look at the error value). 1001 * 1002 * System reset interrupts are not subject to interlock like machine 1003 * check, so this memory area could be corrupted if the sreset is 1004 * interrupted by a machine check (or vice versa) if it was shared. To 1005 * prevent this, system reset uses per-CPU areas for the sreset save 1006 * area. A system reset that interrupts a system reset handler could 1007 * still overwrite this area, but Linux doesn't try to recover in that 1008 * case anyway. 1009 * 1010 * The extra 8 bytes is required because Linux's FWNMI error log check 1011 * is off-by-one. 1012 * 1013 * RTAS_MIN_SIZE is required for the RTAS blob itself. 1014 */ 1015 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_MIN_SIZE + 1016 RTAS_ERROR_LOG_MAX + 1017 ms->smp.max_cpus * sizeof(uint64_t) * 2 + 1018 sizeof(uint64_t))); 1019 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 1020 RTAS_ERROR_LOG_MAX)); 1021 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 1022 RTAS_EVENT_SCAN_RATE)); 1023 1024 g_assert(msi_nonbroken); 1025 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 1026 1027 /* 1028 * According to PAPR, rtas ibm,os-term does not guarantee a return 1029 * back to the guest cpu. 1030 * 1031 * While an additional ibm,extended-os-term property indicates 1032 * that rtas call return will always occur. Set this property. 1033 */ 1034 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 1035 1036 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 1037 lrdr_capacity, sizeof(lrdr_capacity))); 1038 1039 spapr_dt_rtas_tokens(fdt, rtas); 1040 } 1041 1042 /* 1043 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 1044 * and the XIVE features that the guest may request and thus the valid 1045 * values for bytes 23..26 of option vector 5: 1046 */ 1047 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 1048 int chosen) 1049 { 1050 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1051 1052 char val[2 * 4] = { 1053 23, 0x00, /* XICS / XIVE mode */ 1054 24, 0x00, /* Hash/Radix, filled in below. */ 1055 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1056 26, 0x40, /* Radix options: GTSE == yes. */ 1057 }; 1058 1059 if (spapr->irq->xics && spapr->irq->xive) { 1060 val[1] = SPAPR_OV5_XIVE_BOTH; 1061 } else if (spapr->irq->xive) { 1062 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 1063 } else { 1064 assert(spapr->irq->xics); 1065 val[1] = SPAPR_OV5_XIVE_LEGACY; 1066 } 1067 1068 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1069 first_ppc_cpu->compat_pvr)) { 1070 /* 1071 * If we're in a pre POWER9 compat mode then the guest should 1072 * do hash and use the legacy interrupt mode 1073 */ 1074 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 1075 val[3] = 0x00; /* Hash */ 1076 spapr_check_mmu_mode(false); 1077 } else if (kvm_enabled()) { 1078 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1079 val[3] = 0x80; /* OV5_MMU_BOTH */ 1080 } else if (kvmppc_has_cap_mmu_radix()) { 1081 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1082 } else { 1083 val[3] = 0x00; /* Hash */ 1084 } 1085 } else { 1086 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1087 val[3] = 0xC0; 1088 } 1089 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1090 val, sizeof(val))); 1091 } 1092 1093 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1094 { 1095 MachineState *machine = MACHINE(spapr); 1096 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1097 int chosen; 1098 1099 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1100 1101 if (reset) { 1102 const char *boot_device = spapr->boot_device; 1103 g_autofree char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1104 size_t cb = 0; 1105 g_autofree char *bootlist = get_boot_devices_list(&cb); 1106 1107 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1108 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1109 machine->kernel_cmdline)); 1110 } 1111 1112 if (spapr->initrd_size) { 1113 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1114 spapr->initrd_base)); 1115 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1116 spapr->initrd_base + spapr->initrd_size)); 1117 } 1118 1119 if (spapr->kernel_size) { 1120 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1121 cpu_to_be64(spapr->kernel_size) }; 1122 1123 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1124 &kprop, sizeof(kprop))); 1125 if (spapr->kernel_le) { 1126 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1127 } 1128 } 1129 if (machine->boot_config.has_menu && machine->boot_config.menu) { 1130 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", true))); 1131 } 1132 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1133 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1134 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1135 1136 if (cb && bootlist) { 1137 int i; 1138 1139 for (i = 0; i < cb; i++) { 1140 if (bootlist[i] == '\n') { 1141 bootlist[i] = ' '; 1142 } 1143 } 1144 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1145 } 1146 1147 if (boot_device && strlen(boot_device)) { 1148 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1149 } 1150 1151 if (spapr->want_stdout_path && stdout_path) { 1152 /* 1153 * "linux,stdout-path" and "stdout" properties are 1154 * deprecated by linux kernel. New platforms should only 1155 * use the "stdout-path" property. Set the new property 1156 * and continue using older property to remain compatible 1157 * with the existing firmware. 1158 */ 1159 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1160 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1161 } 1162 1163 /* 1164 * We can deal with BAR reallocation just fine, advertise it 1165 * to the guest 1166 */ 1167 if (smc->linux_pci_probe) { 1168 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1169 } 1170 1171 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1172 } 1173 1174 _FDT(fdt_setprop(fdt, chosen, "rng-seed", spapr->fdt_rng_seed, 32)); 1175 1176 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1177 } 1178 1179 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1180 { 1181 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1182 * KVM to work under pHyp with some guest co-operation */ 1183 int hypervisor; 1184 uint8_t hypercall[16]; 1185 1186 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1187 /* indicate KVM hypercall interface */ 1188 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1189 if (kvmppc_has_cap_fixup_hcalls()) { 1190 /* 1191 * Older KVM versions with older guest kernels were broken 1192 * with the magic page, don't allow the guest to map it. 1193 */ 1194 if (!kvmppc_get_hypercall(cpu_env(first_cpu), hypercall, 1195 sizeof(hypercall))) { 1196 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1197 hypercall, sizeof(hypercall))); 1198 } 1199 } 1200 } 1201 1202 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1203 { 1204 MachineState *machine = MACHINE(spapr); 1205 MachineClass *mc = MACHINE_GET_CLASS(machine); 1206 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1207 uint32_t root_drc_type_mask = 0; 1208 int ret; 1209 void *fdt; 1210 SpaprPhbState *phb; 1211 char *buf; 1212 1213 fdt = g_malloc0(space); 1214 _FDT((fdt_create_empty_tree(fdt, space))); 1215 1216 /* Root node */ 1217 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1218 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1219 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1220 1221 /* Guest UUID & Name*/ 1222 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1223 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1224 if (qemu_uuid_set) { 1225 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1226 } 1227 g_free(buf); 1228 1229 if (qemu_get_vm_name()) { 1230 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1231 qemu_get_vm_name())); 1232 } 1233 1234 /* Host Model & Serial Number */ 1235 if (spapr->host_model) { 1236 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1237 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1238 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1239 g_free(buf); 1240 } 1241 1242 if (spapr->host_serial) { 1243 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1244 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1245 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1246 g_free(buf); 1247 } 1248 1249 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1250 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1251 1252 /* /interrupt controller */ 1253 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1254 1255 ret = spapr_dt_memory(spapr, fdt); 1256 if (ret < 0) { 1257 error_report("couldn't setup memory nodes in fdt"); 1258 exit(1); 1259 } 1260 1261 /* /vdevice */ 1262 spapr_dt_vdevice(spapr->vio_bus, fdt); 1263 1264 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1265 ret = spapr_dt_rng(fdt); 1266 if (ret < 0) { 1267 error_report("could not set up rng device in the fdt"); 1268 exit(1); 1269 } 1270 } 1271 1272 QLIST_FOREACH(phb, &spapr->phbs, list) { 1273 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1274 if (ret < 0) { 1275 error_report("couldn't setup PCI devices in fdt"); 1276 exit(1); 1277 } 1278 } 1279 1280 spapr_dt_cpus(fdt, spapr); 1281 1282 /* ibm,drc-indexes and friends */ 1283 if (smc->dr_lmb_enabled) { 1284 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; 1285 } 1286 if (smc->dr_phb_enabled) { 1287 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; 1288 } 1289 if (mc->nvdimm_supported) { 1290 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM; 1291 } 1292 if (root_drc_type_mask) { 1293 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask)); 1294 } 1295 1296 if (mc->has_hotpluggable_cpus) { 1297 int offset = fdt_path_offset(fdt, "/cpus"); 1298 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1299 if (ret < 0) { 1300 error_report("Couldn't set up CPU DR device tree properties"); 1301 exit(1); 1302 } 1303 } 1304 1305 /* /event-sources */ 1306 spapr_dt_events(spapr, fdt); 1307 1308 /* /rtas */ 1309 spapr_dt_rtas(spapr, fdt); 1310 1311 /* /chosen */ 1312 spapr_dt_chosen(spapr, fdt, reset); 1313 1314 /* /hypervisor */ 1315 if (kvm_enabled()) { 1316 spapr_dt_hypervisor(spapr, fdt); 1317 } 1318 1319 /* Build memory reserve map */ 1320 if (reset) { 1321 if (spapr->kernel_size) { 1322 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1323 spapr->kernel_size))); 1324 } 1325 if (spapr->initrd_size) { 1326 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1327 spapr->initrd_size))); 1328 } 1329 } 1330 1331 /* NVDIMM devices */ 1332 if (mc->nvdimm_supported) { 1333 spapr_dt_persistent_memory(spapr, fdt); 1334 } 1335 1336 return fdt; 1337 } 1338 1339 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1340 { 1341 SpaprMachineState *spapr = opaque; 1342 1343 return (addr & 0x0fffffff) + spapr->kernel_addr; 1344 } 1345 1346 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1347 PowerPCCPU *cpu) 1348 { 1349 CPUPPCState *env = &cpu->env; 1350 1351 /* The TCG path should also be holding the BQL at this point */ 1352 g_assert(bql_locked()); 1353 1354 g_assert(!vhyp_cpu_in_nested(cpu)); 1355 1356 if (FIELD_EX64(env->msr, MSR, PR)) { 1357 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1358 env->gpr[3] = H_PRIVILEGE; 1359 } else { 1360 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1361 } 1362 } 1363 1364 struct LPCRSyncState { 1365 target_ulong value; 1366 target_ulong mask; 1367 }; 1368 1369 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1370 { 1371 struct LPCRSyncState *s = arg.host_ptr; 1372 PowerPCCPU *cpu = POWERPC_CPU(cs); 1373 CPUPPCState *env = &cpu->env; 1374 target_ulong lpcr; 1375 1376 cpu_synchronize_state(cs); 1377 lpcr = env->spr[SPR_LPCR]; 1378 lpcr &= ~s->mask; 1379 lpcr |= s->value; 1380 ppc_store_lpcr(cpu, lpcr); 1381 } 1382 1383 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1384 { 1385 CPUState *cs; 1386 struct LPCRSyncState s = { 1387 .value = value, 1388 .mask = mask 1389 }; 1390 CPU_FOREACH(cs) { 1391 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1392 } 1393 } 1394 1395 /* May be used when the machine is not running */ 1396 void spapr_init_all_lpcrs(target_ulong value, target_ulong mask) 1397 { 1398 CPUState *cs; 1399 CPU_FOREACH(cs) { 1400 PowerPCCPU *cpu = POWERPC_CPU(cs); 1401 CPUPPCState *env = &cpu->env; 1402 target_ulong lpcr; 1403 1404 lpcr = env->spr[SPR_LPCR]; 1405 lpcr &= ~(LPCR_HR | LPCR_UPRT); 1406 ppc_store_lpcr(cpu, lpcr); 1407 } 1408 } 1409 1410 static bool spapr_get_pate(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu, 1411 target_ulong lpid, ppc_v3_pate_t *entry) 1412 { 1413 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1414 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 1415 1416 if (!spapr_cpu->in_nested) { 1417 assert(lpid == 0); 1418 1419 /* Copy PATE1:GR into PATE0:HR */ 1420 entry->dw0 = spapr->patb_entry & PATE0_HR; 1421 entry->dw1 = spapr->patb_entry; 1422 return true; 1423 } else { 1424 if (spapr_nested_api(spapr) == NESTED_API_KVM_HV) { 1425 return spapr_get_pate_nested_hv(spapr, cpu, lpid, entry); 1426 } else if (spapr_nested_api(spapr) == NESTED_API_PAPR) { 1427 return spapr_get_pate_nested_papr(spapr, cpu, lpid, entry); 1428 } else { 1429 g_assert_not_reached(); 1430 } 1431 } 1432 } 1433 1434 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1435 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1436 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1437 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1438 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1439 1440 /* 1441 * Get the fd to access the kernel htab, re-opening it if necessary 1442 */ 1443 static int get_htab_fd(SpaprMachineState *spapr) 1444 { 1445 Error *local_err = NULL; 1446 1447 if (spapr->htab_fd >= 0) { 1448 return spapr->htab_fd; 1449 } 1450 1451 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1452 if (spapr->htab_fd < 0) { 1453 error_report_err(local_err); 1454 } 1455 1456 return spapr->htab_fd; 1457 } 1458 1459 void close_htab_fd(SpaprMachineState *spapr) 1460 { 1461 if (spapr->htab_fd >= 0) { 1462 close(spapr->htab_fd); 1463 } 1464 spapr->htab_fd = -1; 1465 } 1466 1467 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1468 { 1469 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1470 1471 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1472 } 1473 1474 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1475 { 1476 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1477 1478 assert(kvm_enabled()); 1479 1480 if (!spapr->htab) { 1481 return 0; 1482 } 1483 1484 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1485 } 1486 1487 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1488 hwaddr ptex, int n) 1489 { 1490 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1491 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1492 1493 if (!spapr->htab) { 1494 /* 1495 * HTAB is controlled by KVM. Fetch into temporary buffer 1496 */ 1497 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1498 kvmppc_read_hptes(hptes, ptex, n); 1499 return hptes; 1500 } 1501 1502 /* 1503 * HTAB is controlled by QEMU. Just point to the internally 1504 * accessible PTEG. 1505 */ 1506 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1507 } 1508 1509 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1510 const ppc_hash_pte64_t *hptes, 1511 hwaddr ptex, int n) 1512 { 1513 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1514 1515 if (!spapr->htab) { 1516 g_free((void *)hptes); 1517 } 1518 1519 /* Nothing to do for qemu managed HPT */ 1520 } 1521 1522 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1523 uint64_t pte0, uint64_t pte1) 1524 { 1525 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1526 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1527 1528 if (!spapr->htab) { 1529 kvmppc_write_hpte(ptex, pte0, pte1); 1530 } else { 1531 if (pte0 & HPTE64_V_VALID) { 1532 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1533 /* 1534 * When setting valid, we write PTE1 first. This ensures 1535 * proper synchronization with the reading code in 1536 * ppc_hash64_pteg_search() 1537 */ 1538 smp_wmb(); 1539 stq_p(spapr->htab + offset, pte0); 1540 } else { 1541 stq_p(spapr->htab + offset, pte0); 1542 /* 1543 * When clearing it we set PTE0 first. This ensures proper 1544 * synchronization with the reading code in 1545 * ppc_hash64_pteg_search() 1546 */ 1547 smp_wmb(); 1548 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1549 } 1550 } 1551 } 1552 1553 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1554 uint64_t pte1) 1555 { 1556 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_C; 1557 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1558 1559 if (!spapr->htab) { 1560 /* There should always be a hash table when this is called */ 1561 error_report("spapr_hpte_set_c called with no hash table !"); 1562 return; 1563 } 1564 1565 /* The HW performs a non-atomic byte update */ 1566 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1567 } 1568 1569 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1570 uint64_t pte1) 1571 { 1572 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_R; 1573 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1574 1575 if (!spapr->htab) { 1576 /* There should always be a hash table when this is called */ 1577 error_report("spapr_hpte_set_r called with no hash table !"); 1578 return; 1579 } 1580 1581 /* The HW performs a non-atomic byte update */ 1582 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1583 } 1584 1585 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1586 { 1587 int shift; 1588 1589 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1590 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1591 * that's much more than is needed for Linux guests */ 1592 shift = ctz64(pow2ceil(ramsize)) - 7; 1593 shift = MAX(shift, 18); /* Minimum architected size */ 1594 shift = MIN(shift, 46); /* Maximum architected size */ 1595 return shift; 1596 } 1597 1598 void spapr_free_hpt(SpaprMachineState *spapr) 1599 { 1600 qemu_vfree(spapr->htab); 1601 spapr->htab = NULL; 1602 spapr->htab_shift = 0; 1603 close_htab_fd(spapr); 1604 } 1605 1606 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1607 { 1608 ERRP_GUARD(); 1609 long rc; 1610 1611 /* Clean up any HPT info from a previous boot */ 1612 spapr_free_hpt(spapr); 1613 1614 rc = kvmppc_reset_htab(shift); 1615 1616 if (rc == -EOPNOTSUPP) { 1617 error_setg(errp, "HPT not supported in nested guests"); 1618 return -EOPNOTSUPP; 1619 } 1620 1621 if (rc < 0) { 1622 /* kernel-side HPT needed, but couldn't allocate one */ 1623 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1624 shift); 1625 error_append_hint(errp, "Try smaller maxmem?\n"); 1626 return -errno; 1627 } else if (rc > 0) { 1628 /* kernel-side HPT allocated */ 1629 if (rc != shift) { 1630 error_setg(errp, 1631 "Requested order %d HPT, but kernel allocated order %ld", 1632 shift, rc); 1633 error_append_hint(errp, "Try smaller maxmem?\n"); 1634 return -ENOSPC; 1635 } 1636 1637 spapr->htab_shift = shift; 1638 spapr->htab = NULL; 1639 } else { 1640 /* kernel-side HPT not needed, allocate in userspace instead */ 1641 size_t size = 1ULL << shift; 1642 int i; 1643 1644 spapr->htab = qemu_memalign(size, size); 1645 memset(spapr->htab, 0, size); 1646 spapr->htab_shift = shift; 1647 1648 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1649 DIRTY_HPTE(HPTE(spapr->htab, i)); 1650 } 1651 } 1652 /* We're setting up a hash table, so that means we're not radix */ 1653 spapr->patb_entry = 0; 1654 spapr_init_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1655 return 0; 1656 } 1657 1658 void spapr_setup_hpt(SpaprMachineState *spapr) 1659 { 1660 int hpt_shift; 1661 1662 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1663 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1664 } else { 1665 uint64_t current_ram_size; 1666 1667 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1668 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1669 } 1670 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1671 1672 if (kvm_enabled()) { 1673 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1674 1675 /* Check our RMA fits in the possible VRMA */ 1676 if (vrma_limit < spapr->rma_size) { 1677 error_report("Unable to create %" HWADDR_PRIu 1678 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1679 spapr->rma_size / MiB, vrma_limit / MiB); 1680 exit(EXIT_FAILURE); 1681 } 1682 } 1683 } 1684 1685 void spapr_check_mmu_mode(bool guest_radix) 1686 { 1687 if (guest_radix) { 1688 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 1689 error_report("Guest requested unavailable MMU mode (radix)."); 1690 exit(EXIT_FAILURE); 1691 } 1692 } else { 1693 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 1694 && !kvmppc_has_cap_mmu_hash_v3()) { 1695 error_report("Guest requested unavailable MMU mode (hash)."); 1696 exit(EXIT_FAILURE); 1697 } 1698 } 1699 } 1700 1701 static void spapr_machine_reset(MachineState *machine, ShutdownCause reason) 1702 { 1703 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1704 PowerPCCPU *first_ppc_cpu; 1705 hwaddr fdt_addr; 1706 void *fdt; 1707 int rc; 1708 1709 if (reason != SHUTDOWN_CAUSE_SNAPSHOT_LOAD) { 1710 /* 1711 * Record-replay snapshot load must not consume random, this was 1712 * already replayed from initial machine reset. 1713 */ 1714 qemu_guest_getrandom_nofail(spapr->fdt_rng_seed, 32); 1715 } 1716 1717 pef_kvm_reset(machine->cgs, &error_fatal); 1718 spapr_caps_apply(spapr); 1719 spapr_nested_reset(spapr); 1720 1721 first_ppc_cpu = POWERPC_CPU(first_cpu); 1722 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1723 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1724 spapr->max_compat_pvr)) { 1725 /* 1726 * If using KVM with radix mode available, VCPUs can be started 1727 * without a HPT because KVM will start them in radix mode. 1728 * Set the GR bit in PATE so that we know there is no HPT. 1729 */ 1730 spapr->patb_entry = PATE1_GR; 1731 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1732 } else { 1733 spapr_setup_hpt(spapr); 1734 } 1735 1736 qemu_devices_reset(reason); 1737 1738 spapr_ovec_cleanup(spapr->ov5_cas); 1739 spapr->ov5_cas = spapr_ovec_new(); 1740 1741 ppc_init_compat_all(spapr->max_compat_pvr, &error_fatal); 1742 1743 /* 1744 * This is fixing some of the default configuration of the XIVE 1745 * devices. To be called after the reset of the machine devices. 1746 */ 1747 spapr_irq_reset(spapr, &error_fatal); 1748 1749 /* 1750 * There is no CAS under qtest. Simulate one to please the code that 1751 * depends on spapr->ov5_cas. This is especially needed to test device 1752 * unplug, so we do that before resetting the DRCs. 1753 */ 1754 if (qtest_enabled()) { 1755 spapr_ovec_cleanup(spapr->ov5_cas); 1756 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1757 } 1758 1759 spapr_nvdimm_finish_flushes(); 1760 1761 /* DRC reset may cause a device to be unplugged. This will cause troubles 1762 * if this device is used by another device (eg, a running vhost backend 1763 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1764 * situations, we reset DRCs after all devices have been reset. 1765 */ 1766 spapr_drc_reset_all(spapr); 1767 1768 spapr_clear_pending_events(spapr); 1769 1770 /* 1771 * We place the device tree just below either the top of the RMA, 1772 * or just below 2GB, whichever is lower, so that it can be 1773 * processed with 32-bit real mode code if necessary 1774 */ 1775 fdt_addr = MIN(spapr->rma_size, FDT_MAX_ADDR) - FDT_MAX_SIZE; 1776 1777 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1778 if (spapr->vof) { 1779 spapr_vof_reset(spapr, fdt, &error_fatal); 1780 /* 1781 * Do not pack the FDT as the client may change properties. 1782 * VOF client does not expect the FDT so we do not load it to the VM. 1783 */ 1784 } else { 1785 rc = fdt_pack(fdt); 1786 /* Should only fail if we've built a corrupted tree */ 1787 assert(rc == 0); 1788 1789 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 1790 0, fdt_addr, 0); 1791 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1792 } 1793 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1794 1795 g_free(spapr->fdt_blob); 1796 spapr->fdt_size = fdt_totalsize(fdt); 1797 spapr->fdt_initial_size = spapr->fdt_size; 1798 spapr->fdt_blob = fdt; 1799 1800 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ 1801 machine->fdt = fdt; 1802 1803 /* Set up the entry state */ 1804 first_ppc_cpu->env.gpr[5] = 0; 1805 1806 spapr->fwnmi_system_reset_addr = -1; 1807 spapr->fwnmi_machine_check_addr = -1; 1808 spapr->fwnmi_machine_check_interlock = -1; 1809 1810 /* Signal all vCPUs waiting on this condition */ 1811 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1812 1813 migrate_del_blocker(&spapr->fwnmi_migration_blocker); 1814 } 1815 1816 static void spapr_create_nvram(SpaprMachineState *spapr) 1817 { 1818 DeviceState *dev = qdev_new("spapr-nvram"); 1819 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1820 1821 if (dinfo) { 1822 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1823 &error_fatal); 1824 } 1825 1826 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1827 1828 spapr->nvram = (struct SpaprNvram *)dev; 1829 } 1830 1831 static void spapr_rtc_create(SpaprMachineState *spapr) 1832 { 1833 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1834 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1835 &error_fatal, NULL); 1836 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1837 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1838 "date"); 1839 } 1840 1841 /* Returns whether we want to use VGA or not */ 1842 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1843 { 1844 vga_interface_created = true; 1845 switch (vga_interface_type) { 1846 case VGA_NONE: 1847 return false; 1848 case VGA_DEVICE: 1849 return true; 1850 case VGA_STD: 1851 case VGA_VIRTIO: 1852 case VGA_CIRRUS: 1853 return pci_vga_init(pci_bus) != NULL; 1854 default: 1855 error_setg(errp, 1856 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1857 return false; 1858 } 1859 } 1860 1861 static int spapr_pre_load(void *opaque) 1862 { 1863 int rc; 1864 1865 rc = spapr_caps_pre_load(opaque); 1866 if (rc) { 1867 return rc; 1868 } 1869 1870 return 0; 1871 } 1872 1873 static int spapr_post_load(void *opaque, int version_id) 1874 { 1875 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1876 int err = 0; 1877 1878 err = spapr_caps_post_migration(spapr); 1879 if (err) { 1880 return err; 1881 } 1882 1883 /* 1884 * In earlier versions, there was no separate qdev for the PAPR 1885 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1886 * So when migrating from those versions, poke the incoming offset 1887 * value into the RTC device 1888 */ 1889 if (version_id < 3) { 1890 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1891 if (err) { 1892 return err; 1893 } 1894 } 1895 1896 if (kvm_enabled() && spapr->patb_entry) { 1897 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1898 bool radix = !!(spapr->patb_entry & PATE1_GR); 1899 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1900 1901 /* 1902 * Update LPCR:HR and UPRT as they may not be set properly in 1903 * the stream 1904 */ 1905 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1906 LPCR_HR | LPCR_UPRT); 1907 1908 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1909 if (err) { 1910 error_report("Process table config unsupported by the host"); 1911 return -EINVAL; 1912 } 1913 } 1914 1915 err = spapr_irq_post_load(spapr, version_id); 1916 if (err) { 1917 return err; 1918 } 1919 1920 return err; 1921 } 1922 1923 static int spapr_pre_save(void *opaque) 1924 { 1925 int rc; 1926 1927 rc = spapr_caps_pre_save(opaque); 1928 if (rc) { 1929 return rc; 1930 } 1931 1932 return 0; 1933 } 1934 1935 static bool version_before_3(void *opaque, int version_id) 1936 { 1937 return version_id < 3; 1938 } 1939 1940 static bool spapr_pending_events_needed(void *opaque) 1941 { 1942 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1943 return !QTAILQ_EMPTY(&spapr->pending_events); 1944 } 1945 1946 static const VMStateDescription vmstate_spapr_event_entry = { 1947 .name = "spapr_event_log_entry", 1948 .version_id = 1, 1949 .minimum_version_id = 1, 1950 .fields = (const VMStateField[]) { 1951 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1952 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1953 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1954 NULL, extended_length), 1955 VMSTATE_END_OF_LIST() 1956 }, 1957 }; 1958 1959 static const VMStateDescription vmstate_spapr_pending_events = { 1960 .name = "spapr_pending_events", 1961 .version_id = 1, 1962 .minimum_version_id = 1, 1963 .needed = spapr_pending_events_needed, 1964 .fields = (const VMStateField[]) { 1965 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1966 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1967 VMSTATE_END_OF_LIST() 1968 }, 1969 }; 1970 1971 static bool spapr_ov5_cas_needed(void *opaque) 1972 { 1973 SpaprMachineState *spapr = opaque; 1974 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1975 bool cas_needed; 1976 1977 /* Prior to the introduction of SpaprOptionVector, we had two option 1978 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1979 * Both of these options encode machine topology into the device-tree 1980 * in such a way that the now-booted OS should still be able to interact 1981 * appropriately with QEMU regardless of what options were actually 1982 * negotiatied on the source side. 1983 * 1984 * As such, we can avoid migrating the CAS-negotiated options if these 1985 * are the only options available on the current machine/platform. 1986 * Since these are the only options available for pseries-2.7 and 1987 * earlier, this allows us to maintain old->new/new->old migration 1988 * compatibility. 1989 * 1990 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1991 * via default pseries-2.8 machines and explicit command-line parameters. 1992 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1993 * of the actual CAS-negotiated values to continue working properly. For 1994 * example, availability of memory unplug depends on knowing whether 1995 * OV5_HP_EVT was negotiated via CAS. 1996 * 1997 * Thus, for any cases where the set of available CAS-negotiatable 1998 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1999 * include the CAS-negotiated options in the migration stream, unless 2000 * if they affect boot time behaviour only. 2001 */ 2002 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 2003 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 2004 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 2005 2006 /* We need extra information if we have any bits outside the mask 2007 * defined above */ 2008 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 2009 2010 spapr_ovec_cleanup(ov5_mask); 2011 2012 return cas_needed; 2013 } 2014 2015 static const VMStateDescription vmstate_spapr_ov5_cas = { 2016 .name = "spapr_option_vector_ov5_cas", 2017 .version_id = 1, 2018 .minimum_version_id = 1, 2019 .needed = spapr_ov5_cas_needed, 2020 .fields = (const VMStateField[]) { 2021 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 2022 vmstate_spapr_ovec, SpaprOptionVector), 2023 VMSTATE_END_OF_LIST() 2024 }, 2025 }; 2026 2027 static bool spapr_patb_entry_needed(void *opaque) 2028 { 2029 SpaprMachineState *spapr = opaque; 2030 2031 return !!spapr->patb_entry; 2032 } 2033 2034 static const VMStateDescription vmstate_spapr_patb_entry = { 2035 .name = "spapr_patb_entry", 2036 .version_id = 1, 2037 .minimum_version_id = 1, 2038 .needed = spapr_patb_entry_needed, 2039 .fields = (const VMStateField[]) { 2040 VMSTATE_UINT64(patb_entry, SpaprMachineState), 2041 VMSTATE_END_OF_LIST() 2042 }, 2043 }; 2044 2045 static bool spapr_irq_map_needed(void *opaque) 2046 { 2047 SpaprMachineState *spapr = opaque; 2048 2049 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 2050 } 2051 2052 static const VMStateDescription vmstate_spapr_irq_map = { 2053 .name = "spapr_irq_map", 2054 .version_id = 1, 2055 .minimum_version_id = 1, 2056 .needed = spapr_irq_map_needed, 2057 .fields = (const VMStateField[]) { 2058 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 2059 VMSTATE_END_OF_LIST() 2060 }, 2061 }; 2062 2063 static bool spapr_dtb_needed(void *opaque) 2064 { 2065 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 2066 2067 return smc->update_dt_enabled; 2068 } 2069 2070 static int spapr_dtb_pre_load(void *opaque) 2071 { 2072 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2073 2074 g_free(spapr->fdt_blob); 2075 spapr->fdt_blob = NULL; 2076 spapr->fdt_size = 0; 2077 2078 return 0; 2079 } 2080 2081 static const VMStateDescription vmstate_spapr_dtb = { 2082 .name = "spapr_dtb", 2083 .version_id = 1, 2084 .minimum_version_id = 1, 2085 .needed = spapr_dtb_needed, 2086 .pre_load = spapr_dtb_pre_load, 2087 .fields = (const VMStateField[]) { 2088 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 2089 VMSTATE_UINT32(fdt_size, SpaprMachineState), 2090 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 2091 fdt_size), 2092 VMSTATE_END_OF_LIST() 2093 }, 2094 }; 2095 2096 static bool spapr_fwnmi_needed(void *opaque) 2097 { 2098 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2099 2100 return spapr->fwnmi_machine_check_addr != -1; 2101 } 2102 2103 static int spapr_fwnmi_pre_save(void *opaque) 2104 { 2105 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2106 2107 /* 2108 * Check if machine check handling is in progress and print a 2109 * warning message. 2110 */ 2111 if (spapr->fwnmi_machine_check_interlock != -1) { 2112 warn_report("A machine check is being handled during migration. The" 2113 "handler may run and log hardware error on the destination"); 2114 } 2115 2116 return 0; 2117 } 2118 2119 static const VMStateDescription vmstate_spapr_fwnmi = { 2120 .name = "spapr_fwnmi", 2121 .version_id = 1, 2122 .minimum_version_id = 1, 2123 .needed = spapr_fwnmi_needed, 2124 .pre_save = spapr_fwnmi_pre_save, 2125 .fields = (const VMStateField[]) { 2126 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 2127 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 2128 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 2129 VMSTATE_END_OF_LIST() 2130 }, 2131 }; 2132 2133 static const VMStateDescription vmstate_spapr = { 2134 .name = "spapr", 2135 .version_id = 3, 2136 .minimum_version_id = 1, 2137 .pre_load = spapr_pre_load, 2138 .post_load = spapr_post_load, 2139 .pre_save = spapr_pre_save, 2140 .fields = (const VMStateField[]) { 2141 /* used to be @next_irq */ 2142 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2143 2144 /* RTC offset */ 2145 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2146 2147 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2148 VMSTATE_END_OF_LIST() 2149 }, 2150 .subsections = (const VMStateDescription * const []) { 2151 &vmstate_spapr_ov5_cas, 2152 &vmstate_spapr_patb_entry, 2153 &vmstate_spapr_pending_events, 2154 &vmstate_spapr_cap_htm, 2155 &vmstate_spapr_cap_vsx, 2156 &vmstate_spapr_cap_dfp, 2157 &vmstate_spapr_cap_cfpc, 2158 &vmstate_spapr_cap_sbbc, 2159 &vmstate_spapr_cap_ibs, 2160 &vmstate_spapr_cap_hpt_maxpagesize, 2161 &vmstate_spapr_irq_map, 2162 &vmstate_spapr_cap_nested_kvm_hv, 2163 &vmstate_spapr_dtb, 2164 &vmstate_spapr_cap_large_decr, 2165 &vmstate_spapr_cap_ccf_assist, 2166 &vmstate_spapr_cap_fwnmi, 2167 &vmstate_spapr_fwnmi, 2168 &vmstate_spapr_cap_rpt_invalidate, 2169 &vmstate_spapr_cap_nested_papr, 2170 NULL 2171 } 2172 }; 2173 2174 static int htab_save_setup(QEMUFile *f, void *opaque) 2175 { 2176 SpaprMachineState *spapr = opaque; 2177 2178 /* "Iteration" header */ 2179 if (!spapr->htab_shift) { 2180 qemu_put_be32(f, -1); 2181 } else { 2182 qemu_put_be32(f, spapr->htab_shift); 2183 } 2184 2185 if (spapr->htab) { 2186 spapr->htab_save_index = 0; 2187 spapr->htab_first_pass = true; 2188 } else { 2189 if (spapr->htab_shift) { 2190 assert(kvm_enabled()); 2191 } 2192 } 2193 2194 2195 return 0; 2196 } 2197 2198 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2199 int chunkstart, int n_valid, int n_invalid) 2200 { 2201 qemu_put_be32(f, chunkstart); 2202 qemu_put_be16(f, n_valid); 2203 qemu_put_be16(f, n_invalid); 2204 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2205 HASH_PTE_SIZE_64 * n_valid); 2206 } 2207 2208 static void htab_save_end_marker(QEMUFile *f) 2209 { 2210 qemu_put_be32(f, 0); 2211 qemu_put_be16(f, 0); 2212 qemu_put_be16(f, 0); 2213 } 2214 2215 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2216 int64_t max_ns) 2217 { 2218 bool has_timeout = max_ns != -1; 2219 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2220 int index = spapr->htab_save_index; 2221 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2222 2223 assert(spapr->htab_first_pass); 2224 2225 do { 2226 int chunkstart; 2227 2228 /* Consume invalid HPTEs */ 2229 while ((index < htabslots) 2230 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2231 CLEAN_HPTE(HPTE(spapr->htab, index)); 2232 index++; 2233 } 2234 2235 /* Consume valid HPTEs */ 2236 chunkstart = index; 2237 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2238 && HPTE_VALID(HPTE(spapr->htab, index))) { 2239 CLEAN_HPTE(HPTE(spapr->htab, index)); 2240 index++; 2241 } 2242 2243 if (index > chunkstart) { 2244 int n_valid = index - chunkstart; 2245 2246 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2247 2248 if (has_timeout && 2249 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2250 break; 2251 } 2252 } 2253 } while ((index < htabslots) && !migration_rate_exceeded(f)); 2254 2255 if (index >= htabslots) { 2256 assert(index == htabslots); 2257 index = 0; 2258 spapr->htab_first_pass = false; 2259 } 2260 spapr->htab_save_index = index; 2261 } 2262 2263 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2264 int64_t max_ns) 2265 { 2266 bool final = max_ns < 0; 2267 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2268 int examined = 0, sent = 0; 2269 int index = spapr->htab_save_index; 2270 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2271 2272 assert(!spapr->htab_first_pass); 2273 2274 do { 2275 int chunkstart, invalidstart; 2276 2277 /* Consume non-dirty HPTEs */ 2278 while ((index < htabslots) 2279 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2280 index++; 2281 examined++; 2282 } 2283 2284 chunkstart = index; 2285 /* Consume valid dirty HPTEs */ 2286 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2287 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2288 && HPTE_VALID(HPTE(spapr->htab, index))) { 2289 CLEAN_HPTE(HPTE(spapr->htab, index)); 2290 index++; 2291 examined++; 2292 } 2293 2294 invalidstart = index; 2295 /* Consume invalid dirty HPTEs */ 2296 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2297 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2298 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2299 CLEAN_HPTE(HPTE(spapr->htab, index)); 2300 index++; 2301 examined++; 2302 } 2303 2304 if (index > chunkstart) { 2305 int n_valid = invalidstart - chunkstart; 2306 int n_invalid = index - invalidstart; 2307 2308 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2309 sent += index - chunkstart; 2310 2311 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2312 break; 2313 } 2314 } 2315 2316 if (examined >= htabslots) { 2317 break; 2318 } 2319 2320 if (index >= htabslots) { 2321 assert(index == htabslots); 2322 index = 0; 2323 } 2324 } while ((examined < htabslots) && (!migration_rate_exceeded(f) || final)); 2325 2326 if (index >= htabslots) { 2327 assert(index == htabslots); 2328 index = 0; 2329 } 2330 2331 spapr->htab_save_index = index; 2332 2333 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2334 } 2335 2336 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2337 #define MAX_KVM_BUF_SIZE 2048 2338 2339 static int htab_save_iterate(QEMUFile *f, void *opaque) 2340 { 2341 SpaprMachineState *spapr = opaque; 2342 int fd; 2343 int rc = 0; 2344 2345 /* Iteration header */ 2346 if (!spapr->htab_shift) { 2347 qemu_put_be32(f, -1); 2348 return 1; 2349 } else { 2350 qemu_put_be32(f, 0); 2351 } 2352 2353 if (!spapr->htab) { 2354 assert(kvm_enabled()); 2355 2356 fd = get_htab_fd(spapr); 2357 if (fd < 0) { 2358 return fd; 2359 } 2360 2361 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2362 if (rc < 0) { 2363 return rc; 2364 } 2365 } else if (spapr->htab_first_pass) { 2366 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2367 } else { 2368 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2369 } 2370 2371 htab_save_end_marker(f); 2372 2373 return rc; 2374 } 2375 2376 static int htab_save_complete(QEMUFile *f, void *opaque) 2377 { 2378 SpaprMachineState *spapr = opaque; 2379 int fd; 2380 2381 /* Iteration header */ 2382 if (!spapr->htab_shift) { 2383 qemu_put_be32(f, -1); 2384 return 0; 2385 } else { 2386 qemu_put_be32(f, 0); 2387 } 2388 2389 if (!spapr->htab) { 2390 int rc; 2391 2392 assert(kvm_enabled()); 2393 2394 fd = get_htab_fd(spapr); 2395 if (fd < 0) { 2396 return fd; 2397 } 2398 2399 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2400 if (rc < 0) { 2401 return rc; 2402 } 2403 } else { 2404 if (spapr->htab_first_pass) { 2405 htab_save_first_pass(f, spapr, -1); 2406 } 2407 htab_save_later_pass(f, spapr, -1); 2408 } 2409 2410 /* End marker */ 2411 htab_save_end_marker(f); 2412 2413 return 0; 2414 } 2415 2416 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2417 { 2418 SpaprMachineState *spapr = opaque; 2419 uint32_t section_hdr; 2420 int fd = -1; 2421 Error *local_err = NULL; 2422 2423 if (version_id < 1 || version_id > 1) { 2424 error_report("htab_load() bad version"); 2425 return -EINVAL; 2426 } 2427 2428 section_hdr = qemu_get_be32(f); 2429 2430 if (section_hdr == -1) { 2431 spapr_free_hpt(spapr); 2432 return 0; 2433 } 2434 2435 if (section_hdr) { 2436 int ret; 2437 2438 /* First section gives the htab size */ 2439 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2440 if (ret < 0) { 2441 error_report_err(local_err); 2442 return ret; 2443 } 2444 return 0; 2445 } 2446 2447 if (!spapr->htab) { 2448 assert(kvm_enabled()); 2449 2450 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2451 if (fd < 0) { 2452 error_report_err(local_err); 2453 return fd; 2454 } 2455 } 2456 2457 while (true) { 2458 uint32_t index; 2459 uint16_t n_valid, n_invalid; 2460 2461 index = qemu_get_be32(f); 2462 n_valid = qemu_get_be16(f); 2463 n_invalid = qemu_get_be16(f); 2464 2465 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2466 /* End of Stream */ 2467 break; 2468 } 2469 2470 if ((index + n_valid + n_invalid) > 2471 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2472 /* Bad index in stream */ 2473 error_report( 2474 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2475 index, n_valid, n_invalid, spapr->htab_shift); 2476 return -EINVAL; 2477 } 2478 2479 if (spapr->htab) { 2480 if (n_valid) { 2481 qemu_get_buffer(f, HPTE(spapr->htab, index), 2482 HASH_PTE_SIZE_64 * n_valid); 2483 } 2484 if (n_invalid) { 2485 memset(HPTE(spapr->htab, index + n_valid), 0, 2486 HASH_PTE_SIZE_64 * n_invalid); 2487 } 2488 } else { 2489 int rc; 2490 2491 assert(fd >= 0); 2492 2493 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2494 &local_err); 2495 if (rc < 0) { 2496 error_report_err(local_err); 2497 return rc; 2498 } 2499 } 2500 } 2501 2502 if (!spapr->htab) { 2503 assert(fd >= 0); 2504 close(fd); 2505 } 2506 2507 return 0; 2508 } 2509 2510 static void htab_save_cleanup(void *opaque) 2511 { 2512 SpaprMachineState *spapr = opaque; 2513 2514 close_htab_fd(spapr); 2515 } 2516 2517 static SaveVMHandlers savevm_htab_handlers = { 2518 .save_setup = htab_save_setup, 2519 .save_live_iterate = htab_save_iterate, 2520 .save_live_complete_precopy = htab_save_complete, 2521 .save_cleanup = htab_save_cleanup, 2522 .load_state = htab_load, 2523 }; 2524 2525 static void spapr_boot_set(void *opaque, const char *boot_device, 2526 Error **errp) 2527 { 2528 SpaprMachineState *spapr = SPAPR_MACHINE(opaque); 2529 2530 g_free(spapr->boot_device); 2531 spapr->boot_device = g_strdup(boot_device); 2532 } 2533 2534 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2535 { 2536 MachineState *machine = MACHINE(spapr); 2537 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2538 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2539 int i; 2540 2541 g_assert(!nr_lmbs || machine->device_memory); 2542 for (i = 0; i < nr_lmbs; i++) { 2543 uint64_t addr; 2544 2545 addr = i * lmb_size + machine->device_memory->base; 2546 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2547 addr / lmb_size); 2548 } 2549 } 2550 2551 /* 2552 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2553 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2554 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2555 */ 2556 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2557 { 2558 int i; 2559 2560 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2561 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2562 " is not aligned to %" PRIu64 " MiB", 2563 machine->ram_size, 2564 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2565 return; 2566 } 2567 2568 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2569 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2570 " is not aligned to %" PRIu64 " MiB", 2571 machine->ram_size, 2572 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2573 return; 2574 } 2575 2576 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2577 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2578 error_setg(errp, 2579 "Node %d memory size 0x%" PRIx64 2580 " is not aligned to %" PRIu64 " MiB", 2581 i, machine->numa_state->nodes[i].node_mem, 2582 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2583 return; 2584 } 2585 } 2586 } 2587 2588 /* find cpu slot in machine->possible_cpus by core_id */ 2589 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2590 { 2591 int index = id / ms->smp.threads; 2592 2593 if (index >= ms->possible_cpus->len) { 2594 return NULL; 2595 } 2596 if (idx) { 2597 *idx = index; 2598 } 2599 return &ms->possible_cpus->cpus[index]; 2600 } 2601 2602 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2603 { 2604 MachineState *ms = MACHINE(spapr); 2605 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2606 Error *local_err = NULL; 2607 bool vsmt_user = !!spapr->vsmt; 2608 int kvm_smt = kvmppc_smt_threads(); 2609 int ret; 2610 unsigned int smp_threads = ms->smp.threads; 2611 2612 if (tcg_enabled()) { 2613 if (smp_threads > 1 && 2614 !ppc_type_check_compat(ms->cpu_type, CPU_POWERPC_LOGICAL_2_07, 0, 2615 spapr->max_compat_pvr)) { 2616 error_setg(errp, "TCG only supports SMT on POWER8 or newer CPUs"); 2617 return; 2618 } 2619 2620 if (smp_threads > 8) { 2621 error_setg(errp, "TCG cannot support more than 8 threads/core " 2622 "on a pseries machine"); 2623 return; 2624 } 2625 } 2626 if (!is_power_of_2(smp_threads)) { 2627 error_setg(errp, "Cannot support %d threads/core on a pseries " 2628 "machine because it must be a power of 2", smp_threads); 2629 return; 2630 } 2631 2632 /* Determine the VSMT mode to use: */ 2633 if (vsmt_user) { 2634 if (spapr->vsmt < smp_threads) { 2635 error_setg(errp, "Cannot support VSMT mode %d" 2636 " because it must be >= threads/core (%d)", 2637 spapr->vsmt, smp_threads); 2638 return; 2639 } 2640 /* In this case, spapr->vsmt has been set by the command line */ 2641 } else if (!smc->smp_threads_vsmt) { 2642 /* 2643 * Default VSMT value is tricky, because we need it to be as 2644 * consistent as possible (for migration), but this requires 2645 * changing it for at least some existing cases. We pick 8 as 2646 * the value that we'd get with KVM on POWER8, the 2647 * overwhelmingly common case in production systems. 2648 */ 2649 spapr->vsmt = MAX(8, smp_threads); 2650 } else { 2651 spapr->vsmt = smp_threads; 2652 } 2653 2654 /* KVM: If necessary, set the SMT mode: */ 2655 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2656 ret = kvmppc_set_smt_threads(spapr->vsmt); 2657 if (ret) { 2658 /* Looks like KVM isn't able to change VSMT mode */ 2659 error_setg(&local_err, 2660 "Failed to set KVM's VSMT mode to %d (errno %d)", 2661 spapr->vsmt, ret); 2662 /* We can live with that if the default one is big enough 2663 * for the number of threads, and a submultiple of the one 2664 * we want. In this case we'll waste some vcpu ids, but 2665 * behaviour will be correct */ 2666 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2667 warn_report_err(local_err); 2668 } else { 2669 if (!vsmt_user) { 2670 error_append_hint(&local_err, 2671 "On PPC, a VM with %d threads/core" 2672 " on a host with %d threads/core" 2673 " requires the use of VSMT mode %d.\n", 2674 smp_threads, kvm_smt, spapr->vsmt); 2675 } 2676 kvmppc_error_append_smt_possible_hint(&local_err); 2677 error_propagate(errp, local_err); 2678 } 2679 } 2680 } 2681 /* else TCG: nothing to do currently */ 2682 } 2683 2684 static void spapr_init_cpus(SpaprMachineState *spapr) 2685 { 2686 MachineState *machine = MACHINE(spapr); 2687 MachineClass *mc = MACHINE_GET_CLASS(machine); 2688 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2689 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2690 const CPUArchIdList *possible_cpus; 2691 unsigned int smp_cpus = machine->smp.cpus; 2692 unsigned int smp_threads = machine->smp.threads; 2693 unsigned int max_cpus = machine->smp.max_cpus; 2694 int boot_cores_nr = smp_cpus / smp_threads; 2695 int i; 2696 2697 possible_cpus = mc->possible_cpu_arch_ids(machine); 2698 if (mc->has_hotpluggable_cpus) { 2699 if (smp_cpus % smp_threads) { 2700 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2701 smp_cpus, smp_threads); 2702 exit(1); 2703 } 2704 if (max_cpus % smp_threads) { 2705 error_report("max_cpus (%u) must be multiple of threads (%u)", 2706 max_cpus, smp_threads); 2707 exit(1); 2708 } 2709 } else { 2710 if (max_cpus != smp_cpus) { 2711 error_report("This machine version does not support CPU hotplug"); 2712 exit(1); 2713 } 2714 boot_cores_nr = possible_cpus->len; 2715 } 2716 2717 if (smc->pre_2_10_has_unused_icps) { 2718 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2719 /* Dummy entries get deregistered when real ICPState objects 2720 * are registered during CPU core hotplug. 2721 */ 2722 pre_2_10_vmstate_register_dummy_icp(i); 2723 } 2724 } 2725 2726 for (i = 0; i < possible_cpus->len; i++) { 2727 int core_id = i * smp_threads; 2728 2729 if (mc->has_hotpluggable_cpus) { 2730 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2731 spapr_vcpu_id(spapr, core_id)); 2732 } 2733 2734 if (i < boot_cores_nr) { 2735 Object *core = object_new(type); 2736 int nr_threads = smp_threads; 2737 2738 /* Handle the partially filled core for older machine types */ 2739 if ((i + 1) * smp_threads >= smp_cpus) { 2740 nr_threads = smp_cpus - i * smp_threads; 2741 } 2742 2743 object_property_set_int(core, "nr-threads", nr_threads, 2744 &error_fatal); 2745 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2746 &error_fatal); 2747 qdev_realize(DEVICE(core), NULL, &error_fatal); 2748 2749 object_unref(core); 2750 } 2751 } 2752 } 2753 2754 static PCIHostState *spapr_create_default_phb(void) 2755 { 2756 DeviceState *dev; 2757 2758 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2759 qdev_prop_set_uint32(dev, "index", 0); 2760 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2761 2762 return PCI_HOST_BRIDGE(dev); 2763 } 2764 2765 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2766 { 2767 MachineState *machine = MACHINE(spapr); 2768 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2769 hwaddr rma_size = machine->ram_size; 2770 hwaddr node0_size = spapr_node0_size(machine); 2771 2772 /* RMA has to fit in the first NUMA node */ 2773 rma_size = MIN(rma_size, node0_size); 2774 2775 /* 2776 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2777 * never exceed that 2778 */ 2779 rma_size = MIN(rma_size, 1 * TiB); 2780 2781 /* 2782 * Clamp the RMA size based on machine type. This is for 2783 * migration compatibility with older qemu versions, which limited 2784 * the RMA size for complicated and mostly bad reasons. 2785 */ 2786 if (smc->rma_limit) { 2787 rma_size = MIN(rma_size, smc->rma_limit); 2788 } 2789 2790 if (rma_size < MIN_RMA_SLOF) { 2791 error_setg(errp, 2792 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2793 "ldMiB guest RMA (Real Mode Area memory)", 2794 MIN_RMA_SLOF / MiB); 2795 return 0; 2796 } 2797 2798 return rma_size; 2799 } 2800 2801 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2802 { 2803 MachineState *machine = MACHINE(spapr); 2804 int i; 2805 2806 for (i = 0; i < machine->ram_slots; i++) { 2807 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2808 } 2809 } 2810 2811 /* pSeries LPAR / sPAPR hardware init */ 2812 static void spapr_machine_init(MachineState *machine) 2813 { 2814 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2815 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2816 MachineClass *mc = MACHINE_GET_CLASS(machine); 2817 const char *bios_default = spapr->vof ? FW_FILE_NAME_VOF : FW_FILE_NAME; 2818 const char *bios_name = machine->firmware ?: bios_default; 2819 g_autofree char *filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2820 const char *kernel_filename = machine->kernel_filename; 2821 const char *initrd_filename = machine->initrd_filename; 2822 PCIHostState *phb; 2823 bool has_vga; 2824 int i; 2825 MemoryRegion *sysmem = get_system_memory(); 2826 long load_limit, fw_size; 2827 Error *resize_hpt_err = NULL; 2828 NICInfo *nd; 2829 2830 if (!filename) { 2831 error_report("Could not find LPAR firmware '%s'", bios_name); 2832 exit(1); 2833 } 2834 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2835 if (fw_size <= 0) { 2836 error_report("Could not load LPAR firmware '%s'", filename); 2837 exit(1); 2838 } 2839 2840 /* 2841 * if Secure VM (PEF) support is configured, then initialize it 2842 */ 2843 pef_kvm_init(machine->cgs, &error_fatal); 2844 2845 msi_nonbroken = true; 2846 2847 QLIST_INIT(&spapr->phbs); 2848 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2849 2850 /* Determine capabilities to run with */ 2851 spapr_caps_init(spapr); 2852 2853 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2854 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2855 /* 2856 * If the user explicitly requested a mode we should either 2857 * supply it, or fail completely (which we do below). But if 2858 * it's not set explicitly, we reset our mode to something 2859 * that works 2860 */ 2861 if (resize_hpt_err) { 2862 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2863 error_free(resize_hpt_err); 2864 resize_hpt_err = NULL; 2865 } else { 2866 spapr->resize_hpt = smc->resize_hpt_default; 2867 } 2868 } 2869 2870 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2871 2872 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2873 /* 2874 * User requested HPT resize, but this host can't supply it. Bail out 2875 */ 2876 error_report_err(resize_hpt_err); 2877 exit(1); 2878 } 2879 error_free(resize_hpt_err); 2880 2881 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2882 2883 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2884 load_limit = MIN(spapr->rma_size, FDT_MAX_ADDR) - FW_OVERHEAD; 2885 2886 /* 2887 * VSMT must be set in order to be able to compute VCPU ids, ie to 2888 * call spapr_max_server_number() or spapr_vcpu_id(). 2889 */ 2890 spapr_set_vsmt_mode(spapr, &error_fatal); 2891 2892 /* Set up Interrupt Controller before we create the VCPUs */ 2893 spapr_irq_init(spapr, &error_fatal); 2894 2895 /* Set up containers for ibm,client-architecture-support negotiated options 2896 */ 2897 spapr->ov5 = spapr_ovec_new(); 2898 spapr->ov5_cas = spapr_ovec_new(); 2899 2900 if (smc->dr_lmb_enabled) { 2901 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2902 spapr_validate_node_memory(machine, &error_fatal); 2903 } 2904 2905 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2906 2907 /* Do not advertise FORM2 NUMA support for pseries-6.1 and older */ 2908 if (!smc->pre_6_2_numa_affinity) { 2909 spapr_ovec_set(spapr->ov5, OV5_FORM2_AFFINITY); 2910 } 2911 2912 /* advertise support for dedicated HP event source to guests */ 2913 if (spapr->use_hotplug_event_source) { 2914 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2915 } 2916 2917 /* advertise support for HPT resizing */ 2918 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2919 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2920 } 2921 2922 /* advertise support for ibm,dyamic-memory-v2 */ 2923 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2924 2925 /* advertise XIVE on POWER9 machines */ 2926 if (spapr->irq->xive) { 2927 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2928 } 2929 2930 /* init CPUs */ 2931 spapr_init_cpus(spapr); 2932 2933 /* Init numa_assoc_array */ 2934 spapr_numa_associativity_init(spapr, machine); 2935 2936 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2937 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2938 spapr->max_compat_pvr)) { 2939 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2940 /* KVM and TCG always allow GTSE with radix... */ 2941 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2942 } 2943 /* ... but not with hash (currently). */ 2944 2945 if (kvm_enabled()) { 2946 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2947 kvmppc_enable_logical_ci_hcalls(); 2948 kvmppc_enable_set_mode_hcall(); 2949 2950 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2951 kvmppc_enable_clear_ref_mod_hcalls(); 2952 2953 /* Enable H_PAGE_INIT */ 2954 kvmppc_enable_h_page_init(); 2955 } 2956 2957 /* map RAM */ 2958 memory_region_add_subregion(sysmem, 0, machine->ram); 2959 2960 /* initialize hotplug memory address space */ 2961 if (machine->ram_size < machine->maxram_size) { 2962 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2963 hwaddr device_mem_base; 2964 2965 /* 2966 * Limit the number of hotpluggable memory slots to half the number 2967 * slots that KVM supports, leaving the other half for PCI and other 2968 * devices. However ensure that number of slots doesn't drop below 32. 2969 */ 2970 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2971 SPAPR_MAX_RAM_SLOTS; 2972 2973 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2974 max_memslots = SPAPR_MAX_RAM_SLOTS; 2975 } 2976 if (machine->ram_slots > max_memslots) { 2977 error_report("Specified number of memory slots %" 2978 PRIu64" exceeds max supported %d", 2979 machine->ram_slots, max_memslots); 2980 exit(1); 2981 } 2982 2983 device_mem_base = ROUND_UP(machine->ram_size, SPAPR_DEVICE_MEM_ALIGN); 2984 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 2985 } 2986 2987 if (smc->dr_lmb_enabled) { 2988 spapr_create_lmb_dr_connectors(spapr); 2989 } 2990 2991 if (mc->nvdimm_supported) { 2992 spapr_create_nvdimm_dr_connectors(spapr); 2993 } 2994 2995 /* Set up RTAS event infrastructure */ 2996 spapr_events_init(spapr); 2997 2998 /* Set up the RTC RTAS interfaces */ 2999 spapr_rtc_create(spapr); 3000 3001 /* Set up VIO bus */ 3002 spapr->vio_bus = spapr_vio_bus_init(); 3003 3004 for (i = 0; serial_hd(i); i++) { 3005 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 3006 } 3007 3008 /* We always have at least the nvram device on VIO */ 3009 spapr_create_nvram(spapr); 3010 3011 /* 3012 * Setup hotplug / dynamic-reconfiguration connectors. top-level 3013 * connectors (described in root DT node's "ibm,drc-types" property) 3014 * are pre-initialized here. additional child connectors (such as 3015 * connectors for a PHBs PCI slots) are added as needed during their 3016 * parent's realization. 3017 */ 3018 if (smc->dr_phb_enabled) { 3019 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 3020 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 3021 } 3022 } 3023 3024 /* Set up PCI */ 3025 spapr_pci_rtas_init(); 3026 3027 phb = spapr_create_default_phb(); 3028 3029 while ((nd = qemu_find_nic_info("spapr-vlan", true, "ibmveth"))) { 3030 spapr_vlan_create(spapr->vio_bus, nd); 3031 } 3032 3033 pci_init_nic_devices(phb->bus, NULL); 3034 3035 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 3036 spapr_vscsi_create(spapr->vio_bus); 3037 } 3038 3039 /* Graphics */ 3040 has_vga = spapr_vga_init(phb->bus, &error_fatal); 3041 if (has_vga) { 3042 spapr->want_stdout_path = !machine->enable_graphics; 3043 machine->usb |= defaults_enabled() && !machine->usb_disabled; 3044 } else { 3045 spapr->want_stdout_path = true; 3046 } 3047 3048 if (machine->usb) { 3049 if (smc->use_ohci_by_default) { 3050 pci_create_simple(phb->bus, -1, "pci-ohci"); 3051 } else { 3052 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 3053 } 3054 3055 if (has_vga) { 3056 USBBus *usb_bus; 3057 3058 usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS, 3059 &error_abort)); 3060 usb_create_simple(usb_bus, "usb-kbd"); 3061 usb_create_simple(usb_bus, "usb-mouse"); 3062 } 3063 } 3064 3065 if (kernel_filename) { 3066 uint64_t loaded_addr = 0; 3067 3068 spapr->kernel_size = load_elf(kernel_filename, NULL, 3069 translate_kernel_address, spapr, 3070 NULL, &loaded_addr, NULL, NULL, 1, 3071 PPC_ELF_MACHINE, 0, 0); 3072 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 3073 spapr->kernel_size = load_elf(kernel_filename, NULL, 3074 translate_kernel_address, spapr, 3075 NULL, &loaded_addr, NULL, NULL, 0, 3076 PPC_ELF_MACHINE, 0, 0); 3077 spapr->kernel_le = spapr->kernel_size > 0; 3078 } 3079 if (spapr->kernel_size < 0) { 3080 error_report("error loading %s: %s", kernel_filename, 3081 load_elf_strerror(spapr->kernel_size)); 3082 exit(1); 3083 } 3084 3085 if (spapr->kernel_addr != loaded_addr) { 3086 warn_report("spapr: kernel_addr changed from 0x%"PRIx64 3087 " to 0x%"PRIx64, 3088 spapr->kernel_addr, loaded_addr); 3089 spapr->kernel_addr = loaded_addr; 3090 } 3091 3092 /* load initrd */ 3093 if (initrd_filename) { 3094 /* Try to locate the initrd in the gap between the kernel 3095 * and the firmware. Add a bit of space just in case 3096 */ 3097 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 3098 + 0x1ffff) & ~0xffff; 3099 spapr->initrd_size = load_image_targphys(initrd_filename, 3100 spapr->initrd_base, 3101 load_limit 3102 - spapr->initrd_base); 3103 if (spapr->initrd_size < 0) { 3104 error_report("could not load initial ram disk '%s'", 3105 initrd_filename); 3106 exit(1); 3107 } 3108 } 3109 } 3110 3111 /* FIXME: Should register things through the MachineState's qdev 3112 * interface, this is a legacy from the sPAPREnvironment structure 3113 * which predated MachineState but had a similar function */ 3114 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3115 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3116 &savevm_htab_handlers, spapr); 3117 3118 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 3119 3120 qemu_register_boot_set(spapr_boot_set, spapr); 3121 3122 /* 3123 * Nothing needs to be done to resume a suspended guest because 3124 * suspending does not change the machine state, so no need for 3125 * a ->wakeup method. 3126 */ 3127 qemu_register_wakeup_support(); 3128 3129 if (kvm_enabled()) { 3130 /* to stop and start vmclock */ 3131 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3132 &spapr->tb); 3133 3134 kvmppc_spapr_enable_inkernel_multitce(); 3135 } 3136 3137 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3138 if (spapr->vof) { 3139 spapr->vof->fw_size = fw_size; /* for claim() on itself */ 3140 spapr_register_hypercall(KVMPPC_H_VOF_CLIENT, spapr_h_vof_client); 3141 } 3142 3143 spapr_watchdog_init(spapr); 3144 } 3145 3146 #define DEFAULT_KVM_TYPE "auto" 3147 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3148 { 3149 /* 3150 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to 3151 * accommodate the 'HV' and 'PV' formats that exists in the 3152 * wild. The 'auto' mode is being introduced already as 3153 * lower-case, thus we don't need to bother checking for 3154 * "AUTO". 3155 */ 3156 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) { 3157 return 0; 3158 } 3159 3160 if (!g_ascii_strcasecmp(vm_type, "hv")) { 3161 return 1; 3162 } 3163 3164 if (!g_ascii_strcasecmp(vm_type, "pr")) { 3165 return 2; 3166 } 3167 3168 error_report("Unknown kvm-type specified '%s'", vm_type); 3169 return -1; 3170 } 3171 3172 /* 3173 * Implementation of an interface to adjust firmware path 3174 * for the bootindex property handling. 3175 */ 3176 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3177 DeviceState *dev) 3178 { 3179 #define CAST(type, obj, name) \ 3180 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3181 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3182 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3183 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3184 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3185 3186 if (d && bus) { 3187 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3188 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3189 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3190 3191 if (spapr) { 3192 /* 3193 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3194 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3195 * 0x8000 | (target << 8) | (bus << 5) | lun 3196 * (see the "Logical unit addressing format" table in SAM5) 3197 */ 3198 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3199 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3200 (uint64_t)id << 48); 3201 } else if (virtio) { 3202 /* 3203 * We use SRP luns of the form 01000000 | (target << 8) | lun 3204 * in the top 32 bits of the 64-bit LUN 3205 * Note: the quote above is from SLOF and it is wrong, 3206 * the actual binding is: 3207 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3208 */ 3209 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3210 if (d->lun >= 256) { 3211 /* Use the LUN "flat space addressing method" */ 3212 id |= 0x4000; 3213 } 3214 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3215 (uint64_t)id << 32); 3216 } else if (usb) { 3217 /* 3218 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3219 * in the top 32 bits of the 64-bit LUN 3220 */ 3221 unsigned usb_port = atoi(usb->port->path); 3222 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3223 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3224 (uint64_t)id << 32); 3225 } 3226 } 3227 3228 /* 3229 * SLOF probes the USB devices, and if it recognizes that the device is a 3230 * storage device, it changes its name to "storage" instead of "usb-host", 3231 * and additionally adds a child node for the SCSI LUN, so the correct 3232 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3233 */ 3234 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3235 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3236 if (usb_device_is_scsi_storage(usbdev)) { 3237 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3238 } 3239 } 3240 3241 if (phb) { 3242 /* Replace "pci" with "pci@800000020000000" */ 3243 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3244 } 3245 3246 if (vsc) { 3247 /* Same logic as virtio above */ 3248 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3249 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3250 } 3251 3252 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3253 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3254 PCIDevice *pdev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3255 return g_strdup_printf("pci@%x", PCI_SLOT(pdev->devfn)); 3256 } 3257 3258 if (pcidev) { 3259 return spapr_pci_fw_dev_name(pcidev); 3260 } 3261 3262 return NULL; 3263 } 3264 3265 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3266 { 3267 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3268 3269 return g_strdup(spapr->kvm_type); 3270 } 3271 3272 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3273 { 3274 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3275 3276 g_free(spapr->kvm_type); 3277 spapr->kvm_type = g_strdup(value); 3278 } 3279 3280 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3281 { 3282 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3283 3284 return spapr->use_hotplug_event_source; 3285 } 3286 3287 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3288 Error **errp) 3289 { 3290 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3291 3292 spapr->use_hotplug_event_source = value; 3293 } 3294 3295 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3296 { 3297 return true; 3298 } 3299 3300 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3301 { 3302 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3303 3304 switch (spapr->resize_hpt) { 3305 case SPAPR_RESIZE_HPT_DEFAULT: 3306 return g_strdup("default"); 3307 case SPAPR_RESIZE_HPT_DISABLED: 3308 return g_strdup("disabled"); 3309 case SPAPR_RESIZE_HPT_ENABLED: 3310 return g_strdup("enabled"); 3311 case SPAPR_RESIZE_HPT_REQUIRED: 3312 return g_strdup("required"); 3313 } 3314 g_assert_not_reached(); 3315 } 3316 3317 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3318 { 3319 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3320 3321 if (strcmp(value, "default") == 0) { 3322 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3323 } else if (strcmp(value, "disabled") == 0) { 3324 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3325 } else if (strcmp(value, "enabled") == 0) { 3326 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3327 } else if (strcmp(value, "required") == 0) { 3328 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3329 } else { 3330 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3331 } 3332 } 3333 3334 static bool spapr_get_vof(Object *obj, Error **errp) 3335 { 3336 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3337 3338 return spapr->vof != NULL; 3339 } 3340 3341 static void spapr_set_vof(Object *obj, bool value, Error **errp) 3342 { 3343 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3344 3345 if (spapr->vof) { 3346 vof_cleanup(spapr->vof); 3347 g_free(spapr->vof); 3348 spapr->vof = NULL; 3349 } 3350 if (!value) { 3351 return; 3352 } 3353 spapr->vof = g_malloc0(sizeof(*spapr->vof)); 3354 } 3355 3356 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3357 { 3358 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3359 3360 if (spapr->irq == &spapr_irq_xics_legacy) { 3361 return g_strdup("legacy"); 3362 } else if (spapr->irq == &spapr_irq_xics) { 3363 return g_strdup("xics"); 3364 } else if (spapr->irq == &spapr_irq_xive) { 3365 return g_strdup("xive"); 3366 } else if (spapr->irq == &spapr_irq_dual) { 3367 return g_strdup("dual"); 3368 } 3369 g_assert_not_reached(); 3370 } 3371 3372 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3373 { 3374 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3375 3376 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3377 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3378 return; 3379 } 3380 3381 /* The legacy IRQ backend can not be set */ 3382 if (strcmp(value, "xics") == 0) { 3383 spapr->irq = &spapr_irq_xics; 3384 } else if (strcmp(value, "xive") == 0) { 3385 spapr->irq = &spapr_irq_xive; 3386 } else if (strcmp(value, "dual") == 0) { 3387 spapr->irq = &spapr_irq_dual; 3388 } else { 3389 error_setg(errp, "Bad value for \"ic-mode\" property"); 3390 } 3391 } 3392 3393 static char *spapr_get_host_model(Object *obj, Error **errp) 3394 { 3395 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3396 3397 return g_strdup(spapr->host_model); 3398 } 3399 3400 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3401 { 3402 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3403 3404 g_free(spapr->host_model); 3405 spapr->host_model = g_strdup(value); 3406 } 3407 3408 static char *spapr_get_host_serial(Object *obj, Error **errp) 3409 { 3410 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3411 3412 return g_strdup(spapr->host_serial); 3413 } 3414 3415 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3416 { 3417 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3418 3419 g_free(spapr->host_serial); 3420 spapr->host_serial = g_strdup(value); 3421 } 3422 3423 static void spapr_instance_init(Object *obj) 3424 { 3425 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3426 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3427 MachineState *ms = MACHINE(spapr); 3428 MachineClass *mc = MACHINE_GET_CLASS(ms); 3429 3430 /* 3431 * NVDIMM support went live in 5.1 without considering that, in 3432 * other archs, the user needs to enable NVDIMM support with the 3433 * 'nvdimm' machine option and the default behavior is NVDIMM 3434 * support disabled. It is too late to roll back to the standard 3435 * behavior without breaking 5.1 guests. 3436 */ 3437 if (mc->nvdimm_supported) { 3438 ms->nvdimms_state->is_enabled = true; 3439 } 3440 3441 spapr->htab_fd = -1; 3442 spapr->use_hotplug_event_source = true; 3443 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE); 3444 object_property_add_str(obj, "kvm-type", 3445 spapr_get_kvm_type, spapr_set_kvm_type); 3446 object_property_set_description(obj, "kvm-type", 3447 "Specifies the KVM virtualization mode (auto," 3448 " hv, pr). Defaults to 'auto'. This mode will use" 3449 " any available KVM module loaded in the host," 3450 " where kvm_hv takes precedence if both kvm_hv and" 3451 " kvm_pr are loaded."); 3452 object_property_add_bool(obj, "modern-hotplug-events", 3453 spapr_get_modern_hotplug_events, 3454 spapr_set_modern_hotplug_events); 3455 object_property_set_description(obj, "modern-hotplug-events", 3456 "Use dedicated hotplug event mechanism in" 3457 " place of standard EPOW events when possible" 3458 " (required for memory hot-unplug support)"); 3459 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3460 "Maximum permitted CPU compatibility mode"); 3461 3462 object_property_add_str(obj, "resize-hpt", 3463 spapr_get_resize_hpt, spapr_set_resize_hpt); 3464 object_property_set_description(obj, "resize-hpt", 3465 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3466 object_property_add_uint32_ptr(obj, "vsmt", 3467 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3468 object_property_set_description(obj, "vsmt", 3469 "Virtual SMT: KVM behaves as if this were" 3470 " the host's SMT mode"); 3471 3472 object_property_add_bool(obj, "vfio-no-msix-emulation", 3473 spapr_get_msix_emulation, NULL); 3474 3475 object_property_add_uint64_ptr(obj, "kernel-addr", 3476 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3477 object_property_set_description(obj, "kernel-addr", 3478 stringify(KERNEL_LOAD_ADDR) 3479 " for -kernel is the default"); 3480 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3481 3482 object_property_add_bool(obj, "x-vof", spapr_get_vof, spapr_set_vof); 3483 object_property_set_description(obj, "x-vof", 3484 "Enable Virtual Open Firmware (experimental)"); 3485 3486 /* The machine class defines the default interrupt controller mode */ 3487 spapr->irq = smc->irq; 3488 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3489 spapr_set_ic_mode); 3490 object_property_set_description(obj, "ic-mode", 3491 "Specifies the interrupt controller mode (xics, xive, dual)"); 3492 3493 object_property_add_str(obj, "host-model", 3494 spapr_get_host_model, spapr_set_host_model); 3495 object_property_set_description(obj, "host-model", 3496 "Host model to advertise in guest device tree"); 3497 object_property_add_str(obj, "host-serial", 3498 spapr_get_host_serial, spapr_set_host_serial); 3499 object_property_set_description(obj, "host-serial", 3500 "Host serial number to advertise in guest device tree"); 3501 } 3502 3503 static void spapr_machine_finalizefn(Object *obj) 3504 { 3505 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3506 3507 g_free(spapr->kvm_type); 3508 } 3509 3510 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3511 { 3512 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3513 CPUPPCState *env = cpu_env(cs); 3514 3515 cpu_synchronize_state(cs); 3516 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3517 if (spapr->fwnmi_system_reset_addr != -1) { 3518 uint64_t rtas_addr, addr; 3519 3520 /* get rtas addr from fdt */ 3521 rtas_addr = spapr_get_rtas_addr(); 3522 if (!rtas_addr) { 3523 qemu_system_guest_panicked(NULL); 3524 return; 3525 } 3526 3527 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3528 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3529 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3530 env->gpr[3] = addr; 3531 } 3532 ppc_cpu_do_system_reset(cs); 3533 if (spapr->fwnmi_system_reset_addr != -1) { 3534 env->nip = spapr->fwnmi_system_reset_addr; 3535 } 3536 } 3537 3538 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3539 { 3540 CPUState *cs; 3541 3542 CPU_FOREACH(cs) { 3543 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3544 } 3545 } 3546 3547 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3548 void *fdt, int *fdt_start_offset, Error **errp) 3549 { 3550 uint64_t addr; 3551 uint32_t node; 3552 3553 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3554 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3555 &error_abort); 3556 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3557 SPAPR_MEMORY_BLOCK_SIZE); 3558 return 0; 3559 } 3560 3561 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3562 bool dedicated_hp_event_source) 3563 { 3564 SpaprDrc *drc; 3565 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3566 int i; 3567 uint64_t addr = addr_start; 3568 bool hotplugged = spapr_drc_hotplugged(dev); 3569 3570 for (i = 0; i < nr_lmbs; i++) { 3571 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3572 addr / SPAPR_MEMORY_BLOCK_SIZE); 3573 g_assert(drc); 3574 3575 /* 3576 * memory_device_get_free_addr() provided a range of free addresses 3577 * that doesn't overlap with any existing mapping at pre-plug. The 3578 * corresponding LMB DRCs are thus assumed to be all attachable. 3579 */ 3580 spapr_drc_attach(drc, dev); 3581 if (!hotplugged) { 3582 spapr_drc_reset(drc); 3583 } 3584 addr += SPAPR_MEMORY_BLOCK_SIZE; 3585 } 3586 /* send hotplug notification to the 3587 * guest only in case of hotplugged memory 3588 */ 3589 if (hotplugged) { 3590 if (dedicated_hp_event_source) { 3591 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3592 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3593 g_assert(drc); 3594 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3595 nr_lmbs, 3596 spapr_drc_index(drc)); 3597 } else { 3598 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3599 nr_lmbs); 3600 } 3601 } 3602 } 3603 3604 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3605 { 3606 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3607 PCDIMMDevice *dimm = PC_DIMM(dev); 3608 uint64_t size, addr; 3609 int64_t slot; 3610 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3611 3612 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3613 3614 pc_dimm_plug(dimm, MACHINE(ms)); 3615 3616 if (!is_nvdimm) { 3617 addr = object_property_get_uint(OBJECT(dimm), 3618 PC_DIMM_ADDR_PROP, &error_abort); 3619 spapr_add_lmbs(dev, addr, size, 3620 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT)); 3621 } else { 3622 slot = object_property_get_int(OBJECT(dimm), 3623 PC_DIMM_SLOT_PROP, &error_abort); 3624 /* We should have valid slot number at this point */ 3625 g_assert(slot >= 0); 3626 spapr_add_nvdimm(dev, slot); 3627 } 3628 } 3629 3630 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3631 Error **errp) 3632 { 3633 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3634 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3635 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3636 PCDIMMDevice *dimm = PC_DIMM(dev); 3637 Error *local_err = NULL; 3638 uint64_t size; 3639 Object *memdev; 3640 hwaddr pagesize; 3641 3642 if (!smc->dr_lmb_enabled) { 3643 error_setg(errp, "Memory hotplug not supported for this machine"); 3644 return; 3645 } 3646 3647 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3648 if (local_err) { 3649 error_propagate(errp, local_err); 3650 return; 3651 } 3652 3653 if (is_nvdimm) { 3654 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3655 return; 3656 } 3657 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3658 error_setg(errp, "Hotplugged memory size must be a multiple of " 3659 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3660 return; 3661 } 3662 3663 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3664 &error_abort); 3665 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3666 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3667 return; 3668 } 3669 3670 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3671 } 3672 3673 struct SpaprDimmState { 3674 PCDIMMDevice *dimm; 3675 uint32_t nr_lmbs; 3676 QTAILQ_ENTRY(SpaprDimmState) next; 3677 }; 3678 3679 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3680 PCDIMMDevice *dimm) 3681 { 3682 SpaprDimmState *dimm_state = NULL; 3683 3684 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3685 if (dimm_state->dimm == dimm) { 3686 break; 3687 } 3688 } 3689 return dimm_state; 3690 } 3691 3692 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3693 uint32_t nr_lmbs, 3694 PCDIMMDevice *dimm) 3695 { 3696 SpaprDimmState *ds = NULL; 3697 3698 /* 3699 * If this request is for a DIMM whose removal had failed earlier 3700 * (due to guest's refusal to remove the LMBs), we would have this 3701 * dimm already in the pending_dimm_unplugs list. In that 3702 * case don't add again. 3703 */ 3704 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3705 if (!ds) { 3706 ds = g_new0(SpaprDimmState, 1); 3707 ds->nr_lmbs = nr_lmbs; 3708 ds->dimm = dimm; 3709 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3710 } 3711 return ds; 3712 } 3713 3714 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3715 SpaprDimmState *dimm_state) 3716 { 3717 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3718 g_free(dimm_state); 3719 } 3720 3721 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3722 PCDIMMDevice *dimm) 3723 { 3724 SpaprDrc *drc; 3725 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3726 &error_abort); 3727 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3728 uint32_t avail_lmbs = 0; 3729 uint64_t addr_start, addr; 3730 int i; 3731 3732 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3733 &error_abort); 3734 3735 addr = addr_start; 3736 for (i = 0; i < nr_lmbs; i++) { 3737 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3738 addr / SPAPR_MEMORY_BLOCK_SIZE); 3739 g_assert(drc); 3740 if (drc->dev) { 3741 avail_lmbs++; 3742 } 3743 addr += SPAPR_MEMORY_BLOCK_SIZE; 3744 } 3745 3746 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3747 } 3748 3749 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev) 3750 { 3751 SpaprDimmState *ds; 3752 PCDIMMDevice *dimm; 3753 SpaprDrc *drc; 3754 uint32_t nr_lmbs; 3755 uint64_t size, addr_start, addr; 3756 g_autofree char *qapi_error = NULL; 3757 int i; 3758 3759 if (!dev) { 3760 return; 3761 } 3762 3763 dimm = PC_DIMM(dev); 3764 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3765 3766 /* 3767 * 'ds == NULL' would mean that the DIMM doesn't have a pending 3768 * unplug state, but one of its DRC is marked as unplug_requested. 3769 * This is bad and weird enough to g_assert() out. 3770 */ 3771 g_assert(ds); 3772 3773 spapr_pending_dimm_unplugs_remove(spapr, ds); 3774 3775 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3776 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3777 3778 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3779 &error_abort); 3780 3781 addr = addr_start; 3782 for (i = 0; i < nr_lmbs; i++) { 3783 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3784 addr / SPAPR_MEMORY_BLOCK_SIZE); 3785 g_assert(drc); 3786 3787 drc->unplug_requested = false; 3788 addr += SPAPR_MEMORY_BLOCK_SIZE; 3789 } 3790 3791 /* 3792 * Tell QAPI that something happened and the memory 3793 * hotunplug wasn't successful. Keep sending 3794 * MEM_UNPLUG_ERROR even while sending 3795 * DEVICE_UNPLUG_GUEST_ERROR until the deprecation of 3796 * MEM_UNPLUG_ERROR is due. 3797 */ 3798 qapi_error = g_strdup_printf("Memory hotunplug rejected by the guest " 3799 "for device %s", dev->id); 3800 3801 qapi_event_send_mem_unplug_error(dev->id ? : "", qapi_error); 3802 3803 qapi_event_send_device_unplug_guest_error(dev->id, 3804 dev->canonical_path); 3805 } 3806 3807 /* Callback to be called during DRC release. */ 3808 void spapr_lmb_release(DeviceState *dev) 3809 { 3810 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3811 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3812 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3813 3814 /* This information will get lost if a migration occurs 3815 * during the unplug process. In this case recover it. */ 3816 if (ds == NULL) { 3817 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3818 g_assert(ds); 3819 /* The DRC being examined by the caller at least must be counted */ 3820 g_assert(ds->nr_lmbs); 3821 } 3822 3823 if (--ds->nr_lmbs) { 3824 return; 3825 } 3826 3827 /* 3828 * Now that all the LMBs have been removed by the guest, call the 3829 * unplug handler chain. This can never fail. 3830 */ 3831 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3832 object_unparent(OBJECT(dev)); 3833 } 3834 3835 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3836 { 3837 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3838 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3839 3840 /* We really shouldn't get this far without anything to unplug */ 3841 g_assert(ds); 3842 3843 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3844 qdev_unrealize(dev); 3845 spapr_pending_dimm_unplugs_remove(spapr, ds); 3846 } 3847 3848 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3849 DeviceState *dev, Error **errp) 3850 { 3851 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3852 PCDIMMDevice *dimm = PC_DIMM(dev); 3853 uint32_t nr_lmbs; 3854 uint64_t size, addr_start, addr; 3855 int i; 3856 SpaprDrc *drc; 3857 3858 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3859 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3860 return; 3861 } 3862 3863 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3864 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3865 3866 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3867 &error_abort); 3868 3869 /* 3870 * An existing pending dimm state for this DIMM means that there is an 3871 * unplug operation in progress, waiting for the spapr_lmb_release 3872 * callback to complete the job (BQL can't cover that far). In this case, 3873 * bail out to avoid detaching DRCs that were already released. 3874 */ 3875 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3876 error_setg(errp, "Memory unplug already in progress for device %s", 3877 dev->id); 3878 return; 3879 } 3880 3881 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3882 3883 addr = addr_start; 3884 for (i = 0; i < nr_lmbs; i++) { 3885 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3886 addr / SPAPR_MEMORY_BLOCK_SIZE); 3887 g_assert(drc); 3888 3889 spapr_drc_unplug_request(drc); 3890 addr += SPAPR_MEMORY_BLOCK_SIZE; 3891 } 3892 3893 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3894 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3895 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3896 nr_lmbs, spapr_drc_index(drc)); 3897 } 3898 3899 /* Callback to be called during DRC release. */ 3900 void spapr_core_release(DeviceState *dev) 3901 { 3902 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3903 3904 /* Call the unplug handler chain. This can never fail. */ 3905 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3906 object_unparent(OBJECT(dev)); 3907 } 3908 3909 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3910 { 3911 MachineState *ms = MACHINE(hotplug_dev); 3912 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3913 CPUCore *cc = CPU_CORE(dev); 3914 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3915 3916 if (smc->pre_2_10_has_unused_icps) { 3917 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3918 int i; 3919 3920 for (i = 0; i < cc->nr_threads; i++) { 3921 CPUState *cs = CPU(sc->threads[i]); 3922 3923 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3924 } 3925 } 3926 3927 assert(core_slot); 3928 core_slot->cpu = NULL; 3929 qdev_unrealize(dev); 3930 } 3931 3932 static 3933 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3934 Error **errp) 3935 { 3936 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3937 int index; 3938 SpaprDrc *drc; 3939 CPUCore *cc = CPU_CORE(dev); 3940 3941 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3942 error_setg(errp, "Unable to find CPU core with core-id: %d", 3943 cc->core_id); 3944 return; 3945 } 3946 if (index == 0) { 3947 error_setg(errp, "Boot CPU core may not be unplugged"); 3948 return; 3949 } 3950 3951 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3952 spapr_vcpu_id(spapr, cc->core_id)); 3953 g_assert(drc); 3954 3955 if (!spapr_drc_unplug_requested(drc)) { 3956 spapr_drc_unplug_request(drc); 3957 } 3958 3959 /* 3960 * spapr_hotplug_req_remove_by_index is left unguarded, out of the 3961 * "!spapr_drc_unplug_requested" check, to allow for multiple IRQ 3962 * pulses removing the same CPU. Otherwise, in an failed hotunplug 3963 * attempt (e.g. the kernel will refuse to remove the last online 3964 * CPU), we will never attempt it again because unplug_requested 3965 * will still be 'true' in that case. 3966 */ 3967 spapr_hotplug_req_remove_by_index(drc); 3968 } 3969 3970 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3971 void *fdt, int *fdt_start_offset, Error **errp) 3972 { 3973 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3974 CPUState *cs = CPU(core->threads[0]); 3975 PowerPCCPU *cpu = POWERPC_CPU(cs); 3976 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3977 int id = spapr_get_vcpu_id(cpu); 3978 g_autofree char *nodename = NULL; 3979 int offset; 3980 3981 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3982 offset = fdt_add_subnode(fdt, 0, nodename); 3983 3984 spapr_dt_cpu(cs, fdt, offset, spapr); 3985 3986 /* 3987 * spapr_dt_cpu() does not fill the 'name' property in the 3988 * CPU node. The function is called during boot process, before 3989 * and after CAS, and overwriting the 'name' property written 3990 * by SLOF is not allowed. 3991 * 3992 * Write it manually after spapr_dt_cpu(). This makes the hotplug 3993 * CPUs more compatible with the coldplugged ones, which have 3994 * the 'name' property. Linux Kernel also relies on this 3995 * property to identify CPU nodes. 3996 */ 3997 _FDT((fdt_setprop_string(fdt, offset, "name", nodename))); 3998 3999 *fdt_start_offset = offset; 4000 return 0; 4001 } 4002 4003 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4004 { 4005 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4006 MachineClass *mc = MACHINE_GET_CLASS(spapr); 4007 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4008 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 4009 CPUCore *cc = CPU_CORE(dev); 4010 SpaprDrc *drc; 4011 CPUArchId *core_slot; 4012 int index; 4013 bool hotplugged = spapr_drc_hotplugged(dev); 4014 int i; 4015 4016 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 4017 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */ 4018 4019 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 4020 spapr_vcpu_id(spapr, cc->core_id)); 4021 4022 g_assert(drc || !mc->has_hotpluggable_cpus); 4023 4024 if (drc) { 4025 /* 4026 * spapr_core_pre_plug() already buys us this is a brand new 4027 * core being plugged into a free slot. Nothing should already 4028 * be attached to the corresponding DRC. 4029 */ 4030 spapr_drc_attach(drc, dev); 4031 4032 if (hotplugged) { 4033 /* 4034 * Send hotplug notification interrupt to the guest only 4035 * in case of hotplugged CPUs. 4036 */ 4037 spapr_hotplug_req_add_by_index(drc); 4038 } else { 4039 spapr_drc_reset(drc); 4040 } 4041 } 4042 4043 core_slot->cpu = CPU(dev); 4044 4045 /* 4046 * Set compatibility mode to match the boot CPU, which was either set 4047 * by the machine reset code or by CAS. This really shouldn't fail at 4048 * this point. 4049 */ 4050 if (hotplugged) { 4051 for (i = 0; i < cc->nr_threads; i++) { 4052 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 4053 &error_abort); 4054 } 4055 } 4056 4057 if (smc->pre_2_10_has_unused_icps) { 4058 for (i = 0; i < cc->nr_threads; i++) { 4059 CPUState *cs = CPU(core->threads[i]); 4060 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 4061 } 4062 } 4063 } 4064 4065 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4066 Error **errp) 4067 { 4068 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 4069 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 4070 CPUCore *cc = CPU_CORE(dev); 4071 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 4072 const char *type = object_get_typename(OBJECT(dev)); 4073 CPUArchId *core_slot; 4074 int index; 4075 unsigned int smp_threads = machine->smp.threads; 4076 4077 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 4078 error_setg(errp, "CPU hotplug not supported for this machine"); 4079 return; 4080 } 4081 4082 if (strcmp(base_core_type, type)) { 4083 error_setg(errp, "CPU core type should be %s", base_core_type); 4084 return; 4085 } 4086 4087 if (cc->core_id % smp_threads) { 4088 error_setg(errp, "invalid core id %d", cc->core_id); 4089 return; 4090 } 4091 4092 /* 4093 * In general we should have homogeneous threads-per-core, but old 4094 * (pre hotplug support) machine types allow the last core to have 4095 * reduced threads as a compatibility hack for when we allowed 4096 * total vcpus not a multiple of threads-per-core. 4097 */ 4098 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 4099 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 4100 smp_threads); 4101 return; 4102 } 4103 4104 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 4105 if (!core_slot) { 4106 error_setg(errp, "core id %d out of range", cc->core_id); 4107 return; 4108 } 4109 4110 if (core_slot->cpu) { 4111 error_setg(errp, "core %d already populated", cc->core_id); 4112 return; 4113 } 4114 4115 numa_cpu_pre_plug(core_slot, dev, errp); 4116 } 4117 4118 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 4119 void *fdt, int *fdt_start_offset, Error **errp) 4120 { 4121 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 4122 int intc_phandle; 4123 4124 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 4125 if (intc_phandle <= 0) { 4126 return -1; 4127 } 4128 4129 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 4130 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 4131 return -1; 4132 } 4133 4134 /* generally SLOF creates these, for hotplug it's up to QEMU */ 4135 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 4136 4137 return 0; 4138 } 4139 4140 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4141 Error **errp) 4142 { 4143 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4144 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4145 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4146 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 4147 SpaprDrc *drc; 4148 4149 if (dev->hotplugged && !smc->dr_phb_enabled) { 4150 error_setg(errp, "PHB hotplug not supported for this machine"); 4151 return false; 4152 } 4153 4154 if (sphb->index == (uint32_t)-1) { 4155 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 4156 return false; 4157 } 4158 4159 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4160 if (drc && drc->dev) { 4161 error_setg(errp, "PHB %d already attached", sphb->index); 4162 return false; 4163 } 4164 4165 /* 4166 * This will check that sphb->index doesn't exceed the maximum number of 4167 * PHBs for the current machine type. 4168 */ 4169 return 4170 smc->phb_placement(spapr, sphb->index, 4171 &sphb->buid, &sphb->io_win_addr, 4172 &sphb->mem_win_addr, &sphb->mem64_win_addr, 4173 windows_supported, sphb->dma_liobn, 4174 errp); 4175 } 4176 4177 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4178 { 4179 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4180 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4181 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4182 SpaprDrc *drc; 4183 bool hotplugged = spapr_drc_hotplugged(dev); 4184 4185 if (!smc->dr_phb_enabled) { 4186 return; 4187 } 4188 4189 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4190 /* hotplug hooks should check it's enabled before getting this far */ 4191 assert(drc); 4192 4193 /* spapr_phb_pre_plug() already checked the DRC is attachable */ 4194 spapr_drc_attach(drc, dev); 4195 4196 if (hotplugged) { 4197 spapr_hotplug_req_add_by_index(drc); 4198 } else { 4199 spapr_drc_reset(drc); 4200 } 4201 } 4202 4203 void spapr_phb_release(DeviceState *dev) 4204 { 4205 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4206 4207 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4208 object_unparent(OBJECT(dev)); 4209 } 4210 4211 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4212 { 4213 qdev_unrealize(dev); 4214 } 4215 4216 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4217 DeviceState *dev, Error **errp) 4218 { 4219 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4220 SpaprDrc *drc; 4221 4222 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4223 assert(drc); 4224 4225 if (!spapr_drc_unplug_requested(drc)) { 4226 spapr_drc_unplug_request(drc); 4227 spapr_hotplug_req_remove_by_index(drc); 4228 } else { 4229 error_setg(errp, 4230 "PCI Host Bridge unplug already in progress for device %s", 4231 dev->id); 4232 } 4233 } 4234 4235 static 4236 bool spapr_tpm_proxy_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4237 Error **errp) 4238 { 4239 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4240 4241 if (spapr->tpm_proxy != NULL) { 4242 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4243 return false; 4244 } 4245 4246 return true; 4247 } 4248 4249 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4250 { 4251 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4252 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4253 4254 /* Already checked in spapr_tpm_proxy_pre_plug() */ 4255 g_assert(spapr->tpm_proxy == NULL); 4256 4257 spapr->tpm_proxy = tpm_proxy; 4258 } 4259 4260 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4261 { 4262 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4263 4264 qdev_unrealize(dev); 4265 object_unparent(OBJECT(dev)); 4266 spapr->tpm_proxy = NULL; 4267 } 4268 4269 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4270 DeviceState *dev, Error **errp) 4271 { 4272 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4273 spapr_memory_plug(hotplug_dev, dev); 4274 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4275 spapr_core_plug(hotplug_dev, dev); 4276 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4277 spapr_phb_plug(hotplug_dev, dev); 4278 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4279 spapr_tpm_proxy_plug(hotplug_dev, dev); 4280 } 4281 } 4282 4283 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4284 DeviceState *dev, Error **errp) 4285 { 4286 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4287 spapr_memory_unplug(hotplug_dev, dev); 4288 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4289 spapr_core_unplug(hotplug_dev, dev); 4290 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4291 spapr_phb_unplug(hotplug_dev, dev); 4292 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4293 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4294 } 4295 } 4296 4297 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr) 4298 { 4299 return spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT) || 4300 /* 4301 * CAS will process all pending unplug requests. 4302 * 4303 * HACK: a guest could theoretically have cleared all bits in OV5, 4304 * but none of the guests we care for do. 4305 */ 4306 spapr_ovec_empty(spapr->ov5_cas); 4307 } 4308 4309 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4310 DeviceState *dev, Error **errp) 4311 { 4312 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4313 MachineClass *mc = MACHINE_GET_CLASS(sms); 4314 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4315 4316 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4317 if (spapr_memory_hot_unplug_supported(sms)) { 4318 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4319 } else { 4320 error_setg(errp, "Memory hot unplug not supported for this guest"); 4321 } 4322 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4323 if (!mc->has_hotpluggable_cpus) { 4324 error_setg(errp, "CPU hot unplug not supported on this machine"); 4325 return; 4326 } 4327 spapr_core_unplug_request(hotplug_dev, dev, errp); 4328 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4329 if (!smc->dr_phb_enabled) { 4330 error_setg(errp, "PHB hot unplug not supported on this machine"); 4331 return; 4332 } 4333 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4334 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4335 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4336 } 4337 } 4338 4339 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4340 DeviceState *dev, Error **errp) 4341 { 4342 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4343 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4344 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4345 spapr_core_pre_plug(hotplug_dev, dev, errp); 4346 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4347 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4348 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4349 spapr_tpm_proxy_pre_plug(hotplug_dev, dev, errp); 4350 } 4351 } 4352 4353 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4354 DeviceState *dev) 4355 { 4356 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4357 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4358 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4359 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4360 return HOTPLUG_HANDLER(machine); 4361 } 4362 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4363 PCIDevice *pcidev = PCI_DEVICE(dev); 4364 PCIBus *root = pci_device_root_bus(pcidev); 4365 SpaprPhbState *phb = 4366 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4367 TYPE_SPAPR_PCI_HOST_BRIDGE); 4368 4369 if (phb) { 4370 return HOTPLUG_HANDLER(phb); 4371 } 4372 } 4373 return NULL; 4374 } 4375 4376 static CpuInstanceProperties 4377 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4378 { 4379 CPUArchId *core_slot; 4380 MachineClass *mc = MACHINE_GET_CLASS(machine); 4381 4382 /* make sure possible_cpu are initialized */ 4383 mc->possible_cpu_arch_ids(machine); 4384 /* get CPU core slot containing thread that matches cpu_index */ 4385 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4386 assert(core_slot); 4387 return core_slot->props; 4388 } 4389 4390 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4391 { 4392 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4393 } 4394 4395 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4396 { 4397 int i; 4398 unsigned int smp_threads = machine->smp.threads; 4399 unsigned int smp_cpus = machine->smp.cpus; 4400 const char *core_type; 4401 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4402 MachineClass *mc = MACHINE_GET_CLASS(machine); 4403 4404 if (!mc->has_hotpluggable_cpus) { 4405 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4406 } 4407 if (machine->possible_cpus) { 4408 assert(machine->possible_cpus->len == spapr_max_cores); 4409 return machine->possible_cpus; 4410 } 4411 4412 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4413 if (!core_type) { 4414 error_report("Unable to find sPAPR CPU Core definition"); 4415 exit(1); 4416 } 4417 4418 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4419 sizeof(CPUArchId) * spapr_max_cores); 4420 machine->possible_cpus->len = spapr_max_cores; 4421 for (i = 0; i < machine->possible_cpus->len; i++) { 4422 int core_id = i * smp_threads; 4423 4424 machine->possible_cpus->cpus[i].type = core_type; 4425 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4426 machine->possible_cpus->cpus[i].arch_id = core_id; 4427 machine->possible_cpus->cpus[i].props.has_core_id = true; 4428 machine->possible_cpus->cpus[i].props.core_id = core_id; 4429 } 4430 return machine->possible_cpus; 4431 } 4432 4433 static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4434 uint64_t *buid, hwaddr *pio, 4435 hwaddr *mmio32, hwaddr *mmio64, 4436 unsigned n_dma, uint32_t *liobns, Error **errp) 4437 { 4438 /* 4439 * New-style PHB window placement. 4440 * 4441 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4442 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4443 * windows. 4444 * 4445 * Some guest kernels can't work with MMIO windows above 1<<46 4446 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4447 * 4448 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4449 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4450 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4451 * 1TiB 64-bit MMIO windows for each PHB. 4452 */ 4453 const uint64_t base_buid = 0x800000020000000ULL; 4454 int i; 4455 4456 /* Sanity check natural alignments */ 4457 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4458 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4459 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4460 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4461 /* Sanity check bounds */ 4462 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4463 SPAPR_PCI_MEM32_WIN_SIZE); 4464 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4465 SPAPR_PCI_MEM64_WIN_SIZE); 4466 4467 if (index >= SPAPR_MAX_PHBS) { 4468 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4469 SPAPR_MAX_PHBS - 1); 4470 return false; 4471 } 4472 4473 *buid = base_buid + index; 4474 for (i = 0; i < n_dma; ++i) { 4475 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4476 } 4477 4478 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4479 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4480 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4481 return true; 4482 } 4483 4484 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4485 { 4486 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4487 4488 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4489 } 4490 4491 static void spapr_ics_resend(XICSFabric *dev) 4492 { 4493 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4494 4495 ics_resend(spapr->ics); 4496 } 4497 4498 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4499 { 4500 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4501 4502 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4503 } 4504 4505 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4506 Monitor *mon) 4507 { 4508 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4509 4510 spapr_irq_print_info(spapr, mon); 4511 monitor_printf(mon, "irqchip: %s\n", 4512 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4513 } 4514 4515 /* 4516 * This is a XIVE only operation 4517 */ 4518 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4519 uint8_t nvt_blk, uint32_t nvt_idx, 4520 bool cam_ignore, uint8_t priority, 4521 uint32_t logic_serv, XiveTCTXMatch *match) 4522 { 4523 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4524 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4525 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4526 int count; 4527 4528 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4529 priority, logic_serv, match); 4530 if (count < 0) { 4531 return count; 4532 } 4533 4534 /* 4535 * When we implement the save and restore of the thread interrupt 4536 * contexts in the enter/exit CPU handlers of the machine and the 4537 * escalations in QEMU, we should be able to handle non dispatched 4538 * vCPUs. 4539 * 4540 * Until this is done, the sPAPR machine should find at least one 4541 * matching context always. 4542 */ 4543 if (count == 0) { 4544 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4545 nvt_blk, nvt_idx); 4546 } 4547 4548 return count; 4549 } 4550 4551 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4552 { 4553 return cpu->vcpu_id; 4554 } 4555 4556 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4557 { 4558 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4559 MachineState *ms = MACHINE(spapr); 4560 int vcpu_id; 4561 4562 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4563 4564 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4565 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4566 error_append_hint(errp, "Adjust the number of cpus to %d " 4567 "or try to raise the number of threads per core\n", 4568 vcpu_id * ms->smp.threads / spapr->vsmt); 4569 return false; 4570 } 4571 4572 cpu->vcpu_id = vcpu_id; 4573 return true; 4574 } 4575 4576 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4577 { 4578 CPUState *cs; 4579 4580 CPU_FOREACH(cs) { 4581 PowerPCCPU *cpu = POWERPC_CPU(cs); 4582 4583 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4584 return cpu; 4585 } 4586 } 4587 4588 return NULL; 4589 } 4590 4591 static bool spapr_cpu_in_nested(PowerPCCPU *cpu) 4592 { 4593 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4594 4595 return spapr_cpu->in_nested; 4596 } 4597 4598 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4599 { 4600 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4601 4602 /* These are only called by TCG, KVM maintains dispatch state */ 4603 4604 spapr_cpu->prod = false; 4605 if (spapr_cpu->vpa_addr) { 4606 CPUState *cs = CPU(cpu); 4607 uint32_t dispatch; 4608 4609 dispatch = ldl_be_phys(cs->as, 4610 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4611 dispatch++; 4612 if ((dispatch & 1) != 0) { 4613 qemu_log_mask(LOG_GUEST_ERROR, 4614 "VPA: incorrect dispatch counter value for " 4615 "dispatched partition %u, correcting.\n", dispatch); 4616 dispatch++; 4617 } 4618 stl_be_phys(cs->as, 4619 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4620 } 4621 } 4622 4623 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4624 { 4625 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4626 4627 if (spapr_cpu->vpa_addr) { 4628 CPUState *cs = CPU(cpu); 4629 uint32_t dispatch; 4630 4631 dispatch = ldl_be_phys(cs->as, 4632 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4633 dispatch++; 4634 if ((dispatch & 1) != 1) { 4635 qemu_log_mask(LOG_GUEST_ERROR, 4636 "VPA: incorrect dispatch counter value for " 4637 "preempted partition %u, correcting.\n", dispatch); 4638 dispatch++; 4639 } 4640 stl_be_phys(cs->as, 4641 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4642 } 4643 } 4644 4645 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4646 { 4647 MachineClass *mc = MACHINE_CLASS(oc); 4648 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4649 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4650 NMIClass *nc = NMI_CLASS(oc); 4651 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4652 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4653 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4654 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4655 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4656 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc); 4657 4658 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4659 mc->ignore_boot_device_suffixes = true; 4660 4661 /* 4662 * We set up the default / latest behaviour here. The class_init 4663 * functions for the specific versioned machine types can override 4664 * these details for backwards compatibility 4665 */ 4666 mc->init = spapr_machine_init; 4667 mc->reset = spapr_machine_reset; 4668 mc->block_default_type = IF_SCSI; 4669 4670 /* 4671 * While KVM determines max cpus in kvm_init() using kvm_max_vcpus(), 4672 * In TCG the limit is restricted by the range of CPU IPIs available. 4673 */ 4674 mc->max_cpus = SPAPR_IRQ_NR_IPIS; 4675 4676 mc->no_parallel = 1; 4677 mc->default_boot_order = ""; 4678 mc->default_ram_size = 512 * MiB; 4679 mc->default_ram_id = "ppc_spapr.ram"; 4680 mc->default_display = "std"; 4681 mc->kvm_type = spapr_kvm_type; 4682 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4683 mc->pci_allow_0_address = true; 4684 assert(!mc->get_hotplug_handler); 4685 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4686 hc->pre_plug = spapr_machine_device_pre_plug; 4687 hc->plug = spapr_machine_device_plug; 4688 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4689 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4690 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4691 hc->unplug_request = spapr_machine_device_unplug_request; 4692 hc->unplug = spapr_machine_device_unplug; 4693 4694 smc->dr_lmb_enabled = true; 4695 smc->update_dt_enabled = true; 4696 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 4697 mc->has_hotpluggable_cpus = true; 4698 mc->nvdimm_supported = true; 4699 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4700 fwc->get_dev_path = spapr_get_fw_dev_path; 4701 nc->nmi_monitor_handler = spapr_nmi; 4702 smc->phb_placement = spapr_phb_placement; 4703 vhc->cpu_in_nested = spapr_cpu_in_nested; 4704 vhc->deliver_hv_excp = spapr_exit_nested; 4705 vhc->hypercall = emulate_spapr_hypercall; 4706 vhc->hpt_mask = spapr_hpt_mask; 4707 vhc->map_hptes = spapr_map_hptes; 4708 vhc->unmap_hptes = spapr_unmap_hptes; 4709 vhc->hpte_set_c = spapr_hpte_set_c; 4710 vhc->hpte_set_r = spapr_hpte_set_r; 4711 vhc->get_pate = spapr_get_pate; 4712 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4713 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4714 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4715 xic->ics_get = spapr_ics_get; 4716 xic->ics_resend = spapr_ics_resend; 4717 xic->icp_get = spapr_icp_get; 4718 ispc->print_info = spapr_pic_print_info; 4719 /* Force NUMA node memory size to be a multiple of 4720 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4721 * in which LMBs are represented and hot-added 4722 */ 4723 mc->numa_mem_align_shift = 28; 4724 mc->auto_enable_numa = true; 4725 4726 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4727 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4728 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4729 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4730 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4731 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4732 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4733 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4734 smc->default_caps.caps[SPAPR_CAP_NESTED_PAPR] = SPAPR_CAP_OFF; 4735 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4736 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4737 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4738 smc->default_caps.caps[SPAPR_CAP_RPT_INVALIDATE] = SPAPR_CAP_OFF; 4739 4740 /* 4741 * This cap specifies whether the AIL 3 mode for 4742 * H_SET_RESOURCE is supported. The default is modified 4743 * by default_caps_with_cpu(). 4744 */ 4745 smc->default_caps.caps[SPAPR_CAP_AIL_MODE_3] = SPAPR_CAP_ON; 4746 spapr_caps_add_properties(smc); 4747 smc->irq = &spapr_irq_dual; 4748 smc->dr_phb_enabled = true; 4749 smc->linux_pci_probe = true; 4750 smc->smp_threads_vsmt = true; 4751 smc->nr_xirqs = SPAPR_NR_XIRQS; 4752 xfc->match_nvt = spapr_match_nvt; 4753 vmc->client_architecture_support = spapr_vof_client_architecture_support; 4754 vmc->quiesce = spapr_vof_quiesce; 4755 vmc->setprop = spapr_vof_setprop; 4756 } 4757 4758 static const TypeInfo spapr_machine_info = { 4759 .name = TYPE_SPAPR_MACHINE, 4760 .parent = TYPE_MACHINE, 4761 .abstract = true, 4762 .instance_size = sizeof(SpaprMachineState), 4763 .instance_init = spapr_instance_init, 4764 .instance_finalize = spapr_machine_finalizefn, 4765 .class_size = sizeof(SpaprMachineClass), 4766 .class_init = spapr_machine_class_init, 4767 .interfaces = (InterfaceInfo[]) { 4768 { TYPE_FW_PATH_PROVIDER }, 4769 { TYPE_NMI }, 4770 { TYPE_HOTPLUG_HANDLER }, 4771 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4772 { TYPE_XICS_FABRIC }, 4773 { TYPE_INTERRUPT_STATS_PROVIDER }, 4774 { TYPE_XIVE_FABRIC }, 4775 { TYPE_VOF_MACHINE_IF }, 4776 { } 4777 }, 4778 }; 4779 4780 static void spapr_machine_latest_class_options(MachineClass *mc) 4781 { 4782 mc->alias = "pseries"; 4783 mc->is_default = true; 4784 } 4785 4786 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4787 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4788 void *data) \ 4789 { \ 4790 MachineClass *mc = MACHINE_CLASS(oc); \ 4791 spapr_machine_##suffix##_class_options(mc); \ 4792 if (latest) { \ 4793 spapr_machine_latest_class_options(mc); \ 4794 } \ 4795 } \ 4796 static const TypeInfo spapr_machine_##suffix##_info = { \ 4797 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4798 .parent = TYPE_SPAPR_MACHINE, \ 4799 .class_init = spapr_machine_##suffix##_class_init, \ 4800 }; \ 4801 static void spapr_machine_register_##suffix(void) \ 4802 { \ 4803 type_register(&spapr_machine_##suffix##_info); \ 4804 } \ 4805 type_init(spapr_machine_register_##suffix) 4806 4807 /* 4808 * pseries-9.0 4809 */ 4810 static void spapr_machine_9_0_class_options(MachineClass *mc) 4811 { 4812 /* Defaults for the latest behaviour inherited from the base class */ 4813 } 4814 4815 DEFINE_SPAPR_MACHINE(9_0, "9.0", true); 4816 4817 /* 4818 * pseries-8.2 4819 */ 4820 static void spapr_machine_8_2_class_options(MachineClass *mc) 4821 { 4822 spapr_machine_9_0_class_options(mc); 4823 compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len); 4824 } 4825 4826 DEFINE_SPAPR_MACHINE(8_2, "8.2", false); 4827 4828 /* 4829 * pseries-8.1 4830 */ 4831 static void spapr_machine_8_1_class_options(MachineClass *mc) 4832 { 4833 spapr_machine_8_2_class_options(mc); 4834 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len); 4835 } 4836 4837 DEFINE_SPAPR_MACHINE(8_1, "8.1", false); 4838 4839 /* 4840 * pseries-8.0 4841 */ 4842 static void spapr_machine_8_0_class_options(MachineClass *mc) 4843 { 4844 spapr_machine_8_1_class_options(mc); 4845 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len); 4846 } 4847 4848 DEFINE_SPAPR_MACHINE(8_0, "8.0", false); 4849 4850 /* 4851 * pseries-7.2 4852 */ 4853 static void spapr_machine_7_2_class_options(MachineClass *mc) 4854 { 4855 spapr_machine_8_0_class_options(mc); 4856 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len); 4857 } 4858 4859 DEFINE_SPAPR_MACHINE(7_2, "7.2", false); 4860 4861 /* 4862 * pseries-7.1 4863 */ 4864 static void spapr_machine_7_1_class_options(MachineClass *mc) 4865 { 4866 spapr_machine_7_2_class_options(mc); 4867 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 4868 } 4869 4870 DEFINE_SPAPR_MACHINE(7_1, "7.1", false); 4871 4872 /* 4873 * pseries-7.0 4874 */ 4875 static void spapr_machine_7_0_class_options(MachineClass *mc) 4876 { 4877 spapr_machine_7_1_class_options(mc); 4878 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 4879 } 4880 4881 DEFINE_SPAPR_MACHINE(7_0, "7.0", false); 4882 4883 /* 4884 * pseries-6.2 4885 */ 4886 static void spapr_machine_6_2_class_options(MachineClass *mc) 4887 { 4888 spapr_machine_7_0_class_options(mc); 4889 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 4890 } 4891 4892 DEFINE_SPAPR_MACHINE(6_2, "6.2", false); 4893 4894 /* 4895 * pseries-6.1 4896 */ 4897 static void spapr_machine_6_1_class_options(MachineClass *mc) 4898 { 4899 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4900 4901 spapr_machine_6_2_class_options(mc); 4902 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 4903 smc->pre_6_2_numa_affinity = true; 4904 mc->smp_props.prefer_sockets = true; 4905 } 4906 4907 DEFINE_SPAPR_MACHINE(6_1, "6.1", false); 4908 4909 /* 4910 * pseries-6.0 4911 */ 4912 static void spapr_machine_6_0_class_options(MachineClass *mc) 4913 { 4914 spapr_machine_6_1_class_options(mc); 4915 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 4916 } 4917 4918 DEFINE_SPAPR_MACHINE(6_0, "6.0", false); 4919 4920 /* 4921 * pseries-5.2 4922 */ 4923 static void spapr_machine_5_2_class_options(MachineClass *mc) 4924 { 4925 spapr_machine_6_0_class_options(mc); 4926 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 4927 } 4928 4929 DEFINE_SPAPR_MACHINE(5_2, "5.2", false); 4930 4931 /* 4932 * pseries-5.1 4933 */ 4934 static void spapr_machine_5_1_class_options(MachineClass *mc) 4935 { 4936 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4937 4938 spapr_machine_5_2_class_options(mc); 4939 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4940 smc->pre_5_2_numa_associativity = true; 4941 } 4942 4943 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4944 4945 /* 4946 * pseries-5.0 4947 */ 4948 static void spapr_machine_5_0_class_options(MachineClass *mc) 4949 { 4950 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4951 static GlobalProperty compat[] = { 4952 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4953 }; 4954 4955 spapr_machine_5_1_class_options(mc); 4956 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4957 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4958 mc->numa_mem_supported = true; 4959 smc->pre_5_1_assoc_refpoints = true; 4960 } 4961 4962 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4963 4964 /* 4965 * pseries-4.2 4966 */ 4967 static void spapr_machine_4_2_class_options(MachineClass *mc) 4968 { 4969 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4970 4971 spapr_machine_5_0_class_options(mc); 4972 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4973 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4974 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4975 smc->rma_limit = 16 * GiB; 4976 mc->nvdimm_supported = false; 4977 } 4978 4979 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4980 4981 /* 4982 * pseries-4.1 4983 */ 4984 static void spapr_machine_4_1_class_options(MachineClass *mc) 4985 { 4986 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4987 static GlobalProperty compat[] = { 4988 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4989 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4990 }; 4991 4992 spapr_machine_4_2_class_options(mc); 4993 smc->linux_pci_probe = false; 4994 smc->smp_threads_vsmt = false; 4995 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4996 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4997 } 4998 4999 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 5000 5001 /* 5002 * pseries-4.0 5003 */ 5004 static bool phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 5005 uint64_t *buid, hwaddr *pio, 5006 hwaddr *mmio32, hwaddr *mmio64, 5007 unsigned n_dma, uint32_t *liobns, Error **errp) 5008 { 5009 if (!spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, 5010 liobns, errp)) { 5011 return false; 5012 } 5013 return true; 5014 } 5015 static void spapr_machine_4_0_class_options(MachineClass *mc) 5016 { 5017 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5018 5019 spapr_machine_4_1_class_options(mc); 5020 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 5021 smc->phb_placement = phb_placement_4_0; 5022 smc->irq = &spapr_irq_xics; 5023 smc->pre_4_1_migration = true; 5024 } 5025 5026 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 5027 5028 /* 5029 * pseries-3.1 5030 */ 5031 static void spapr_machine_3_1_class_options(MachineClass *mc) 5032 { 5033 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5034 5035 spapr_machine_4_0_class_options(mc); 5036 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 5037 5038 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 5039 smc->update_dt_enabled = false; 5040 smc->dr_phb_enabled = false; 5041 smc->broken_host_serial_model = true; 5042 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 5043 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 5044 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 5045 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 5046 } 5047 5048 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 5049 5050 /* 5051 * pseries-3.0 5052 */ 5053 5054 static void spapr_machine_3_0_class_options(MachineClass *mc) 5055 { 5056 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5057 5058 spapr_machine_3_1_class_options(mc); 5059 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 5060 5061 smc->legacy_irq_allocation = true; 5062 smc->nr_xirqs = 0x400; 5063 smc->irq = &spapr_irq_xics_legacy; 5064 } 5065 5066 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 5067 5068 /* 5069 * pseries-2.12 5070 */ 5071 static void spapr_machine_2_12_class_options(MachineClass *mc) 5072 { 5073 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5074 static GlobalProperty compat[] = { 5075 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 5076 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 5077 }; 5078 5079 spapr_machine_3_0_class_options(mc); 5080 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 5081 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5082 5083 /* We depend on kvm_enabled() to choose a default value for the 5084 * hpt-max-page-size capability. Of course we can't do it here 5085 * because this is too early and the HW accelerator isn't initialized 5086 * yet. Postpone this to machine init (see default_caps_with_cpu()). 5087 */ 5088 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 5089 } 5090 5091 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 5092 5093 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 5094 { 5095 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5096 5097 spapr_machine_2_12_class_options(mc); 5098 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 5099 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 5100 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 5101 } 5102 5103 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 5104 5105 /* 5106 * pseries-2.11 5107 */ 5108 5109 static void spapr_machine_2_11_class_options(MachineClass *mc) 5110 { 5111 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5112 5113 spapr_machine_2_12_class_options(mc); 5114 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 5115 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 5116 mc->deprecation_reason = "old and not maintained - use a 2.12+ version"; 5117 } 5118 5119 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 5120 5121 /* 5122 * pseries-2.10 5123 */ 5124 5125 static void spapr_machine_2_10_class_options(MachineClass *mc) 5126 { 5127 spapr_machine_2_11_class_options(mc); 5128 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 5129 } 5130 5131 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 5132 5133 /* 5134 * pseries-2.9 5135 */ 5136 5137 static void spapr_machine_2_9_class_options(MachineClass *mc) 5138 { 5139 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5140 static GlobalProperty compat[] = { 5141 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 5142 }; 5143 5144 spapr_machine_2_10_class_options(mc); 5145 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 5146 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5147 smc->pre_2_10_has_unused_icps = true; 5148 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 5149 } 5150 5151 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 5152 5153 /* 5154 * pseries-2.8 5155 */ 5156 5157 static void spapr_machine_2_8_class_options(MachineClass *mc) 5158 { 5159 static GlobalProperty compat[] = { 5160 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 5161 }; 5162 5163 spapr_machine_2_9_class_options(mc); 5164 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 5165 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5166 mc->numa_mem_align_shift = 23; 5167 } 5168 5169 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 5170 5171 /* 5172 * pseries-2.7 5173 */ 5174 5175 static bool phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 5176 uint64_t *buid, hwaddr *pio, 5177 hwaddr *mmio32, hwaddr *mmio64, 5178 unsigned n_dma, uint32_t *liobns, Error **errp) 5179 { 5180 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 5181 const uint64_t base_buid = 0x800000020000000ULL; 5182 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 5183 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 5184 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 5185 const uint32_t max_index = 255; 5186 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 5187 5188 uint64_t ram_top = MACHINE(spapr)->ram_size; 5189 hwaddr phb0_base, phb_base; 5190 int i; 5191 5192 /* Do we have device memory? */ 5193 if (MACHINE(spapr)->device_memory) { 5194 /* Can't just use maxram_size, because there may be an 5195 * alignment gap between normal and device memory regions 5196 */ 5197 ram_top = MACHINE(spapr)->device_memory->base + 5198 memory_region_size(&MACHINE(spapr)->device_memory->mr); 5199 } 5200 5201 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 5202 5203 if (index > max_index) { 5204 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 5205 max_index); 5206 return false; 5207 } 5208 5209 *buid = base_buid + index; 5210 for (i = 0; i < n_dma; ++i) { 5211 liobns[i] = SPAPR_PCI_LIOBN(index, i); 5212 } 5213 5214 phb_base = phb0_base + index * phb_spacing; 5215 *pio = phb_base + pio_offset; 5216 *mmio32 = phb_base + mmio_offset; 5217 /* 5218 * We don't set the 64-bit MMIO window, relying on the PHB's 5219 * fallback behaviour of automatically splitting a large "32-bit" 5220 * window into contiguous 32-bit and 64-bit windows 5221 */ 5222 5223 return true; 5224 } 5225 5226 static void spapr_machine_2_7_class_options(MachineClass *mc) 5227 { 5228 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5229 static GlobalProperty compat[] = { 5230 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 5231 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 5232 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 5233 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 5234 }; 5235 5236 spapr_machine_2_8_class_options(mc); 5237 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 5238 mc->default_machine_opts = "modern-hotplug-events=off"; 5239 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 5240 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5241 smc->phb_placement = phb_placement_2_7; 5242 } 5243 5244 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 5245 5246 /* 5247 * pseries-2.6 5248 */ 5249 5250 static void spapr_machine_2_6_class_options(MachineClass *mc) 5251 { 5252 static GlobalProperty compat[] = { 5253 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 5254 }; 5255 5256 spapr_machine_2_7_class_options(mc); 5257 mc->has_hotpluggable_cpus = false; 5258 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 5259 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5260 } 5261 5262 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 5263 5264 /* 5265 * pseries-2.5 5266 */ 5267 5268 static void spapr_machine_2_5_class_options(MachineClass *mc) 5269 { 5270 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5271 static GlobalProperty compat[] = { 5272 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 5273 }; 5274 5275 spapr_machine_2_6_class_options(mc); 5276 smc->use_ohci_by_default = true; 5277 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 5278 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5279 } 5280 5281 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 5282 5283 /* 5284 * pseries-2.4 5285 */ 5286 5287 static void spapr_machine_2_4_class_options(MachineClass *mc) 5288 { 5289 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5290 5291 spapr_machine_2_5_class_options(mc); 5292 smc->dr_lmb_enabled = false; 5293 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 5294 } 5295 5296 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 5297 5298 /* 5299 * pseries-2.3 5300 */ 5301 5302 static void spapr_machine_2_3_class_options(MachineClass *mc) 5303 { 5304 static GlobalProperty compat[] = { 5305 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 5306 }; 5307 spapr_machine_2_4_class_options(mc); 5308 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 5309 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5310 } 5311 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 5312 5313 /* 5314 * pseries-2.2 5315 */ 5316 5317 static void spapr_machine_2_2_class_options(MachineClass *mc) 5318 { 5319 static GlobalProperty compat[] = { 5320 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 5321 }; 5322 5323 spapr_machine_2_3_class_options(mc); 5324 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 5325 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5326 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 5327 } 5328 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 5329 5330 /* 5331 * pseries-2.1 5332 */ 5333 5334 static void spapr_machine_2_1_class_options(MachineClass *mc) 5335 { 5336 spapr_machine_2_2_class_options(mc); 5337 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 5338 } 5339 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 5340 5341 static void spapr_machine_register_types(void) 5342 { 5343 type_register_static(&spapr_machine_info); 5344 } 5345 5346 type_init(spapr_machine_register_types) 5347