1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qapi/error.h" 30 #include "qapi/visitor.h" 31 #include "sysemu/sysemu.h" 32 #include "sysemu/hostmem.h" 33 #include "sysemu/numa.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/reset.h" 36 #include "sysemu/runstate.h" 37 #include "qemu/log.h" 38 #include "hw/fw-path-provider.h" 39 #include "elf.h" 40 #include "net/net.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/cpus.h" 43 #include "sysemu/hw_accel.h" 44 #include "kvm_ppc.h" 45 #include "migration/misc.h" 46 #include "migration/qemu-file-types.h" 47 #include "migration/global_state.h" 48 #include "migration/register.h" 49 #include "migration/blocker.h" 50 #include "mmu-hash64.h" 51 #include "mmu-book3s-v3.h" 52 #include "cpu-models.h" 53 #include "hw/core/cpu.h" 54 55 #include "hw/boards.h" 56 #include "hw/ppc/ppc.h" 57 #include "hw/loader.h" 58 59 #include "hw/ppc/fdt.h" 60 #include "hw/ppc/spapr.h" 61 #include "hw/ppc/spapr_vio.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/pci-host/spapr.h" 64 #include "hw/pci/msi.h" 65 66 #include "hw/pci/pci.h" 67 #include "hw/scsi/scsi.h" 68 #include "hw/virtio/virtio-scsi.h" 69 #include "hw/virtio/vhost-scsi-common.h" 70 71 #include "exec/address-spaces.h" 72 #include "exec/ram_addr.h" 73 #include "hw/usb.h" 74 #include "qemu/config-file.h" 75 #include "qemu/error-report.h" 76 #include "trace.h" 77 #include "hw/nmi.h" 78 #include "hw/intc/intc.h" 79 80 #include "hw/ppc/spapr_cpu_core.h" 81 #include "hw/mem/memory-device.h" 82 #include "hw/ppc/spapr_tpm_proxy.h" 83 #include "hw/ppc/spapr_nvdimm.h" 84 #include "hw/ppc/spapr_numa.h" 85 86 #include "monitor/monitor.h" 87 88 #include <libfdt.h> 89 90 /* SLOF memory layout: 91 * 92 * SLOF raw image loaded at 0, copies its romfs right below the flat 93 * device-tree, then position SLOF itself 31M below that 94 * 95 * So we set FW_OVERHEAD to 40MB which should account for all of that 96 * and more 97 * 98 * We load our kernel at 4M, leaving space for SLOF initial image 99 */ 100 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 101 #define FW_MAX_SIZE 0x400000 102 #define FW_FILE_NAME "slof.bin" 103 #define FW_OVERHEAD 0x2800000 104 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 105 106 #define MIN_RMA_SLOF (128 * MiB) 107 108 #define PHANDLE_INTC 0x00001111 109 110 /* These two functions implement the VCPU id numbering: one to compute them 111 * all and one to identify thread 0 of a VCORE. Any change to the first one 112 * is likely to have an impact on the second one, so let's keep them close. 113 */ 114 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 115 { 116 MachineState *ms = MACHINE(spapr); 117 unsigned int smp_threads = ms->smp.threads; 118 119 assert(spapr->vsmt); 120 return 121 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 122 } 123 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 124 PowerPCCPU *cpu) 125 { 126 assert(spapr->vsmt); 127 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 128 } 129 130 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 131 { 132 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 133 * and newer QEMUs don't even have them. In both cases, we don't want 134 * to send anything on the wire. 135 */ 136 return false; 137 } 138 139 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 140 .name = "icp/server", 141 .version_id = 1, 142 .minimum_version_id = 1, 143 .needed = pre_2_10_vmstate_dummy_icp_needed, 144 .fields = (VMStateField[]) { 145 VMSTATE_UNUSED(4), /* uint32_t xirr */ 146 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 147 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 148 VMSTATE_END_OF_LIST() 149 }, 150 }; 151 152 static void pre_2_10_vmstate_register_dummy_icp(int i) 153 { 154 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 155 (void *)(uintptr_t) i); 156 } 157 158 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 159 { 160 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 161 (void *)(uintptr_t) i); 162 } 163 164 int spapr_max_server_number(SpaprMachineState *spapr) 165 { 166 MachineState *ms = MACHINE(spapr); 167 168 assert(spapr->vsmt); 169 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 170 } 171 172 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 173 int smt_threads) 174 { 175 int i, ret = 0; 176 uint32_t servers_prop[smt_threads]; 177 uint32_t gservers_prop[smt_threads * 2]; 178 int index = spapr_get_vcpu_id(cpu); 179 180 if (cpu->compat_pvr) { 181 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 182 if (ret < 0) { 183 return ret; 184 } 185 } 186 187 /* Build interrupt servers and gservers properties */ 188 for (i = 0; i < smt_threads; i++) { 189 servers_prop[i] = cpu_to_be32(index + i); 190 /* Hack, direct the group queues back to cpu 0 */ 191 gservers_prop[i*2] = cpu_to_be32(index + i); 192 gservers_prop[i*2 + 1] = 0; 193 } 194 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 195 servers_prop, sizeof(servers_prop)); 196 if (ret < 0) { 197 return ret; 198 } 199 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 200 gservers_prop, sizeof(gservers_prop)); 201 202 return ret; 203 } 204 205 static void spapr_dt_pa_features(SpaprMachineState *spapr, 206 PowerPCCPU *cpu, 207 void *fdt, int offset) 208 { 209 uint8_t pa_features_206[] = { 6, 0, 210 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 211 uint8_t pa_features_207[] = { 24, 0, 212 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 213 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 214 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 215 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 216 uint8_t pa_features_300[] = { 66, 0, 217 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 218 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 219 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 220 /* 6: DS207 */ 221 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 222 /* 16: Vector */ 223 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 224 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 225 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 226 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 227 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 228 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 229 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 230 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 231 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 232 /* 42: PM, 44: PC RA, 46: SC vec'd */ 233 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 234 /* 48: SIMD, 50: QP BFP, 52: String */ 235 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 236 /* 54: DecFP, 56: DecI, 58: SHA */ 237 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 238 /* 60: NM atomic, 62: RNG */ 239 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 240 }; 241 uint8_t *pa_features = NULL; 242 size_t pa_size; 243 244 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 245 pa_features = pa_features_206; 246 pa_size = sizeof(pa_features_206); 247 } 248 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 249 pa_features = pa_features_207; 250 pa_size = sizeof(pa_features_207); 251 } 252 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 253 pa_features = pa_features_300; 254 pa_size = sizeof(pa_features_300); 255 } 256 if (!pa_features) { 257 return; 258 } 259 260 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 261 /* 262 * Note: we keep CI large pages off by default because a 64K capable 263 * guest provisioned with large pages might otherwise try to map a qemu 264 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 265 * even if that qemu runs on a 4k host. 266 * We dd this bit back here if we are confident this is not an issue 267 */ 268 pa_features[3] |= 0x20; 269 } 270 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 271 pa_features[24] |= 0x80; /* Transactional memory support */ 272 } 273 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 274 /* Workaround for broken kernels that attempt (guest) radix 275 * mode when they can't handle it, if they see the radix bit set 276 * in pa-features. So hide it from them. */ 277 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 278 } 279 280 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 281 } 282 283 static hwaddr spapr_node0_size(MachineState *machine) 284 { 285 if (machine->numa_state->num_nodes) { 286 int i; 287 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 288 if (machine->numa_state->nodes[i].node_mem) { 289 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 290 machine->ram_size); 291 } 292 } 293 } 294 return machine->ram_size; 295 } 296 297 bool spapr_machine_using_legacy_numa(SpaprMachineState *spapr) 298 { 299 MachineState *machine = MACHINE(spapr); 300 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 301 302 return smc->pre_5_2_numa_associativity || 303 machine->numa_state->num_nodes <= 1; 304 } 305 306 static void add_str(GString *s, const gchar *s1) 307 { 308 g_string_append_len(s, s1, strlen(s1) + 1); 309 } 310 311 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 312 hwaddr start, hwaddr size) 313 { 314 char mem_name[32]; 315 uint64_t mem_reg_property[2]; 316 int off; 317 318 mem_reg_property[0] = cpu_to_be64(start); 319 mem_reg_property[1] = cpu_to_be64(size); 320 321 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 322 off = fdt_add_subnode(fdt, 0, mem_name); 323 _FDT(off); 324 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 325 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 326 sizeof(mem_reg_property)))); 327 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 328 return off; 329 } 330 331 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 332 { 333 MemoryDeviceInfoList *info; 334 335 for (info = list; info; info = info->next) { 336 MemoryDeviceInfo *value = info->value; 337 338 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 339 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 340 341 if (addr >= pcdimm_info->addr && 342 addr < (pcdimm_info->addr + pcdimm_info->size)) { 343 return pcdimm_info->node; 344 } 345 } 346 } 347 348 return -1; 349 } 350 351 struct sPAPRDrconfCellV2 { 352 uint32_t seq_lmbs; 353 uint64_t base_addr; 354 uint32_t drc_index; 355 uint32_t aa_index; 356 uint32_t flags; 357 } QEMU_PACKED; 358 359 typedef struct DrconfCellQueue { 360 struct sPAPRDrconfCellV2 cell; 361 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 362 } DrconfCellQueue; 363 364 static DrconfCellQueue * 365 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 366 uint32_t drc_index, uint32_t aa_index, 367 uint32_t flags) 368 { 369 DrconfCellQueue *elem; 370 371 elem = g_malloc0(sizeof(*elem)); 372 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 373 elem->cell.base_addr = cpu_to_be64(base_addr); 374 elem->cell.drc_index = cpu_to_be32(drc_index); 375 elem->cell.aa_index = cpu_to_be32(aa_index); 376 elem->cell.flags = cpu_to_be32(flags); 377 378 return elem; 379 } 380 381 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 382 int offset, MemoryDeviceInfoList *dimms) 383 { 384 MachineState *machine = MACHINE(spapr); 385 uint8_t *int_buf, *cur_index; 386 int ret; 387 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 388 uint64_t addr, cur_addr, size; 389 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 390 uint64_t mem_end = machine->device_memory->base + 391 memory_region_size(&machine->device_memory->mr); 392 uint32_t node, buf_len, nr_entries = 0; 393 SpaprDrc *drc; 394 DrconfCellQueue *elem, *next; 395 MemoryDeviceInfoList *info; 396 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 397 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 398 399 /* Entry to cover RAM and the gap area */ 400 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 401 SPAPR_LMB_FLAGS_RESERVED | 402 SPAPR_LMB_FLAGS_DRC_INVALID); 403 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 404 nr_entries++; 405 406 cur_addr = machine->device_memory->base; 407 for (info = dimms; info; info = info->next) { 408 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 409 410 addr = di->addr; 411 size = di->size; 412 node = di->node; 413 414 /* 415 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 416 * area is marked hotpluggable in the next iteration for the bigger 417 * chunk including the NVDIMM occupied area. 418 */ 419 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 420 continue; 421 422 /* Entry for hot-pluggable area */ 423 if (cur_addr < addr) { 424 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 425 g_assert(drc); 426 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 427 cur_addr, spapr_drc_index(drc), -1, 0); 428 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 429 nr_entries++; 430 } 431 432 /* Entry for DIMM */ 433 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 434 g_assert(drc); 435 elem = spapr_get_drconf_cell(size / lmb_size, addr, 436 spapr_drc_index(drc), node, 437 (SPAPR_LMB_FLAGS_ASSIGNED | 438 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 439 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 440 nr_entries++; 441 cur_addr = addr + size; 442 } 443 444 /* Entry for remaining hotpluggable area */ 445 if (cur_addr < mem_end) { 446 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 447 g_assert(drc); 448 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 449 cur_addr, spapr_drc_index(drc), -1, 0); 450 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 451 nr_entries++; 452 } 453 454 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 455 int_buf = cur_index = g_malloc0(buf_len); 456 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 457 cur_index += sizeof(nr_entries); 458 459 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 460 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 461 cur_index += sizeof(elem->cell); 462 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 463 g_free(elem); 464 } 465 466 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 467 g_free(int_buf); 468 if (ret < 0) { 469 return -1; 470 } 471 return 0; 472 } 473 474 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 475 int offset, MemoryDeviceInfoList *dimms) 476 { 477 MachineState *machine = MACHINE(spapr); 478 int i, ret; 479 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 480 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 481 uint32_t nr_lmbs = (machine->device_memory->base + 482 memory_region_size(&machine->device_memory->mr)) / 483 lmb_size; 484 uint32_t *int_buf, *cur_index, buf_len; 485 486 /* 487 * Allocate enough buffer size to fit in ibm,dynamic-memory 488 */ 489 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 490 cur_index = int_buf = g_malloc0(buf_len); 491 int_buf[0] = cpu_to_be32(nr_lmbs); 492 cur_index++; 493 for (i = 0; i < nr_lmbs; i++) { 494 uint64_t addr = i * lmb_size; 495 uint32_t *dynamic_memory = cur_index; 496 497 if (i >= device_lmb_start) { 498 SpaprDrc *drc; 499 500 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 501 g_assert(drc); 502 503 dynamic_memory[0] = cpu_to_be32(addr >> 32); 504 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 505 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 506 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 507 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 508 if (memory_region_present(get_system_memory(), addr)) { 509 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 510 } else { 511 dynamic_memory[5] = cpu_to_be32(0); 512 } 513 } else { 514 /* 515 * LMB information for RMA, boot time RAM and gap b/n RAM and 516 * device memory region -- all these are marked as reserved 517 * and as having no valid DRC. 518 */ 519 dynamic_memory[0] = cpu_to_be32(addr >> 32); 520 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 521 dynamic_memory[2] = cpu_to_be32(0); 522 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 523 dynamic_memory[4] = cpu_to_be32(-1); 524 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 525 SPAPR_LMB_FLAGS_DRC_INVALID); 526 } 527 528 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 529 } 530 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 531 g_free(int_buf); 532 if (ret < 0) { 533 return -1; 534 } 535 return 0; 536 } 537 538 /* 539 * Adds ibm,dynamic-reconfiguration-memory node. 540 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 541 * of this device tree node. 542 */ 543 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 544 void *fdt) 545 { 546 MachineState *machine = MACHINE(spapr); 547 int ret, offset; 548 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 549 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 550 cpu_to_be32(lmb_size & 0xffffffff)}; 551 MemoryDeviceInfoList *dimms = NULL; 552 553 /* 554 * Don't create the node if there is no device memory 555 */ 556 if (machine->ram_size == machine->maxram_size) { 557 return 0; 558 } 559 560 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 561 562 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 563 sizeof(prop_lmb_size)); 564 if (ret < 0) { 565 return ret; 566 } 567 568 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 569 if (ret < 0) { 570 return ret; 571 } 572 573 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 574 if (ret < 0) { 575 return ret; 576 } 577 578 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 579 dimms = qmp_memory_device_list(); 580 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 581 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 582 } else { 583 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 584 } 585 qapi_free_MemoryDeviceInfoList(dimms); 586 587 if (ret < 0) { 588 return ret; 589 } 590 591 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 592 593 return ret; 594 } 595 596 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 597 { 598 MachineState *machine = MACHINE(spapr); 599 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 600 hwaddr mem_start, node_size; 601 int i, nb_nodes = machine->numa_state->num_nodes; 602 NodeInfo *nodes = machine->numa_state->nodes; 603 604 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 605 if (!nodes[i].node_mem) { 606 continue; 607 } 608 if (mem_start >= machine->ram_size) { 609 node_size = 0; 610 } else { 611 node_size = nodes[i].node_mem; 612 if (node_size > machine->ram_size - mem_start) { 613 node_size = machine->ram_size - mem_start; 614 } 615 } 616 if (!mem_start) { 617 /* spapr_machine_init() checks for rma_size <= node0_size 618 * already */ 619 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 620 mem_start += spapr->rma_size; 621 node_size -= spapr->rma_size; 622 } 623 for ( ; node_size; ) { 624 hwaddr sizetmp = pow2floor(node_size); 625 626 /* mem_start != 0 here */ 627 if (ctzl(mem_start) < ctzl(sizetmp)) { 628 sizetmp = 1ULL << ctzl(mem_start); 629 } 630 631 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 632 node_size -= sizetmp; 633 mem_start += sizetmp; 634 } 635 } 636 637 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 638 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 639 int ret; 640 641 g_assert(smc->dr_lmb_enabled); 642 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 643 if (ret) { 644 return ret; 645 } 646 } 647 648 return 0; 649 } 650 651 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 652 SpaprMachineState *spapr) 653 { 654 MachineState *ms = MACHINE(spapr); 655 PowerPCCPU *cpu = POWERPC_CPU(cs); 656 CPUPPCState *env = &cpu->env; 657 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 658 int index = spapr_get_vcpu_id(cpu); 659 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 660 0xffffffff, 0xffffffff}; 661 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 662 : SPAPR_TIMEBASE_FREQ; 663 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 664 uint32_t page_sizes_prop[64]; 665 size_t page_sizes_prop_size; 666 unsigned int smp_threads = ms->smp.threads; 667 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 668 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 669 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 670 SpaprDrc *drc; 671 int drc_index; 672 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 673 int i; 674 675 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 676 if (drc) { 677 drc_index = spapr_drc_index(drc); 678 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 679 } 680 681 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 682 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 683 684 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 685 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 686 env->dcache_line_size))); 687 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 688 env->dcache_line_size))); 689 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 690 env->icache_line_size))); 691 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 692 env->icache_line_size))); 693 694 if (pcc->l1_dcache_size) { 695 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 696 pcc->l1_dcache_size))); 697 } else { 698 warn_report("Unknown L1 dcache size for cpu"); 699 } 700 if (pcc->l1_icache_size) { 701 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 702 pcc->l1_icache_size))); 703 } else { 704 warn_report("Unknown L1 icache size for cpu"); 705 } 706 707 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 708 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 709 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 710 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 711 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 712 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 713 714 if (env->spr_cb[SPR_PURR].oea_read) { 715 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 716 } 717 if (env->spr_cb[SPR_SPURR].oea_read) { 718 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 719 } 720 721 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 722 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 723 segs, sizeof(segs)))); 724 } 725 726 /* Advertise VSX (vector extensions) if available 727 * 1 == VMX / Altivec available 728 * 2 == VSX available 729 * 730 * Only CPUs for which we create core types in spapr_cpu_core.c 731 * are possible, and all of those have VMX */ 732 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 733 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 734 } else { 735 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 736 } 737 738 /* Advertise DFP (Decimal Floating Point) if available 739 * 0 / no property == no DFP 740 * 1 == DFP available */ 741 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 742 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 743 } 744 745 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 746 sizeof(page_sizes_prop)); 747 if (page_sizes_prop_size) { 748 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 749 page_sizes_prop, page_sizes_prop_size))); 750 } 751 752 spapr_dt_pa_features(spapr, cpu, fdt, offset); 753 754 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 755 cs->cpu_index / vcpus_per_socket))); 756 757 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 758 pft_size_prop, sizeof(pft_size_prop)))); 759 760 if (ms->numa_state->num_nodes > 1) { 761 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 762 } 763 764 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 765 766 if (pcc->radix_page_info) { 767 for (i = 0; i < pcc->radix_page_info->count; i++) { 768 radix_AP_encodings[i] = 769 cpu_to_be32(pcc->radix_page_info->entries[i]); 770 } 771 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 772 radix_AP_encodings, 773 pcc->radix_page_info->count * 774 sizeof(radix_AP_encodings[0])))); 775 } 776 777 /* 778 * We set this property to let the guest know that it can use the large 779 * decrementer and its width in bits. 780 */ 781 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 782 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 783 pcc->lrg_decr_bits))); 784 } 785 786 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 787 { 788 CPUState **rev; 789 CPUState *cs; 790 int n_cpus; 791 int cpus_offset; 792 char *nodename; 793 int i; 794 795 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 796 _FDT(cpus_offset); 797 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 798 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 799 800 /* 801 * We walk the CPUs in reverse order to ensure that CPU DT nodes 802 * created by fdt_add_subnode() end up in the right order in FDT 803 * for the guest kernel the enumerate the CPUs correctly. 804 * 805 * The CPU list cannot be traversed in reverse order, so we need 806 * to do extra work. 807 */ 808 n_cpus = 0; 809 rev = NULL; 810 CPU_FOREACH(cs) { 811 rev = g_renew(CPUState *, rev, n_cpus + 1); 812 rev[n_cpus++] = cs; 813 } 814 815 for (i = n_cpus - 1; i >= 0; i--) { 816 CPUState *cs = rev[i]; 817 PowerPCCPU *cpu = POWERPC_CPU(cs); 818 int index = spapr_get_vcpu_id(cpu); 819 DeviceClass *dc = DEVICE_GET_CLASS(cs); 820 int offset; 821 822 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 823 continue; 824 } 825 826 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 827 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 828 g_free(nodename); 829 _FDT(offset); 830 spapr_dt_cpu(cs, fdt, offset, spapr); 831 } 832 833 g_free(rev); 834 } 835 836 static int spapr_dt_rng(void *fdt) 837 { 838 int node; 839 int ret; 840 841 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 842 if (node <= 0) { 843 return -1; 844 } 845 ret = fdt_setprop_string(fdt, node, "device_type", 846 "ibm,platform-facilities"); 847 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 848 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 849 850 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 851 if (node <= 0) { 852 return -1; 853 } 854 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 855 856 return ret ? -1 : 0; 857 } 858 859 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 860 { 861 MachineState *ms = MACHINE(spapr); 862 int rtas; 863 GString *hypertas = g_string_sized_new(256); 864 GString *qemu_hypertas = g_string_sized_new(256); 865 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 866 memory_region_size(&MACHINE(spapr)->device_memory->mr); 867 uint32_t lrdr_capacity[] = { 868 cpu_to_be32(max_device_addr >> 32), 869 cpu_to_be32(max_device_addr & 0xffffffff), 870 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 871 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 872 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 873 }; 874 875 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 876 877 /* hypertas */ 878 add_str(hypertas, "hcall-pft"); 879 add_str(hypertas, "hcall-term"); 880 add_str(hypertas, "hcall-dabr"); 881 add_str(hypertas, "hcall-interrupt"); 882 add_str(hypertas, "hcall-tce"); 883 add_str(hypertas, "hcall-vio"); 884 add_str(hypertas, "hcall-splpar"); 885 add_str(hypertas, "hcall-join"); 886 add_str(hypertas, "hcall-bulk"); 887 add_str(hypertas, "hcall-set-mode"); 888 add_str(hypertas, "hcall-sprg0"); 889 add_str(hypertas, "hcall-copy"); 890 add_str(hypertas, "hcall-debug"); 891 add_str(hypertas, "hcall-vphn"); 892 add_str(qemu_hypertas, "hcall-memop1"); 893 894 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 895 add_str(hypertas, "hcall-multi-tce"); 896 } 897 898 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 899 add_str(hypertas, "hcall-hpt-resize"); 900 } 901 902 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 903 hypertas->str, hypertas->len)); 904 g_string_free(hypertas, TRUE); 905 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 906 qemu_hypertas->str, qemu_hypertas->len)); 907 g_string_free(qemu_hypertas, TRUE); 908 909 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 910 911 /* 912 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 913 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 914 * 915 * The system reset requirements are driven by existing Linux and PowerVM 916 * implementation which (contrary to PAPR) saves r3 in the error log 917 * structure like machine check, so Linux expects to find the saved r3 918 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 919 * does not look at the error value). 920 * 921 * System reset interrupts are not subject to interlock like machine 922 * check, so this memory area could be corrupted if the sreset is 923 * interrupted by a machine check (or vice versa) if it was shared. To 924 * prevent this, system reset uses per-CPU areas for the sreset save 925 * area. A system reset that interrupts a system reset handler could 926 * still overwrite this area, but Linux doesn't try to recover in that 927 * case anyway. 928 * 929 * The extra 8 bytes is required because Linux's FWNMI error log check 930 * is off-by-one. 931 */ 932 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_ERROR_LOG_MAX + 933 ms->smp.max_cpus * sizeof(uint64_t)*2 + sizeof(uint64_t))); 934 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 935 RTAS_ERROR_LOG_MAX)); 936 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 937 RTAS_EVENT_SCAN_RATE)); 938 939 g_assert(msi_nonbroken); 940 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 941 942 /* 943 * According to PAPR, rtas ibm,os-term does not guarantee a return 944 * back to the guest cpu. 945 * 946 * While an additional ibm,extended-os-term property indicates 947 * that rtas call return will always occur. Set this property. 948 */ 949 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 950 951 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 952 lrdr_capacity, sizeof(lrdr_capacity))); 953 954 spapr_dt_rtas_tokens(fdt, rtas); 955 } 956 957 /* 958 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 959 * and the XIVE features that the guest may request and thus the valid 960 * values for bytes 23..26 of option vector 5: 961 */ 962 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 963 int chosen) 964 { 965 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 966 967 char val[2 * 4] = { 968 23, 0x00, /* XICS / XIVE mode */ 969 24, 0x00, /* Hash/Radix, filled in below. */ 970 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 971 26, 0x40, /* Radix options: GTSE == yes. */ 972 }; 973 974 if (spapr->irq->xics && spapr->irq->xive) { 975 val[1] = SPAPR_OV5_XIVE_BOTH; 976 } else if (spapr->irq->xive) { 977 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 978 } else { 979 assert(spapr->irq->xics); 980 val[1] = SPAPR_OV5_XIVE_LEGACY; 981 } 982 983 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 984 first_ppc_cpu->compat_pvr)) { 985 /* 986 * If we're in a pre POWER9 compat mode then the guest should 987 * do hash and use the legacy interrupt mode 988 */ 989 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 990 val[3] = 0x00; /* Hash */ 991 } else if (kvm_enabled()) { 992 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 993 val[3] = 0x80; /* OV5_MMU_BOTH */ 994 } else if (kvmppc_has_cap_mmu_radix()) { 995 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 996 } else { 997 val[3] = 0x00; /* Hash */ 998 } 999 } else { 1000 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1001 val[3] = 0xC0; 1002 } 1003 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1004 val, sizeof(val))); 1005 } 1006 1007 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1008 { 1009 MachineState *machine = MACHINE(spapr); 1010 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1011 int chosen; 1012 1013 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1014 1015 if (reset) { 1016 const char *boot_device = machine->boot_order; 1017 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1018 size_t cb = 0; 1019 char *bootlist = get_boot_devices_list(&cb); 1020 1021 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1022 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1023 machine->kernel_cmdline)); 1024 } 1025 1026 if (spapr->initrd_size) { 1027 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1028 spapr->initrd_base)); 1029 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1030 spapr->initrd_base + spapr->initrd_size)); 1031 } 1032 1033 if (spapr->kernel_size) { 1034 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1035 cpu_to_be64(spapr->kernel_size) }; 1036 1037 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1038 &kprop, sizeof(kprop))); 1039 if (spapr->kernel_le) { 1040 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1041 } 1042 } 1043 if (boot_menu) { 1044 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1045 } 1046 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1047 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1048 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1049 1050 if (cb && bootlist) { 1051 int i; 1052 1053 for (i = 0; i < cb; i++) { 1054 if (bootlist[i] == '\n') { 1055 bootlist[i] = ' '; 1056 } 1057 } 1058 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1059 } 1060 1061 if (boot_device && strlen(boot_device)) { 1062 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1063 } 1064 1065 if (!spapr->has_graphics && stdout_path) { 1066 /* 1067 * "linux,stdout-path" and "stdout" properties are 1068 * deprecated by linux kernel. New platforms should only 1069 * use the "stdout-path" property. Set the new property 1070 * and continue using older property to remain compatible 1071 * with the existing firmware. 1072 */ 1073 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1074 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1075 } 1076 1077 /* 1078 * We can deal with BAR reallocation just fine, advertise it 1079 * to the guest 1080 */ 1081 if (smc->linux_pci_probe) { 1082 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1083 } 1084 1085 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1086 1087 g_free(stdout_path); 1088 g_free(bootlist); 1089 } 1090 1091 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1092 } 1093 1094 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1095 { 1096 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1097 * KVM to work under pHyp with some guest co-operation */ 1098 int hypervisor; 1099 uint8_t hypercall[16]; 1100 1101 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1102 /* indicate KVM hypercall interface */ 1103 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1104 if (kvmppc_has_cap_fixup_hcalls()) { 1105 /* 1106 * Older KVM versions with older guest kernels were broken 1107 * with the magic page, don't allow the guest to map it. 1108 */ 1109 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1110 sizeof(hypercall))) { 1111 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1112 hypercall, sizeof(hypercall))); 1113 } 1114 } 1115 } 1116 1117 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1118 { 1119 MachineState *machine = MACHINE(spapr); 1120 MachineClass *mc = MACHINE_GET_CLASS(machine); 1121 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1122 int ret; 1123 void *fdt; 1124 SpaprPhbState *phb; 1125 char *buf; 1126 1127 fdt = g_malloc0(space); 1128 _FDT((fdt_create_empty_tree(fdt, space))); 1129 1130 /* Root node */ 1131 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1132 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1133 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1134 1135 /* Guest UUID & Name*/ 1136 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1137 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1138 if (qemu_uuid_set) { 1139 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1140 } 1141 g_free(buf); 1142 1143 if (qemu_get_vm_name()) { 1144 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1145 qemu_get_vm_name())); 1146 } 1147 1148 /* Host Model & Serial Number */ 1149 if (spapr->host_model) { 1150 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1151 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1152 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1153 g_free(buf); 1154 } 1155 1156 if (spapr->host_serial) { 1157 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1158 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1159 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1160 g_free(buf); 1161 } 1162 1163 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1164 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1165 1166 /* /interrupt controller */ 1167 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1168 1169 ret = spapr_dt_memory(spapr, fdt); 1170 if (ret < 0) { 1171 error_report("couldn't setup memory nodes in fdt"); 1172 exit(1); 1173 } 1174 1175 /* /vdevice */ 1176 spapr_dt_vdevice(spapr->vio_bus, fdt); 1177 1178 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1179 ret = spapr_dt_rng(fdt); 1180 if (ret < 0) { 1181 error_report("could not set up rng device in the fdt"); 1182 exit(1); 1183 } 1184 } 1185 1186 QLIST_FOREACH(phb, &spapr->phbs, list) { 1187 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1188 if (ret < 0) { 1189 error_report("couldn't setup PCI devices in fdt"); 1190 exit(1); 1191 } 1192 } 1193 1194 spapr_dt_cpus(fdt, spapr); 1195 1196 if (smc->dr_lmb_enabled) { 1197 _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1198 } 1199 1200 if (mc->has_hotpluggable_cpus) { 1201 int offset = fdt_path_offset(fdt, "/cpus"); 1202 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1203 if (ret < 0) { 1204 error_report("Couldn't set up CPU DR device tree properties"); 1205 exit(1); 1206 } 1207 } 1208 1209 /* /event-sources */ 1210 spapr_dt_events(spapr, fdt); 1211 1212 /* /rtas */ 1213 spapr_dt_rtas(spapr, fdt); 1214 1215 /* /chosen */ 1216 spapr_dt_chosen(spapr, fdt, reset); 1217 1218 /* /hypervisor */ 1219 if (kvm_enabled()) { 1220 spapr_dt_hypervisor(spapr, fdt); 1221 } 1222 1223 /* Build memory reserve map */ 1224 if (reset) { 1225 if (spapr->kernel_size) { 1226 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1227 spapr->kernel_size))); 1228 } 1229 if (spapr->initrd_size) { 1230 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1231 spapr->initrd_size))); 1232 } 1233 } 1234 1235 if (smc->dr_phb_enabled) { 1236 ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB); 1237 if (ret < 0) { 1238 error_report("Couldn't set up PHB DR device tree properties"); 1239 exit(1); 1240 } 1241 } 1242 1243 /* NVDIMM devices */ 1244 if (mc->nvdimm_supported) { 1245 spapr_dt_persistent_memory(spapr, fdt); 1246 } 1247 1248 return fdt; 1249 } 1250 1251 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1252 { 1253 SpaprMachineState *spapr = opaque; 1254 1255 return (addr & 0x0fffffff) + spapr->kernel_addr; 1256 } 1257 1258 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1259 PowerPCCPU *cpu) 1260 { 1261 CPUPPCState *env = &cpu->env; 1262 1263 /* The TCG path should also be holding the BQL at this point */ 1264 g_assert(qemu_mutex_iothread_locked()); 1265 1266 if (msr_pr) { 1267 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1268 env->gpr[3] = H_PRIVILEGE; 1269 } else { 1270 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1271 } 1272 } 1273 1274 struct LPCRSyncState { 1275 target_ulong value; 1276 target_ulong mask; 1277 }; 1278 1279 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1280 { 1281 struct LPCRSyncState *s = arg.host_ptr; 1282 PowerPCCPU *cpu = POWERPC_CPU(cs); 1283 CPUPPCState *env = &cpu->env; 1284 target_ulong lpcr; 1285 1286 cpu_synchronize_state(cs); 1287 lpcr = env->spr[SPR_LPCR]; 1288 lpcr &= ~s->mask; 1289 lpcr |= s->value; 1290 ppc_store_lpcr(cpu, lpcr); 1291 } 1292 1293 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1294 { 1295 CPUState *cs; 1296 struct LPCRSyncState s = { 1297 .value = value, 1298 .mask = mask 1299 }; 1300 CPU_FOREACH(cs) { 1301 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1302 } 1303 } 1304 1305 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1306 { 1307 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1308 1309 /* Copy PATE1:GR into PATE0:HR */ 1310 entry->dw0 = spapr->patb_entry & PATE0_HR; 1311 entry->dw1 = spapr->patb_entry; 1312 } 1313 1314 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1315 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1316 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1317 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1318 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1319 1320 /* 1321 * Get the fd to access the kernel htab, re-opening it if necessary 1322 */ 1323 static int get_htab_fd(SpaprMachineState *spapr) 1324 { 1325 Error *local_err = NULL; 1326 1327 if (spapr->htab_fd >= 0) { 1328 return spapr->htab_fd; 1329 } 1330 1331 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1332 if (spapr->htab_fd < 0) { 1333 error_report_err(local_err); 1334 } 1335 1336 return spapr->htab_fd; 1337 } 1338 1339 void close_htab_fd(SpaprMachineState *spapr) 1340 { 1341 if (spapr->htab_fd >= 0) { 1342 close(spapr->htab_fd); 1343 } 1344 spapr->htab_fd = -1; 1345 } 1346 1347 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1348 { 1349 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1350 1351 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1352 } 1353 1354 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1355 { 1356 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1357 1358 assert(kvm_enabled()); 1359 1360 if (!spapr->htab) { 1361 return 0; 1362 } 1363 1364 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1365 } 1366 1367 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1368 hwaddr ptex, int n) 1369 { 1370 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1371 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1372 1373 if (!spapr->htab) { 1374 /* 1375 * HTAB is controlled by KVM. Fetch into temporary buffer 1376 */ 1377 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1378 kvmppc_read_hptes(hptes, ptex, n); 1379 return hptes; 1380 } 1381 1382 /* 1383 * HTAB is controlled by QEMU. Just point to the internally 1384 * accessible PTEG. 1385 */ 1386 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1387 } 1388 1389 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1390 const ppc_hash_pte64_t *hptes, 1391 hwaddr ptex, int n) 1392 { 1393 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1394 1395 if (!spapr->htab) { 1396 g_free((void *)hptes); 1397 } 1398 1399 /* Nothing to do for qemu managed HPT */ 1400 } 1401 1402 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1403 uint64_t pte0, uint64_t pte1) 1404 { 1405 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1406 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1407 1408 if (!spapr->htab) { 1409 kvmppc_write_hpte(ptex, pte0, pte1); 1410 } else { 1411 if (pte0 & HPTE64_V_VALID) { 1412 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1413 /* 1414 * When setting valid, we write PTE1 first. This ensures 1415 * proper synchronization with the reading code in 1416 * ppc_hash64_pteg_search() 1417 */ 1418 smp_wmb(); 1419 stq_p(spapr->htab + offset, pte0); 1420 } else { 1421 stq_p(spapr->htab + offset, pte0); 1422 /* 1423 * When clearing it we set PTE0 first. This ensures proper 1424 * synchronization with the reading code in 1425 * ppc_hash64_pteg_search() 1426 */ 1427 smp_wmb(); 1428 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1429 } 1430 } 1431 } 1432 1433 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1434 uint64_t pte1) 1435 { 1436 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1437 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1438 1439 if (!spapr->htab) { 1440 /* There should always be a hash table when this is called */ 1441 error_report("spapr_hpte_set_c called with no hash table !"); 1442 return; 1443 } 1444 1445 /* The HW performs a non-atomic byte update */ 1446 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1447 } 1448 1449 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1450 uint64_t pte1) 1451 { 1452 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1453 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1454 1455 if (!spapr->htab) { 1456 /* There should always be a hash table when this is called */ 1457 error_report("spapr_hpte_set_r called with no hash table !"); 1458 return; 1459 } 1460 1461 /* The HW performs a non-atomic byte update */ 1462 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1463 } 1464 1465 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1466 { 1467 int shift; 1468 1469 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1470 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1471 * that's much more than is needed for Linux guests */ 1472 shift = ctz64(pow2ceil(ramsize)) - 7; 1473 shift = MAX(shift, 18); /* Minimum architected size */ 1474 shift = MIN(shift, 46); /* Maximum architected size */ 1475 return shift; 1476 } 1477 1478 void spapr_free_hpt(SpaprMachineState *spapr) 1479 { 1480 g_free(spapr->htab); 1481 spapr->htab = NULL; 1482 spapr->htab_shift = 0; 1483 close_htab_fd(spapr); 1484 } 1485 1486 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1487 { 1488 ERRP_GUARD(); 1489 long rc; 1490 1491 /* Clean up any HPT info from a previous boot */ 1492 spapr_free_hpt(spapr); 1493 1494 rc = kvmppc_reset_htab(shift); 1495 1496 if (rc == -EOPNOTSUPP) { 1497 error_setg(errp, "HPT not supported in nested guests"); 1498 return -EOPNOTSUPP; 1499 } 1500 1501 if (rc < 0) { 1502 /* kernel-side HPT needed, but couldn't allocate one */ 1503 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1504 shift); 1505 error_append_hint(errp, "Try smaller maxmem?\n"); 1506 return -errno; 1507 } else if (rc > 0) { 1508 /* kernel-side HPT allocated */ 1509 if (rc != shift) { 1510 error_setg(errp, 1511 "Requested order %d HPT, but kernel allocated order %ld", 1512 shift, rc); 1513 error_append_hint(errp, "Try smaller maxmem?\n"); 1514 return -ENOSPC; 1515 } 1516 1517 spapr->htab_shift = shift; 1518 spapr->htab = NULL; 1519 } else { 1520 /* kernel-side HPT not needed, allocate in userspace instead */ 1521 size_t size = 1ULL << shift; 1522 int i; 1523 1524 spapr->htab = qemu_memalign(size, size); 1525 memset(spapr->htab, 0, size); 1526 spapr->htab_shift = shift; 1527 1528 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1529 DIRTY_HPTE(HPTE(spapr->htab, i)); 1530 } 1531 } 1532 /* We're setting up a hash table, so that means we're not radix */ 1533 spapr->patb_entry = 0; 1534 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1535 return 0; 1536 } 1537 1538 void spapr_setup_hpt(SpaprMachineState *spapr) 1539 { 1540 int hpt_shift; 1541 1542 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1543 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1544 } else { 1545 uint64_t current_ram_size; 1546 1547 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1548 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1549 } 1550 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1551 1552 if (kvm_enabled()) { 1553 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1554 1555 /* Check our RMA fits in the possible VRMA */ 1556 if (vrma_limit < spapr->rma_size) { 1557 error_report("Unable to create %" HWADDR_PRIu 1558 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1559 spapr->rma_size / MiB, vrma_limit / MiB); 1560 exit(EXIT_FAILURE); 1561 } 1562 } 1563 } 1564 1565 static int spapr_reset_drcs(Object *child, void *opaque) 1566 { 1567 SpaprDrc *drc = 1568 (SpaprDrc *) object_dynamic_cast(child, 1569 TYPE_SPAPR_DR_CONNECTOR); 1570 1571 if (drc) { 1572 spapr_drc_reset(drc); 1573 } 1574 1575 return 0; 1576 } 1577 1578 static void spapr_machine_reset(MachineState *machine) 1579 { 1580 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1581 PowerPCCPU *first_ppc_cpu; 1582 hwaddr fdt_addr; 1583 void *fdt; 1584 int rc; 1585 1586 kvmppc_svm_off(&error_fatal); 1587 spapr_caps_apply(spapr); 1588 1589 first_ppc_cpu = POWERPC_CPU(first_cpu); 1590 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1591 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1592 spapr->max_compat_pvr)) { 1593 /* 1594 * If using KVM with radix mode available, VCPUs can be started 1595 * without a HPT because KVM will start them in radix mode. 1596 * Set the GR bit in PATE so that we know there is no HPT. 1597 */ 1598 spapr->patb_entry = PATE1_GR; 1599 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1600 } else { 1601 spapr_setup_hpt(spapr); 1602 } 1603 1604 qemu_devices_reset(); 1605 1606 spapr_ovec_cleanup(spapr->ov5_cas); 1607 spapr->ov5_cas = spapr_ovec_new(); 1608 1609 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1610 1611 /* 1612 * This is fixing some of the default configuration of the XIVE 1613 * devices. To be called after the reset of the machine devices. 1614 */ 1615 spapr_irq_reset(spapr, &error_fatal); 1616 1617 /* 1618 * There is no CAS under qtest. Simulate one to please the code that 1619 * depends on spapr->ov5_cas. This is especially needed to test device 1620 * unplug, so we do that before resetting the DRCs. 1621 */ 1622 if (qtest_enabled()) { 1623 spapr_ovec_cleanup(spapr->ov5_cas); 1624 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1625 } 1626 1627 /* DRC reset may cause a device to be unplugged. This will cause troubles 1628 * if this device is used by another device (eg, a running vhost backend 1629 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1630 * situations, we reset DRCs after all devices have been reset. 1631 */ 1632 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1633 1634 spapr_clear_pending_events(spapr); 1635 1636 /* 1637 * We place the device tree and RTAS just below either the top of the RMA, 1638 * or just below 2GB, whichever is lower, so that it can be 1639 * processed with 32-bit real mode code if necessary 1640 */ 1641 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; 1642 1643 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1644 1645 rc = fdt_pack(fdt); 1646 1647 /* Should only fail if we've built a corrupted tree */ 1648 assert(rc == 0); 1649 1650 /* Load the fdt */ 1651 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1652 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1653 g_free(spapr->fdt_blob); 1654 spapr->fdt_size = fdt_totalsize(fdt); 1655 spapr->fdt_initial_size = spapr->fdt_size; 1656 spapr->fdt_blob = fdt; 1657 1658 /* Set up the entry state */ 1659 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0); 1660 first_ppc_cpu->env.gpr[5] = 0; 1661 1662 spapr->fwnmi_system_reset_addr = -1; 1663 spapr->fwnmi_machine_check_addr = -1; 1664 spapr->fwnmi_machine_check_interlock = -1; 1665 1666 /* Signal all vCPUs waiting on this condition */ 1667 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1668 1669 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1670 } 1671 1672 static void spapr_create_nvram(SpaprMachineState *spapr) 1673 { 1674 DeviceState *dev = qdev_new("spapr-nvram"); 1675 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1676 1677 if (dinfo) { 1678 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1679 &error_fatal); 1680 } 1681 1682 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1683 1684 spapr->nvram = (struct SpaprNvram *)dev; 1685 } 1686 1687 static void spapr_rtc_create(SpaprMachineState *spapr) 1688 { 1689 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1690 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1691 &error_fatal, NULL); 1692 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1693 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1694 "date"); 1695 } 1696 1697 /* Returns whether we want to use VGA or not */ 1698 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1699 { 1700 switch (vga_interface_type) { 1701 case VGA_NONE: 1702 return false; 1703 case VGA_DEVICE: 1704 return true; 1705 case VGA_STD: 1706 case VGA_VIRTIO: 1707 case VGA_CIRRUS: 1708 return pci_vga_init(pci_bus) != NULL; 1709 default: 1710 error_setg(errp, 1711 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1712 return false; 1713 } 1714 } 1715 1716 static int spapr_pre_load(void *opaque) 1717 { 1718 int rc; 1719 1720 rc = spapr_caps_pre_load(opaque); 1721 if (rc) { 1722 return rc; 1723 } 1724 1725 return 0; 1726 } 1727 1728 static int spapr_post_load(void *opaque, int version_id) 1729 { 1730 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1731 int err = 0; 1732 1733 err = spapr_caps_post_migration(spapr); 1734 if (err) { 1735 return err; 1736 } 1737 1738 /* 1739 * In earlier versions, there was no separate qdev for the PAPR 1740 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1741 * So when migrating from those versions, poke the incoming offset 1742 * value into the RTC device 1743 */ 1744 if (version_id < 3) { 1745 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1746 if (err) { 1747 return err; 1748 } 1749 } 1750 1751 if (kvm_enabled() && spapr->patb_entry) { 1752 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1753 bool radix = !!(spapr->patb_entry & PATE1_GR); 1754 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1755 1756 /* 1757 * Update LPCR:HR and UPRT as they may not be set properly in 1758 * the stream 1759 */ 1760 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1761 LPCR_HR | LPCR_UPRT); 1762 1763 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1764 if (err) { 1765 error_report("Process table config unsupported by the host"); 1766 return -EINVAL; 1767 } 1768 } 1769 1770 err = spapr_irq_post_load(spapr, version_id); 1771 if (err) { 1772 return err; 1773 } 1774 1775 return err; 1776 } 1777 1778 static int spapr_pre_save(void *opaque) 1779 { 1780 int rc; 1781 1782 rc = spapr_caps_pre_save(opaque); 1783 if (rc) { 1784 return rc; 1785 } 1786 1787 return 0; 1788 } 1789 1790 static bool version_before_3(void *opaque, int version_id) 1791 { 1792 return version_id < 3; 1793 } 1794 1795 static bool spapr_pending_events_needed(void *opaque) 1796 { 1797 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1798 return !QTAILQ_EMPTY(&spapr->pending_events); 1799 } 1800 1801 static const VMStateDescription vmstate_spapr_event_entry = { 1802 .name = "spapr_event_log_entry", 1803 .version_id = 1, 1804 .minimum_version_id = 1, 1805 .fields = (VMStateField[]) { 1806 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1807 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1808 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1809 NULL, extended_length), 1810 VMSTATE_END_OF_LIST() 1811 }, 1812 }; 1813 1814 static const VMStateDescription vmstate_spapr_pending_events = { 1815 .name = "spapr_pending_events", 1816 .version_id = 1, 1817 .minimum_version_id = 1, 1818 .needed = spapr_pending_events_needed, 1819 .fields = (VMStateField[]) { 1820 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1821 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1822 VMSTATE_END_OF_LIST() 1823 }, 1824 }; 1825 1826 static bool spapr_ov5_cas_needed(void *opaque) 1827 { 1828 SpaprMachineState *spapr = opaque; 1829 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1830 bool cas_needed; 1831 1832 /* Prior to the introduction of SpaprOptionVector, we had two option 1833 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1834 * Both of these options encode machine topology into the device-tree 1835 * in such a way that the now-booted OS should still be able to interact 1836 * appropriately with QEMU regardless of what options were actually 1837 * negotiatied on the source side. 1838 * 1839 * As such, we can avoid migrating the CAS-negotiated options if these 1840 * are the only options available on the current machine/platform. 1841 * Since these are the only options available for pseries-2.7 and 1842 * earlier, this allows us to maintain old->new/new->old migration 1843 * compatibility. 1844 * 1845 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1846 * via default pseries-2.8 machines and explicit command-line parameters. 1847 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1848 * of the actual CAS-negotiated values to continue working properly. For 1849 * example, availability of memory unplug depends on knowing whether 1850 * OV5_HP_EVT was negotiated via CAS. 1851 * 1852 * Thus, for any cases where the set of available CAS-negotiatable 1853 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1854 * include the CAS-negotiated options in the migration stream, unless 1855 * if they affect boot time behaviour only. 1856 */ 1857 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1858 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1859 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1860 1861 /* We need extra information if we have any bits outside the mask 1862 * defined above */ 1863 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1864 1865 spapr_ovec_cleanup(ov5_mask); 1866 1867 return cas_needed; 1868 } 1869 1870 static const VMStateDescription vmstate_spapr_ov5_cas = { 1871 .name = "spapr_option_vector_ov5_cas", 1872 .version_id = 1, 1873 .minimum_version_id = 1, 1874 .needed = spapr_ov5_cas_needed, 1875 .fields = (VMStateField[]) { 1876 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1877 vmstate_spapr_ovec, SpaprOptionVector), 1878 VMSTATE_END_OF_LIST() 1879 }, 1880 }; 1881 1882 static bool spapr_patb_entry_needed(void *opaque) 1883 { 1884 SpaprMachineState *spapr = opaque; 1885 1886 return !!spapr->patb_entry; 1887 } 1888 1889 static const VMStateDescription vmstate_spapr_patb_entry = { 1890 .name = "spapr_patb_entry", 1891 .version_id = 1, 1892 .minimum_version_id = 1, 1893 .needed = spapr_patb_entry_needed, 1894 .fields = (VMStateField[]) { 1895 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1896 VMSTATE_END_OF_LIST() 1897 }, 1898 }; 1899 1900 static bool spapr_irq_map_needed(void *opaque) 1901 { 1902 SpaprMachineState *spapr = opaque; 1903 1904 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1905 } 1906 1907 static const VMStateDescription vmstate_spapr_irq_map = { 1908 .name = "spapr_irq_map", 1909 .version_id = 1, 1910 .minimum_version_id = 1, 1911 .needed = spapr_irq_map_needed, 1912 .fields = (VMStateField[]) { 1913 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1914 VMSTATE_END_OF_LIST() 1915 }, 1916 }; 1917 1918 static bool spapr_dtb_needed(void *opaque) 1919 { 1920 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1921 1922 return smc->update_dt_enabled; 1923 } 1924 1925 static int spapr_dtb_pre_load(void *opaque) 1926 { 1927 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1928 1929 g_free(spapr->fdt_blob); 1930 spapr->fdt_blob = NULL; 1931 spapr->fdt_size = 0; 1932 1933 return 0; 1934 } 1935 1936 static const VMStateDescription vmstate_spapr_dtb = { 1937 .name = "spapr_dtb", 1938 .version_id = 1, 1939 .minimum_version_id = 1, 1940 .needed = spapr_dtb_needed, 1941 .pre_load = spapr_dtb_pre_load, 1942 .fields = (VMStateField[]) { 1943 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1944 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1945 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1946 fdt_size), 1947 VMSTATE_END_OF_LIST() 1948 }, 1949 }; 1950 1951 static bool spapr_fwnmi_needed(void *opaque) 1952 { 1953 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1954 1955 return spapr->fwnmi_machine_check_addr != -1; 1956 } 1957 1958 static int spapr_fwnmi_pre_save(void *opaque) 1959 { 1960 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1961 1962 /* 1963 * Check if machine check handling is in progress and print a 1964 * warning message. 1965 */ 1966 if (spapr->fwnmi_machine_check_interlock != -1) { 1967 warn_report("A machine check is being handled during migration. The" 1968 "handler may run and log hardware error on the destination"); 1969 } 1970 1971 return 0; 1972 } 1973 1974 static const VMStateDescription vmstate_spapr_fwnmi = { 1975 .name = "spapr_fwnmi", 1976 .version_id = 1, 1977 .minimum_version_id = 1, 1978 .needed = spapr_fwnmi_needed, 1979 .pre_save = spapr_fwnmi_pre_save, 1980 .fields = (VMStateField[]) { 1981 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 1982 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 1983 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 1984 VMSTATE_END_OF_LIST() 1985 }, 1986 }; 1987 1988 static const VMStateDescription vmstate_spapr = { 1989 .name = "spapr", 1990 .version_id = 3, 1991 .minimum_version_id = 1, 1992 .pre_load = spapr_pre_load, 1993 .post_load = spapr_post_load, 1994 .pre_save = spapr_pre_save, 1995 .fields = (VMStateField[]) { 1996 /* used to be @next_irq */ 1997 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1998 1999 /* RTC offset */ 2000 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2001 2002 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2003 VMSTATE_END_OF_LIST() 2004 }, 2005 .subsections = (const VMStateDescription*[]) { 2006 &vmstate_spapr_ov5_cas, 2007 &vmstate_spapr_patb_entry, 2008 &vmstate_spapr_pending_events, 2009 &vmstate_spapr_cap_htm, 2010 &vmstate_spapr_cap_vsx, 2011 &vmstate_spapr_cap_dfp, 2012 &vmstate_spapr_cap_cfpc, 2013 &vmstate_spapr_cap_sbbc, 2014 &vmstate_spapr_cap_ibs, 2015 &vmstate_spapr_cap_hpt_maxpagesize, 2016 &vmstate_spapr_irq_map, 2017 &vmstate_spapr_cap_nested_kvm_hv, 2018 &vmstate_spapr_dtb, 2019 &vmstate_spapr_cap_large_decr, 2020 &vmstate_spapr_cap_ccf_assist, 2021 &vmstate_spapr_cap_fwnmi, 2022 &vmstate_spapr_fwnmi, 2023 NULL 2024 } 2025 }; 2026 2027 static int htab_save_setup(QEMUFile *f, void *opaque) 2028 { 2029 SpaprMachineState *spapr = opaque; 2030 2031 /* "Iteration" header */ 2032 if (!spapr->htab_shift) { 2033 qemu_put_be32(f, -1); 2034 } else { 2035 qemu_put_be32(f, spapr->htab_shift); 2036 } 2037 2038 if (spapr->htab) { 2039 spapr->htab_save_index = 0; 2040 spapr->htab_first_pass = true; 2041 } else { 2042 if (spapr->htab_shift) { 2043 assert(kvm_enabled()); 2044 } 2045 } 2046 2047 2048 return 0; 2049 } 2050 2051 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2052 int chunkstart, int n_valid, int n_invalid) 2053 { 2054 qemu_put_be32(f, chunkstart); 2055 qemu_put_be16(f, n_valid); 2056 qemu_put_be16(f, n_invalid); 2057 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2058 HASH_PTE_SIZE_64 * n_valid); 2059 } 2060 2061 static void htab_save_end_marker(QEMUFile *f) 2062 { 2063 qemu_put_be32(f, 0); 2064 qemu_put_be16(f, 0); 2065 qemu_put_be16(f, 0); 2066 } 2067 2068 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2069 int64_t max_ns) 2070 { 2071 bool has_timeout = max_ns != -1; 2072 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2073 int index = spapr->htab_save_index; 2074 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2075 2076 assert(spapr->htab_first_pass); 2077 2078 do { 2079 int chunkstart; 2080 2081 /* Consume invalid HPTEs */ 2082 while ((index < htabslots) 2083 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2084 CLEAN_HPTE(HPTE(spapr->htab, index)); 2085 index++; 2086 } 2087 2088 /* Consume valid HPTEs */ 2089 chunkstart = index; 2090 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2091 && HPTE_VALID(HPTE(spapr->htab, index))) { 2092 CLEAN_HPTE(HPTE(spapr->htab, index)); 2093 index++; 2094 } 2095 2096 if (index > chunkstart) { 2097 int n_valid = index - chunkstart; 2098 2099 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2100 2101 if (has_timeout && 2102 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2103 break; 2104 } 2105 } 2106 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2107 2108 if (index >= htabslots) { 2109 assert(index == htabslots); 2110 index = 0; 2111 spapr->htab_first_pass = false; 2112 } 2113 spapr->htab_save_index = index; 2114 } 2115 2116 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2117 int64_t max_ns) 2118 { 2119 bool final = max_ns < 0; 2120 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2121 int examined = 0, sent = 0; 2122 int index = spapr->htab_save_index; 2123 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2124 2125 assert(!spapr->htab_first_pass); 2126 2127 do { 2128 int chunkstart, invalidstart; 2129 2130 /* Consume non-dirty HPTEs */ 2131 while ((index < htabslots) 2132 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2133 index++; 2134 examined++; 2135 } 2136 2137 chunkstart = index; 2138 /* Consume valid dirty HPTEs */ 2139 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2140 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2141 && HPTE_VALID(HPTE(spapr->htab, index))) { 2142 CLEAN_HPTE(HPTE(spapr->htab, index)); 2143 index++; 2144 examined++; 2145 } 2146 2147 invalidstart = index; 2148 /* Consume invalid dirty HPTEs */ 2149 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2150 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2151 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2152 CLEAN_HPTE(HPTE(spapr->htab, index)); 2153 index++; 2154 examined++; 2155 } 2156 2157 if (index > chunkstart) { 2158 int n_valid = invalidstart - chunkstart; 2159 int n_invalid = index - invalidstart; 2160 2161 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2162 sent += index - chunkstart; 2163 2164 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2165 break; 2166 } 2167 } 2168 2169 if (examined >= htabslots) { 2170 break; 2171 } 2172 2173 if (index >= htabslots) { 2174 assert(index == htabslots); 2175 index = 0; 2176 } 2177 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2178 2179 if (index >= htabslots) { 2180 assert(index == htabslots); 2181 index = 0; 2182 } 2183 2184 spapr->htab_save_index = index; 2185 2186 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2187 } 2188 2189 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2190 #define MAX_KVM_BUF_SIZE 2048 2191 2192 static int htab_save_iterate(QEMUFile *f, void *opaque) 2193 { 2194 SpaprMachineState *spapr = opaque; 2195 int fd; 2196 int rc = 0; 2197 2198 /* Iteration header */ 2199 if (!spapr->htab_shift) { 2200 qemu_put_be32(f, -1); 2201 return 1; 2202 } else { 2203 qemu_put_be32(f, 0); 2204 } 2205 2206 if (!spapr->htab) { 2207 assert(kvm_enabled()); 2208 2209 fd = get_htab_fd(spapr); 2210 if (fd < 0) { 2211 return fd; 2212 } 2213 2214 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2215 if (rc < 0) { 2216 return rc; 2217 } 2218 } else if (spapr->htab_first_pass) { 2219 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2220 } else { 2221 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2222 } 2223 2224 htab_save_end_marker(f); 2225 2226 return rc; 2227 } 2228 2229 static int htab_save_complete(QEMUFile *f, void *opaque) 2230 { 2231 SpaprMachineState *spapr = opaque; 2232 int fd; 2233 2234 /* Iteration header */ 2235 if (!spapr->htab_shift) { 2236 qemu_put_be32(f, -1); 2237 return 0; 2238 } else { 2239 qemu_put_be32(f, 0); 2240 } 2241 2242 if (!spapr->htab) { 2243 int rc; 2244 2245 assert(kvm_enabled()); 2246 2247 fd = get_htab_fd(spapr); 2248 if (fd < 0) { 2249 return fd; 2250 } 2251 2252 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2253 if (rc < 0) { 2254 return rc; 2255 } 2256 } else { 2257 if (spapr->htab_first_pass) { 2258 htab_save_first_pass(f, spapr, -1); 2259 } 2260 htab_save_later_pass(f, spapr, -1); 2261 } 2262 2263 /* End marker */ 2264 htab_save_end_marker(f); 2265 2266 return 0; 2267 } 2268 2269 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2270 { 2271 SpaprMachineState *spapr = opaque; 2272 uint32_t section_hdr; 2273 int fd = -1; 2274 Error *local_err = NULL; 2275 2276 if (version_id < 1 || version_id > 1) { 2277 error_report("htab_load() bad version"); 2278 return -EINVAL; 2279 } 2280 2281 section_hdr = qemu_get_be32(f); 2282 2283 if (section_hdr == -1) { 2284 spapr_free_hpt(spapr); 2285 return 0; 2286 } 2287 2288 if (section_hdr) { 2289 int ret; 2290 2291 /* First section gives the htab size */ 2292 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2293 if (ret < 0) { 2294 error_report_err(local_err); 2295 return ret; 2296 } 2297 return 0; 2298 } 2299 2300 if (!spapr->htab) { 2301 assert(kvm_enabled()); 2302 2303 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2304 if (fd < 0) { 2305 error_report_err(local_err); 2306 return fd; 2307 } 2308 } 2309 2310 while (true) { 2311 uint32_t index; 2312 uint16_t n_valid, n_invalid; 2313 2314 index = qemu_get_be32(f); 2315 n_valid = qemu_get_be16(f); 2316 n_invalid = qemu_get_be16(f); 2317 2318 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2319 /* End of Stream */ 2320 break; 2321 } 2322 2323 if ((index + n_valid + n_invalid) > 2324 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2325 /* Bad index in stream */ 2326 error_report( 2327 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2328 index, n_valid, n_invalid, spapr->htab_shift); 2329 return -EINVAL; 2330 } 2331 2332 if (spapr->htab) { 2333 if (n_valid) { 2334 qemu_get_buffer(f, HPTE(spapr->htab, index), 2335 HASH_PTE_SIZE_64 * n_valid); 2336 } 2337 if (n_invalid) { 2338 memset(HPTE(spapr->htab, index + n_valid), 0, 2339 HASH_PTE_SIZE_64 * n_invalid); 2340 } 2341 } else { 2342 int rc; 2343 2344 assert(fd >= 0); 2345 2346 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2347 &local_err); 2348 if (rc < 0) { 2349 error_report_err(local_err); 2350 return rc; 2351 } 2352 } 2353 } 2354 2355 if (!spapr->htab) { 2356 assert(fd >= 0); 2357 close(fd); 2358 } 2359 2360 return 0; 2361 } 2362 2363 static void htab_save_cleanup(void *opaque) 2364 { 2365 SpaprMachineState *spapr = opaque; 2366 2367 close_htab_fd(spapr); 2368 } 2369 2370 static SaveVMHandlers savevm_htab_handlers = { 2371 .save_setup = htab_save_setup, 2372 .save_live_iterate = htab_save_iterate, 2373 .save_live_complete_precopy = htab_save_complete, 2374 .save_cleanup = htab_save_cleanup, 2375 .load_state = htab_load, 2376 }; 2377 2378 static void spapr_boot_set(void *opaque, const char *boot_device, 2379 Error **errp) 2380 { 2381 MachineState *machine = MACHINE(opaque); 2382 machine->boot_order = g_strdup(boot_device); 2383 } 2384 2385 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2386 { 2387 MachineState *machine = MACHINE(spapr); 2388 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2389 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2390 int i; 2391 2392 for (i = 0; i < nr_lmbs; i++) { 2393 uint64_t addr; 2394 2395 addr = i * lmb_size + machine->device_memory->base; 2396 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2397 addr / lmb_size); 2398 } 2399 } 2400 2401 /* 2402 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2403 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2404 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2405 */ 2406 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2407 { 2408 int i; 2409 2410 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2411 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2412 " is not aligned to %" PRIu64 " MiB", 2413 machine->ram_size, 2414 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2415 return; 2416 } 2417 2418 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2419 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2420 " is not aligned to %" PRIu64 " MiB", 2421 machine->ram_size, 2422 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2423 return; 2424 } 2425 2426 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2427 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2428 error_setg(errp, 2429 "Node %d memory size 0x%" PRIx64 2430 " is not aligned to %" PRIu64 " MiB", 2431 i, machine->numa_state->nodes[i].node_mem, 2432 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2433 return; 2434 } 2435 } 2436 } 2437 2438 /* find cpu slot in machine->possible_cpus by core_id */ 2439 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2440 { 2441 int index = id / ms->smp.threads; 2442 2443 if (index >= ms->possible_cpus->len) { 2444 return NULL; 2445 } 2446 if (idx) { 2447 *idx = index; 2448 } 2449 return &ms->possible_cpus->cpus[index]; 2450 } 2451 2452 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2453 { 2454 MachineState *ms = MACHINE(spapr); 2455 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2456 Error *local_err = NULL; 2457 bool vsmt_user = !!spapr->vsmt; 2458 int kvm_smt = kvmppc_smt_threads(); 2459 int ret; 2460 unsigned int smp_threads = ms->smp.threads; 2461 2462 if (!kvm_enabled() && (smp_threads > 1)) { 2463 error_setg(errp, "TCG cannot support more than 1 thread/core " 2464 "on a pseries machine"); 2465 return; 2466 } 2467 if (!is_power_of_2(smp_threads)) { 2468 error_setg(errp, "Cannot support %d threads/core on a pseries " 2469 "machine because it must be a power of 2", smp_threads); 2470 return; 2471 } 2472 2473 /* Detemine the VSMT mode to use: */ 2474 if (vsmt_user) { 2475 if (spapr->vsmt < smp_threads) { 2476 error_setg(errp, "Cannot support VSMT mode %d" 2477 " because it must be >= threads/core (%d)", 2478 spapr->vsmt, smp_threads); 2479 return; 2480 } 2481 /* In this case, spapr->vsmt has been set by the command line */ 2482 } else if (!smc->smp_threads_vsmt) { 2483 /* 2484 * Default VSMT value is tricky, because we need it to be as 2485 * consistent as possible (for migration), but this requires 2486 * changing it for at least some existing cases. We pick 8 as 2487 * the value that we'd get with KVM on POWER8, the 2488 * overwhelmingly common case in production systems. 2489 */ 2490 spapr->vsmt = MAX(8, smp_threads); 2491 } else { 2492 spapr->vsmt = smp_threads; 2493 } 2494 2495 /* KVM: If necessary, set the SMT mode: */ 2496 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2497 ret = kvmppc_set_smt_threads(spapr->vsmt); 2498 if (ret) { 2499 /* Looks like KVM isn't able to change VSMT mode */ 2500 error_setg(&local_err, 2501 "Failed to set KVM's VSMT mode to %d (errno %d)", 2502 spapr->vsmt, ret); 2503 /* We can live with that if the default one is big enough 2504 * for the number of threads, and a submultiple of the one 2505 * we want. In this case we'll waste some vcpu ids, but 2506 * behaviour will be correct */ 2507 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2508 warn_report_err(local_err); 2509 } else { 2510 if (!vsmt_user) { 2511 error_append_hint(&local_err, 2512 "On PPC, a VM with %d threads/core" 2513 " on a host with %d threads/core" 2514 " requires the use of VSMT mode %d.\n", 2515 smp_threads, kvm_smt, spapr->vsmt); 2516 } 2517 kvmppc_error_append_smt_possible_hint(&local_err); 2518 error_propagate(errp, local_err); 2519 } 2520 } 2521 } 2522 /* else TCG: nothing to do currently */ 2523 } 2524 2525 static void spapr_init_cpus(SpaprMachineState *spapr) 2526 { 2527 MachineState *machine = MACHINE(spapr); 2528 MachineClass *mc = MACHINE_GET_CLASS(machine); 2529 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2530 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2531 const CPUArchIdList *possible_cpus; 2532 unsigned int smp_cpus = machine->smp.cpus; 2533 unsigned int smp_threads = machine->smp.threads; 2534 unsigned int max_cpus = machine->smp.max_cpus; 2535 int boot_cores_nr = smp_cpus / smp_threads; 2536 int i; 2537 2538 possible_cpus = mc->possible_cpu_arch_ids(machine); 2539 if (mc->has_hotpluggable_cpus) { 2540 if (smp_cpus % smp_threads) { 2541 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2542 smp_cpus, smp_threads); 2543 exit(1); 2544 } 2545 if (max_cpus % smp_threads) { 2546 error_report("max_cpus (%u) must be multiple of threads (%u)", 2547 max_cpus, smp_threads); 2548 exit(1); 2549 } 2550 } else { 2551 if (max_cpus != smp_cpus) { 2552 error_report("This machine version does not support CPU hotplug"); 2553 exit(1); 2554 } 2555 boot_cores_nr = possible_cpus->len; 2556 } 2557 2558 if (smc->pre_2_10_has_unused_icps) { 2559 int i; 2560 2561 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2562 /* Dummy entries get deregistered when real ICPState objects 2563 * are registered during CPU core hotplug. 2564 */ 2565 pre_2_10_vmstate_register_dummy_icp(i); 2566 } 2567 } 2568 2569 for (i = 0; i < possible_cpus->len; i++) { 2570 int core_id = i * smp_threads; 2571 2572 if (mc->has_hotpluggable_cpus) { 2573 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2574 spapr_vcpu_id(spapr, core_id)); 2575 } 2576 2577 if (i < boot_cores_nr) { 2578 Object *core = object_new(type); 2579 int nr_threads = smp_threads; 2580 2581 /* Handle the partially filled core for older machine types */ 2582 if ((i + 1) * smp_threads >= smp_cpus) { 2583 nr_threads = smp_cpus - i * smp_threads; 2584 } 2585 2586 object_property_set_int(core, "nr-threads", nr_threads, 2587 &error_fatal); 2588 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2589 &error_fatal); 2590 qdev_realize(DEVICE(core), NULL, &error_fatal); 2591 2592 object_unref(core); 2593 } 2594 } 2595 } 2596 2597 static PCIHostState *spapr_create_default_phb(void) 2598 { 2599 DeviceState *dev; 2600 2601 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2602 qdev_prop_set_uint32(dev, "index", 0); 2603 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2604 2605 return PCI_HOST_BRIDGE(dev); 2606 } 2607 2608 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2609 { 2610 MachineState *machine = MACHINE(spapr); 2611 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2612 hwaddr rma_size = machine->ram_size; 2613 hwaddr node0_size = spapr_node0_size(machine); 2614 2615 /* RMA has to fit in the first NUMA node */ 2616 rma_size = MIN(rma_size, node0_size); 2617 2618 /* 2619 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2620 * never exceed that 2621 */ 2622 rma_size = MIN(rma_size, 1 * TiB); 2623 2624 /* 2625 * Clamp the RMA size based on machine type. This is for 2626 * migration compatibility with older qemu versions, which limited 2627 * the RMA size for complicated and mostly bad reasons. 2628 */ 2629 if (smc->rma_limit) { 2630 rma_size = MIN(rma_size, smc->rma_limit); 2631 } 2632 2633 if (rma_size < MIN_RMA_SLOF) { 2634 error_setg(errp, 2635 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2636 "ldMiB guest RMA (Real Mode Area memory)", 2637 MIN_RMA_SLOF / MiB); 2638 return 0; 2639 } 2640 2641 return rma_size; 2642 } 2643 2644 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2645 { 2646 MachineState *machine = MACHINE(spapr); 2647 int i; 2648 2649 for (i = 0; i < machine->ram_slots; i++) { 2650 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2651 } 2652 } 2653 2654 /* pSeries LPAR / sPAPR hardware init */ 2655 static void spapr_machine_init(MachineState *machine) 2656 { 2657 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2658 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2659 MachineClass *mc = MACHINE_GET_CLASS(machine); 2660 const char *kernel_filename = machine->kernel_filename; 2661 const char *initrd_filename = machine->initrd_filename; 2662 PCIHostState *phb; 2663 int i; 2664 MemoryRegion *sysmem = get_system_memory(); 2665 long load_limit, fw_size; 2666 char *filename; 2667 Error *resize_hpt_err = NULL; 2668 2669 msi_nonbroken = true; 2670 2671 QLIST_INIT(&spapr->phbs); 2672 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2673 2674 /* Determine capabilities to run with */ 2675 spapr_caps_init(spapr); 2676 2677 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2678 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2679 /* 2680 * If the user explicitly requested a mode we should either 2681 * supply it, or fail completely (which we do below). But if 2682 * it's not set explicitly, we reset our mode to something 2683 * that works 2684 */ 2685 if (resize_hpt_err) { 2686 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2687 error_free(resize_hpt_err); 2688 resize_hpt_err = NULL; 2689 } else { 2690 spapr->resize_hpt = smc->resize_hpt_default; 2691 } 2692 } 2693 2694 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2695 2696 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2697 /* 2698 * User requested HPT resize, but this host can't supply it. Bail out 2699 */ 2700 error_report_err(resize_hpt_err); 2701 exit(1); 2702 } 2703 error_free(resize_hpt_err); 2704 2705 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2706 2707 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2708 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2709 2710 /* 2711 * VSMT must be set in order to be able to compute VCPU ids, ie to 2712 * call spapr_max_server_number() or spapr_vcpu_id(). 2713 */ 2714 spapr_set_vsmt_mode(spapr, &error_fatal); 2715 2716 /* Set up Interrupt Controller before we create the VCPUs */ 2717 spapr_irq_init(spapr, &error_fatal); 2718 2719 /* Set up containers for ibm,client-architecture-support negotiated options 2720 */ 2721 spapr->ov5 = spapr_ovec_new(); 2722 spapr->ov5_cas = spapr_ovec_new(); 2723 2724 if (smc->dr_lmb_enabled) { 2725 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2726 spapr_validate_node_memory(machine, &error_fatal); 2727 } 2728 2729 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2730 2731 /* advertise support for dedicated HP event source to guests */ 2732 if (spapr->use_hotplug_event_source) { 2733 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2734 } 2735 2736 /* advertise support for HPT resizing */ 2737 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2738 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2739 } 2740 2741 /* advertise support for ibm,dyamic-memory-v2 */ 2742 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2743 2744 /* advertise XIVE on POWER9 machines */ 2745 if (spapr->irq->xive) { 2746 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2747 } 2748 2749 /* init CPUs */ 2750 spapr_init_cpus(spapr); 2751 2752 /* 2753 * check we don't have a memory-less/cpu-less NUMA node 2754 * Firmware relies on the existing memory/cpu topology to provide the 2755 * NUMA topology to the kernel. 2756 * And the linux kernel needs to know the NUMA topology at start 2757 * to be able to hotplug CPUs later. 2758 */ 2759 if (machine->numa_state->num_nodes) { 2760 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2761 /* check for memory-less node */ 2762 if (machine->numa_state->nodes[i].node_mem == 0) { 2763 CPUState *cs; 2764 int found = 0; 2765 /* check for cpu-less node */ 2766 CPU_FOREACH(cs) { 2767 PowerPCCPU *cpu = POWERPC_CPU(cs); 2768 if (cpu->node_id == i) { 2769 found = 1; 2770 break; 2771 } 2772 } 2773 /* memory-less and cpu-less node */ 2774 if (!found) { 2775 error_report( 2776 "Memory-less/cpu-less nodes are not supported (node %d)", 2777 i); 2778 exit(1); 2779 } 2780 } 2781 } 2782 2783 } 2784 2785 /* 2786 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. 2787 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is 2788 * called from vPHB reset handler so we initialize the counter here. 2789 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM 2790 * must be equally distant from any other node. 2791 * The final value of spapr->gpu_numa_id is going to be written to 2792 * max-associativity-domains in spapr_build_fdt(). 2793 */ 2794 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes); 2795 2796 /* Init numa_assoc_array */ 2797 spapr_numa_associativity_init(spapr, machine); 2798 2799 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2800 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2801 spapr->max_compat_pvr)) { 2802 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2803 /* KVM and TCG always allow GTSE with radix... */ 2804 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2805 } 2806 /* ... but not with hash (currently). */ 2807 2808 if (kvm_enabled()) { 2809 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2810 kvmppc_enable_logical_ci_hcalls(); 2811 kvmppc_enable_set_mode_hcall(); 2812 2813 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2814 kvmppc_enable_clear_ref_mod_hcalls(); 2815 2816 /* Enable H_PAGE_INIT */ 2817 kvmppc_enable_h_page_init(); 2818 } 2819 2820 /* map RAM */ 2821 memory_region_add_subregion(sysmem, 0, machine->ram); 2822 2823 /* always allocate the device memory information */ 2824 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2825 2826 /* initialize hotplug memory address space */ 2827 if (machine->ram_size < machine->maxram_size) { 2828 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2829 /* 2830 * Limit the number of hotpluggable memory slots to half the number 2831 * slots that KVM supports, leaving the other half for PCI and other 2832 * devices. However ensure that number of slots doesn't drop below 32. 2833 */ 2834 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2835 SPAPR_MAX_RAM_SLOTS; 2836 2837 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2838 max_memslots = SPAPR_MAX_RAM_SLOTS; 2839 } 2840 if (machine->ram_slots > max_memslots) { 2841 error_report("Specified number of memory slots %" 2842 PRIu64" exceeds max supported %d", 2843 machine->ram_slots, max_memslots); 2844 exit(1); 2845 } 2846 2847 machine->device_memory->base = ROUND_UP(machine->ram_size, 2848 SPAPR_DEVICE_MEM_ALIGN); 2849 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2850 "device-memory", device_mem_size); 2851 memory_region_add_subregion(sysmem, machine->device_memory->base, 2852 &machine->device_memory->mr); 2853 } 2854 2855 if (smc->dr_lmb_enabled) { 2856 spapr_create_lmb_dr_connectors(spapr); 2857 } 2858 2859 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { 2860 /* Create the error string for live migration blocker */ 2861 error_setg(&spapr->fwnmi_migration_blocker, 2862 "A machine check is being handled during migration. The handler" 2863 "may run and log hardware error on the destination"); 2864 } 2865 2866 if (mc->nvdimm_supported) { 2867 spapr_create_nvdimm_dr_connectors(spapr); 2868 } 2869 2870 /* Set up RTAS event infrastructure */ 2871 spapr_events_init(spapr); 2872 2873 /* Set up the RTC RTAS interfaces */ 2874 spapr_rtc_create(spapr); 2875 2876 /* Set up VIO bus */ 2877 spapr->vio_bus = spapr_vio_bus_init(); 2878 2879 for (i = 0; i < serial_max_hds(); i++) { 2880 if (serial_hd(i)) { 2881 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2882 } 2883 } 2884 2885 /* We always have at least the nvram device on VIO */ 2886 spapr_create_nvram(spapr); 2887 2888 /* 2889 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2890 * connectors (described in root DT node's "ibm,drc-types" property) 2891 * are pre-initialized here. additional child connectors (such as 2892 * connectors for a PHBs PCI slots) are added as needed during their 2893 * parent's realization. 2894 */ 2895 if (smc->dr_phb_enabled) { 2896 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2897 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2898 } 2899 } 2900 2901 /* Set up PCI */ 2902 spapr_pci_rtas_init(); 2903 2904 phb = spapr_create_default_phb(); 2905 2906 for (i = 0; i < nb_nics; i++) { 2907 NICInfo *nd = &nd_table[i]; 2908 2909 if (!nd->model) { 2910 nd->model = g_strdup("spapr-vlan"); 2911 } 2912 2913 if (g_str_equal(nd->model, "spapr-vlan") || 2914 g_str_equal(nd->model, "ibmveth")) { 2915 spapr_vlan_create(spapr->vio_bus, nd); 2916 } else { 2917 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2918 } 2919 } 2920 2921 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2922 spapr_vscsi_create(spapr->vio_bus); 2923 } 2924 2925 /* Graphics */ 2926 if (spapr_vga_init(phb->bus, &error_fatal)) { 2927 spapr->has_graphics = true; 2928 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2929 } 2930 2931 if (machine->usb) { 2932 if (smc->use_ohci_by_default) { 2933 pci_create_simple(phb->bus, -1, "pci-ohci"); 2934 } else { 2935 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2936 } 2937 2938 if (spapr->has_graphics) { 2939 USBBus *usb_bus = usb_bus_find(-1); 2940 2941 usb_create_simple(usb_bus, "usb-kbd"); 2942 usb_create_simple(usb_bus, "usb-mouse"); 2943 } 2944 } 2945 2946 if (kernel_filename) { 2947 spapr->kernel_size = load_elf(kernel_filename, NULL, 2948 translate_kernel_address, spapr, 2949 NULL, NULL, NULL, NULL, 1, 2950 PPC_ELF_MACHINE, 0, 0); 2951 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2952 spapr->kernel_size = load_elf(kernel_filename, NULL, 2953 translate_kernel_address, spapr, 2954 NULL, NULL, NULL, NULL, 0, 2955 PPC_ELF_MACHINE, 0, 0); 2956 spapr->kernel_le = spapr->kernel_size > 0; 2957 } 2958 if (spapr->kernel_size < 0) { 2959 error_report("error loading %s: %s", kernel_filename, 2960 load_elf_strerror(spapr->kernel_size)); 2961 exit(1); 2962 } 2963 2964 /* load initrd */ 2965 if (initrd_filename) { 2966 /* Try to locate the initrd in the gap between the kernel 2967 * and the firmware. Add a bit of space just in case 2968 */ 2969 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 2970 + 0x1ffff) & ~0xffff; 2971 spapr->initrd_size = load_image_targphys(initrd_filename, 2972 spapr->initrd_base, 2973 load_limit 2974 - spapr->initrd_base); 2975 if (spapr->initrd_size < 0) { 2976 error_report("could not load initial ram disk '%s'", 2977 initrd_filename); 2978 exit(1); 2979 } 2980 } 2981 } 2982 2983 if (bios_name == NULL) { 2984 bios_name = FW_FILE_NAME; 2985 } 2986 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2987 if (!filename) { 2988 error_report("Could not find LPAR firmware '%s'", bios_name); 2989 exit(1); 2990 } 2991 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2992 if (fw_size <= 0) { 2993 error_report("Could not load LPAR firmware '%s'", filename); 2994 exit(1); 2995 } 2996 g_free(filename); 2997 2998 /* FIXME: Should register things through the MachineState's qdev 2999 * interface, this is a legacy from the sPAPREnvironment structure 3000 * which predated MachineState but had a similar function */ 3001 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3002 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3003 &savevm_htab_handlers, spapr); 3004 3005 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 3006 3007 qemu_register_boot_set(spapr_boot_set, spapr); 3008 3009 /* 3010 * Nothing needs to be done to resume a suspended guest because 3011 * suspending does not change the machine state, so no need for 3012 * a ->wakeup method. 3013 */ 3014 qemu_register_wakeup_support(); 3015 3016 if (kvm_enabled()) { 3017 /* to stop and start vmclock */ 3018 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3019 &spapr->tb); 3020 3021 kvmppc_spapr_enable_inkernel_multitce(); 3022 } 3023 3024 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3025 } 3026 3027 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3028 { 3029 if (!vm_type) { 3030 return 0; 3031 } 3032 3033 if (!strcmp(vm_type, "HV")) { 3034 return 1; 3035 } 3036 3037 if (!strcmp(vm_type, "PR")) { 3038 return 2; 3039 } 3040 3041 error_report("Unknown kvm-type specified '%s'", vm_type); 3042 exit(1); 3043 } 3044 3045 /* 3046 * Implementation of an interface to adjust firmware path 3047 * for the bootindex property handling. 3048 */ 3049 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3050 DeviceState *dev) 3051 { 3052 #define CAST(type, obj, name) \ 3053 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3054 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3055 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3056 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3057 3058 if (d) { 3059 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3060 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3061 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3062 3063 if (spapr) { 3064 /* 3065 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3066 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3067 * 0x8000 | (target << 8) | (bus << 5) | lun 3068 * (see the "Logical unit addressing format" table in SAM5) 3069 */ 3070 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3071 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3072 (uint64_t)id << 48); 3073 } else if (virtio) { 3074 /* 3075 * We use SRP luns of the form 01000000 | (target << 8) | lun 3076 * in the top 32 bits of the 64-bit LUN 3077 * Note: the quote above is from SLOF and it is wrong, 3078 * the actual binding is: 3079 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3080 */ 3081 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3082 if (d->lun >= 256) { 3083 /* Use the LUN "flat space addressing method" */ 3084 id |= 0x4000; 3085 } 3086 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3087 (uint64_t)id << 32); 3088 } else if (usb) { 3089 /* 3090 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3091 * in the top 32 bits of the 64-bit LUN 3092 */ 3093 unsigned usb_port = atoi(usb->port->path); 3094 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3095 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3096 (uint64_t)id << 32); 3097 } 3098 } 3099 3100 /* 3101 * SLOF probes the USB devices, and if it recognizes that the device is a 3102 * storage device, it changes its name to "storage" instead of "usb-host", 3103 * and additionally adds a child node for the SCSI LUN, so the correct 3104 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3105 */ 3106 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3107 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3108 if (usb_host_dev_is_scsi_storage(usbdev)) { 3109 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3110 } 3111 } 3112 3113 if (phb) { 3114 /* Replace "pci" with "pci@800000020000000" */ 3115 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3116 } 3117 3118 if (vsc) { 3119 /* Same logic as virtio above */ 3120 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3121 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3122 } 3123 3124 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3125 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3126 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3127 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3128 } 3129 3130 return NULL; 3131 } 3132 3133 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3134 { 3135 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3136 3137 return g_strdup(spapr->kvm_type); 3138 } 3139 3140 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3141 { 3142 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3143 3144 g_free(spapr->kvm_type); 3145 spapr->kvm_type = g_strdup(value); 3146 } 3147 3148 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3149 { 3150 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3151 3152 return spapr->use_hotplug_event_source; 3153 } 3154 3155 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3156 Error **errp) 3157 { 3158 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3159 3160 spapr->use_hotplug_event_source = value; 3161 } 3162 3163 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3164 { 3165 return true; 3166 } 3167 3168 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3169 { 3170 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3171 3172 switch (spapr->resize_hpt) { 3173 case SPAPR_RESIZE_HPT_DEFAULT: 3174 return g_strdup("default"); 3175 case SPAPR_RESIZE_HPT_DISABLED: 3176 return g_strdup("disabled"); 3177 case SPAPR_RESIZE_HPT_ENABLED: 3178 return g_strdup("enabled"); 3179 case SPAPR_RESIZE_HPT_REQUIRED: 3180 return g_strdup("required"); 3181 } 3182 g_assert_not_reached(); 3183 } 3184 3185 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3186 { 3187 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3188 3189 if (strcmp(value, "default") == 0) { 3190 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3191 } else if (strcmp(value, "disabled") == 0) { 3192 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3193 } else if (strcmp(value, "enabled") == 0) { 3194 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3195 } else if (strcmp(value, "required") == 0) { 3196 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3197 } else { 3198 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3199 } 3200 } 3201 3202 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3203 { 3204 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3205 3206 if (spapr->irq == &spapr_irq_xics_legacy) { 3207 return g_strdup("legacy"); 3208 } else if (spapr->irq == &spapr_irq_xics) { 3209 return g_strdup("xics"); 3210 } else if (spapr->irq == &spapr_irq_xive) { 3211 return g_strdup("xive"); 3212 } else if (spapr->irq == &spapr_irq_dual) { 3213 return g_strdup("dual"); 3214 } 3215 g_assert_not_reached(); 3216 } 3217 3218 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3219 { 3220 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3221 3222 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3223 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3224 return; 3225 } 3226 3227 /* The legacy IRQ backend can not be set */ 3228 if (strcmp(value, "xics") == 0) { 3229 spapr->irq = &spapr_irq_xics; 3230 } else if (strcmp(value, "xive") == 0) { 3231 spapr->irq = &spapr_irq_xive; 3232 } else if (strcmp(value, "dual") == 0) { 3233 spapr->irq = &spapr_irq_dual; 3234 } else { 3235 error_setg(errp, "Bad value for \"ic-mode\" property"); 3236 } 3237 } 3238 3239 static char *spapr_get_host_model(Object *obj, Error **errp) 3240 { 3241 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3242 3243 return g_strdup(spapr->host_model); 3244 } 3245 3246 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3247 { 3248 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3249 3250 g_free(spapr->host_model); 3251 spapr->host_model = g_strdup(value); 3252 } 3253 3254 static char *spapr_get_host_serial(Object *obj, Error **errp) 3255 { 3256 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3257 3258 return g_strdup(spapr->host_serial); 3259 } 3260 3261 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3262 { 3263 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3264 3265 g_free(spapr->host_serial); 3266 spapr->host_serial = g_strdup(value); 3267 } 3268 3269 static void spapr_instance_init(Object *obj) 3270 { 3271 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3272 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3273 3274 spapr->htab_fd = -1; 3275 spapr->use_hotplug_event_source = true; 3276 object_property_add_str(obj, "kvm-type", 3277 spapr_get_kvm_type, spapr_set_kvm_type); 3278 object_property_set_description(obj, "kvm-type", 3279 "Specifies the KVM virtualization mode (HV, PR)"); 3280 object_property_add_bool(obj, "modern-hotplug-events", 3281 spapr_get_modern_hotplug_events, 3282 spapr_set_modern_hotplug_events); 3283 object_property_set_description(obj, "modern-hotplug-events", 3284 "Use dedicated hotplug event mechanism in" 3285 " place of standard EPOW events when possible" 3286 " (required for memory hot-unplug support)"); 3287 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3288 "Maximum permitted CPU compatibility mode"); 3289 3290 object_property_add_str(obj, "resize-hpt", 3291 spapr_get_resize_hpt, spapr_set_resize_hpt); 3292 object_property_set_description(obj, "resize-hpt", 3293 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3294 object_property_add_uint32_ptr(obj, "vsmt", 3295 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3296 object_property_set_description(obj, "vsmt", 3297 "Virtual SMT: KVM behaves as if this were" 3298 " the host's SMT mode"); 3299 3300 object_property_add_bool(obj, "vfio-no-msix-emulation", 3301 spapr_get_msix_emulation, NULL); 3302 3303 object_property_add_uint64_ptr(obj, "kernel-addr", 3304 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3305 object_property_set_description(obj, "kernel-addr", 3306 stringify(KERNEL_LOAD_ADDR) 3307 " for -kernel is the default"); 3308 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3309 /* The machine class defines the default interrupt controller mode */ 3310 spapr->irq = smc->irq; 3311 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3312 spapr_set_ic_mode); 3313 object_property_set_description(obj, "ic-mode", 3314 "Specifies the interrupt controller mode (xics, xive, dual)"); 3315 3316 object_property_add_str(obj, "host-model", 3317 spapr_get_host_model, spapr_set_host_model); 3318 object_property_set_description(obj, "host-model", 3319 "Host model to advertise in guest device tree"); 3320 object_property_add_str(obj, "host-serial", 3321 spapr_get_host_serial, spapr_set_host_serial); 3322 object_property_set_description(obj, "host-serial", 3323 "Host serial number to advertise in guest device tree"); 3324 } 3325 3326 static void spapr_machine_finalizefn(Object *obj) 3327 { 3328 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3329 3330 g_free(spapr->kvm_type); 3331 } 3332 3333 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3334 { 3335 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3336 PowerPCCPU *cpu = POWERPC_CPU(cs); 3337 CPUPPCState *env = &cpu->env; 3338 3339 cpu_synchronize_state(cs); 3340 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3341 if (spapr->fwnmi_system_reset_addr != -1) { 3342 uint64_t rtas_addr, addr; 3343 3344 /* get rtas addr from fdt */ 3345 rtas_addr = spapr_get_rtas_addr(); 3346 if (!rtas_addr) { 3347 qemu_system_guest_panicked(NULL); 3348 return; 3349 } 3350 3351 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3352 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3353 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3354 env->gpr[3] = addr; 3355 } 3356 ppc_cpu_do_system_reset(cs); 3357 if (spapr->fwnmi_system_reset_addr != -1) { 3358 env->nip = spapr->fwnmi_system_reset_addr; 3359 } 3360 } 3361 3362 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3363 { 3364 CPUState *cs; 3365 3366 CPU_FOREACH(cs) { 3367 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3368 } 3369 } 3370 3371 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3372 void *fdt, int *fdt_start_offset, Error **errp) 3373 { 3374 uint64_t addr; 3375 uint32_t node; 3376 3377 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3378 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3379 &error_abort); 3380 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3381 SPAPR_MEMORY_BLOCK_SIZE); 3382 return 0; 3383 } 3384 3385 static bool spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3386 bool dedicated_hp_event_source, Error **errp) 3387 { 3388 SpaprDrc *drc; 3389 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3390 int i; 3391 uint64_t addr = addr_start; 3392 bool hotplugged = spapr_drc_hotplugged(dev); 3393 3394 for (i = 0; i < nr_lmbs; i++) { 3395 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3396 addr / SPAPR_MEMORY_BLOCK_SIZE); 3397 g_assert(drc); 3398 3399 if (!spapr_drc_attach(drc, dev, errp)) { 3400 while (addr > addr_start) { 3401 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3402 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3403 addr / SPAPR_MEMORY_BLOCK_SIZE); 3404 spapr_drc_detach(drc); 3405 } 3406 return false; 3407 } 3408 if (!hotplugged) { 3409 spapr_drc_reset(drc); 3410 } 3411 addr += SPAPR_MEMORY_BLOCK_SIZE; 3412 } 3413 /* send hotplug notification to the 3414 * guest only in case of hotplugged memory 3415 */ 3416 if (hotplugged) { 3417 if (dedicated_hp_event_source) { 3418 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3419 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3420 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3421 nr_lmbs, 3422 spapr_drc_index(drc)); 3423 } else { 3424 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3425 nr_lmbs); 3426 } 3427 } 3428 return true; 3429 } 3430 3431 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3432 Error **errp) 3433 { 3434 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3435 PCDIMMDevice *dimm = PC_DIMM(dev); 3436 uint64_t size, addr; 3437 int64_t slot; 3438 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3439 3440 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3441 3442 pc_dimm_plug(dimm, MACHINE(ms)); 3443 3444 if (!is_nvdimm) { 3445 addr = object_property_get_uint(OBJECT(dimm), 3446 PC_DIMM_ADDR_PROP, &error_abort); 3447 if (!spapr_add_lmbs(dev, addr, size, 3448 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), errp)) { 3449 goto out_unplug; 3450 } 3451 } else { 3452 slot = object_property_get_int(OBJECT(dimm), 3453 PC_DIMM_SLOT_PROP, &error_abort); 3454 /* We should have valid slot number at this point */ 3455 g_assert(slot >= 0); 3456 if (!spapr_add_nvdimm(dev, slot, errp)) { 3457 goto out_unplug; 3458 } 3459 } 3460 3461 return; 3462 3463 out_unplug: 3464 pc_dimm_unplug(dimm, MACHINE(ms)); 3465 } 3466 3467 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3468 Error **errp) 3469 { 3470 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3471 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3472 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3473 PCDIMMDevice *dimm = PC_DIMM(dev); 3474 Error *local_err = NULL; 3475 uint64_t size; 3476 Object *memdev; 3477 hwaddr pagesize; 3478 3479 if (!smc->dr_lmb_enabled) { 3480 error_setg(errp, "Memory hotplug not supported for this machine"); 3481 return; 3482 } 3483 3484 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3485 if (local_err) { 3486 error_propagate(errp, local_err); 3487 return; 3488 } 3489 3490 if (is_nvdimm) { 3491 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3492 return; 3493 } 3494 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3495 error_setg(errp, "Hotplugged memory size must be a multiple of " 3496 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3497 return; 3498 } 3499 3500 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3501 &error_abort); 3502 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3503 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3504 return; 3505 } 3506 3507 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3508 } 3509 3510 struct SpaprDimmState { 3511 PCDIMMDevice *dimm; 3512 uint32_t nr_lmbs; 3513 QTAILQ_ENTRY(SpaprDimmState) next; 3514 }; 3515 3516 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3517 PCDIMMDevice *dimm) 3518 { 3519 SpaprDimmState *dimm_state = NULL; 3520 3521 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3522 if (dimm_state->dimm == dimm) { 3523 break; 3524 } 3525 } 3526 return dimm_state; 3527 } 3528 3529 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3530 uint32_t nr_lmbs, 3531 PCDIMMDevice *dimm) 3532 { 3533 SpaprDimmState *ds = NULL; 3534 3535 /* 3536 * If this request is for a DIMM whose removal had failed earlier 3537 * (due to guest's refusal to remove the LMBs), we would have this 3538 * dimm already in the pending_dimm_unplugs list. In that 3539 * case don't add again. 3540 */ 3541 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3542 if (!ds) { 3543 ds = g_malloc0(sizeof(SpaprDimmState)); 3544 ds->nr_lmbs = nr_lmbs; 3545 ds->dimm = dimm; 3546 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3547 } 3548 return ds; 3549 } 3550 3551 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3552 SpaprDimmState *dimm_state) 3553 { 3554 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3555 g_free(dimm_state); 3556 } 3557 3558 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3559 PCDIMMDevice *dimm) 3560 { 3561 SpaprDrc *drc; 3562 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3563 &error_abort); 3564 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3565 uint32_t avail_lmbs = 0; 3566 uint64_t addr_start, addr; 3567 int i; 3568 3569 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3570 &error_abort); 3571 3572 addr = addr_start; 3573 for (i = 0; i < nr_lmbs; i++) { 3574 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3575 addr / SPAPR_MEMORY_BLOCK_SIZE); 3576 g_assert(drc); 3577 if (drc->dev) { 3578 avail_lmbs++; 3579 } 3580 addr += SPAPR_MEMORY_BLOCK_SIZE; 3581 } 3582 3583 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3584 } 3585 3586 /* Callback to be called during DRC release. */ 3587 void spapr_lmb_release(DeviceState *dev) 3588 { 3589 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3590 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3591 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3592 3593 /* This information will get lost if a migration occurs 3594 * during the unplug process. In this case recover it. */ 3595 if (ds == NULL) { 3596 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3597 g_assert(ds); 3598 /* The DRC being examined by the caller at least must be counted */ 3599 g_assert(ds->nr_lmbs); 3600 } 3601 3602 if (--ds->nr_lmbs) { 3603 return; 3604 } 3605 3606 /* 3607 * Now that all the LMBs have been removed by the guest, call the 3608 * unplug handler chain. This can never fail. 3609 */ 3610 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3611 object_unparent(OBJECT(dev)); 3612 } 3613 3614 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3615 { 3616 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3617 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3618 3619 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3620 qdev_unrealize(dev); 3621 spapr_pending_dimm_unplugs_remove(spapr, ds); 3622 } 3623 3624 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3625 DeviceState *dev, Error **errp) 3626 { 3627 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3628 PCDIMMDevice *dimm = PC_DIMM(dev); 3629 uint32_t nr_lmbs; 3630 uint64_t size, addr_start, addr; 3631 int i; 3632 SpaprDrc *drc; 3633 3634 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3635 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3636 return; 3637 } 3638 3639 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3640 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3641 3642 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3643 &error_abort); 3644 3645 /* 3646 * An existing pending dimm state for this DIMM means that there is an 3647 * unplug operation in progress, waiting for the spapr_lmb_release 3648 * callback to complete the job (BQL can't cover that far). In this case, 3649 * bail out to avoid detaching DRCs that were already released. 3650 */ 3651 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3652 error_setg(errp, "Memory unplug already in progress for device %s", 3653 dev->id); 3654 return; 3655 } 3656 3657 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3658 3659 addr = addr_start; 3660 for (i = 0; i < nr_lmbs; i++) { 3661 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3662 addr / SPAPR_MEMORY_BLOCK_SIZE); 3663 g_assert(drc); 3664 3665 spapr_drc_detach(drc); 3666 addr += SPAPR_MEMORY_BLOCK_SIZE; 3667 } 3668 3669 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3670 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3671 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3672 nr_lmbs, spapr_drc_index(drc)); 3673 } 3674 3675 /* Callback to be called during DRC release. */ 3676 void spapr_core_release(DeviceState *dev) 3677 { 3678 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3679 3680 /* Call the unplug handler chain. This can never fail. */ 3681 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3682 object_unparent(OBJECT(dev)); 3683 } 3684 3685 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3686 { 3687 MachineState *ms = MACHINE(hotplug_dev); 3688 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3689 CPUCore *cc = CPU_CORE(dev); 3690 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3691 3692 if (smc->pre_2_10_has_unused_icps) { 3693 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3694 int i; 3695 3696 for (i = 0; i < cc->nr_threads; i++) { 3697 CPUState *cs = CPU(sc->threads[i]); 3698 3699 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3700 } 3701 } 3702 3703 assert(core_slot); 3704 core_slot->cpu = NULL; 3705 qdev_unrealize(dev); 3706 } 3707 3708 static 3709 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3710 Error **errp) 3711 { 3712 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3713 int index; 3714 SpaprDrc *drc; 3715 CPUCore *cc = CPU_CORE(dev); 3716 3717 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3718 error_setg(errp, "Unable to find CPU core with core-id: %d", 3719 cc->core_id); 3720 return; 3721 } 3722 if (index == 0) { 3723 error_setg(errp, "Boot CPU core may not be unplugged"); 3724 return; 3725 } 3726 3727 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3728 spapr_vcpu_id(spapr, cc->core_id)); 3729 g_assert(drc); 3730 3731 if (!spapr_drc_unplug_requested(drc)) { 3732 spapr_drc_detach(drc); 3733 spapr_hotplug_req_remove_by_index(drc); 3734 } 3735 } 3736 3737 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3738 void *fdt, int *fdt_start_offset, Error **errp) 3739 { 3740 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3741 CPUState *cs = CPU(core->threads[0]); 3742 PowerPCCPU *cpu = POWERPC_CPU(cs); 3743 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3744 int id = spapr_get_vcpu_id(cpu); 3745 char *nodename; 3746 int offset; 3747 3748 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3749 offset = fdt_add_subnode(fdt, 0, nodename); 3750 g_free(nodename); 3751 3752 spapr_dt_cpu(cs, fdt, offset, spapr); 3753 3754 *fdt_start_offset = offset; 3755 return 0; 3756 } 3757 3758 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3759 Error **errp) 3760 { 3761 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3762 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3763 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3764 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3765 CPUCore *cc = CPU_CORE(dev); 3766 CPUState *cs; 3767 SpaprDrc *drc; 3768 CPUArchId *core_slot; 3769 int index; 3770 bool hotplugged = spapr_drc_hotplugged(dev); 3771 int i; 3772 3773 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3774 if (!core_slot) { 3775 error_setg(errp, "Unable to find CPU core with core-id: %d", 3776 cc->core_id); 3777 return; 3778 } 3779 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3780 spapr_vcpu_id(spapr, cc->core_id)); 3781 3782 g_assert(drc || !mc->has_hotpluggable_cpus); 3783 3784 if (drc) { 3785 if (!spapr_drc_attach(drc, dev, errp)) { 3786 return; 3787 } 3788 3789 if (hotplugged) { 3790 /* 3791 * Send hotplug notification interrupt to the guest only 3792 * in case of hotplugged CPUs. 3793 */ 3794 spapr_hotplug_req_add_by_index(drc); 3795 } else { 3796 spapr_drc_reset(drc); 3797 } 3798 } 3799 3800 core_slot->cpu = OBJECT(dev); 3801 3802 if (smc->pre_2_10_has_unused_icps) { 3803 for (i = 0; i < cc->nr_threads; i++) { 3804 cs = CPU(core->threads[i]); 3805 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3806 } 3807 } 3808 3809 /* 3810 * Set compatibility mode to match the boot CPU, which was either set 3811 * by the machine reset code or by CAS. 3812 */ 3813 if (hotplugged) { 3814 for (i = 0; i < cc->nr_threads; i++) { 3815 if (ppc_set_compat(core->threads[i], 3816 POWERPC_CPU(first_cpu)->compat_pvr, 3817 errp) < 0) { 3818 return; 3819 } 3820 } 3821 } 3822 } 3823 3824 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3825 Error **errp) 3826 { 3827 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3828 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3829 CPUCore *cc = CPU_CORE(dev); 3830 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3831 const char *type = object_get_typename(OBJECT(dev)); 3832 CPUArchId *core_slot; 3833 int index; 3834 unsigned int smp_threads = machine->smp.threads; 3835 3836 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3837 error_setg(errp, "CPU hotplug not supported for this machine"); 3838 return; 3839 } 3840 3841 if (strcmp(base_core_type, type)) { 3842 error_setg(errp, "CPU core type should be %s", base_core_type); 3843 return; 3844 } 3845 3846 if (cc->core_id % smp_threads) { 3847 error_setg(errp, "invalid core id %d", cc->core_id); 3848 return; 3849 } 3850 3851 /* 3852 * In general we should have homogeneous threads-per-core, but old 3853 * (pre hotplug support) machine types allow the last core to have 3854 * reduced threads as a compatibility hack for when we allowed 3855 * total vcpus not a multiple of threads-per-core. 3856 */ 3857 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3858 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 3859 smp_threads); 3860 return; 3861 } 3862 3863 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3864 if (!core_slot) { 3865 error_setg(errp, "core id %d out of range", cc->core_id); 3866 return; 3867 } 3868 3869 if (core_slot->cpu) { 3870 error_setg(errp, "core %d already populated", cc->core_id); 3871 return; 3872 } 3873 3874 numa_cpu_pre_plug(core_slot, dev, errp); 3875 } 3876 3877 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3878 void *fdt, int *fdt_start_offset, Error **errp) 3879 { 3880 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3881 int intc_phandle; 3882 3883 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3884 if (intc_phandle <= 0) { 3885 return -1; 3886 } 3887 3888 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3889 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3890 return -1; 3891 } 3892 3893 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3894 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3895 3896 return 0; 3897 } 3898 3899 static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3900 Error **errp) 3901 { 3902 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3903 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3904 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3905 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3906 3907 if (dev->hotplugged && !smc->dr_phb_enabled) { 3908 error_setg(errp, "PHB hotplug not supported for this machine"); 3909 return; 3910 } 3911 3912 if (sphb->index == (uint32_t)-1) { 3913 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3914 return; 3915 } 3916 3917 /* 3918 * This will check that sphb->index doesn't exceed the maximum number of 3919 * PHBs for the current machine type. 3920 */ 3921 smc->phb_placement(spapr, sphb->index, 3922 &sphb->buid, &sphb->io_win_addr, 3923 &sphb->mem_win_addr, &sphb->mem64_win_addr, 3924 windows_supported, sphb->dma_liobn, 3925 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 3926 errp); 3927 } 3928 3929 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3930 Error **errp) 3931 { 3932 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3933 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3934 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3935 SpaprDrc *drc; 3936 bool hotplugged = spapr_drc_hotplugged(dev); 3937 3938 if (!smc->dr_phb_enabled) { 3939 return; 3940 } 3941 3942 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3943 /* hotplug hooks should check it's enabled before getting this far */ 3944 assert(drc); 3945 3946 if (!spapr_drc_attach(drc, dev, errp)) { 3947 return; 3948 } 3949 3950 if (hotplugged) { 3951 spapr_hotplug_req_add_by_index(drc); 3952 } else { 3953 spapr_drc_reset(drc); 3954 } 3955 } 3956 3957 void spapr_phb_release(DeviceState *dev) 3958 { 3959 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3960 3961 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3962 object_unparent(OBJECT(dev)); 3963 } 3964 3965 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3966 { 3967 qdev_unrealize(dev); 3968 } 3969 3970 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 3971 DeviceState *dev, Error **errp) 3972 { 3973 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3974 SpaprDrc *drc; 3975 3976 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3977 assert(drc); 3978 3979 if (!spapr_drc_unplug_requested(drc)) { 3980 spapr_drc_detach(drc); 3981 spapr_hotplug_req_remove_by_index(drc); 3982 } 3983 } 3984 3985 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3986 Error **errp) 3987 { 3988 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3989 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 3990 3991 if (spapr->tpm_proxy != NULL) { 3992 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 3993 return; 3994 } 3995 3996 spapr->tpm_proxy = tpm_proxy; 3997 } 3998 3999 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4000 { 4001 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4002 4003 qdev_unrealize(dev); 4004 object_unparent(OBJECT(dev)); 4005 spapr->tpm_proxy = NULL; 4006 } 4007 4008 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4009 DeviceState *dev, Error **errp) 4010 { 4011 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4012 spapr_memory_plug(hotplug_dev, dev, errp); 4013 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4014 spapr_core_plug(hotplug_dev, dev, errp); 4015 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4016 spapr_phb_plug(hotplug_dev, dev, errp); 4017 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4018 spapr_tpm_proxy_plug(hotplug_dev, dev, errp); 4019 } 4020 } 4021 4022 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4023 DeviceState *dev, Error **errp) 4024 { 4025 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4026 spapr_memory_unplug(hotplug_dev, dev); 4027 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4028 spapr_core_unplug(hotplug_dev, dev); 4029 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4030 spapr_phb_unplug(hotplug_dev, dev); 4031 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4032 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4033 } 4034 } 4035 4036 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4037 DeviceState *dev, Error **errp) 4038 { 4039 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4040 MachineClass *mc = MACHINE_GET_CLASS(sms); 4041 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4042 4043 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4044 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 4045 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4046 } else { 4047 /* NOTE: this means there is a window after guest reset, prior to 4048 * CAS negotiation, where unplug requests will fail due to the 4049 * capability not being detected yet. This is a bit different than 4050 * the case with PCI unplug, where the events will be queued and 4051 * eventually handled by the guest after boot 4052 */ 4053 error_setg(errp, "Memory hot unplug not supported for this guest"); 4054 } 4055 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4056 if (!mc->has_hotpluggable_cpus) { 4057 error_setg(errp, "CPU hot unplug not supported on this machine"); 4058 return; 4059 } 4060 spapr_core_unplug_request(hotplug_dev, dev, errp); 4061 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4062 if (!smc->dr_phb_enabled) { 4063 error_setg(errp, "PHB hot unplug not supported on this machine"); 4064 return; 4065 } 4066 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4067 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4068 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4069 } 4070 } 4071 4072 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4073 DeviceState *dev, Error **errp) 4074 { 4075 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4076 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4077 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4078 spapr_core_pre_plug(hotplug_dev, dev, errp); 4079 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4080 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4081 } 4082 } 4083 4084 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4085 DeviceState *dev) 4086 { 4087 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4088 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4089 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4090 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4091 return HOTPLUG_HANDLER(machine); 4092 } 4093 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4094 PCIDevice *pcidev = PCI_DEVICE(dev); 4095 PCIBus *root = pci_device_root_bus(pcidev); 4096 SpaprPhbState *phb = 4097 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4098 TYPE_SPAPR_PCI_HOST_BRIDGE); 4099 4100 if (phb) { 4101 return HOTPLUG_HANDLER(phb); 4102 } 4103 } 4104 return NULL; 4105 } 4106 4107 static CpuInstanceProperties 4108 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4109 { 4110 CPUArchId *core_slot; 4111 MachineClass *mc = MACHINE_GET_CLASS(machine); 4112 4113 /* make sure possible_cpu are intialized */ 4114 mc->possible_cpu_arch_ids(machine); 4115 /* get CPU core slot containing thread that matches cpu_index */ 4116 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4117 assert(core_slot); 4118 return core_slot->props; 4119 } 4120 4121 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4122 { 4123 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4124 } 4125 4126 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4127 { 4128 int i; 4129 unsigned int smp_threads = machine->smp.threads; 4130 unsigned int smp_cpus = machine->smp.cpus; 4131 const char *core_type; 4132 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4133 MachineClass *mc = MACHINE_GET_CLASS(machine); 4134 4135 if (!mc->has_hotpluggable_cpus) { 4136 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4137 } 4138 if (machine->possible_cpus) { 4139 assert(machine->possible_cpus->len == spapr_max_cores); 4140 return machine->possible_cpus; 4141 } 4142 4143 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4144 if (!core_type) { 4145 error_report("Unable to find sPAPR CPU Core definition"); 4146 exit(1); 4147 } 4148 4149 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4150 sizeof(CPUArchId) * spapr_max_cores); 4151 machine->possible_cpus->len = spapr_max_cores; 4152 for (i = 0; i < machine->possible_cpus->len; i++) { 4153 int core_id = i * smp_threads; 4154 4155 machine->possible_cpus->cpus[i].type = core_type; 4156 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4157 machine->possible_cpus->cpus[i].arch_id = core_id; 4158 machine->possible_cpus->cpus[i].props.has_core_id = true; 4159 machine->possible_cpus->cpus[i].props.core_id = core_id; 4160 } 4161 return machine->possible_cpus; 4162 } 4163 4164 static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4165 uint64_t *buid, hwaddr *pio, 4166 hwaddr *mmio32, hwaddr *mmio64, 4167 unsigned n_dma, uint32_t *liobns, 4168 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4169 { 4170 /* 4171 * New-style PHB window placement. 4172 * 4173 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4174 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4175 * windows. 4176 * 4177 * Some guest kernels can't work with MMIO windows above 1<<46 4178 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4179 * 4180 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4181 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4182 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4183 * 1TiB 64-bit MMIO windows for each PHB. 4184 */ 4185 const uint64_t base_buid = 0x800000020000000ULL; 4186 int i; 4187 4188 /* Sanity check natural alignments */ 4189 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4190 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4191 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4192 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4193 /* Sanity check bounds */ 4194 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4195 SPAPR_PCI_MEM32_WIN_SIZE); 4196 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4197 SPAPR_PCI_MEM64_WIN_SIZE); 4198 4199 if (index >= SPAPR_MAX_PHBS) { 4200 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4201 SPAPR_MAX_PHBS - 1); 4202 return; 4203 } 4204 4205 *buid = base_buid + index; 4206 for (i = 0; i < n_dma; ++i) { 4207 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4208 } 4209 4210 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4211 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4212 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4213 4214 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4215 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4216 } 4217 4218 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4219 { 4220 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4221 4222 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4223 } 4224 4225 static void spapr_ics_resend(XICSFabric *dev) 4226 { 4227 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4228 4229 ics_resend(spapr->ics); 4230 } 4231 4232 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4233 { 4234 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4235 4236 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4237 } 4238 4239 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4240 Monitor *mon) 4241 { 4242 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4243 4244 spapr_irq_print_info(spapr, mon); 4245 monitor_printf(mon, "irqchip: %s\n", 4246 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4247 } 4248 4249 /* 4250 * This is a XIVE only operation 4251 */ 4252 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4253 uint8_t nvt_blk, uint32_t nvt_idx, 4254 bool cam_ignore, uint8_t priority, 4255 uint32_t logic_serv, XiveTCTXMatch *match) 4256 { 4257 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4258 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4259 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4260 int count; 4261 4262 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4263 priority, logic_serv, match); 4264 if (count < 0) { 4265 return count; 4266 } 4267 4268 /* 4269 * When we implement the save and restore of the thread interrupt 4270 * contexts in the enter/exit CPU handlers of the machine and the 4271 * escalations in QEMU, we should be able to handle non dispatched 4272 * vCPUs. 4273 * 4274 * Until this is done, the sPAPR machine should find at least one 4275 * matching context always. 4276 */ 4277 if (count == 0) { 4278 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4279 nvt_blk, nvt_idx); 4280 } 4281 4282 return count; 4283 } 4284 4285 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4286 { 4287 return cpu->vcpu_id; 4288 } 4289 4290 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4291 { 4292 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4293 MachineState *ms = MACHINE(spapr); 4294 int vcpu_id; 4295 4296 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4297 4298 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4299 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4300 error_append_hint(errp, "Adjust the number of cpus to %d " 4301 "or try to raise the number of threads per core\n", 4302 vcpu_id * ms->smp.threads / spapr->vsmt); 4303 return false; 4304 } 4305 4306 cpu->vcpu_id = vcpu_id; 4307 return true; 4308 } 4309 4310 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4311 { 4312 CPUState *cs; 4313 4314 CPU_FOREACH(cs) { 4315 PowerPCCPU *cpu = POWERPC_CPU(cs); 4316 4317 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4318 return cpu; 4319 } 4320 } 4321 4322 return NULL; 4323 } 4324 4325 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4326 { 4327 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4328 4329 /* These are only called by TCG, KVM maintains dispatch state */ 4330 4331 spapr_cpu->prod = false; 4332 if (spapr_cpu->vpa_addr) { 4333 CPUState *cs = CPU(cpu); 4334 uint32_t dispatch; 4335 4336 dispatch = ldl_be_phys(cs->as, 4337 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4338 dispatch++; 4339 if ((dispatch & 1) != 0) { 4340 qemu_log_mask(LOG_GUEST_ERROR, 4341 "VPA: incorrect dispatch counter value for " 4342 "dispatched partition %u, correcting.\n", dispatch); 4343 dispatch++; 4344 } 4345 stl_be_phys(cs->as, 4346 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4347 } 4348 } 4349 4350 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4351 { 4352 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4353 4354 if (spapr_cpu->vpa_addr) { 4355 CPUState *cs = CPU(cpu); 4356 uint32_t dispatch; 4357 4358 dispatch = ldl_be_phys(cs->as, 4359 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4360 dispatch++; 4361 if ((dispatch & 1) != 1) { 4362 qemu_log_mask(LOG_GUEST_ERROR, 4363 "VPA: incorrect dispatch counter value for " 4364 "preempted partition %u, correcting.\n", dispatch); 4365 dispatch++; 4366 } 4367 stl_be_phys(cs->as, 4368 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4369 } 4370 } 4371 4372 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4373 { 4374 MachineClass *mc = MACHINE_CLASS(oc); 4375 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4376 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4377 NMIClass *nc = NMI_CLASS(oc); 4378 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4379 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4380 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4381 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4382 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4383 4384 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4385 mc->ignore_boot_device_suffixes = true; 4386 4387 /* 4388 * We set up the default / latest behaviour here. The class_init 4389 * functions for the specific versioned machine types can override 4390 * these details for backwards compatibility 4391 */ 4392 mc->init = spapr_machine_init; 4393 mc->reset = spapr_machine_reset; 4394 mc->block_default_type = IF_SCSI; 4395 mc->max_cpus = 1024; 4396 mc->no_parallel = 1; 4397 mc->default_boot_order = ""; 4398 mc->default_ram_size = 512 * MiB; 4399 mc->default_ram_id = "ppc_spapr.ram"; 4400 mc->default_display = "std"; 4401 mc->kvm_type = spapr_kvm_type; 4402 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4403 mc->pci_allow_0_address = true; 4404 assert(!mc->get_hotplug_handler); 4405 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4406 hc->pre_plug = spapr_machine_device_pre_plug; 4407 hc->plug = spapr_machine_device_plug; 4408 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4409 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4410 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4411 hc->unplug_request = spapr_machine_device_unplug_request; 4412 hc->unplug = spapr_machine_device_unplug; 4413 4414 smc->dr_lmb_enabled = true; 4415 smc->update_dt_enabled = true; 4416 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4417 mc->has_hotpluggable_cpus = true; 4418 mc->nvdimm_supported = true; 4419 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4420 fwc->get_dev_path = spapr_get_fw_dev_path; 4421 nc->nmi_monitor_handler = spapr_nmi; 4422 smc->phb_placement = spapr_phb_placement; 4423 vhc->hypercall = emulate_spapr_hypercall; 4424 vhc->hpt_mask = spapr_hpt_mask; 4425 vhc->map_hptes = spapr_map_hptes; 4426 vhc->unmap_hptes = spapr_unmap_hptes; 4427 vhc->hpte_set_c = spapr_hpte_set_c; 4428 vhc->hpte_set_r = spapr_hpte_set_r; 4429 vhc->get_pate = spapr_get_pate; 4430 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4431 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4432 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4433 xic->ics_get = spapr_ics_get; 4434 xic->ics_resend = spapr_ics_resend; 4435 xic->icp_get = spapr_icp_get; 4436 ispc->print_info = spapr_pic_print_info; 4437 /* Force NUMA node memory size to be a multiple of 4438 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4439 * in which LMBs are represented and hot-added 4440 */ 4441 mc->numa_mem_align_shift = 28; 4442 mc->auto_enable_numa = true; 4443 4444 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4445 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4446 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4447 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4448 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4449 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4450 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4451 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4452 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4453 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4454 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4455 spapr_caps_add_properties(smc); 4456 smc->irq = &spapr_irq_dual; 4457 smc->dr_phb_enabled = true; 4458 smc->linux_pci_probe = true; 4459 smc->smp_threads_vsmt = true; 4460 smc->nr_xirqs = SPAPR_NR_XIRQS; 4461 xfc->match_nvt = spapr_match_nvt; 4462 } 4463 4464 static const TypeInfo spapr_machine_info = { 4465 .name = TYPE_SPAPR_MACHINE, 4466 .parent = TYPE_MACHINE, 4467 .abstract = true, 4468 .instance_size = sizeof(SpaprMachineState), 4469 .instance_init = spapr_instance_init, 4470 .instance_finalize = spapr_machine_finalizefn, 4471 .class_size = sizeof(SpaprMachineClass), 4472 .class_init = spapr_machine_class_init, 4473 .interfaces = (InterfaceInfo[]) { 4474 { TYPE_FW_PATH_PROVIDER }, 4475 { TYPE_NMI }, 4476 { TYPE_HOTPLUG_HANDLER }, 4477 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4478 { TYPE_XICS_FABRIC }, 4479 { TYPE_INTERRUPT_STATS_PROVIDER }, 4480 { TYPE_XIVE_FABRIC }, 4481 { } 4482 }, 4483 }; 4484 4485 static void spapr_machine_latest_class_options(MachineClass *mc) 4486 { 4487 mc->alias = "pseries"; 4488 mc->is_default = true; 4489 } 4490 4491 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4492 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4493 void *data) \ 4494 { \ 4495 MachineClass *mc = MACHINE_CLASS(oc); \ 4496 spapr_machine_##suffix##_class_options(mc); \ 4497 if (latest) { \ 4498 spapr_machine_latest_class_options(mc); \ 4499 } \ 4500 } \ 4501 static const TypeInfo spapr_machine_##suffix##_info = { \ 4502 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4503 .parent = TYPE_SPAPR_MACHINE, \ 4504 .class_init = spapr_machine_##suffix##_class_init, \ 4505 }; \ 4506 static void spapr_machine_register_##suffix(void) \ 4507 { \ 4508 type_register(&spapr_machine_##suffix##_info); \ 4509 } \ 4510 type_init(spapr_machine_register_##suffix) 4511 4512 /* 4513 * pseries-5.2 4514 */ 4515 static void spapr_machine_5_2_class_options(MachineClass *mc) 4516 { 4517 /* Defaults for the latest behaviour inherited from the base class */ 4518 } 4519 4520 DEFINE_SPAPR_MACHINE(5_2, "5.2", true); 4521 4522 /* 4523 * pseries-5.1 4524 */ 4525 static void spapr_machine_5_1_class_options(MachineClass *mc) 4526 { 4527 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4528 4529 spapr_machine_5_2_class_options(mc); 4530 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4531 smc->pre_5_2_numa_associativity = true; 4532 } 4533 4534 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4535 4536 /* 4537 * pseries-5.0 4538 */ 4539 static void spapr_machine_5_0_class_options(MachineClass *mc) 4540 { 4541 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4542 static GlobalProperty compat[] = { 4543 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4544 }; 4545 4546 spapr_machine_5_1_class_options(mc); 4547 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4548 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4549 mc->numa_mem_supported = true; 4550 smc->pre_5_1_assoc_refpoints = true; 4551 } 4552 4553 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4554 4555 /* 4556 * pseries-4.2 4557 */ 4558 static void spapr_machine_4_2_class_options(MachineClass *mc) 4559 { 4560 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4561 4562 spapr_machine_5_0_class_options(mc); 4563 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4564 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4565 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4566 smc->rma_limit = 16 * GiB; 4567 mc->nvdimm_supported = false; 4568 } 4569 4570 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4571 4572 /* 4573 * pseries-4.1 4574 */ 4575 static void spapr_machine_4_1_class_options(MachineClass *mc) 4576 { 4577 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4578 static GlobalProperty compat[] = { 4579 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4580 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4581 }; 4582 4583 spapr_machine_4_2_class_options(mc); 4584 smc->linux_pci_probe = false; 4585 smc->smp_threads_vsmt = false; 4586 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4587 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4588 } 4589 4590 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4591 4592 /* 4593 * pseries-4.0 4594 */ 4595 static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4596 uint64_t *buid, hwaddr *pio, 4597 hwaddr *mmio32, hwaddr *mmio64, 4598 unsigned n_dma, uint32_t *liobns, 4599 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4600 { 4601 spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns, 4602 nv2gpa, nv2atsd, errp); 4603 *nv2gpa = 0; 4604 *nv2atsd = 0; 4605 } 4606 4607 static void spapr_machine_4_0_class_options(MachineClass *mc) 4608 { 4609 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4610 4611 spapr_machine_4_1_class_options(mc); 4612 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4613 smc->phb_placement = phb_placement_4_0; 4614 smc->irq = &spapr_irq_xics; 4615 smc->pre_4_1_migration = true; 4616 } 4617 4618 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4619 4620 /* 4621 * pseries-3.1 4622 */ 4623 static void spapr_machine_3_1_class_options(MachineClass *mc) 4624 { 4625 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4626 4627 spapr_machine_4_0_class_options(mc); 4628 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4629 4630 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4631 smc->update_dt_enabled = false; 4632 smc->dr_phb_enabled = false; 4633 smc->broken_host_serial_model = true; 4634 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4635 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4636 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4637 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4638 } 4639 4640 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4641 4642 /* 4643 * pseries-3.0 4644 */ 4645 4646 static void spapr_machine_3_0_class_options(MachineClass *mc) 4647 { 4648 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4649 4650 spapr_machine_3_1_class_options(mc); 4651 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4652 4653 smc->legacy_irq_allocation = true; 4654 smc->nr_xirqs = 0x400; 4655 smc->irq = &spapr_irq_xics_legacy; 4656 } 4657 4658 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4659 4660 /* 4661 * pseries-2.12 4662 */ 4663 static void spapr_machine_2_12_class_options(MachineClass *mc) 4664 { 4665 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4666 static GlobalProperty compat[] = { 4667 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4668 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4669 }; 4670 4671 spapr_machine_3_0_class_options(mc); 4672 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4673 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4674 4675 /* We depend on kvm_enabled() to choose a default value for the 4676 * hpt-max-page-size capability. Of course we can't do it here 4677 * because this is too early and the HW accelerator isn't initialzed 4678 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4679 */ 4680 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4681 } 4682 4683 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4684 4685 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4686 { 4687 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4688 4689 spapr_machine_2_12_class_options(mc); 4690 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4691 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4692 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4693 } 4694 4695 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4696 4697 /* 4698 * pseries-2.11 4699 */ 4700 4701 static void spapr_machine_2_11_class_options(MachineClass *mc) 4702 { 4703 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4704 4705 spapr_machine_2_12_class_options(mc); 4706 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4707 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4708 } 4709 4710 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4711 4712 /* 4713 * pseries-2.10 4714 */ 4715 4716 static void spapr_machine_2_10_class_options(MachineClass *mc) 4717 { 4718 spapr_machine_2_11_class_options(mc); 4719 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4720 } 4721 4722 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4723 4724 /* 4725 * pseries-2.9 4726 */ 4727 4728 static void spapr_machine_2_9_class_options(MachineClass *mc) 4729 { 4730 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4731 static GlobalProperty compat[] = { 4732 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4733 }; 4734 4735 spapr_machine_2_10_class_options(mc); 4736 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4737 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4738 smc->pre_2_10_has_unused_icps = true; 4739 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4740 } 4741 4742 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4743 4744 /* 4745 * pseries-2.8 4746 */ 4747 4748 static void spapr_machine_2_8_class_options(MachineClass *mc) 4749 { 4750 static GlobalProperty compat[] = { 4751 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4752 }; 4753 4754 spapr_machine_2_9_class_options(mc); 4755 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4756 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4757 mc->numa_mem_align_shift = 23; 4758 } 4759 4760 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4761 4762 /* 4763 * pseries-2.7 4764 */ 4765 4766 static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4767 uint64_t *buid, hwaddr *pio, 4768 hwaddr *mmio32, hwaddr *mmio64, 4769 unsigned n_dma, uint32_t *liobns, 4770 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4771 { 4772 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4773 const uint64_t base_buid = 0x800000020000000ULL; 4774 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4775 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4776 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4777 const uint32_t max_index = 255; 4778 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4779 4780 uint64_t ram_top = MACHINE(spapr)->ram_size; 4781 hwaddr phb0_base, phb_base; 4782 int i; 4783 4784 /* Do we have device memory? */ 4785 if (MACHINE(spapr)->maxram_size > ram_top) { 4786 /* Can't just use maxram_size, because there may be an 4787 * alignment gap between normal and device memory regions 4788 */ 4789 ram_top = MACHINE(spapr)->device_memory->base + 4790 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4791 } 4792 4793 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4794 4795 if (index > max_index) { 4796 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4797 max_index); 4798 return; 4799 } 4800 4801 *buid = base_buid + index; 4802 for (i = 0; i < n_dma; ++i) { 4803 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4804 } 4805 4806 phb_base = phb0_base + index * phb_spacing; 4807 *pio = phb_base + pio_offset; 4808 *mmio32 = phb_base + mmio_offset; 4809 /* 4810 * We don't set the 64-bit MMIO window, relying on the PHB's 4811 * fallback behaviour of automatically splitting a large "32-bit" 4812 * window into contiguous 32-bit and 64-bit windows 4813 */ 4814 4815 *nv2gpa = 0; 4816 *nv2atsd = 0; 4817 } 4818 4819 static void spapr_machine_2_7_class_options(MachineClass *mc) 4820 { 4821 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4822 static GlobalProperty compat[] = { 4823 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4824 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4825 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4826 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4827 }; 4828 4829 spapr_machine_2_8_class_options(mc); 4830 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4831 mc->default_machine_opts = "modern-hotplug-events=off"; 4832 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4833 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4834 smc->phb_placement = phb_placement_2_7; 4835 } 4836 4837 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4838 4839 /* 4840 * pseries-2.6 4841 */ 4842 4843 static void spapr_machine_2_6_class_options(MachineClass *mc) 4844 { 4845 static GlobalProperty compat[] = { 4846 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4847 }; 4848 4849 spapr_machine_2_7_class_options(mc); 4850 mc->has_hotpluggable_cpus = false; 4851 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4852 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4853 } 4854 4855 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4856 4857 /* 4858 * pseries-2.5 4859 */ 4860 4861 static void spapr_machine_2_5_class_options(MachineClass *mc) 4862 { 4863 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4864 static GlobalProperty compat[] = { 4865 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4866 }; 4867 4868 spapr_machine_2_6_class_options(mc); 4869 smc->use_ohci_by_default = true; 4870 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4871 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4872 } 4873 4874 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4875 4876 /* 4877 * pseries-2.4 4878 */ 4879 4880 static void spapr_machine_2_4_class_options(MachineClass *mc) 4881 { 4882 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4883 4884 spapr_machine_2_5_class_options(mc); 4885 smc->dr_lmb_enabled = false; 4886 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4887 } 4888 4889 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4890 4891 /* 4892 * pseries-2.3 4893 */ 4894 4895 static void spapr_machine_2_3_class_options(MachineClass *mc) 4896 { 4897 static GlobalProperty compat[] = { 4898 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4899 }; 4900 spapr_machine_2_4_class_options(mc); 4901 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4902 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4903 } 4904 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4905 4906 /* 4907 * pseries-2.2 4908 */ 4909 4910 static void spapr_machine_2_2_class_options(MachineClass *mc) 4911 { 4912 static GlobalProperty compat[] = { 4913 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4914 }; 4915 4916 spapr_machine_2_3_class_options(mc); 4917 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4918 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4919 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4920 } 4921 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4922 4923 /* 4924 * pseries-2.1 4925 */ 4926 4927 static void spapr_machine_2_1_class_options(MachineClass *mc) 4928 { 4929 spapr_machine_2_2_class_options(mc); 4930 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4931 } 4932 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4933 4934 static void spapr_machine_register_types(void) 4935 { 4936 type_register_static(&spapr_machine_info); 4937 } 4938 4939 type_init(spapr_machine_register_types) 4940