1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qemu/datadir.h" 30 #include "qapi/error.h" 31 #include "qapi/qapi-events-machine.h" 32 #include "qapi/qapi-events-qdev.h" 33 #include "qapi/visitor.h" 34 #include "sysemu/sysemu.h" 35 #include "sysemu/hostmem.h" 36 #include "sysemu/numa.h" 37 #include "sysemu/qtest.h" 38 #include "sysemu/reset.h" 39 #include "sysemu/runstate.h" 40 #include "qemu/log.h" 41 #include "hw/fw-path-provider.h" 42 #include "elf.h" 43 #include "net/net.h" 44 #include "sysemu/device_tree.h" 45 #include "sysemu/cpus.h" 46 #include "sysemu/hw_accel.h" 47 #include "kvm_ppc.h" 48 #include "migration/misc.h" 49 #include "migration/qemu-file-types.h" 50 #include "migration/global_state.h" 51 #include "migration/register.h" 52 #include "migration/blocker.h" 53 #include "mmu-hash64.h" 54 #include "mmu-book3s-v3.h" 55 #include "cpu-models.h" 56 #include "hw/core/cpu.h" 57 58 #include "hw/ppc/ppc.h" 59 #include "hw/loader.h" 60 61 #include "hw/ppc/fdt.h" 62 #include "hw/ppc/spapr.h" 63 #include "hw/ppc/spapr_vio.h" 64 #include "hw/qdev-properties.h" 65 #include "hw/pci-host/spapr.h" 66 #include "hw/pci/msi.h" 67 68 #include "hw/pci/pci.h" 69 #include "hw/scsi/scsi.h" 70 #include "hw/virtio/virtio-scsi.h" 71 #include "hw/virtio/vhost-scsi-common.h" 72 73 #include "exec/ram_addr.h" 74 #include "hw/usb.h" 75 #include "qemu/config-file.h" 76 #include "qemu/error-report.h" 77 #include "trace.h" 78 #include "hw/nmi.h" 79 #include "hw/intc/intc.h" 80 81 #include "hw/ppc/spapr_cpu_core.h" 82 #include "hw/mem/memory-device.h" 83 #include "hw/ppc/spapr_tpm_proxy.h" 84 #include "hw/ppc/spapr_nvdimm.h" 85 #include "hw/ppc/spapr_numa.h" 86 #include "hw/ppc/pef.h" 87 88 #include "monitor/monitor.h" 89 90 #include <libfdt.h> 91 92 /* SLOF memory layout: 93 * 94 * SLOF raw image loaded at 0, copies its romfs right below the flat 95 * device-tree, then position SLOF itself 31M below that 96 * 97 * So we set FW_OVERHEAD to 40MB which should account for all of that 98 * and more 99 * 100 * We load our kernel at 4M, leaving space for SLOF initial image 101 */ 102 #define FDT_MAX_ADDR 0x80000000 /* FDT must stay below that */ 103 #define FW_MAX_SIZE 0x400000 104 #define FW_FILE_NAME "slof.bin" 105 #define FW_FILE_NAME_VOF "vof.bin" 106 #define FW_OVERHEAD 0x2800000 107 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 108 109 #define MIN_RMA_SLOF (128 * MiB) 110 111 #define PHANDLE_INTC 0x00001111 112 113 /* These two functions implement the VCPU id numbering: one to compute them 114 * all and one to identify thread 0 of a VCORE. Any change to the first one 115 * is likely to have an impact on the second one, so let's keep them close. 116 */ 117 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 118 { 119 MachineState *ms = MACHINE(spapr); 120 unsigned int smp_threads = ms->smp.threads; 121 122 assert(spapr->vsmt); 123 return 124 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 125 } 126 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 127 PowerPCCPU *cpu) 128 { 129 assert(spapr->vsmt); 130 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 131 } 132 133 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 134 { 135 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 136 * and newer QEMUs don't even have them. In both cases, we don't want 137 * to send anything on the wire. 138 */ 139 return false; 140 } 141 142 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 143 .name = "icp/server", 144 .version_id = 1, 145 .minimum_version_id = 1, 146 .needed = pre_2_10_vmstate_dummy_icp_needed, 147 .fields = (VMStateField[]) { 148 VMSTATE_UNUSED(4), /* uint32_t xirr */ 149 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 150 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 151 VMSTATE_END_OF_LIST() 152 }, 153 }; 154 155 static void pre_2_10_vmstate_register_dummy_icp(int i) 156 { 157 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 158 (void *)(uintptr_t) i); 159 } 160 161 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 162 { 163 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 164 (void *)(uintptr_t) i); 165 } 166 167 int spapr_max_server_number(SpaprMachineState *spapr) 168 { 169 MachineState *ms = MACHINE(spapr); 170 171 assert(spapr->vsmt); 172 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 173 } 174 175 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 176 int smt_threads) 177 { 178 int i, ret = 0; 179 uint32_t servers_prop[smt_threads]; 180 uint32_t gservers_prop[smt_threads * 2]; 181 int index = spapr_get_vcpu_id(cpu); 182 183 if (cpu->compat_pvr) { 184 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 185 if (ret < 0) { 186 return ret; 187 } 188 } 189 190 /* Build interrupt servers and gservers properties */ 191 for (i = 0; i < smt_threads; i++) { 192 servers_prop[i] = cpu_to_be32(index + i); 193 /* Hack, direct the group queues back to cpu 0 */ 194 gservers_prop[i*2] = cpu_to_be32(index + i); 195 gservers_prop[i*2 + 1] = 0; 196 } 197 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 198 servers_prop, sizeof(servers_prop)); 199 if (ret < 0) { 200 return ret; 201 } 202 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 203 gservers_prop, sizeof(gservers_prop)); 204 205 return ret; 206 } 207 208 static void spapr_dt_pa_features(SpaprMachineState *spapr, 209 PowerPCCPU *cpu, 210 void *fdt, int offset) 211 { 212 uint8_t pa_features_206[] = { 6, 0, 213 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 214 uint8_t pa_features_207[] = { 24, 0, 215 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 216 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 217 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 218 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 219 uint8_t pa_features_300[] = { 66, 0, 220 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 221 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 222 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 223 /* 6: DS207 */ 224 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 225 /* 16: Vector */ 226 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 227 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 228 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 229 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 230 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 231 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 232 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 233 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 235 /* 42: PM, 44: PC RA, 46: SC vec'd */ 236 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 237 /* 48: SIMD, 50: QP BFP, 52: String */ 238 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 239 /* 54: DecFP, 56: DecI, 58: SHA */ 240 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 241 /* 60: NM atomic, 62: RNG */ 242 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 243 }; 244 uint8_t *pa_features = NULL; 245 size_t pa_size; 246 247 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 248 pa_features = pa_features_206; 249 pa_size = sizeof(pa_features_206); 250 } 251 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 252 pa_features = pa_features_207; 253 pa_size = sizeof(pa_features_207); 254 } 255 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 256 pa_features = pa_features_300; 257 pa_size = sizeof(pa_features_300); 258 } 259 if (!pa_features) { 260 return; 261 } 262 263 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 264 /* 265 * Note: we keep CI large pages off by default because a 64K capable 266 * guest provisioned with large pages might otherwise try to map a qemu 267 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 268 * even if that qemu runs on a 4k host. 269 * We dd this bit back here if we are confident this is not an issue 270 */ 271 pa_features[3] |= 0x20; 272 } 273 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 274 pa_features[24] |= 0x80; /* Transactional memory support */ 275 } 276 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 277 /* Workaround for broken kernels that attempt (guest) radix 278 * mode when they can't handle it, if they see the radix bit set 279 * in pa-features. So hide it from them. */ 280 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 281 } 282 283 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 284 } 285 286 static hwaddr spapr_node0_size(MachineState *machine) 287 { 288 if (machine->numa_state->num_nodes) { 289 int i; 290 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 291 if (machine->numa_state->nodes[i].node_mem) { 292 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 293 machine->ram_size); 294 } 295 } 296 } 297 return machine->ram_size; 298 } 299 300 static void add_str(GString *s, const gchar *s1) 301 { 302 g_string_append_len(s, s1, strlen(s1) + 1); 303 } 304 305 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 306 hwaddr start, hwaddr size) 307 { 308 char mem_name[32]; 309 uint64_t mem_reg_property[2]; 310 int off; 311 312 mem_reg_property[0] = cpu_to_be64(start); 313 mem_reg_property[1] = cpu_to_be64(size); 314 315 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 316 off = fdt_add_subnode(fdt, 0, mem_name); 317 _FDT(off); 318 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 319 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 320 sizeof(mem_reg_property)))); 321 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 322 return off; 323 } 324 325 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 326 { 327 MemoryDeviceInfoList *info; 328 329 for (info = list; info; info = info->next) { 330 MemoryDeviceInfo *value = info->value; 331 332 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 333 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 334 335 if (addr >= pcdimm_info->addr && 336 addr < (pcdimm_info->addr + pcdimm_info->size)) { 337 return pcdimm_info->node; 338 } 339 } 340 } 341 342 return -1; 343 } 344 345 struct sPAPRDrconfCellV2 { 346 uint32_t seq_lmbs; 347 uint64_t base_addr; 348 uint32_t drc_index; 349 uint32_t aa_index; 350 uint32_t flags; 351 } QEMU_PACKED; 352 353 typedef struct DrconfCellQueue { 354 struct sPAPRDrconfCellV2 cell; 355 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 356 } DrconfCellQueue; 357 358 static DrconfCellQueue * 359 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 360 uint32_t drc_index, uint32_t aa_index, 361 uint32_t flags) 362 { 363 DrconfCellQueue *elem; 364 365 elem = g_malloc0(sizeof(*elem)); 366 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 367 elem->cell.base_addr = cpu_to_be64(base_addr); 368 elem->cell.drc_index = cpu_to_be32(drc_index); 369 elem->cell.aa_index = cpu_to_be32(aa_index); 370 elem->cell.flags = cpu_to_be32(flags); 371 372 return elem; 373 } 374 375 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 376 int offset, MemoryDeviceInfoList *dimms) 377 { 378 MachineState *machine = MACHINE(spapr); 379 uint8_t *int_buf, *cur_index; 380 int ret; 381 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 382 uint64_t addr, cur_addr, size; 383 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 384 uint64_t mem_end = machine->device_memory->base + 385 memory_region_size(&machine->device_memory->mr); 386 uint32_t node, buf_len, nr_entries = 0; 387 SpaprDrc *drc; 388 DrconfCellQueue *elem, *next; 389 MemoryDeviceInfoList *info; 390 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 391 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 392 393 /* Entry to cover RAM and the gap area */ 394 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 395 SPAPR_LMB_FLAGS_RESERVED | 396 SPAPR_LMB_FLAGS_DRC_INVALID); 397 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 398 nr_entries++; 399 400 cur_addr = machine->device_memory->base; 401 for (info = dimms; info; info = info->next) { 402 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 403 404 addr = di->addr; 405 size = di->size; 406 node = di->node; 407 408 /* 409 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 410 * area is marked hotpluggable in the next iteration for the bigger 411 * chunk including the NVDIMM occupied area. 412 */ 413 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 414 continue; 415 416 /* Entry for hot-pluggable area */ 417 if (cur_addr < addr) { 418 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 419 g_assert(drc); 420 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 421 cur_addr, spapr_drc_index(drc), -1, 0); 422 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 423 nr_entries++; 424 } 425 426 /* Entry for DIMM */ 427 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 428 g_assert(drc); 429 elem = spapr_get_drconf_cell(size / lmb_size, addr, 430 spapr_drc_index(drc), node, 431 (SPAPR_LMB_FLAGS_ASSIGNED | 432 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 433 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 434 nr_entries++; 435 cur_addr = addr + size; 436 } 437 438 /* Entry for remaining hotpluggable area */ 439 if (cur_addr < mem_end) { 440 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 441 g_assert(drc); 442 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 443 cur_addr, spapr_drc_index(drc), -1, 0); 444 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 445 nr_entries++; 446 } 447 448 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 449 int_buf = cur_index = g_malloc0(buf_len); 450 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 451 cur_index += sizeof(nr_entries); 452 453 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 454 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 455 cur_index += sizeof(elem->cell); 456 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 457 g_free(elem); 458 } 459 460 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 461 g_free(int_buf); 462 if (ret < 0) { 463 return -1; 464 } 465 return 0; 466 } 467 468 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 469 int offset, MemoryDeviceInfoList *dimms) 470 { 471 MachineState *machine = MACHINE(spapr); 472 int i, ret; 473 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 474 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 475 uint32_t nr_lmbs = (machine->device_memory->base + 476 memory_region_size(&machine->device_memory->mr)) / 477 lmb_size; 478 uint32_t *int_buf, *cur_index, buf_len; 479 480 /* 481 * Allocate enough buffer size to fit in ibm,dynamic-memory 482 */ 483 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 484 cur_index = int_buf = g_malloc0(buf_len); 485 int_buf[0] = cpu_to_be32(nr_lmbs); 486 cur_index++; 487 for (i = 0; i < nr_lmbs; i++) { 488 uint64_t addr = i * lmb_size; 489 uint32_t *dynamic_memory = cur_index; 490 491 if (i >= device_lmb_start) { 492 SpaprDrc *drc; 493 494 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 495 g_assert(drc); 496 497 dynamic_memory[0] = cpu_to_be32(addr >> 32); 498 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 499 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 500 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 501 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 502 if (memory_region_present(get_system_memory(), addr)) { 503 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 504 } else { 505 dynamic_memory[5] = cpu_to_be32(0); 506 } 507 } else { 508 /* 509 * LMB information for RMA, boot time RAM and gap b/n RAM and 510 * device memory region -- all these are marked as reserved 511 * and as having no valid DRC. 512 */ 513 dynamic_memory[0] = cpu_to_be32(addr >> 32); 514 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 515 dynamic_memory[2] = cpu_to_be32(0); 516 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 517 dynamic_memory[4] = cpu_to_be32(-1); 518 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 519 SPAPR_LMB_FLAGS_DRC_INVALID); 520 } 521 522 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 523 } 524 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 525 g_free(int_buf); 526 if (ret < 0) { 527 return -1; 528 } 529 return 0; 530 } 531 532 /* 533 * Adds ibm,dynamic-reconfiguration-memory node. 534 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 535 * of this device tree node. 536 */ 537 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 538 void *fdt) 539 { 540 MachineState *machine = MACHINE(spapr); 541 int ret, offset; 542 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 543 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 544 cpu_to_be32(lmb_size & 0xffffffff)}; 545 MemoryDeviceInfoList *dimms = NULL; 546 547 /* 548 * Don't create the node if there is no device memory 549 */ 550 if (machine->ram_size == machine->maxram_size) { 551 return 0; 552 } 553 554 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 555 556 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 557 sizeof(prop_lmb_size)); 558 if (ret < 0) { 559 return ret; 560 } 561 562 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 563 if (ret < 0) { 564 return ret; 565 } 566 567 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 568 if (ret < 0) { 569 return ret; 570 } 571 572 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 573 dimms = qmp_memory_device_list(); 574 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 575 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 576 } else { 577 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 578 } 579 qapi_free_MemoryDeviceInfoList(dimms); 580 581 if (ret < 0) { 582 return ret; 583 } 584 585 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 586 587 return ret; 588 } 589 590 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 591 { 592 MachineState *machine = MACHINE(spapr); 593 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 594 hwaddr mem_start, node_size; 595 int i, nb_nodes = machine->numa_state->num_nodes; 596 NodeInfo *nodes = machine->numa_state->nodes; 597 598 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 599 if (!nodes[i].node_mem) { 600 continue; 601 } 602 if (mem_start >= machine->ram_size) { 603 node_size = 0; 604 } else { 605 node_size = nodes[i].node_mem; 606 if (node_size > machine->ram_size - mem_start) { 607 node_size = machine->ram_size - mem_start; 608 } 609 } 610 if (!mem_start) { 611 /* spapr_machine_init() checks for rma_size <= node0_size 612 * already */ 613 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 614 mem_start += spapr->rma_size; 615 node_size -= spapr->rma_size; 616 } 617 for ( ; node_size; ) { 618 hwaddr sizetmp = pow2floor(node_size); 619 620 /* mem_start != 0 here */ 621 if (ctzl(mem_start) < ctzl(sizetmp)) { 622 sizetmp = 1ULL << ctzl(mem_start); 623 } 624 625 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 626 node_size -= sizetmp; 627 mem_start += sizetmp; 628 } 629 } 630 631 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 632 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 633 int ret; 634 635 g_assert(smc->dr_lmb_enabled); 636 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 637 if (ret) { 638 return ret; 639 } 640 } 641 642 return 0; 643 } 644 645 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 646 SpaprMachineState *spapr) 647 { 648 MachineState *ms = MACHINE(spapr); 649 PowerPCCPU *cpu = POWERPC_CPU(cs); 650 CPUPPCState *env = &cpu->env; 651 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 652 int index = spapr_get_vcpu_id(cpu); 653 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 654 0xffffffff, 0xffffffff}; 655 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 656 : SPAPR_TIMEBASE_FREQ; 657 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 658 uint32_t page_sizes_prop[64]; 659 size_t page_sizes_prop_size; 660 unsigned int smp_threads = ms->smp.threads; 661 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 662 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 663 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 664 SpaprDrc *drc; 665 int drc_index; 666 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 667 int i; 668 669 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 670 if (drc) { 671 drc_index = spapr_drc_index(drc); 672 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 673 } 674 675 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 676 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 677 678 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 679 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 680 env->dcache_line_size))); 681 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 682 env->dcache_line_size))); 683 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 684 env->icache_line_size))); 685 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 686 env->icache_line_size))); 687 688 if (pcc->l1_dcache_size) { 689 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 690 pcc->l1_dcache_size))); 691 } else { 692 warn_report("Unknown L1 dcache size for cpu"); 693 } 694 if (pcc->l1_icache_size) { 695 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 696 pcc->l1_icache_size))); 697 } else { 698 warn_report("Unknown L1 icache size for cpu"); 699 } 700 701 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 702 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 703 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 704 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 705 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 706 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 707 708 if (ppc_has_spr(cpu, SPR_PURR)) { 709 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 710 } 711 if (ppc_has_spr(cpu, SPR_PURR)) { 712 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 713 } 714 715 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 716 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 717 segs, sizeof(segs)))); 718 } 719 720 /* Advertise VSX (vector extensions) if available 721 * 1 == VMX / Altivec available 722 * 2 == VSX available 723 * 724 * Only CPUs for which we create core types in spapr_cpu_core.c 725 * are possible, and all of those have VMX */ 726 if (env->insns_flags & PPC_ALTIVEC) { 727 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 728 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 729 } else { 730 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 731 } 732 } 733 734 /* Advertise DFP (Decimal Floating Point) if available 735 * 0 / no property == no DFP 736 * 1 == DFP available */ 737 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 738 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 739 } 740 741 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 742 sizeof(page_sizes_prop)); 743 if (page_sizes_prop_size) { 744 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 745 page_sizes_prop, page_sizes_prop_size))); 746 } 747 748 spapr_dt_pa_features(spapr, cpu, fdt, offset); 749 750 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 751 cs->cpu_index / vcpus_per_socket))); 752 753 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 754 pft_size_prop, sizeof(pft_size_prop)))); 755 756 if (ms->numa_state->num_nodes > 1) { 757 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 758 } 759 760 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 761 762 if (pcc->radix_page_info) { 763 for (i = 0; i < pcc->radix_page_info->count; i++) { 764 radix_AP_encodings[i] = 765 cpu_to_be32(pcc->radix_page_info->entries[i]); 766 } 767 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 768 radix_AP_encodings, 769 pcc->radix_page_info->count * 770 sizeof(radix_AP_encodings[0])))); 771 } 772 773 /* 774 * We set this property to let the guest know that it can use the large 775 * decrementer and its width in bits. 776 */ 777 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 778 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 779 pcc->lrg_decr_bits))); 780 } 781 782 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 783 { 784 CPUState **rev; 785 CPUState *cs; 786 int n_cpus; 787 int cpus_offset; 788 int i; 789 790 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 791 _FDT(cpus_offset); 792 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 793 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 794 795 /* 796 * We walk the CPUs in reverse order to ensure that CPU DT nodes 797 * created by fdt_add_subnode() end up in the right order in FDT 798 * for the guest kernel the enumerate the CPUs correctly. 799 * 800 * The CPU list cannot be traversed in reverse order, so we need 801 * to do extra work. 802 */ 803 n_cpus = 0; 804 rev = NULL; 805 CPU_FOREACH(cs) { 806 rev = g_renew(CPUState *, rev, n_cpus + 1); 807 rev[n_cpus++] = cs; 808 } 809 810 for (i = n_cpus - 1; i >= 0; i--) { 811 CPUState *cs = rev[i]; 812 PowerPCCPU *cpu = POWERPC_CPU(cs); 813 int index = spapr_get_vcpu_id(cpu); 814 DeviceClass *dc = DEVICE_GET_CLASS(cs); 815 g_autofree char *nodename = NULL; 816 int offset; 817 818 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 819 continue; 820 } 821 822 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 823 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 824 _FDT(offset); 825 spapr_dt_cpu(cs, fdt, offset, spapr); 826 } 827 828 g_free(rev); 829 } 830 831 static int spapr_dt_rng(void *fdt) 832 { 833 int node; 834 int ret; 835 836 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 837 if (node <= 0) { 838 return -1; 839 } 840 ret = fdt_setprop_string(fdt, node, "device_type", 841 "ibm,platform-facilities"); 842 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 843 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 844 845 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 846 if (node <= 0) { 847 return -1; 848 } 849 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 850 851 return ret ? -1 : 0; 852 } 853 854 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 855 { 856 MachineState *ms = MACHINE(spapr); 857 int rtas; 858 GString *hypertas = g_string_sized_new(256); 859 GString *qemu_hypertas = g_string_sized_new(256); 860 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 861 memory_region_size(&MACHINE(spapr)->device_memory->mr); 862 uint32_t lrdr_capacity[] = { 863 cpu_to_be32(max_device_addr >> 32), 864 cpu_to_be32(max_device_addr & 0xffffffff), 865 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 866 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 867 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 868 }; 869 870 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 871 872 /* hypertas */ 873 add_str(hypertas, "hcall-pft"); 874 add_str(hypertas, "hcall-term"); 875 add_str(hypertas, "hcall-dabr"); 876 add_str(hypertas, "hcall-interrupt"); 877 add_str(hypertas, "hcall-tce"); 878 add_str(hypertas, "hcall-vio"); 879 add_str(hypertas, "hcall-splpar"); 880 add_str(hypertas, "hcall-join"); 881 add_str(hypertas, "hcall-bulk"); 882 add_str(hypertas, "hcall-set-mode"); 883 add_str(hypertas, "hcall-sprg0"); 884 add_str(hypertas, "hcall-copy"); 885 add_str(hypertas, "hcall-debug"); 886 add_str(hypertas, "hcall-vphn"); 887 if (spapr_get_cap(spapr, SPAPR_CAP_RPT_INVALIDATE) == SPAPR_CAP_ON) { 888 add_str(hypertas, "hcall-rpt-invalidate"); 889 } 890 891 add_str(qemu_hypertas, "hcall-memop1"); 892 893 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 894 add_str(hypertas, "hcall-multi-tce"); 895 } 896 897 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 898 add_str(hypertas, "hcall-hpt-resize"); 899 } 900 901 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 902 hypertas->str, hypertas->len)); 903 g_string_free(hypertas, TRUE); 904 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 905 qemu_hypertas->str, qemu_hypertas->len)); 906 g_string_free(qemu_hypertas, TRUE); 907 908 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 909 910 /* 911 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 912 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 913 * 914 * The system reset requirements are driven by existing Linux and PowerVM 915 * implementation which (contrary to PAPR) saves r3 in the error log 916 * structure like machine check, so Linux expects to find the saved r3 917 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 918 * does not look at the error value). 919 * 920 * System reset interrupts are not subject to interlock like machine 921 * check, so this memory area could be corrupted if the sreset is 922 * interrupted by a machine check (or vice versa) if it was shared. To 923 * prevent this, system reset uses per-CPU areas for the sreset save 924 * area. A system reset that interrupts a system reset handler could 925 * still overwrite this area, but Linux doesn't try to recover in that 926 * case anyway. 927 * 928 * The extra 8 bytes is required because Linux's FWNMI error log check 929 * is off-by-one. 930 * 931 * RTAS_MIN_SIZE is required for the RTAS blob itself. 932 */ 933 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_MIN_SIZE + 934 RTAS_ERROR_LOG_MAX + 935 ms->smp.max_cpus * sizeof(uint64_t) * 2 + 936 sizeof(uint64_t))); 937 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 938 RTAS_ERROR_LOG_MAX)); 939 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 940 RTAS_EVENT_SCAN_RATE)); 941 942 g_assert(msi_nonbroken); 943 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 944 945 /* 946 * According to PAPR, rtas ibm,os-term does not guarantee a return 947 * back to the guest cpu. 948 * 949 * While an additional ibm,extended-os-term property indicates 950 * that rtas call return will always occur. Set this property. 951 */ 952 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 953 954 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 955 lrdr_capacity, sizeof(lrdr_capacity))); 956 957 spapr_dt_rtas_tokens(fdt, rtas); 958 } 959 960 /* 961 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 962 * and the XIVE features that the guest may request and thus the valid 963 * values for bytes 23..26 of option vector 5: 964 */ 965 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 966 int chosen) 967 { 968 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 969 970 char val[2 * 4] = { 971 23, 0x00, /* XICS / XIVE mode */ 972 24, 0x00, /* Hash/Radix, filled in below. */ 973 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 974 26, 0x40, /* Radix options: GTSE == yes. */ 975 }; 976 977 if (spapr->irq->xics && spapr->irq->xive) { 978 val[1] = SPAPR_OV5_XIVE_BOTH; 979 } else if (spapr->irq->xive) { 980 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 981 } else { 982 assert(spapr->irq->xics); 983 val[1] = SPAPR_OV5_XIVE_LEGACY; 984 } 985 986 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 987 first_ppc_cpu->compat_pvr)) { 988 /* 989 * If we're in a pre POWER9 compat mode then the guest should 990 * do hash and use the legacy interrupt mode 991 */ 992 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 993 val[3] = 0x00; /* Hash */ 994 spapr_check_mmu_mode(false); 995 } else if (kvm_enabled()) { 996 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 997 val[3] = 0x80; /* OV5_MMU_BOTH */ 998 } else if (kvmppc_has_cap_mmu_radix()) { 999 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1000 } else { 1001 val[3] = 0x00; /* Hash */ 1002 } 1003 } else { 1004 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1005 val[3] = 0xC0; 1006 } 1007 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1008 val, sizeof(val))); 1009 } 1010 1011 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1012 { 1013 MachineState *machine = MACHINE(spapr); 1014 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1015 int chosen; 1016 1017 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1018 1019 if (reset) { 1020 const char *boot_device = spapr->boot_device; 1021 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1022 size_t cb = 0; 1023 char *bootlist = get_boot_devices_list(&cb); 1024 1025 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1026 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1027 machine->kernel_cmdline)); 1028 } 1029 1030 if (spapr->initrd_size) { 1031 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1032 spapr->initrd_base)); 1033 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1034 spapr->initrd_base + spapr->initrd_size)); 1035 } 1036 1037 if (spapr->kernel_size) { 1038 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1039 cpu_to_be64(spapr->kernel_size) }; 1040 1041 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1042 &kprop, sizeof(kprop))); 1043 if (spapr->kernel_le) { 1044 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1045 } 1046 } 1047 if (boot_menu) { 1048 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1049 } 1050 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1051 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1052 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1053 1054 if (cb && bootlist) { 1055 int i; 1056 1057 for (i = 0; i < cb; i++) { 1058 if (bootlist[i] == '\n') { 1059 bootlist[i] = ' '; 1060 } 1061 } 1062 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1063 } 1064 1065 if (boot_device && strlen(boot_device)) { 1066 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1067 } 1068 1069 if (!spapr->has_graphics && stdout_path) { 1070 /* 1071 * "linux,stdout-path" and "stdout" properties are 1072 * deprecated by linux kernel. New platforms should only 1073 * use the "stdout-path" property. Set the new property 1074 * and continue using older property to remain compatible 1075 * with the existing firmware. 1076 */ 1077 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1078 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1079 } 1080 1081 /* 1082 * We can deal with BAR reallocation just fine, advertise it 1083 * to the guest 1084 */ 1085 if (smc->linux_pci_probe) { 1086 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1087 } 1088 1089 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1090 1091 g_free(stdout_path); 1092 g_free(bootlist); 1093 } 1094 1095 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1096 } 1097 1098 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1099 { 1100 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1101 * KVM to work under pHyp with some guest co-operation */ 1102 int hypervisor; 1103 uint8_t hypercall[16]; 1104 1105 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1106 /* indicate KVM hypercall interface */ 1107 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1108 if (kvmppc_has_cap_fixup_hcalls()) { 1109 /* 1110 * Older KVM versions with older guest kernels were broken 1111 * with the magic page, don't allow the guest to map it. 1112 */ 1113 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1114 sizeof(hypercall))) { 1115 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1116 hypercall, sizeof(hypercall))); 1117 } 1118 } 1119 } 1120 1121 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1122 { 1123 MachineState *machine = MACHINE(spapr); 1124 MachineClass *mc = MACHINE_GET_CLASS(machine); 1125 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1126 uint32_t root_drc_type_mask = 0; 1127 int ret; 1128 void *fdt; 1129 SpaprPhbState *phb; 1130 char *buf; 1131 1132 fdt = g_malloc0(space); 1133 _FDT((fdt_create_empty_tree(fdt, space))); 1134 1135 /* Root node */ 1136 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1137 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1138 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1139 1140 /* Guest UUID & Name*/ 1141 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1142 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1143 if (qemu_uuid_set) { 1144 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1145 } 1146 g_free(buf); 1147 1148 if (qemu_get_vm_name()) { 1149 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1150 qemu_get_vm_name())); 1151 } 1152 1153 /* Host Model & Serial Number */ 1154 if (spapr->host_model) { 1155 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1156 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1157 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1158 g_free(buf); 1159 } 1160 1161 if (spapr->host_serial) { 1162 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1163 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1164 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1165 g_free(buf); 1166 } 1167 1168 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1169 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1170 1171 /* /interrupt controller */ 1172 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1173 1174 ret = spapr_dt_memory(spapr, fdt); 1175 if (ret < 0) { 1176 error_report("couldn't setup memory nodes in fdt"); 1177 exit(1); 1178 } 1179 1180 /* /vdevice */ 1181 spapr_dt_vdevice(spapr->vio_bus, fdt); 1182 1183 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1184 ret = spapr_dt_rng(fdt); 1185 if (ret < 0) { 1186 error_report("could not set up rng device in the fdt"); 1187 exit(1); 1188 } 1189 } 1190 1191 QLIST_FOREACH(phb, &spapr->phbs, list) { 1192 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1193 if (ret < 0) { 1194 error_report("couldn't setup PCI devices in fdt"); 1195 exit(1); 1196 } 1197 } 1198 1199 spapr_dt_cpus(fdt, spapr); 1200 1201 /* ibm,drc-indexes and friends */ 1202 if (smc->dr_lmb_enabled) { 1203 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; 1204 } 1205 if (smc->dr_phb_enabled) { 1206 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; 1207 } 1208 if (mc->nvdimm_supported) { 1209 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM; 1210 } 1211 if (root_drc_type_mask) { 1212 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask)); 1213 } 1214 1215 if (mc->has_hotpluggable_cpus) { 1216 int offset = fdt_path_offset(fdt, "/cpus"); 1217 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1218 if (ret < 0) { 1219 error_report("Couldn't set up CPU DR device tree properties"); 1220 exit(1); 1221 } 1222 } 1223 1224 /* /event-sources */ 1225 spapr_dt_events(spapr, fdt); 1226 1227 /* /rtas */ 1228 spapr_dt_rtas(spapr, fdt); 1229 1230 /* /chosen */ 1231 spapr_dt_chosen(spapr, fdt, reset); 1232 1233 /* /hypervisor */ 1234 if (kvm_enabled()) { 1235 spapr_dt_hypervisor(spapr, fdt); 1236 } 1237 1238 /* Build memory reserve map */ 1239 if (reset) { 1240 if (spapr->kernel_size) { 1241 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1242 spapr->kernel_size))); 1243 } 1244 if (spapr->initrd_size) { 1245 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1246 spapr->initrd_size))); 1247 } 1248 } 1249 1250 /* NVDIMM devices */ 1251 if (mc->nvdimm_supported) { 1252 spapr_dt_persistent_memory(spapr, fdt); 1253 } 1254 1255 return fdt; 1256 } 1257 1258 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1259 { 1260 SpaprMachineState *spapr = opaque; 1261 1262 return (addr & 0x0fffffff) + spapr->kernel_addr; 1263 } 1264 1265 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1266 PowerPCCPU *cpu) 1267 { 1268 CPUPPCState *env = &cpu->env; 1269 1270 /* The TCG path should also be holding the BQL at this point */ 1271 g_assert(qemu_mutex_iothread_locked()); 1272 1273 if (msr_pr) { 1274 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1275 env->gpr[3] = H_PRIVILEGE; 1276 } else { 1277 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1278 } 1279 } 1280 1281 struct LPCRSyncState { 1282 target_ulong value; 1283 target_ulong mask; 1284 }; 1285 1286 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1287 { 1288 struct LPCRSyncState *s = arg.host_ptr; 1289 PowerPCCPU *cpu = POWERPC_CPU(cs); 1290 CPUPPCState *env = &cpu->env; 1291 target_ulong lpcr; 1292 1293 cpu_synchronize_state(cs); 1294 lpcr = env->spr[SPR_LPCR]; 1295 lpcr &= ~s->mask; 1296 lpcr |= s->value; 1297 ppc_store_lpcr(cpu, lpcr); 1298 } 1299 1300 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1301 { 1302 CPUState *cs; 1303 struct LPCRSyncState s = { 1304 .value = value, 1305 .mask = mask 1306 }; 1307 CPU_FOREACH(cs) { 1308 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1309 } 1310 } 1311 1312 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1313 { 1314 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1315 1316 /* Copy PATE1:GR into PATE0:HR */ 1317 entry->dw0 = spapr->patb_entry & PATE0_HR; 1318 entry->dw1 = spapr->patb_entry; 1319 } 1320 1321 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1322 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1323 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1324 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1325 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1326 1327 /* 1328 * Get the fd to access the kernel htab, re-opening it if necessary 1329 */ 1330 static int get_htab_fd(SpaprMachineState *spapr) 1331 { 1332 Error *local_err = NULL; 1333 1334 if (spapr->htab_fd >= 0) { 1335 return spapr->htab_fd; 1336 } 1337 1338 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1339 if (spapr->htab_fd < 0) { 1340 error_report_err(local_err); 1341 } 1342 1343 return spapr->htab_fd; 1344 } 1345 1346 void close_htab_fd(SpaprMachineState *spapr) 1347 { 1348 if (spapr->htab_fd >= 0) { 1349 close(spapr->htab_fd); 1350 } 1351 spapr->htab_fd = -1; 1352 } 1353 1354 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1355 { 1356 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1357 1358 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1359 } 1360 1361 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1362 { 1363 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1364 1365 assert(kvm_enabled()); 1366 1367 if (!spapr->htab) { 1368 return 0; 1369 } 1370 1371 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1372 } 1373 1374 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1375 hwaddr ptex, int n) 1376 { 1377 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1378 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1379 1380 if (!spapr->htab) { 1381 /* 1382 * HTAB is controlled by KVM. Fetch into temporary buffer 1383 */ 1384 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1385 kvmppc_read_hptes(hptes, ptex, n); 1386 return hptes; 1387 } 1388 1389 /* 1390 * HTAB is controlled by QEMU. Just point to the internally 1391 * accessible PTEG. 1392 */ 1393 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1394 } 1395 1396 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1397 const ppc_hash_pte64_t *hptes, 1398 hwaddr ptex, int n) 1399 { 1400 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1401 1402 if (!spapr->htab) { 1403 g_free((void *)hptes); 1404 } 1405 1406 /* Nothing to do for qemu managed HPT */ 1407 } 1408 1409 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1410 uint64_t pte0, uint64_t pte1) 1411 { 1412 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1413 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1414 1415 if (!spapr->htab) { 1416 kvmppc_write_hpte(ptex, pte0, pte1); 1417 } else { 1418 if (pte0 & HPTE64_V_VALID) { 1419 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1420 /* 1421 * When setting valid, we write PTE1 first. This ensures 1422 * proper synchronization with the reading code in 1423 * ppc_hash64_pteg_search() 1424 */ 1425 smp_wmb(); 1426 stq_p(spapr->htab + offset, pte0); 1427 } else { 1428 stq_p(spapr->htab + offset, pte0); 1429 /* 1430 * When clearing it we set PTE0 first. This ensures proper 1431 * synchronization with the reading code in 1432 * ppc_hash64_pteg_search() 1433 */ 1434 smp_wmb(); 1435 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1436 } 1437 } 1438 } 1439 1440 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1441 uint64_t pte1) 1442 { 1443 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_C; 1444 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1445 1446 if (!spapr->htab) { 1447 /* There should always be a hash table when this is called */ 1448 error_report("spapr_hpte_set_c called with no hash table !"); 1449 return; 1450 } 1451 1452 /* The HW performs a non-atomic byte update */ 1453 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1454 } 1455 1456 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1457 uint64_t pte1) 1458 { 1459 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_R; 1460 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1461 1462 if (!spapr->htab) { 1463 /* There should always be a hash table when this is called */ 1464 error_report("spapr_hpte_set_r called with no hash table !"); 1465 return; 1466 } 1467 1468 /* The HW performs a non-atomic byte update */ 1469 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1470 } 1471 1472 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1473 { 1474 int shift; 1475 1476 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1477 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1478 * that's much more than is needed for Linux guests */ 1479 shift = ctz64(pow2ceil(ramsize)) - 7; 1480 shift = MAX(shift, 18); /* Minimum architected size */ 1481 shift = MIN(shift, 46); /* Maximum architected size */ 1482 return shift; 1483 } 1484 1485 void spapr_free_hpt(SpaprMachineState *spapr) 1486 { 1487 g_free(spapr->htab); 1488 spapr->htab = NULL; 1489 spapr->htab_shift = 0; 1490 close_htab_fd(spapr); 1491 } 1492 1493 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1494 { 1495 ERRP_GUARD(); 1496 long rc; 1497 1498 /* Clean up any HPT info from a previous boot */ 1499 spapr_free_hpt(spapr); 1500 1501 rc = kvmppc_reset_htab(shift); 1502 1503 if (rc == -EOPNOTSUPP) { 1504 error_setg(errp, "HPT not supported in nested guests"); 1505 return -EOPNOTSUPP; 1506 } 1507 1508 if (rc < 0) { 1509 /* kernel-side HPT needed, but couldn't allocate one */ 1510 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1511 shift); 1512 error_append_hint(errp, "Try smaller maxmem?\n"); 1513 return -errno; 1514 } else if (rc > 0) { 1515 /* kernel-side HPT allocated */ 1516 if (rc != shift) { 1517 error_setg(errp, 1518 "Requested order %d HPT, but kernel allocated order %ld", 1519 shift, rc); 1520 error_append_hint(errp, "Try smaller maxmem?\n"); 1521 return -ENOSPC; 1522 } 1523 1524 spapr->htab_shift = shift; 1525 spapr->htab = NULL; 1526 } else { 1527 /* kernel-side HPT not needed, allocate in userspace instead */ 1528 size_t size = 1ULL << shift; 1529 int i; 1530 1531 spapr->htab = qemu_memalign(size, size); 1532 memset(spapr->htab, 0, size); 1533 spapr->htab_shift = shift; 1534 1535 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1536 DIRTY_HPTE(HPTE(spapr->htab, i)); 1537 } 1538 } 1539 /* We're setting up a hash table, so that means we're not radix */ 1540 spapr->patb_entry = 0; 1541 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1542 return 0; 1543 } 1544 1545 void spapr_setup_hpt(SpaprMachineState *spapr) 1546 { 1547 int hpt_shift; 1548 1549 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1550 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1551 } else { 1552 uint64_t current_ram_size; 1553 1554 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1555 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1556 } 1557 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1558 1559 if (kvm_enabled()) { 1560 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1561 1562 /* Check our RMA fits in the possible VRMA */ 1563 if (vrma_limit < spapr->rma_size) { 1564 error_report("Unable to create %" HWADDR_PRIu 1565 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1566 spapr->rma_size / MiB, vrma_limit / MiB); 1567 exit(EXIT_FAILURE); 1568 } 1569 } 1570 } 1571 1572 void spapr_check_mmu_mode(bool guest_radix) 1573 { 1574 if (guest_radix) { 1575 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 1576 error_report("Guest requested unavailable MMU mode (radix)."); 1577 exit(EXIT_FAILURE); 1578 } 1579 } else { 1580 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 1581 && !kvmppc_has_cap_mmu_hash_v3()) { 1582 error_report("Guest requested unavailable MMU mode (hash)."); 1583 exit(EXIT_FAILURE); 1584 } 1585 } 1586 } 1587 1588 static void spapr_machine_reset(MachineState *machine) 1589 { 1590 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1591 PowerPCCPU *first_ppc_cpu; 1592 hwaddr fdt_addr; 1593 void *fdt; 1594 int rc; 1595 1596 pef_kvm_reset(machine->cgs, &error_fatal); 1597 spapr_caps_apply(spapr); 1598 1599 first_ppc_cpu = POWERPC_CPU(first_cpu); 1600 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1601 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1602 spapr->max_compat_pvr)) { 1603 /* 1604 * If using KVM with radix mode available, VCPUs can be started 1605 * without a HPT because KVM will start them in radix mode. 1606 * Set the GR bit in PATE so that we know there is no HPT. 1607 */ 1608 spapr->patb_entry = PATE1_GR; 1609 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1610 } else { 1611 spapr_setup_hpt(spapr); 1612 } 1613 1614 qemu_devices_reset(); 1615 1616 spapr_ovec_cleanup(spapr->ov5_cas); 1617 spapr->ov5_cas = spapr_ovec_new(); 1618 1619 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1620 1621 /* 1622 * This is fixing some of the default configuration of the XIVE 1623 * devices. To be called after the reset of the machine devices. 1624 */ 1625 spapr_irq_reset(spapr, &error_fatal); 1626 1627 /* 1628 * There is no CAS under qtest. Simulate one to please the code that 1629 * depends on spapr->ov5_cas. This is especially needed to test device 1630 * unplug, so we do that before resetting the DRCs. 1631 */ 1632 if (qtest_enabled()) { 1633 spapr_ovec_cleanup(spapr->ov5_cas); 1634 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1635 } 1636 1637 /* DRC reset may cause a device to be unplugged. This will cause troubles 1638 * if this device is used by another device (eg, a running vhost backend 1639 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1640 * situations, we reset DRCs after all devices have been reset. 1641 */ 1642 spapr_drc_reset_all(spapr); 1643 1644 spapr_clear_pending_events(spapr); 1645 1646 /* 1647 * We place the device tree just below either the top of the RMA, 1648 * or just below 2GB, whichever is lower, so that it can be 1649 * processed with 32-bit real mode code if necessary 1650 */ 1651 fdt_addr = MIN(spapr->rma_size, FDT_MAX_ADDR) - FDT_MAX_SIZE; 1652 1653 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1654 if (spapr->vof) { 1655 spapr_vof_reset(spapr, fdt, &error_fatal); 1656 /* 1657 * Do not pack the FDT as the client may change properties. 1658 * VOF client does not expect the FDT so we do not load it to the VM. 1659 */ 1660 } else { 1661 rc = fdt_pack(fdt); 1662 /* Should only fail if we've built a corrupted tree */ 1663 assert(rc == 0); 1664 1665 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 1666 0, fdt_addr, 0); 1667 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1668 } 1669 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1670 1671 g_free(spapr->fdt_blob); 1672 spapr->fdt_size = fdt_totalsize(fdt); 1673 spapr->fdt_initial_size = spapr->fdt_size; 1674 spapr->fdt_blob = fdt; 1675 1676 /* Set up the entry state */ 1677 first_ppc_cpu->env.gpr[5] = 0; 1678 1679 spapr->fwnmi_system_reset_addr = -1; 1680 spapr->fwnmi_machine_check_addr = -1; 1681 spapr->fwnmi_machine_check_interlock = -1; 1682 1683 /* Signal all vCPUs waiting on this condition */ 1684 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1685 1686 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1687 } 1688 1689 static void spapr_create_nvram(SpaprMachineState *spapr) 1690 { 1691 DeviceState *dev = qdev_new("spapr-nvram"); 1692 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1693 1694 if (dinfo) { 1695 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1696 &error_fatal); 1697 } 1698 1699 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1700 1701 spapr->nvram = (struct SpaprNvram *)dev; 1702 } 1703 1704 static void spapr_rtc_create(SpaprMachineState *spapr) 1705 { 1706 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1707 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1708 &error_fatal, NULL); 1709 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1710 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1711 "date"); 1712 } 1713 1714 /* Returns whether we want to use VGA or not */ 1715 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1716 { 1717 switch (vga_interface_type) { 1718 case VGA_NONE: 1719 return false; 1720 case VGA_DEVICE: 1721 return true; 1722 case VGA_STD: 1723 case VGA_VIRTIO: 1724 case VGA_CIRRUS: 1725 return pci_vga_init(pci_bus) != NULL; 1726 default: 1727 error_setg(errp, 1728 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1729 return false; 1730 } 1731 } 1732 1733 static int spapr_pre_load(void *opaque) 1734 { 1735 int rc; 1736 1737 rc = spapr_caps_pre_load(opaque); 1738 if (rc) { 1739 return rc; 1740 } 1741 1742 return 0; 1743 } 1744 1745 static int spapr_post_load(void *opaque, int version_id) 1746 { 1747 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1748 int err = 0; 1749 1750 err = spapr_caps_post_migration(spapr); 1751 if (err) { 1752 return err; 1753 } 1754 1755 /* 1756 * In earlier versions, there was no separate qdev for the PAPR 1757 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1758 * So when migrating from those versions, poke the incoming offset 1759 * value into the RTC device 1760 */ 1761 if (version_id < 3) { 1762 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1763 if (err) { 1764 return err; 1765 } 1766 } 1767 1768 if (kvm_enabled() && spapr->patb_entry) { 1769 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1770 bool radix = !!(spapr->patb_entry & PATE1_GR); 1771 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1772 1773 /* 1774 * Update LPCR:HR and UPRT as they may not be set properly in 1775 * the stream 1776 */ 1777 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1778 LPCR_HR | LPCR_UPRT); 1779 1780 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1781 if (err) { 1782 error_report("Process table config unsupported by the host"); 1783 return -EINVAL; 1784 } 1785 } 1786 1787 err = spapr_irq_post_load(spapr, version_id); 1788 if (err) { 1789 return err; 1790 } 1791 1792 return err; 1793 } 1794 1795 static int spapr_pre_save(void *opaque) 1796 { 1797 int rc; 1798 1799 rc = spapr_caps_pre_save(opaque); 1800 if (rc) { 1801 return rc; 1802 } 1803 1804 return 0; 1805 } 1806 1807 static bool version_before_3(void *opaque, int version_id) 1808 { 1809 return version_id < 3; 1810 } 1811 1812 static bool spapr_pending_events_needed(void *opaque) 1813 { 1814 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1815 return !QTAILQ_EMPTY(&spapr->pending_events); 1816 } 1817 1818 static const VMStateDescription vmstate_spapr_event_entry = { 1819 .name = "spapr_event_log_entry", 1820 .version_id = 1, 1821 .minimum_version_id = 1, 1822 .fields = (VMStateField[]) { 1823 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1824 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1825 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1826 NULL, extended_length), 1827 VMSTATE_END_OF_LIST() 1828 }, 1829 }; 1830 1831 static const VMStateDescription vmstate_spapr_pending_events = { 1832 .name = "spapr_pending_events", 1833 .version_id = 1, 1834 .minimum_version_id = 1, 1835 .needed = spapr_pending_events_needed, 1836 .fields = (VMStateField[]) { 1837 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1838 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1839 VMSTATE_END_OF_LIST() 1840 }, 1841 }; 1842 1843 static bool spapr_ov5_cas_needed(void *opaque) 1844 { 1845 SpaprMachineState *spapr = opaque; 1846 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1847 bool cas_needed; 1848 1849 /* Prior to the introduction of SpaprOptionVector, we had two option 1850 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1851 * Both of these options encode machine topology into the device-tree 1852 * in such a way that the now-booted OS should still be able to interact 1853 * appropriately with QEMU regardless of what options were actually 1854 * negotiatied on the source side. 1855 * 1856 * As such, we can avoid migrating the CAS-negotiated options if these 1857 * are the only options available on the current machine/platform. 1858 * Since these are the only options available for pseries-2.7 and 1859 * earlier, this allows us to maintain old->new/new->old migration 1860 * compatibility. 1861 * 1862 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1863 * via default pseries-2.8 machines and explicit command-line parameters. 1864 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1865 * of the actual CAS-negotiated values to continue working properly. For 1866 * example, availability of memory unplug depends on knowing whether 1867 * OV5_HP_EVT was negotiated via CAS. 1868 * 1869 * Thus, for any cases where the set of available CAS-negotiatable 1870 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1871 * include the CAS-negotiated options in the migration stream, unless 1872 * if they affect boot time behaviour only. 1873 */ 1874 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1875 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1876 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1877 1878 /* We need extra information if we have any bits outside the mask 1879 * defined above */ 1880 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1881 1882 spapr_ovec_cleanup(ov5_mask); 1883 1884 return cas_needed; 1885 } 1886 1887 static const VMStateDescription vmstate_spapr_ov5_cas = { 1888 .name = "spapr_option_vector_ov5_cas", 1889 .version_id = 1, 1890 .minimum_version_id = 1, 1891 .needed = spapr_ov5_cas_needed, 1892 .fields = (VMStateField[]) { 1893 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1894 vmstate_spapr_ovec, SpaprOptionVector), 1895 VMSTATE_END_OF_LIST() 1896 }, 1897 }; 1898 1899 static bool spapr_patb_entry_needed(void *opaque) 1900 { 1901 SpaprMachineState *spapr = opaque; 1902 1903 return !!spapr->patb_entry; 1904 } 1905 1906 static const VMStateDescription vmstate_spapr_patb_entry = { 1907 .name = "spapr_patb_entry", 1908 .version_id = 1, 1909 .minimum_version_id = 1, 1910 .needed = spapr_patb_entry_needed, 1911 .fields = (VMStateField[]) { 1912 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1913 VMSTATE_END_OF_LIST() 1914 }, 1915 }; 1916 1917 static bool spapr_irq_map_needed(void *opaque) 1918 { 1919 SpaprMachineState *spapr = opaque; 1920 1921 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1922 } 1923 1924 static const VMStateDescription vmstate_spapr_irq_map = { 1925 .name = "spapr_irq_map", 1926 .version_id = 1, 1927 .minimum_version_id = 1, 1928 .needed = spapr_irq_map_needed, 1929 .fields = (VMStateField[]) { 1930 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1931 VMSTATE_END_OF_LIST() 1932 }, 1933 }; 1934 1935 static bool spapr_dtb_needed(void *opaque) 1936 { 1937 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1938 1939 return smc->update_dt_enabled; 1940 } 1941 1942 static int spapr_dtb_pre_load(void *opaque) 1943 { 1944 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1945 1946 g_free(spapr->fdt_blob); 1947 spapr->fdt_blob = NULL; 1948 spapr->fdt_size = 0; 1949 1950 return 0; 1951 } 1952 1953 static const VMStateDescription vmstate_spapr_dtb = { 1954 .name = "spapr_dtb", 1955 .version_id = 1, 1956 .minimum_version_id = 1, 1957 .needed = spapr_dtb_needed, 1958 .pre_load = spapr_dtb_pre_load, 1959 .fields = (VMStateField[]) { 1960 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1961 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1962 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1963 fdt_size), 1964 VMSTATE_END_OF_LIST() 1965 }, 1966 }; 1967 1968 static bool spapr_fwnmi_needed(void *opaque) 1969 { 1970 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1971 1972 return spapr->fwnmi_machine_check_addr != -1; 1973 } 1974 1975 static int spapr_fwnmi_pre_save(void *opaque) 1976 { 1977 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1978 1979 /* 1980 * Check if machine check handling is in progress and print a 1981 * warning message. 1982 */ 1983 if (spapr->fwnmi_machine_check_interlock != -1) { 1984 warn_report("A machine check is being handled during migration. The" 1985 "handler may run and log hardware error on the destination"); 1986 } 1987 1988 return 0; 1989 } 1990 1991 static const VMStateDescription vmstate_spapr_fwnmi = { 1992 .name = "spapr_fwnmi", 1993 .version_id = 1, 1994 .minimum_version_id = 1, 1995 .needed = spapr_fwnmi_needed, 1996 .pre_save = spapr_fwnmi_pre_save, 1997 .fields = (VMStateField[]) { 1998 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 1999 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 2000 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 2001 VMSTATE_END_OF_LIST() 2002 }, 2003 }; 2004 2005 static const VMStateDescription vmstate_spapr = { 2006 .name = "spapr", 2007 .version_id = 3, 2008 .minimum_version_id = 1, 2009 .pre_load = spapr_pre_load, 2010 .post_load = spapr_post_load, 2011 .pre_save = spapr_pre_save, 2012 .fields = (VMStateField[]) { 2013 /* used to be @next_irq */ 2014 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2015 2016 /* RTC offset */ 2017 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2018 2019 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2020 VMSTATE_END_OF_LIST() 2021 }, 2022 .subsections = (const VMStateDescription*[]) { 2023 &vmstate_spapr_ov5_cas, 2024 &vmstate_spapr_patb_entry, 2025 &vmstate_spapr_pending_events, 2026 &vmstate_spapr_cap_htm, 2027 &vmstate_spapr_cap_vsx, 2028 &vmstate_spapr_cap_dfp, 2029 &vmstate_spapr_cap_cfpc, 2030 &vmstate_spapr_cap_sbbc, 2031 &vmstate_spapr_cap_ibs, 2032 &vmstate_spapr_cap_hpt_maxpagesize, 2033 &vmstate_spapr_irq_map, 2034 &vmstate_spapr_cap_nested_kvm_hv, 2035 &vmstate_spapr_dtb, 2036 &vmstate_spapr_cap_large_decr, 2037 &vmstate_spapr_cap_ccf_assist, 2038 &vmstate_spapr_cap_fwnmi, 2039 &vmstate_spapr_fwnmi, 2040 &vmstate_spapr_cap_rpt_invalidate, 2041 NULL 2042 } 2043 }; 2044 2045 static int htab_save_setup(QEMUFile *f, void *opaque) 2046 { 2047 SpaprMachineState *spapr = opaque; 2048 2049 /* "Iteration" header */ 2050 if (!spapr->htab_shift) { 2051 qemu_put_be32(f, -1); 2052 } else { 2053 qemu_put_be32(f, spapr->htab_shift); 2054 } 2055 2056 if (spapr->htab) { 2057 spapr->htab_save_index = 0; 2058 spapr->htab_first_pass = true; 2059 } else { 2060 if (spapr->htab_shift) { 2061 assert(kvm_enabled()); 2062 } 2063 } 2064 2065 2066 return 0; 2067 } 2068 2069 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2070 int chunkstart, int n_valid, int n_invalid) 2071 { 2072 qemu_put_be32(f, chunkstart); 2073 qemu_put_be16(f, n_valid); 2074 qemu_put_be16(f, n_invalid); 2075 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2076 HASH_PTE_SIZE_64 * n_valid); 2077 } 2078 2079 static void htab_save_end_marker(QEMUFile *f) 2080 { 2081 qemu_put_be32(f, 0); 2082 qemu_put_be16(f, 0); 2083 qemu_put_be16(f, 0); 2084 } 2085 2086 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2087 int64_t max_ns) 2088 { 2089 bool has_timeout = max_ns != -1; 2090 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2091 int index = spapr->htab_save_index; 2092 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2093 2094 assert(spapr->htab_first_pass); 2095 2096 do { 2097 int chunkstart; 2098 2099 /* Consume invalid HPTEs */ 2100 while ((index < htabslots) 2101 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2102 CLEAN_HPTE(HPTE(spapr->htab, index)); 2103 index++; 2104 } 2105 2106 /* Consume valid HPTEs */ 2107 chunkstart = index; 2108 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2109 && HPTE_VALID(HPTE(spapr->htab, index))) { 2110 CLEAN_HPTE(HPTE(spapr->htab, index)); 2111 index++; 2112 } 2113 2114 if (index > chunkstart) { 2115 int n_valid = index - chunkstart; 2116 2117 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2118 2119 if (has_timeout && 2120 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2121 break; 2122 } 2123 } 2124 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2125 2126 if (index >= htabslots) { 2127 assert(index == htabslots); 2128 index = 0; 2129 spapr->htab_first_pass = false; 2130 } 2131 spapr->htab_save_index = index; 2132 } 2133 2134 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2135 int64_t max_ns) 2136 { 2137 bool final = max_ns < 0; 2138 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2139 int examined = 0, sent = 0; 2140 int index = spapr->htab_save_index; 2141 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2142 2143 assert(!spapr->htab_first_pass); 2144 2145 do { 2146 int chunkstart, invalidstart; 2147 2148 /* Consume non-dirty HPTEs */ 2149 while ((index < htabslots) 2150 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2151 index++; 2152 examined++; 2153 } 2154 2155 chunkstart = index; 2156 /* Consume valid dirty HPTEs */ 2157 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2158 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2159 && HPTE_VALID(HPTE(spapr->htab, index))) { 2160 CLEAN_HPTE(HPTE(spapr->htab, index)); 2161 index++; 2162 examined++; 2163 } 2164 2165 invalidstart = index; 2166 /* Consume invalid dirty HPTEs */ 2167 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2168 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2169 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2170 CLEAN_HPTE(HPTE(spapr->htab, index)); 2171 index++; 2172 examined++; 2173 } 2174 2175 if (index > chunkstart) { 2176 int n_valid = invalidstart - chunkstart; 2177 int n_invalid = index - invalidstart; 2178 2179 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2180 sent += index - chunkstart; 2181 2182 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2183 break; 2184 } 2185 } 2186 2187 if (examined >= htabslots) { 2188 break; 2189 } 2190 2191 if (index >= htabslots) { 2192 assert(index == htabslots); 2193 index = 0; 2194 } 2195 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2196 2197 if (index >= htabslots) { 2198 assert(index == htabslots); 2199 index = 0; 2200 } 2201 2202 spapr->htab_save_index = index; 2203 2204 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2205 } 2206 2207 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2208 #define MAX_KVM_BUF_SIZE 2048 2209 2210 static int htab_save_iterate(QEMUFile *f, void *opaque) 2211 { 2212 SpaprMachineState *spapr = opaque; 2213 int fd; 2214 int rc = 0; 2215 2216 /* Iteration header */ 2217 if (!spapr->htab_shift) { 2218 qemu_put_be32(f, -1); 2219 return 1; 2220 } else { 2221 qemu_put_be32(f, 0); 2222 } 2223 2224 if (!spapr->htab) { 2225 assert(kvm_enabled()); 2226 2227 fd = get_htab_fd(spapr); 2228 if (fd < 0) { 2229 return fd; 2230 } 2231 2232 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2233 if (rc < 0) { 2234 return rc; 2235 } 2236 } else if (spapr->htab_first_pass) { 2237 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2238 } else { 2239 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2240 } 2241 2242 htab_save_end_marker(f); 2243 2244 return rc; 2245 } 2246 2247 static int htab_save_complete(QEMUFile *f, void *opaque) 2248 { 2249 SpaprMachineState *spapr = opaque; 2250 int fd; 2251 2252 /* Iteration header */ 2253 if (!spapr->htab_shift) { 2254 qemu_put_be32(f, -1); 2255 return 0; 2256 } else { 2257 qemu_put_be32(f, 0); 2258 } 2259 2260 if (!spapr->htab) { 2261 int rc; 2262 2263 assert(kvm_enabled()); 2264 2265 fd = get_htab_fd(spapr); 2266 if (fd < 0) { 2267 return fd; 2268 } 2269 2270 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2271 if (rc < 0) { 2272 return rc; 2273 } 2274 } else { 2275 if (spapr->htab_first_pass) { 2276 htab_save_first_pass(f, spapr, -1); 2277 } 2278 htab_save_later_pass(f, spapr, -1); 2279 } 2280 2281 /* End marker */ 2282 htab_save_end_marker(f); 2283 2284 return 0; 2285 } 2286 2287 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2288 { 2289 SpaprMachineState *spapr = opaque; 2290 uint32_t section_hdr; 2291 int fd = -1; 2292 Error *local_err = NULL; 2293 2294 if (version_id < 1 || version_id > 1) { 2295 error_report("htab_load() bad version"); 2296 return -EINVAL; 2297 } 2298 2299 section_hdr = qemu_get_be32(f); 2300 2301 if (section_hdr == -1) { 2302 spapr_free_hpt(spapr); 2303 return 0; 2304 } 2305 2306 if (section_hdr) { 2307 int ret; 2308 2309 /* First section gives the htab size */ 2310 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2311 if (ret < 0) { 2312 error_report_err(local_err); 2313 return ret; 2314 } 2315 return 0; 2316 } 2317 2318 if (!spapr->htab) { 2319 assert(kvm_enabled()); 2320 2321 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2322 if (fd < 0) { 2323 error_report_err(local_err); 2324 return fd; 2325 } 2326 } 2327 2328 while (true) { 2329 uint32_t index; 2330 uint16_t n_valid, n_invalid; 2331 2332 index = qemu_get_be32(f); 2333 n_valid = qemu_get_be16(f); 2334 n_invalid = qemu_get_be16(f); 2335 2336 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2337 /* End of Stream */ 2338 break; 2339 } 2340 2341 if ((index + n_valid + n_invalid) > 2342 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2343 /* Bad index in stream */ 2344 error_report( 2345 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2346 index, n_valid, n_invalid, spapr->htab_shift); 2347 return -EINVAL; 2348 } 2349 2350 if (spapr->htab) { 2351 if (n_valid) { 2352 qemu_get_buffer(f, HPTE(spapr->htab, index), 2353 HASH_PTE_SIZE_64 * n_valid); 2354 } 2355 if (n_invalid) { 2356 memset(HPTE(spapr->htab, index + n_valid), 0, 2357 HASH_PTE_SIZE_64 * n_invalid); 2358 } 2359 } else { 2360 int rc; 2361 2362 assert(fd >= 0); 2363 2364 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2365 &local_err); 2366 if (rc < 0) { 2367 error_report_err(local_err); 2368 return rc; 2369 } 2370 } 2371 } 2372 2373 if (!spapr->htab) { 2374 assert(fd >= 0); 2375 close(fd); 2376 } 2377 2378 return 0; 2379 } 2380 2381 static void htab_save_cleanup(void *opaque) 2382 { 2383 SpaprMachineState *spapr = opaque; 2384 2385 close_htab_fd(spapr); 2386 } 2387 2388 static SaveVMHandlers savevm_htab_handlers = { 2389 .save_setup = htab_save_setup, 2390 .save_live_iterate = htab_save_iterate, 2391 .save_live_complete_precopy = htab_save_complete, 2392 .save_cleanup = htab_save_cleanup, 2393 .load_state = htab_load, 2394 }; 2395 2396 static void spapr_boot_set(void *opaque, const char *boot_device, 2397 Error **errp) 2398 { 2399 SpaprMachineState *spapr = SPAPR_MACHINE(opaque); 2400 2401 g_free(spapr->boot_device); 2402 spapr->boot_device = g_strdup(boot_device); 2403 } 2404 2405 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2406 { 2407 MachineState *machine = MACHINE(spapr); 2408 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2409 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2410 int i; 2411 2412 for (i = 0; i < nr_lmbs; i++) { 2413 uint64_t addr; 2414 2415 addr = i * lmb_size + machine->device_memory->base; 2416 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2417 addr / lmb_size); 2418 } 2419 } 2420 2421 /* 2422 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2423 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2424 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2425 */ 2426 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2427 { 2428 int i; 2429 2430 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2431 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2432 " is not aligned to %" PRIu64 " MiB", 2433 machine->ram_size, 2434 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2435 return; 2436 } 2437 2438 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2439 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2440 " is not aligned to %" PRIu64 " MiB", 2441 machine->ram_size, 2442 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2443 return; 2444 } 2445 2446 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2447 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2448 error_setg(errp, 2449 "Node %d memory size 0x%" PRIx64 2450 " is not aligned to %" PRIu64 " MiB", 2451 i, machine->numa_state->nodes[i].node_mem, 2452 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2453 return; 2454 } 2455 } 2456 } 2457 2458 /* find cpu slot in machine->possible_cpus by core_id */ 2459 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2460 { 2461 int index = id / ms->smp.threads; 2462 2463 if (index >= ms->possible_cpus->len) { 2464 return NULL; 2465 } 2466 if (idx) { 2467 *idx = index; 2468 } 2469 return &ms->possible_cpus->cpus[index]; 2470 } 2471 2472 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2473 { 2474 MachineState *ms = MACHINE(spapr); 2475 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2476 Error *local_err = NULL; 2477 bool vsmt_user = !!spapr->vsmt; 2478 int kvm_smt = kvmppc_smt_threads(); 2479 int ret; 2480 unsigned int smp_threads = ms->smp.threads; 2481 2482 if (!kvm_enabled() && (smp_threads > 1)) { 2483 error_setg(errp, "TCG cannot support more than 1 thread/core " 2484 "on a pseries machine"); 2485 return; 2486 } 2487 if (!is_power_of_2(smp_threads)) { 2488 error_setg(errp, "Cannot support %d threads/core on a pseries " 2489 "machine because it must be a power of 2", smp_threads); 2490 return; 2491 } 2492 2493 /* Detemine the VSMT mode to use: */ 2494 if (vsmt_user) { 2495 if (spapr->vsmt < smp_threads) { 2496 error_setg(errp, "Cannot support VSMT mode %d" 2497 " because it must be >= threads/core (%d)", 2498 spapr->vsmt, smp_threads); 2499 return; 2500 } 2501 /* In this case, spapr->vsmt has been set by the command line */ 2502 } else if (!smc->smp_threads_vsmt) { 2503 /* 2504 * Default VSMT value is tricky, because we need it to be as 2505 * consistent as possible (for migration), but this requires 2506 * changing it for at least some existing cases. We pick 8 as 2507 * the value that we'd get with KVM on POWER8, the 2508 * overwhelmingly common case in production systems. 2509 */ 2510 spapr->vsmt = MAX(8, smp_threads); 2511 } else { 2512 spapr->vsmt = smp_threads; 2513 } 2514 2515 /* KVM: If necessary, set the SMT mode: */ 2516 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2517 ret = kvmppc_set_smt_threads(spapr->vsmt); 2518 if (ret) { 2519 /* Looks like KVM isn't able to change VSMT mode */ 2520 error_setg(&local_err, 2521 "Failed to set KVM's VSMT mode to %d (errno %d)", 2522 spapr->vsmt, ret); 2523 /* We can live with that if the default one is big enough 2524 * for the number of threads, and a submultiple of the one 2525 * we want. In this case we'll waste some vcpu ids, but 2526 * behaviour will be correct */ 2527 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2528 warn_report_err(local_err); 2529 } else { 2530 if (!vsmt_user) { 2531 error_append_hint(&local_err, 2532 "On PPC, a VM with %d threads/core" 2533 " on a host with %d threads/core" 2534 " requires the use of VSMT mode %d.\n", 2535 smp_threads, kvm_smt, spapr->vsmt); 2536 } 2537 kvmppc_error_append_smt_possible_hint(&local_err); 2538 error_propagate(errp, local_err); 2539 } 2540 } 2541 } 2542 /* else TCG: nothing to do currently */ 2543 } 2544 2545 static void spapr_init_cpus(SpaprMachineState *spapr) 2546 { 2547 MachineState *machine = MACHINE(spapr); 2548 MachineClass *mc = MACHINE_GET_CLASS(machine); 2549 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2550 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2551 const CPUArchIdList *possible_cpus; 2552 unsigned int smp_cpus = machine->smp.cpus; 2553 unsigned int smp_threads = machine->smp.threads; 2554 unsigned int max_cpus = machine->smp.max_cpus; 2555 int boot_cores_nr = smp_cpus / smp_threads; 2556 int i; 2557 2558 possible_cpus = mc->possible_cpu_arch_ids(machine); 2559 if (mc->has_hotpluggable_cpus) { 2560 if (smp_cpus % smp_threads) { 2561 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2562 smp_cpus, smp_threads); 2563 exit(1); 2564 } 2565 if (max_cpus % smp_threads) { 2566 error_report("max_cpus (%u) must be multiple of threads (%u)", 2567 max_cpus, smp_threads); 2568 exit(1); 2569 } 2570 } else { 2571 if (max_cpus != smp_cpus) { 2572 error_report("This machine version does not support CPU hotplug"); 2573 exit(1); 2574 } 2575 boot_cores_nr = possible_cpus->len; 2576 } 2577 2578 if (smc->pre_2_10_has_unused_icps) { 2579 int i; 2580 2581 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2582 /* Dummy entries get deregistered when real ICPState objects 2583 * are registered during CPU core hotplug. 2584 */ 2585 pre_2_10_vmstate_register_dummy_icp(i); 2586 } 2587 } 2588 2589 for (i = 0; i < possible_cpus->len; i++) { 2590 int core_id = i * smp_threads; 2591 2592 if (mc->has_hotpluggable_cpus) { 2593 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2594 spapr_vcpu_id(spapr, core_id)); 2595 } 2596 2597 if (i < boot_cores_nr) { 2598 Object *core = object_new(type); 2599 int nr_threads = smp_threads; 2600 2601 /* Handle the partially filled core for older machine types */ 2602 if ((i + 1) * smp_threads >= smp_cpus) { 2603 nr_threads = smp_cpus - i * smp_threads; 2604 } 2605 2606 object_property_set_int(core, "nr-threads", nr_threads, 2607 &error_fatal); 2608 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2609 &error_fatal); 2610 qdev_realize(DEVICE(core), NULL, &error_fatal); 2611 2612 object_unref(core); 2613 } 2614 } 2615 } 2616 2617 static PCIHostState *spapr_create_default_phb(void) 2618 { 2619 DeviceState *dev; 2620 2621 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2622 qdev_prop_set_uint32(dev, "index", 0); 2623 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2624 2625 return PCI_HOST_BRIDGE(dev); 2626 } 2627 2628 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2629 { 2630 MachineState *machine = MACHINE(spapr); 2631 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2632 hwaddr rma_size = machine->ram_size; 2633 hwaddr node0_size = spapr_node0_size(machine); 2634 2635 /* RMA has to fit in the first NUMA node */ 2636 rma_size = MIN(rma_size, node0_size); 2637 2638 /* 2639 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2640 * never exceed that 2641 */ 2642 rma_size = MIN(rma_size, 1 * TiB); 2643 2644 /* 2645 * Clamp the RMA size based on machine type. This is for 2646 * migration compatibility with older qemu versions, which limited 2647 * the RMA size for complicated and mostly bad reasons. 2648 */ 2649 if (smc->rma_limit) { 2650 rma_size = MIN(rma_size, smc->rma_limit); 2651 } 2652 2653 if (rma_size < MIN_RMA_SLOF) { 2654 error_setg(errp, 2655 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2656 "ldMiB guest RMA (Real Mode Area memory)", 2657 MIN_RMA_SLOF / MiB); 2658 return 0; 2659 } 2660 2661 return rma_size; 2662 } 2663 2664 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2665 { 2666 MachineState *machine = MACHINE(spapr); 2667 int i; 2668 2669 for (i = 0; i < machine->ram_slots; i++) { 2670 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2671 } 2672 } 2673 2674 /* pSeries LPAR / sPAPR hardware init */ 2675 static void spapr_machine_init(MachineState *machine) 2676 { 2677 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2678 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2679 MachineClass *mc = MACHINE_GET_CLASS(machine); 2680 const char *bios_default = spapr->vof ? FW_FILE_NAME_VOF : FW_FILE_NAME; 2681 const char *bios_name = machine->firmware ?: bios_default; 2682 const char *kernel_filename = machine->kernel_filename; 2683 const char *initrd_filename = machine->initrd_filename; 2684 PCIHostState *phb; 2685 int i; 2686 MemoryRegion *sysmem = get_system_memory(); 2687 long load_limit, fw_size; 2688 char *filename; 2689 Error *resize_hpt_err = NULL; 2690 2691 /* 2692 * if Secure VM (PEF) support is configured, then initialize it 2693 */ 2694 pef_kvm_init(machine->cgs, &error_fatal); 2695 2696 msi_nonbroken = true; 2697 2698 QLIST_INIT(&spapr->phbs); 2699 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2700 2701 /* Determine capabilities to run with */ 2702 spapr_caps_init(spapr); 2703 2704 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2705 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2706 /* 2707 * If the user explicitly requested a mode we should either 2708 * supply it, or fail completely (which we do below). But if 2709 * it's not set explicitly, we reset our mode to something 2710 * that works 2711 */ 2712 if (resize_hpt_err) { 2713 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2714 error_free(resize_hpt_err); 2715 resize_hpt_err = NULL; 2716 } else { 2717 spapr->resize_hpt = smc->resize_hpt_default; 2718 } 2719 } 2720 2721 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2722 2723 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2724 /* 2725 * User requested HPT resize, but this host can't supply it. Bail out 2726 */ 2727 error_report_err(resize_hpt_err); 2728 exit(1); 2729 } 2730 error_free(resize_hpt_err); 2731 2732 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2733 2734 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2735 load_limit = MIN(spapr->rma_size, FDT_MAX_ADDR) - FW_OVERHEAD; 2736 2737 /* 2738 * VSMT must be set in order to be able to compute VCPU ids, ie to 2739 * call spapr_max_server_number() or spapr_vcpu_id(). 2740 */ 2741 spapr_set_vsmt_mode(spapr, &error_fatal); 2742 2743 /* Set up Interrupt Controller before we create the VCPUs */ 2744 spapr_irq_init(spapr, &error_fatal); 2745 2746 /* Set up containers for ibm,client-architecture-support negotiated options 2747 */ 2748 spapr->ov5 = spapr_ovec_new(); 2749 spapr->ov5_cas = spapr_ovec_new(); 2750 2751 if (smc->dr_lmb_enabled) { 2752 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2753 spapr_validate_node_memory(machine, &error_fatal); 2754 } 2755 2756 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2757 2758 /* Do not advertise FORM2 NUMA support for pseries-6.1 and older */ 2759 if (!smc->pre_6_2_numa_affinity) { 2760 spapr_ovec_set(spapr->ov5, OV5_FORM2_AFFINITY); 2761 } 2762 2763 /* advertise support for dedicated HP event source to guests */ 2764 if (spapr->use_hotplug_event_source) { 2765 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2766 } 2767 2768 /* advertise support for HPT resizing */ 2769 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2770 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2771 } 2772 2773 /* advertise support for ibm,dyamic-memory-v2 */ 2774 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2775 2776 /* advertise XIVE on POWER9 machines */ 2777 if (spapr->irq->xive) { 2778 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2779 } 2780 2781 /* init CPUs */ 2782 spapr_init_cpus(spapr); 2783 2784 spapr->gpu_numa_id = spapr_numa_initial_nvgpu_numa_id(machine); 2785 2786 /* Init numa_assoc_array */ 2787 spapr_numa_associativity_init(spapr, machine); 2788 2789 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2790 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2791 spapr->max_compat_pvr)) { 2792 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2793 /* KVM and TCG always allow GTSE with radix... */ 2794 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2795 } 2796 /* ... but not with hash (currently). */ 2797 2798 if (kvm_enabled()) { 2799 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2800 kvmppc_enable_logical_ci_hcalls(); 2801 kvmppc_enable_set_mode_hcall(); 2802 2803 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2804 kvmppc_enable_clear_ref_mod_hcalls(); 2805 2806 /* Enable H_PAGE_INIT */ 2807 kvmppc_enable_h_page_init(); 2808 } 2809 2810 /* map RAM */ 2811 memory_region_add_subregion(sysmem, 0, machine->ram); 2812 2813 /* always allocate the device memory information */ 2814 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2815 2816 /* initialize hotplug memory address space */ 2817 if (machine->ram_size < machine->maxram_size) { 2818 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2819 /* 2820 * Limit the number of hotpluggable memory slots to half the number 2821 * slots that KVM supports, leaving the other half for PCI and other 2822 * devices. However ensure that number of slots doesn't drop below 32. 2823 */ 2824 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2825 SPAPR_MAX_RAM_SLOTS; 2826 2827 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2828 max_memslots = SPAPR_MAX_RAM_SLOTS; 2829 } 2830 if (machine->ram_slots > max_memslots) { 2831 error_report("Specified number of memory slots %" 2832 PRIu64" exceeds max supported %d", 2833 machine->ram_slots, max_memslots); 2834 exit(1); 2835 } 2836 2837 machine->device_memory->base = ROUND_UP(machine->ram_size, 2838 SPAPR_DEVICE_MEM_ALIGN); 2839 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2840 "device-memory", device_mem_size); 2841 memory_region_add_subregion(sysmem, machine->device_memory->base, 2842 &machine->device_memory->mr); 2843 } 2844 2845 if (smc->dr_lmb_enabled) { 2846 spapr_create_lmb_dr_connectors(spapr); 2847 } 2848 2849 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { 2850 /* Create the error string for live migration blocker */ 2851 error_setg(&spapr->fwnmi_migration_blocker, 2852 "A machine check is being handled during migration. The handler" 2853 "may run and log hardware error on the destination"); 2854 } 2855 2856 if (mc->nvdimm_supported) { 2857 spapr_create_nvdimm_dr_connectors(spapr); 2858 } 2859 2860 /* Set up RTAS event infrastructure */ 2861 spapr_events_init(spapr); 2862 2863 /* Set up the RTC RTAS interfaces */ 2864 spapr_rtc_create(spapr); 2865 2866 /* Set up VIO bus */ 2867 spapr->vio_bus = spapr_vio_bus_init(); 2868 2869 for (i = 0; serial_hd(i); i++) { 2870 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2871 } 2872 2873 /* We always have at least the nvram device on VIO */ 2874 spapr_create_nvram(spapr); 2875 2876 /* 2877 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2878 * connectors (described in root DT node's "ibm,drc-types" property) 2879 * are pre-initialized here. additional child connectors (such as 2880 * connectors for a PHBs PCI slots) are added as needed during their 2881 * parent's realization. 2882 */ 2883 if (smc->dr_phb_enabled) { 2884 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2885 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2886 } 2887 } 2888 2889 /* Set up PCI */ 2890 spapr_pci_rtas_init(); 2891 2892 phb = spapr_create_default_phb(); 2893 2894 for (i = 0; i < nb_nics; i++) { 2895 NICInfo *nd = &nd_table[i]; 2896 2897 if (!nd->model) { 2898 nd->model = g_strdup("spapr-vlan"); 2899 } 2900 2901 if (g_str_equal(nd->model, "spapr-vlan") || 2902 g_str_equal(nd->model, "ibmveth")) { 2903 spapr_vlan_create(spapr->vio_bus, nd); 2904 } else { 2905 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2906 } 2907 } 2908 2909 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2910 spapr_vscsi_create(spapr->vio_bus); 2911 } 2912 2913 /* Graphics */ 2914 if (spapr_vga_init(phb->bus, &error_fatal)) { 2915 spapr->has_graphics = true; 2916 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2917 } 2918 2919 if (machine->usb) { 2920 if (smc->use_ohci_by_default) { 2921 pci_create_simple(phb->bus, -1, "pci-ohci"); 2922 } else { 2923 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2924 } 2925 2926 if (spapr->has_graphics) { 2927 USBBus *usb_bus = usb_bus_find(-1); 2928 2929 usb_create_simple(usb_bus, "usb-kbd"); 2930 usb_create_simple(usb_bus, "usb-mouse"); 2931 } 2932 } 2933 2934 if (kernel_filename) { 2935 spapr->kernel_size = load_elf(kernel_filename, NULL, 2936 translate_kernel_address, spapr, 2937 NULL, NULL, NULL, NULL, 1, 2938 PPC_ELF_MACHINE, 0, 0); 2939 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2940 spapr->kernel_size = load_elf(kernel_filename, NULL, 2941 translate_kernel_address, spapr, 2942 NULL, NULL, NULL, NULL, 0, 2943 PPC_ELF_MACHINE, 0, 0); 2944 spapr->kernel_le = spapr->kernel_size > 0; 2945 } 2946 if (spapr->kernel_size < 0) { 2947 error_report("error loading %s: %s", kernel_filename, 2948 load_elf_strerror(spapr->kernel_size)); 2949 exit(1); 2950 } 2951 2952 /* load initrd */ 2953 if (initrd_filename) { 2954 /* Try to locate the initrd in the gap between the kernel 2955 * and the firmware. Add a bit of space just in case 2956 */ 2957 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 2958 + 0x1ffff) & ~0xffff; 2959 spapr->initrd_size = load_image_targphys(initrd_filename, 2960 spapr->initrd_base, 2961 load_limit 2962 - spapr->initrd_base); 2963 if (spapr->initrd_size < 0) { 2964 error_report("could not load initial ram disk '%s'", 2965 initrd_filename); 2966 exit(1); 2967 } 2968 } 2969 } 2970 2971 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2972 if (!filename) { 2973 error_report("Could not find LPAR firmware '%s'", bios_name); 2974 exit(1); 2975 } 2976 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2977 if (fw_size <= 0) { 2978 error_report("Could not load LPAR firmware '%s'", filename); 2979 exit(1); 2980 } 2981 g_free(filename); 2982 2983 /* FIXME: Should register things through the MachineState's qdev 2984 * interface, this is a legacy from the sPAPREnvironment structure 2985 * which predated MachineState but had a similar function */ 2986 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2987 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 2988 &savevm_htab_handlers, spapr); 2989 2990 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 2991 2992 qemu_register_boot_set(spapr_boot_set, spapr); 2993 2994 /* 2995 * Nothing needs to be done to resume a suspended guest because 2996 * suspending does not change the machine state, so no need for 2997 * a ->wakeup method. 2998 */ 2999 qemu_register_wakeup_support(); 3000 3001 if (kvm_enabled()) { 3002 /* to stop and start vmclock */ 3003 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3004 &spapr->tb); 3005 3006 kvmppc_spapr_enable_inkernel_multitce(); 3007 } 3008 3009 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3010 if (spapr->vof) { 3011 spapr->vof->fw_size = fw_size; /* for claim() on itself */ 3012 spapr_register_hypercall(KVMPPC_H_VOF_CLIENT, spapr_h_vof_client); 3013 } 3014 } 3015 3016 #define DEFAULT_KVM_TYPE "auto" 3017 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3018 { 3019 /* 3020 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to 3021 * accomodate the 'HV' and 'PV' formats that exists in the 3022 * wild. The 'auto' mode is being introduced already as 3023 * lower-case, thus we don't need to bother checking for 3024 * "AUTO". 3025 */ 3026 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) { 3027 return 0; 3028 } 3029 3030 if (!g_ascii_strcasecmp(vm_type, "hv")) { 3031 return 1; 3032 } 3033 3034 if (!g_ascii_strcasecmp(vm_type, "pr")) { 3035 return 2; 3036 } 3037 3038 error_report("Unknown kvm-type specified '%s'", vm_type); 3039 exit(1); 3040 } 3041 3042 /* 3043 * Implementation of an interface to adjust firmware path 3044 * for the bootindex property handling. 3045 */ 3046 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3047 DeviceState *dev) 3048 { 3049 #define CAST(type, obj, name) \ 3050 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3051 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3052 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3053 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3054 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3055 3056 if (d) { 3057 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3058 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3059 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3060 3061 if (spapr) { 3062 /* 3063 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3064 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3065 * 0x8000 | (target << 8) | (bus << 5) | lun 3066 * (see the "Logical unit addressing format" table in SAM5) 3067 */ 3068 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3069 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3070 (uint64_t)id << 48); 3071 } else if (virtio) { 3072 /* 3073 * We use SRP luns of the form 01000000 | (target << 8) | lun 3074 * in the top 32 bits of the 64-bit LUN 3075 * Note: the quote above is from SLOF and it is wrong, 3076 * the actual binding is: 3077 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3078 */ 3079 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3080 if (d->lun >= 256) { 3081 /* Use the LUN "flat space addressing method" */ 3082 id |= 0x4000; 3083 } 3084 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3085 (uint64_t)id << 32); 3086 } else if (usb) { 3087 /* 3088 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3089 * in the top 32 bits of the 64-bit LUN 3090 */ 3091 unsigned usb_port = atoi(usb->port->path); 3092 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3093 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3094 (uint64_t)id << 32); 3095 } 3096 } 3097 3098 /* 3099 * SLOF probes the USB devices, and if it recognizes that the device is a 3100 * storage device, it changes its name to "storage" instead of "usb-host", 3101 * and additionally adds a child node for the SCSI LUN, so the correct 3102 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3103 */ 3104 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3105 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3106 if (usb_device_is_scsi_storage(usbdev)) { 3107 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3108 } 3109 } 3110 3111 if (phb) { 3112 /* Replace "pci" with "pci@800000020000000" */ 3113 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3114 } 3115 3116 if (vsc) { 3117 /* Same logic as virtio above */ 3118 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3119 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3120 } 3121 3122 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3123 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3124 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3125 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3126 } 3127 3128 if (pcidev) { 3129 return spapr_pci_fw_dev_name(pcidev); 3130 } 3131 3132 return NULL; 3133 } 3134 3135 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3136 { 3137 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3138 3139 return g_strdup(spapr->kvm_type); 3140 } 3141 3142 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3143 { 3144 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3145 3146 g_free(spapr->kvm_type); 3147 spapr->kvm_type = g_strdup(value); 3148 } 3149 3150 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3151 { 3152 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3153 3154 return spapr->use_hotplug_event_source; 3155 } 3156 3157 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3158 Error **errp) 3159 { 3160 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3161 3162 spapr->use_hotplug_event_source = value; 3163 } 3164 3165 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3166 { 3167 return true; 3168 } 3169 3170 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3171 { 3172 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3173 3174 switch (spapr->resize_hpt) { 3175 case SPAPR_RESIZE_HPT_DEFAULT: 3176 return g_strdup("default"); 3177 case SPAPR_RESIZE_HPT_DISABLED: 3178 return g_strdup("disabled"); 3179 case SPAPR_RESIZE_HPT_ENABLED: 3180 return g_strdup("enabled"); 3181 case SPAPR_RESIZE_HPT_REQUIRED: 3182 return g_strdup("required"); 3183 } 3184 g_assert_not_reached(); 3185 } 3186 3187 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3188 { 3189 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3190 3191 if (strcmp(value, "default") == 0) { 3192 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3193 } else if (strcmp(value, "disabled") == 0) { 3194 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3195 } else if (strcmp(value, "enabled") == 0) { 3196 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3197 } else if (strcmp(value, "required") == 0) { 3198 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3199 } else { 3200 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3201 } 3202 } 3203 3204 static bool spapr_get_vof(Object *obj, Error **errp) 3205 { 3206 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3207 3208 return spapr->vof != NULL; 3209 } 3210 3211 static void spapr_set_vof(Object *obj, bool value, Error **errp) 3212 { 3213 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3214 3215 if (spapr->vof) { 3216 vof_cleanup(spapr->vof); 3217 g_free(spapr->vof); 3218 spapr->vof = NULL; 3219 } 3220 if (!value) { 3221 return; 3222 } 3223 spapr->vof = g_malloc0(sizeof(*spapr->vof)); 3224 } 3225 3226 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3227 { 3228 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3229 3230 if (spapr->irq == &spapr_irq_xics_legacy) { 3231 return g_strdup("legacy"); 3232 } else if (spapr->irq == &spapr_irq_xics) { 3233 return g_strdup("xics"); 3234 } else if (spapr->irq == &spapr_irq_xive) { 3235 return g_strdup("xive"); 3236 } else if (spapr->irq == &spapr_irq_dual) { 3237 return g_strdup("dual"); 3238 } 3239 g_assert_not_reached(); 3240 } 3241 3242 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3243 { 3244 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3245 3246 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3247 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3248 return; 3249 } 3250 3251 /* The legacy IRQ backend can not be set */ 3252 if (strcmp(value, "xics") == 0) { 3253 spapr->irq = &spapr_irq_xics; 3254 } else if (strcmp(value, "xive") == 0) { 3255 spapr->irq = &spapr_irq_xive; 3256 } else if (strcmp(value, "dual") == 0) { 3257 spapr->irq = &spapr_irq_dual; 3258 } else { 3259 error_setg(errp, "Bad value for \"ic-mode\" property"); 3260 } 3261 } 3262 3263 static char *spapr_get_host_model(Object *obj, Error **errp) 3264 { 3265 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3266 3267 return g_strdup(spapr->host_model); 3268 } 3269 3270 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3271 { 3272 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3273 3274 g_free(spapr->host_model); 3275 spapr->host_model = g_strdup(value); 3276 } 3277 3278 static char *spapr_get_host_serial(Object *obj, Error **errp) 3279 { 3280 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3281 3282 return g_strdup(spapr->host_serial); 3283 } 3284 3285 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3286 { 3287 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3288 3289 g_free(spapr->host_serial); 3290 spapr->host_serial = g_strdup(value); 3291 } 3292 3293 static void spapr_instance_init(Object *obj) 3294 { 3295 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3296 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3297 MachineState *ms = MACHINE(spapr); 3298 MachineClass *mc = MACHINE_GET_CLASS(ms); 3299 3300 /* 3301 * NVDIMM support went live in 5.1 without considering that, in 3302 * other archs, the user needs to enable NVDIMM support with the 3303 * 'nvdimm' machine option and the default behavior is NVDIMM 3304 * support disabled. It is too late to roll back to the standard 3305 * behavior without breaking 5.1 guests. 3306 */ 3307 if (mc->nvdimm_supported) { 3308 ms->nvdimms_state->is_enabled = true; 3309 } 3310 3311 spapr->htab_fd = -1; 3312 spapr->use_hotplug_event_source = true; 3313 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE); 3314 object_property_add_str(obj, "kvm-type", 3315 spapr_get_kvm_type, spapr_set_kvm_type); 3316 object_property_set_description(obj, "kvm-type", 3317 "Specifies the KVM virtualization mode (auto," 3318 " hv, pr). Defaults to 'auto'. This mode will use" 3319 " any available KVM module loaded in the host," 3320 " where kvm_hv takes precedence if both kvm_hv and" 3321 " kvm_pr are loaded."); 3322 object_property_add_bool(obj, "modern-hotplug-events", 3323 spapr_get_modern_hotplug_events, 3324 spapr_set_modern_hotplug_events); 3325 object_property_set_description(obj, "modern-hotplug-events", 3326 "Use dedicated hotplug event mechanism in" 3327 " place of standard EPOW events when possible" 3328 " (required for memory hot-unplug support)"); 3329 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3330 "Maximum permitted CPU compatibility mode"); 3331 3332 object_property_add_str(obj, "resize-hpt", 3333 spapr_get_resize_hpt, spapr_set_resize_hpt); 3334 object_property_set_description(obj, "resize-hpt", 3335 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3336 object_property_add_uint32_ptr(obj, "vsmt", 3337 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3338 object_property_set_description(obj, "vsmt", 3339 "Virtual SMT: KVM behaves as if this were" 3340 " the host's SMT mode"); 3341 3342 object_property_add_bool(obj, "vfio-no-msix-emulation", 3343 spapr_get_msix_emulation, NULL); 3344 3345 object_property_add_uint64_ptr(obj, "kernel-addr", 3346 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3347 object_property_set_description(obj, "kernel-addr", 3348 stringify(KERNEL_LOAD_ADDR) 3349 " for -kernel is the default"); 3350 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3351 3352 object_property_add_bool(obj, "x-vof", spapr_get_vof, spapr_set_vof); 3353 object_property_set_description(obj, "x-vof", 3354 "Enable Virtual Open Firmware (experimental)"); 3355 3356 /* The machine class defines the default interrupt controller mode */ 3357 spapr->irq = smc->irq; 3358 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3359 spapr_set_ic_mode); 3360 object_property_set_description(obj, "ic-mode", 3361 "Specifies the interrupt controller mode (xics, xive, dual)"); 3362 3363 object_property_add_str(obj, "host-model", 3364 spapr_get_host_model, spapr_set_host_model); 3365 object_property_set_description(obj, "host-model", 3366 "Host model to advertise in guest device tree"); 3367 object_property_add_str(obj, "host-serial", 3368 spapr_get_host_serial, spapr_set_host_serial); 3369 object_property_set_description(obj, "host-serial", 3370 "Host serial number to advertise in guest device tree"); 3371 } 3372 3373 static void spapr_machine_finalizefn(Object *obj) 3374 { 3375 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3376 3377 g_free(spapr->kvm_type); 3378 } 3379 3380 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3381 { 3382 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3383 PowerPCCPU *cpu = POWERPC_CPU(cs); 3384 CPUPPCState *env = &cpu->env; 3385 3386 cpu_synchronize_state(cs); 3387 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3388 if (spapr->fwnmi_system_reset_addr != -1) { 3389 uint64_t rtas_addr, addr; 3390 3391 /* get rtas addr from fdt */ 3392 rtas_addr = spapr_get_rtas_addr(); 3393 if (!rtas_addr) { 3394 qemu_system_guest_panicked(NULL); 3395 return; 3396 } 3397 3398 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3399 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3400 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3401 env->gpr[3] = addr; 3402 } 3403 ppc_cpu_do_system_reset(cs); 3404 if (spapr->fwnmi_system_reset_addr != -1) { 3405 env->nip = spapr->fwnmi_system_reset_addr; 3406 } 3407 } 3408 3409 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3410 { 3411 CPUState *cs; 3412 3413 CPU_FOREACH(cs) { 3414 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3415 } 3416 } 3417 3418 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3419 void *fdt, int *fdt_start_offset, Error **errp) 3420 { 3421 uint64_t addr; 3422 uint32_t node; 3423 3424 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3425 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3426 &error_abort); 3427 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3428 SPAPR_MEMORY_BLOCK_SIZE); 3429 return 0; 3430 } 3431 3432 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3433 bool dedicated_hp_event_source) 3434 { 3435 SpaprDrc *drc; 3436 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3437 int i; 3438 uint64_t addr = addr_start; 3439 bool hotplugged = spapr_drc_hotplugged(dev); 3440 3441 for (i = 0; i < nr_lmbs; i++) { 3442 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3443 addr / SPAPR_MEMORY_BLOCK_SIZE); 3444 g_assert(drc); 3445 3446 /* 3447 * memory_device_get_free_addr() provided a range of free addresses 3448 * that doesn't overlap with any existing mapping at pre-plug. The 3449 * corresponding LMB DRCs are thus assumed to be all attachable. 3450 */ 3451 spapr_drc_attach(drc, dev); 3452 if (!hotplugged) { 3453 spapr_drc_reset(drc); 3454 } 3455 addr += SPAPR_MEMORY_BLOCK_SIZE; 3456 } 3457 /* send hotplug notification to the 3458 * guest only in case of hotplugged memory 3459 */ 3460 if (hotplugged) { 3461 if (dedicated_hp_event_source) { 3462 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3463 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3464 g_assert(drc); 3465 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3466 nr_lmbs, 3467 spapr_drc_index(drc)); 3468 } else { 3469 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3470 nr_lmbs); 3471 } 3472 } 3473 } 3474 3475 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3476 { 3477 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3478 PCDIMMDevice *dimm = PC_DIMM(dev); 3479 uint64_t size, addr; 3480 int64_t slot; 3481 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3482 3483 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3484 3485 pc_dimm_plug(dimm, MACHINE(ms)); 3486 3487 if (!is_nvdimm) { 3488 addr = object_property_get_uint(OBJECT(dimm), 3489 PC_DIMM_ADDR_PROP, &error_abort); 3490 spapr_add_lmbs(dev, addr, size, 3491 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT)); 3492 } else { 3493 slot = object_property_get_int(OBJECT(dimm), 3494 PC_DIMM_SLOT_PROP, &error_abort); 3495 /* We should have valid slot number at this point */ 3496 g_assert(slot >= 0); 3497 spapr_add_nvdimm(dev, slot); 3498 } 3499 } 3500 3501 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3502 Error **errp) 3503 { 3504 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3505 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3506 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3507 PCDIMMDevice *dimm = PC_DIMM(dev); 3508 Error *local_err = NULL; 3509 uint64_t size; 3510 Object *memdev; 3511 hwaddr pagesize; 3512 3513 if (!smc->dr_lmb_enabled) { 3514 error_setg(errp, "Memory hotplug not supported for this machine"); 3515 return; 3516 } 3517 3518 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3519 if (local_err) { 3520 error_propagate(errp, local_err); 3521 return; 3522 } 3523 3524 if (is_nvdimm) { 3525 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3526 return; 3527 } 3528 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3529 error_setg(errp, "Hotplugged memory size must be a multiple of " 3530 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3531 return; 3532 } 3533 3534 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3535 &error_abort); 3536 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3537 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3538 return; 3539 } 3540 3541 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3542 } 3543 3544 struct SpaprDimmState { 3545 PCDIMMDevice *dimm; 3546 uint32_t nr_lmbs; 3547 QTAILQ_ENTRY(SpaprDimmState) next; 3548 }; 3549 3550 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3551 PCDIMMDevice *dimm) 3552 { 3553 SpaprDimmState *dimm_state = NULL; 3554 3555 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3556 if (dimm_state->dimm == dimm) { 3557 break; 3558 } 3559 } 3560 return dimm_state; 3561 } 3562 3563 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3564 uint32_t nr_lmbs, 3565 PCDIMMDevice *dimm) 3566 { 3567 SpaprDimmState *ds = NULL; 3568 3569 /* 3570 * If this request is for a DIMM whose removal had failed earlier 3571 * (due to guest's refusal to remove the LMBs), we would have this 3572 * dimm already in the pending_dimm_unplugs list. In that 3573 * case don't add again. 3574 */ 3575 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3576 if (!ds) { 3577 ds = g_malloc0(sizeof(SpaprDimmState)); 3578 ds->nr_lmbs = nr_lmbs; 3579 ds->dimm = dimm; 3580 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3581 } 3582 return ds; 3583 } 3584 3585 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3586 SpaprDimmState *dimm_state) 3587 { 3588 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3589 g_free(dimm_state); 3590 } 3591 3592 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3593 PCDIMMDevice *dimm) 3594 { 3595 SpaprDrc *drc; 3596 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3597 &error_abort); 3598 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3599 uint32_t avail_lmbs = 0; 3600 uint64_t addr_start, addr; 3601 int i; 3602 3603 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3604 &error_abort); 3605 3606 addr = addr_start; 3607 for (i = 0; i < nr_lmbs; i++) { 3608 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3609 addr / SPAPR_MEMORY_BLOCK_SIZE); 3610 g_assert(drc); 3611 if (drc->dev) { 3612 avail_lmbs++; 3613 } 3614 addr += SPAPR_MEMORY_BLOCK_SIZE; 3615 } 3616 3617 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3618 } 3619 3620 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev) 3621 { 3622 SpaprDimmState *ds; 3623 PCDIMMDevice *dimm; 3624 SpaprDrc *drc; 3625 uint32_t nr_lmbs; 3626 uint64_t size, addr_start, addr; 3627 g_autofree char *qapi_error = NULL; 3628 int i; 3629 3630 if (!dev) { 3631 return; 3632 } 3633 3634 dimm = PC_DIMM(dev); 3635 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3636 3637 /* 3638 * 'ds == NULL' would mean that the DIMM doesn't have a pending 3639 * unplug state, but one of its DRC is marked as unplug_requested. 3640 * This is bad and weird enough to g_assert() out. 3641 */ 3642 g_assert(ds); 3643 3644 spapr_pending_dimm_unplugs_remove(spapr, ds); 3645 3646 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3647 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3648 3649 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3650 &error_abort); 3651 3652 addr = addr_start; 3653 for (i = 0; i < nr_lmbs; i++) { 3654 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3655 addr / SPAPR_MEMORY_BLOCK_SIZE); 3656 g_assert(drc); 3657 3658 drc->unplug_requested = false; 3659 addr += SPAPR_MEMORY_BLOCK_SIZE; 3660 } 3661 3662 /* 3663 * Tell QAPI that something happened and the memory 3664 * hotunplug wasn't successful. Keep sending 3665 * MEM_UNPLUG_ERROR even while sending 3666 * DEVICE_UNPLUG_GUEST_ERROR until the deprecation of 3667 * MEM_UNPLUG_ERROR is due. 3668 */ 3669 qapi_error = g_strdup_printf("Memory hotunplug rejected by the guest " 3670 "for device %s", dev->id); 3671 3672 qapi_event_send_mem_unplug_error(dev->id ? : "", qapi_error); 3673 3674 qapi_event_send_device_unplug_guest_error(!!dev->id, dev->id, 3675 dev->canonical_path); 3676 } 3677 3678 /* Callback to be called during DRC release. */ 3679 void spapr_lmb_release(DeviceState *dev) 3680 { 3681 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3682 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3683 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3684 3685 /* This information will get lost if a migration occurs 3686 * during the unplug process. In this case recover it. */ 3687 if (ds == NULL) { 3688 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3689 g_assert(ds); 3690 /* The DRC being examined by the caller at least must be counted */ 3691 g_assert(ds->nr_lmbs); 3692 } 3693 3694 if (--ds->nr_lmbs) { 3695 return; 3696 } 3697 3698 /* 3699 * Now that all the LMBs have been removed by the guest, call the 3700 * unplug handler chain. This can never fail. 3701 */ 3702 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3703 object_unparent(OBJECT(dev)); 3704 } 3705 3706 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3707 { 3708 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3709 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3710 3711 /* We really shouldn't get this far without anything to unplug */ 3712 g_assert(ds); 3713 3714 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3715 qdev_unrealize(dev); 3716 spapr_pending_dimm_unplugs_remove(spapr, ds); 3717 } 3718 3719 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3720 DeviceState *dev, Error **errp) 3721 { 3722 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3723 PCDIMMDevice *dimm = PC_DIMM(dev); 3724 uint32_t nr_lmbs; 3725 uint64_t size, addr_start, addr; 3726 int i; 3727 SpaprDrc *drc; 3728 3729 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3730 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3731 return; 3732 } 3733 3734 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3735 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3736 3737 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3738 &error_abort); 3739 3740 /* 3741 * An existing pending dimm state for this DIMM means that there is an 3742 * unplug operation in progress, waiting for the spapr_lmb_release 3743 * callback to complete the job (BQL can't cover that far). In this case, 3744 * bail out to avoid detaching DRCs that were already released. 3745 */ 3746 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3747 error_setg(errp, "Memory unplug already in progress for device %s", 3748 dev->id); 3749 return; 3750 } 3751 3752 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3753 3754 addr = addr_start; 3755 for (i = 0; i < nr_lmbs; i++) { 3756 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3757 addr / SPAPR_MEMORY_BLOCK_SIZE); 3758 g_assert(drc); 3759 3760 spapr_drc_unplug_request(drc); 3761 addr += SPAPR_MEMORY_BLOCK_SIZE; 3762 } 3763 3764 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3765 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3766 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3767 nr_lmbs, spapr_drc_index(drc)); 3768 } 3769 3770 /* Callback to be called during DRC release. */ 3771 void spapr_core_release(DeviceState *dev) 3772 { 3773 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3774 3775 /* Call the unplug handler chain. This can never fail. */ 3776 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3777 object_unparent(OBJECT(dev)); 3778 } 3779 3780 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3781 { 3782 MachineState *ms = MACHINE(hotplug_dev); 3783 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3784 CPUCore *cc = CPU_CORE(dev); 3785 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3786 3787 if (smc->pre_2_10_has_unused_icps) { 3788 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3789 int i; 3790 3791 for (i = 0; i < cc->nr_threads; i++) { 3792 CPUState *cs = CPU(sc->threads[i]); 3793 3794 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3795 } 3796 } 3797 3798 assert(core_slot); 3799 core_slot->cpu = NULL; 3800 qdev_unrealize(dev); 3801 } 3802 3803 static 3804 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3805 Error **errp) 3806 { 3807 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3808 int index; 3809 SpaprDrc *drc; 3810 CPUCore *cc = CPU_CORE(dev); 3811 3812 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3813 error_setg(errp, "Unable to find CPU core with core-id: %d", 3814 cc->core_id); 3815 return; 3816 } 3817 if (index == 0) { 3818 error_setg(errp, "Boot CPU core may not be unplugged"); 3819 return; 3820 } 3821 3822 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3823 spapr_vcpu_id(spapr, cc->core_id)); 3824 g_assert(drc); 3825 3826 if (!spapr_drc_unplug_requested(drc)) { 3827 spapr_drc_unplug_request(drc); 3828 } 3829 3830 /* 3831 * spapr_hotplug_req_remove_by_index is left unguarded, out of the 3832 * "!spapr_drc_unplug_requested" check, to allow for multiple IRQ 3833 * pulses removing the same CPU. Otherwise, in an failed hotunplug 3834 * attempt (e.g. the kernel will refuse to remove the last online 3835 * CPU), we will never attempt it again because unplug_requested 3836 * will still be 'true' in that case. 3837 */ 3838 spapr_hotplug_req_remove_by_index(drc); 3839 } 3840 3841 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3842 void *fdt, int *fdt_start_offset, Error **errp) 3843 { 3844 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3845 CPUState *cs = CPU(core->threads[0]); 3846 PowerPCCPU *cpu = POWERPC_CPU(cs); 3847 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3848 int id = spapr_get_vcpu_id(cpu); 3849 g_autofree char *nodename = NULL; 3850 int offset; 3851 3852 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3853 offset = fdt_add_subnode(fdt, 0, nodename); 3854 3855 spapr_dt_cpu(cs, fdt, offset, spapr); 3856 3857 /* 3858 * spapr_dt_cpu() does not fill the 'name' property in the 3859 * CPU node. The function is called during boot process, before 3860 * and after CAS, and overwriting the 'name' property written 3861 * by SLOF is not allowed. 3862 * 3863 * Write it manually after spapr_dt_cpu(). This makes the hotplug 3864 * CPUs more compatible with the coldplugged ones, which have 3865 * the 'name' property. Linux Kernel also relies on this 3866 * property to identify CPU nodes. 3867 */ 3868 _FDT((fdt_setprop_string(fdt, offset, "name", nodename))); 3869 3870 *fdt_start_offset = offset; 3871 return 0; 3872 } 3873 3874 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3875 { 3876 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3877 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3878 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3879 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3880 CPUCore *cc = CPU_CORE(dev); 3881 CPUState *cs; 3882 SpaprDrc *drc; 3883 CPUArchId *core_slot; 3884 int index; 3885 bool hotplugged = spapr_drc_hotplugged(dev); 3886 int i; 3887 3888 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3889 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */ 3890 3891 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3892 spapr_vcpu_id(spapr, cc->core_id)); 3893 3894 g_assert(drc || !mc->has_hotpluggable_cpus); 3895 3896 if (drc) { 3897 /* 3898 * spapr_core_pre_plug() already buys us this is a brand new 3899 * core being plugged into a free slot. Nothing should already 3900 * be attached to the corresponding DRC. 3901 */ 3902 spapr_drc_attach(drc, dev); 3903 3904 if (hotplugged) { 3905 /* 3906 * Send hotplug notification interrupt to the guest only 3907 * in case of hotplugged CPUs. 3908 */ 3909 spapr_hotplug_req_add_by_index(drc); 3910 } else { 3911 spapr_drc_reset(drc); 3912 } 3913 } 3914 3915 core_slot->cpu = OBJECT(dev); 3916 3917 /* 3918 * Set compatibility mode to match the boot CPU, which was either set 3919 * by the machine reset code or by CAS. This really shouldn't fail at 3920 * this point. 3921 */ 3922 if (hotplugged) { 3923 for (i = 0; i < cc->nr_threads; i++) { 3924 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3925 &error_abort); 3926 } 3927 } 3928 3929 if (smc->pre_2_10_has_unused_icps) { 3930 for (i = 0; i < cc->nr_threads; i++) { 3931 cs = CPU(core->threads[i]); 3932 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3933 } 3934 } 3935 } 3936 3937 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3938 Error **errp) 3939 { 3940 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3941 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3942 CPUCore *cc = CPU_CORE(dev); 3943 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3944 const char *type = object_get_typename(OBJECT(dev)); 3945 CPUArchId *core_slot; 3946 int index; 3947 unsigned int smp_threads = machine->smp.threads; 3948 3949 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3950 error_setg(errp, "CPU hotplug not supported for this machine"); 3951 return; 3952 } 3953 3954 if (strcmp(base_core_type, type)) { 3955 error_setg(errp, "CPU core type should be %s", base_core_type); 3956 return; 3957 } 3958 3959 if (cc->core_id % smp_threads) { 3960 error_setg(errp, "invalid core id %d", cc->core_id); 3961 return; 3962 } 3963 3964 /* 3965 * In general we should have homogeneous threads-per-core, but old 3966 * (pre hotplug support) machine types allow the last core to have 3967 * reduced threads as a compatibility hack for when we allowed 3968 * total vcpus not a multiple of threads-per-core. 3969 */ 3970 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3971 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 3972 smp_threads); 3973 return; 3974 } 3975 3976 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3977 if (!core_slot) { 3978 error_setg(errp, "core id %d out of range", cc->core_id); 3979 return; 3980 } 3981 3982 if (core_slot->cpu) { 3983 error_setg(errp, "core %d already populated", cc->core_id); 3984 return; 3985 } 3986 3987 numa_cpu_pre_plug(core_slot, dev, errp); 3988 } 3989 3990 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3991 void *fdt, int *fdt_start_offset, Error **errp) 3992 { 3993 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3994 int intc_phandle; 3995 3996 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3997 if (intc_phandle <= 0) { 3998 return -1; 3999 } 4000 4001 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 4002 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 4003 return -1; 4004 } 4005 4006 /* generally SLOF creates these, for hotplug it's up to QEMU */ 4007 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 4008 4009 return 0; 4010 } 4011 4012 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4013 Error **errp) 4014 { 4015 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4016 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4017 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4018 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 4019 SpaprDrc *drc; 4020 4021 if (dev->hotplugged && !smc->dr_phb_enabled) { 4022 error_setg(errp, "PHB hotplug not supported for this machine"); 4023 return false; 4024 } 4025 4026 if (sphb->index == (uint32_t)-1) { 4027 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 4028 return false; 4029 } 4030 4031 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4032 if (drc && drc->dev) { 4033 error_setg(errp, "PHB %d already attached", sphb->index); 4034 return false; 4035 } 4036 4037 /* 4038 * This will check that sphb->index doesn't exceed the maximum number of 4039 * PHBs for the current machine type. 4040 */ 4041 return 4042 smc->phb_placement(spapr, sphb->index, 4043 &sphb->buid, &sphb->io_win_addr, 4044 &sphb->mem_win_addr, &sphb->mem64_win_addr, 4045 windows_supported, sphb->dma_liobn, 4046 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 4047 errp); 4048 } 4049 4050 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4051 { 4052 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4053 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4054 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4055 SpaprDrc *drc; 4056 bool hotplugged = spapr_drc_hotplugged(dev); 4057 4058 if (!smc->dr_phb_enabled) { 4059 return; 4060 } 4061 4062 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4063 /* hotplug hooks should check it's enabled before getting this far */ 4064 assert(drc); 4065 4066 /* spapr_phb_pre_plug() already checked the DRC is attachable */ 4067 spapr_drc_attach(drc, dev); 4068 4069 if (hotplugged) { 4070 spapr_hotplug_req_add_by_index(drc); 4071 } else { 4072 spapr_drc_reset(drc); 4073 } 4074 } 4075 4076 void spapr_phb_release(DeviceState *dev) 4077 { 4078 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4079 4080 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4081 object_unparent(OBJECT(dev)); 4082 } 4083 4084 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4085 { 4086 qdev_unrealize(dev); 4087 } 4088 4089 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4090 DeviceState *dev, Error **errp) 4091 { 4092 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4093 SpaprDrc *drc; 4094 4095 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4096 assert(drc); 4097 4098 if (!spapr_drc_unplug_requested(drc)) { 4099 spapr_drc_unplug_request(drc); 4100 spapr_hotplug_req_remove_by_index(drc); 4101 } else { 4102 error_setg(errp, 4103 "PCI Host Bridge unplug already in progress for device %s", 4104 dev->id); 4105 } 4106 } 4107 4108 static 4109 bool spapr_tpm_proxy_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4110 Error **errp) 4111 { 4112 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4113 4114 if (spapr->tpm_proxy != NULL) { 4115 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4116 return false; 4117 } 4118 4119 return true; 4120 } 4121 4122 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4123 { 4124 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4125 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4126 4127 /* Already checked in spapr_tpm_proxy_pre_plug() */ 4128 g_assert(spapr->tpm_proxy == NULL); 4129 4130 spapr->tpm_proxy = tpm_proxy; 4131 } 4132 4133 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4134 { 4135 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4136 4137 qdev_unrealize(dev); 4138 object_unparent(OBJECT(dev)); 4139 spapr->tpm_proxy = NULL; 4140 } 4141 4142 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4143 DeviceState *dev, Error **errp) 4144 { 4145 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4146 spapr_memory_plug(hotplug_dev, dev); 4147 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4148 spapr_core_plug(hotplug_dev, dev); 4149 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4150 spapr_phb_plug(hotplug_dev, dev); 4151 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4152 spapr_tpm_proxy_plug(hotplug_dev, dev); 4153 } 4154 } 4155 4156 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4157 DeviceState *dev, Error **errp) 4158 { 4159 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4160 spapr_memory_unplug(hotplug_dev, dev); 4161 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4162 spapr_core_unplug(hotplug_dev, dev); 4163 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4164 spapr_phb_unplug(hotplug_dev, dev); 4165 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4166 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4167 } 4168 } 4169 4170 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr) 4171 { 4172 return spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT) || 4173 /* 4174 * CAS will process all pending unplug requests. 4175 * 4176 * HACK: a guest could theoretically have cleared all bits in OV5, 4177 * but none of the guests we care for do. 4178 */ 4179 spapr_ovec_empty(spapr->ov5_cas); 4180 } 4181 4182 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4183 DeviceState *dev, Error **errp) 4184 { 4185 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4186 MachineClass *mc = MACHINE_GET_CLASS(sms); 4187 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4188 4189 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4190 if (spapr_memory_hot_unplug_supported(sms)) { 4191 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4192 } else { 4193 error_setg(errp, "Memory hot unplug not supported for this guest"); 4194 } 4195 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4196 if (!mc->has_hotpluggable_cpus) { 4197 error_setg(errp, "CPU hot unplug not supported on this machine"); 4198 return; 4199 } 4200 spapr_core_unplug_request(hotplug_dev, dev, errp); 4201 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4202 if (!smc->dr_phb_enabled) { 4203 error_setg(errp, "PHB hot unplug not supported on this machine"); 4204 return; 4205 } 4206 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4207 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4208 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4209 } 4210 } 4211 4212 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4213 DeviceState *dev, Error **errp) 4214 { 4215 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4216 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4217 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4218 spapr_core_pre_plug(hotplug_dev, dev, errp); 4219 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4220 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4221 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4222 spapr_tpm_proxy_pre_plug(hotplug_dev, dev, errp); 4223 } 4224 } 4225 4226 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4227 DeviceState *dev) 4228 { 4229 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4230 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4231 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4232 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4233 return HOTPLUG_HANDLER(machine); 4234 } 4235 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4236 PCIDevice *pcidev = PCI_DEVICE(dev); 4237 PCIBus *root = pci_device_root_bus(pcidev); 4238 SpaprPhbState *phb = 4239 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4240 TYPE_SPAPR_PCI_HOST_BRIDGE); 4241 4242 if (phb) { 4243 return HOTPLUG_HANDLER(phb); 4244 } 4245 } 4246 return NULL; 4247 } 4248 4249 static CpuInstanceProperties 4250 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4251 { 4252 CPUArchId *core_slot; 4253 MachineClass *mc = MACHINE_GET_CLASS(machine); 4254 4255 /* make sure possible_cpu are intialized */ 4256 mc->possible_cpu_arch_ids(machine); 4257 /* get CPU core slot containing thread that matches cpu_index */ 4258 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4259 assert(core_slot); 4260 return core_slot->props; 4261 } 4262 4263 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4264 { 4265 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4266 } 4267 4268 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4269 { 4270 int i; 4271 unsigned int smp_threads = machine->smp.threads; 4272 unsigned int smp_cpus = machine->smp.cpus; 4273 const char *core_type; 4274 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4275 MachineClass *mc = MACHINE_GET_CLASS(machine); 4276 4277 if (!mc->has_hotpluggable_cpus) { 4278 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4279 } 4280 if (machine->possible_cpus) { 4281 assert(machine->possible_cpus->len == spapr_max_cores); 4282 return machine->possible_cpus; 4283 } 4284 4285 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4286 if (!core_type) { 4287 error_report("Unable to find sPAPR CPU Core definition"); 4288 exit(1); 4289 } 4290 4291 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4292 sizeof(CPUArchId) * spapr_max_cores); 4293 machine->possible_cpus->len = spapr_max_cores; 4294 for (i = 0; i < machine->possible_cpus->len; i++) { 4295 int core_id = i * smp_threads; 4296 4297 machine->possible_cpus->cpus[i].type = core_type; 4298 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4299 machine->possible_cpus->cpus[i].arch_id = core_id; 4300 machine->possible_cpus->cpus[i].props.has_core_id = true; 4301 machine->possible_cpus->cpus[i].props.core_id = core_id; 4302 } 4303 return machine->possible_cpus; 4304 } 4305 4306 static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4307 uint64_t *buid, hwaddr *pio, 4308 hwaddr *mmio32, hwaddr *mmio64, 4309 unsigned n_dma, uint32_t *liobns, 4310 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4311 { 4312 /* 4313 * New-style PHB window placement. 4314 * 4315 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4316 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4317 * windows. 4318 * 4319 * Some guest kernels can't work with MMIO windows above 1<<46 4320 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4321 * 4322 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4323 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4324 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4325 * 1TiB 64-bit MMIO windows for each PHB. 4326 */ 4327 const uint64_t base_buid = 0x800000020000000ULL; 4328 int i; 4329 4330 /* Sanity check natural alignments */ 4331 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4332 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4333 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4334 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4335 /* Sanity check bounds */ 4336 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4337 SPAPR_PCI_MEM32_WIN_SIZE); 4338 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4339 SPAPR_PCI_MEM64_WIN_SIZE); 4340 4341 if (index >= SPAPR_MAX_PHBS) { 4342 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4343 SPAPR_MAX_PHBS - 1); 4344 return false; 4345 } 4346 4347 *buid = base_buid + index; 4348 for (i = 0; i < n_dma; ++i) { 4349 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4350 } 4351 4352 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4353 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4354 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4355 4356 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4357 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4358 return true; 4359 } 4360 4361 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4362 { 4363 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4364 4365 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4366 } 4367 4368 static void spapr_ics_resend(XICSFabric *dev) 4369 { 4370 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4371 4372 ics_resend(spapr->ics); 4373 } 4374 4375 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4376 { 4377 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4378 4379 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4380 } 4381 4382 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4383 Monitor *mon) 4384 { 4385 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4386 4387 spapr_irq_print_info(spapr, mon); 4388 monitor_printf(mon, "irqchip: %s\n", 4389 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4390 } 4391 4392 /* 4393 * This is a XIVE only operation 4394 */ 4395 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4396 uint8_t nvt_blk, uint32_t nvt_idx, 4397 bool cam_ignore, uint8_t priority, 4398 uint32_t logic_serv, XiveTCTXMatch *match) 4399 { 4400 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4401 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4402 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4403 int count; 4404 4405 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4406 priority, logic_serv, match); 4407 if (count < 0) { 4408 return count; 4409 } 4410 4411 /* 4412 * When we implement the save and restore of the thread interrupt 4413 * contexts in the enter/exit CPU handlers of the machine and the 4414 * escalations in QEMU, we should be able to handle non dispatched 4415 * vCPUs. 4416 * 4417 * Until this is done, the sPAPR machine should find at least one 4418 * matching context always. 4419 */ 4420 if (count == 0) { 4421 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4422 nvt_blk, nvt_idx); 4423 } 4424 4425 return count; 4426 } 4427 4428 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4429 { 4430 return cpu->vcpu_id; 4431 } 4432 4433 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4434 { 4435 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4436 MachineState *ms = MACHINE(spapr); 4437 int vcpu_id; 4438 4439 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4440 4441 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4442 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4443 error_append_hint(errp, "Adjust the number of cpus to %d " 4444 "or try to raise the number of threads per core\n", 4445 vcpu_id * ms->smp.threads / spapr->vsmt); 4446 return false; 4447 } 4448 4449 cpu->vcpu_id = vcpu_id; 4450 return true; 4451 } 4452 4453 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4454 { 4455 CPUState *cs; 4456 4457 CPU_FOREACH(cs) { 4458 PowerPCCPU *cpu = POWERPC_CPU(cs); 4459 4460 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4461 return cpu; 4462 } 4463 } 4464 4465 return NULL; 4466 } 4467 4468 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4469 { 4470 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4471 4472 /* These are only called by TCG, KVM maintains dispatch state */ 4473 4474 spapr_cpu->prod = false; 4475 if (spapr_cpu->vpa_addr) { 4476 CPUState *cs = CPU(cpu); 4477 uint32_t dispatch; 4478 4479 dispatch = ldl_be_phys(cs->as, 4480 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4481 dispatch++; 4482 if ((dispatch & 1) != 0) { 4483 qemu_log_mask(LOG_GUEST_ERROR, 4484 "VPA: incorrect dispatch counter value for " 4485 "dispatched partition %u, correcting.\n", dispatch); 4486 dispatch++; 4487 } 4488 stl_be_phys(cs->as, 4489 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4490 } 4491 } 4492 4493 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4494 { 4495 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4496 4497 if (spapr_cpu->vpa_addr) { 4498 CPUState *cs = CPU(cpu); 4499 uint32_t dispatch; 4500 4501 dispatch = ldl_be_phys(cs->as, 4502 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4503 dispatch++; 4504 if ((dispatch & 1) != 1) { 4505 qemu_log_mask(LOG_GUEST_ERROR, 4506 "VPA: incorrect dispatch counter value for " 4507 "preempted partition %u, correcting.\n", dispatch); 4508 dispatch++; 4509 } 4510 stl_be_phys(cs->as, 4511 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4512 } 4513 } 4514 4515 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4516 { 4517 MachineClass *mc = MACHINE_CLASS(oc); 4518 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4519 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4520 NMIClass *nc = NMI_CLASS(oc); 4521 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4522 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4523 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4524 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4525 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4526 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc); 4527 4528 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4529 mc->ignore_boot_device_suffixes = true; 4530 4531 /* 4532 * We set up the default / latest behaviour here. The class_init 4533 * functions for the specific versioned machine types can override 4534 * these details for backwards compatibility 4535 */ 4536 mc->init = spapr_machine_init; 4537 mc->reset = spapr_machine_reset; 4538 mc->block_default_type = IF_SCSI; 4539 4540 /* 4541 * Setting max_cpus to INT32_MAX. Both KVM and TCG max_cpus values 4542 * should be limited by the host capability instead of hardcoded. 4543 * max_cpus for KVM guests will be checked in kvm_init(), and TCG 4544 * guests are welcome to have as many CPUs as the host are capable 4545 * of emulate. 4546 */ 4547 mc->max_cpus = INT32_MAX; 4548 4549 mc->no_parallel = 1; 4550 mc->default_boot_order = ""; 4551 mc->default_ram_size = 512 * MiB; 4552 mc->default_ram_id = "ppc_spapr.ram"; 4553 mc->default_display = "std"; 4554 mc->kvm_type = spapr_kvm_type; 4555 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4556 mc->pci_allow_0_address = true; 4557 assert(!mc->get_hotplug_handler); 4558 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4559 hc->pre_plug = spapr_machine_device_pre_plug; 4560 hc->plug = spapr_machine_device_plug; 4561 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4562 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4563 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4564 hc->unplug_request = spapr_machine_device_unplug_request; 4565 hc->unplug = spapr_machine_device_unplug; 4566 4567 smc->dr_lmb_enabled = true; 4568 smc->update_dt_enabled = true; 4569 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4570 mc->has_hotpluggable_cpus = true; 4571 mc->nvdimm_supported = true; 4572 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4573 fwc->get_dev_path = spapr_get_fw_dev_path; 4574 nc->nmi_monitor_handler = spapr_nmi; 4575 smc->phb_placement = spapr_phb_placement; 4576 vhc->hypercall = emulate_spapr_hypercall; 4577 vhc->hpt_mask = spapr_hpt_mask; 4578 vhc->map_hptes = spapr_map_hptes; 4579 vhc->unmap_hptes = spapr_unmap_hptes; 4580 vhc->hpte_set_c = spapr_hpte_set_c; 4581 vhc->hpte_set_r = spapr_hpte_set_r; 4582 vhc->get_pate = spapr_get_pate; 4583 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4584 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4585 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4586 xic->ics_get = spapr_ics_get; 4587 xic->ics_resend = spapr_ics_resend; 4588 xic->icp_get = spapr_icp_get; 4589 ispc->print_info = spapr_pic_print_info; 4590 /* Force NUMA node memory size to be a multiple of 4591 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4592 * in which LMBs are represented and hot-added 4593 */ 4594 mc->numa_mem_align_shift = 28; 4595 mc->auto_enable_numa = true; 4596 4597 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4598 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4599 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4600 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4601 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4602 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4603 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4604 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4605 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4606 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4607 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4608 smc->default_caps.caps[SPAPR_CAP_RPT_INVALIDATE] = SPAPR_CAP_OFF; 4609 spapr_caps_add_properties(smc); 4610 smc->irq = &spapr_irq_dual; 4611 smc->dr_phb_enabled = true; 4612 smc->linux_pci_probe = true; 4613 smc->smp_threads_vsmt = true; 4614 smc->nr_xirqs = SPAPR_NR_XIRQS; 4615 xfc->match_nvt = spapr_match_nvt; 4616 vmc->client_architecture_support = spapr_vof_client_architecture_support; 4617 vmc->quiesce = spapr_vof_quiesce; 4618 vmc->setprop = spapr_vof_setprop; 4619 } 4620 4621 static const TypeInfo spapr_machine_info = { 4622 .name = TYPE_SPAPR_MACHINE, 4623 .parent = TYPE_MACHINE, 4624 .abstract = true, 4625 .instance_size = sizeof(SpaprMachineState), 4626 .instance_init = spapr_instance_init, 4627 .instance_finalize = spapr_machine_finalizefn, 4628 .class_size = sizeof(SpaprMachineClass), 4629 .class_init = spapr_machine_class_init, 4630 .interfaces = (InterfaceInfo[]) { 4631 { TYPE_FW_PATH_PROVIDER }, 4632 { TYPE_NMI }, 4633 { TYPE_HOTPLUG_HANDLER }, 4634 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4635 { TYPE_XICS_FABRIC }, 4636 { TYPE_INTERRUPT_STATS_PROVIDER }, 4637 { TYPE_XIVE_FABRIC }, 4638 { TYPE_VOF_MACHINE_IF }, 4639 { } 4640 }, 4641 }; 4642 4643 static void spapr_machine_latest_class_options(MachineClass *mc) 4644 { 4645 mc->alias = "pseries"; 4646 mc->is_default = true; 4647 } 4648 4649 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4650 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4651 void *data) \ 4652 { \ 4653 MachineClass *mc = MACHINE_CLASS(oc); \ 4654 spapr_machine_##suffix##_class_options(mc); \ 4655 if (latest) { \ 4656 spapr_machine_latest_class_options(mc); \ 4657 } \ 4658 } \ 4659 static const TypeInfo spapr_machine_##suffix##_info = { \ 4660 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4661 .parent = TYPE_SPAPR_MACHINE, \ 4662 .class_init = spapr_machine_##suffix##_class_init, \ 4663 }; \ 4664 static void spapr_machine_register_##suffix(void) \ 4665 { \ 4666 type_register(&spapr_machine_##suffix##_info); \ 4667 } \ 4668 type_init(spapr_machine_register_##suffix) 4669 4670 /* 4671 * pseries-7.0 4672 */ 4673 static void spapr_machine_7_0_class_options(MachineClass *mc) 4674 { 4675 /* Defaults for the latest behaviour inherited from the base class */ 4676 } 4677 4678 DEFINE_SPAPR_MACHINE(7_0, "7.0", true); 4679 4680 /* 4681 * pseries-6.2 4682 */ 4683 static void spapr_machine_6_2_class_options(MachineClass *mc) 4684 { 4685 spapr_machine_7_0_class_options(mc); 4686 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 4687 } 4688 4689 DEFINE_SPAPR_MACHINE(6_2, "6.2", false); 4690 4691 /* 4692 * pseries-6.1 4693 */ 4694 static void spapr_machine_6_1_class_options(MachineClass *mc) 4695 { 4696 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4697 4698 spapr_machine_6_2_class_options(mc); 4699 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 4700 smc->pre_6_2_numa_affinity = true; 4701 mc->smp_props.prefer_sockets = true; 4702 } 4703 4704 DEFINE_SPAPR_MACHINE(6_1, "6.1", false); 4705 4706 /* 4707 * pseries-6.0 4708 */ 4709 static void spapr_machine_6_0_class_options(MachineClass *mc) 4710 { 4711 spapr_machine_6_1_class_options(mc); 4712 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 4713 } 4714 4715 DEFINE_SPAPR_MACHINE(6_0, "6.0", false); 4716 4717 /* 4718 * pseries-5.2 4719 */ 4720 static void spapr_machine_5_2_class_options(MachineClass *mc) 4721 { 4722 spapr_machine_6_0_class_options(mc); 4723 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 4724 } 4725 4726 DEFINE_SPAPR_MACHINE(5_2, "5.2", false); 4727 4728 /* 4729 * pseries-5.1 4730 */ 4731 static void spapr_machine_5_1_class_options(MachineClass *mc) 4732 { 4733 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4734 4735 spapr_machine_5_2_class_options(mc); 4736 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4737 smc->pre_5_2_numa_associativity = true; 4738 } 4739 4740 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4741 4742 /* 4743 * pseries-5.0 4744 */ 4745 static void spapr_machine_5_0_class_options(MachineClass *mc) 4746 { 4747 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4748 static GlobalProperty compat[] = { 4749 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4750 }; 4751 4752 spapr_machine_5_1_class_options(mc); 4753 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4754 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4755 mc->numa_mem_supported = true; 4756 smc->pre_5_1_assoc_refpoints = true; 4757 } 4758 4759 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4760 4761 /* 4762 * pseries-4.2 4763 */ 4764 static void spapr_machine_4_2_class_options(MachineClass *mc) 4765 { 4766 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4767 4768 spapr_machine_5_0_class_options(mc); 4769 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4770 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4771 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4772 smc->rma_limit = 16 * GiB; 4773 mc->nvdimm_supported = false; 4774 } 4775 4776 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4777 4778 /* 4779 * pseries-4.1 4780 */ 4781 static void spapr_machine_4_1_class_options(MachineClass *mc) 4782 { 4783 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4784 static GlobalProperty compat[] = { 4785 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4786 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4787 }; 4788 4789 spapr_machine_4_2_class_options(mc); 4790 smc->linux_pci_probe = false; 4791 smc->smp_threads_vsmt = false; 4792 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4793 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4794 } 4795 4796 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4797 4798 /* 4799 * pseries-4.0 4800 */ 4801 static bool phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4802 uint64_t *buid, hwaddr *pio, 4803 hwaddr *mmio32, hwaddr *mmio64, 4804 unsigned n_dma, uint32_t *liobns, 4805 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4806 { 4807 if (!spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, 4808 liobns, nv2gpa, nv2atsd, errp)) { 4809 return false; 4810 } 4811 4812 *nv2gpa = 0; 4813 *nv2atsd = 0; 4814 return true; 4815 } 4816 static void spapr_machine_4_0_class_options(MachineClass *mc) 4817 { 4818 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4819 4820 spapr_machine_4_1_class_options(mc); 4821 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4822 smc->phb_placement = phb_placement_4_0; 4823 smc->irq = &spapr_irq_xics; 4824 smc->pre_4_1_migration = true; 4825 } 4826 4827 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4828 4829 /* 4830 * pseries-3.1 4831 */ 4832 static void spapr_machine_3_1_class_options(MachineClass *mc) 4833 { 4834 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4835 4836 spapr_machine_4_0_class_options(mc); 4837 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4838 4839 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4840 smc->update_dt_enabled = false; 4841 smc->dr_phb_enabled = false; 4842 smc->broken_host_serial_model = true; 4843 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4844 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4845 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4846 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4847 } 4848 4849 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4850 4851 /* 4852 * pseries-3.0 4853 */ 4854 4855 static void spapr_machine_3_0_class_options(MachineClass *mc) 4856 { 4857 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4858 4859 spapr_machine_3_1_class_options(mc); 4860 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4861 4862 smc->legacy_irq_allocation = true; 4863 smc->nr_xirqs = 0x400; 4864 smc->irq = &spapr_irq_xics_legacy; 4865 } 4866 4867 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4868 4869 /* 4870 * pseries-2.12 4871 */ 4872 static void spapr_machine_2_12_class_options(MachineClass *mc) 4873 { 4874 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4875 static GlobalProperty compat[] = { 4876 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4877 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4878 }; 4879 4880 spapr_machine_3_0_class_options(mc); 4881 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4882 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4883 4884 /* We depend on kvm_enabled() to choose a default value for the 4885 * hpt-max-page-size capability. Of course we can't do it here 4886 * because this is too early and the HW accelerator isn't initialzed 4887 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4888 */ 4889 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4890 } 4891 4892 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4893 4894 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4895 { 4896 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4897 4898 spapr_machine_2_12_class_options(mc); 4899 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4900 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4901 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4902 } 4903 4904 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4905 4906 /* 4907 * pseries-2.11 4908 */ 4909 4910 static void spapr_machine_2_11_class_options(MachineClass *mc) 4911 { 4912 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4913 4914 spapr_machine_2_12_class_options(mc); 4915 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4916 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4917 } 4918 4919 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4920 4921 /* 4922 * pseries-2.10 4923 */ 4924 4925 static void spapr_machine_2_10_class_options(MachineClass *mc) 4926 { 4927 spapr_machine_2_11_class_options(mc); 4928 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4929 } 4930 4931 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4932 4933 /* 4934 * pseries-2.9 4935 */ 4936 4937 static void spapr_machine_2_9_class_options(MachineClass *mc) 4938 { 4939 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4940 static GlobalProperty compat[] = { 4941 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4942 }; 4943 4944 spapr_machine_2_10_class_options(mc); 4945 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4946 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4947 smc->pre_2_10_has_unused_icps = true; 4948 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4949 } 4950 4951 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4952 4953 /* 4954 * pseries-2.8 4955 */ 4956 4957 static void spapr_machine_2_8_class_options(MachineClass *mc) 4958 { 4959 static GlobalProperty compat[] = { 4960 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4961 }; 4962 4963 spapr_machine_2_9_class_options(mc); 4964 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4965 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4966 mc->numa_mem_align_shift = 23; 4967 } 4968 4969 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4970 4971 /* 4972 * pseries-2.7 4973 */ 4974 4975 static bool phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4976 uint64_t *buid, hwaddr *pio, 4977 hwaddr *mmio32, hwaddr *mmio64, 4978 unsigned n_dma, uint32_t *liobns, 4979 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4980 { 4981 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4982 const uint64_t base_buid = 0x800000020000000ULL; 4983 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4984 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4985 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4986 const uint32_t max_index = 255; 4987 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4988 4989 uint64_t ram_top = MACHINE(spapr)->ram_size; 4990 hwaddr phb0_base, phb_base; 4991 int i; 4992 4993 /* Do we have device memory? */ 4994 if (MACHINE(spapr)->maxram_size > ram_top) { 4995 /* Can't just use maxram_size, because there may be an 4996 * alignment gap between normal and device memory regions 4997 */ 4998 ram_top = MACHINE(spapr)->device_memory->base + 4999 memory_region_size(&MACHINE(spapr)->device_memory->mr); 5000 } 5001 5002 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 5003 5004 if (index > max_index) { 5005 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 5006 max_index); 5007 return false; 5008 } 5009 5010 *buid = base_buid + index; 5011 for (i = 0; i < n_dma; ++i) { 5012 liobns[i] = SPAPR_PCI_LIOBN(index, i); 5013 } 5014 5015 phb_base = phb0_base + index * phb_spacing; 5016 *pio = phb_base + pio_offset; 5017 *mmio32 = phb_base + mmio_offset; 5018 /* 5019 * We don't set the 64-bit MMIO window, relying on the PHB's 5020 * fallback behaviour of automatically splitting a large "32-bit" 5021 * window into contiguous 32-bit and 64-bit windows 5022 */ 5023 5024 *nv2gpa = 0; 5025 *nv2atsd = 0; 5026 return true; 5027 } 5028 5029 static void spapr_machine_2_7_class_options(MachineClass *mc) 5030 { 5031 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5032 static GlobalProperty compat[] = { 5033 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 5034 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 5035 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 5036 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 5037 }; 5038 5039 spapr_machine_2_8_class_options(mc); 5040 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 5041 mc->default_machine_opts = "modern-hotplug-events=off"; 5042 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 5043 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5044 smc->phb_placement = phb_placement_2_7; 5045 } 5046 5047 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 5048 5049 /* 5050 * pseries-2.6 5051 */ 5052 5053 static void spapr_machine_2_6_class_options(MachineClass *mc) 5054 { 5055 static GlobalProperty compat[] = { 5056 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 5057 }; 5058 5059 spapr_machine_2_7_class_options(mc); 5060 mc->has_hotpluggable_cpus = false; 5061 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 5062 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5063 } 5064 5065 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 5066 5067 /* 5068 * pseries-2.5 5069 */ 5070 5071 static void spapr_machine_2_5_class_options(MachineClass *mc) 5072 { 5073 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5074 static GlobalProperty compat[] = { 5075 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 5076 }; 5077 5078 spapr_machine_2_6_class_options(mc); 5079 smc->use_ohci_by_default = true; 5080 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 5081 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5082 } 5083 5084 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 5085 5086 /* 5087 * pseries-2.4 5088 */ 5089 5090 static void spapr_machine_2_4_class_options(MachineClass *mc) 5091 { 5092 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5093 5094 spapr_machine_2_5_class_options(mc); 5095 smc->dr_lmb_enabled = false; 5096 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 5097 } 5098 5099 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 5100 5101 /* 5102 * pseries-2.3 5103 */ 5104 5105 static void spapr_machine_2_3_class_options(MachineClass *mc) 5106 { 5107 static GlobalProperty compat[] = { 5108 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 5109 }; 5110 spapr_machine_2_4_class_options(mc); 5111 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 5112 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5113 } 5114 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 5115 5116 /* 5117 * pseries-2.2 5118 */ 5119 5120 static void spapr_machine_2_2_class_options(MachineClass *mc) 5121 { 5122 static GlobalProperty compat[] = { 5123 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 5124 }; 5125 5126 spapr_machine_2_3_class_options(mc); 5127 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 5128 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5129 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 5130 } 5131 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 5132 5133 /* 5134 * pseries-2.1 5135 */ 5136 5137 static void spapr_machine_2_1_class_options(MachineClass *mc) 5138 { 5139 spapr_machine_2_2_class_options(mc); 5140 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 5141 } 5142 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 5143 5144 static void spapr_machine_register_types(void) 5145 { 5146 type_register_static(&spapr_machine_info); 5147 } 5148 5149 type_init(spapr_machine_register_types) 5150