1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "sysemu/sysemu.h" 28 #include "hw/hw.h" 29 #include "hw/fw-path-provider.h" 30 #include "elf.h" 31 #include "net/net.h" 32 #include "sysemu/blockdev.h" 33 #include "sysemu/cpus.h" 34 #include "sysemu/kvm.h" 35 #include "kvm_ppc.h" 36 #include "mmu-hash64.h" 37 #include "qom/cpu.h" 38 39 #include "hw/boards.h" 40 #include "hw/ppc/ppc.h" 41 #include "hw/loader.h" 42 43 #include "hw/ppc/spapr.h" 44 #include "hw/ppc/spapr_vio.h" 45 #include "hw/pci-host/spapr.h" 46 #include "hw/ppc/xics.h" 47 #include "hw/pci/msi.h" 48 49 #include "hw/pci/pci.h" 50 #include "hw/scsi/scsi.h" 51 #include "hw/virtio/virtio-scsi.h" 52 53 #include "exec/address-spaces.h" 54 #include "hw/usb.h" 55 #include "qemu/config-file.h" 56 #include "qemu/error-report.h" 57 #include "trace.h" 58 59 #include <libfdt.h> 60 61 /* SLOF memory layout: 62 * 63 * SLOF raw image loaded at 0, copies its romfs right below the flat 64 * device-tree, then position SLOF itself 31M below that 65 * 66 * So we set FW_OVERHEAD to 40MB which should account for all of that 67 * and more 68 * 69 * We load our kernel at 4M, leaving space for SLOF initial image 70 */ 71 #define FDT_MAX_SIZE 0x40000 72 #define RTAS_MAX_SIZE 0x10000 73 #define FW_MAX_SIZE 0x400000 74 #define FW_FILE_NAME "slof.bin" 75 #define FW_OVERHEAD 0x2800000 76 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 77 78 #define MIN_RMA_SLOF 128UL 79 80 #define TIMEBASE_FREQ 512000000ULL 81 82 #define MAX_CPUS 256 83 84 #define PHANDLE_XICP 0x00001111 85 86 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 87 88 typedef struct sPAPRMachineState sPAPRMachineState; 89 90 #define TYPE_SPAPR_MACHINE "spapr-machine" 91 #define SPAPR_MACHINE(obj) \ 92 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) 93 94 /** 95 * sPAPRMachineState: 96 */ 97 struct sPAPRMachineState { 98 /*< private >*/ 99 MachineState parent_obj; 100 101 /*< public >*/ 102 char *kvm_type; 103 }; 104 105 sPAPREnvironment *spapr; 106 107 static XICSState *try_create_xics(const char *type, int nr_servers, 108 int nr_irqs) 109 { 110 DeviceState *dev; 111 112 dev = qdev_create(NULL, type); 113 qdev_prop_set_uint32(dev, "nr_servers", nr_servers); 114 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); 115 if (qdev_init(dev) < 0) { 116 return NULL; 117 } 118 119 return XICS_COMMON(dev); 120 } 121 122 static XICSState *xics_system_init(int nr_servers, int nr_irqs) 123 { 124 XICSState *icp = NULL; 125 126 if (kvm_enabled()) { 127 QemuOpts *machine_opts = qemu_get_machine_opts(); 128 bool irqchip_allowed = qemu_opt_get_bool(machine_opts, 129 "kernel_irqchip", true); 130 bool irqchip_required = qemu_opt_get_bool(machine_opts, 131 "kernel_irqchip", false); 132 if (irqchip_allowed) { 133 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs); 134 } 135 136 if (irqchip_required && !icp) { 137 perror("Failed to create in-kernel XICS\n"); 138 abort(); 139 } 140 } 141 142 if (!icp) { 143 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs); 144 } 145 146 if (!icp) { 147 perror("Failed to create XICS\n"); 148 abort(); 149 } 150 151 return icp; 152 } 153 154 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 155 int smt_threads) 156 { 157 int i, ret = 0; 158 uint32_t servers_prop[smt_threads]; 159 uint32_t gservers_prop[smt_threads * 2]; 160 int index = ppc_get_vcpu_dt_id(cpu); 161 162 if (cpu->cpu_version) { 163 ret = fdt_setprop(fdt, offset, "cpu-version", 164 &cpu->cpu_version, sizeof(cpu->cpu_version)); 165 if (ret < 0) { 166 return ret; 167 } 168 } 169 170 /* Build interrupt servers and gservers properties */ 171 for (i = 0; i < smt_threads; i++) { 172 servers_prop[i] = cpu_to_be32(index + i); 173 /* Hack, direct the group queues back to cpu 0 */ 174 gservers_prop[i*2] = cpu_to_be32(index + i); 175 gservers_prop[i*2 + 1] = 0; 176 } 177 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 178 servers_prop, sizeof(servers_prop)); 179 if (ret < 0) { 180 return ret; 181 } 182 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 183 gservers_prop, sizeof(gservers_prop)); 184 185 return ret; 186 } 187 188 static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr) 189 { 190 int ret = 0, offset, cpus_offset; 191 CPUState *cs; 192 char cpu_model[32]; 193 int smt = kvmppc_smt_threads(); 194 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 195 196 CPU_FOREACH(cs) { 197 PowerPCCPU *cpu = POWERPC_CPU(cs); 198 DeviceClass *dc = DEVICE_GET_CLASS(cs); 199 int index = ppc_get_vcpu_dt_id(cpu); 200 uint32_t associativity[] = {cpu_to_be32(0x5), 201 cpu_to_be32(0x0), 202 cpu_to_be32(0x0), 203 cpu_to_be32(0x0), 204 cpu_to_be32(cs->numa_node), 205 cpu_to_be32(index)}; 206 207 if ((index % smt) != 0) { 208 continue; 209 } 210 211 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 212 213 cpus_offset = fdt_path_offset(fdt, "/cpus"); 214 if (cpus_offset < 0) { 215 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 216 "cpus"); 217 if (cpus_offset < 0) { 218 return cpus_offset; 219 } 220 } 221 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 222 if (offset < 0) { 223 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 224 if (offset < 0) { 225 return offset; 226 } 227 } 228 229 if (nb_numa_nodes > 1) { 230 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 231 sizeof(associativity)); 232 if (ret < 0) { 233 return ret; 234 } 235 } 236 237 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 238 pft_size_prop, sizeof(pft_size_prop)); 239 if (ret < 0) { 240 return ret; 241 } 242 243 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 244 ppc_get_compat_smt_threads(cpu)); 245 if (ret < 0) { 246 return ret; 247 } 248 } 249 return ret; 250 } 251 252 253 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, 254 size_t maxsize) 255 { 256 size_t maxcells = maxsize / sizeof(uint32_t); 257 int i, j, count; 258 uint32_t *p = prop; 259 260 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 261 struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; 262 263 if (!sps->page_shift) { 264 break; 265 } 266 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { 267 if (sps->enc[count].page_shift == 0) { 268 break; 269 } 270 } 271 if ((p - prop) >= (maxcells - 3 - count * 2)) { 272 break; 273 } 274 *(p++) = cpu_to_be32(sps->page_shift); 275 *(p++) = cpu_to_be32(sps->slb_enc); 276 *(p++) = cpu_to_be32(count); 277 for (j = 0; j < count; j++) { 278 *(p++) = cpu_to_be32(sps->enc[j].page_shift); 279 *(p++) = cpu_to_be32(sps->enc[j].pte_enc); 280 } 281 } 282 283 return (p - prop) * sizeof(uint32_t); 284 } 285 286 #define _FDT(exp) \ 287 do { \ 288 int ret = (exp); \ 289 if (ret < 0) { \ 290 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ 291 #exp, fdt_strerror(ret)); \ 292 exit(1); \ 293 } \ 294 } while (0) 295 296 static void add_str(GString *s, const gchar *s1) 297 { 298 g_string_append_len(s, s1, strlen(s1) + 1); 299 } 300 301 static void *spapr_create_fdt_skel(hwaddr initrd_base, 302 hwaddr initrd_size, 303 hwaddr kernel_size, 304 bool little_endian, 305 const char *boot_device, 306 const char *kernel_cmdline, 307 uint32_t epow_irq) 308 { 309 void *fdt; 310 CPUState *cs; 311 uint32_t start_prop = cpu_to_be32(initrd_base); 312 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); 313 GString *hypertas = g_string_sized_new(256); 314 GString *qemu_hypertas = g_string_sized_new(256); 315 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; 316 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)}; 317 int smt = kvmppc_smt_threads(); 318 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; 319 QemuOpts *opts = qemu_opts_find(qemu_find_opts("smp-opts"), NULL); 320 unsigned sockets = opts ? qemu_opt_get_number(opts, "sockets", 0) : 0; 321 uint32_t cpus_per_socket = sockets ? (smp_cpus / sockets) : 1; 322 323 add_str(hypertas, "hcall-pft"); 324 add_str(hypertas, "hcall-term"); 325 add_str(hypertas, "hcall-dabr"); 326 add_str(hypertas, "hcall-interrupt"); 327 add_str(hypertas, "hcall-tce"); 328 add_str(hypertas, "hcall-vio"); 329 add_str(hypertas, "hcall-splpar"); 330 add_str(hypertas, "hcall-bulk"); 331 add_str(hypertas, "hcall-set-mode"); 332 add_str(qemu_hypertas, "hcall-memop1"); 333 334 fdt = g_malloc0(FDT_MAX_SIZE); 335 _FDT((fdt_create(fdt, FDT_MAX_SIZE))); 336 337 if (kernel_size) { 338 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); 339 } 340 if (initrd_size) { 341 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); 342 } 343 _FDT((fdt_finish_reservemap(fdt))); 344 345 /* Root node */ 346 _FDT((fdt_begin_node(fdt, ""))); 347 _FDT((fdt_property_string(fdt, "device_type", "chrp"))); 348 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); 349 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); 350 351 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); 352 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); 353 354 /* /chosen */ 355 _FDT((fdt_begin_node(fdt, "chosen"))); 356 357 /* Set Form1_affinity */ 358 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); 359 360 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); 361 _FDT((fdt_property(fdt, "linux,initrd-start", 362 &start_prop, sizeof(start_prop)))); 363 _FDT((fdt_property(fdt, "linux,initrd-end", 364 &end_prop, sizeof(end_prop)))); 365 if (kernel_size) { 366 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 367 cpu_to_be64(kernel_size) }; 368 369 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); 370 if (little_endian) { 371 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); 372 } 373 } 374 if (boot_device) { 375 _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device))); 376 } 377 if (boot_menu) { 378 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu))); 379 } 380 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); 381 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); 382 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); 383 384 _FDT((fdt_end_node(fdt))); 385 386 /* cpus */ 387 _FDT((fdt_begin_node(fdt, "cpus"))); 388 389 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 390 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 391 392 CPU_FOREACH(cs) { 393 PowerPCCPU *cpu = POWERPC_CPU(cs); 394 CPUPPCState *env = &cpu->env; 395 DeviceClass *dc = DEVICE_GET_CLASS(cs); 396 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 397 int index = ppc_get_vcpu_dt_id(cpu); 398 char *nodename; 399 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 400 0xffffffff, 0xffffffff}; 401 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; 402 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 403 uint32_t page_sizes_prop[64]; 404 size_t page_sizes_prop_size; 405 406 if ((index % smt) != 0) { 407 continue; 408 } 409 410 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 411 412 _FDT((fdt_begin_node(fdt, nodename))); 413 414 g_free(nodename); 415 416 _FDT((fdt_property_cell(fdt, "reg", index))); 417 _FDT((fdt_property_string(fdt, "device_type", "cpu"))); 418 419 _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR]))); 420 _FDT((fdt_property_cell(fdt, "d-cache-block-size", 421 env->dcache_line_size))); 422 _FDT((fdt_property_cell(fdt, "d-cache-line-size", 423 env->dcache_line_size))); 424 _FDT((fdt_property_cell(fdt, "i-cache-block-size", 425 env->icache_line_size))); 426 _FDT((fdt_property_cell(fdt, "i-cache-line-size", 427 env->icache_line_size))); 428 429 if (pcc->l1_dcache_size) { 430 _FDT((fdt_property_cell(fdt, "d-cache-size", pcc->l1_dcache_size))); 431 } else { 432 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); 433 } 434 if (pcc->l1_icache_size) { 435 _FDT((fdt_property_cell(fdt, "i-cache-size", pcc->l1_icache_size))); 436 } else { 437 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); 438 } 439 440 _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq))); 441 _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq))); 442 _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr))); 443 _FDT((fdt_property_string(fdt, "status", "okay"))); 444 _FDT((fdt_property(fdt, "64-bit", NULL, 0))); 445 446 if (env->spr_cb[SPR_PURR].oea_read) { 447 _FDT((fdt_property(fdt, "ibm,purr", NULL, 0))); 448 } 449 450 if (env->mmu_model & POWERPC_MMU_1TSEG) { 451 _FDT((fdt_property(fdt, "ibm,processor-segment-sizes", 452 segs, sizeof(segs)))); 453 } 454 455 /* Advertise VMX/VSX (vector extensions) if available 456 * 0 / no property == no vector extensions 457 * 1 == VMX / Altivec available 458 * 2 == VSX available */ 459 if (env->insns_flags & PPC_ALTIVEC) { 460 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 461 462 _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx))); 463 } 464 465 /* Advertise DFP (Decimal Floating Point) if available 466 * 0 / no property == no DFP 467 * 1 == DFP available */ 468 if (env->insns_flags2 & PPC2_DFP) { 469 _FDT((fdt_property_cell(fdt, "ibm,dfp", 1))); 470 } 471 472 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, 473 sizeof(page_sizes_prop)); 474 if (page_sizes_prop_size) { 475 _FDT((fdt_property(fdt, "ibm,segment-page-sizes", 476 page_sizes_prop, page_sizes_prop_size))); 477 } 478 479 _FDT((fdt_property_cell(fdt, "ibm,chip-id", 480 cs->cpu_index / cpus_per_socket))); 481 482 _FDT((fdt_end_node(fdt))); 483 } 484 485 _FDT((fdt_end_node(fdt))); 486 487 /* RTAS */ 488 _FDT((fdt_begin_node(fdt, "rtas"))); 489 490 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 491 add_str(hypertas, "hcall-multi-tce"); 492 } 493 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str, 494 hypertas->len))); 495 g_string_free(hypertas, TRUE); 496 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str, 497 qemu_hypertas->len))); 498 g_string_free(qemu_hypertas, TRUE); 499 500 _FDT((fdt_property(fdt, "ibm,associativity-reference-points", 501 refpoints, sizeof(refpoints)))); 502 503 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); 504 505 _FDT((fdt_end_node(fdt))); 506 507 /* interrupt controller */ 508 _FDT((fdt_begin_node(fdt, "interrupt-controller"))); 509 510 _FDT((fdt_property_string(fdt, "device_type", 511 "PowerPC-External-Interrupt-Presentation"))); 512 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); 513 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 514 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", 515 interrupt_server_ranges_prop, 516 sizeof(interrupt_server_ranges_prop)))); 517 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); 518 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); 519 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); 520 521 _FDT((fdt_end_node(fdt))); 522 523 /* vdevice */ 524 _FDT((fdt_begin_node(fdt, "vdevice"))); 525 526 _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); 527 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); 528 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 529 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 530 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); 531 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 532 533 _FDT((fdt_end_node(fdt))); 534 535 /* event-sources */ 536 spapr_events_fdt_skel(fdt, epow_irq); 537 538 /* /hypervisor node */ 539 if (kvm_enabled()) { 540 uint8_t hypercall[16]; 541 542 /* indicate KVM hypercall interface */ 543 _FDT((fdt_begin_node(fdt, "hypervisor"))); 544 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm"))); 545 if (kvmppc_has_cap_fixup_hcalls()) { 546 /* 547 * Older KVM versions with older guest kernels were broken with the 548 * magic page, don't allow the guest to map it. 549 */ 550 kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 551 sizeof(hypercall)); 552 _FDT((fdt_property(fdt, "hcall-instructions", hypercall, 553 sizeof(hypercall)))); 554 } 555 _FDT((fdt_end_node(fdt))); 556 } 557 558 _FDT((fdt_end_node(fdt))); /* close root node */ 559 _FDT((fdt_finish(fdt))); 560 561 return fdt; 562 } 563 564 int spapr_h_cas_compose_response(target_ulong addr, target_ulong size) 565 { 566 void *fdt, *fdt_skel; 567 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 568 569 size -= sizeof(hdr); 570 571 /* Create sceleton */ 572 fdt_skel = g_malloc0(size); 573 _FDT((fdt_create(fdt_skel, size))); 574 _FDT((fdt_begin_node(fdt_skel, ""))); 575 _FDT((fdt_end_node(fdt_skel))); 576 _FDT((fdt_finish(fdt_skel))); 577 fdt = g_malloc0(size); 578 _FDT((fdt_open_into(fdt_skel, fdt, size))); 579 g_free(fdt_skel); 580 581 /* Fix skeleton up */ 582 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 583 584 /* Pack resulting tree */ 585 _FDT((fdt_pack(fdt))); 586 587 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 588 trace_spapr_cas_failed(size); 589 return -1; 590 } 591 592 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 593 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 594 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 595 g_free(fdt); 596 597 return 0; 598 } 599 600 static int spapr_populate_memory(sPAPREnvironment *spapr, void *fdt) 601 { 602 uint32_t associativity[] = {cpu_to_be32(0x4), cpu_to_be32(0x0), 603 cpu_to_be32(0x0), cpu_to_be32(0x0), 604 cpu_to_be32(0x0)}; 605 char mem_name[32]; 606 hwaddr node0_size, mem_start, node_size; 607 uint64_t mem_reg_property[2]; 608 int i, off; 609 610 /* memory node(s) */ 611 if (nb_numa_nodes > 1 && numa_info[0].node_mem < ram_size) { 612 node0_size = numa_info[0].node_mem; 613 } else { 614 node0_size = ram_size; 615 } 616 617 /* RMA */ 618 mem_reg_property[0] = 0; 619 mem_reg_property[1] = cpu_to_be64(spapr->rma_size); 620 off = fdt_add_subnode(fdt, 0, "memory@0"); 621 _FDT(off); 622 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 623 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 624 sizeof(mem_reg_property)))); 625 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 626 sizeof(associativity)))); 627 628 /* RAM: Node 0 */ 629 if (node0_size > spapr->rma_size) { 630 mem_reg_property[0] = cpu_to_be64(spapr->rma_size); 631 mem_reg_property[1] = cpu_to_be64(node0_size - spapr->rma_size); 632 633 sprintf(mem_name, "memory@" TARGET_FMT_lx, spapr->rma_size); 634 off = fdt_add_subnode(fdt, 0, mem_name); 635 _FDT(off); 636 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 637 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 638 sizeof(mem_reg_property)))); 639 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 640 sizeof(associativity)))); 641 } 642 643 /* RAM: Node 1 and beyond */ 644 mem_start = node0_size; 645 for (i = 1; i < nb_numa_nodes; i++) { 646 mem_reg_property[0] = cpu_to_be64(mem_start); 647 if (mem_start >= ram_size) { 648 node_size = 0; 649 } else { 650 node_size = numa_info[i].node_mem; 651 if (node_size > ram_size - mem_start) { 652 node_size = ram_size - mem_start; 653 } 654 } 655 mem_reg_property[1] = cpu_to_be64(node_size); 656 associativity[3] = associativity[4] = cpu_to_be32(i); 657 sprintf(mem_name, "memory@" TARGET_FMT_lx, mem_start); 658 off = fdt_add_subnode(fdt, 0, mem_name); 659 _FDT(off); 660 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 661 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 662 sizeof(mem_reg_property)))); 663 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 664 sizeof(associativity)))); 665 mem_start += node_size; 666 } 667 668 return 0; 669 } 670 671 static void spapr_finalize_fdt(sPAPREnvironment *spapr, 672 hwaddr fdt_addr, 673 hwaddr rtas_addr, 674 hwaddr rtas_size) 675 { 676 int ret, i; 677 size_t cb = 0; 678 char *bootlist; 679 void *fdt; 680 sPAPRPHBState *phb; 681 682 fdt = g_malloc(FDT_MAX_SIZE); 683 684 /* open out the base tree into a temp buffer for the final tweaks */ 685 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); 686 687 ret = spapr_populate_memory(spapr, fdt); 688 if (ret < 0) { 689 fprintf(stderr, "couldn't setup memory nodes in fdt\n"); 690 exit(1); 691 } 692 693 ret = spapr_populate_vdevice(spapr->vio_bus, fdt); 694 if (ret < 0) { 695 fprintf(stderr, "couldn't setup vio devices in fdt\n"); 696 exit(1); 697 } 698 699 QLIST_FOREACH(phb, &spapr->phbs, list) { 700 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 701 } 702 703 if (ret < 0) { 704 fprintf(stderr, "couldn't setup PCI devices in fdt\n"); 705 exit(1); 706 } 707 708 /* RTAS */ 709 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); 710 if (ret < 0) { 711 fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); 712 } 713 714 /* Advertise NUMA via ibm,associativity */ 715 ret = spapr_fixup_cpu_dt(fdt, spapr); 716 if (ret < 0) { 717 fprintf(stderr, "Couldn't finalize CPU device tree properties\n"); 718 } 719 720 bootlist = get_boot_devices_list(&cb, true); 721 if (cb && bootlist) { 722 int offset = fdt_path_offset(fdt, "/chosen"); 723 if (offset < 0) { 724 exit(1); 725 } 726 for (i = 0; i < cb; i++) { 727 if (bootlist[i] == '\n') { 728 bootlist[i] = ' '; 729 } 730 731 } 732 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist); 733 } 734 735 if (!spapr->has_graphics) { 736 spapr_populate_chosen_stdout(fdt, spapr->vio_bus); 737 } 738 739 _FDT((fdt_pack(fdt))); 740 741 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 742 hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n", 743 fdt_totalsize(fdt), FDT_MAX_SIZE); 744 exit(1); 745 } 746 747 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 748 749 g_free(fdt); 750 } 751 752 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 753 { 754 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 755 } 756 757 static void emulate_spapr_hypercall(PowerPCCPU *cpu) 758 { 759 CPUPPCState *env = &cpu->env; 760 761 if (msr_pr) { 762 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 763 env->gpr[3] = H_PRIVILEGE; 764 } else { 765 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 766 } 767 } 768 769 static void spapr_reset_htab(sPAPREnvironment *spapr) 770 { 771 long shift; 772 773 /* allocate hash page table. For now we always make this 16mb, 774 * later we should probably make it scale to the size of guest 775 * RAM */ 776 777 shift = kvmppc_reset_htab(spapr->htab_shift); 778 779 if (shift > 0) { 780 /* Kernel handles htab, we don't need to allocate one */ 781 spapr->htab_shift = shift; 782 kvmppc_kern_htab = true; 783 } else { 784 if (!spapr->htab) { 785 /* Allocate an htab if we don't yet have one */ 786 spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); 787 } 788 789 /* And clear it */ 790 memset(spapr->htab, 0, HTAB_SIZE(spapr)); 791 } 792 793 /* Update the RMA size if necessary */ 794 if (spapr->vrma_adjust) { 795 hwaddr node0_size = (nb_numa_nodes > 1) ? 796 numa_info[0].node_mem : ram_size; 797 spapr->rma_size = kvmppc_rma_size(node0_size, spapr->htab_shift); 798 } 799 } 800 801 static void ppc_spapr_reset(void) 802 { 803 PowerPCCPU *first_ppc_cpu; 804 805 /* Reset the hash table & recalc the RMA */ 806 spapr_reset_htab(spapr); 807 808 qemu_devices_reset(); 809 810 /* Load the fdt */ 811 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, 812 spapr->rtas_size); 813 814 /* Set up the entry state */ 815 first_ppc_cpu = POWERPC_CPU(first_cpu); 816 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; 817 first_ppc_cpu->env.gpr[5] = 0; 818 first_cpu->halted = 0; 819 first_ppc_cpu->env.nip = spapr->entry_point; 820 821 } 822 823 static void spapr_cpu_reset(void *opaque) 824 { 825 PowerPCCPU *cpu = opaque; 826 CPUState *cs = CPU(cpu); 827 CPUPPCState *env = &cpu->env; 828 829 cpu_reset(cs); 830 831 /* All CPUs start halted. CPU0 is unhalted from the machine level 832 * reset code and the rest are explicitly started up by the guest 833 * using an RTAS call */ 834 cs->halted = 1; 835 836 env->spr[SPR_HIOR] = 0; 837 838 env->external_htab = (uint8_t *)spapr->htab; 839 if (kvm_enabled() && !env->external_htab) { 840 /* 841 * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte* 842 * functions do the right thing. 843 */ 844 env->external_htab = (void *)1; 845 } 846 env->htab_base = -1; 847 /* 848 * htab_mask is the mask used to normalize hash value to PTEG index. 849 * htab_shift is log2 of hash table size. 850 * We have 8 hpte per group, and each hpte is 16 bytes. 851 * ie have 128 bytes per hpte entry. 852 */ 853 env->htab_mask = (1ULL << ((spapr)->htab_shift - 7)) - 1; 854 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | 855 (spapr->htab_shift - 18); 856 } 857 858 static void spapr_create_nvram(sPAPREnvironment *spapr) 859 { 860 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 861 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 862 863 if (dinfo) { 864 qdev_prop_set_drive_nofail(dev, "drive", dinfo->bdrv); 865 } 866 867 qdev_init_nofail(dev); 868 869 spapr->nvram = (struct sPAPRNVRAM *)dev; 870 } 871 872 /* Returns whether we want to use VGA or not */ 873 static int spapr_vga_init(PCIBus *pci_bus) 874 { 875 switch (vga_interface_type) { 876 case VGA_NONE: 877 return false; 878 case VGA_DEVICE: 879 return true; 880 case VGA_STD: 881 return pci_vga_init(pci_bus) != NULL; 882 default: 883 fprintf(stderr, "This vga model is not supported," 884 "currently it only supports -vga std\n"); 885 exit(0); 886 } 887 } 888 889 static const VMStateDescription vmstate_spapr = { 890 .name = "spapr", 891 .version_id = 2, 892 .minimum_version_id = 1, 893 .fields = (VMStateField[]) { 894 VMSTATE_UNUSED(4), /* used to be @next_irq */ 895 896 /* RTC offset */ 897 VMSTATE_UINT64(rtc_offset, sPAPREnvironment), 898 VMSTATE_PPC_TIMEBASE_V(tb, sPAPREnvironment, 2), 899 VMSTATE_END_OF_LIST() 900 }, 901 }; 902 903 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 904 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 905 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 906 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 907 908 static int htab_save_setup(QEMUFile *f, void *opaque) 909 { 910 sPAPREnvironment *spapr = opaque; 911 912 /* "Iteration" header */ 913 qemu_put_be32(f, spapr->htab_shift); 914 915 if (spapr->htab) { 916 spapr->htab_save_index = 0; 917 spapr->htab_first_pass = true; 918 } else { 919 assert(kvm_enabled()); 920 921 spapr->htab_fd = kvmppc_get_htab_fd(false); 922 if (spapr->htab_fd < 0) { 923 fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n", 924 strerror(errno)); 925 return -1; 926 } 927 } 928 929 930 return 0; 931 } 932 933 static void htab_save_first_pass(QEMUFile *f, sPAPREnvironment *spapr, 934 int64_t max_ns) 935 { 936 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 937 int index = spapr->htab_save_index; 938 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 939 940 assert(spapr->htab_first_pass); 941 942 do { 943 int chunkstart; 944 945 /* Consume invalid HPTEs */ 946 while ((index < htabslots) 947 && !HPTE_VALID(HPTE(spapr->htab, index))) { 948 index++; 949 CLEAN_HPTE(HPTE(spapr->htab, index)); 950 } 951 952 /* Consume valid HPTEs */ 953 chunkstart = index; 954 while ((index < htabslots) 955 && HPTE_VALID(HPTE(spapr->htab, index))) { 956 index++; 957 CLEAN_HPTE(HPTE(spapr->htab, index)); 958 } 959 960 if (index > chunkstart) { 961 int n_valid = index - chunkstart; 962 963 qemu_put_be32(f, chunkstart); 964 qemu_put_be16(f, n_valid); 965 qemu_put_be16(f, 0); 966 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 967 HASH_PTE_SIZE_64 * n_valid); 968 969 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 970 break; 971 } 972 } 973 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 974 975 if (index >= htabslots) { 976 assert(index == htabslots); 977 index = 0; 978 spapr->htab_first_pass = false; 979 } 980 spapr->htab_save_index = index; 981 } 982 983 static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr, 984 int64_t max_ns) 985 { 986 bool final = max_ns < 0; 987 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 988 int examined = 0, sent = 0; 989 int index = spapr->htab_save_index; 990 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 991 992 assert(!spapr->htab_first_pass); 993 994 do { 995 int chunkstart, invalidstart; 996 997 /* Consume non-dirty HPTEs */ 998 while ((index < htabslots) 999 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1000 index++; 1001 examined++; 1002 } 1003 1004 chunkstart = index; 1005 /* Consume valid dirty HPTEs */ 1006 while ((index < htabslots) 1007 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1008 && HPTE_VALID(HPTE(spapr->htab, index))) { 1009 CLEAN_HPTE(HPTE(spapr->htab, index)); 1010 index++; 1011 examined++; 1012 } 1013 1014 invalidstart = index; 1015 /* Consume invalid dirty HPTEs */ 1016 while ((index < htabslots) 1017 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1018 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1019 CLEAN_HPTE(HPTE(spapr->htab, index)); 1020 index++; 1021 examined++; 1022 } 1023 1024 if (index > chunkstart) { 1025 int n_valid = invalidstart - chunkstart; 1026 int n_invalid = index - invalidstart; 1027 1028 qemu_put_be32(f, chunkstart); 1029 qemu_put_be16(f, n_valid); 1030 qemu_put_be16(f, n_invalid); 1031 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1032 HASH_PTE_SIZE_64 * n_valid); 1033 sent += index - chunkstart; 1034 1035 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1036 break; 1037 } 1038 } 1039 1040 if (examined >= htabslots) { 1041 break; 1042 } 1043 1044 if (index >= htabslots) { 1045 assert(index == htabslots); 1046 index = 0; 1047 } 1048 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1049 1050 if (index >= htabslots) { 1051 assert(index == htabslots); 1052 index = 0; 1053 } 1054 1055 spapr->htab_save_index = index; 1056 1057 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1058 } 1059 1060 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1061 #define MAX_KVM_BUF_SIZE 2048 1062 1063 static int htab_save_iterate(QEMUFile *f, void *opaque) 1064 { 1065 sPAPREnvironment *spapr = opaque; 1066 int rc = 0; 1067 1068 /* Iteration header */ 1069 qemu_put_be32(f, 0); 1070 1071 if (!spapr->htab) { 1072 assert(kvm_enabled()); 1073 1074 rc = kvmppc_save_htab(f, spapr->htab_fd, 1075 MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1076 if (rc < 0) { 1077 return rc; 1078 } 1079 } else if (spapr->htab_first_pass) { 1080 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1081 } else { 1082 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1083 } 1084 1085 /* End marker */ 1086 qemu_put_be32(f, 0); 1087 qemu_put_be16(f, 0); 1088 qemu_put_be16(f, 0); 1089 1090 return rc; 1091 } 1092 1093 static int htab_save_complete(QEMUFile *f, void *opaque) 1094 { 1095 sPAPREnvironment *spapr = opaque; 1096 1097 /* Iteration header */ 1098 qemu_put_be32(f, 0); 1099 1100 if (!spapr->htab) { 1101 int rc; 1102 1103 assert(kvm_enabled()); 1104 1105 rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1); 1106 if (rc < 0) { 1107 return rc; 1108 } 1109 close(spapr->htab_fd); 1110 spapr->htab_fd = -1; 1111 } else { 1112 htab_save_later_pass(f, spapr, -1); 1113 } 1114 1115 /* End marker */ 1116 qemu_put_be32(f, 0); 1117 qemu_put_be16(f, 0); 1118 qemu_put_be16(f, 0); 1119 1120 return 0; 1121 } 1122 1123 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1124 { 1125 sPAPREnvironment *spapr = opaque; 1126 uint32_t section_hdr; 1127 int fd = -1; 1128 1129 if (version_id < 1 || version_id > 1) { 1130 fprintf(stderr, "htab_load() bad version\n"); 1131 return -EINVAL; 1132 } 1133 1134 section_hdr = qemu_get_be32(f); 1135 1136 if (section_hdr) { 1137 /* First section, just the hash shift */ 1138 if (spapr->htab_shift != section_hdr) { 1139 return -EINVAL; 1140 } 1141 return 0; 1142 } 1143 1144 if (!spapr->htab) { 1145 assert(kvm_enabled()); 1146 1147 fd = kvmppc_get_htab_fd(true); 1148 if (fd < 0) { 1149 fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n", 1150 strerror(errno)); 1151 } 1152 } 1153 1154 while (true) { 1155 uint32_t index; 1156 uint16_t n_valid, n_invalid; 1157 1158 index = qemu_get_be32(f); 1159 n_valid = qemu_get_be16(f); 1160 n_invalid = qemu_get_be16(f); 1161 1162 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1163 /* End of Stream */ 1164 break; 1165 } 1166 1167 if ((index + n_valid + n_invalid) > 1168 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1169 /* Bad index in stream */ 1170 fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) " 1171 "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid, 1172 spapr->htab_shift); 1173 return -EINVAL; 1174 } 1175 1176 if (spapr->htab) { 1177 if (n_valid) { 1178 qemu_get_buffer(f, HPTE(spapr->htab, index), 1179 HASH_PTE_SIZE_64 * n_valid); 1180 } 1181 if (n_invalid) { 1182 memset(HPTE(spapr->htab, index + n_valid), 0, 1183 HASH_PTE_SIZE_64 * n_invalid); 1184 } 1185 } else { 1186 int rc; 1187 1188 assert(fd >= 0); 1189 1190 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1191 if (rc < 0) { 1192 return rc; 1193 } 1194 } 1195 } 1196 1197 if (!spapr->htab) { 1198 assert(fd >= 0); 1199 close(fd); 1200 } 1201 1202 return 0; 1203 } 1204 1205 static SaveVMHandlers savevm_htab_handlers = { 1206 .save_live_setup = htab_save_setup, 1207 .save_live_iterate = htab_save_iterate, 1208 .save_live_complete = htab_save_complete, 1209 .load_state = htab_load, 1210 }; 1211 1212 /* pSeries LPAR / sPAPR hardware init */ 1213 static void ppc_spapr_init(MachineState *machine) 1214 { 1215 ram_addr_t ram_size = machine->ram_size; 1216 const char *cpu_model = machine->cpu_model; 1217 const char *kernel_filename = machine->kernel_filename; 1218 const char *kernel_cmdline = machine->kernel_cmdline; 1219 const char *initrd_filename = machine->initrd_filename; 1220 const char *boot_device = machine->boot_order; 1221 PowerPCCPU *cpu; 1222 CPUPPCState *env; 1223 PCIHostState *phb; 1224 int i; 1225 MemoryRegion *sysmem = get_system_memory(); 1226 MemoryRegion *ram = g_new(MemoryRegion, 1); 1227 hwaddr rma_alloc_size; 1228 hwaddr node0_size = (nb_numa_nodes > 1) ? numa_info[0].node_mem : ram_size; 1229 uint32_t initrd_base = 0; 1230 long kernel_size = 0, initrd_size = 0; 1231 long load_limit, rtas_limit, fw_size; 1232 bool kernel_le = false; 1233 char *filename; 1234 1235 msi_supported = true; 1236 1237 spapr = g_malloc0(sizeof(*spapr)); 1238 QLIST_INIT(&spapr->phbs); 1239 1240 cpu_ppc_hypercall = emulate_spapr_hypercall; 1241 1242 /* Allocate RMA if necessary */ 1243 rma_alloc_size = kvmppc_alloc_rma("ppc_spapr.rma", sysmem); 1244 1245 if (rma_alloc_size == -1) { 1246 hw_error("qemu: Unable to create RMA\n"); 1247 exit(1); 1248 } 1249 1250 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1251 spapr->rma_size = rma_alloc_size; 1252 } else { 1253 spapr->rma_size = node0_size; 1254 1255 /* With KVM, we don't actually know whether KVM supports an 1256 * unbounded RMA (PR KVM) or is limited by the hash table size 1257 * (HV KVM using VRMA), so we always assume the latter 1258 * 1259 * In that case, we also limit the initial allocations for RTAS 1260 * etc... to 256M since we have no way to know what the VRMA size 1261 * is going to be as it depends on the size of the hash table 1262 * isn't determined yet. 1263 */ 1264 if (kvm_enabled()) { 1265 spapr->vrma_adjust = 1; 1266 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1267 } 1268 } 1269 1270 if (spapr->rma_size > node0_size) { 1271 fprintf(stderr, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")\n", 1272 spapr->rma_size); 1273 exit(1); 1274 } 1275 1276 /* We place the device tree and RTAS just below either the top of the RMA, 1277 * or just below 2GB, whichever is lowere, so that it can be 1278 * processed with 32-bit real mode code if necessary */ 1279 rtas_limit = MIN(spapr->rma_size, 0x80000000); 1280 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1281 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; 1282 load_limit = spapr->fdt_addr - FW_OVERHEAD; 1283 1284 /* We aim for a hash table of size 1/128 the size of RAM. The 1285 * normal rule of thumb is 1/64 the size of RAM, but that's much 1286 * more than needed for the Linux guests we support. */ 1287 spapr->htab_shift = 18; /* Minimum architected size */ 1288 while (spapr->htab_shift <= 46) { 1289 if ((1ULL << (spapr->htab_shift + 7)) >= ram_size) { 1290 break; 1291 } 1292 spapr->htab_shift++; 1293 } 1294 1295 /* Set up Interrupt Controller before we create the VCPUs */ 1296 spapr->icp = xics_system_init(smp_cpus * kvmppc_smt_threads() / smp_threads, 1297 XICS_IRQS); 1298 1299 /* init CPUs */ 1300 if (cpu_model == NULL) { 1301 cpu_model = kvm_enabled() ? "host" : "POWER7"; 1302 } 1303 for (i = 0; i < smp_cpus; i++) { 1304 cpu = cpu_ppc_init(cpu_model); 1305 if (cpu == NULL) { 1306 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 1307 exit(1); 1308 } 1309 env = &cpu->env; 1310 1311 /* Set time-base frequency to 512 MHz */ 1312 cpu_ppc_tb_init(env, TIMEBASE_FREQ); 1313 1314 /* PAPR always has exception vectors in RAM not ROM. To ensure this, 1315 * MSR[IP] should never be set. 1316 */ 1317 env->msr_mask &= ~(1 << 6); 1318 1319 /* Tell KVM that we're in PAPR mode */ 1320 if (kvm_enabled()) { 1321 kvmppc_set_papr(cpu); 1322 } 1323 1324 if (cpu->max_compat) { 1325 if (ppc_set_compat(cpu, cpu->max_compat) < 0) { 1326 exit(1); 1327 } 1328 } 1329 1330 xics_cpu_setup(spapr->icp, cpu); 1331 1332 qemu_register_reset(spapr_cpu_reset, cpu); 1333 } 1334 1335 /* allocate RAM */ 1336 spapr->ram_limit = ram_size; 1337 if (spapr->ram_limit > rma_alloc_size) { 1338 ram_addr_t nonrma_base = rma_alloc_size; 1339 ram_addr_t nonrma_size = spapr->ram_limit - rma_alloc_size; 1340 1341 memory_region_init_ram(ram, NULL, "ppc_spapr.ram", nonrma_size); 1342 vmstate_register_ram_global(ram); 1343 memory_region_add_subregion(sysmem, nonrma_base, ram); 1344 } 1345 1346 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 1347 spapr->rtas_size = load_image_targphys(filename, spapr->rtas_addr, 1348 rtas_limit - spapr->rtas_addr); 1349 if (spapr->rtas_size < 0) { 1350 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 1351 exit(1); 1352 } 1353 if (spapr->rtas_size > RTAS_MAX_SIZE) { 1354 hw_error("RTAS too big ! 0x%lx bytes (max is 0x%x)\n", 1355 spapr->rtas_size, RTAS_MAX_SIZE); 1356 exit(1); 1357 } 1358 g_free(filename); 1359 1360 /* Set up EPOW events infrastructure */ 1361 spapr_events_init(spapr); 1362 1363 /* Set up VIO bus */ 1364 spapr->vio_bus = spapr_vio_bus_init(); 1365 1366 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 1367 if (serial_hds[i]) { 1368 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 1369 } 1370 } 1371 1372 /* We always have at least the nvram device on VIO */ 1373 spapr_create_nvram(spapr); 1374 1375 /* Set up PCI */ 1376 spapr_pci_msi_init(spapr, SPAPR_PCI_MSI_WINDOW); 1377 spapr_pci_rtas_init(); 1378 1379 phb = spapr_create_phb(spapr, 0); 1380 1381 for (i = 0; i < nb_nics; i++) { 1382 NICInfo *nd = &nd_table[i]; 1383 1384 if (!nd->model) { 1385 nd->model = g_strdup("ibmveth"); 1386 } 1387 1388 if (strcmp(nd->model, "ibmveth") == 0) { 1389 spapr_vlan_create(spapr->vio_bus, nd); 1390 } else { 1391 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 1392 } 1393 } 1394 1395 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 1396 spapr_vscsi_create(spapr->vio_bus); 1397 } 1398 1399 /* Graphics */ 1400 if (spapr_vga_init(phb->bus)) { 1401 spapr->has_graphics = true; 1402 } 1403 1404 if (usb_enabled(spapr->has_graphics)) { 1405 pci_create_simple(phb->bus, -1, "pci-ohci"); 1406 if (spapr->has_graphics) { 1407 usbdevice_create("keyboard"); 1408 usbdevice_create("mouse"); 1409 } 1410 } 1411 1412 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 1413 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= " 1414 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF); 1415 exit(1); 1416 } 1417 1418 if (kernel_filename) { 1419 uint64_t lowaddr = 0; 1420 1421 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 1422 NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); 1423 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) { 1424 kernel_size = load_elf(kernel_filename, 1425 translate_kernel_address, NULL, 1426 NULL, &lowaddr, NULL, 0, ELF_MACHINE, 0); 1427 kernel_le = kernel_size > 0; 1428 } 1429 if (kernel_size < 0) { 1430 fprintf(stderr, "qemu: error loading %s: %s\n", 1431 kernel_filename, load_elf_strerror(kernel_size)); 1432 exit(1); 1433 } 1434 1435 /* load initrd */ 1436 if (initrd_filename) { 1437 /* Try to locate the initrd in the gap between the kernel 1438 * and the firmware. Add a bit of space just in case 1439 */ 1440 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; 1441 initrd_size = load_image_targphys(initrd_filename, initrd_base, 1442 load_limit - initrd_base); 1443 if (initrd_size < 0) { 1444 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 1445 initrd_filename); 1446 exit(1); 1447 } 1448 } else { 1449 initrd_base = 0; 1450 initrd_size = 0; 1451 } 1452 } 1453 1454 if (bios_name == NULL) { 1455 bios_name = FW_FILE_NAME; 1456 } 1457 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1458 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 1459 if (fw_size < 0) { 1460 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 1461 exit(1); 1462 } 1463 g_free(filename); 1464 1465 spapr->entry_point = 0x100; 1466 1467 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 1468 register_savevm_live(NULL, "spapr/htab", -1, 1, 1469 &savevm_htab_handlers, spapr); 1470 1471 /* Prepare the device tree */ 1472 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, 1473 kernel_size, kernel_le, 1474 boot_device, kernel_cmdline, 1475 spapr->epow_irq); 1476 assert(spapr->fdt_skel != NULL); 1477 } 1478 1479 static int spapr_kvm_type(const char *vm_type) 1480 { 1481 if (!vm_type) { 1482 return 0; 1483 } 1484 1485 if (!strcmp(vm_type, "HV")) { 1486 return 1; 1487 } 1488 1489 if (!strcmp(vm_type, "PR")) { 1490 return 2; 1491 } 1492 1493 error_report("Unknown kvm-type specified '%s'", vm_type); 1494 exit(1); 1495 } 1496 1497 /* 1498 * Implementation of an interface to adjust firmware patch 1499 * for the bootindex property handling. 1500 */ 1501 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 1502 DeviceState *dev) 1503 { 1504 #define CAST(type, obj, name) \ 1505 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 1506 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 1507 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 1508 1509 if (d) { 1510 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 1511 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 1512 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 1513 1514 if (spapr) { 1515 /* 1516 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 1517 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 1518 * in the top 16 bits of the 64-bit LUN 1519 */ 1520 unsigned id = 0x8000 | (d->id << 8) | d->lun; 1521 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1522 (uint64_t)id << 48); 1523 } else if (virtio) { 1524 /* 1525 * We use SRP luns of the form 01000000 | (target << 8) | lun 1526 * in the top 32 bits of the 64-bit LUN 1527 * Note: the quote above is from SLOF and it is wrong, 1528 * the actual binding is: 1529 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 1530 */ 1531 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 1532 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1533 (uint64_t)id << 32); 1534 } else if (usb) { 1535 /* 1536 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 1537 * in the top 32 bits of the 64-bit LUN 1538 */ 1539 unsigned usb_port = atoi(usb->port->path); 1540 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 1541 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1542 (uint64_t)id << 32); 1543 } 1544 } 1545 1546 if (phb) { 1547 /* Replace "pci" with "pci@800000020000000" */ 1548 return g_strdup_printf("pci@%"PRIX64, phb->buid); 1549 } 1550 1551 return NULL; 1552 } 1553 1554 static char *spapr_get_kvm_type(Object *obj, Error **errp) 1555 { 1556 sPAPRMachineState *sm = SPAPR_MACHINE(obj); 1557 1558 return g_strdup(sm->kvm_type); 1559 } 1560 1561 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 1562 { 1563 sPAPRMachineState *sm = SPAPR_MACHINE(obj); 1564 1565 g_free(sm->kvm_type); 1566 sm->kvm_type = g_strdup(value); 1567 } 1568 1569 static void spapr_machine_initfn(Object *obj) 1570 { 1571 object_property_add_str(obj, "kvm-type", 1572 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 1573 } 1574 1575 static void spapr_machine_class_init(ObjectClass *oc, void *data) 1576 { 1577 MachineClass *mc = MACHINE_CLASS(oc); 1578 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 1579 1580 mc->name = "pseries"; 1581 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 1582 mc->is_default = 1; 1583 mc->init = ppc_spapr_init; 1584 mc->reset = ppc_spapr_reset; 1585 mc->block_default_type = IF_SCSI; 1586 mc->max_cpus = MAX_CPUS; 1587 mc->no_parallel = 1; 1588 mc->default_boot_order = NULL; 1589 mc->kvm_type = spapr_kvm_type; 1590 1591 fwc->get_dev_path = spapr_get_fw_dev_path; 1592 } 1593 1594 static const TypeInfo spapr_machine_info = { 1595 .name = TYPE_SPAPR_MACHINE, 1596 .parent = TYPE_MACHINE, 1597 .instance_size = sizeof(sPAPRMachineState), 1598 .instance_init = spapr_machine_initfn, 1599 .class_init = spapr_machine_class_init, 1600 .interfaces = (InterfaceInfo[]) { 1601 { TYPE_FW_PATH_PROVIDER }, 1602 { } 1603 }, 1604 }; 1605 1606 static void spapr_machine_2_1_class_init(ObjectClass *oc, void *data) 1607 { 1608 MachineClass *mc = MACHINE_CLASS(oc); 1609 1610 mc->name = "pseries-2.1"; 1611 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.1"; 1612 mc->is_default = 0; 1613 } 1614 1615 static const TypeInfo spapr_machine_2_1_info = { 1616 .name = TYPE_SPAPR_MACHINE "2.1", 1617 .parent = TYPE_SPAPR_MACHINE, 1618 .class_init = spapr_machine_2_1_class_init, 1619 }; 1620 1621 static void spapr_machine_register_types(void) 1622 { 1623 type_register_static(&spapr_machine_info); 1624 type_register_static(&spapr_machine_2_1_info); 1625 } 1626 1627 type_init(spapr_machine_register_types) 1628