1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/numa.h" 31 #include "hw/hw.h" 32 #include "qemu/log.h" 33 #include "hw/fw-path-provider.h" 34 #include "elf.h" 35 #include "net/net.h" 36 #include "sysemu/device_tree.h" 37 #include "sysemu/block-backend.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/hw_accel.h" 40 #include "kvm_ppc.h" 41 #include "migration/migration.h" 42 #include "mmu-hash64.h" 43 #include "mmu-book3s-v3.h" 44 #include "qom/cpu.h" 45 46 #include "hw/boards.h" 47 #include "hw/ppc/ppc.h" 48 #include "hw/loader.h" 49 50 #include "hw/ppc/fdt.h" 51 #include "hw/ppc/spapr.h" 52 #include "hw/ppc/spapr_vio.h" 53 #include "hw/pci-host/spapr.h" 54 #include "hw/ppc/xics.h" 55 #include "hw/pci/msi.h" 56 57 #include "hw/pci/pci.h" 58 #include "hw/scsi/scsi.h" 59 #include "hw/virtio/virtio-scsi.h" 60 61 #include "exec/address-spaces.h" 62 #include "hw/usb.h" 63 #include "qemu/config-file.h" 64 #include "qemu/error-report.h" 65 #include "trace.h" 66 #include "hw/nmi.h" 67 #include "hw/intc/intc.h" 68 69 #include "hw/compat.h" 70 #include "qemu/cutils.h" 71 #include "hw/ppc/spapr_cpu_core.h" 72 #include "qmp-commands.h" 73 74 #include <libfdt.h> 75 76 /* SLOF memory layout: 77 * 78 * SLOF raw image loaded at 0, copies its romfs right below the flat 79 * device-tree, then position SLOF itself 31M below that 80 * 81 * So we set FW_OVERHEAD to 40MB which should account for all of that 82 * and more 83 * 84 * We load our kernel at 4M, leaving space for SLOF initial image 85 */ 86 #define FDT_MAX_SIZE 0x100000 87 #define RTAS_MAX_SIZE 0x10000 88 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 89 #define FW_MAX_SIZE 0x400000 90 #define FW_FILE_NAME "slof.bin" 91 #define FW_OVERHEAD 0x2800000 92 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 93 94 #define MIN_RMA_SLOF 128UL 95 96 #define PHANDLE_XICP 0x00001111 97 98 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 99 100 static ICSState *spapr_ics_create(sPAPRMachineState *spapr, 101 const char *type_ics, 102 int nr_irqs, Error **errp) 103 { 104 Error *local_err = NULL; 105 Object *obj; 106 107 obj = object_new(type_ics); 108 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); 109 object_property_add_const_link(obj, "xics", OBJECT(spapr), &error_abort); 110 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err); 111 if (local_err) { 112 goto error; 113 } 114 object_property_set_bool(obj, true, "realized", &local_err); 115 if (local_err) { 116 goto error; 117 } 118 119 return ICS_SIMPLE(obj); 120 121 error: 122 error_propagate(errp, local_err); 123 return NULL; 124 } 125 126 static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp) 127 { 128 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 129 130 if (kvm_enabled()) { 131 Error *err = NULL; 132 133 if (machine_kernel_irqchip_allowed(machine) && 134 !xics_kvm_init(spapr, errp)) { 135 spapr->icp_type = TYPE_KVM_ICP; 136 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, &err); 137 } 138 if (machine_kernel_irqchip_required(machine) && !spapr->ics) { 139 error_reportf_err(err, 140 "kernel_irqchip requested but unavailable: "); 141 } else { 142 error_free(err); 143 } 144 } 145 146 if (!spapr->ics) { 147 xics_spapr_init(spapr); 148 spapr->icp_type = TYPE_ICP; 149 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp); 150 } 151 } 152 153 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 154 int smt_threads) 155 { 156 int i, ret = 0; 157 uint32_t servers_prop[smt_threads]; 158 uint32_t gservers_prop[smt_threads * 2]; 159 int index = ppc_get_vcpu_dt_id(cpu); 160 161 if (cpu->compat_pvr) { 162 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 163 if (ret < 0) { 164 return ret; 165 } 166 } 167 168 /* Build interrupt servers and gservers properties */ 169 for (i = 0; i < smt_threads; i++) { 170 servers_prop[i] = cpu_to_be32(index + i); 171 /* Hack, direct the group queues back to cpu 0 */ 172 gservers_prop[i*2] = cpu_to_be32(index + i); 173 gservers_prop[i*2 + 1] = 0; 174 } 175 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 176 servers_prop, sizeof(servers_prop)); 177 if (ret < 0) { 178 return ret; 179 } 180 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 181 gservers_prop, sizeof(gservers_prop)); 182 183 return ret; 184 } 185 186 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs) 187 { 188 int ret = 0; 189 PowerPCCPU *cpu = POWERPC_CPU(cs); 190 int index = ppc_get_vcpu_dt_id(cpu); 191 uint32_t associativity[] = {cpu_to_be32(0x5), 192 cpu_to_be32(0x0), 193 cpu_to_be32(0x0), 194 cpu_to_be32(0x0), 195 cpu_to_be32(cs->numa_node), 196 cpu_to_be32(index)}; 197 198 /* Advertise NUMA via ibm,associativity */ 199 if (nb_numa_nodes > 1) { 200 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 201 sizeof(associativity)); 202 } 203 204 return ret; 205 } 206 207 /* Populate the "ibm,pa-features" property */ 208 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset, 209 bool legacy_guest) 210 { 211 uint8_t pa_features_206[] = { 6, 0, 212 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 213 uint8_t pa_features_207[] = { 24, 0, 214 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 215 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 216 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 217 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 218 uint8_t pa_features_300[] = { 66, 0, 219 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 220 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 221 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 222 /* 6: DS207 */ 223 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 224 /* 16: Vector */ 225 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 226 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 227 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 228 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 229 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 230 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 231 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 232 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 233 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 234 /* 42: PM, 44: PC RA, 46: SC vec'd */ 235 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 236 /* 48: SIMD, 50: QP BFP, 52: String */ 237 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 238 /* 54: DecFP, 56: DecI, 58: SHA */ 239 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 240 /* 60: NM atomic, 62: RNG */ 241 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 242 }; 243 uint8_t *pa_features; 244 size_t pa_size; 245 246 switch (POWERPC_MMU_VER(env->mmu_model)) { 247 case POWERPC_MMU_VER_2_06: 248 pa_features = pa_features_206; 249 pa_size = sizeof(pa_features_206); 250 break; 251 case POWERPC_MMU_VER_2_07: 252 pa_features = pa_features_207; 253 pa_size = sizeof(pa_features_207); 254 break; 255 case POWERPC_MMU_VER_3_00: 256 pa_features = pa_features_300; 257 pa_size = sizeof(pa_features_300); 258 break; 259 default: 260 return; 261 } 262 263 if (env->ci_large_pages) { 264 /* 265 * Note: we keep CI large pages off by default because a 64K capable 266 * guest provisioned with large pages might otherwise try to map a qemu 267 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 268 * even if that qemu runs on a 4k host. 269 * We dd this bit back here if we are confident this is not an issue 270 */ 271 pa_features[3] |= 0x20; 272 } 273 if (kvmppc_has_cap_htm() && pa_size > 24) { 274 pa_features[24] |= 0x80; /* Transactional memory support */ 275 } 276 if (legacy_guest && pa_size > 40) { 277 /* Workaround for broken kernels that attempt (guest) radix 278 * mode when they can't handle it, if they see the radix bit set 279 * in pa-features. So hide it from them. */ 280 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 281 } 282 283 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 284 } 285 286 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 287 { 288 int ret = 0, offset, cpus_offset; 289 CPUState *cs; 290 char cpu_model[32]; 291 int smt = kvmppc_smt_threads(); 292 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 293 294 CPU_FOREACH(cs) { 295 PowerPCCPU *cpu = POWERPC_CPU(cs); 296 CPUPPCState *env = &cpu->env; 297 DeviceClass *dc = DEVICE_GET_CLASS(cs); 298 int index = ppc_get_vcpu_dt_id(cpu); 299 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 300 301 if ((index % smt) != 0) { 302 continue; 303 } 304 305 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 306 307 cpus_offset = fdt_path_offset(fdt, "/cpus"); 308 if (cpus_offset < 0) { 309 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 310 "cpus"); 311 if (cpus_offset < 0) { 312 return cpus_offset; 313 } 314 } 315 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 316 if (offset < 0) { 317 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 318 if (offset < 0) { 319 return offset; 320 } 321 } 322 323 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 324 pft_size_prop, sizeof(pft_size_prop)); 325 if (ret < 0) { 326 return ret; 327 } 328 329 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs); 330 if (ret < 0) { 331 return ret; 332 } 333 334 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 335 if (ret < 0) { 336 return ret; 337 } 338 339 spapr_populate_pa_features(env, fdt, offset, 340 spapr->cas_legacy_guest_workaround); 341 } 342 return ret; 343 } 344 345 static hwaddr spapr_node0_size(void) 346 { 347 MachineState *machine = MACHINE(qdev_get_machine()); 348 349 if (nb_numa_nodes) { 350 int i; 351 for (i = 0; i < nb_numa_nodes; ++i) { 352 if (numa_info[i].node_mem) { 353 return MIN(pow2floor(numa_info[i].node_mem), 354 machine->ram_size); 355 } 356 } 357 } 358 return machine->ram_size; 359 } 360 361 static void add_str(GString *s, const gchar *s1) 362 { 363 g_string_append_len(s, s1, strlen(s1) + 1); 364 } 365 366 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 367 hwaddr size) 368 { 369 uint32_t associativity[] = { 370 cpu_to_be32(0x4), /* length */ 371 cpu_to_be32(0x0), cpu_to_be32(0x0), 372 cpu_to_be32(0x0), cpu_to_be32(nodeid) 373 }; 374 char mem_name[32]; 375 uint64_t mem_reg_property[2]; 376 int off; 377 378 mem_reg_property[0] = cpu_to_be64(start); 379 mem_reg_property[1] = cpu_to_be64(size); 380 381 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 382 off = fdt_add_subnode(fdt, 0, mem_name); 383 _FDT(off); 384 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 385 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 386 sizeof(mem_reg_property)))); 387 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 388 sizeof(associativity)))); 389 return off; 390 } 391 392 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 393 { 394 MachineState *machine = MACHINE(spapr); 395 hwaddr mem_start, node_size; 396 int i, nb_nodes = nb_numa_nodes; 397 NodeInfo *nodes = numa_info; 398 NodeInfo ramnode; 399 400 /* No NUMA nodes, assume there is just one node with whole RAM */ 401 if (!nb_numa_nodes) { 402 nb_nodes = 1; 403 ramnode.node_mem = machine->ram_size; 404 nodes = &ramnode; 405 } 406 407 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 408 if (!nodes[i].node_mem) { 409 continue; 410 } 411 if (mem_start >= machine->ram_size) { 412 node_size = 0; 413 } else { 414 node_size = nodes[i].node_mem; 415 if (node_size > machine->ram_size - mem_start) { 416 node_size = machine->ram_size - mem_start; 417 } 418 } 419 if (!mem_start) { 420 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 421 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 422 mem_start += spapr->rma_size; 423 node_size -= spapr->rma_size; 424 } 425 for ( ; node_size; ) { 426 hwaddr sizetmp = pow2floor(node_size); 427 428 /* mem_start != 0 here */ 429 if (ctzl(mem_start) < ctzl(sizetmp)) { 430 sizetmp = 1ULL << ctzl(mem_start); 431 } 432 433 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 434 node_size -= sizetmp; 435 mem_start += sizetmp; 436 } 437 } 438 439 return 0; 440 } 441 442 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 443 sPAPRMachineState *spapr) 444 { 445 PowerPCCPU *cpu = POWERPC_CPU(cs); 446 CPUPPCState *env = &cpu->env; 447 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 448 int index = ppc_get_vcpu_dt_id(cpu); 449 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 450 0xffffffff, 0xffffffff}; 451 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 452 : SPAPR_TIMEBASE_FREQ; 453 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 454 uint32_t page_sizes_prop[64]; 455 size_t page_sizes_prop_size; 456 uint32_t vcpus_per_socket = smp_threads * smp_cores; 457 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 458 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 459 sPAPRDRConnector *drc; 460 sPAPRDRConnectorClass *drck; 461 int drc_index; 462 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 463 int i; 464 465 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index); 466 if (drc) { 467 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 468 drc_index = drck->get_index(drc); 469 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 470 } 471 472 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 473 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 474 475 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 476 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 477 env->dcache_line_size))); 478 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 479 env->dcache_line_size))); 480 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 481 env->icache_line_size))); 482 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 483 env->icache_line_size))); 484 485 if (pcc->l1_dcache_size) { 486 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 487 pcc->l1_dcache_size))); 488 } else { 489 error_report("Warning: Unknown L1 dcache size for cpu"); 490 } 491 if (pcc->l1_icache_size) { 492 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 493 pcc->l1_icache_size))); 494 } else { 495 error_report("Warning: Unknown L1 icache size for cpu"); 496 } 497 498 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 499 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 500 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 501 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 502 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 503 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 504 505 if (env->spr_cb[SPR_PURR].oea_read) { 506 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 507 } 508 509 if (env->mmu_model & POWERPC_MMU_1TSEG) { 510 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 511 segs, sizeof(segs)))); 512 } 513 514 /* Advertise VMX/VSX (vector extensions) if available 515 * 0 / no property == no vector extensions 516 * 1 == VMX / Altivec available 517 * 2 == VSX available */ 518 if (env->insns_flags & PPC_ALTIVEC) { 519 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 520 521 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 522 } 523 524 /* Advertise DFP (Decimal Floating Point) if available 525 * 0 / no property == no DFP 526 * 1 == DFP available */ 527 if (env->insns_flags2 & PPC2_DFP) { 528 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 529 } 530 531 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 532 sizeof(page_sizes_prop)); 533 if (page_sizes_prop_size) { 534 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 535 page_sizes_prop, page_sizes_prop_size))); 536 } 537 538 spapr_populate_pa_features(env, fdt, offset, false); 539 540 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 541 cs->cpu_index / vcpus_per_socket))); 542 543 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 544 pft_size_prop, sizeof(pft_size_prop)))); 545 546 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs)); 547 548 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 549 550 if (pcc->radix_page_info) { 551 for (i = 0; i < pcc->radix_page_info->count; i++) { 552 radix_AP_encodings[i] = 553 cpu_to_be32(pcc->radix_page_info->entries[i]); 554 } 555 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 556 radix_AP_encodings, 557 pcc->radix_page_info->count * 558 sizeof(radix_AP_encodings[0])))); 559 } 560 } 561 562 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 563 { 564 CPUState *cs; 565 int cpus_offset; 566 char *nodename; 567 int smt = kvmppc_smt_threads(); 568 569 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 570 _FDT(cpus_offset); 571 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 572 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 573 574 /* 575 * We walk the CPUs in reverse order to ensure that CPU DT nodes 576 * created by fdt_add_subnode() end up in the right order in FDT 577 * for the guest kernel the enumerate the CPUs correctly. 578 */ 579 CPU_FOREACH_REVERSE(cs) { 580 PowerPCCPU *cpu = POWERPC_CPU(cs); 581 int index = ppc_get_vcpu_dt_id(cpu); 582 DeviceClass *dc = DEVICE_GET_CLASS(cs); 583 int offset; 584 585 if ((index % smt) != 0) { 586 continue; 587 } 588 589 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 590 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 591 g_free(nodename); 592 _FDT(offset); 593 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 594 } 595 596 } 597 598 /* 599 * Adds ibm,dynamic-reconfiguration-memory node. 600 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 601 * of this device tree node. 602 */ 603 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 604 { 605 MachineState *machine = MACHINE(spapr); 606 int ret, i, offset; 607 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 608 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 609 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 610 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 611 memory_region_size(&spapr->hotplug_memory.mr)) / 612 lmb_size; 613 uint32_t *int_buf, *cur_index, buf_len; 614 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 615 616 /* 617 * Don't create the node if there is no hotpluggable memory 618 */ 619 if (machine->ram_size == machine->maxram_size) { 620 return 0; 621 } 622 623 /* 624 * Allocate enough buffer size to fit in ibm,dynamic-memory 625 * or ibm,associativity-lookup-arrays 626 */ 627 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 628 * sizeof(uint32_t); 629 cur_index = int_buf = g_malloc0(buf_len); 630 631 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 632 633 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 634 sizeof(prop_lmb_size)); 635 if (ret < 0) { 636 goto out; 637 } 638 639 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 640 if (ret < 0) { 641 goto out; 642 } 643 644 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 645 if (ret < 0) { 646 goto out; 647 } 648 649 /* ibm,dynamic-memory */ 650 int_buf[0] = cpu_to_be32(nr_lmbs); 651 cur_index++; 652 for (i = 0; i < nr_lmbs; i++) { 653 uint64_t addr = i * lmb_size; 654 uint32_t *dynamic_memory = cur_index; 655 656 if (i >= hotplug_lmb_start) { 657 sPAPRDRConnector *drc; 658 sPAPRDRConnectorClass *drck; 659 660 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i); 661 g_assert(drc); 662 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 663 664 dynamic_memory[0] = cpu_to_be32(addr >> 32); 665 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 666 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); 667 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 668 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); 669 if (memory_region_present(get_system_memory(), addr)) { 670 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 671 } else { 672 dynamic_memory[5] = cpu_to_be32(0); 673 } 674 } else { 675 /* 676 * LMB information for RMA, boot time RAM and gap b/n RAM and 677 * hotplug memory region -- all these are marked as reserved 678 * and as having no valid DRC. 679 */ 680 dynamic_memory[0] = cpu_to_be32(addr >> 32); 681 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 682 dynamic_memory[2] = cpu_to_be32(0); 683 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 684 dynamic_memory[4] = cpu_to_be32(-1); 685 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 686 SPAPR_LMB_FLAGS_DRC_INVALID); 687 } 688 689 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 690 } 691 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 692 if (ret < 0) { 693 goto out; 694 } 695 696 /* ibm,associativity-lookup-arrays */ 697 cur_index = int_buf; 698 int_buf[0] = cpu_to_be32(nr_nodes); 699 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 700 cur_index += 2; 701 for (i = 0; i < nr_nodes; i++) { 702 uint32_t associativity[] = { 703 cpu_to_be32(0x0), 704 cpu_to_be32(0x0), 705 cpu_to_be32(0x0), 706 cpu_to_be32(i) 707 }; 708 memcpy(cur_index, associativity, sizeof(associativity)); 709 cur_index += 4; 710 } 711 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 712 (cur_index - int_buf) * sizeof(uint32_t)); 713 out: 714 g_free(int_buf); 715 return ret; 716 } 717 718 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 719 sPAPROptionVector *ov5_updates) 720 { 721 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 722 int ret = 0, offset; 723 724 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 725 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 726 g_assert(smc->dr_lmb_enabled); 727 ret = spapr_populate_drconf_memory(spapr, fdt); 728 if (ret) { 729 goto out; 730 } 731 } 732 733 offset = fdt_path_offset(fdt, "/chosen"); 734 if (offset < 0) { 735 offset = fdt_add_subnode(fdt, 0, "chosen"); 736 if (offset < 0) { 737 return offset; 738 } 739 } 740 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 741 "ibm,architecture-vec-5"); 742 743 out: 744 return ret; 745 } 746 747 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 748 target_ulong addr, target_ulong size, 749 sPAPROptionVector *ov5_updates) 750 { 751 void *fdt, *fdt_skel; 752 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 753 754 size -= sizeof(hdr); 755 756 /* Create sceleton */ 757 fdt_skel = g_malloc0(size); 758 _FDT((fdt_create(fdt_skel, size))); 759 _FDT((fdt_begin_node(fdt_skel, ""))); 760 _FDT((fdt_end_node(fdt_skel))); 761 _FDT((fdt_finish(fdt_skel))); 762 fdt = g_malloc0(size); 763 _FDT((fdt_open_into(fdt_skel, fdt, size))); 764 g_free(fdt_skel); 765 766 /* Fixup cpu nodes */ 767 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 768 769 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 770 return -1; 771 } 772 773 /* Pack resulting tree */ 774 _FDT((fdt_pack(fdt))); 775 776 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 777 trace_spapr_cas_failed(size); 778 return -1; 779 } 780 781 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 782 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 783 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 784 g_free(fdt); 785 786 return 0; 787 } 788 789 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 790 { 791 int rtas; 792 GString *hypertas = g_string_sized_new(256); 793 GString *qemu_hypertas = g_string_sized_new(256); 794 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 795 uint64_t max_hotplug_addr = spapr->hotplug_memory.base + 796 memory_region_size(&spapr->hotplug_memory.mr); 797 uint32_t lrdr_capacity[] = { 798 cpu_to_be32(max_hotplug_addr >> 32), 799 cpu_to_be32(max_hotplug_addr & 0xffffffff), 800 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 801 cpu_to_be32(max_cpus / smp_threads), 802 }; 803 804 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 805 806 /* hypertas */ 807 add_str(hypertas, "hcall-pft"); 808 add_str(hypertas, "hcall-term"); 809 add_str(hypertas, "hcall-dabr"); 810 add_str(hypertas, "hcall-interrupt"); 811 add_str(hypertas, "hcall-tce"); 812 add_str(hypertas, "hcall-vio"); 813 add_str(hypertas, "hcall-splpar"); 814 add_str(hypertas, "hcall-bulk"); 815 add_str(hypertas, "hcall-set-mode"); 816 add_str(hypertas, "hcall-sprg0"); 817 add_str(hypertas, "hcall-copy"); 818 add_str(hypertas, "hcall-debug"); 819 add_str(qemu_hypertas, "hcall-memop1"); 820 821 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 822 add_str(hypertas, "hcall-multi-tce"); 823 } 824 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 825 hypertas->str, hypertas->len)); 826 g_string_free(hypertas, TRUE); 827 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 828 qemu_hypertas->str, qemu_hypertas->len)); 829 g_string_free(qemu_hypertas, TRUE); 830 831 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 832 refpoints, sizeof(refpoints))); 833 834 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 835 RTAS_ERROR_LOG_MAX)); 836 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 837 RTAS_EVENT_SCAN_RATE)); 838 839 if (msi_nonbroken) { 840 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 841 } 842 843 /* 844 * According to PAPR, rtas ibm,os-term does not guarantee a return 845 * back to the guest cpu. 846 * 847 * While an additional ibm,extended-os-term property indicates 848 * that rtas call return will always occur. Set this property. 849 */ 850 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 851 852 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 853 lrdr_capacity, sizeof(lrdr_capacity))); 854 855 spapr_dt_rtas_tokens(fdt, rtas); 856 } 857 858 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features 859 * that the guest may request and thus the valid values for bytes 24..26 of 860 * option vector 5: */ 861 static void spapr_dt_ov5_platform_support(void *fdt, int chosen) 862 { 863 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 864 865 char val[2 * 3] = { 866 24, 0x00, /* Hash/Radix, filled in below. */ 867 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 868 26, 0x40, /* Radix options: GTSE == yes. */ 869 }; 870 871 if (kvm_enabled()) { 872 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 873 val[1] = 0x80; /* OV5_MMU_BOTH */ 874 } else if (kvmppc_has_cap_mmu_radix()) { 875 val[1] = 0x40; /* OV5_MMU_RADIX_300 */ 876 } else { 877 val[1] = 0x00; /* Hash */ 878 } 879 } else { 880 if (first_ppc_cpu->env.mmu_model & POWERPC_MMU_V3) { 881 /* V3 MMU supports both hash and radix (with dynamic switching) */ 882 val[1] = 0xC0; 883 } else { 884 /* Otherwise we can only do hash */ 885 val[1] = 0x00; 886 } 887 } 888 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 889 val, sizeof(val))); 890 } 891 892 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 893 { 894 MachineState *machine = MACHINE(spapr); 895 int chosen; 896 const char *boot_device = machine->boot_order; 897 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 898 size_t cb = 0; 899 char *bootlist = get_boot_devices_list(&cb, true); 900 901 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 902 903 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 904 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 905 spapr->initrd_base)); 906 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 907 spapr->initrd_base + spapr->initrd_size)); 908 909 if (spapr->kernel_size) { 910 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 911 cpu_to_be64(spapr->kernel_size) }; 912 913 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 914 &kprop, sizeof(kprop))); 915 if (spapr->kernel_le) { 916 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 917 } 918 } 919 if (boot_menu) { 920 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 921 } 922 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 923 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 924 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 925 926 if (cb && bootlist) { 927 int i; 928 929 for (i = 0; i < cb; i++) { 930 if (bootlist[i] == '\n') { 931 bootlist[i] = ' '; 932 } 933 } 934 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 935 } 936 937 if (boot_device && strlen(boot_device)) { 938 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 939 } 940 941 if (!spapr->has_graphics && stdout_path) { 942 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 943 } 944 945 spapr_dt_ov5_platform_support(fdt, chosen); 946 947 g_free(stdout_path); 948 g_free(bootlist); 949 } 950 951 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 952 { 953 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 954 * KVM to work under pHyp with some guest co-operation */ 955 int hypervisor; 956 uint8_t hypercall[16]; 957 958 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 959 /* indicate KVM hypercall interface */ 960 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 961 if (kvmppc_has_cap_fixup_hcalls()) { 962 /* 963 * Older KVM versions with older guest kernels were broken 964 * with the magic page, don't allow the guest to map it. 965 */ 966 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 967 sizeof(hypercall))) { 968 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 969 hypercall, sizeof(hypercall))); 970 } 971 } 972 } 973 974 static void *spapr_build_fdt(sPAPRMachineState *spapr, 975 hwaddr rtas_addr, 976 hwaddr rtas_size) 977 { 978 MachineState *machine = MACHINE(qdev_get_machine()); 979 MachineClass *mc = MACHINE_GET_CLASS(machine); 980 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 981 int ret; 982 void *fdt; 983 sPAPRPHBState *phb; 984 char *buf; 985 int smt = kvmppc_smt_threads(); 986 987 fdt = g_malloc0(FDT_MAX_SIZE); 988 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 989 990 /* Root node */ 991 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 992 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 993 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 994 995 /* 996 * Add info to guest to indentify which host is it being run on 997 * and what is the uuid of the guest 998 */ 999 if (kvmppc_get_host_model(&buf)) { 1000 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1001 g_free(buf); 1002 } 1003 if (kvmppc_get_host_serial(&buf)) { 1004 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1005 g_free(buf); 1006 } 1007 1008 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1009 1010 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1011 if (qemu_uuid_set) { 1012 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1013 } 1014 g_free(buf); 1015 1016 if (qemu_get_vm_name()) { 1017 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1018 qemu_get_vm_name())); 1019 } 1020 1021 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1022 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1023 1024 /* /interrupt controller */ 1025 spapr_dt_xics(DIV_ROUND_UP(max_cpus * smt, smp_threads), fdt, PHANDLE_XICP); 1026 1027 ret = spapr_populate_memory(spapr, fdt); 1028 if (ret < 0) { 1029 error_report("couldn't setup memory nodes in fdt"); 1030 exit(1); 1031 } 1032 1033 /* /vdevice */ 1034 spapr_dt_vdevice(spapr->vio_bus, fdt); 1035 1036 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1037 ret = spapr_rng_populate_dt(fdt); 1038 if (ret < 0) { 1039 error_report("could not set up rng device in the fdt"); 1040 exit(1); 1041 } 1042 } 1043 1044 QLIST_FOREACH(phb, &spapr->phbs, list) { 1045 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 1046 if (ret < 0) { 1047 error_report("couldn't setup PCI devices in fdt"); 1048 exit(1); 1049 } 1050 } 1051 1052 /* cpus */ 1053 spapr_populate_cpus_dt_node(fdt, spapr); 1054 1055 if (smc->dr_lmb_enabled) { 1056 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1057 } 1058 1059 if (mc->has_hotpluggable_cpus) { 1060 int offset = fdt_path_offset(fdt, "/cpus"); 1061 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1062 SPAPR_DR_CONNECTOR_TYPE_CPU); 1063 if (ret < 0) { 1064 error_report("Couldn't set up CPU DR device tree properties"); 1065 exit(1); 1066 } 1067 } 1068 1069 /* /event-sources */ 1070 spapr_dt_events(spapr, fdt); 1071 1072 /* /rtas */ 1073 spapr_dt_rtas(spapr, fdt); 1074 1075 /* /chosen */ 1076 spapr_dt_chosen(spapr, fdt); 1077 1078 /* /hypervisor */ 1079 if (kvm_enabled()) { 1080 spapr_dt_hypervisor(spapr, fdt); 1081 } 1082 1083 /* Build memory reserve map */ 1084 if (spapr->kernel_size) { 1085 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1086 } 1087 if (spapr->initrd_size) { 1088 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1089 } 1090 1091 /* ibm,client-architecture-support updates */ 1092 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1093 if (ret < 0) { 1094 error_report("couldn't setup CAS properties fdt"); 1095 exit(1); 1096 } 1097 1098 return fdt; 1099 } 1100 1101 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1102 { 1103 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1104 } 1105 1106 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1107 PowerPCCPU *cpu) 1108 { 1109 CPUPPCState *env = &cpu->env; 1110 1111 /* The TCG path should also be holding the BQL at this point */ 1112 g_assert(qemu_mutex_iothread_locked()); 1113 1114 if (msr_pr) { 1115 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1116 env->gpr[3] = H_PRIVILEGE; 1117 } else { 1118 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1119 } 1120 } 1121 1122 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) 1123 { 1124 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1125 1126 return spapr->patb_entry; 1127 } 1128 1129 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1130 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1131 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1132 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1133 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1134 1135 /* 1136 * Get the fd to access the kernel htab, re-opening it if necessary 1137 */ 1138 static int get_htab_fd(sPAPRMachineState *spapr) 1139 { 1140 if (spapr->htab_fd >= 0) { 1141 return spapr->htab_fd; 1142 } 1143 1144 spapr->htab_fd = kvmppc_get_htab_fd(false); 1145 if (spapr->htab_fd < 0) { 1146 error_report("Unable to open fd for reading hash table from KVM: %s", 1147 strerror(errno)); 1148 } 1149 1150 return spapr->htab_fd; 1151 } 1152 1153 void close_htab_fd(sPAPRMachineState *spapr) 1154 { 1155 if (spapr->htab_fd >= 0) { 1156 close(spapr->htab_fd); 1157 } 1158 spapr->htab_fd = -1; 1159 } 1160 1161 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1162 { 1163 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1164 1165 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1166 } 1167 1168 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1169 hwaddr ptex, int n) 1170 { 1171 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1172 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1173 1174 if (!spapr->htab) { 1175 /* 1176 * HTAB is controlled by KVM. Fetch into temporary buffer 1177 */ 1178 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1179 kvmppc_read_hptes(hptes, ptex, n); 1180 return hptes; 1181 } 1182 1183 /* 1184 * HTAB is controlled by QEMU. Just point to the internally 1185 * accessible PTEG. 1186 */ 1187 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1188 } 1189 1190 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1191 const ppc_hash_pte64_t *hptes, 1192 hwaddr ptex, int n) 1193 { 1194 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1195 1196 if (!spapr->htab) { 1197 g_free((void *)hptes); 1198 } 1199 1200 /* Nothing to do for qemu managed HPT */ 1201 } 1202 1203 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1204 uint64_t pte0, uint64_t pte1) 1205 { 1206 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1207 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1208 1209 if (!spapr->htab) { 1210 kvmppc_write_hpte(ptex, pte0, pte1); 1211 } else { 1212 stq_p(spapr->htab + offset, pte0); 1213 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1214 } 1215 } 1216 1217 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1218 { 1219 int shift; 1220 1221 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1222 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1223 * that's much more than is needed for Linux guests */ 1224 shift = ctz64(pow2ceil(ramsize)) - 7; 1225 shift = MAX(shift, 18); /* Minimum architected size */ 1226 shift = MIN(shift, 46); /* Maximum architected size */ 1227 return shift; 1228 } 1229 1230 void spapr_free_hpt(sPAPRMachineState *spapr) 1231 { 1232 g_free(spapr->htab); 1233 spapr->htab = NULL; 1234 spapr->htab_shift = 0; 1235 close_htab_fd(spapr); 1236 } 1237 1238 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1239 Error **errp) 1240 { 1241 long rc; 1242 1243 /* Clean up any HPT info from a previous boot */ 1244 spapr_free_hpt(spapr); 1245 1246 rc = kvmppc_reset_htab(shift); 1247 if (rc < 0) { 1248 /* kernel-side HPT needed, but couldn't allocate one */ 1249 error_setg_errno(errp, errno, 1250 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1251 shift); 1252 /* This is almost certainly fatal, but if the caller really 1253 * wants to carry on with shift == 0, it's welcome to try */ 1254 } else if (rc > 0) { 1255 /* kernel-side HPT allocated */ 1256 if (rc != shift) { 1257 error_setg(errp, 1258 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1259 shift, rc); 1260 } 1261 1262 spapr->htab_shift = shift; 1263 spapr->htab = NULL; 1264 } else { 1265 /* kernel-side HPT not needed, allocate in userspace instead */ 1266 size_t size = 1ULL << shift; 1267 int i; 1268 1269 spapr->htab = qemu_memalign(size, size); 1270 if (!spapr->htab) { 1271 error_setg_errno(errp, errno, 1272 "Could not allocate HPT of order %d", shift); 1273 return; 1274 } 1275 1276 memset(spapr->htab, 0, size); 1277 spapr->htab_shift = shift; 1278 1279 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1280 DIRTY_HPTE(HPTE(spapr->htab, i)); 1281 } 1282 } 1283 } 1284 1285 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) 1286 { 1287 spapr_reallocate_hpt(spapr, 1288 spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size), 1289 &error_fatal); 1290 if (spapr->vrma_adjust) { 1291 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 1292 spapr->htab_shift); 1293 } 1294 /* We're setting up a hash table, so that means we're not radix */ 1295 spapr->patb_entry = 0; 1296 } 1297 1298 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1299 { 1300 bool matched = false; 1301 1302 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1303 matched = true; 1304 } 1305 1306 if (!matched) { 1307 error_report("Device %s is not supported by this machine yet.", 1308 qdev_fw_name(DEVICE(sbdev))); 1309 exit(1); 1310 } 1311 } 1312 1313 static void ppc_spapr_reset(void) 1314 { 1315 MachineState *machine = MACHINE(qdev_get_machine()); 1316 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1317 PowerPCCPU *first_ppc_cpu; 1318 uint32_t rtas_limit; 1319 hwaddr rtas_addr, fdt_addr; 1320 void *fdt; 1321 int rc; 1322 1323 /* Check for unknown sysbus devices */ 1324 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1325 1326 if (kvm_enabled() && kvmppc_has_cap_mmu_radix()) { 1327 /* If using KVM with radix mode available, VCPUs can be started 1328 * without a HPT because KVM will start them in radix mode. 1329 * Set the GR bit in PATB so that we know there is no HPT. */ 1330 spapr->patb_entry = PATBE1_GR; 1331 } else { 1332 spapr->patb_entry = 0; 1333 spapr_setup_hpt_and_vrma(spapr); 1334 } 1335 1336 qemu_devices_reset(); 1337 1338 /* 1339 * We place the device tree and RTAS just below either the top of the RMA, 1340 * or just below 2GB, whichever is lowere, so that it can be 1341 * processed with 32-bit real mode code if necessary 1342 */ 1343 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1344 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1345 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1346 1347 /* if this reset wasn't generated by CAS, we should reset our 1348 * negotiated options and start from scratch */ 1349 if (!spapr->cas_reboot) { 1350 spapr_ovec_cleanup(spapr->ov5_cas); 1351 spapr->ov5_cas = spapr_ovec_new(); 1352 } 1353 1354 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1355 1356 spapr_load_rtas(spapr, fdt, rtas_addr); 1357 1358 rc = fdt_pack(fdt); 1359 1360 /* Should only fail if we've built a corrupted tree */ 1361 assert(rc == 0); 1362 1363 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1364 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1365 fdt_totalsize(fdt), FDT_MAX_SIZE); 1366 exit(1); 1367 } 1368 1369 /* Load the fdt */ 1370 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1371 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1372 g_free(fdt); 1373 1374 /* Set up the entry state */ 1375 first_ppc_cpu = POWERPC_CPU(first_cpu); 1376 first_ppc_cpu->env.gpr[3] = fdt_addr; 1377 first_ppc_cpu->env.gpr[5] = 0; 1378 first_cpu->halted = 0; 1379 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1380 1381 spapr->cas_reboot = false; 1382 } 1383 1384 static void spapr_create_nvram(sPAPRMachineState *spapr) 1385 { 1386 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1387 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1388 1389 if (dinfo) { 1390 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1391 &error_fatal); 1392 } 1393 1394 qdev_init_nofail(dev); 1395 1396 spapr->nvram = (struct sPAPRNVRAM *)dev; 1397 } 1398 1399 static void spapr_rtc_create(sPAPRMachineState *spapr) 1400 { 1401 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); 1402 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), 1403 &error_fatal); 1404 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1405 &error_fatal); 1406 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1407 "date", &error_fatal); 1408 } 1409 1410 /* Returns whether we want to use VGA or not */ 1411 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1412 { 1413 switch (vga_interface_type) { 1414 case VGA_NONE: 1415 return false; 1416 case VGA_DEVICE: 1417 return true; 1418 case VGA_STD: 1419 case VGA_VIRTIO: 1420 return pci_vga_init(pci_bus) != NULL; 1421 default: 1422 error_setg(errp, 1423 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1424 return false; 1425 } 1426 } 1427 1428 static int spapr_post_load(void *opaque, int version_id) 1429 { 1430 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1431 int err = 0; 1432 1433 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { 1434 CPUState *cs; 1435 CPU_FOREACH(cs) { 1436 PowerPCCPU *cpu = POWERPC_CPU(cs); 1437 icp_resend(ICP(cpu->intc)); 1438 } 1439 } 1440 1441 /* In earlier versions, there was no separate qdev for the PAPR 1442 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1443 * So when migrating from those versions, poke the incoming offset 1444 * value into the RTC device */ 1445 if (version_id < 3) { 1446 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1447 } 1448 1449 return err; 1450 } 1451 1452 static bool version_before_3(void *opaque, int version_id) 1453 { 1454 return version_id < 3; 1455 } 1456 1457 static bool spapr_ov5_cas_needed(void *opaque) 1458 { 1459 sPAPRMachineState *spapr = opaque; 1460 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1461 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1462 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1463 bool cas_needed; 1464 1465 /* Prior to the introduction of sPAPROptionVector, we had two option 1466 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1467 * Both of these options encode machine topology into the device-tree 1468 * in such a way that the now-booted OS should still be able to interact 1469 * appropriately with QEMU regardless of what options were actually 1470 * negotiatied on the source side. 1471 * 1472 * As such, we can avoid migrating the CAS-negotiated options if these 1473 * are the only options available on the current machine/platform. 1474 * Since these are the only options available for pseries-2.7 and 1475 * earlier, this allows us to maintain old->new/new->old migration 1476 * compatibility. 1477 * 1478 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1479 * via default pseries-2.8 machines and explicit command-line parameters. 1480 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1481 * of the actual CAS-negotiated values to continue working properly. For 1482 * example, availability of memory unplug depends on knowing whether 1483 * OV5_HP_EVT was negotiated via CAS. 1484 * 1485 * Thus, for any cases where the set of available CAS-negotiatable 1486 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1487 * include the CAS-negotiated options in the migration stream. 1488 */ 1489 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1490 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1491 1492 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1493 * the mask itself since in the future it's possible "legacy" bits may be 1494 * removed via machine options, which could generate a false positive 1495 * that breaks migration. 1496 */ 1497 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1498 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1499 1500 spapr_ovec_cleanup(ov5_mask); 1501 spapr_ovec_cleanup(ov5_legacy); 1502 spapr_ovec_cleanup(ov5_removed); 1503 1504 return cas_needed; 1505 } 1506 1507 static const VMStateDescription vmstate_spapr_ov5_cas = { 1508 .name = "spapr_option_vector_ov5_cas", 1509 .version_id = 1, 1510 .minimum_version_id = 1, 1511 .needed = spapr_ov5_cas_needed, 1512 .fields = (VMStateField[]) { 1513 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1514 vmstate_spapr_ovec, sPAPROptionVector), 1515 VMSTATE_END_OF_LIST() 1516 }, 1517 }; 1518 1519 static bool spapr_patb_entry_needed(void *opaque) 1520 { 1521 sPAPRMachineState *spapr = opaque; 1522 1523 return !!spapr->patb_entry; 1524 } 1525 1526 static const VMStateDescription vmstate_spapr_patb_entry = { 1527 .name = "spapr_patb_entry", 1528 .version_id = 1, 1529 .minimum_version_id = 1, 1530 .needed = spapr_patb_entry_needed, 1531 .fields = (VMStateField[]) { 1532 VMSTATE_UINT64(patb_entry, sPAPRMachineState), 1533 VMSTATE_END_OF_LIST() 1534 }, 1535 }; 1536 1537 static const VMStateDescription vmstate_spapr = { 1538 .name = "spapr", 1539 .version_id = 3, 1540 .minimum_version_id = 1, 1541 .post_load = spapr_post_load, 1542 .fields = (VMStateField[]) { 1543 /* used to be @next_irq */ 1544 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1545 1546 /* RTC offset */ 1547 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1548 1549 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1550 VMSTATE_END_OF_LIST() 1551 }, 1552 .subsections = (const VMStateDescription*[]) { 1553 &vmstate_spapr_ov5_cas, 1554 &vmstate_spapr_patb_entry, 1555 NULL 1556 } 1557 }; 1558 1559 static int htab_save_setup(QEMUFile *f, void *opaque) 1560 { 1561 sPAPRMachineState *spapr = opaque; 1562 1563 /* "Iteration" header */ 1564 qemu_put_be32(f, spapr->htab_shift); 1565 1566 if (spapr->htab) { 1567 spapr->htab_save_index = 0; 1568 spapr->htab_first_pass = true; 1569 } else { 1570 assert(kvm_enabled()); 1571 } 1572 1573 1574 return 0; 1575 } 1576 1577 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1578 int64_t max_ns) 1579 { 1580 bool has_timeout = max_ns != -1; 1581 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1582 int index = spapr->htab_save_index; 1583 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1584 1585 assert(spapr->htab_first_pass); 1586 1587 do { 1588 int chunkstart; 1589 1590 /* Consume invalid HPTEs */ 1591 while ((index < htabslots) 1592 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1593 CLEAN_HPTE(HPTE(spapr->htab, index)); 1594 index++; 1595 } 1596 1597 /* Consume valid HPTEs */ 1598 chunkstart = index; 1599 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1600 && HPTE_VALID(HPTE(spapr->htab, index))) { 1601 CLEAN_HPTE(HPTE(spapr->htab, index)); 1602 index++; 1603 } 1604 1605 if (index > chunkstart) { 1606 int n_valid = index - chunkstart; 1607 1608 qemu_put_be32(f, chunkstart); 1609 qemu_put_be16(f, n_valid); 1610 qemu_put_be16(f, 0); 1611 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1612 HASH_PTE_SIZE_64 * n_valid); 1613 1614 if (has_timeout && 1615 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1616 break; 1617 } 1618 } 1619 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1620 1621 if (index >= htabslots) { 1622 assert(index == htabslots); 1623 index = 0; 1624 spapr->htab_first_pass = false; 1625 } 1626 spapr->htab_save_index = index; 1627 } 1628 1629 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1630 int64_t max_ns) 1631 { 1632 bool final = max_ns < 0; 1633 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1634 int examined = 0, sent = 0; 1635 int index = spapr->htab_save_index; 1636 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1637 1638 assert(!spapr->htab_first_pass); 1639 1640 do { 1641 int chunkstart, invalidstart; 1642 1643 /* Consume non-dirty HPTEs */ 1644 while ((index < htabslots) 1645 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1646 index++; 1647 examined++; 1648 } 1649 1650 chunkstart = index; 1651 /* Consume valid dirty HPTEs */ 1652 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1653 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1654 && HPTE_VALID(HPTE(spapr->htab, index))) { 1655 CLEAN_HPTE(HPTE(spapr->htab, index)); 1656 index++; 1657 examined++; 1658 } 1659 1660 invalidstart = index; 1661 /* Consume invalid dirty HPTEs */ 1662 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1663 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1664 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1665 CLEAN_HPTE(HPTE(spapr->htab, index)); 1666 index++; 1667 examined++; 1668 } 1669 1670 if (index > chunkstart) { 1671 int n_valid = invalidstart - chunkstart; 1672 int n_invalid = index - invalidstart; 1673 1674 qemu_put_be32(f, chunkstart); 1675 qemu_put_be16(f, n_valid); 1676 qemu_put_be16(f, n_invalid); 1677 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1678 HASH_PTE_SIZE_64 * n_valid); 1679 sent += index - chunkstart; 1680 1681 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1682 break; 1683 } 1684 } 1685 1686 if (examined >= htabslots) { 1687 break; 1688 } 1689 1690 if (index >= htabslots) { 1691 assert(index == htabslots); 1692 index = 0; 1693 } 1694 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1695 1696 if (index >= htabslots) { 1697 assert(index == htabslots); 1698 index = 0; 1699 } 1700 1701 spapr->htab_save_index = index; 1702 1703 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1704 } 1705 1706 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1707 #define MAX_KVM_BUF_SIZE 2048 1708 1709 static int htab_save_iterate(QEMUFile *f, void *opaque) 1710 { 1711 sPAPRMachineState *spapr = opaque; 1712 int fd; 1713 int rc = 0; 1714 1715 /* Iteration header */ 1716 qemu_put_be32(f, 0); 1717 1718 if (!spapr->htab) { 1719 assert(kvm_enabled()); 1720 1721 fd = get_htab_fd(spapr); 1722 if (fd < 0) { 1723 return fd; 1724 } 1725 1726 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1727 if (rc < 0) { 1728 return rc; 1729 } 1730 } else if (spapr->htab_first_pass) { 1731 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1732 } else { 1733 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1734 } 1735 1736 /* End marker */ 1737 qemu_put_be32(f, 0); 1738 qemu_put_be16(f, 0); 1739 qemu_put_be16(f, 0); 1740 1741 return rc; 1742 } 1743 1744 static int htab_save_complete(QEMUFile *f, void *opaque) 1745 { 1746 sPAPRMachineState *spapr = opaque; 1747 int fd; 1748 1749 /* Iteration header */ 1750 qemu_put_be32(f, 0); 1751 1752 if (!spapr->htab) { 1753 int rc; 1754 1755 assert(kvm_enabled()); 1756 1757 fd = get_htab_fd(spapr); 1758 if (fd < 0) { 1759 return fd; 1760 } 1761 1762 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 1763 if (rc < 0) { 1764 return rc; 1765 } 1766 } else { 1767 if (spapr->htab_first_pass) { 1768 htab_save_first_pass(f, spapr, -1); 1769 } 1770 htab_save_later_pass(f, spapr, -1); 1771 } 1772 1773 /* End marker */ 1774 qemu_put_be32(f, 0); 1775 qemu_put_be16(f, 0); 1776 qemu_put_be16(f, 0); 1777 1778 return 0; 1779 } 1780 1781 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1782 { 1783 sPAPRMachineState *spapr = opaque; 1784 uint32_t section_hdr; 1785 int fd = -1; 1786 1787 if (version_id < 1 || version_id > 1) { 1788 error_report("htab_load() bad version"); 1789 return -EINVAL; 1790 } 1791 1792 section_hdr = qemu_get_be32(f); 1793 1794 if (section_hdr) { 1795 Error *local_err = NULL; 1796 1797 /* First section gives the htab size */ 1798 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 1799 if (local_err) { 1800 error_report_err(local_err); 1801 return -EINVAL; 1802 } 1803 return 0; 1804 } 1805 1806 if (!spapr->htab) { 1807 assert(kvm_enabled()); 1808 1809 fd = kvmppc_get_htab_fd(true); 1810 if (fd < 0) { 1811 error_report("Unable to open fd to restore KVM hash table: %s", 1812 strerror(errno)); 1813 } 1814 } 1815 1816 while (true) { 1817 uint32_t index; 1818 uint16_t n_valid, n_invalid; 1819 1820 index = qemu_get_be32(f); 1821 n_valid = qemu_get_be16(f); 1822 n_invalid = qemu_get_be16(f); 1823 1824 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1825 /* End of Stream */ 1826 break; 1827 } 1828 1829 if ((index + n_valid + n_invalid) > 1830 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1831 /* Bad index in stream */ 1832 error_report( 1833 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 1834 index, n_valid, n_invalid, spapr->htab_shift); 1835 return -EINVAL; 1836 } 1837 1838 if (spapr->htab) { 1839 if (n_valid) { 1840 qemu_get_buffer(f, HPTE(spapr->htab, index), 1841 HASH_PTE_SIZE_64 * n_valid); 1842 } 1843 if (n_invalid) { 1844 memset(HPTE(spapr->htab, index + n_valid), 0, 1845 HASH_PTE_SIZE_64 * n_invalid); 1846 } 1847 } else { 1848 int rc; 1849 1850 assert(fd >= 0); 1851 1852 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1853 if (rc < 0) { 1854 return rc; 1855 } 1856 } 1857 } 1858 1859 if (!spapr->htab) { 1860 assert(fd >= 0); 1861 close(fd); 1862 } 1863 1864 return 0; 1865 } 1866 1867 static void htab_cleanup(void *opaque) 1868 { 1869 sPAPRMachineState *spapr = opaque; 1870 1871 close_htab_fd(spapr); 1872 } 1873 1874 static SaveVMHandlers savevm_htab_handlers = { 1875 .save_live_setup = htab_save_setup, 1876 .save_live_iterate = htab_save_iterate, 1877 .save_live_complete_precopy = htab_save_complete, 1878 .cleanup = htab_cleanup, 1879 .load_state = htab_load, 1880 }; 1881 1882 static void spapr_boot_set(void *opaque, const char *boot_device, 1883 Error **errp) 1884 { 1885 MachineState *machine = MACHINE(qdev_get_machine()); 1886 machine->boot_order = g_strdup(boot_device); 1887 } 1888 1889 /* 1890 * Reset routine for LMB DR devices. 1891 * 1892 * Unlike PCI DR devices, LMB DR devices explicitly register this reset 1893 * routine. Reset for PCI DR devices will be handled by PHB reset routine 1894 * when it walks all its children devices. LMB devices reset occurs 1895 * as part of spapr_ppc_reset(). 1896 */ 1897 static void spapr_drc_reset(void *opaque) 1898 { 1899 sPAPRDRConnector *drc = opaque; 1900 DeviceState *d = DEVICE(drc); 1901 1902 if (d) { 1903 device_reset(d); 1904 } 1905 } 1906 1907 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 1908 { 1909 MachineState *machine = MACHINE(spapr); 1910 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 1911 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 1912 int i; 1913 1914 for (i = 0; i < nr_lmbs; i++) { 1915 sPAPRDRConnector *drc; 1916 uint64_t addr; 1917 1918 addr = i * lmb_size + spapr->hotplug_memory.base; 1919 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB, 1920 addr/lmb_size); 1921 qemu_register_reset(spapr_drc_reset, drc); 1922 } 1923 } 1924 1925 /* 1926 * If RAM size, maxmem size and individual node mem sizes aren't aligned 1927 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 1928 * since we can't support such unaligned sizes with DRCONF_MEMORY. 1929 */ 1930 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 1931 { 1932 int i; 1933 1934 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1935 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 1936 " is not aligned to %llu MiB", 1937 machine->ram_size, 1938 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1939 return; 1940 } 1941 1942 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1943 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 1944 " is not aligned to %llu MiB", 1945 machine->ram_size, 1946 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1947 return; 1948 } 1949 1950 for (i = 0; i < nb_numa_nodes; i++) { 1951 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 1952 error_setg(errp, 1953 "Node %d memory size 0x%" PRIx64 1954 " is not aligned to %llu MiB", 1955 i, numa_info[i].node_mem, 1956 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1957 return; 1958 } 1959 } 1960 } 1961 1962 /* find cpu slot in machine->possible_cpus by core_id */ 1963 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 1964 { 1965 int index = id / smp_threads; 1966 1967 if (index >= ms->possible_cpus->len) { 1968 return NULL; 1969 } 1970 if (idx) { 1971 *idx = index; 1972 } 1973 return &ms->possible_cpus->cpus[index]; 1974 } 1975 1976 static void spapr_init_cpus(sPAPRMachineState *spapr) 1977 { 1978 MachineState *machine = MACHINE(spapr); 1979 MachineClass *mc = MACHINE_GET_CLASS(machine); 1980 char *type = spapr_get_cpu_core_type(machine->cpu_model); 1981 int smt = kvmppc_smt_threads(); 1982 const CPUArchIdList *possible_cpus; 1983 int boot_cores_nr = smp_cpus / smp_threads; 1984 int i; 1985 1986 if (!type) { 1987 error_report("Unable to find sPAPR CPU Core definition"); 1988 exit(1); 1989 } 1990 1991 possible_cpus = mc->possible_cpu_arch_ids(machine); 1992 if (mc->has_hotpluggable_cpus) { 1993 if (smp_cpus % smp_threads) { 1994 error_report("smp_cpus (%u) must be multiple of threads (%u)", 1995 smp_cpus, smp_threads); 1996 exit(1); 1997 } 1998 if (max_cpus % smp_threads) { 1999 error_report("max_cpus (%u) must be multiple of threads (%u)", 2000 max_cpus, smp_threads); 2001 exit(1); 2002 } 2003 } else { 2004 if (max_cpus != smp_cpus) { 2005 error_report("This machine version does not support CPU hotplug"); 2006 exit(1); 2007 } 2008 boot_cores_nr = possible_cpus->len; 2009 } 2010 2011 for (i = 0; i < possible_cpus->len; i++) { 2012 int core_id = i * smp_threads; 2013 2014 if (mc->has_hotpluggable_cpus) { 2015 sPAPRDRConnector *drc = 2016 spapr_dr_connector_new(OBJECT(spapr), 2017 SPAPR_DR_CONNECTOR_TYPE_CPU, 2018 (core_id / smp_threads) * smt); 2019 2020 qemu_register_reset(spapr_drc_reset, drc); 2021 } 2022 2023 if (i < boot_cores_nr) { 2024 Object *core = object_new(type); 2025 int nr_threads = smp_threads; 2026 2027 /* Handle the partially filled core for older machine types */ 2028 if ((i + 1) * smp_threads >= smp_cpus) { 2029 nr_threads = smp_cpus - i * smp_threads; 2030 } 2031 2032 object_property_set_int(core, nr_threads, "nr-threads", 2033 &error_fatal); 2034 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2035 &error_fatal); 2036 object_property_set_bool(core, true, "realized", &error_fatal); 2037 } 2038 } 2039 g_free(type); 2040 } 2041 2042 /* pSeries LPAR / sPAPR hardware init */ 2043 static void ppc_spapr_init(MachineState *machine) 2044 { 2045 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2046 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2047 const char *kernel_filename = machine->kernel_filename; 2048 const char *initrd_filename = machine->initrd_filename; 2049 PCIHostState *phb; 2050 int i; 2051 MemoryRegion *sysmem = get_system_memory(); 2052 MemoryRegion *ram = g_new(MemoryRegion, 1); 2053 MemoryRegion *rma_region; 2054 void *rma = NULL; 2055 hwaddr rma_alloc_size; 2056 hwaddr node0_size = spapr_node0_size(); 2057 long load_limit, fw_size; 2058 char *filename; 2059 2060 msi_nonbroken = true; 2061 2062 QLIST_INIT(&spapr->phbs); 2063 2064 /* Allocate RMA if necessary */ 2065 rma_alloc_size = kvmppc_alloc_rma(&rma); 2066 2067 if (rma_alloc_size == -1) { 2068 error_report("Unable to create RMA"); 2069 exit(1); 2070 } 2071 2072 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 2073 spapr->rma_size = rma_alloc_size; 2074 } else { 2075 spapr->rma_size = node0_size; 2076 2077 /* With KVM, we don't actually know whether KVM supports an 2078 * unbounded RMA (PR KVM) or is limited by the hash table size 2079 * (HV KVM using VRMA), so we always assume the latter 2080 * 2081 * In that case, we also limit the initial allocations for RTAS 2082 * etc... to 256M since we have no way to know what the VRMA size 2083 * is going to be as it depends on the size of the hash table 2084 * isn't determined yet. 2085 */ 2086 if (kvm_enabled()) { 2087 spapr->vrma_adjust = 1; 2088 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2089 } 2090 2091 /* Actually we don't support unbounded RMA anymore since we 2092 * added proper emulation of HV mode. The max we can get is 2093 * 16G which also happens to be what we configure for PAPR 2094 * mode so make sure we don't do anything bigger than that 2095 */ 2096 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2097 } 2098 2099 if (spapr->rma_size > node0_size) { 2100 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2101 spapr->rma_size); 2102 exit(1); 2103 } 2104 2105 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2106 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2107 2108 /* Set up Interrupt Controller before we create the VCPUs */ 2109 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal); 2110 2111 /* Set up containers for ibm,client-set-architecture negotiated options */ 2112 spapr->ov5 = spapr_ovec_new(); 2113 spapr->ov5_cas = spapr_ovec_new(); 2114 2115 if (smc->dr_lmb_enabled) { 2116 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2117 spapr_validate_node_memory(machine, &error_fatal); 2118 } 2119 2120 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2121 if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) { 2122 /* KVM and TCG always allow GTSE with radix... */ 2123 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2124 } 2125 /* ... but not with hash (currently). */ 2126 2127 /* advertise support for dedicated HP event source to guests */ 2128 if (spapr->use_hotplug_event_source) { 2129 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2130 } 2131 2132 /* init CPUs */ 2133 if (machine->cpu_model == NULL) { 2134 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu; 2135 } 2136 2137 ppc_cpu_parse_features(machine->cpu_model); 2138 2139 spapr_init_cpus(spapr); 2140 2141 if (kvm_enabled()) { 2142 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2143 kvmppc_enable_logical_ci_hcalls(); 2144 kvmppc_enable_set_mode_hcall(); 2145 2146 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2147 kvmppc_enable_clear_ref_mod_hcalls(); 2148 } 2149 2150 /* allocate RAM */ 2151 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2152 machine->ram_size); 2153 memory_region_add_subregion(sysmem, 0, ram); 2154 2155 if (rma_alloc_size && rma) { 2156 rma_region = g_new(MemoryRegion, 1); 2157 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 2158 rma_alloc_size, rma); 2159 vmstate_register_ram_global(rma_region); 2160 memory_region_add_subregion(sysmem, 0, rma_region); 2161 } 2162 2163 /* initialize hotplug memory address space */ 2164 if (machine->ram_size < machine->maxram_size) { 2165 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 2166 /* 2167 * Limit the number of hotpluggable memory slots to half the number 2168 * slots that KVM supports, leaving the other half for PCI and other 2169 * devices. However ensure that number of slots doesn't drop below 32. 2170 */ 2171 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2172 SPAPR_MAX_RAM_SLOTS; 2173 2174 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2175 max_memslots = SPAPR_MAX_RAM_SLOTS; 2176 } 2177 if (machine->ram_slots > max_memslots) { 2178 error_report("Specified number of memory slots %" 2179 PRIu64" exceeds max supported %d", 2180 machine->ram_slots, max_memslots); 2181 exit(1); 2182 } 2183 2184 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 2185 SPAPR_HOTPLUG_MEM_ALIGN); 2186 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 2187 "hotplug-memory", hotplug_mem_size); 2188 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 2189 &spapr->hotplug_memory.mr); 2190 } 2191 2192 if (smc->dr_lmb_enabled) { 2193 spapr_create_lmb_dr_connectors(spapr); 2194 } 2195 2196 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2197 if (!filename) { 2198 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2199 exit(1); 2200 } 2201 spapr->rtas_size = get_image_size(filename); 2202 if (spapr->rtas_size < 0) { 2203 error_report("Could not get size of LPAR rtas '%s'", filename); 2204 exit(1); 2205 } 2206 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2207 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2208 error_report("Could not load LPAR rtas '%s'", filename); 2209 exit(1); 2210 } 2211 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2212 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2213 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2214 exit(1); 2215 } 2216 g_free(filename); 2217 2218 /* Set up RTAS event infrastructure */ 2219 spapr_events_init(spapr); 2220 2221 /* Set up the RTC RTAS interfaces */ 2222 spapr_rtc_create(spapr); 2223 2224 /* Set up VIO bus */ 2225 spapr->vio_bus = spapr_vio_bus_init(); 2226 2227 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 2228 if (serial_hds[i]) { 2229 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 2230 } 2231 } 2232 2233 /* We always have at least the nvram device on VIO */ 2234 spapr_create_nvram(spapr); 2235 2236 /* Set up PCI */ 2237 spapr_pci_rtas_init(); 2238 2239 phb = spapr_create_phb(spapr, 0); 2240 2241 for (i = 0; i < nb_nics; i++) { 2242 NICInfo *nd = &nd_table[i]; 2243 2244 if (!nd->model) { 2245 nd->model = g_strdup("ibmveth"); 2246 } 2247 2248 if (strcmp(nd->model, "ibmveth") == 0) { 2249 spapr_vlan_create(spapr->vio_bus, nd); 2250 } else { 2251 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2252 } 2253 } 2254 2255 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2256 spapr_vscsi_create(spapr->vio_bus); 2257 } 2258 2259 /* Graphics */ 2260 if (spapr_vga_init(phb->bus, &error_fatal)) { 2261 spapr->has_graphics = true; 2262 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2263 } 2264 2265 if (machine->usb) { 2266 if (smc->use_ohci_by_default) { 2267 pci_create_simple(phb->bus, -1, "pci-ohci"); 2268 } else { 2269 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2270 } 2271 2272 if (spapr->has_graphics) { 2273 USBBus *usb_bus = usb_bus_find(-1); 2274 2275 usb_create_simple(usb_bus, "usb-kbd"); 2276 usb_create_simple(usb_bus, "usb-mouse"); 2277 } 2278 } 2279 2280 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 2281 error_report( 2282 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2283 MIN_RMA_SLOF); 2284 exit(1); 2285 } 2286 2287 if (kernel_filename) { 2288 uint64_t lowaddr = 0; 2289 2290 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2291 NULL, NULL, &lowaddr, NULL, 1, 2292 PPC_ELF_MACHINE, 0, 0); 2293 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2294 spapr->kernel_size = load_elf(kernel_filename, 2295 translate_kernel_address, NULL, NULL, 2296 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2297 0, 0); 2298 spapr->kernel_le = spapr->kernel_size > 0; 2299 } 2300 if (spapr->kernel_size < 0) { 2301 error_report("error loading %s: %s", kernel_filename, 2302 load_elf_strerror(spapr->kernel_size)); 2303 exit(1); 2304 } 2305 2306 /* load initrd */ 2307 if (initrd_filename) { 2308 /* Try to locate the initrd in the gap between the kernel 2309 * and the firmware. Add a bit of space just in case 2310 */ 2311 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2312 + 0x1ffff) & ~0xffff; 2313 spapr->initrd_size = load_image_targphys(initrd_filename, 2314 spapr->initrd_base, 2315 load_limit 2316 - spapr->initrd_base); 2317 if (spapr->initrd_size < 0) { 2318 error_report("could not load initial ram disk '%s'", 2319 initrd_filename); 2320 exit(1); 2321 } 2322 } 2323 } 2324 2325 if (bios_name == NULL) { 2326 bios_name = FW_FILE_NAME; 2327 } 2328 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2329 if (!filename) { 2330 error_report("Could not find LPAR firmware '%s'", bios_name); 2331 exit(1); 2332 } 2333 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2334 if (fw_size <= 0) { 2335 error_report("Could not load LPAR firmware '%s'", filename); 2336 exit(1); 2337 } 2338 g_free(filename); 2339 2340 /* FIXME: Should register things through the MachineState's qdev 2341 * interface, this is a legacy from the sPAPREnvironment structure 2342 * which predated MachineState but had a similar function */ 2343 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2344 register_savevm_live(NULL, "spapr/htab", -1, 1, 2345 &savevm_htab_handlers, spapr); 2346 2347 /* used by RTAS */ 2348 QTAILQ_INIT(&spapr->ccs_list); 2349 qemu_register_reset(spapr_ccs_reset_hook, spapr); 2350 2351 qemu_register_boot_set(spapr_boot_set, spapr); 2352 2353 if (kvm_enabled()) { 2354 /* to stop and start vmclock */ 2355 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2356 &spapr->tb); 2357 2358 kvmppc_spapr_enable_inkernel_multitce(); 2359 } 2360 } 2361 2362 static int spapr_kvm_type(const char *vm_type) 2363 { 2364 if (!vm_type) { 2365 return 0; 2366 } 2367 2368 if (!strcmp(vm_type, "HV")) { 2369 return 1; 2370 } 2371 2372 if (!strcmp(vm_type, "PR")) { 2373 return 2; 2374 } 2375 2376 error_report("Unknown kvm-type specified '%s'", vm_type); 2377 exit(1); 2378 } 2379 2380 /* 2381 * Implementation of an interface to adjust firmware path 2382 * for the bootindex property handling. 2383 */ 2384 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2385 DeviceState *dev) 2386 { 2387 #define CAST(type, obj, name) \ 2388 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2389 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2390 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2391 2392 if (d) { 2393 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2394 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2395 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2396 2397 if (spapr) { 2398 /* 2399 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2400 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2401 * in the top 16 bits of the 64-bit LUN 2402 */ 2403 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2404 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2405 (uint64_t)id << 48); 2406 } else if (virtio) { 2407 /* 2408 * We use SRP luns of the form 01000000 | (target << 8) | lun 2409 * in the top 32 bits of the 64-bit LUN 2410 * Note: the quote above is from SLOF and it is wrong, 2411 * the actual binding is: 2412 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2413 */ 2414 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2415 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2416 (uint64_t)id << 32); 2417 } else if (usb) { 2418 /* 2419 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2420 * in the top 32 bits of the 64-bit LUN 2421 */ 2422 unsigned usb_port = atoi(usb->port->path); 2423 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2424 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2425 (uint64_t)id << 32); 2426 } 2427 } 2428 2429 /* 2430 * SLOF probes the USB devices, and if it recognizes that the device is a 2431 * storage device, it changes its name to "storage" instead of "usb-host", 2432 * and additionally adds a child node for the SCSI LUN, so the correct 2433 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2434 */ 2435 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2436 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2437 if (usb_host_dev_is_scsi_storage(usbdev)) { 2438 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2439 } 2440 } 2441 2442 if (phb) { 2443 /* Replace "pci" with "pci@800000020000000" */ 2444 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2445 } 2446 2447 return NULL; 2448 } 2449 2450 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2451 { 2452 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2453 2454 return g_strdup(spapr->kvm_type); 2455 } 2456 2457 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2458 { 2459 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2460 2461 g_free(spapr->kvm_type); 2462 spapr->kvm_type = g_strdup(value); 2463 } 2464 2465 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2466 { 2467 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2468 2469 return spapr->use_hotplug_event_source; 2470 } 2471 2472 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2473 Error **errp) 2474 { 2475 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2476 2477 spapr->use_hotplug_event_source = value; 2478 } 2479 2480 static void spapr_machine_initfn(Object *obj) 2481 { 2482 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2483 2484 spapr->htab_fd = -1; 2485 spapr->use_hotplug_event_source = true; 2486 object_property_add_str(obj, "kvm-type", 2487 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2488 object_property_set_description(obj, "kvm-type", 2489 "Specifies the KVM virtualization mode (HV, PR)", 2490 NULL); 2491 object_property_add_bool(obj, "modern-hotplug-events", 2492 spapr_get_modern_hotplug_events, 2493 spapr_set_modern_hotplug_events, 2494 NULL); 2495 object_property_set_description(obj, "modern-hotplug-events", 2496 "Use dedicated hotplug event mechanism in" 2497 " place of standard EPOW events when possible" 2498 " (required for memory hot-unplug support)", 2499 NULL); 2500 } 2501 2502 static void spapr_machine_finalizefn(Object *obj) 2503 { 2504 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2505 2506 g_free(spapr->kvm_type); 2507 } 2508 2509 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 2510 { 2511 cpu_synchronize_state(cs); 2512 ppc_cpu_do_system_reset(cs); 2513 } 2514 2515 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2516 { 2517 CPUState *cs; 2518 2519 CPU_FOREACH(cs) { 2520 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 2521 } 2522 } 2523 2524 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2525 uint32_t node, bool dedicated_hp_event_source, 2526 Error **errp) 2527 { 2528 sPAPRDRConnector *drc; 2529 sPAPRDRConnectorClass *drck; 2530 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2531 int i, fdt_offset, fdt_size; 2532 void *fdt; 2533 uint64_t addr = addr_start; 2534 2535 for (i = 0; i < nr_lmbs; i++) { 2536 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2537 addr/SPAPR_MEMORY_BLOCK_SIZE); 2538 g_assert(drc); 2539 2540 fdt = create_device_tree(&fdt_size); 2541 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2542 SPAPR_MEMORY_BLOCK_SIZE); 2543 2544 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2545 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); 2546 addr += SPAPR_MEMORY_BLOCK_SIZE; 2547 if (!dev->hotplugged) { 2548 /* guests expect coldplugged LMBs to be pre-allocated */ 2549 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); 2550 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); 2551 } 2552 } 2553 /* send hotplug notification to the 2554 * guest only in case of hotplugged memory 2555 */ 2556 if (dev->hotplugged) { 2557 if (dedicated_hp_event_source) { 2558 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2559 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2560 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2561 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2562 nr_lmbs, 2563 drck->get_index(drc)); 2564 } else { 2565 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 2566 nr_lmbs); 2567 } 2568 } 2569 } 2570 2571 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2572 uint32_t node, Error **errp) 2573 { 2574 Error *local_err = NULL; 2575 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2576 PCDIMMDevice *dimm = PC_DIMM(dev); 2577 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2578 MemoryRegion *mr = ddc->get_memory_region(dimm); 2579 uint64_t align = memory_region_get_alignment(mr); 2580 uint64_t size = memory_region_size(mr); 2581 uint64_t addr; 2582 char *mem_dev; 2583 2584 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 2585 error_setg(&local_err, "Hotplugged memory size must be a multiple of " 2586 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); 2587 goto out; 2588 } 2589 2590 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); 2591 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { 2592 error_setg(&local_err, "Memory backend has bad page size. " 2593 "Use 'memory-backend-file' with correct mem-path."); 2594 goto out; 2595 } 2596 2597 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 2598 if (local_err) { 2599 goto out; 2600 } 2601 2602 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2603 if (local_err) { 2604 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2605 goto out; 2606 } 2607 2608 spapr_add_lmbs(dev, addr, size, node, 2609 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 2610 &error_abort); 2611 2612 out: 2613 error_propagate(errp, local_err); 2614 } 2615 2616 typedef struct sPAPRDIMMState { 2617 uint32_t nr_lmbs; 2618 } sPAPRDIMMState; 2619 2620 static void spapr_lmb_release(DeviceState *dev, void *opaque) 2621 { 2622 sPAPRDIMMState *ds = (sPAPRDIMMState *)opaque; 2623 HotplugHandler *hotplug_ctrl; 2624 2625 if (--ds->nr_lmbs) { 2626 return; 2627 } 2628 2629 g_free(ds); 2630 2631 /* 2632 * Now that all the LMBs have been removed by the guest, call the 2633 * pc-dimm unplug handler to cleanup up the pc-dimm device. 2634 */ 2635 hotplug_ctrl = qdev_get_hotplug_handler(dev); 2636 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2637 } 2638 2639 static void spapr_del_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2640 Error **errp) 2641 { 2642 sPAPRDRConnector *drc; 2643 sPAPRDRConnectorClass *drck; 2644 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 2645 int i; 2646 sPAPRDIMMState *ds = g_malloc0(sizeof(sPAPRDIMMState)); 2647 uint64_t addr = addr_start; 2648 2649 ds->nr_lmbs = nr_lmbs; 2650 for (i = 0; i < nr_lmbs; i++) { 2651 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2652 addr / SPAPR_MEMORY_BLOCK_SIZE); 2653 g_assert(drc); 2654 2655 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2656 drck->detach(drc, dev, spapr_lmb_release, ds, errp); 2657 addr += SPAPR_MEMORY_BLOCK_SIZE; 2658 } 2659 2660 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2661 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2662 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2663 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2664 nr_lmbs, 2665 drck->get_index(drc)); 2666 } 2667 2668 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2669 Error **errp) 2670 { 2671 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2672 PCDIMMDevice *dimm = PC_DIMM(dev); 2673 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2674 MemoryRegion *mr = ddc->get_memory_region(dimm); 2675 2676 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2677 object_unparent(OBJECT(dev)); 2678 } 2679 2680 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 2681 DeviceState *dev, Error **errp) 2682 { 2683 Error *local_err = NULL; 2684 PCDIMMDevice *dimm = PC_DIMM(dev); 2685 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2686 MemoryRegion *mr = ddc->get_memory_region(dimm); 2687 uint64_t size = memory_region_size(mr); 2688 uint64_t addr; 2689 2690 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2691 if (local_err) { 2692 goto out; 2693 } 2694 2695 spapr_del_lmbs(dev, addr, size, &error_abort); 2696 out: 2697 error_propagate(errp, local_err); 2698 } 2699 2700 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 2701 sPAPRMachineState *spapr) 2702 { 2703 PowerPCCPU *cpu = POWERPC_CPU(cs); 2704 DeviceClass *dc = DEVICE_GET_CLASS(cs); 2705 int id = ppc_get_vcpu_dt_id(cpu); 2706 void *fdt; 2707 int offset, fdt_size; 2708 char *nodename; 2709 2710 fdt = create_device_tree(&fdt_size); 2711 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 2712 offset = fdt_add_subnode(fdt, 0, nodename); 2713 2714 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 2715 g_free(nodename); 2716 2717 *fdt_offset = offset; 2718 return fdt; 2719 } 2720 2721 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2722 Error **errp) 2723 { 2724 MachineState *ms = MACHINE(qdev_get_machine()); 2725 CPUCore *cc = CPU_CORE(dev); 2726 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 2727 2728 core_slot->cpu = NULL; 2729 object_unparent(OBJECT(dev)); 2730 } 2731 2732 static void spapr_core_release(DeviceState *dev, void *opaque) 2733 { 2734 HotplugHandler *hotplug_ctrl; 2735 2736 hotplug_ctrl = qdev_get_hotplug_handler(dev); 2737 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2738 } 2739 2740 static 2741 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 2742 Error **errp) 2743 { 2744 int index; 2745 sPAPRDRConnector *drc; 2746 sPAPRDRConnectorClass *drck; 2747 Error *local_err = NULL; 2748 CPUCore *cc = CPU_CORE(dev); 2749 int smt = kvmppc_smt_threads(); 2750 2751 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 2752 error_setg(errp, "Unable to find CPU core with core-id: %d", 2753 cc->core_id); 2754 return; 2755 } 2756 if (index == 0) { 2757 error_setg(errp, "Boot CPU core may not be unplugged"); 2758 return; 2759 } 2760 2761 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt); 2762 g_assert(drc); 2763 2764 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2765 drck->detach(drc, dev, spapr_core_release, NULL, &local_err); 2766 if (local_err) { 2767 error_propagate(errp, local_err); 2768 return; 2769 } 2770 2771 spapr_hotplug_req_remove_by_index(drc); 2772 } 2773 2774 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2775 Error **errp) 2776 { 2777 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 2778 MachineClass *mc = MACHINE_GET_CLASS(spapr); 2779 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 2780 CPUCore *cc = CPU_CORE(dev); 2781 CPUState *cs = CPU(core->threads); 2782 sPAPRDRConnector *drc; 2783 Error *local_err = NULL; 2784 void *fdt = NULL; 2785 int fdt_offset = 0; 2786 int smt = kvmppc_smt_threads(); 2787 CPUArchId *core_slot; 2788 int index; 2789 2790 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 2791 if (!core_slot) { 2792 error_setg(errp, "Unable to find CPU core with core-id: %d", 2793 cc->core_id); 2794 return; 2795 } 2796 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt); 2797 2798 g_assert(drc || !mc->has_hotpluggable_cpus); 2799 2800 /* 2801 * Setup CPU DT entries only for hotplugged CPUs. For boot time or 2802 * coldplugged CPUs DT entries are setup in spapr_build_fdt(). 2803 */ 2804 if (dev->hotplugged) { 2805 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 2806 } 2807 2808 if (drc) { 2809 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2810 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err); 2811 if (local_err) { 2812 g_free(fdt); 2813 error_propagate(errp, local_err); 2814 return; 2815 } 2816 } 2817 2818 if (dev->hotplugged) { 2819 /* 2820 * Send hotplug notification interrupt to the guest only in case 2821 * of hotplugged CPUs. 2822 */ 2823 spapr_hotplug_req_add_by_index(drc); 2824 } else { 2825 /* 2826 * Set the right DRC states for cold plugged CPU. 2827 */ 2828 if (drc) { 2829 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2830 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); 2831 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); 2832 } 2833 } 2834 core_slot->cpu = OBJECT(dev); 2835 } 2836 2837 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2838 Error **errp) 2839 { 2840 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 2841 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 2842 Error *local_err = NULL; 2843 CPUCore *cc = CPU_CORE(dev); 2844 sPAPRCPUCore *sc = SPAPR_CPU_CORE(dev); 2845 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model); 2846 const char *type = object_get_typename(OBJECT(dev)); 2847 CPUArchId *core_slot; 2848 int node_id; 2849 int index; 2850 2851 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 2852 error_setg(&local_err, "CPU hotplug not supported for this machine"); 2853 goto out; 2854 } 2855 2856 if (strcmp(base_core_type, type)) { 2857 error_setg(&local_err, "CPU core type should be %s", base_core_type); 2858 goto out; 2859 } 2860 2861 if (cc->core_id % smp_threads) { 2862 error_setg(&local_err, "invalid core id %d", cc->core_id); 2863 goto out; 2864 } 2865 2866 if (cc->nr_threads != smp_threads) { 2867 error_setg(errp, "invalid nr-threads %d, must be %d", 2868 cc->nr_threads, smp_threads); 2869 return; 2870 } 2871 2872 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 2873 if (!core_slot) { 2874 error_setg(&local_err, "core id %d out of range", cc->core_id); 2875 goto out; 2876 } 2877 2878 if (core_slot->cpu) { 2879 error_setg(&local_err, "core %d already populated", cc->core_id); 2880 goto out; 2881 } 2882 2883 node_id = core_slot->props.node_id; 2884 if (!core_slot->props.has_node_id) { 2885 /* by default CPUState::numa_node was 0 if it's not set via CLI 2886 * keep it this way for now but in future we probably should 2887 * refuse to start up with incomplete numa mapping */ 2888 node_id = 0; 2889 } 2890 if (sc->node_id == CPU_UNSET_NUMA_NODE_ID) { 2891 sc->node_id = node_id; 2892 } else if (sc->node_id != node_id) { 2893 error_setg(&local_err, "node-id %d must match numa node specified" 2894 "with -numa option for cpu-index %d", sc->node_id, cc->core_id); 2895 goto out; 2896 } 2897 2898 out: 2899 g_free(base_core_type); 2900 error_propagate(errp, local_err); 2901 } 2902 2903 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 2904 DeviceState *dev, Error **errp) 2905 { 2906 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 2907 2908 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2909 int node; 2910 2911 if (!smc->dr_lmb_enabled) { 2912 error_setg(errp, "Memory hotplug not supported for this machine"); 2913 return; 2914 } 2915 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 2916 if (*errp) { 2917 return; 2918 } 2919 if (node < 0 || node >= MAX_NODES) { 2920 error_setg(errp, "Invaild node %d", node); 2921 return; 2922 } 2923 2924 /* 2925 * Currently PowerPC kernel doesn't allow hot-adding memory to 2926 * memory-less node, but instead will silently add the memory 2927 * to the first node that has some memory. This causes two 2928 * unexpected behaviours for the user. 2929 * 2930 * - Memory gets hotplugged to a different node than what the user 2931 * specified. 2932 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 2933 * to memory-less node, a reboot will set things accordingly 2934 * and the previously hotplugged memory now ends in the right node. 2935 * This appears as if some memory moved from one node to another. 2936 * 2937 * So until kernel starts supporting memory hotplug to memory-less 2938 * nodes, just prevent such attempts upfront in QEMU. 2939 */ 2940 if (nb_numa_nodes && !numa_info[node].node_mem) { 2941 error_setg(errp, "Can't hotplug memory to memory-less node %d", 2942 node); 2943 return; 2944 } 2945 2946 spapr_memory_plug(hotplug_dev, dev, node, errp); 2947 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2948 spapr_core_plug(hotplug_dev, dev, errp); 2949 } 2950 } 2951 2952 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 2953 DeviceState *dev, Error **errp) 2954 { 2955 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 2956 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 2957 2958 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2959 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 2960 spapr_memory_unplug(hotplug_dev, dev, errp); 2961 } else { 2962 error_setg(errp, "Memory hot unplug not supported for this guest"); 2963 } 2964 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2965 if (!mc->has_hotpluggable_cpus) { 2966 error_setg(errp, "CPU hot unplug not supported on this machine"); 2967 return; 2968 } 2969 spapr_core_unplug(hotplug_dev, dev, errp); 2970 } 2971 } 2972 2973 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 2974 DeviceState *dev, Error **errp) 2975 { 2976 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 2977 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 2978 2979 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2980 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 2981 spapr_memory_unplug_request(hotplug_dev, dev, errp); 2982 } else { 2983 /* NOTE: this means there is a window after guest reset, prior to 2984 * CAS negotiation, where unplug requests will fail due to the 2985 * capability not being detected yet. This is a bit different than 2986 * the case with PCI unplug, where the events will be queued and 2987 * eventually handled by the guest after boot 2988 */ 2989 error_setg(errp, "Memory hot unplug not supported for this guest"); 2990 } 2991 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2992 if (!mc->has_hotpluggable_cpus) { 2993 error_setg(errp, "CPU hot unplug not supported on this machine"); 2994 return; 2995 } 2996 spapr_core_unplug_request(hotplug_dev, dev, errp); 2997 } 2998 } 2999 3000 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 3001 DeviceState *dev, Error **errp) 3002 { 3003 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3004 spapr_core_pre_plug(hotplug_dev, dev, errp); 3005 } 3006 } 3007 3008 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 3009 DeviceState *dev) 3010 { 3011 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3012 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3013 return HOTPLUG_HANDLER(machine); 3014 } 3015 return NULL; 3016 } 3017 3018 static CpuInstanceProperties 3019 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 3020 { 3021 CPUArchId *core_slot; 3022 MachineClass *mc = MACHINE_GET_CLASS(machine); 3023 3024 /* make sure possible_cpu are intialized */ 3025 mc->possible_cpu_arch_ids(machine); 3026 /* get CPU core slot containing thread that matches cpu_index */ 3027 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 3028 assert(core_slot); 3029 return core_slot->props; 3030 } 3031 3032 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 3033 { 3034 int i; 3035 int spapr_max_cores = max_cpus / smp_threads; 3036 MachineClass *mc = MACHINE_GET_CLASS(machine); 3037 3038 if (!mc->has_hotpluggable_cpus) { 3039 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 3040 } 3041 if (machine->possible_cpus) { 3042 assert(machine->possible_cpus->len == spapr_max_cores); 3043 return machine->possible_cpus; 3044 } 3045 3046 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 3047 sizeof(CPUArchId) * spapr_max_cores); 3048 machine->possible_cpus->len = spapr_max_cores; 3049 for (i = 0; i < machine->possible_cpus->len; i++) { 3050 int core_id = i * smp_threads; 3051 3052 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 3053 machine->possible_cpus->cpus[i].arch_id = core_id; 3054 machine->possible_cpus->cpus[i].props.has_core_id = true; 3055 machine->possible_cpus->cpus[i].props.core_id = core_id; 3056 3057 /* default distribution of CPUs over NUMA nodes */ 3058 if (nb_numa_nodes) { 3059 /* preset values but do not enable them i.e. 'has_node_id = false', 3060 * numa init code will enable them later if manual mapping wasn't 3061 * present on CLI */ 3062 machine->possible_cpus->cpus[i].props.node_id = 3063 core_id / smp_threads / smp_cores % nb_numa_nodes; 3064 } 3065 } 3066 return machine->possible_cpus; 3067 } 3068 3069 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 3070 uint64_t *buid, hwaddr *pio, 3071 hwaddr *mmio32, hwaddr *mmio64, 3072 unsigned n_dma, uint32_t *liobns, Error **errp) 3073 { 3074 /* 3075 * New-style PHB window placement. 3076 * 3077 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 3078 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 3079 * windows. 3080 * 3081 * Some guest kernels can't work with MMIO windows above 1<<46 3082 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 3083 * 3084 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 3085 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 3086 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 3087 * 1TiB 64-bit MMIO windows for each PHB. 3088 */ 3089 const uint64_t base_buid = 0x800000020000000ULL; 3090 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 3091 SPAPR_PCI_MEM64_WIN_SIZE - 1) 3092 int i; 3093 3094 /* Sanity check natural alignments */ 3095 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3096 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3097 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 3098 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 3099 /* Sanity check bounds */ 3100 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 3101 SPAPR_PCI_MEM32_WIN_SIZE); 3102 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 3103 SPAPR_PCI_MEM64_WIN_SIZE); 3104 3105 if (index >= SPAPR_MAX_PHBS) { 3106 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 3107 SPAPR_MAX_PHBS - 1); 3108 return; 3109 } 3110 3111 *buid = base_buid + index; 3112 for (i = 0; i < n_dma; ++i) { 3113 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3114 } 3115 3116 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 3117 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 3118 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 3119 } 3120 3121 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 3122 { 3123 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3124 3125 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 3126 } 3127 3128 static void spapr_ics_resend(XICSFabric *dev) 3129 { 3130 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3131 3132 ics_resend(spapr->ics); 3133 } 3134 3135 static ICPState *spapr_icp_get(XICSFabric *xi, int cpu_dt_id) 3136 { 3137 PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id); 3138 3139 return cpu ? ICP(cpu->intc) : NULL; 3140 } 3141 3142 static void spapr_pic_print_info(InterruptStatsProvider *obj, 3143 Monitor *mon) 3144 { 3145 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3146 CPUState *cs; 3147 3148 CPU_FOREACH(cs) { 3149 PowerPCCPU *cpu = POWERPC_CPU(cs); 3150 3151 icp_pic_print_info(ICP(cpu->intc), mon); 3152 } 3153 3154 ics_pic_print_info(spapr->ics, mon); 3155 } 3156 3157 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3158 { 3159 MachineClass *mc = MACHINE_CLASS(oc); 3160 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3161 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3162 NMIClass *nc = NMI_CLASS(oc); 3163 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3164 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3165 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3166 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 3167 3168 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3169 3170 /* 3171 * We set up the default / latest behaviour here. The class_init 3172 * functions for the specific versioned machine types can override 3173 * these details for backwards compatibility 3174 */ 3175 mc->init = ppc_spapr_init; 3176 mc->reset = ppc_spapr_reset; 3177 mc->block_default_type = IF_SCSI; 3178 mc->max_cpus = 1024; 3179 mc->no_parallel = 1; 3180 mc->default_boot_order = ""; 3181 mc->default_ram_size = 512 * M_BYTE; 3182 mc->kvm_type = spapr_kvm_type; 3183 mc->has_dynamic_sysbus = true; 3184 mc->pci_allow_0_address = true; 3185 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3186 hc->pre_plug = spapr_machine_device_pre_plug; 3187 hc->plug = spapr_machine_device_plug; 3188 hc->unplug = spapr_machine_device_unplug; 3189 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 3190 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3191 hc->unplug_request = spapr_machine_device_unplug_request; 3192 3193 smc->dr_lmb_enabled = true; 3194 smc->tcg_default_cpu = "POWER8"; 3195 mc->has_hotpluggable_cpus = true; 3196 fwc->get_dev_path = spapr_get_fw_dev_path; 3197 nc->nmi_monitor_handler = spapr_nmi; 3198 smc->phb_placement = spapr_phb_placement; 3199 vhc->hypercall = emulate_spapr_hypercall; 3200 vhc->hpt_mask = spapr_hpt_mask; 3201 vhc->map_hptes = spapr_map_hptes; 3202 vhc->unmap_hptes = spapr_unmap_hptes; 3203 vhc->store_hpte = spapr_store_hpte; 3204 vhc->get_patbe = spapr_get_patbe; 3205 xic->ics_get = spapr_ics_get; 3206 xic->ics_resend = spapr_ics_resend; 3207 xic->icp_get = spapr_icp_get; 3208 ispc->print_info = spapr_pic_print_info; 3209 /* Force NUMA node memory size to be a multiple of 3210 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 3211 * in which LMBs are represented and hot-added 3212 */ 3213 mc->numa_mem_align_shift = 28; 3214 } 3215 3216 static const TypeInfo spapr_machine_info = { 3217 .name = TYPE_SPAPR_MACHINE, 3218 .parent = TYPE_MACHINE, 3219 .abstract = true, 3220 .instance_size = sizeof(sPAPRMachineState), 3221 .instance_init = spapr_machine_initfn, 3222 .instance_finalize = spapr_machine_finalizefn, 3223 .class_size = sizeof(sPAPRMachineClass), 3224 .class_init = spapr_machine_class_init, 3225 .interfaces = (InterfaceInfo[]) { 3226 { TYPE_FW_PATH_PROVIDER }, 3227 { TYPE_NMI }, 3228 { TYPE_HOTPLUG_HANDLER }, 3229 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 3230 { TYPE_XICS_FABRIC }, 3231 { TYPE_INTERRUPT_STATS_PROVIDER }, 3232 { } 3233 }, 3234 }; 3235 3236 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 3237 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 3238 void *data) \ 3239 { \ 3240 MachineClass *mc = MACHINE_CLASS(oc); \ 3241 spapr_machine_##suffix##_class_options(mc); \ 3242 if (latest) { \ 3243 mc->alias = "pseries"; \ 3244 mc->is_default = 1; \ 3245 } \ 3246 } \ 3247 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 3248 { \ 3249 MachineState *machine = MACHINE(obj); \ 3250 spapr_machine_##suffix##_instance_options(machine); \ 3251 } \ 3252 static const TypeInfo spapr_machine_##suffix##_info = { \ 3253 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 3254 .parent = TYPE_SPAPR_MACHINE, \ 3255 .class_init = spapr_machine_##suffix##_class_init, \ 3256 .instance_init = spapr_machine_##suffix##_instance_init, \ 3257 }; \ 3258 static void spapr_machine_register_##suffix(void) \ 3259 { \ 3260 type_register(&spapr_machine_##suffix##_info); \ 3261 } \ 3262 type_init(spapr_machine_register_##suffix) 3263 3264 /* 3265 * pseries-2.10 3266 */ 3267 static void spapr_machine_2_10_instance_options(MachineState *machine) 3268 { 3269 } 3270 3271 static void spapr_machine_2_10_class_options(MachineClass *mc) 3272 { 3273 /* Defaults for the latest behaviour inherited from the base class */ 3274 } 3275 3276 DEFINE_SPAPR_MACHINE(2_10, "2.10", true); 3277 3278 /* 3279 * pseries-2.9 3280 */ 3281 #define SPAPR_COMPAT_2_9 \ 3282 HW_COMPAT_2_9 3283 3284 static void spapr_machine_2_9_instance_options(MachineState *machine) 3285 { 3286 spapr_machine_2_10_instance_options(machine); 3287 } 3288 3289 static void spapr_machine_2_9_class_options(MachineClass *mc) 3290 { 3291 spapr_machine_2_10_class_options(mc); 3292 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); 3293 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 3294 } 3295 3296 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 3297 3298 /* 3299 * pseries-2.8 3300 */ 3301 #define SPAPR_COMPAT_2_8 \ 3302 HW_COMPAT_2_8 \ 3303 { \ 3304 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3305 .property = "pcie-extended-configuration-space", \ 3306 .value = "off", \ 3307 }, 3308 3309 static void spapr_machine_2_8_instance_options(MachineState *machine) 3310 { 3311 spapr_machine_2_9_instance_options(machine); 3312 } 3313 3314 static void spapr_machine_2_8_class_options(MachineClass *mc) 3315 { 3316 spapr_machine_2_9_class_options(mc); 3317 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 3318 mc->numa_mem_align_shift = 23; 3319 } 3320 3321 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 3322 3323 /* 3324 * pseries-2.7 3325 */ 3326 #define SPAPR_COMPAT_2_7 \ 3327 HW_COMPAT_2_7 \ 3328 { \ 3329 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3330 .property = "mem_win_size", \ 3331 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 3332 }, \ 3333 { \ 3334 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3335 .property = "mem64_win_size", \ 3336 .value = "0", \ 3337 }, \ 3338 { \ 3339 .driver = TYPE_POWERPC_CPU, \ 3340 .property = "pre-2.8-migration", \ 3341 .value = "on", \ 3342 }, \ 3343 { \ 3344 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3345 .property = "pre-2.8-migration", \ 3346 .value = "on", \ 3347 }, 3348 3349 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 3350 uint64_t *buid, hwaddr *pio, 3351 hwaddr *mmio32, hwaddr *mmio64, 3352 unsigned n_dma, uint32_t *liobns, Error **errp) 3353 { 3354 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 3355 const uint64_t base_buid = 0x800000020000000ULL; 3356 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 3357 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 3358 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 3359 const uint32_t max_index = 255; 3360 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 3361 3362 uint64_t ram_top = MACHINE(spapr)->ram_size; 3363 hwaddr phb0_base, phb_base; 3364 int i; 3365 3366 /* Do we have hotpluggable memory? */ 3367 if (MACHINE(spapr)->maxram_size > ram_top) { 3368 /* Can't just use maxram_size, because there may be an 3369 * alignment gap between normal and hotpluggable memory 3370 * regions */ 3371 ram_top = spapr->hotplug_memory.base + 3372 memory_region_size(&spapr->hotplug_memory.mr); 3373 } 3374 3375 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 3376 3377 if (index > max_index) { 3378 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 3379 max_index); 3380 return; 3381 } 3382 3383 *buid = base_buid + index; 3384 for (i = 0; i < n_dma; ++i) { 3385 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3386 } 3387 3388 phb_base = phb0_base + index * phb_spacing; 3389 *pio = phb_base + pio_offset; 3390 *mmio32 = phb_base + mmio_offset; 3391 /* 3392 * We don't set the 64-bit MMIO window, relying on the PHB's 3393 * fallback behaviour of automatically splitting a large "32-bit" 3394 * window into contiguous 32-bit and 64-bit windows 3395 */ 3396 } 3397 3398 static void spapr_machine_2_7_instance_options(MachineState *machine) 3399 { 3400 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 3401 3402 spapr_machine_2_8_instance_options(machine); 3403 spapr->use_hotplug_event_source = false; 3404 } 3405 3406 static void spapr_machine_2_7_class_options(MachineClass *mc) 3407 { 3408 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3409 3410 spapr_machine_2_8_class_options(mc); 3411 smc->tcg_default_cpu = "POWER7"; 3412 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 3413 smc->phb_placement = phb_placement_2_7; 3414 } 3415 3416 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 3417 3418 /* 3419 * pseries-2.6 3420 */ 3421 #define SPAPR_COMPAT_2_6 \ 3422 HW_COMPAT_2_6 \ 3423 { \ 3424 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3425 .property = "ddw",\ 3426 .value = stringify(off),\ 3427 }, 3428 3429 static void spapr_machine_2_6_instance_options(MachineState *machine) 3430 { 3431 spapr_machine_2_7_instance_options(machine); 3432 } 3433 3434 static void spapr_machine_2_6_class_options(MachineClass *mc) 3435 { 3436 spapr_machine_2_7_class_options(mc); 3437 mc->has_hotpluggable_cpus = false; 3438 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 3439 } 3440 3441 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 3442 3443 /* 3444 * pseries-2.5 3445 */ 3446 #define SPAPR_COMPAT_2_5 \ 3447 HW_COMPAT_2_5 \ 3448 { \ 3449 .driver = "spapr-vlan", \ 3450 .property = "use-rx-buffer-pools", \ 3451 .value = "off", \ 3452 }, 3453 3454 static void spapr_machine_2_5_instance_options(MachineState *machine) 3455 { 3456 spapr_machine_2_6_instance_options(machine); 3457 } 3458 3459 static void spapr_machine_2_5_class_options(MachineClass *mc) 3460 { 3461 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3462 3463 spapr_machine_2_6_class_options(mc); 3464 smc->use_ohci_by_default = true; 3465 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 3466 } 3467 3468 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 3469 3470 /* 3471 * pseries-2.4 3472 */ 3473 #define SPAPR_COMPAT_2_4 \ 3474 HW_COMPAT_2_4 3475 3476 static void spapr_machine_2_4_instance_options(MachineState *machine) 3477 { 3478 spapr_machine_2_5_instance_options(machine); 3479 } 3480 3481 static void spapr_machine_2_4_class_options(MachineClass *mc) 3482 { 3483 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3484 3485 spapr_machine_2_5_class_options(mc); 3486 smc->dr_lmb_enabled = false; 3487 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 3488 } 3489 3490 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 3491 3492 /* 3493 * pseries-2.3 3494 */ 3495 #define SPAPR_COMPAT_2_3 \ 3496 HW_COMPAT_2_3 \ 3497 {\ 3498 .driver = "spapr-pci-host-bridge",\ 3499 .property = "dynamic-reconfiguration",\ 3500 .value = "off",\ 3501 }, 3502 3503 static void spapr_machine_2_3_instance_options(MachineState *machine) 3504 { 3505 spapr_machine_2_4_instance_options(machine); 3506 savevm_skip_section_footers(); 3507 global_state_set_optional(); 3508 savevm_skip_configuration(); 3509 } 3510 3511 static void spapr_machine_2_3_class_options(MachineClass *mc) 3512 { 3513 spapr_machine_2_4_class_options(mc); 3514 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 3515 } 3516 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 3517 3518 /* 3519 * pseries-2.2 3520 */ 3521 3522 #define SPAPR_COMPAT_2_2 \ 3523 HW_COMPAT_2_2 \ 3524 {\ 3525 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3526 .property = "mem_win_size",\ 3527 .value = "0x20000000",\ 3528 }, 3529 3530 static void spapr_machine_2_2_instance_options(MachineState *machine) 3531 { 3532 spapr_machine_2_3_instance_options(machine); 3533 machine->suppress_vmdesc = true; 3534 } 3535 3536 static void spapr_machine_2_2_class_options(MachineClass *mc) 3537 { 3538 spapr_machine_2_3_class_options(mc); 3539 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 3540 } 3541 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 3542 3543 /* 3544 * pseries-2.1 3545 */ 3546 #define SPAPR_COMPAT_2_1 \ 3547 HW_COMPAT_2_1 3548 3549 static void spapr_machine_2_1_instance_options(MachineState *machine) 3550 { 3551 spapr_machine_2_2_instance_options(machine); 3552 } 3553 3554 static void spapr_machine_2_1_class_options(MachineClass *mc) 3555 { 3556 spapr_machine_2_2_class_options(mc); 3557 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 3558 } 3559 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 3560 3561 static void spapr_machine_register_types(void) 3562 { 3563 type_register_static(&spapr_machine_info); 3564 } 3565 3566 type_init(spapr_machine_register_types) 3567