1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu/datadir.h" 29 #include "qemu/memalign.h" 30 #include "qapi/error.h" 31 #include "qapi/qapi-events-machine.h" 32 #include "qapi/qapi-events-qdev.h" 33 #include "qapi/visitor.h" 34 #include "sysemu/sysemu.h" 35 #include "sysemu/hostmem.h" 36 #include "sysemu/numa.h" 37 #include "sysemu/qtest.h" 38 #include "sysemu/reset.h" 39 #include "sysemu/runstate.h" 40 #include "qemu/log.h" 41 #include "hw/fw-path-provider.h" 42 #include "elf.h" 43 #include "net/net.h" 44 #include "sysemu/device_tree.h" 45 #include "sysemu/cpus.h" 46 #include "sysemu/hw_accel.h" 47 #include "kvm_ppc.h" 48 #include "migration/misc.h" 49 #include "migration/qemu-file-types.h" 50 #include "migration/global_state.h" 51 #include "migration/register.h" 52 #include "migration/blocker.h" 53 #include "mmu-hash64.h" 54 #include "mmu-book3s-v3.h" 55 #include "cpu-models.h" 56 #include "hw/core/cpu.h" 57 58 #include "hw/ppc/ppc.h" 59 #include "hw/loader.h" 60 61 #include "hw/ppc/fdt.h" 62 #include "hw/ppc/spapr.h" 63 #include "hw/ppc/spapr_vio.h" 64 #include "hw/qdev-properties.h" 65 #include "hw/pci-host/spapr.h" 66 #include "hw/pci/msi.h" 67 68 #include "hw/pci/pci.h" 69 #include "hw/scsi/scsi.h" 70 #include "hw/virtio/virtio-scsi.h" 71 #include "hw/virtio/vhost-scsi-common.h" 72 73 #include "exec/ram_addr.h" 74 #include "hw/usb.h" 75 #include "qemu/config-file.h" 76 #include "qemu/error-report.h" 77 #include "trace.h" 78 #include "hw/nmi.h" 79 #include "hw/intc/intc.h" 80 81 #include "hw/ppc/spapr_cpu_core.h" 82 #include "hw/mem/memory-device.h" 83 #include "hw/ppc/spapr_tpm_proxy.h" 84 #include "hw/ppc/spapr_nvdimm.h" 85 #include "hw/ppc/spapr_numa.h" 86 #include "hw/ppc/pef.h" 87 88 #include "monitor/monitor.h" 89 90 #include <libfdt.h> 91 92 /* SLOF memory layout: 93 * 94 * SLOF raw image loaded at 0, copies its romfs right below the flat 95 * device-tree, then position SLOF itself 31M below that 96 * 97 * So we set FW_OVERHEAD to 40MB which should account for all of that 98 * and more 99 * 100 * We load our kernel at 4M, leaving space for SLOF initial image 101 */ 102 #define FDT_MAX_ADDR 0x80000000 /* FDT must stay below that */ 103 #define FW_MAX_SIZE 0x400000 104 #define FW_FILE_NAME "slof.bin" 105 #define FW_FILE_NAME_VOF "vof.bin" 106 #define FW_OVERHEAD 0x2800000 107 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 108 109 #define MIN_RMA_SLOF (128 * MiB) 110 111 #define PHANDLE_INTC 0x00001111 112 113 /* These two functions implement the VCPU id numbering: one to compute them 114 * all and one to identify thread 0 of a VCORE. Any change to the first one 115 * is likely to have an impact on the second one, so let's keep them close. 116 */ 117 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 118 { 119 MachineState *ms = MACHINE(spapr); 120 unsigned int smp_threads = ms->smp.threads; 121 122 assert(spapr->vsmt); 123 return 124 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 125 } 126 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 127 PowerPCCPU *cpu) 128 { 129 assert(spapr->vsmt); 130 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 131 } 132 133 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 134 { 135 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 136 * and newer QEMUs don't even have them. In both cases, we don't want 137 * to send anything on the wire. 138 */ 139 return false; 140 } 141 142 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 143 .name = "icp/server", 144 .version_id = 1, 145 .minimum_version_id = 1, 146 .needed = pre_2_10_vmstate_dummy_icp_needed, 147 .fields = (VMStateField[]) { 148 VMSTATE_UNUSED(4), /* uint32_t xirr */ 149 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 150 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 151 VMSTATE_END_OF_LIST() 152 }, 153 }; 154 155 static void pre_2_10_vmstate_register_dummy_icp(int i) 156 { 157 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 158 (void *)(uintptr_t) i); 159 } 160 161 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 162 { 163 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 164 (void *)(uintptr_t) i); 165 } 166 167 int spapr_max_server_number(SpaprMachineState *spapr) 168 { 169 MachineState *ms = MACHINE(spapr); 170 171 assert(spapr->vsmt); 172 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 173 } 174 175 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 176 int smt_threads) 177 { 178 int i, ret = 0; 179 uint32_t servers_prop[smt_threads]; 180 uint32_t gservers_prop[smt_threads * 2]; 181 int index = spapr_get_vcpu_id(cpu); 182 183 if (cpu->compat_pvr) { 184 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 185 if (ret < 0) { 186 return ret; 187 } 188 } 189 190 /* Build interrupt servers and gservers properties */ 191 for (i = 0; i < smt_threads; i++) { 192 servers_prop[i] = cpu_to_be32(index + i); 193 /* Hack, direct the group queues back to cpu 0 */ 194 gservers_prop[i*2] = cpu_to_be32(index + i); 195 gservers_prop[i*2 + 1] = 0; 196 } 197 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 198 servers_prop, sizeof(servers_prop)); 199 if (ret < 0) { 200 return ret; 201 } 202 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 203 gservers_prop, sizeof(gservers_prop)); 204 205 return ret; 206 } 207 208 static void spapr_dt_pa_features(SpaprMachineState *spapr, 209 PowerPCCPU *cpu, 210 void *fdt, int offset) 211 { 212 uint8_t pa_features_206[] = { 6, 0, 213 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 214 uint8_t pa_features_207[] = { 24, 0, 215 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 216 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 217 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 218 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 219 uint8_t pa_features_300[] = { 66, 0, 220 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 221 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 222 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 223 /* 6: DS207 */ 224 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 225 /* 16: Vector */ 226 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 227 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 228 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 229 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 230 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 231 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 232 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 233 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 235 /* 42: PM, 44: PC RA, 46: SC vec'd */ 236 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 237 /* 48: SIMD, 50: QP BFP, 52: String */ 238 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 239 /* 54: DecFP, 56: DecI, 58: SHA */ 240 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 241 /* 60: NM atomic, 62: RNG */ 242 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 243 }; 244 uint8_t *pa_features = NULL; 245 size_t pa_size; 246 247 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 248 pa_features = pa_features_206; 249 pa_size = sizeof(pa_features_206); 250 } 251 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 252 pa_features = pa_features_207; 253 pa_size = sizeof(pa_features_207); 254 } 255 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 256 pa_features = pa_features_300; 257 pa_size = sizeof(pa_features_300); 258 } 259 if (!pa_features) { 260 return; 261 } 262 263 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 264 /* 265 * Note: we keep CI large pages off by default because a 64K capable 266 * guest provisioned with large pages might otherwise try to map a qemu 267 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 268 * even if that qemu runs on a 4k host. 269 * We dd this bit back here if we are confident this is not an issue 270 */ 271 pa_features[3] |= 0x20; 272 } 273 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 274 pa_features[24] |= 0x80; /* Transactional memory support */ 275 } 276 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 277 /* Workaround for broken kernels that attempt (guest) radix 278 * mode when they can't handle it, if they see the radix bit set 279 * in pa-features. So hide it from them. */ 280 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 281 } 282 283 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 284 } 285 286 static hwaddr spapr_node0_size(MachineState *machine) 287 { 288 if (machine->numa_state->num_nodes) { 289 int i; 290 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 291 if (machine->numa_state->nodes[i].node_mem) { 292 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 293 machine->ram_size); 294 } 295 } 296 } 297 return machine->ram_size; 298 } 299 300 static void add_str(GString *s, const gchar *s1) 301 { 302 g_string_append_len(s, s1, strlen(s1) + 1); 303 } 304 305 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 306 hwaddr start, hwaddr size) 307 { 308 char mem_name[32]; 309 uint64_t mem_reg_property[2]; 310 int off; 311 312 mem_reg_property[0] = cpu_to_be64(start); 313 mem_reg_property[1] = cpu_to_be64(size); 314 315 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 316 off = fdt_add_subnode(fdt, 0, mem_name); 317 _FDT(off); 318 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 319 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 320 sizeof(mem_reg_property)))); 321 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 322 return off; 323 } 324 325 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 326 { 327 MemoryDeviceInfoList *info; 328 329 for (info = list; info; info = info->next) { 330 MemoryDeviceInfo *value = info->value; 331 332 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 333 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 334 335 if (addr >= pcdimm_info->addr && 336 addr < (pcdimm_info->addr + pcdimm_info->size)) { 337 return pcdimm_info->node; 338 } 339 } 340 } 341 342 return -1; 343 } 344 345 struct sPAPRDrconfCellV2 { 346 uint32_t seq_lmbs; 347 uint64_t base_addr; 348 uint32_t drc_index; 349 uint32_t aa_index; 350 uint32_t flags; 351 } QEMU_PACKED; 352 353 typedef struct DrconfCellQueue { 354 struct sPAPRDrconfCellV2 cell; 355 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 356 } DrconfCellQueue; 357 358 static DrconfCellQueue * 359 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 360 uint32_t drc_index, uint32_t aa_index, 361 uint32_t flags) 362 { 363 DrconfCellQueue *elem; 364 365 elem = g_malloc0(sizeof(*elem)); 366 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 367 elem->cell.base_addr = cpu_to_be64(base_addr); 368 elem->cell.drc_index = cpu_to_be32(drc_index); 369 elem->cell.aa_index = cpu_to_be32(aa_index); 370 elem->cell.flags = cpu_to_be32(flags); 371 372 return elem; 373 } 374 375 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 376 int offset, MemoryDeviceInfoList *dimms) 377 { 378 MachineState *machine = MACHINE(spapr); 379 uint8_t *int_buf, *cur_index; 380 int ret; 381 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 382 uint64_t addr, cur_addr, size; 383 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 384 uint64_t mem_end = machine->device_memory->base + 385 memory_region_size(&machine->device_memory->mr); 386 uint32_t node, buf_len, nr_entries = 0; 387 SpaprDrc *drc; 388 DrconfCellQueue *elem, *next; 389 MemoryDeviceInfoList *info; 390 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 391 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 392 393 /* Entry to cover RAM and the gap area */ 394 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 395 SPAPR_LMB_FLAGS_RESERVED | 396 SPAPR_LMB_FLAGS_DRC_INVALID); 397 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 398 nr_entries++; 399 400 cur_addr = machine->device_memory->base; 401 for (info = dimms; info; info = info->next) { 402 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 403 404 addr = di->addr; 405 size = di->size; 406 node = di->node; 407 408 /* 409 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 410 * area is marked hotpluggable in the next iteration for the bigger 411 * chunk including the NVDIMM occupied area. 412 */ 413 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 414 continue; 415 416 /* Entry for hot-pluggable area */ 417 if (cur_addr < addr) { 418 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 419 g_assert(drc); 420 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 421 cur_addr, spapr_drc_index(drc), -1, 0); 422 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 423 nr_entries++; 424 } 425 426 /* Entry for DIMM */ 427 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 428 g_assert(drc); 429 elem = spapr_get_drconf_cell(size / lmb_size, addr, 430 spapr_drc_index(drc), node, 431 (SPAPR_LMB_FLAGS_ASSIGNED | 432 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 433 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 434 nr_entries++; 435 cur_addr = addr + size; 436 } 437 438 /* Entry for remaining hotpluggable area */ 439 if (cur_addr < mem_end) { 440 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 441 g_assert(drc); 442 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 443 cur_addr, spapr_drc_index(drc), -1, 0); 444 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 445 nr_entries++; 446 } 447 448 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 449 int_buf = cur_index = g_malloc0(buf_len); 450 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 451 cur_index += sizeof(nr_entries); 452 453 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 454 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 455 cur_index += sizeof(elem->cell); 456 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 457 g_free(elem); 458 } 459 460 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 461 g_free(int_buf); 462 if (ret < 0) { 463 return -1; 464 } 465 return 0; 466 } 467 468 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 469 int offset, MemoryDeviceInfoList *dimms) 470 { 471 MachineState *machine = MACHINE(spapr); 472 int i, ret; 473 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 474 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 475 uint32_t nr_lmbs = (machine->device_memory->base + 476 memory_region_size(&machine->device_memory->mr)) / 477 lmb_size; 478 uint32_t *int_buf, *cur_index, buf_len; 479 480 /* 481 * Allocate enough buffer size to fit in ibm,dynamic-memory 482 */ 483 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 484 cur_index = int_buf = g_malloc0(buf_len); 485 int_buf[0] = cpu_to_be32(nr_lmbs); 486 cur_index++; 487 for (i = 0; i < nr_lmbs; i++) { 488 uint64_t addr = i * lmb_size; 489 uint32_t *dynamic_memory = cur_index; 490 491 if (i >= device_lmb_start) { 492 SpaprDrc *drc; 493 494 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 495 g_assert(drc); 496 497 dynamic_memory[0] = cpu_to_be32(addr >> 32); 498 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 499 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 500 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 501 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 502 if (memory_region_present(get_system_memory(), addr)) { 503 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 504 } else { 505 dynamic_memory[5] = cpu_to_be32(0); 506 } 507 } else { 508 /* 509 * LMB information for RMA, boot time RAM and gap b/n RAM and 510 * device memory region -- all these are marked as reserved 511 * and as having no valid DRC. 512 */ 513 dynamic_memory[0] = cpu_to_be32(addr >> 32); 514 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 515 dynamic_memory[2] = cpu_to_be32(0); 516 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 517 dynamic_memory[4] = cpu_to_be32(-1); 518 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 519 SPAPR_LMB_FLAGS_DRC_INVALID); 520 } 521 522 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 523 } 524 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 525 g_free(int_buf); 526 if (ret < 0) { 527 return -1; 528 } 529 return 0; 530 } 531 532 /* 533 * Adds ibm,dynamic-reconfiguration-memory node. 534 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 535 * of this device tree node. 536 */ 537 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 538 void *fdt) 539 { 540 MachineState *machine = MACHINE(spapr); 541 int ret, offset; 542 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 543 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 544 cpu_to_be32(lmb_size & 0xffffffff)}; 545 MemoryDeviceInfoList *dimms = NULL; 546 547 /* 548 * Don't create the node if there is no device memory 549 */ 550 if (machine->ram_size == machine->maxram_size) { 551 return 0; 552 } 553 554 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 555 556 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 557 sizeof(prop_lmb_size)); 558 if (ret < 0) { 559 return ret; 560 } 561 562 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 563 if (ret < 0) { 564 return ret; 565 } 566 567 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 568 if (ret < 0) { 569 return ret; 570 } 571 572 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 573 dimms = qmp_memory_device_list(); 574 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 575 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 576 } else { 577 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 578 } 579 qapi_free_MemoryDeviceInfoList(dimms); 580 581 if (ret < 0) { 582 return ret; 583 } 584 585 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 586 587 return ret; 588 } 589 590 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 591 { 592 MachineState *machine = MACHINE(spapr); 593 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 594 hwaddr mem_start, node_size; 595 int i, nb_nodes = machine->numa_state->num_nodes; 596 NodeInfo *nodes = machine->numa_state->nodes; 597 598 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 599 if (!nodes[i].node_mem) { 600 continue; 601 } 602 if (mem_start >= machine->ram_size) { 603 node_size = 0; 604 } else { 605 node_size = nodes[i].node_mem; 606 if (node_size > machine->ram_size - mem_start) { 607 node_size = machine->ram_size - mem_start; 608 } 609 } 610 if (!mem_start) { 611 /* spapr_machine_init() checks for rma_size <= node0_size 612 * already */ 613 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 614 mem_start += spapr->rma_size; 615 node_size -= spapr->rma_size; 616 } 617 for ( ; node_size; ) { 618 hwaddr sizetmp = pow2floor(node_size); 619 620 /* mem_start != 0 here */ 621 if (ctzl(mem_start) < ctzl(sizetmp)) { 622 sizetmp = 1ULL << ctzl(mem_start); 623 } 624 625 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 626 node_size -= sizetmp; 627 mem_start += sizetmp; 628 } 629 } 630 631 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 632 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 633 int ret; 634 635 g_assert(smc->dr_lmb_enabled); 636 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 637 if (ret) { 638 return ret; 639 } 640 } 641 642 return 0; 643 } 644 645 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 646 SpaprMachineState *spapr) 647 { 648 MachineState *ms = MACHINE(spapr); 649 PowerPCCPU *cpu = POWERPC_CPU(cs); 650 CPUPPCState *env = &cpu->env; 651 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 652 int index = spapr_get_vcpu_id(cpu); 653 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 654 0xffffffff, 0xffffffff}; 655 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 656 : SPAPR_TIMEBASE_FREQ; 657 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 658 uint32_t page_sizes_prop[64]; 659 size_t page_sizes_prop_size; 660 unsigned int smp_threads = ms->smp.threads; 661 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 662 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 663 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 664 SpaprDrc *drc; 665 int drc_index; 666 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 667 int i; 668 669 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 670 if (drc) { 671 drc_index = spapr_drc_index(drc); 672 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 673 } 674 675 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 676 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 677 678 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 679 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 680 env->dcache_line_size))); 681 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 682 env->dcache_line_size))); 683 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 684 env->icache_line_size))); 685 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 686 env->icache_line_size))); 687 688 if (pcc->l1_dcache_size) { 689 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 690 pcc->l1_dcache_size))); 691 } else { 692 warn_report("Unknown L1 dcache size for cpu"); 693 } 694 if (pcc->l1_icache_size) { 695 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 696 pcc->l1_icache_size))); 697 } else { 698 warn_report("Unknown L1 icache size for cpu"); 699 } 700 701 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 702 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 703 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 704 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 705 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 706 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 707 708 if (ppc_has_spr(cpu, SPR_PURR)) { 709 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 710 } 711 if (ppc_has_spr(cpu, SPR_PURR)) { 712 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 713 } 714 715 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 716 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 717 segs, sizeof(segs)))); 718 } 719 720 /* Advertise VSX (vector extensions) if available 721 * 1 == VMX / Altivec available 722 * 2 == VSX available 723 * 724 * Only CPUs for which we create core types in spapr_cpu_core.c 725 * are possible, and all of those have VMX */ 726 if (env->insns_flags & PPC_ALTIVEC) { 727 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 728 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 729 } else { 730 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 731 } 732 } 733 734 /* Advertise DFP (Decimal Floating Point) if available 735 * 0 / no property == no DFP 736 * 1 == DFP available */ 737 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 738 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 739 } 740 741 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 742 sizeof(page_sizes_prop)); 743 if (page_sizes_prop_size) { 744 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 745 page_sizes_prop, page_sizes_prop_size))); 746 } 747 748 spapr_dt_pa_features(spapr, cpu, fdt, offset); 749 750 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 751 cs->cpu_index / vcpus_per_socket))); 752 753 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 754 pft_size_prop, sizeof(pft_size_prop)))); 755 756 if (ms->numa_state->num_nodes > 1) { 757 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 758 } 759 760 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 761 762 if (pcc->radix_page_info) { 763 for (i = 0; i < pcc->radix_page_info->count; i++) { 764 radix_AP_encodings[i] = 765 cpu_to_be32(pcc->radix_page_info->entries[i]); 766 } 767 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 768 radix_AP_encodings, 769 pcc->radix_page_info->count * 770 sizeof(radix_AP_encodings[0])))); 771 } 772 773 /* 774 * We set this property to let the guest know that it can use the large 775 * decrementer and its width in bits. 776 */ 777 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 778 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 779 pcc->lrg_decr_bits))); 780 } 781 782 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 783 { 784 CPUState **rev; 785 CPUState *cs; 786 int n_cpus; 787 int cpus_offset; 788 int i; 789 790 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 791 _FDT(cpus_offset); 792 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 793 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 794 795 /* 796 * We walk the CPUs in reverse order to ensure that CPU DT nodes 797 * created by fdt_add_subnode() end up in the right order in FDT 798 * for the guest kernel the enumerate the CPUs correctly. 799 * 800 * The CPU list cannot be traversed in reverse order, so we need 801 * to do extra work. 802 */ 803 n_cpus = 0; 804 rev = NULL; 805 CPU_FOREACH(cs) { 806 rev = g_renew(CPUState *, rev, n_cpus + 1); 807 rev[n_cpus++] = cs; 808 } 809 810 for (i = n_cpus - 1; i >= 0; i--) { 811 CPUState *cs = rev[i]; 812 PowerPCCPU *cpu = POWERPC_CPU(cs); 813 int index = spapr_get_vcpu_id(cpu); 814 DeviceClass *dc = DEVICE_GET_CLASS(cs); 815 g_autofree char *nodename = NULL; 816 int offset; 817 818 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 819 continue; 820 } 821 822 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 823 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 824 _FDT(offset); 825 spapr_dt_cpu(cs, fdt, offset, spapr); 826 } 827 828 g_free(rev); 829 } 830 831 static int spapr_dt_rng(void *fdt) 832 { 833 int node; 834 int ret; 835 836 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 837 if (node <= 0) { 838 return -1; 839 } 840 ret = fdt_setprop_string(fdt, node, "device_type", 841 "ibm,platform-facilities"); 842 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 843 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 844 845 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 846 if (node <= 0) { 847 return -1; 848 } 849 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 850 851 return ret ? -1 : 0; 852 } 853 854 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 855 { 856 MachineState *ms = MACHINE(spapr); 857 int rtas; 858 GString *hypertas = g_string_sized_new(256); 859 GString *qemu_hypertas = g_string_sized_new(256); 860 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 861 memory_region_size(&MACHINE(spapr)->device_memory->mr); 862 uint32_t lrdr_capacity[] = { 863 cpu_to_be32(max_device_addr >> 32), 864 cpu_to_be32(max_device_addr & 0xffffffff), 865 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 866 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 867 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 868 }; 869 870 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 871 872 /* hypertas */ 873 add_str(hypertas, "hcall-pft"); 874 add_str(hypertas, "hcall-term"); 875 add_str(hypertas, "hcall-dabr"); 876 add_str(hypertas, "hcall-interrupt"); 877 add_str(hypertas, "hcall-tce"); 878 add_str(hypertas, "hcall-vio"); 879 add_str(hypertas, "hcall-splpar"); 880 add_str(hypertas, "hcall-join"); 881 add_str(hypertas, "hcall-bulk"); 882 add_str(hypertas, "hcall-set-mode"); 883 add_str(hypertas, "hcall-sprg0"); 884 add_str(hypertas, "hcall-copy"); 885 add_str(hypertas, "hcall-debug"); 886 add_str(hypertas, "hcall-vphn"); 887 if (spapr_get_cap(spapr, SPAPR_CAP_RPT_INVALIDATE) == SPAPR_CAP_ON) { 888 add_str(hypertas, "hcall-rpt-invalidate"); 889 } 890 891 add_str(qemu_hypertas, "hcall-memop1"); 892 893 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 894 add_str(hypertas, "hcall-multi-tce"); 895 } 896 897 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 898 add_str(hypertas, "hcall-hpt-resize"); 899 } 900 901 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 902 hypertas->str, hypertas->len)); 903 g_string_free(hypertas, TRUE); 904 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 905 qemu_hypertas->str, qemu_hypertas->len)); 906 g_string_free(qemu_hypertas, TRUE); 907 908 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 909 910 /* 911 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 912 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 913 * 914 * The system reset requirements are driven by existing Linux and PowerVM 915 * implementation which (contrary to PAPR) saves r3 in the error log 916 * structure like machine check, so Linux expects to find the saved r3 917 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 918 * does not look at the error value). 919 * 920 * System reset interrupts are not subject to interlock like machine 921 * check, so this memory area could be corrupted if the sreset is 922 * interrupted by a machine check (or vice versa) if it was shared. To 923 * prevent this, system reset uses per-CPU areas for the sreset save 924 * area. A system reset that interrupts a system reset handler could 925 * still overwrite this area, but Linux doesn't try to recover in that 926 * case anyway. 927 * 928 * The extra 8 bytes is required because Linux's FWNMI error log check 929 * is off-by-one. 930 * 931 * RTAS_MIN_SIZE is required for the RTAS blob itself. 932 */ 933 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_MIN_SIZE + 934 RTAS_ERROR_LOG_MAX + 935 ms->smp.max_cpus * sizeof(uint64_t) * 2 + 936 sizeof(uint64_t))); 937 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 938 RTAS_ERROR_LOG_MAX)); 939 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 940 RTAS_EVENT_SCAN_RATE)); 941 942 g_assert(msi_nonbroken); 943 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 944 945 /* 946 * According to PAPR, rtas ibm,os-term does not guarantee a return 947 * back to the guest cpu. 948 * 949 * While an additional ibm,extended-os-term property indicates 950 * that rtas call return will always occur. Set this property. 951 */ 952 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 953 954 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 955 lrdr_capacity, sizeof(lrdr_capacity))); 956 957 spapr_dt_rtas_tokens(fdt, rtas); 958 } 959 960 /* 961 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 962 * and the XIVE features that the guest may request and thus the valid 963 * values for bytes 23..26 of option vector 5: 964 */ 965 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 966 int chosen) 967 { 968 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 969 970 char val[2 * 4] = { 971 23, 0x00, /* XICS / XIVE mode */ 972 24, 0x00, /* Hash/Radix, filled in below. */ 973 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 974 26, 0x40, /* Radix options: GTSE == yes. */ 975 }; 976 977 if (spapr->irq->xics && spapr->irq->xive) { 978 val[1] = SPAPR_OV5_XIVE_BOTH; 979 } else if (spapr->irq->xive) { 980 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 981 } else { 982 assert(spapr->irq->xics); 983 val[1] = SPAPR_OV5_XIVE_LEGACY; 984 } 985 986 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 987 first_ppc_cpu->compat_pvr)) { 988 /* 989 * If we're in a pre POWER9 compat mode then the guest should 990 * do hash and use the legacy interrupt mode 991 */ 992 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 993 val[3] = 0x00; /* Hash */ 994 spapr_check_mmu_mode(false); 995 } else if (kvm_enabled()) { 996 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 997 val[3] = 0x80; /* OV5_MMU_BOTH */ 998 } else if (kvmppc_has_cap_mmu_radix()) { 999 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1000 } else { 1001 val[3] = 0x00; /* Hash */ 1002 } 1003 } else { 1004 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1005 val[3] = 0xC0; 1006 } 1007 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1008 val, sizeof(val))); 1009 } 1010 1011 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1012 { 1013 MachineState *machine = MACHINE(spapr); 1014 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1015 int chosen; 1016 1017 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1018 1019 if (reset) { 1020 const char *boot_device = spapr->boot_device; 1021 g_autofree char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1022 size_t cb = 0; 1023 g_autofree char *bootlist = get_boot_devices_list(&cb); 1024 1025 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1026 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1027 machine->kernel_cmdline)); 1028 } 1029 1030 if (spapr->initrd_size) { 1031 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1032 spapr->initrd_base)); 1033 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1034 spapr->initrd_base + spapr->initrd_size)); 1035 } 1036 1037 if (spapr->kernel_size) { 1038 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1039 cpu_to_be64(spapr->kernel_size) }; 1040 1041 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1042 &kprop, sizeof(kprop))); 1043 if (spapr->kernel_le) { 1044 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1045 } 1046 } 1047 if (machine->boot_config.has_menu && machine->boot_config.menu) { 1048 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", true))); 1049 } 1050 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1051 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1052 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1053 1054 if (cb && bootlist) { 1055 int i; 1056 1057 for (i = 0; i < cb; i++) { 1058 if (bootlist[i] == '\n') { 1059 bootlist[i] = ' '; 1060 } 1061 } 1062 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1063 } 1064 1065 if (boot_device && strlen(boot_device)) { 1066 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1067 } 1068 1069 if (spapr->want_stdout_path && stdout_path) { 1070 /* 1071 * "linux,stdout-path" and "stdout" properties are 1072 * deprecated by linux kernel. New platforms should only 1073 * use the "stdout-path" property. Set the new property 1074 * and continue using older property to remain compatible 1075 * with the existing firmware. 1076 */ 1077 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1078 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1079 } 1080 1081 /* 1082 * We can deal with BAR reallocation just fine, advertise it 1083 * to the guest 1084 */ 1085 if (smc->linux_pci_probe) { 1086 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1087 } 1088 1089 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1090 } 1091 1092 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1093 } 1094 1095 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1096 { 1097 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1098 * KVM to work under pHyp with some guest co-operation */ 1099 int hypervisor; 1100 uint8_t hypercall[16]; 1101 1102 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1103 /* indicate KVM hypercall interface */ 1104 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1105 if (kvmppc_has_cap_fixup_hcalls()) { 1106 /* 1107 * Older KVM versions with older guest kernels were broken 1108 * with the magic page, don't allow the guest to map it. 1109 */ 1110 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1111 sizeof(hypercall))) { 1112 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1113 hypercall, sizeof(hypercall))); 1114 } 1115 } 1116 } 1117 1118 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1119 { 1120 MachineState *machine = MACHINE(spapr); 1121 MachineClass *mc = MACHINE_GET_CLASS(machine); 1122 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1123 uint32_t root_drc_type_mask = 0; 1124 int ret; 1125 void *fdt; 1126 SpaprPhbState *phb; 1127 char *buf; 1128 1129 fdt = g_malloc0(space); 1130 _FDT((fdt_create_empty_tree(fdt, space))); 1131 1132 /* Root node */ 1133 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1134 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1135 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1136 1137 /* Guest UUID & Name*/ 1138 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1139 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1140 if (qemu_uuid_set) { 1141 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1142 } 1143 g_free(buf); 1144 1145 if (qemu_get_vm_name()) { 1146 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1147 qemu_get_vm_name())); 1148 } 1149 1150 /* Host Model & Serial Number */ 1151 if (spapr->host_model) { 1152 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1153 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1154 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1155 g_free(buf); 1156 } 1157 1158 if (spapr->host_serial) { 1159 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1160 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1161 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1162 g_free(buf); 1163 } 1164 1165 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1166 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1167 1168 /* /interrupt controller */ 1169 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1170 1171 ret = spapr_dt_memory(spapr, fdt); 1172 if (ret < 0) { 1173 error_report("couldn't setup memory nodes in fdt"); 1174 exit(1); 1175 } 1176 1177 /* /vdevice */ 1178 spapr_dt_vdevice(spapr->vio_bus, fdt); 1179 1180 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1181 ret = spapr_dt_rng(fdt); 1182 if (ret < 0) { 1183 error_report("could not set up rng device in the fdt"); 1184 exit(1); 1185 } 1186 } 1187 1188 QLIST_FOREACH(phb, &spapr->phbs, list) { 1189 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1190 if (ret < 0) { 1191 error_report("couldn't setup PCI devices in fdt"); 1192 exit(1); 1193 } 1194 } 1195 1196 spapr_dt_cpus(fdt, spapr); 1197 1198 /* ibm,drc-indexes and friends */ 1199 if (smc->dr_lmb_enabled) { 1200 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; 1201 } 1202 if (smc->dr_phb_enabled) { 1203 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; 1204 } 1205 if (mc->nvdimm_supported) { 1206 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM; 1207 } 1208 if (root_drc_type_mask) { 1209 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask)); 1210 } 1211 1212 if (mc->has_hotpluggable_cpus) { 1213 int offset = fdt_path_offset(fdt, "/cpus"); 1214 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1215 if (ret < 0) { 1216 error_report("Couldn't set up CPU DR device tree properties"); 1217 exit(1); 1218 } 1219 } 1220 1221 /* /event-sources */ 1222 spapr_dt_events(spapr, fdt); 1223 1224 /* /rtas */ 1225 spapr_dt_rtas(spapr, fdt); 1226 1227 /* /chosen */ 1228 spapr_dt_chosen(spapr, fdt, reset); 1229 1230 /* /hypervisor */ 1231 if (kvm_enabled()) { 1232 spapr_dt_hypervisor(spapr, fdt); 1233 } 1234 1235 /* Build memory reserve map */ 1236 if (reset) { 1237 if (spapr->kernel_size) { 1238 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1239 spapr->kernel_size))); 1240 } 1241 if (spapr->initrd_size) { 1242 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1243 spapr->initrd_size))); 1244 } 1245 } 1246 1247 /* NVDIMM devices */ 1248 if (mc->nvdimm_supported) { 1249 spapr_dt_persistent_memory(spapr, fdt); 1250 } 1251 1252 return fdt; 1253 } 1254 1255 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1256 { 1257 SpaprMachineState *spapr = opaque; 1258 1259 return (addr & 0x0fffffff) + spapr->kernel_addr; 1260 } 1261 1262 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1263 PowerPCCPU *cpu) 1264 { 1265 CPUPPCState *env = &cpu->env; 1266 1267 /* The TCG path should also be holding the BQL at this point */ 1268 g_assert(qemu_mutex_iothread_locked()); 1269 1270 g_assert(!vhyp_cpu_in_nested(cpu)); 1271 1272 if (FIELD_EX64(env->msr, MSR, PR)) { 1273 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1274 env->gpr[3] = H_PRIVILEGE; 1275 } else { 1276 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1277 } 1278 } 1279 1280 struct LPCRSyncState { 1281 target_ulong value; 1282 target_ulong mask; 1283 }; 1284 1285 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1286 { 1287 struct LPCRSyncState *s = arg.host_ptr; 1288 PowerPCCPU *cpu = POWERPC_CPU(cs); 1289 CPUPPCState *env = &cpu->env; 1290 target_ulong lpcr; 1291 1292 cpu_synchronize_state(cs); 1293 lpcr = env->spr[SPR_LPCR]; 1294 lpcr &= ~s->mask; 1295 lpcr |= s->value; 1296 ppc_store_lpcr(cpu, lpcr); 1297 } 1298 1299 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1300 { 1301 CPUState *cs; 1302 struct LPCRSyncState s = { 1303 .value = value, 1304 .mask = mask 1305 }; 1306 CPU_FOREACH(cs) { 1307 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1308 } 1309 } 1310 1311 static bool spapr_get_pate(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu, 1312 target_ulong lpid, ppc_v3_pate_t *entry) 1313 { 1314 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1315 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 1316 1317 if (!spapr_cpu->in_nested) { 1318 assert(lpid == 0); 1319 1320 /* Copy PATE1:GR into PATE0:HR */ 1321 entry->dw0 = spapr->patb_entry & PATE0_HR; 1322 entry->dw1 = spapr->patb_entry; 1323 1324 } else { 1325 uint64_t patb, pats; 1326 1327 assert(lpid != 0); 1328 1329 patb = spapr->nested_ptcr & PTCR_PATB; 1330 pats = spapr->nested_ptcr & PTCR_PATS; 1331 1332 /* Calculate number of entries */ 1333 pats = 1ull << (pats + 12 - 4); 1334 if (pats <= lpid) { 1335 return false; 1336 } 1337 1338 /* Grab entry */ 1339 patb += 16 * lpid; 1340 entry->dw0 = ldq_phys(CPU(cpu)->as, patb); 1341 entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8); 1342 } 1343 1344 return true; 1345 } 1346 1347 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1348 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1349 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1350 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1351 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1352 1353 /* 1354 * Get the fd to access the kernel htab, re-opening it if necessary 1355 */ 1356 static int get_htab_fd(SpaprMachineState *spapr) 1357 { 1358 Error *local_err = NULL; 1359 1360 if (spapr->htab_fd >= 0) { 1361 return spapr->htab_fd; 1362 } 1363 1364 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1365 if (spapr->htab_fd < 0) { 1366 error_report_err(local_err); 1367 } 1368 1369 return spapr->htab_fd; 1370 } 1371 1372 void close_htab_fd(SpaprMachineState *spapr) 1373 { 1374 if (spapr->htab_fd >= 0) { 1375 close(spapr->htab_fd); 1376 } 1377 spapr->htab_fd = -1; 1378 } 1379 1380 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1381 { 1382 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1383 1384 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1385 } 1386 1387 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1388 { 1389 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1390 1391 assert(kvm_enabled()); 1392 1393 if (!spapr->htab) { 1394 return 0; 1395 } 1396 1397 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1398 } 1399 1400 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1401 hwaddr ptex, int n) 1402 { 1403 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1404 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1405 1406 if (!spapr->htab) { 1407 /* 1408 * HTAB is controlled by KVM. Fetch into temporary buffer 1409 */ 1410 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1411 kvmppc_read_hptes(hptes, ptex, n); 1412 return hptes; 1413 } 1414 1415 /* 1416 * HTAB is controlled by QEMU. Just point to the internally 1417 * accessible PTEG. 1418 */ 1419 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1420 } 1421 1422 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1423 const ppc_hash_pte64_t *hptes, 1424 hwaddr ptex, int n) 1425 { 1426 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1427 1428 if (!spapr->htab) { 1429 g_free((void *)hptes); 1430 } 1431 1432 /* Nothing to do for qemu managed HPT */ 1433 } 1434 1435 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1436 uint64_t pte0, uint64_t pte1) 1437 { 1438 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1439 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1440 1441 if (!spapr->htab) { 1442 kvmppc_write_hpte(ptex, pte0, pte1); 1443 } else { 1444 if (pte0 & HPTE64_V_VALID) { 1445 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1446 /* 1447 * When setting valid, we write PTE1 first. This ensures 1448 * proper synchronization with the reading code in 1449 * ppc_hash64_pteg_search() 1450 */ 1451 smp_wmb(); 1452 stq_p(spapr->htab + offset, pte0); 1453 } else { 1454 stq_p(spapr->htab + offset, pte0); 1455 /* 1456 * When clearing it we set PTE0 first. This ensures proper 1457 * synchronization with the reading code in 1458 * ppc_hash64_pteg_search() 1459 */ 1460 smp_wmb(); 1461 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1462 } 1463 } 1464 } 1465 1466 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1467 uint64_t pte1) 1468 { 1469 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_C; 1470 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1471 1472 if (!spapr->htab) { 1473 /* There should always be a hash table when this is called */ 1474 error_report("spapr_hpte_set_c called with no hash table !"); 1475 return; 1476 } 1477 1478 /* The HW performs a non-atomic byte update */ 1479 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1480 } 1481 1482 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1483 uint64_t pte1) 1484 { 1485 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_R; 1486 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1487 1488 if (!spapr->htab) { 1489 /* There should always be a hash table when this is called */ 1490 error_report("spapr_hpte_set_r called with no hash table !"); 1491 return; 1492 } 1493 1494 /* The HW performs a non-atomic byte update */ 1495 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1496 } 1497 1498 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1499 { 1500 int shift; 1501 1502 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1503 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1504 * that's much more than is needed for Linux guests */ 1505 shift = ctz64(pow2ceil(ramsize)) - 7; 1506 shift = MAX(shift, 18); /* Minimum architected size */ 1507 shift = MIN(shift, 46); /* Maximum architected size */ 1508 return shift; 1509 } 1510 1511 void spapr_free_hpt(SpaprMachineState *spapr) 1512 { 1513 g_free(spapr->htab); 1514 spapr->htab = NULL; 1515 spapr->htab_shift = 0; 1516 close_htab_fd(spapr); 1517 } 1518 1519 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1520 { 1521 ERRP_GUARD(); 1522 long rc; 1523 1524 /* Clean up any HPT info from a previous boot */ 1525 spapr_free_hpt(spapr); 1526 1527 rc = kvmppc_reset_htab(shift); 1528 1529 if (rc == -EOPNOTSUPP) { 1530 error_setg(errp, "HPT not supported in nested guests"); 1531 return -EOPNOTSUPP; 1532 } 1533 1534 if (rc < 0) { 1535 /* kernel-side HPT needed, but couldn't allocate one */ 1536 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1537 shift); 1538 error_append_hint(errp, "Try smaller maxmem?\n"); 1539 return -errno; 1540 } else if (rc > 0) { 1541 /* kernel-side HPT allocated */ 1542 if (rc != shift) { 1543 error_setg(errp, 1544 "Requested order %d HPT, but kernel allocated order %ld", 1545 shift, rc); 1546 error_append_hint(errp, "Try smaller maxmem?\n"); 1547 return -ENOSPC; 1548 } 1549 1550 spapr->htab_shift = shift; 1551 spapr->htab = NULL; 1552 } else { 1553 /* kernel-side HPT not needed, allocate in userspace instead */ 1554 size_t size = 1ULL << shift; 1555 int i; 1556 1557 spapr->htab = qemu_memalign(size, size); 1558 memset(spapr->htab, 0, size); 1559 spapr->htab_shift = shift; 1560 1561 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1562 DIRTY_HPTE(HPTE(spapr->htab, i)); 1563 } 1564 } 1565 /* We're setting up a hash table, so that means we're not radix */ 1566 spapr->patb_entry = 0; 1567 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1568 return 0; 1569 } 1570 1571 void spapr_setup_hpt(SpaprMachineState *spapr) 1572 { 1573 int hpt_shift; 1574 1575 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1576 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1577 } else { 1578 uint64_t current_ram_size; 1579 1580 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1581 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1582 } 1583 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1584 1585 if (kvm_enabled()) { 1586 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1587 1588 /* Check our RMA fits in the possible VRMA */ 1589 if (vrma_limit < spapr->rma_size) { 1590 error_report("Unable to create %" HWADDR_PRIu 1591 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1592 spapr->rma_size / MiB, vrma_limit / MiB); 1593 exit(EXIT_FAILURE); 1594 } 1595 } 1596 } 1597 1598 void spapr_check_mmu_mode(bool guest_radix) 1599 { 1600 if (guest_radix) { 1601 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 1602 error_report("Guest requested unavailable MMU mode (radix)."); 1603 exit(EXIT_FAILURE); 1604 } 1605 } else { 1606 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 1607 && !kvmppc_has_cap_mmu_hash_v3()) { 1608 error_report("Guest requested unavailable MMU mode (hash)."); 1609 exit(EXIT_FAILURE); 1610 } 1611 } 1612 } 1613 1614 static void spapr_machine_reset(MachineState *machine) 1615 { 1616 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1617 PowerPCCPU *first_ppc_cpu; 1618 hwaddr fdt_addr; 1619 void *fdt; 1620 int rc; 1621 1622 pef_kvm_reset(machine->cgs, &error_fatal); 1623 spapr_caps_apply(spapr); 1624 1625 first_ppc_cpu = POWERPC_CPU(first_cpu); 1626 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1627 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1628 spapr->max_compat_pvr)) { 1629 /* 1630 * If using KVM with radix mode available, VCPUs can be started 1631 * without a HPT because KVM will start them in radix mode. 1632 * Set the GR bit in PATE so that we know there is no HPT. 1633 */ 1634 spapr->patb_entry = PATE1_GR; 1635 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1636 } else { 1637 spapr_setup_hpt(spapr); 1638 } 1639 1640 qemu_devices_reset(); 1641 1642 spapr_ovec_cleanup(spapr->ov5_cas); 1643 spapr->ov5_cas = spapr_ovec_new(); 1644 1645 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1646 1647 /* 1648 * This is fixing some of the default configuration of the XIVE 1649 * devices. To be called after the reset of the machine devices. 1650 */ 1651 spapr_irq_reset(spapr, &error_fatal); 1652 1653 /* 1654 * There is no CAS under qtest. Simulate one to please the code that 1655 * depends on spapr->ov5_cas. This is especially needed to test device 1656 * unplug, so we do that before resetting the DRCs. 1657 */ 1658 if (qtest_enabled()) { 1659 spapr_ovec_cleanup(spapr->ov5_cas); 1660 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1661 } 1662 1663 spapr_nvdimm_finish_flushes(); 1664 1665 /* DRC reset may cause a device to be unplugged. This will cause troubles 1666 * if this device is used by another device (eg, a running vhost backend 1667 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1668 * situations, we reset DRCs after all devices have been reset. 1669 */ 1670 spapr_drc_reset_all(spapr); 1671 1672 spapr_clear_pending_events(spapr); 1673 1674 /* 1675 * We place the device tree just below either the top of the RMA, 1676 * or just below 2GB, whichever is lower, so that it can be 1677 * processed with 32-bit real mode code if necessary 1678 */ 1679 fdt_addr = MIN(spapr->rma_size, FDT_MAX_ADDR) - FDT_MAX_SIZE; 1680 1681 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1682 if (spapr->vof) { 1683 spapr_vof_reset(spapr, fdt, &error_fatal); 1684 /* 1685 * Do not pack the FDT as the client may change properties. 1686 * VOF client does not expect the FDT so we do not load it to the VM. 1687 */ 1688 } else { 1689 rc = fdt_pack(fdt); 1690 /* Should only fail if we've built a corrupted tree */ 1691 assert(rc == 0); 1692 1693 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 1694 0, fdt_addr, 0); 1695 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1696 } 1697 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1698 1699 g_free(spapr->fdt_blob); 1700 spapr->fdt_size = fdt_totalsize(fdt); 1701 spapr->fdt_initial_size = spapr->fdt_size; 1702 spapr->fdt_blob = fdt; 1703 1704 /* Set up the entry state */ 1705 first_ppc_cpu->env.gpr[5] = 0; 1706 1707 spapr->fwnmi_system_reset_addr = -1; 1708 spapr->fwnmi_machine_check_addr = -1; 1709 spapr->fwnmi_machine_check_interlock = -1; 1710 1711 /* Signal all vCPUs waiting on this condition */ 1712 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1713 1714 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1715 } 1716 1717 static void spapr_create_nvram(SpaprMachineState *spapr) 1718 { 1719 DeviceState *dev = qdev_new("spapr-nvram"); 1720 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1721 1722 if (dinfo) { 1723 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1724 &error_fatal); 1725 } 1726 1727 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1728 1729 spapr->nvram = (struct SpaprNvram *)dev; 1730 } 1731 1732 static void spapr_rtc_create(SpaprMachineState *spapr) 1733 { 1734 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1735 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1736 &error_fatal, NULL); 1737 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1738 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1739 "date"); 1740 } 1741 1742 /* Returns whether we want to use VGA or not */ 1743 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1744 { 1745 vga_interface_created = true; 1746 switch (vga_interface_type) { 1747 case VGA_NONE: 1748 return false; 1749 case VGA_DEVICE: 1750 return true; 1751 case VGA_STD: 1752 case VGA_VIRTIO: 1753 case VGA_CIRRUS: 1754 return pci_vga_init(pci_bus) != NULL; 1755 default: 1756 error_setg(errp, 1757 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1758 return false; 1759 } 1760 } 1761 1762 static int spapr_pre_load(void *opaque) 1763 { 1764 int rc; 1765 1766 rc = spapr_caps_pre_load(opaque); 1767 if (rc) { 1768 return rc; 1769 } 1770 1771 return 0; 1772 } 1773 1774 static int spapr_post_load(void *opaque, int version_id) 1775 { 1776 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1777 int err = 0; 1778 1779 err = spapr_caps_post_migration(spapr); 1780 if (err) { 1781 return err; 1782 } 1783 1784 /* 1785 * In earlier versions, there was no separate qdev for the PAPR 1786 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1787 * So when migrating from those versions, poke the incoming offset 1788 * value into the RTC device 1789 */ 1790 if (version_id < 3) { 1791 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1792 if (err) { 1793 return err; 1794 } 1795 } 1796 1797 if (kvm_enabled() && spapr->patb_entry) { 1798 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1799 bool radix = !!(spapr->patb_entry & PATE1_GR); 1800 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1801 1802 /* 1803 * Update LPCR:HR and UPRT as they may not be set properly in 1804 * the stream 1805 */ 1806 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1807 LPCR_HR | LPCR_UPRT); 1808 1809 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1810 if (err) { 1811 error_report("Process table config unsupported by the host"); 1812 return -EINVAL; 1813 } 1814 } 1815 1816 err = spapr_irq_post_load(spapr, version_id); 1817 if (err) { 1818 return err; 1819 } 1820 1821 return err; 1822 } 1823 1824 static int spapr_pre_save(void *opaque) 1825 { 1826 int rc; 1827 1828 rc = spapr_caps_pre_save(opaque); 1829 if (rc) { 1830 return rc; 1831 } 1832 1833 return 0; 1834 } 1835 1836 static bool version_before_3(void *opaque, int version_id) 1837 { 1838 return version_id < 3; 1839 } 1840 1841 static bool spapr_pending_events_needed(void *opaque) 1842 { 1843 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1844 return !QTAILQ_EMPTY(&spapr->pending_events); 1845 } 1846 1847 static const VMStateDescription vmstate_spapr_event_entry = { 1848 .name = "spapr_event_log_entry", 1849 .version_id = 1, 1850 .minimum_version_id = 1, 1851 .fields = (VMStateField[]) { 1852 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1853 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1854 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1855 NULL, extended_length), 1856 VMSTATE_END_OF_LIST() 1857 }, 1858 }; 1859 1860 static const VMStateDescription vmstate_spapr_pending_events = { 1861 .name = "spapr_pending_events", 1862 .version_id = 1, 1863 .minimum_version_id = 1, 1864 .needed = spapr_pending_events_needed, 1865 .fields = (VMStateField[]) { 1866 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1867 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1868 VMSTATE_END_OF_LIST() 1869 }, 1870 }; 1871 1872 static bool spapr_ov5_cas_needed(void *opaque) 1873 { 1874 SpaprMachineState *spapr = opaque; 1875 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1876 bool cas_needed; 1877 1878 /* Prior to the introduction of SpaprOptionVector, we had two option 1879 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1880 * Both of these options encode machine topology into the device-tree 1881 * in such a way that the now-booted OS should still be able to interact 1882 * appropriately with QEMU regardless of what options were actually 1883 * negotiatied on the source side. 1884 * 1885 * As such, we can avoid migrating the CAS-negotiated options if these 1886 * are the only options available on the current machine/platform. 1887 * Since these are the only options available for pseries-2.7 and 1888 * earlier, this allows us to maintain old->new/new->old migration 1889 * compatibility. 1890 * 1891 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1892 * via default pseries-2.8 machines and explicit command-line parameters. 1893 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1894 * of the actual CAS-negotiated values to continue working properly. For 1895 * example, availability of memory unplug depends on knowing whether 1896 * OV5_HP_EVT was negotiated via CAS. 1897 * 1898 * Thus, for any cases where the set of available CAS-negotiatable 1899 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1900 * include the CAS-negotiated options in the migration stream, unless 1901 * if they affect boot time behaviour only. 1902 */ 1903 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1904 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1905 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1906 1907 /* We need extra information if we have any bits outside the mask 1908 * defined above */ 1909 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1910 1911 spapr_ovec_cleanup(ov5_mask); 1912 1913 return cas_needed; 1914 } 1915 1916 static const VMStateDescription vmstate_spapr_ov5_cas = { 1917 .name = "spapr_option_vector_ov5_cas", 1918 .version_id = 1, 1919 .minimum_version_id = 1, 1920 .needed = spapr_ov5_cas_needed, 1921 .fields = (VMStateField[]) { 1922 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1923 vmstate_spapr_ovec, SpaprOptionVector), 1924 VMSTATE_END_OF_LIST() 1925 }, 1926 }; 1927 1928 static bool spapr_patb_entry_needed(void *opaque) 1929 { 1930 SpaprMachineState *spapr = opaque; 1931 1932 return !!spapr->patb_entry; 1933 } 1934 1935 static const VMStateDescription vmstate_spapr_patb_entry = { 1936 .name = "spapr_patb_entry", 1937 .version_id = 1, 1938 .minimum_version_id = 1, 1939 .needed = spapr_patb_entry_needed, 1940 .fields = (VMStateField[]) { 1941 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1942 VMSTATE_END_OF_LIST() 1943 }, 1944 }; 1945 1946 static bool spapr_irq_map_needed(void *opaque) 1947 { 1948 SpaprMachineState *spapr = opaque; 1949 1950 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1951 } 1952 1953 static const VMStateDescription vmstate_spapr_irq_map = { 1954 .name = "spapr_irq_map", 1955 .version_id = 1, 1956 .minimum_version_id = 1, 1957 .needed = spapr_irq_map_needed, 1958 .fields = (VMStateField[]) { 1959 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1960 VMSTATE_END_OF_LIST() 1961 }, 1962 }; 1963 1964 static bool spapr_dtb_needed(void *opaque) 1965 { 1966 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1967 1968 return smc->update_dt_enabled; 1969 } 1970 1971 static int spapr_dtb_pre_load(void *opaque) 1972 { 1973 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1974 1975 g_free(spapr->fdt_blob); 1976 spapr->fdt_blob = NULL; 1977 spapr->fdt_size = 0; 1978 1979 return 0; 1980 } 1981 1982 static const VMStateDescription vmstate_spapr_dtb = { 1983 .name = "spapr_dtb", 1984 .version_id = 1, 1985 .minimum_version_id = 1, 1986 .needed = spapr_dtb_needed, 1987 .pre_load = spapr_dtb_pre_load, 1988 .fields = (VMStateField[]) { 1989 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1990 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1991 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1992 fdt_size), 1993 VMSTATE_END_OF_LIST() 1994 }, 1995 }; 1996 1997 static bool spapr_fwnmi_needed(void *opaque) 1998 { 1999 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2000 2001 return spapr->fwnmi_machine_check_addr != -1; 2002 } 2003 2004 static int spapr_fwnmi_pre_save(void *opaque) 2005 { 2006 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2007 2008 /* 2009 * Check if machine check handling is in progress and print a 2010 * warning message. 2011 */ 2012 if (spapr->fwnmi_machine_check_interlock != -1) { 2013 warn_report("A machine check is being handled during migration. The" 2014 "handler may run and log hardware error on the destination"); 2015 } 2016 2017 return 0; 2018 } 2019 2020 static const VMStateDescription vmstate_spapr_fwnmi = { 2021 .name = "spapr_fwnmi", 2022 .version_id = 1, 2023 .minimum_version_id = 1, 2024 .needed = spapr_fwnmi_needed, 2025 .pre_save = spapr_fwnmi_pre_save, 2026 .fields = (VMStateField[]) { 2027 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 2028 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 2029 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 2030 VMSTATE_END_OF_LIST() 2031 }, 2032 }; 2033 2034 static const VMStateDescription vmstate_spapr = { 2035 .name = "spapr", 2036 .version_id = 3, 2037 .minimum_version_id = 1, 2038 .pre_load = spapr_pre_load, 2039 .post_load = spapr_post_load, 2040 .pre_save = spapr_pre_save, 2041 .fields = (VMStateField[]) { 2042 /* used to be @next_irq */ 2043 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2044 2045 /* RTC offset */ 2046 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2047 2048 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2049 VMSTATE_END_OF_LIST() 2050 }, 2051 .subsections = (const VMStateDescription*[]) { 2052 &vmstate_spapr_ov5_cas, 2053 &vmstate_spapr_patb_entry, 2054 &vmstate_spapr_pending_events, 2055 &vmstate_spapr_cap_htm, 2056 &vmstate_spapr_cap_vsx, 2057 &vmstate_spapr_cap_dfp, 2058 &vmstate_spapr_cap_cfpc, 2059 &vmstate_spapr_cap_sbbc, 2060 &vmstate_spapr_cap_ibs, 2061 &vmstate_spapr_cap_hpt_maxpagesize, 2062 &vmstate_spapr_irq_map, 2063 &vmstate_spapr_cap_nested_kvm_hv, 2064 &vmstate_spapr_dtb, 2065 &vmstate_spapr_cap_large_decr, 2066 &vmstate_spapr_cap_ccf_assist, 2067 &vmstate_spapr_cap_fwnmi, 2068 &vmstate_spapr_fwnmi, 2069 &vmstate_spapr_cap_rpt_invalidate, 2070 NULL 2071 } 2072 }; 2073 2074 static int htab_save_setup(QEMUFile *f, void *opaque) 2075 { 2076 SpaprMachineState *spapr = opaque; 2077 2078 /* "Iteration" header */ 2079 if (!spapr->htab_shift) { 2080 qemu_put_be32(f, -1); 2081 } else { 2082 qemu_put_be32(f, spapr->htab_shift); 2083 } 2084 2085 if (spapr->htab) { 2086 spapr->htab_save_index = 0; 2087 spapr->htab_first_pass = true; 2088 } else { 2089 if (spapr->htab_shift) { 2090 assert(kvm_enabled()); 2091 } 2092 } 2093 2094 2095 return 0; 2096 } 2097 2098 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2099 int chunkstart, int n_valid, int n_invalid) 2100 { 2101 qemu_put_be32(f, chunkstart); 2102 qemu_put_be16(f, n_valid); 2103 qemu_put_be16(f, n_invalid); 2104 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2105 HASH_PTE_SIZE_64 * n_valid); 2106 } 2107 2108 static void htab_save_end_marker(QEMUFile *f) 2109 { 2110 qemu_put_be32(f, 0); 2111 qemu_put_be16(f, 0); 2112 qemu_put_be16(f, 0); 2113 } 2114 2115 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2116 int64_t max_ns) 2117 { 2118 bool has_timeout = max_ns != -1; 2119 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2120 int index = spapr->htab_save_index; 2121 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2122 2123 assert(spapr->htab_first_pass); 2124 2125 do { 2126 int chunkstart; 2127 2128 /* Consume invalid HPTEs */ 2129 while ((index < htabslots) 2130 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2131 CLEAN_HPTE(HPTE(spapr->htab, index)); 2132 index++; 2133 } 2134 2135 /* Consume valid HPTEs */ 2136 chunkstart = index; 2137 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2138 && HPTE_VALID(HPTE(spapr->htab, index))) { 2139 CLEAN_HPTE(HPTE(spapr->htab, index)); 2140 index++; 2141 } 2142 2143 if (index > chunkstart) { 2144 int n_valid = index - chunkstart; 2145 2146 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2147 2148 if (has_timeout && 2149 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2150 break; 2151 } 2152 } 2153 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2154 2155 if (index >= htabslots) { 2156 assert(index == htabslots); 2157 index = 0; 2158 spapr->htab_first_pass = false; 2159 } 2160 spapr->htab_save_index = index; 2161 } 2162 2163 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2164 int64_t max_ns) 2165 { 2166 bool final = max_ns < 0; 2167 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2168 int examined = 0, sent = 0; 2169 int index = spapr->htab_save_index; 2170 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2171 2172 assert(!spapr->htab_first_pass); 2173 2174 do { 2175 int chunkstart, invalidstart; 2176 2177 /* Consume non-dirty HPTEs */ 2178 while ((index < htabslots) 2179 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2180 index++; 2181 examined++; 2182 } 2183 2184 chunkstart = index; 2185 /* Consume valid dirty HPTEs */ 2186 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2187 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2188 && HPTE_VALID(HPTE(spapr->htab, index))) { 2189 CLEAN_HPTE(HPTE(spapr->htab, index)); 2190 index++; 2191 examined++; 2192 } 2193 2194 invalidstart = index; 2195 /* Consume invalid dirty HPTEs */ 2196 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2197 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2198 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2199 CLEAN_HPTE(HPTE(spapr->htab, index)); 2200 index++; 2201 examined++; 2202 } 2203 2204 if (index > chunkstart) { 2205 int n_valid = invalidstart - chunkstart; 2206 int n_invalid = index - invalidstart; 2207 2208 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2209 sent += index - chunkstart; 2210 2211 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2212 break; 2213 } 2214 } 2215 2216 if (examined >= htabslots) { 2217 break; 2218 } 2219 2220 if (index >= htabslots) { 2221 assert(index == htabslots); 2222 index = 0; 2223 } 2224 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2225 2226 if (index >= htabslots) { 2227 assert(index == htabslots); 2228 index = 0; 2229 } 2230 2231 spapr->htab_save_index = index; 2232 2233 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2234 } 2235 2236 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2237 #define MAX_KVM_BUF_SIZE 2048 2238 2239 static int htab_save_iterate(QEMUFile *f, void *opaque) 2240 { 2241 SpaprMachineState *spapr = opaque; 2242 int fd; 2243 int rc = 0; 2244 2245 /* Iteration header */ 2246 if (!spapr->htab_shift) { 2247 qemu_put_be32(f, -1); 2248 return 1; 2249 } else { 2250 qemu_put_be32(f, 0); 2251 } 2252 2253 if (!spapr->htab) { 2254 assert(kvm_enabled()); 2255 2256 fd = get_htab_fd(spapr); 2257 if (fd < 0) { 2258 return fd; 2259 } 2260 2261 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2262 if (rc < 0) { 2263 return rc; 2264 } 2265 } else if (spapr->htab_first_pass) { 2266 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2267 } else { 2268 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2269 } 2270 2271 htab_save_end_marker(f); 2272 2273 return rc; 2274 } 2275 2276 static int htab_save_complete(QEMUFile *f, void *opaque) 2277 { 2278 SpaprMachineState *spapr = opaque; 2279 int fd; 2280 2281 /* Iteration header */ 2282 if (!spapr->htab_shift) { 2283 qemu_put_be32(f, -1); 2284 return 0; 2285 } else { 2286 qemu_put_be32(f, 0); 2287 } 2288 2289 if (!spapr->htab) { 2290 int rc; 2291 2292 assert(kvm_enabled()); 2293 2294 fd = get_htab_fd(spapr); 2295 if (fd < 0) { 2296 return fd; 2297 } 2298 2299 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2300 if (rc < 0) { 2301 return rc; 2302 } 2303 } else { 2304 if (spapr->htab_first_pass) { 2305 htab_save_first_pass(f, spapr, -1); 2306 } 2307 htab_save_later_pass(f, spapr, -1); 2308 } 2309 2310 /* End marker */ 2311 htab_save_end_marker(f); 2312 2313 return 0; 2314 } 2315 2316 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2317 { 2318 SpaprMachineState *spapr = opaque; 2319 uint32_t section_hdr; 2320 int fd = -1; 2321 Error *local_err = NULL; 2322 2323 if (version_id < 1 || version_id > 1) { 2324 error_report("htab_load() bad version"); 2325 return -EINVAL; 2326 } 2327 2328 section_hdr = qemu_get_be32(f); 2329 2330 if (section_hdr == -1) { 2331 spapr_free_hpt(spapr); 2332 return 0; 2333 } 2334 2335 if (section_hdr) { 2336 int ret; 2337 2338 /* First section gives the htab size */ 2339 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2340 if (ret < 0) { 2341 error_report_err(local_err); 2342 return ret; 2343 } 2344 return 0; 2345 } 2346 2347 if (!spapr->htab) { 2348 assert(kvm_enabled()); 2349 2350 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2351 if (fd < 0) { 2352 error_report_err(local_err); 2353 return fd; 2354 } 2355 } 2356 2357 while (true) { 2358 uint32_t index; 2359 uint16_t n_valid, n_invalid; 2360 2361 index = qemu_get_be32(f); 2362 n_valid = qemu_get_be16(f); 2363 n_invalid = qemu_get_be16(f); 2364 2365 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2366 /* End of Stream */ 2367 break; 2368 } 2369 2370 if ((index + n_valid + n_invalid) > 2371 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2372 /* Bad index in stream */ 2373 error_report( 2374 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2375 index, n_valid, n_invalid, spapr->htab_shift); 2376 return -EINVAL; 2377 } 2378 2379 if (spapr->htab) { 2380 if (n_valid) { 2381 qemu_get_buffer(f, HPTE(spapr->htab, index), 2382 HASH_PTE_SIZE_64 * n_valid); 2383 } 2384 if (n_invalid) { 2385 memset(HPTE(spapr->htab, index + n_valid), 0, 2386 HASH_PTE_SIZE_64 * n_invalid); 2387 } 2388 } else { 2389 int rc; 2390 2391 assert(fd >= 0); 2392 2393 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2394 &local_err); 2395 if (rc < 0) { 2396 error_report_err(local_err); 2397 return rc; 2398 } 2399 } 2400 } 2401 2402 if (!spapr->htab) { 2403 assert(fd >= 0); 2404 close(fd); 2405 } 2406 2407 return 0; 2408 } 2409 2410 static void htab_save_cleanup(void *opaque) 2411 { 2412 SpaprMachineState *spapr = opaque; 2413 2414 close_htab_fd(spapr); 2415 } 2416 2417 static SaveVMHandlers savevm_htab_handlers = { 2418 .save_setup = htab_save_setup, 2419 .save_live_iterate = htab_save_iterate, 2420 .save_live_complete_precopy = htab_save_complete, 2421 .save_cleanup = htab_save_cleanup, 2422 .load_state = htab_load, 2423 }; 2424 2425 static void spapr_boot_set(void *opaque, const char *boot_device, 2426 Error **errp) 2427 { 2428 SpaprMachineState *spapr = SPAPR_MACHINE(opaque); 2429 2430 g_free(spapr->boot_device); 2431 spapr->boot_device = g_strdup(boot_device); 2432 } 2433 2434 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2435 { 2436 MachineState *machine = MACHINE(spapr); 2437 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2438 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2439 int i; 2440 2441 for (i = 0; i < nr_lmbs; i++) { 2442 uint64_t addr; 2443 2444 addr = i * lmb_size + machine->device_memory->base; 2445 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2446 addr / lmb_size); 2447 } 2448 } 2449 2450 /* 2451 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2452 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2453 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2454 */ 2455 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2456 { 2457 int i; 2458 2459 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2460 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2461 " is not aligned to %" PRIu64 " MiB", 2462 machine->ram_size, 2463 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2464 return; 2465 } 2466 2467 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2468 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2469 " is not aligned to %" PRIu64 " MiB", 2470 machine->ram_size, 2471 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2472 return; 2473 } 2474 2475 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2476 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2477 error_setg(errp, 2478 "Node %d memory size 0x%" PRIx64 2479 " is not aligned to %" PRIu64 " MiB", 2480 i, machine->numa_state->nodes[i].node_mem, 2481 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2482 return; 2483 } 2484 } 2485 } 2486 2487 /* find cpu slot in machine->possible_cpus by core_id */ 2488 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2489 { 2490 int index = id / ms->smp.threads; 2491 2492 if (index >= ms->possible_cpus->len) { 2493 return NULL; 2494 } 2495 if (idx) { 2496 *idx = index; 2497 } 2498 return &ms->possible_cpus->cpus[index]; 2499 } 2500 2501 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2502 { 2503 MachineState *ms = MACHINE(spapr); 2504 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2505 Error *local_err = NULL; 2506 bool vsmt_user = !!spapr->vsmt; 2507 int kvm_smt = kvmppc_smt_threads(); 2508 int ret; 2509 unsigned int smp_threads = ms->smp.threads; 2510 2511 if (!kvm_enabled() && (smp_threads > 1)) { 2512 error_setg(errp, "TCG cannot support more than 1 thread/core " 2513 "on a pseries machine"); 2514 return; 2515 } 2516 if (!is_power_of_2(smp_threads)) { 2517 error_setg(errp, "Cannot support %d threads/core on a pseries " 2518 "machine because it must be a power of 2", smp_threads); 2519 return; 2520 } 2521 2522 /* Detemine the VSMT mode to use: */ 2523 if (vsmt_user) { 2524 if (spapr->vsmt < smp_threads) { 2525 error_setg(errp, "Cannot support VSMT mode %d" 2526 " because it must be >= threads/core (%d)", 2527 spapr->vsmt, smp_threads); 2528 return; 2529 } 2530 /* In this case, spapr->vsmt has been set by the command line */ 2531 } else if (!smc->smp_threads_vsmt) { 2532 /* 2533 * Default VSMT value is tricky, because we need it to be as 2534 * consistent as possible (for migration), but this requires 2535 * changing it for at least some existing cases. We pick 8 as 2536 * the value that we'd get with KVM on POWER8, the 2537 * overwhelmingly common case in production systems. 2538 */ 2539 spapr->vsmt = MAX(8, smp_threads); 2540 } else { 2541 spapr->vsmt = smp_threads; 2542 } 2543 2544 /* KVM: If necessary, set the SMT mode: */ 2545 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2546 ret = kvmppc_set_smt_threads(spapr->vsmt); 2547 if (ret) { 2548 /* Looks like KVM isn't able to change VSMT mode */ 2549 error_setg(&local_err, 2550 "Failed to set KVM's VSMT mode to %d (errno %d)", 2551 spapr->vsmt, ret); 2552 /* We can live with that if the default one is big enough 2553 * for the number of threads, and a submultiple of the one 2554 * we want. In this case we'll waste some vcpu ids, but 2555 * behaviour will be correct */ 2556 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2557 warn_report_err(local_err); 2558 } else { 2559 if (!vsmt_user) { 2560 error_append_hint(&local_err, 2561 "On PPC, a VM with %d threads/core" 2562 " on a host with %d threads/core" 2563 " requires the use of VSMT mode %d.\n", 2564 smp_threads, kvm_smt, spapr->vsmt); 2565 } 2566 kvmppc_error_append_smt_possible_hint(&local_err); 2567 error_propagate(errp, local_err); 2568 } 2569 } 2570 } 2571 /* else TCG: nothing to do currently */ 2572 } 2573 2574 static void spapr_init_cpus(SpaprMachineState *spapr) 2575 { 2576 MachineState *machine = MACHINE(spapr); 2577 MachineClass *mc = MACHINE_GET_CLASS(machine); 2578 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2579 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2580 const CPUArchIdList *possible_cpus; 2581 unsigned int smp_cpus = machine->smp.cpus; 2582 unsigned int smp_threads = machine->smp.threads; 2583 unsigned int max_cpus = machine->smp.max_cpus; 2584 int boot_cores_nr = smp_cpus / smp_threads; 2585 int i; 2586 2587 possible_cpus = mc->possible_cpu_arch_ids(machine); 2588 if (mc->has_hotpluggable_cpus) { 2589 if (smp_cpus % smp_threads) { 2590 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2591 smp_cpus, smp_threads); 2592 exit(1); 2593 } 2594 if (max_cpus % smp_threads) { 2595 error_report("max_cpus (%u) must be multiple of threads (%u)", 2596 max_cpus, smp_threads); 2597 exit(1); 2598 } 2599 } else { 2600 if (max_cpus != smp_cpus) { 2601 error_report("This machine version does not support CPU hotplug"); 2602 exit(1); 2603 } 2604 boot_cores_nr = possible_cpus->len; 2605 } 2606 2607 if (smc->pre_2_10_has_unused_icps) { 2608 int i; 2609 2610 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2611 /* Dummy entries get deregistered when real ICPState objects 2612 * are registered during CPU core hotplug. 2613 */ 2614 pre_2_10_vmstate_register_dummy_icp(i); 2615 } 2616 } 2617 2618 for (i = 0; i < possible_cpus->len; i++) { 2619 int core_id = i * smp_threads; 2620 2621 if (mc->has_hotpluggable_cpus) { 2622 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2623 spapr_vcpu_id(spapr, core_id)); 2624 } 2625 2626 if (i < boot_cores_nr) { 2627 Object *core = object_new(type); 2628 int nr_threads = smp_threads; 2629 2630 /* Handle the partially filled core for older machine types */ 2631 if ((i + 1) * smp_threads >= smp_cpus) { 2632 nr_threads = smp_cpus - i * smp_threads; 2633 } 2634 2635 object_property_set_int(core, "nr-threads", nr_threads, 2636 &error_fatal); 2637 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2638 &error_fatal); 2639 qdev_realize(DEVICE(core), NULL, &error_fatal); 2640 2641 object_unref(core); 2642 } 2643 } 2644 } 2645 2646 static PCIHostState *spapr_create_default_phb(void) 2647 { 2648 DeviceState *dev; 2649 2650 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2651 qdev_prop_set_uint32(dev, "index", 0); 2652 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2653 2654 return PCI_HOST_BRIDGE(dev); 2655 } 2656 2657 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2658 { 2659 MachineState *machine = MACHINE(spapr); 2660 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2661 hwaddr rma_size = machine->ram_size; 2662 hwaddr node0_size = spapr_node0_size(machine); 2663 2664 /* RMA has to fit in the first NUMA node */ 2665 rma_size = MIN(rma_size, node0_size); 2666 2667 /* 2668 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2669 * never exceed that 2670 */ 2671 rma_size = MIN(rma_size, 1 * TiB); 2672 2673 /* 2674 * Clamp the RMA size based on machine type. This is for 2675 * migration compatibility with older qemu versions, which limited 2676 * the RMA size for complicated and mostly bad reasons. 2677 */ 2678 if (smc->rma_limit) { 2679 rma_size = MIN(rma_size, smc->rma_limit); 2680 } 2681 2682 if (rma_size < MIN_RMA_SLOF) { 2683 error_setg(errp, 2684 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2685 "ldMiB guest RMA (Real Mode Area memory)", 2686 MIN_RMA_SLOF / MiB); 2687 return 0; 2688 } 2689 2690 return rma_size; 2691 } 2692 2693 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2694 { 2695 MachineState *machine = MACHINE(spapr); 2696 int i; 2697 2698 for (i = 0; i < machine->ram_slots; i++) { 2699 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2700 } 2701 } 2702 2703 /* pSeries LPAR / sPAPR hardware init */ 2704 static void spapr_machine_init(MachineState *machine) 2705 { 2706 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2707 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2708 MachineClass *mc = MACHINE_GET_CLASS(machine); 2709 const char *bios_default = spapr->vof ? FW_FILE_NAME_VOF : FW_FILE_NAME; 2710 const char *bios_name = machine->firmware ?: bios_default; 2711 g_autofree char *filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2712 const char *kernel_filename = machine->kernel_filename; 2713 const char *initrd_filename = machine->initrd_filename; 2714 PCIHostState *phb; 2715 bool has_vga; 2716 int i; 2717 MemoryRegion *sysmem = get_system_memory(); 2718 long load_limit, fw_size; 2719 Error *resize_hpt_err = NULL; 2720 2721 if (!filename) { 2722 error_report("Could not find LPAR firmware '%s'", bios_name); 2723 exit(1); 2724 } 2725 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2726 if (fw_size <= 0) { 2727 error_report("Could not load LPAR firmware '%s'", filename); 2728 exit(1); 2729 } 2730 2731 /* 2732 * if Secure VM (PEF) support is configured, then initialize it 2733 */ 2734 pef_kvm_init(machine->cgs, &error_fatal); 2735 2736 msi_nonbroken = true; 2737 2738 QLIST_INIT(&spapr->phbs); 2739 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2740 2741 /* Determine capabilities to run with */ 2742 spapr_caps_init(spapr); 2743 2744 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2745 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2746 /* 2747 * If the user explicitly requested a mode we should either 2748 * supply it, or fail completely (which we do below). But if 2749 * it's not set explicitly, we reset our mode to something 2750 * that works 2751 */ 2752 if (resize_hpt_err) { 2753 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2754 error_free(resize_hpt_err); 2755 resize_hpt_err = NULL; 2756 } else { 2757 spapr->resize_hpt = smc->resize_hpt_default; 2758 } 2759 } 2760 2761 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2762 2763 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2764 /* 2765 * User requested HPT resize, but this host can't supply it. Bail out 2766 */ 2767 error_report_err(resize_hpt_err); 2768 exit(1); 2769 } 2770 error_free(resize_hpt_err); 2771 2772 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2773 2774 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2775 load_limit = MIN(spapr->rma_size, FDT_MAX_ADDR) - FW_OVERHEAD; 2776 2777 /* 2778 * VSMT must be set in order to be able to compute VCPU ids, ie to 2779 * call spapr_max_server_number() or spapr_vcpu_id(). 2780 */ 2781 spapr_set_vsmt_mode(spapr, &error_fatal); 2782 2783 /* Set up Interrupt Controller before we create the VCPUs */ 2784 spapr_irq_init(spapr, &error_fatal); 2785 2786 /* Set up containers for ibm,client-architecture-support negotiated options 2787 */ 2788 spapr->ov5 = spapr_ovec_new(); 2789 spapr->ov5_cas = spapr_ovec_new(); 2790 2791 if (smc->dr_lmb_enabled) { 2792 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2793 spapr_validate_node_memory(machine, &error_fatal); 2794 } 2795 2796 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2797 2798 /* Do not advertise FORM2 NUMA support for pseries-6.1 and older */ 2799 if (!smc->pre_6_2_numa_affinity) { 2800 spapr_ovec_set(spapr->ov5, OV5_FORM2_AFFINITY); 2801 } 2802 2803 /* advertise support for dedicated HP event source to guests */ 2804 if (spapr->use_hotplug_event_source) { 2805 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2806 } 2807 2808 /* advertise support for HPT resizing */ 2809 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2810 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2811 } 2812 2813 /* advertise support for ibm,dyamic-memory-v2 */ 2814 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2815 2816 /* advertise XIVE on POWER9 machines */ 2817 if (spapr->irq->xive) { 2818 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2819 } 2820 2821 /* init CPUs */ 2822 spapr_init_cpus(spapr); 2823 2824 spapr->gpu_numa_id = spapr_numa_initial_nvgpu_numa_id(machine); 2825 2826 /* Init numa_assoc_array */ 2827 spapr_numa_associativity_init(spapr, machine); 2828 2829 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2830 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2831 spapr->max_compat_pvr)) { 2832 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2833 /* KVM and TCG always allow GTSE with radix... */ 2834 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2835 } 2836 /* ... but not with hash (currently). */ 2837 2838 if (kvm_enabled()) { 2839 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2840 kvmppc_enable_logical_ci_hcalls(); 2841 kvmppc_enable_set_mode_hcall(); 2842 2843 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2844 kvmppc_enable_clear_ref_mod_hcalls(); 2845 2846 /* Enable H_PAGE_INIT */ 2847 kvmppc_enable_h_page_init(); 2848 } 2849 2850 /* map RAM */ 2851 memory_region_add_subregion(sysmem, 0, machine->ram); 2852 2853 /* always allocate the device memory information */ 2854 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2855 2856 /* initialize hotplug memory address space */ 2857 if (machine->ram_size < machine->maxram_size) { 2858 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2859 /* 2860 * Limit the number of hotpluggable memory slots to half the number 2861 * slots that KVM supports, leaving the other half for PCI and other 2862 * devices. However ensure that number of slots doesn't drop below 32. 2863 */ 2864 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2865 SPAPR_MAX_RAM_SLOTS; 2866 2867 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2868 max_memslots = SPAPR_MAX_RAM_SLOTS; 2869 } 2870 if (machine->ram_slots > max_memslots) { 2871 error_report("Specified number of memory slots %" 2872 PRIu64" exceeds max supported %d", 2873 machine->ram_slots, max_memslots); 2874 exit(1); 2875 } 2876 2877 machine->device_memory->base = ROUND_UP(machine->ram_size, 2878 SPAPR_DEVICE_MEM_ALIGN); 2879 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2880 "device-memory", device_mem_size); 2881 memory_region_add_subregion(sysmem, machine->device_memory->base, 2882 &machine->device_memory->mr); 2883 } 2884 2885 if (smc->dr_lmb_enabled) { 2886 spapr_create_lmb_dr_connectors(spapr); 2887 } 2888 2889 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { 2890 /* Create the error string for live migration blocker */ 2891 error_setg(&spapr->fwnmi_migration_blocker, 2892 "A machine check is being handled during migration. The handler" 2893 "may run and log hardware error on the destination"); 2894 } 2895 2896 if (mc->nvdimm_supported) { 2897 spapr_create_nvdimm_dr_connectors(spapr); 2898 } 2899 2900 /* Set up RTAS event infrastructure */ 2901 spapr_events_init(spapr); 2902 2903 /* Set up the RTC RTAS interfaces */ 2904 spapr_rtc_create(spapr); 2905 2906 /* Set up VIO bus */ 2907 spapr->vio_bus = spapr_vio_bus_init(); 2908 2909 for (i = 0; serial_hd(i); i++) { 2910 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2911 } 2912 2913 /* We always have at least the nvram device on VIO */ 2914 spapr_create_nvram(spapr); 2915 2916 /* 2917 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2918 * connectors (described in root DT node's "ibm,drc-types" property) 2919 * are pre-initialized here. additional child connectors (such as 2920 * connectors for a PHBs PCI slots) are added as needed during their 2921 * parent's realization. 2922 */ 2923 if (smc->dr_phb_enabled) { 2924 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2925 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2926 } 2927 } 2928 2929 /* Set up PCI */ 2930 spapr_pci_rtas_init(); 2931 2932 phb = spapr_create_default_phb(); 2933 2934 for (i = 0; i < nb_nics; i++) { 2935 NICInfo *nd = &nd_table[i]; 2936 2937 if (!nd->model) { 2938 nd->model = g_strdup("spapr-vlan"); 2939 } 2940 2941 if (g_str_equal(nd->model, "spapr-vlan") || 2942 g_str_equal(nd->model, "ibmveth")) { 2943 spapr_vlan_create(spapr->vio_bus, nd); 2944 } else { 2945 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2946 } 2947 } 2948 2949 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2950 spapr_vscsi_create(spapr->vio_bus); 2951 } 2952 2953 /* Graphics */ 2954 has_vga = spapr_vga_init(phb->bus, &error_fatal); 2955 if (has_vga) { 2956 spapr->want_stdout_path = !machine->enable_graphics; 2957 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2958 } else { 2959 spapr->want_stdout_path = true; 2960 } 2961 2962 if (machine->usb) { 2963 if (smc->use_ohci_by_default) { 2964 pci_create_simple(phb->bus, -1, "pci-ohci"); 2965 } else { 2966 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2967 } 2968 2969 if (has_vga) { 2970 USBBus *usb_bus = usb_bus_find(-1); 2971 2972 usb_create_simple(usb_bus, "usb-kbd"); 2973 usb_create_simple(usb_bus, "usb-mouse"); 2974 } 2975 } 2976 2977 if (kernel_filename) { 2978 uint64_t loaded_addr = 0; 2979 2980 spapr->kernel_size = load_elf(kernel_filename, NULL, 2981 translate_kernel_address, spapr, 2982 NULL, &loaded_addr, NULL, NULL, 1, 2983 PPC_ELF_MACHINE, 0, 0); 2984 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2985 spapr->kernel_size = load_elf(kernel_filename, NULL, 2986 translate_kernel_address, spapr, 2987 NULL, &loaded_addr, NULL, NULL, 0, 2988 PPC_ELF_MACHINE, 0, 0); 2989 spapr->kernel_le = spapr->kernel_size > 0; 2990 } 2991 if (spapr->kernel_size < 0) { 2992 error_report("error loading %s: %s", kernel_filename, 2993 load_elf_strerror(spapr->kernel_size)); 2994 exit(1); 2995 } 2996 2997 if (spapr->kernel_addr != loaded_addr) { 2998 warn_report("spapr: kernel_addr changed from 0x%"PRIx64 2999 " to 0x%"PRIx64, 3000 spapr->kernel_addr, loaded_addr); 3001 spapr->kernel_addr = loaded_addr; 3002 } 3003 3004 /* load initrd */ 3005 if (initrd_filename) { 3006 /* Try to locate the initrd in the gap between the kernel 3007 * and the firmware. Add a bit of space just in case 3008 */ 3009 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 3010 + 0x1ffff) & ~0xffff; 3011 spapr->initrd_size = load_image_targphys(initrd_filename, 3012 spapr->initrd_base, 3013 load_limit 3014 - spapr->initrd_base); 3015 if (spapr->initrd_size < 0) { 3016 error_report("could not load initial ram disk '%s'", 3017 initrd_filename); 3018 exit(1); 3019 } 3020 } 3021 } 3022 3023 /* FIXME: Should register things through the MachineState's qdev 3024 * interface, this is a legacy from the sPAPREnvironment structure 3025 * which predated MachineState but had a similar function */ 3026 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3027 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3028 &savevm_htab_handlers, spapr); 3029 3030 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 3031 3032 qemu_register_boot_set(spapr_boot_set, spapr); 3033 3034 /* 3035 * Nothing needs to be done to resume a suspended guest because 3036 * suspending does not change the machine state, so no need for 3037 * a ->wakeup method. 3038 */ 3039 qemu_register_wakeup_support(); 3040 3041 if (kvm_enabled()) { 3042 /* to stop and start vmclock */ 3043 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3044 &spapr->tb); 3045 3046 kvmppc_spapr_enable_inkernel_multitce(); 3047 } 3048 3049 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3050 if (spapr->vof) { 3051 spapr->vof->fw_size = fw_size; /* for claim() on itself */ 3052 spapr_register_hypercall(KVMPPC_H_VOF_CLIENT, spapr_h_vof_client); 3053 } 3054 } 3055 3056 #define DEFAULT_KVM_TYPE "auto" 3057 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3058 { 3059 /* 3060 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to 3061 * accomodate the 'HV' and 'PV' formats that exists in the 3062 * wild. The 'auto' mode is being introduced already as 3063 * lower-case, thus we don't need to bother checking for 3064 * "AUTO". 3065 */ 3066 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) { 3067 return 0; 3068 } 3069 3070 if (!g_ascii_strcasecmp(vm_type, "hv")) { 3071 return 1; 3072 } 3073 3074 if (!g_ascii_strcasecmp(vm_type, "pr")) { 3075 return 2; 3076 } 3077 3078 error_report("Unknown kvm-type specified '%s'", vm_type); 3079 exit(1); 3080 } 3081 3082 /* 3083 * Implementation of an interface to adjust firmware path 3084 * for the bootindex property handling. 3085 */ 3086 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3087 DeviceState *dev) 3088 { 3089 #define CAST(type, obj, name) \ 3090 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3091 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3092 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3093 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3094 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3095 3096 if (d && bus) { 3097 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3098 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3099 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3100 3101 if (spapr) { 3102 /* 3103 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3104 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3105 * 0x8000 | (target << 8) | (bus << 5) | lun 3106 * (see the "Logical unit addressing format" table in SAM5) 3107 */ 3108 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3109 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3110 (uint64_t)id << 48); 3111 } else if (virtio) { 3112 /* 3113 * We use SRP luns of the form 01000000 | (target << 8) | lun 3114 * in the top 32 bits of the 64-bit LUN 3115 * Note: the quote above is from SLOF and it is wrong, 3116 * the actual binding is: 3117 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3118 */ 3119 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3120 if (d->lun >= 256) { 3121 /* Use the LUN "flat space addressing method" */ 3122 id |= 0x4000; 3123 } 3124 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3125 (uint64_t)id << 32); 3126 } else if (usb) { 3127 /* 3128 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3129 * in the top 32 bits of the 64-bit LUN 3130 */ 3131 unsigned usb_port = atoi(usb->port->path); 3132 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3133 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3134 (uint64_t)id << 32); 3135 } 3136 } 3137 3138 /* 3139 * SLOF probes the USB devices, and if it recognizes that the device is a 3140 * storage device, it changes its name to "storage" instead of "usb-host", 3141 * and additionally adds a child node for the SCSI LUN, so the correct 3142 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3143 */ 3144 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3145 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3146 if (usb_device_is_scsi_storage(usbdev)) { 3147 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3148 } 3149 } 3150 3151 if (phb) { 3152 /* Replace "pci" with "pci@800000020000000" */ 3153 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3154 } 3155 3156 if (vsc) { 3157 /* Same logic as virtio above */ 3158 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3159 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3160 } 3161 3162 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3163 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3164 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3165 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3166 } 3167 3168 if (pcidev) { 3169 return spapr_pci_fw_dev_name(pcidev); 3170 } 3171 3172 return NULL; 3173 } 3174 3175 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3176 { 3177 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3178 3179 return g_strdup(spapr->kvm_type); 3180 } 3181 3182 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3183 { 3184 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3185 3186 g_free(spapr->kvm_type); 3187 spapr->kvm_type = g_strdup(value); 3188 } 3189 3190 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3191 { 3192 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3193 3194 return spapr->use_hotplug_event_source; 3195 } 3196 3197 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3198 Error **errp) 3199 { 3200 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3201 3202 spapr->use_hotplug_event_source = value; 3203 } 3204 3205 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3206 { 3207 return true; 3208 } 3209 3210 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3211 { 3212 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3213 3214 switch (spapr->resize_hpt) { 3215 case SPAPR_RESIZE_HPT_DEFAULT: 3216 return g_strdup("default"); 3217 case SPAPR_RESIZE_HPT_DISABLED: 3218 return g_strdup("disabled"); 3219 case SPAPR_RESIZE_HPT_ENABLED: 3220 return g_strdup("enabled"); 3221 case SPAPR_RESIZE_HPT_REQUIRED: 3222 return g_strdup("required"); 3223 } 3224 g_assert_not_reached(); 3225 } 3226 3227 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3228 { 3229 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3230 3231 if (strcmp(value, "default") == 0) { 3232 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3233 } else if (strcmp(value, "disabled") == 0) { 3234 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3235 } else if (strcmp(value, "enabled") == 0) { 3236 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3237 } else if (strcmp(value, "required") == 0) { 3238 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3239 } else { 3240 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3241 } 3242 } 3243 3244 static bool spapr_get_vof(Object *obj, Error **errp) 3245 { 3246 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3247 3248 return spapr->vof != NULL; 3249 } 3250 3251 static void spapr_set_vof(Object *obj, bool value, Error **errp) 3252 { 3253 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3254 3255 if (spapr->vof) { 3256 vof_cleanup(spapr->vof); 3257 g_free(spapr->vof); 3258 spapr->vof = NULL; 3259 } 3260 if (!value) { 3261 return; 3262 } 3263 spapr->vof = g_malloc0(sizeof(*spapr->vof)); 3264 } 3265 3266 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3267 { 3268 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3269 3270 if (spapr->irq == &spapr_irq_xics_legacy) { 3271 return g_strdup("legacy"); 3272 } else if (spapr->irq == &spapr_irq_xics) { 3273 return g_strdup("xics"); 3274 } else if (spapr->irq == &spapr_irq_xive) { 3275 return g_strdup("xive"); 3276 } else if (spapr->irq == &spapr_irq_dual) { 3277 return g_strdup("dual"); 3278 } 3279 g_assert_not_reached(); 3280 } 3281 3282 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3283 { 3284 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3285 3286 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3287 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3288 return; 3289 } 3290 3291 /* The legacy IRQ backend can not be set */ 3292 if (strcmp(value, "xics") == 0) { 3293 spapr->irq = &spapr_irq_xics; 3294 } else if (strcmp(value, "xive") == 0) { 3295 spapr->irq = &spapr_irq_xive; 3296 } else if (strcmp(value, "dual") == 0) { 3297 spapr->irq = &spapr_irq_dual; 3298 } else { 3299 error_setg(errp, "Bad value for \"ic-mode\" property"); 3300 } 3301 } 3302 3303 static char *spapr_get_host_model(Object *obj, Error **errp) 3304 { 3305 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3306 3307 return g_strdup(spapr->host_model); 3308 } 3309 3310 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3311 { 3312 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3313 3314 g_free(spapr->host_model); 3315 spapr->host_model = g_strdup(value); 3316 } 3317 3318 static char *spapr_get_host_serial(Object *obj, Error **errp) 3319 { 3320 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3321 3322 return g_strdup(spapr->host_serial); 3323 } 3324 3325 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3326 { 3327 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3328 3329 g_free(spapr->host_serial); 3330 spapr->host_serial = g_strdup(value); 3331 } 3332 3333 static void spapr_instance_init(Object *obj) 3334 { 3335 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3336 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3337 MachineState *ms = MACHINE(spapr); 3338 MachineClass *mc = MACHINE_GET_CLASS(ms); 3339 3340 /* 3341 * NVDIMM support went live in 5.1 without considering that, in 3342 * other archs, the user needs to enable NVDIMM support with the 3343 * 'nvdimm' machine option and the default behavior is NVDIMM 3344 * support disabled. It is too late to roll back to the standard 3345 * behavior without breaking 5.1 guests. 3346 */ 3347 if (mc->nvdimm_supported) { 3348 ms->nvdimms_state->is_enabled = true; 3349 } 3350 3351 spapr->htab_fd = -1; 3352 spapr->use_hotplug_event_source = true; 3353 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE); 3354 object_property_add_str(obj, "kvm-type", 3355 spapr_get_kvm_type, spapr_set_kvm_type); 3356 object_property_set_description(obj, "kvm-type", 3357 "Specifies the KVM virtualization mode (auto," 3358 " hv, pr). Defaults to 'auto'. This mode will use" 3359 " any available KVM module loaded in the host," 3360 " where kvm_hv takes precedence if both kvm_hv and" 3361 " kvm_pr are loaded."); 3362 object_property_add_bool(obj, "modern-hotplug-events", 3363 spapr_get_modern_hotplug_events, 3364 spapr_set_modern_hotplug_events); 3365 object_property_set_description(obj, "modern-hotplug-events", 3366 "Use dedicated hotplug event mechanism in" 3367 " place of standard EPOW events when possible" 3368 " (required for memory hot-unplug support)"); 3369 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3370 "Maximum permitted CPU compatibility mode"); 3371 3372 object_property_add_str(obj, "resize-hpt", 3373 spapr_get_resize_hpt, spapr_set_resize_hpt); 3374 object_property_set_description(obj, "resize-hpt", 3375 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3376 object_property_add_uint32_ptr(obj, "vsmt", 3377 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3378 object_property_set_description(obj, "vsmt", 3379 "Virtual SMT: KVM behaves as if this were" 3380 " the host's SMT mode"); 3381 3382 object_property_add_bool(obj, "vfio-no-msix-emulation", 3383 spapr_get_msix_emulation, NULL); 3384 3385 object_property_add_uint64_ptr(obj, "kernel-addr", 3386 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3387 object_property_set_description(obj, "kernel-addr", 3388 stringify(KERNEL_LOAD_ADDR) 3389 " for -kernel is the default"); 3390 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3391 3392 object_property_add_bool(obj, "x-vof", spapr_get_vof, spapr_set_vof); 3393 object_property_set_description(obj, "x-vof", 3394 "Enable Virtual Open Firmware (experimental)"); 3395 3396 /* The machine class defines the default interrupt controller mode */ 3397 spapr->irq = smc->irq; 3398 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3399 spapr_set_ic_mode); 3400 object_property_set_description(obj, "ic-mode", 3401 "Specifies the interrupt controller mode (xics, xive, dual)"); 3402 3403 object_property_add_str(obj, "host-model", 3404 spapr_get_host_model, spapr_set_host_model); 3405 object_property_set_description(obj, "host-model", 3406 "Host model to advertise in guest device tree"); 3407 object_property_add_str(obj, "host-serial", 3408 spapr_get_host_serial, spapr_set_host_serial); 3409 object_property_set_description(obj, "host-serial", 3410 "Host serial number to advertise in guest device tree"); 3411 } 3412 3413 static void spapr_machine_finalizefn(Object *obj) 3414 { 3415 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3416 3417 g_free(spapr->kvm_type); 3418 } 3419 3420 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3421 { 3422 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3423 PowerPCCPU *cpu = POWERPC_CPU(cs); 3424 CPUPPCState *env = &cpu->env; 3425 3426 cpu_synchronize_state(cs); 3427 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3428 if (spapr->fwnmi_system_reset_addr != -1) { 3429 uint64_t rtas_addr, addr; 3430 3431 /* get rtas addr from fdt */ 3432 rtas_addr = spapr_get_rtas_addr(); 3433 if (!rtas_addr) { 3434 qemu_system_guest_panicked(NULL); 3435 return; 3436 } 3437 3438 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3439 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3440 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3441 env->gpr[3] = addr; 3442 } 3443 ppc_cpu_do_system_reset(cs); 3444 if (spapr->fwnmi_system_reset_addr != -1) { 3445 env->nip = spapr->fwnmi_system_reset_addr; 3446 } 3447 } 3448 3449 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3450 { 3451 CPUState *cs; 3452 3453 CPU_FOREACH(cs) { 3454 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3455 } 3456 } 3457 3458 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3459 void *fdt, int *fdt_start_offset, Error **errp) 3460 { 3461 uint64_t addr; 3462 uint32_t node; 3463 3464 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3465 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3466 &error_abort); 3467 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3468 SPAPR_MEMORY_BLOCK_SIZE); 3469 return 0; 3470 } 3471 3472 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3473 bool dedicated_hp_event_source) 3474 { 3475 SpaprDrc *drc; 3476 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3477 int i; 3478 uint64_t addr = addr_start; 3479 bool hotplugged = spapr_drc_hotplugged(dev); 3480 3481 for (i = 0; i < nr_lmbs; i++) { 3482 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3483 addr / SPAPR_MEMORY_BLOCK_SIZE); 3484 g_assert(drc); 3485 3486 /* 3487 * memory_device_get_free_addr() provided a range of free addresses 3488 * that doesn't overlap with any existing mapping at pre-plug. The 3489 * corresponding LMB DRCs are thus assumed to be all attachable. 3490 */ 3491 spapr_drc_attach(drc, dev); 3492 if (!hotplugged) { 3493 spapr_drc_reset(drc); 3494 } 3495 addr += SPAPR_MEMORY_BLOCK_SIZE; 3496 } 3497 /* send hotplug notification to the 3498 * guest only in case of hotplugged memory 3499 */ 3500 if (hotplugged) { 3501 if (dedicated_hp_event_source) { 3502 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3503 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3504 g_assert(drc); 3505 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3506 nr_lmbs, 3507 spapr_drc_index(drc)); 3508 } else { 3509 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3510 nr_lmbs); 3511 } 3512 } 3513 } 3514 3515 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3516 { 3517 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3518 PCDIMMDevice *dimm = PC_DIMM(dev); 3519 uint64_t size, addr; 3520 int64_t slot; 3521 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3522 3523 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3524 3525 pc_dimm_plug(dimm, MACHINE(ms)); 3526 3527 if (!is_nvdimm) { 3528 addr = object_property_get_uint(OBJECT(dimm), 3529 PC_DIMM_ADDR_PROP, &error_abort); 3530 spapr_add_lmbs(dev, addr, size, 3531 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT)); 3532 } else { 3533 slot = object_property_get_int(OBJECT(dimm), 3534 PC_DIMM_SLOT_PROP, &error_abort); 3535 /* We should have valid slot number at this point */ 3536 g_assert(slot >= 0); 3537 spapr_add_nvdimm(dev, slot); 3538 } 3539 } 3540 3541 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3542 Error **errp) 3543 { 3544 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3545 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3546 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3547 PCDIMMDevice *dimm = PC_DIMM(dev); 3548 Error *local_err = NULL; 3549 uint64_t size; 3550 Object *memdev; 3551 hwaddr pagesize; 3552 3553 if (!smc->dr_lmb_enabled) { 3554 error_setg(errp, "Memory hotplug not supported for this machine"); 3555 return; 3556 } 3557 3558 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3559 if (local_err) { 3560 error_propagate(errp, local_err); 3561 return; 3562 } 3563 3564 if (is_nvdimm) { 3565 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3566 return; 3567 } 3568 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3569 error_setg(errp, "Hotplugged memory size must be a multiple of " 3570 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3571 return; 3572 } 3573 3574 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3575 &error_abort); 3576 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3577 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3578 return; 3579 } 3580 3581 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3582 } 3583 3584 struct SpaprDimmState { 3585 PCDIMMDevice *dimm; 3586 uint32_t nr_lmbs; 3587 QTAILQ_ENTRY(SpaprDimmState) next; 3588 }; 3589 3590 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3591 PCDIMMDevice *dimm) 3592 { 3593 SpaprDimmState *dimm_state = NULL; 3594 3595 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3596 if (dimm_state->dimm == dimm) { 3597 break; 3598 } 3599 } 3600 return dimm_state; 3601 } 3602 3603 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3604 uint32_t nr_lmbs, 3605 PCDIMMDevice *dimm) 3606 { 3607 SpaprDimmState *ds = NULL; 3608 3609 /* 3610 * If this request is for a DIMM whose removal had failed earlier 3611 * (due to guest's refusal to remove the LMBs), we would have this 3612 * dimm already in the pending_dimm_unplugs list. In that 3613 * case don't add again. 3614 */ 3615 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3616 if (!ds) { 3617 ds = g_new0(SpaprDimmState, 1); 3618 ds->nr_lmbs = nr_lmbs; 3619 ds->dimm = dimm; 3620 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3621 } 3622 return ds; 3623 } 3624 3625 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3626 SpaprDimmState *dimm_state) 3627 { 3628 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3629 g_free(dimm_state); 3630 } 3631 3632 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3633 PCDIMMDevice *dimm) 3634 { 3635 SpaprDrc *drc; 3636 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3637 &error_abort); 3638 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3639 uint32_t avail_lmbs = 0; 3640 uint64_t addr_start, addr; 3641 int i; 3642 3643 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3644 &error_abort); 3645 3646 addr = addr_start; 3647 for (i = 0; i < nr_lmbs; i++) { 3648 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3649 addr / SPAPR_MEMORY_BLOCK_SIZE); 3650 g_assert(drc); 3651 if (drc->dev) { 3652 avail_lmbs++; 3653 } 3654 addr += SPAPR_MEMORY_BLOCK_SIZE; 3655 } 3656 3657 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3658 } 3659 3660 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev) 3661 { 3662 SpaprDimmState *ds; 3663 PCDIMMDevice *dimm; 3664 SpaprDrc *drc; 3665 uint32_t nr_lmbs; 3666 uint64_t size, addr_start, addr; 3667 g_autofree char *qapi_error = NULL; 3668 int i; 3669 3670 if (!dev) { 3671 return; 3672 } 3673 3674 dimm = PC_DIMM(dev); 3675 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3676 3677 /* 3678 * 'ds == NULL' would mean that the DIMM doesn't have a pending 3679 * unplug state, but one of its DRC is marked as unplug_requested. 3680 * This is bad and weird enough to g_assert() out. 3681 */ 3682 g_assert(ds); 3683 3684 spapr_pending_dimm_unplugs_remove(spapr, ds); 3685 3686 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3687 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3688 3689 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3690 &error_abort); 3691 3692 addr = addr_start; 3693 for (i = 0; i < nr_lmbs; i++) { 3694 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3695 addr / SPAPR_MEMORY_BLOCK_SIZE); 3696 g_assert(drc); 3697 3698 drc->unplug_requested = false; 3699 addr += SPAPR_MEMORY_BLOCK_SIZE; 3700 } 3701 3702 /* 3703 * Tell QAPI that something happened and the memory 3704 * hotunplug wasn't successful. Keep sending 3705 * MEM_UNPLUG_ERROR even while sending 3706 * DEVICE_UNPLUG_GUEST_ERROR until the deprecation of 3707 * MEM_UNPLUG_ERROR is due. 3708 */ 3709 qapi_error = g_strdup_printf("Memory hotunplug rejected by the guest " 3710 "for device %s", dev->id); 3711 3712 qapi_event_send_mem_unplug_error(dev->id ? : "", qapi_error); 3713 3714 qapi_event_send_device_unplug_guest_error(!!dev->id, dev->id, 3715 dev->canonical_path); 3716 } 3717 3718 /* Callback to be called during DRC release. */ 3719 void spapr_lmb_release(DeviceState *dev) 3720 { 3721 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3722 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3723 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3724 3725 /* This information will get lost if a migration occurs 3726 * during the unplug process. In this case recover it. */ 3727 if (ds == NULL) { 3728 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3729 g_assert(ds); 3730 /* The DRC being examined by the caller at least must be counted */ 3731 g_assert(ds->nr_lmbs); 3732 } 3733 3734 if (--ds->nr_lmbs) { 3735 return; 3736 } 3737 3738 /* 3739 * Now that all the LMBs have been removed by the guest, call the 3740 * unplug handler chain. This can never fail. 3741 */ 3742 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3743 object_unparent(OBJECT(dev)); 3744 } 3745 3746 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3747 { 3748 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3749 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3750 3751 /* We really shouldn't get this far without anything to unplug */ 3752 g_assert(ds); 3753 3754 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3755 qdev_unrealize(dev); 3756 spapr_pending_dimm_unplugs_remove(spapr, ds); 3757 } 3758 3759 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3760 DeviceState *dev, Error **errp) 3761 { 3762 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3763 PCDIMMDevice *dimm = PC_DIMM(dev); 3764 uint32_t nr_lmbs; 3765 uint64_t size, addr_start, addr; 3766 int i; 3767 SpaprDrc *drc; 3768 3769 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3770 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3771 return; 3772 } 3773 3774 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3775 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3776 3777 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3778 &error_abort); 3779 3780 /* 3781 * An existing pending dimm state for this DIMM means that there is an 3782 * unplug operation in progress, waiting for the spapr_lmb_release 3783 * callback to complete the job (BQL can't cover that far). In this case, 3784 * bail out to avoid detaching DRCs that were already released. 3785 */ 3786 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3787 error_setg(errp, "Memory unplug already in progress for device %s", 3788 dev->id); 3789 return; 3790 } 3791 3792 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3793 3794 addr = addr_start; 3795 for (i = 0; i < nr_lmbs; i++) { 3796 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3797 addr / SPAPR_MEMORY_BLOCK_SIZE); 3798 g_assert(drc); 3799 3800 spapr_drc_unplug_request(drc); 3801 addr += SPAPR_MEMORY_BLOCK_SIZE; 3802 } 3803 3804 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3805 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3806 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3807 nr_lmbs, spapr_drc_index(drc)); 3808 } 3809 3810 /* Callback to be called during DRC release. */ 3811 void spapr_core_release(DeviceState *dev) 3812 { 3813 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3814 3815 /* Call the unplug handler chain. This can never fail. */ 3816 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3817 object_unparent(OBJECT(dev)); 3818 } 3819 3820 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3821 { 3822 MachineState *ms = MACHINE(hotplug_dev); 3823 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3824 CPUCore *cc = CPU_CORE(dev); 3825 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3826 3827 if (smc->pre_2_10_has_unused_icps) { 3828 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3829 int i; 3830 3831 for (i = 0; i < cc->nr_threads; i++) { 3832 CPUState *cs = CPU(sc->threads[i]); 3833 3834 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3835 } 3836 } 3837 3838 assert(core_slot); 3839 core_slot->cpu = NULL; 3840 qdev_unrealize(dev); 3841 } 3842 3843 static 3844 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3845 Error **errp) 3846 { 3847 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3848 int index; 3849 SpaprDrc *drc; 3850 CPUCore *cc = CPU_CORE(dev); 3851 3852 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3853 error_setg(errp, "Unable to find CPU core with core-id: %d", 3854 cc->core_id); 3855 return; 3856 } 3857 if (index == 0) { 3858 error_setg(errp, "Boot CPU core may not be unplugged"); 3859 return; 3860 } 3861 3862 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3863 spapr_vcpu_id(spapr, cc->core_id)); 3864 g_assert(drc); 3865 3866 if (!spapr_drc_unplug_requested(drc)) { 3867 spapr_drc_unplug_request(drc); 3868 } 3869 3870 /* 3871 * spapr_hotplug_req_remove_by_index is left unguarded, out of the 3872 * "!spapr_drc_unplug_requested" check, to allow for multiple IRQ 3873 * pulses removing the same CPU. Otherwise, in an failed hotunplug 3874 * attempt (e.g. the kernel will refuse to remove the last online 3875 * CPU), we will never attempt it again because unplug_requested 3876 * will still be 'true' in that case. 3877 */ 3878 spapr_hotplug_req_remove_by_index(drc); 3879 } 3880 3881 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3882 void *fdt, int *fdt_start_offset, Error **errp) 3883 { 3884 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3885 CPUState *cs = CPU(core->threads[0]); 3886 PowerPCCPU *cpu = POWERPC_CPU(cs); 3887 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3888 int id = spapr_get_vcpu_id(cpu); 3889 g_autofree char *nodename = NULL; 3890 int offset; 3891 3892 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3893 offset = fdt_add_subnode(fdt, 0, nodename); 3894 3895 spapr_dt_cpu(cs, fdt, offset, spapr); 3896 3897 /* 3898 * spapr_dt_cpu() does not fill the 'name' property in the 3899 * CPU node. The function is called during boot process, before 3900 * and after CAS, and overwriting the 'name' property written 3901 * by SLOF is not allowed. 3902 * 3903 * Write it manually after spapr_dt_cpu(). This makes the hotplug 3904 * CPUs more compatible with the coldplugged ones, which have 3905 * the 'name' property. Linux Kernel also relies on this 3906 * property to identify CPU nodes. 3907 */ 3908 _FDT((fdt_setprop_string(fdt, offset, "name", nodename))); 3909 3910 *fdt_start_offset = offset; 3911 return 0; 3912 } 3913 3914 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3915 { 3916 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3917 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3918 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3919 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3920 CPUCore *cc = CPU_CORE(dev); 3921 CPUState *cs; 3922 SpaprDrc *drc; 3923 CPUArchId *core_slot; 3924 int index; 3925 bool hotplugged = spapr_drc_hotplugged(dev); 3926 int i; 3927 3928 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3929 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */ 3930 3931 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3932 spapr_vcpu_id(spapr, cc->core_id)); 3933 3934 g_assert(drc || !mc->has_hotpluggable_cpus); 3935 3936 if (drc) { 3937 /* 3938 * spapr_core_pre_plug() already buys us this is a brand new 3939 * core being plugged into a free slot. Nothing should already 3940 * be attached to the corresponding DRC. 3941 */ 3942 spapr_drc_attach(drc, dev); 3943 3944 if (hotplugged) { 3945 /* 3946 * Send hotplug notification interrupt to the guest only 3947 * in case of hotplugged CPUs. 3948 */ 3949 spapr_hotplug_req_add_by_index(drc); 3950 } else { 3951 spapr_drc_reset(drc); 3952 } 3953 } 3954 3955 core_slot->cpu = OBJECT(dev); 3956 3957 /* 3958 * Set compatibility mode to match the boot CPU, which was either set 3959 * by the machine reset code or by CAS. This really shouldn't fail at 3960 * this point. 3961 */ 3962 if (hotplugged) { 3963 for (i = 0; i < cc->nr_threads; i++) { 3964 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3965 &error_abort); 3966 } 3967 } 3968 3969 if (smc->pre_2_10_has_unused_icps) { 3970 for (i = 0; i < cc->nr_threads; i++) { 3971 cs = CPU(core->threads[i]); 3972 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3973 } 3974 } 3975 } 3976 3977 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3978 Error **errp) 3979 { 3980 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3981 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3982 CPUCore *cc = CPU_CORE(dev); 3983 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3984 const char *type = object_get_typename(OBJECT(dev)); 3985 CPUArchId *core_slot; 3986 int index; 3987 unsigned int smp_threads = machine->smp.threads; 3988 3989 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3990 error_setg(errp, "CPU hotplug not supported for this machine"); 3991 return; 3992 } 3993 3994 if (strcmp(base_core_type, type)) { 3995 error_setg(errp, "CPU core type should be %s", base_core_type); 3996 return; 3997 } 3998 3999 if (cc->core_id % smp_threads) { 4000 error_setg(errp, "invalid core id %d", cc->core_id); 4001 return; 4002 } 4003 4004 /* 4005 * In general we should have homogeneous threads-per-core, but old 4006 * (pre hotplug support) machine types allow the last core to have 4007 * reduced threads as a compatibility hack for when we allowed 4008 * total vcpus not a multiple of threads-per-core. 4009 */ 4010 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 4011 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 4012 smp_threads); 4013 return; 4014 } 4015 4016 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 4017 if (!core_slot) { 4018 error_setg(errp, "core id %d out of range", cc->core_id); 4019 return; 4020 } 4021 4022 if (core_slot->cpu) { 4023 error_setg(errp, "core %d already populated", cc->core_id); 4024 return; 4025 } 4026 4027 numa_cpu_pre_plug(core_slot, dev, errp); 4028 } 4029 4030 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 4031 void *fdt, int *fdt_start_offset, Error **errp) 4032 { 4033 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 4034 int intc_phandle; 4035 4036 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 4037 if (intc_phandle <= 0) { 4038 return -1; 4039 } 4040 4041 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 4042 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 4043 return -1; 4044 } 4045 4046 /* generally SLOF creates these, for hotplug it's up to QEMU */ 4047 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 4048 4049 return 0; 4050 } 4051 4052 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4053 Error **errp) 4054 { 4055 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4056 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4057 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4058 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 4059 SpaprDrc *drc; 4060 4061 if (dev->hotplugged && !smc->dr_phb_enabled) { 4062 error_setg(errp, "PHB hotplug not supported for this machine"); 4063 return false; 4064 } 4065 4066 if (sphb->index == (uint32_t)-1) { 4067 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 4068 return false; 4069 } 4070 4071 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4072 if (drc && drc->dev) { 4073 error_setg(errp, "PHB %d already attached", sphb->index); 4074 return false; 4075 } 4076 4077 /* 4078 * This will check that sphb->index doesn't exceed the maximum number of 4079 * PHBs for the current machine type. 4080 */ 4081 return 4082 smc->phb_placement(spapr, sphb->index, 4083 &sphb->buid, &sphb->io_win_addr, 4084 &sphb->mem_win_addr, &sphb->mem64_win_addr, 4085 windows_supported, sphb->dma_liobn, 4086 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 4087 errp); 4088 } 4089 4090 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4091 { 4092 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4093 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4094 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4095 SpaprDrc *drc; 4096 bool hotplugged = spapr_drc_hotplugged(dev); 4097 4098 if (!smc->dr_phb_enabled) { 4099 return; 4100 } 4101 4102 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4103 /* hotplug hooks should check it's enabled before getting this far */ 4104 assert(drc); 4105 4106 /* spapr_phb_pre_plug() already checked the DRC is attachable */ 4107 spapr_drc_attach(drc, dev); 4108 4109 if (hotplugged) { 4110 spapr_hotplug_req_add_by_index(drc); 4111 } else { 4112 spapr_drc_reset(drc); 4113 } 4114 } 4115 4116 void spapr_phb_release(DeviceState *dev) 4117 { 4118 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4119 4120 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4121 object_unparent(OBJECT(dev)); 4122 } 4123 4124 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4125 { 4126 qdev_unrealize(dev); 4127 } 4128 4129 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4130 DeviceState *dev, Error **errp) 4131 { 4132 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4133 SpaprDrc *drc; 4134 4135 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4136 assert(drc); 4137 4138 if (!spapr_drc_unplug_requested(drc)) { 4139 spapr_drc_unplug_request(drc); 4140 spapr_hotplug_req_remove_by_index(drc); 4141 } else { 4142 error_setg(errp, 4143 "PCI Host Bridge unplug already in progress for device %s", 4144 dev->id); 4145 } 4146 } 4147 4148 static 4149 bool spapr_tpm_proxy_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4150 Error **errp) 4151 { 4152 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4153 4154 if (spapr->tpm_proxy != NULL) { 4155 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4156 return false; 4157 } 4158 4159 return true; 4160 } 4161 4162 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4163 { 4164 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4165 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4166 4167 /* Already checked in spapr_tpm_proxy_pre_plug() */ 4168 g_assert(spapr->tpm_proxy == NULL); 4169 4170 spapr->tpm_proxy = tpm_proxy; 4171 } 4172 4173 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4174 { 4175 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4176 4177 qdev_unrealize(dev); 4178 object_unparent(OBJECT(dev)); 4179 spapr->tpm_proxy = NULL; 4180 } 4181 4182 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4183 DeviceState *dev, Error **errp) 4184 { 4185 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4186 spapr_memory_plug(hotplug_dev, dev); 4187 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4188 spapr_core_plug(hotplug_dev, dev); 4189 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4190 spapr_phb_plug(hotplug_dev, dev); 4191 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4192 spapr_tpm_proxy_plug(hotplug_dev, dev); 4193 } 4194 } 4195 4196 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4197 DeviceState *dev, Error **errp) 4198 { 4199 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4200 spapr_memory_unplug(hotplug_dev, dev); 4201 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4202 spapr_core_unplug(hotplug_dev, dev); 4203 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4204 spapr_phb_unplug(hotplug_dev, dev); 4205 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4206 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4207 } 4208 } 4209 4210 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr) 4211 { 4212 return spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT) || 4213 /* 4214 * CAS will process all pending unplug requests. 4215 * 4216 * HACK: a guest could theoretically have cleared all bits in OV5, 4217 * but none of the guests we care for do. 4218 */ 4219 spapr_ovec_empty(spapr->ov5_cas); 4220 } 4221 4222 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4223 DeviceState *dev, Error **errp) 4224 { 4225 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4226 MachineClass *mc = MACHINE_GET_CLASS(sms); 4227 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4228 4229 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4230 if (spapr_memory_hot_unplug_supported(sms)) { 4231 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4232 } else { 4233 error_setg(errp, "Memory hot unplug not supported for this guest"); 4234 } 4235 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4236 if (!mc->has_hotpluggable_cpus) { 4237 error_setg(errp, "CPU hot unplug not supported on this machine"); 4238 return; 4239 } 4240 spapr_core_unplug_request(hotplug_dev, dev, errp); 4241 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4242 if (!smc->dr_phb_enabled) { 4243 error_setg(errp, "PHB hot unplug not supported on this machine"); 4244 return; 4245 } 4246 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4247 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4248 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4249 } 4250 } 4251 4252 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4253 DeviceState *dev, Error **errp) 4254 { 4255 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4256 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4257 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4258 spapr_core_pre_plug(hotplug_dev, dev, errp); 4259 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4260 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4261 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4262 spapr_tpm_proxy_pre_plug(hotplug_dev, dev, errp); 4263 } 4264 } 4265 4266 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4267 DeviceState *dev) 4268 { 4269 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4270 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4271 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4272 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4273 return HOTPLUG_HANDLER(machine); 4274 } 4275 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4276 PCIDevice *pcidev = PCI_DEVICE(dev); 4277 PCIBus *root = pci_device_root_bus(pcidev); 4278 SpaprPhbState *phb = 4279 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4280 TYPE_SPAPR_PCI_HOST_BRIDGE); 4281 4282 if (phb) { 4283 return HOTPLUG_HANDLER(phb); 4284 } 4285 } 4286 return NULL; 4287 } 4288 4289 static CpuInstanceProperties 4290 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4291 { 4292 CPUArchId *core_slot; 4293 MachineClass *mc = MACHINE_GET_CLASS(machine); 4294 4295 /* make sure possible_cpu are intialized */ 4296 mc->possible_cpu_arch_ids(machine); 4297 /* get CPU core slot containing thread that matches cpu_index */ 4298 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4299 assert(core_slot); 4300 return core_slot->props; 4301 } 4302 4303 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4304 { 4305 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4306 } 4307 4308 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4309 { 4310 int i; 4311 unsigned int smp_threads = machine->smp.threads; 4312 unsigned int smp_cpus = machine->smp.cpus; 4313 const char *core_type; 4314 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4315 MachineClass *mc = MACHINE_GET_CLASS(machine); 4316 4317 if (!mc->has_hotpluggable_cpus) { 4318 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4319 } 4320 if (machine->possible_cpus) { 4321 assert(machine->possible_cpus->len == spapr_max_cores); 4322 return machine->possible_cpus; 4323 } 4324 4325 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4326 if (!core_type) { 4327 error_report("Unable to find sPAPR CPU Core definition"); 4328 exit(1); 4329 } 4330 4331 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4332 sizeof(CPUArchId) * spapr_max_cores); 4333 machine->possible_cpus->len = spapr_max_cores; 4334 for (i = 0; i < machine->possible_cpus->len; i++) { 4335 int core_id = i * smp_threads; 4336 4337 machine->possible_cpus->cpus[i].type = core_type; 4338 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4339 machine->possible_cpus->cpus[i].arch_id = core_id; 4340 machine->possible_cpus->cpus[i].props.has_core_id = true; 4341 machine->possible_cpus->cpus[i].props.core_id = core_id; 4342 } 4343 return machine->possible_cpus; 4344 } 4345 4346 static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4347 uint64_t *buid, hwaddr *pio, 4348 hwaddr *mmio32, hwaddr *mmio64, 4349 unsigned n_dma, uint32_t *liobns, 4350 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4351 { 4352 /* 4353 * New-style PHB window placement. 4354 * 4355 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4356 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4357 * windows. 4358 * 4359 * Some guest kernels can't work with MMIO windows above 1<<46 4360 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4361 * 4362 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4363 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4364 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4365 * 1TiB 64-bit MMIO windows for each PHB. 4366 */ 4367 const uint64_t base_buid = 0x800000020000000ULL; 4368 int i; 4369 4370 /* Sanity check natural alignments */ 4371 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4372 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4373 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4374 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4375 /* Sanity check bounds */ 4376 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4377 SPAPR_PCI_MEM32_WIN_SIZE); 4378 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4379 SPAPR_PCI_MEM64_WIN_SIZE); 4380 4381 if (index >= SPAPR_MAX_PHBS) { 4382 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4383 SPAPR_MAX_PHBS - 1); 4384 return false; 4385 } 4386 4387 *buid = base_buid + index; 4388 for (i = 0; i < n_dma; ++i) { 4389 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4390 } 4391 4392 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4393 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4394 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4395 4396 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4397 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4398 return true; 4399 } 4400 4401 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4402 { 4403 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4404 4405 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4406 } 4407 4408 static void spapr_ics_resend(XICSFabric *dev) 4409 { 4410 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4411 4412 ics_resend(spapr->ics); 4413 } 4414 4415 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4416 { 4417 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4418 4419 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4420 } 4421 4422 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4423 Monitor *mon) 4424 { 4425 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4426 4427 spapr_irq_print_info(spapr, mon); 4428 monitor_printf(mon, "irqchip: %s\n", 4429 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4430 } 4431 4432 /* 4433 * This is a XIVE only operation 4434 */ 4435 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4436 uint8_t nvt_blk, uint32_t nvt_idx, 4437 bool cam_ignore, uint8_t priority, 4438 uint32_t logic_serv, XiveTCTXMatch *match) 4439 { 4440 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4441 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4442 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4443 int count; 4444 4445 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4446 priority, logic_serv, match); 4447 if (count < 0) { 4448 return count; 4449 } 4450 4451 /* 4452 * When we implement the save and restore of the thread interrupt 4453 * contexts in the enter/exit CPU handlers of the machine and the 4454 * escalations in QEMU, we should be able to handle non dispatched 4455 * vCPUs. 4456 * 4457 * Until this is done, the sPAPR machine should find at least one 4458 * matching context always. 4459 */ 4460 if (count == 0) { 4461 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4462 nvt_blk, nvt_idx); 4463 } 4464 4465 return count; 4466 } 4467 4468 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4469 { 4470 return cpu->vcpu_id; 4471 } 4472 4473 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4474 { 4475 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4476 MachineState *ms = MACHINE(spapr); 4477 int vcpu_id; 4478 4479 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4480 4481 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4482 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4483 error_append_hint(errp, "Adjust the number of cpus to %d " 4484 "or try to raise the number of threads per core\n", 4485 vcpu_id * ms->smp.threads / spapr->vsmt); 4486 return false; 4487 } 4488 4489 cpu->vcpu_id = vcpu_id; 4490 return true; 4491 } 4492 4493 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4494 { 4495 CPUState *cs; 4496 4497 CPU_FOREACH(cs) { 4498 PowerPCCPU *cpu = POWERPC_CPU(cs); 4499 4500 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4501 return cpu; 4502 } 4503 } 4504 4505 return NULL; 4506 } 4507 4508 static bool spapr_cpu_in_nested(PowerPCCPU *cpu) 4509 { 4510 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4511 4512 return spapr_cpu->in_nested; 4513 } 4514 4515 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4516 { 4517 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4518 4519 /* These are only called by TCG, KVM maintains dispatch state */ 4520 4521 spapr_cpu->prod = false; 4522 if (spapr_cpu->vpa_addr) { 4523 CPUState *cs = CPU(cpu); 4524 uint32_t dispatch; 4525 4526 dispatch = ldl_be_phys(cs->as, 4527 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4528 dispatch++; 4529 if ((dispatch & 1) != 0) { 4530 qemu_log_mask(LOG_GUEST_ERROR, 4531 "VPA: incorrect dispatch counter value for " 4532 "dispatched partition %u, correcting.\n", dispatch); 4533 dispatch++; 4534 } 4535 stl_be_phys(cs->as, 4536 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4537 } 4538 } 4539 4540 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4541 { 4542 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4543 4544 if (spapr_cpu->vpa_addr) { 4545 CPUState *cs = CPU(cpu); 4546 uint32_t dispatch; 4547 4548 dispatch = ldl_be_phys(cs->as, 4549 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4550 dispatch++; 4551 if ((dispatch & 1) != 1) { 4552 qemu_log_mask(LOG_GUEST_ERROR, 4553 "VPA: incorrect dispatch counter value for " 4554 "preempted partition %u, correcting.\n", dispatch); 4555 dispatch++; 4556 } 4557 stl_be_phys(cs->as, 4558 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4559 } 4560 } 4561 4562 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4563 { 4564 MachineClass *mc = MACHINE_CLASS(oc); 4565 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4566 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4567 NMIClass *nc = NMI_CLASS(oc); 4568 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4569 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4570 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4571 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4572 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4573 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc); 4574 4575 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4576 mc->ignore_boot_device_suffixes = true; 4577 4578 /* 4579 * We set up the default / latest behaviour here. The class_init 4580 * functions for the specific versioned machine types can override 4581 * these details for backwards compatibility 4582 */ 4583 mc->init = spapr_machine_init; 4584 mc->reset = spapr_machine_reset; 4585 mc->block_default_type = IF_SCSI; 4586 4587 /* 4588 * Setting max_cpus to INT32_MAX. Both KVM and TCG max_cpus values 4589 * should be limited by the host capability instead of hardcoded. 4590 * max_cpus for KVM guests will be checked in kvm_init(), and TCG 4591 * guests are welcome to have as many CPUs as the host are capable 4592 * of emulate. 4593 */ 4594 mc->max_cpus = INT32_MAX; 4595 4596 mc->no_parallel = 1; 4597 mc->default_boot_order = ""; 4598 mc->default_ram_size = 512 * MiB; 4599 mc->default_ram_id = "ppc_spapr.ram"; 4600 mc->default_display = "std"; 4601 mc->kvm_type = spapr_kvm_type; 4602 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4603 mc->pci_allow_0_address = true; 4604 assert(!mc->get_hotplug_handler); 4605 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4606 hc->pre_plug = spapr_machine_device_pre_plug; 4607 hc->plug = spapr_machine_device_plug; 4608 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4609 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4610 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4611 hc->unplug_request = spapr_machine_device_unplug_request; 4612 hc->unplug = spapr_machine_device_unplug; 4613 4614 smc->dr_lmb_enabled = true; 4615 smc->update_dt_enabled = true; 4616 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4617 mc->has_hotpluggable_cpus = true; 4618 mc->nvdimm_supported = true; 4619 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4620 fwc->get_dev_path = spapr_get_fw_dev_path; 4621 nc->nmi_monitor_handler = spapr_nmi; 4622 smc->phb_placement = spapr_phb_placement; 4623 vhc->cpu_in_nested = spapr_cpu_in_nested; 4624 vhc->deliver_hv_excp = spapr_exit_nested; 4625 vhc->hypercall = emulate_spapr_hypercall; 4626 vhc->hpt_mask = spapr_hpt_mask; 4627 vhc->map_hptes = spapr_map_hptes; 4628 vhc->unmap_hptes = spapr_unmap_hptes; 4629 vhc->hpte_set_c = spapr_hpte_set_c; 4630 vhc->hpte_set_r = spapr_hpte_set_r; 4631 vhc->get_pate = spapr_get_pate; 4632 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4633 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4634 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4635 xic->ics_get = spapr_ics_get; 4636 xic->ics_resend = spapr_ics_resend; 4637 xic->icp_get = spapr_icp_get; 4638 ispc->print_info = spapr_pic_print_info; 4639 /* Force NUMA node memory size to be a multiple of 4640 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4641 * in which LMBs are represented and hot-added 4642 */ 4643 mc->numa_mem_align_shift = 28; 4644 mc->auto_enable_numa = true; 4645 4646 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4647 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4648 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4649 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4650 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4651 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4652 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4653 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4654 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4655 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4656 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4657 smc->default_caps.caps[SPAPR_CAP_RPT_INVALIDATE] = SPAPR_CAP_OFF; 4658 spapr_caps_add_properties(smc); 4659 smc->irq = &spapr_irq_dual; 4660 smc->dr_phb_enabled = true; 4661 smc->linux_pci_probe = true; 4662 smc->smp_threads_vsmt = true; 4663 smc->nr_xirqs = SPAPR_NR_XIRQS; 4664 xfc->match_nvt = spapr_match_nvt; 4665 vmc->client_architecture_support = spapr_vof_client_architecture_support; 4666 vmc->quiesce = spapr_vof_quiesce; 4667 vmc->setprop = spapr_vof_setprop; 4668 } 4669 4670 static const TypeInfo spapr_machine_info = { 4671 .name = TYPE_SPAPR_MACHINE, 4672 .parent = TYPE_MACHINE, 4673 .abstract = true, 4674 .instance_size = sizeof(SpaprMachineState), 4675 .instance_init = spapr_instance_init, 4676 .instance_finalize = spapr_machine_finalizefn, 4677 .class_size = sizeof(SpaprMachineClass), 4678 .class_init = spapr_machine_class_init, 4679 .interfaces = (InterfaceInfo[]) { 4680 { TYPE_FW_PATH_PROVIDER }, 4681 { TYPE_NMI }, 4682 { TYPE_HOTPLUG_HANDLER }, 4683 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4684 { TYPE_XICS_FABRIC }, 4685 { TYPE_INTERRUPT_STATS_PROVIDER }, 4686 { TYPE_XIVE_FABRIC }, 4687 { TYPE_VOF_MACHINE_IF }, 4688 { } 4689 }, 4690 }; 4691 4692 static void spapr_machine_latest_class_options(MachineClass *mc) 4693 { 4694 mc->alias = "pseries"; 4695 mc->is_default = true; 4696 } 4697 4698 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4699 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4700 void *data) \ 4701 { \ 4702 MachineClass *mc = MACHINE_CLASS(oc); \ 4703 spapr_machine_##suffix##_class_options(mc); \ 4704 if (latest) { \ 4705 spapr_machine_latest_class_options(mc); \ 4706 } \ 4707 } \ 4708 static const TypeInfo spapr_machine_##suffix##_info = { \ 4709 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4710 .parent = TYPE_SPAPR_MACHINE, \ 4711 .class_init = spapr_machine_##suffix##_class_init, \ 4712 }; \ 4713 static void spapr_machine_register_##suffix(void) \ 4714 { \ 4715 type_register(&spapr_machine_##suffix##_info); \ 4716 } \ 4717 type_init(spapr_machine_register_##suffix) 4718 4719 /* 4720 * pseries-7.1 4721 */ 4722 static void spapr_machine_7_1_class_options(MachineClass *mc) 4723 { 4724 /* Defaults for the latest behaviour inherited from the base class */ 4725 } 4726 4727 DEFINE_SPAPR_MACHINE(7_1, "7.1", true); 4728 4729 /* 4730 * pseries-7.0 4731 */ 4732 static void spapr_machine_7_0_class_options(MachineClass *mc) 4733 { 4734 spapr_machine_7_1_class_options(mc); 4735 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 4736 } 4737 4738 DEFINE_SPAPR_MACHINE(7_0, "7.0", false); 4739 4740 /* 4741 * pseries-6.2 4742 */ 4743 static void spapr_machine_6_2_class_options(MachineClass *mc) 4744 { 4745 spapr_machine_7_0_class_options(mc); 4746 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 4747 } 4748 4749 DEFINE_SPAPR_MACHINE(6_2, "6.2", false); 4750 4751 /* 4752 * pseries-6.1 4753 */ 4754 static void spapr_machine_6_1_class_options(MachineClass *mc) 4755 { 4756 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4757 4758 spapr_machine_6_2_class_options(mc); 4759 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 4760 smc->pre_6_2_numa_affinity = true; 4761 mc->smp_props.prefer_sockets = true; 4762 } 4763 4764 DEFINE_SPAPR_MACHINE(6_1, "6.1", false); 4765 4766 /* 4767 * pseries-6.0 4768 */ 4769 static void spapr_machine_6_0_class_options(MachineClass *mc) 4770 { 4771 spapr_machine_6_1_class_options(mc); 4772 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 4773 } 4774 4775 DEFINE_SPAPR_MACHINE(6_0, "6.0", false); 4776 4777 /* 4778 * pseries-5.2 4779 */ 4780 static void spapr_machine_5_2_class_options(MachineClass *mc) 4781 { 4782 spapr_machine_6_0_class_options(mc); 4783 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 4784 } 4785 4786 DEFINE_SPAPR_MACHINE(5_2, "5.2", false); 4787 4788 /* 4789 * pseries-5.1 4790 */ 4791 static void spapr_machine_5_1_class_options(MachineClass *mc) 4792 { 4793 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4794 4795 spapr_machine_5_2_class_options(mc); 4796 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4797 smc->pre_5_2_numa_associativity = true; 4798 } 4799 4800 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4801 4802 /* 4803 * pseries-5.0 4804 */ 4805 static void spapr_machine_5_0_class_options(MachineClass *mc) 4806 { 4807 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4808 static GlobalProperty compat[] = { 4809 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4810 }; 4811 4812 spapr_machine_5_1_class_options(mc); 4813 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4814 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4815 mc->numa_mem_supported = true; 4816 smc->pre_5_1_assoc_refpoints = true; 4817 } 4818 4819 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4820 4821 /* 4822 * pseries-4.2 4823 */ 4824 static void spapr_machine_4_2_class_options(MachineClass *mc) 4825 { 4826 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4827 4828 spapr_machine_5_0_class_options(mc); 4829 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4830 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4831 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4832 smc->rma_limit = 16 * GiB; 4833 mc->nvdimm_supported = false; 4834 } 4835 4836 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4837 4838 /* 4839 * pseries-4.1 4840 */ 4841 static void spapr_machine_4_1_class_options(MachineClass *mc) 4842 { 4843 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4844 static GlobalProperty compat[] = { 4845 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4846 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4847 }; 4848 4849 spapr_machine_4_2_class_options(mc); 4850 smc->linux_pci_probe = false; 4851 smc->smp_threads_vsmt = false; 4852 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4853 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4854 } 4855 4856 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4857 4858 /* 4859 * pseries-4.0 4860 */ 4861 static bool phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4862 uint64_t *buid, hwaddr *pio, 4863 hwaddr *mmio32, hwaddr *mmio64, 4864 unsigned n_dma, uint32_t *liobns, 4865 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4866 { 4867 if (!spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, 4868 liobns, nv2gpa, nv2atsd, errp)) { 4869 return false; 4870 } 4871 4872 *nv2gpa = 0; 4873 *nv2atsd = 0; 4874 return true; 4875 } 4876 static void spapr_machine_4_0_class_options(MachineClass *mc) 4877 { 4878 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4879 4880 spapr_machine_4_1_class_options(mc); 4881 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4882 smc->phb_placement = phb_placement_4_0; 4883 smc->irq = &spapr_irq_xics; 4884 smc->pre_4_1_migration = true; 4885 } 4886 4887 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4888 4889 /* 4890 * pseries-3.1 4891 */ 4892 static void spapr_machine_3_1_class_options(MachineClass *mc) 4893 { 4894 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4895 4896 spapr_machine_4_0_class_options(mc); 4897 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4898 4899 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4900 smc->update_dt_enabled = false; 4901 smc->dr_phb_enabled = false; 4902 smc->broken_host_serial_model = true; 4903 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4904 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4905 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4906 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4907 } 4908 4909 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4910 4911 /* 4912 * pseries-3.0 4913 */ 4914 4915 static void spapr_machine_3_0_class_options(MachineClass *mc) 4916 { 4917 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4918 4919 spapr_machine_3_1_class_options(mc); 4920 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4921 4922 smc->legacy_irq_allocation = true; 4923 smc->nr_xirqs = 0x400; 4924 smc->irq = &spapr_irq_xics_legacy; 4925 } 4926 4927 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4928 4929 /* 4930 * pseries-2.12 4931 */ 4932 static void spapr_machine_2_12_class_options(MachineClass *mc) 4933 { 4934 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4935 static GlobalProperty compat[] = { 4936 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4937 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4938 }; 4939 4940 spapr_machine_3_0_class_options(mc); 4941 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4942 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4943 4944 /* We depend on kvm_enabled() to choose a default value for the 4945 * hpt-max-page-size capability. Of course we can't do it here 4946 * because this is too early and the HW accelerator isn't initialzed 4947 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4948 */ 4949 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4950 } 4951 4952 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4953 4954 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4955 { 4956 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4957 4958 spapr_machine_2_12_class_options(mc); 4959 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4960 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4961 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4962 } 4963 4964 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4965 4966 /* 4967 * pseries-2.11 4968 */ 4969 4970 static void spapr_machine_2_11_class_options(MachineClass *mc) 4971 { 4972 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4973 4974 spapr_machine_2_12_class_options(mc); 4975 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4976 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4977 } 4978 4979 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4980 4981 /* 4982 * pseries-2.10 4983 */ 4984 4985 static void spapr_machine_2_10_class_options(MachineClass *mc) 4986 { 4987 spapr_machine_2_11_class_options(mc); 4988 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4989 } 4990 4991 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4992 4993 /* 4994 * pseries-2.9 4995 */ 4996 4997 static void spapr_machine_2_9_class_options(MachineClass *mc) 4998 { 4999 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5000 static GlobalProperty compat[] = { 5001 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 5002 }; 5003 5004 spapr_machine_2_10_class_options(mc); 5005 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 5006 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5007 smc->pre_2_10_has_unused_icps = true; 5008 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 5009 } 5010 5011 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 5012 5013 /* 5014 * pseries-2.8 5015 */ 5016 5017 static void spapr_machine_2_8_class_options(MachineClass *mc) 5018 { 5019 static GlobalProperty compat[] = { 5020 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 5021 }; 5022 5023 spapr_machine_2_9_class_options(mc); 5024 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 5025 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5026 mc->numa_mem_align_shift = 23; 5027 } 5028 5029 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 5030 5031 /* 5032 * pseries-2.7 5033 */ 5034 5035 static bool phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 5036 uint64_t *buid, hwaddr *pio, 5037 hwaddr *mmio32, hwaddr *mmio64, 5038 unsigned n_dma, uint32_t *liobns, 5039 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 5040 { 5041 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 5042 const uint64_t base_buid = 0x800000020000000ULL; 5043 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 5044 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 5045 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 5046 const uint32_t max_index = 255; 5047 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 5048 5049 uint64_t ram_top = MACHINE(spapr)->ram_size; 5050 hwaddr phb0_base, phb_base; 5051 int i; 5052 5053 /* Do we have device memory? */ 5054 if (MACHINE(spapr)->maxram_size > ram_top) { 5055 /* Can't just use maxram_size, because there may be an 5056 * alignment gap between normal and device memory regions 5057 */ 5058 ram_top = MACHINE(spapr)->device_memory->base + 5059 memory_region_size(&MACHINE(spapr)->device_memory->mr); 5060 } 5061 5062 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 5063 5064 if (index > max_index) { 5065 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 5066 max_index); 5067 return false; 5068 } 5069 5070 *buid = base_buid + index; 5071 for (i = 0; i < n_dma; ++i) { 5072 liobns[i] = SPAPR_PCI_LIOBN(index, i); 5073 } 5074 5075 phb_base = phb0_base + index * phb_spacing; 5076 *pio = phb_base + pio_offset; 5077 *mmio32 = phb_base + mmio_offset; 5078 /* 5079 * We don't set the 64-bit MMIO window, relying on the PHB's 5080 * fallback behaviour of automatically splitting a large "32-bit" 5081 * window into contiguous 32-bit and 64-bit windows 5082 */ 5083 5084 *nv2gpa = 0; 5085 *nv2atsd = 0; 5086 return true; 5087 } 5088 5089 static void spapr_machine_2_7_class_options(MachineClass *mc) 5090 { 5091 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5092 static GlobalProperty compat[] = { 5093 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 5094 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 5095 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 5096 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 5097 }; 5098 5099 spapr_machine_2_8_class_options(mc); 5100 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 5101 mc->default_machine_opts = "modern-hotplug-events=off"; 5102 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 5103 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5104 smc->phb_placement = phb_placement_2_7; 5105 } 5106 5107 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 5108 5109 /* 5110 * pseries-2.6 5111 */ 5112 5113 static void spapr_machine_2_6_class_options(MachineClass *mc) 5114 { 5115 static GlobalProperty compat[] = { 5116 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 5117 }; 5118 5119 spapr_machine_2_7_class_options(mc); 5120 mc->has_hotpluggable_cpus = false; 5121 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 5122 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5123 } 5124 5125 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 5126 5127 /* 5128 * pseries-2.5 5129 */ 5130 5131 static void spapr_machine_2_5_class_options(MachineClass *mc) 5132 { 5133 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5134 static GlobalProperty compat[] = { 5135 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 5136 }; 5137 5138 spapr_machine_2_6_class_options(mc); 5139 smc->use_ohci_by_default = true; 5140 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 5141 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5142 } 5143 5144 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 5145 5146 /* 5147 * pseries-2.4 5148 */ 5149 5150 static void spapr_machine_2_4_class_options(MachineClass *mc) 5151 { 5152 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5153 5154 spapr_machine_2_5_class_options(mc); 5155 smc->dr_lmb_enabled = false; 5156 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 5157 } 5158 5159 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 5160 5161 /* 5162 * pseries-2.3 5163 */ 5164 5165 static void spapr_machine_2_3_class_options(MachineClass *mc) 5166 { 5167 static GlobalProperty compat[] = { 5168 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 5169 }; 5170 spapr_machine_2_4_class_options(mc); 5171 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 5172 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5173 } 5174 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 5175 5176 /* 5177 * pseries-2.2 5178 */ 5179 5180 static void spapr_machine_2_2_class_options(MachineClass *mc) 5181 { 5182 static GlobalProperty compat[] = { 5183 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 5184 }; 5185 5186 spapr_machine_2_3_class_options(mc); 5187 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 5188 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5189 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 5190 } 5191 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 5192 5193 /* 5194 * pseries-2.1 5195 */ 5196 5197 static void spapr_machine_2_1_class_options(MachineClass *mc) 5198 { 5199 spapr_machine_2_2_class_options(mc); 5200 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 5201 } 5202 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 5203 5204 static void spapr_machine_register_types(void) 5205 { 5206 type_register_static(&spapr_machine_info); 5207 } 5208 5209 type_init(spapr_machine_register_types) 5210