1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "sysemu/sysemu.h" 28 #include "hw/hw.h" 29 #include "elf.h" 30 #include "net/net.h" 31 #include "sysemu/blockdev.h" 32 #include "sysemu/cpus.h" 33 #include "sysemu/kvm.h" 34 #include "kvm_ppc.h" 35 36 #include "hw/boards.h" 37 #include "hw/ppc/ppc.h" 38 #include "hw/loader.h" 39 40 #include "hw/ppc/spapr.h" 41 #include "hw/ppc/spapr_vio.h" 42 #include "hw/pci-host/spapr.h" 43 #include "hw/ppc/xics.h" 44 #include "hw/pci/msi.h" 45 46 #include "hw/pci/pci.h" 47 48 #include "exec/address-spaces.h" 49 #include "hw/usb.h" 50 #include "qemu/config-file.h" 51 52 #include <libfdt.h> 53 54 /* SLOF memory layout: 55 * 56 * SLOF raw image loaded at 0, copies its romfs right below the flat 57 * device-tree, then position SLOF itself 31M below that 58 * 59 * So we set FW_OVERHEAD to 40MB which should account for all of that 60 * and more 61 * 62 * We load our kernel at 4M, leaving space for SLOF initial image 63 */ 64 #define FDT_MAX_SIZE 0x10000 65 #define RTAS_MAX_SIZE 0x10000 66 #define FW_MAX_SIZE 0x400000 67 #define FW_FILE_NAME "slof.bin" 68 #define FW_OVERHEAD 0x2800000 69 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 70 71 #define MIN_RMA_SLOF 128UL 72 73 #define TIMEBASE_FREQ 512000000ULL 74 75 #define MAX_CPUS 256 76 #define XICS_IRQS 1024 77 78 #define PHANDLE_XICP 0x00001111 79 80 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 81 82 sPAPREnvironment *spapr; 83 84 int spapr_allocate_irq(int hint, bool lsi) 85 { 86 int irq; 87 88 if (hint) { 89 irq = hint; 90 /* FIXME: we should probably check for collisions somehow */ 91 } else { 92 irq = spapr->next_irq++; 93 } 94 95 /* Configure irq type */ 96 if (!xics_get_qirq(spapr->icp, irq)) { 97 return 0; 98 } 99 100 xics_set_irq_type(spapr->icp, irq, lsi); 101 102 return irq; 103 } 104 105 /* Allocate block of consequtive IRQs, returns a number of the first */ 106 int spapr_allocate_irq_block(int num, bool lsi) 107 { 108 int first = -1; 109 int i; 110 111 for (i = 0; i < num; ++i) { 112 int irq; 113 114 irq = spapr_allocate_irq(0, lsi); 115 if (!irq) { 116 return -1; 117 } 118 119 if (0 == i) { 120 first = irq; 121 } 122 123 /* If the above doesn't create a consecutive block then that's 124 * an internal bug */ 125 assert(irq == (first + i)); 126 } 127 128 return first; 129 } 130 131 static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr) 132 { 133 int ret = 0, offset; 134 CPUState *cpu; 135 char cpu_model[32]; 136 int smt = kvmppc_smt_threads(); 137 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 138 139 assert(spapr->cpu_model); 140 141 for (cpu = first_cpu; cpu != NULL; cpu = cpu->next_cpu) { 142 uint32_t associativity[] = {cpu_to_be32(0x5), 143 cpu_to_be32(0x0), 144 cpu_to_be32(0x0), 145 cpu_to_be32(0x0), 146 cpu_to_be32(cpu->numa_node), 147 cpu_to_be32(cpu->cpu_index)}; 148 149 if ((cpu->cpu_index % smt) != 0) { 150 continue; 151 } 152 153 snprintf(cpu_model, 32, "/cpus/%s@%x", spapr->cpu_model, 154 cpu->cpu_index); 155 156 offset = fdt_path_offset(fdt, cpu_model); 157 if (offset < 0) { 158 return offset; 159 } 160 161 if (nb_numa_nodes > 1) { 162 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 163 sizeof(associativity)); 164 if (ret < 0) { 165 return ret; 166 } 167 } 168 169 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 170 pft_size_prop, sizeof(pft_size_prop)); 171 if (ret < 0) { 172 return ret; 173 } 174 } 175 return ret; 176 } 177 178 179 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, 180 size_t maxsize) 181 { 182 size_t maxcells = maxsize / sizeof(uint32_t); 183 int i, j, count; 184 uint32_t *p = prop; 185 186 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 187 struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; 188 189 if (!sps->page_shift) { 190 break; 191 } 192 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { 193 if (sps->enc[count].page_shift == 0) { 194 break; 195 } 196 } 197 if ((p - prop) >= (maxcells - 3 - count * 2)) { 198 break; 199 } 200 *(p++) = cpu_to_be32(sps->page_shift); 201 *(p++) = cpu_to_be32(sps->slb_enc); 202 *(p++) = cpu_to_be32(count); 203 for (j = 0; j < count; j++) { 204 *(p++) = cpu_to_be32(sps->enc[j].page_shift); 205 *(p++) = cpu_to_be32(sps->enc[j].pte_enc); 206 } 207 } 208 209 return (p - prop) * sizeof(uint32_t); 210 } 211 212 #define _FDT(exp) \ 213 do { \ 214 int ret = (exp); \ 215 if (ret < 0) { \ 216 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ 217 #exp, fdt_strerror(ret)); \ 218 exit(1); \ 219 } \ 220 } while (0) 221 222 223 static void *spapr_create_fdt_skel(const char *cpu_model, 224 hwaddr initrd_base, 225 hwaddr initrd_size, 226 hwaddr kernel_size, 227 const char *boot_device, 228 const char *kernel_cmdline, 229 uint32_t epow_irq) 230 { 231 void *fdt; 232 CPUState *cs; 233 uint32_t start_prop = cpu_to_be32(initrd_base); 234 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); 235 char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt" 236 "\0hcall-tce\0hcall-vio\0hcall-splpar\0hcall-bulk"; 237 char qemu_hypertas_prop[] = "hcall-memop1"; 238 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; 239 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)}; 240 char *modelname; 241 int i, smt = kvmppc_smt_threads(); 242 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; 243 244 fdt = g_malloc0(FDT_MAX_SIZE); 245 _FDT((fdt_create(fdt, FDT_MAX_SIZE))); 246 247 if (kernel_size) { 248 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); 249 } 250 if (initrd_size) { 251 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); 252 } 253 _FDT((fdt_finish_reservemap(fdt))); 254 255 /* Root node */ 256 _FDT((fdt_begin_node(fdt, ""))); 257 _FDT((fdt_property_string(fdt, "device_type", "chrp"))); 258 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); 259 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); 260 261 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); 262 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); 263 264 /* /chosen */ 265 _FDT((fdt_begin_node(fdt, "chosen"))); 266 267 /* Set Form1_affinity */ 268 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); 269 270 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); 271 _FDT((fdt_property(fdt, "linux,initrd-start", 272 &start_prop, sizeof(start_prop)))); 273 _FDT((fdt_property(fdt, "linux,initrd-end", 274 &end_prop, sizeof(end_prop)))); 275 if (kernel_size) { 276 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 277 cpu_to_be64(kernel_size) }; 278 279 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); 280 } 281 if (boot_device) { 282 _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device))); 283 } 284 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); 285 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); 286 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); 287 288 _FDT((fdt_end_node(fdt))); 289 290 /* cpus */ 291 _FDT((fdt_begin_node(fdt, "cpus"))); 292 293 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 294 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 295 296 modelname = g_strdup(cpu_model); 297 298 for (i = 0; i < strlen(modelname); i++) { 299 modelname[i] = toupper(modelname[i]); 300 } 301 302 /* This is needed during FDT finalization */ 303 spapr->cpu_model = g_strdup(modelname); 304 305 for (cs = first_cpu; cs != NULL; cs = cs->next_cpu) { 306 PowerPCCPU *cpu = POWERPC_CPU(cs); 307 CPUPPCState *env = &cpu->env; 308 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 309 int index = cs->cpu_index; 310 uint32_t servers_prop[smp_threads]; 311 uint32_t gservers_prop[smp_threads * 2]; 312 char *nodename; 313 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 314 0xffffffff, 0xffffffff}; 315 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; 316 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 317 uint32_t page_sizes_prop[64]; 318 size_t page_sizes_prop_size; 319 320 if ((index % smt) != 0) { 321 continue; 322 } 323 324 nodename = g_strdup_printf("%s@%x", modelname, index); 325 326 _FDT((fdt_begin_node(fdt, nodename))); 327 328 g_free(nodename); 329 330 _FDT((fdt_property_cell(fdt, "reg", index))); 331 _FDT((fdt_property_string(fdt, "device_type", "cpu"))); 332 333 _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR]))); 334 _FDT((fdt_property_cell(fdt, "d-cache-block-size", 335 env->dcache_line_size))); 336 _FDT((fdt_property_cell(fdt, "d-cache-line-size", 337 env->dcache_line_size))); 338 _FDT((fdt_property_cell(fdt, "i-cache-block-size", 339 env->icache_line_size))); 340 _FDT((fdt_property_cell(fdt, "i-cache-line-size", 341 env->icache_line_size))); 342 343 if (pcc->l1_dcache_size) { 344 _FDT((fdt_property_cell(fdt, "d-cache-size", pcc->l1_dcache_size))); 345 } else { 346 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); 347 } 348 if (pcc->l1_icache_size) { 349 _FDT((fdt_property_cell(fdt, "i-cache-size", pcc->l1_icache_size))); 350 } else { 351 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); 352 } 353 354 _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq))); 355 _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq))); 356 _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr))); 357 _FDT((fdt_property_string(fdt, "status", "okay"))); 358 _FDT((fdt_property(fdt, "64-bit", NULL, 0))); 359 360 /* Build interrupt servers and gservers properties */ 361 for (i = 0; i < smp_threads; i++) { 362 servers_prop[i] = cpu_to_be32(index + i); 363 /* Hack, direct the group queues back to cpu 0 */ 364 gservers_prop[i*2] = cpu_to_be32(index + i); 365 gservers_prop[i*2 + 1] = 0; 366 } 367 _FDT((fdt_property(fdt, "ibm,ppc-interrupt-server#s", 368 servers_prop, sizeof(servers_prop)))); 369 _FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s", 370 gservers_prop, sizeof(gservers_prop)))); 371 372 if (env->mmu_model & POWERPC_MMU_1TSEG) { 373 _FDT((fdt_property(fdt, "ibm,processor-segment-sizes", 374 segs, sizeof(segs)))); 375 } 376 377 /* Advertise VMX/VSX (vector extensions) if available 378 * 0 / no property == no vector extensions 379 * 1 == VMX / Altivec available 380 * 2 == VSX available */ 381 if (env->insns_flags & PPC_ALTIVEC) { 382 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 383 384 _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx))); 385 } 386 387 /* Advertise DFP (Decimal Floating Point) if available 388 * 0 / no property == no DFP 389 * 1 == DFP available */ 390 if (env->insns_flags2 & PPC2_DFP) { 391 _FDT((fdt_property_cell(fdt, "ibm,dfp", 1))); 392 } 393 394 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, 395 sizeof(page_sizes_prop)); 396 if (page_sizes_prop_size) { 397 _FDT((fdt_property(fdt, "ibm,segment-page-sizes", 398 page_sizes_prop, page_sizes_prop_size))); 399 } 400 401 _FDT((fdt_end_node(fdt))); 402 } 403 404 g_free(modelname); 405 406 _FDT((fdt_end_node(fdt))); 407 408 /* RTAS */ 409 _FDT((fdt_begin_node(fdt, "rtas"))); 410 411 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop, 412 sizeof(hypertas_prop)))); 413 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas_prop, 414 sizeof(qemu_hypertas_prop)))); 415 416 _FDT((fdt_property(fdt, "ibm,associativity-reference-points", 417 refpoints, sizeof(refpoints)))); 418 419 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); 420 421 _FDT((fdt_end_node(fdt))); 422 423 /* interrupt controller */ 424 _FDT((fdt_begin_node(fdt, "interrupt-controller"))); 425 426 _FDT((fdt_property_string(fdt, "device_type", 427 "PowerPC-External-Interrupt-Presentation"))); 428 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); 429 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 430 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", 431 interrupt_server_ranges_prop, 432 sizeof(interrupt_server_ranges_prop)))); 433 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); 434 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); 435 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); 436 437 _FDT((fdt_end_node(fdt))); 438 439 /* vdevice */ 440 _FDT((fdt_begin_node(fdt, "vdevice"))); 441 442 _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); 443 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); 444 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 445 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 446 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); 447 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 448 449 _FDT((fdt_end_node(fdt))); 450 451 /* event-sources */ 452 spapr_events_fdt_skel(fdt, epow_irq); 453 454 _FDT((fdt_end_node(fdt))); /* close root node */ 455 _FDT((fdt_finish(fdt))); 456 457 return fdt; 458 } 459 460 static int spapr_populate_memory(sPAPREnvironment *spapr, void *fdt) 461 { 462 uint32_t associativity[] = {cpu_to_be32(0x4), cpu_to_be32(0x0), 463 cpu_to_be32(0x0), cpu_to_be32(0x0), 464 cpu_to_be32(0x0)}; 465 char mem_name[32]; 466 hwaddr node0_size, mem_start; 467 uint64_t mem_reg_property[2]; 468 int i, off; 469 470 /* memory node(s) */ 471 node0_size = (nb_numa_nodes > 1) ? node_mem[0] : ram_size; 472 if (spapr->rma_size > node0_size) { 473 spapr->rma_size = node0_size; 474 } 475 476 /* RMA */ 477 mem_reg_property[0] = 0; 478 mem_reg_property[1] = cpu_to_be64(spapr->rma_size); 479 off = fdt_add_subnode(fdt, 0, "memory@0"); 480 _FDT(off); 481 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 482 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 483 sizeof(mem_reg_property)))); 484 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 485 sizeof(associativity)))); 486 487 /* RAM: Node 0 */ 488 if (node0_size > spapr->rma_size) { 489 mem_reg_property[0] = cpu_to_be64(spapr->rma_size); 490 mem_reg_property[1] = cpu_to_be64(node0_size - spapr->rma_size); 491 492 sprintf(mem_name, "memory@" TARGET_FMT_lx, spapr->rma_size); 493 off = fdt_add_subnode(fdt, 0, mem_name); 494 _FDT(off); 495 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 496 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 497 sizeof(mem_reg_property)))); 498 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 499 sizeof(associativity)))); 500 } 501 502 /* RAM: Node 1 and beyond */ 503 mem_start = node0_size; 504 for (i = 1; i < nb_numa_nodes; i++) { 505 mem_reg_property[0] = cpu_to_be64(mem_start); 506 mem_reg_property[1] = cpu_to_be64(node_mem[i]); 507 associativity[3] = associativity[4] = cpu_to_be32(i); 508 sprintf(mem_name, "memory@" TARGET_FMT_lx, mem_start); 509 off = fdt_add_subnode(fdt, 0, mem_name); 510 _FDT(off); 511 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 512 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 513 sizeof(mem_reg_property)))); 514 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 515 sizeof(associativity)))); 516 mem_start += node_mem[i]; 517 } 518 519 return 0; 520 } 521 522 static void spapr_finalize_fdt(sPAPREnvironment *spapr, 523 hwaddr fdt_addr, 524 hwaddr rtas_addr, 525 hwaddr rtas_size) 526 { 527 int ret; 528 void *fdt; 529 sPAPRPHBState *phb; 530 531 fdt = g_malloc(FDT_MAX_SIZE); 532 533 /* open out the base tree into a temp buffer for the final tweaks */ 534 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); 535 536 ret = spapr_populate_memory(spapr, fdt); 537 if (ret < 0) { 538 fprintf(stderr, "couldn't setup memory nodes in fdt\n"); 539 exit(1); 540 } 541 542 ret = spapr_populate_vdevice(spapr->vio_bus, fdt); 543 if (ret < 0) { 544 fprintf(stderr, "couldn't setup vio devices in fdt\n"); 545 exit(1); 546 } 547 548 QLIST_FOREACH(phb, &spapr->phbs, list) { 549 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 550 } 551 552 if (ret < 0) { 553 fprintf(stderr, "couldn't setup PCI devices in fdt\n"); 554 exit(1); 555 } 556 557 /* RTAS */ 558 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); 559 if (ret < 0) { 560 fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); 561 } 562 563 /* Advertise NUMA via ibm,associativity */ 564 ret = spapr_fixup_cpu_dt(fdt, spapr); 565 if (ret < 0) { 566 fprintf(stderr, "Couldn't finalize CPU device tree properties\n"); 567 } 568 569 if (!spapr->has_graphics) { 570 spapr_populate_chosen_stdout(fdt, spapr->vio_bus); 571 } 572 573 _FDT((fdt_pack(fdt))); 574 575 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 576 hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n", 577 fdt_totalsize(fdt), FDT_MAX_SIZE); 578 exit(1); 579 } 580 581 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 582 583 g_free(fdt); 584 } 585 586 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 587 { 588 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 589 } 590 591 static void emulate_spapr_hypercall(PowerPCCPU *cpu) 592 { 593 CPUPPCState *env = &cpu->env; 594 595 if (msr_pr) { 596 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 597 env->gpr[3] = H_PRIVILEGE; 598 } else { 599 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 600 } 601 } 602 603 static void spapr_reset_htab(sPAPREnvironment *spapr) 604 { 605 long shift; 606 607 /* allocate hash page table. For now we always make this 16mb, 608 * later we should probably make it scale to the size of guest 609 * RAM */ 610 611 shift = kvmppc_reset_htab(spapr->htab_shift); 612 613 if (shift > 0) { 614 /* Kernel handles htab, we don't need to allocate one */ 615 spapr->htab_shift = shift; 616 } else { 617 if (!spapr->htab) { 618 /* Allocate an htab if we don't yet have one */ 619 spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); 620 } 621 622 /* And clear it */ 623 memset(spapr->htab, 0, HTAB_SIZE(spapr)); 624 } 625 626 /* Update the RMA size if necessary */ 627 if (spapr->vrma_adjust) { 628 spapr->rma_size = kvmppc_rma_size(ram_size, spapr->htab_shift); 629 } 630 } 631 632 static void ppc_spapr_reset(void) 633 { 634 PowerPCCPU *first_ppc_cpu; 635 636 /* Reset the hash table & recalc the RMA */ 637 spapr_reset_htab(spapr); 638 639 qemu_devices_reset(); 640 641 /* Load the fdt */ 642 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, 643 spapr->rtas_size); 644 645 /* Set up the entry state */ 646 first_ppc_cpu = POWERPC_CPU(first_cpu); 647 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; 648 first_ppc_cpu->env.gpr[5] = 0; 649 first_cpu->halted = 0; 650 first_ppc_cpu->env.nip = spapr->entry_point; 651 652 } 653 654 static void spapr_cpu_reset(void *opaque) 655 { 656 PowerPCCPU *cpu = opaque; 657 CPUState *cs = CPU(cpu); 658 CPUPPCState *env = &cpu->env; 659 660 cpu_reset(cs); 661 662 /* All CPUs start halted. CPU0 is unhalted from the machine level 663 * reset code and the rest are explicitly started up by the guest 664 * using an RTAS call */ 665 cs->halted = 1; 666 667 env->spr[SPR_HIOR] = 0; 668 669 env->external_htab = spapr->htab; 670 env->htab_base = -1; 671 env->htab_mask = HTAB_SIZE(spapr) - 1; 672 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | 673 (spapr->htab_shift - 18); 674 } 675 676 static void spapr_create_nvram(sPAPREnvironment *spapr) 677 { 678 QemuOpts *machine_opts; 679 DeviceState *dev; 680 681 dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 682 683 machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0); 684 if (machine_opts) { 685 const char *drivename; 686 687 drivename = qemu_opt_get(machine_opts, "nvram"); 688 if (drivename) { 689 BlockDriverState *bs; 690 691 bs = bdrv_find(drivename); 692 if (!bs) { 693 fprintf(stderr, "No such block device \"%s\" for nvram\n", 694 drivename); 695 exit(1); 696 } 697 qdev_prop_set_drive_nofail(dev, "drive", bs); 698 } 699 } 700 701 qdev_init_nofail(dev); 702 703 spapr->nvram = (struct sPAPRNVRAM *)dev; 704 } 705 706 /* Returns whether we want to use VGA or not */ 707 static int spapr_vga_init(PCIBus *pci_bus) 708 { 709 switch (vga_interface_type) { 710 case VGA_NONE: 711 case VGA_STD: 712 return pci_vga_init(pci_bus) != NULL; 713 default: 714 fprintf(stderr, "This vga model is not supported," 715 "currently it only supports -vga std\n"); 716 exit(0); 717 break; 718 } 719 } 720 721 /* pSeries LPAR / sPAPR hardware init */ 722 static void ppc_spapr_init(QEMUMachineInitArgs *args) 723 { 724 ram_addr_t ram_size = args->ram_size; 725 const char *cpu_model = args->cpu_model; 726 const char *kernel_filename = args->kernel_filename; 727 const char *kernel_cmdline = args->kernel_cmdline; 728 const char *initrd_filename = args->initrd_filename; 729 const char *boot_device = args->boot_device; 730 PowerPCCPU *cpu; 731 CPUPPCState *env; 732 PCIHostState *phb; 733 int i; 734 MemoryRegion *sysmem = get_system_memory(); 735 MemoryRegion *ram = g_new(MemoryRegion, 1); 736 hwaddr rma_alloc_size; 737 uint32_t initrd_base = 0; 738 long kernel_size = 0, initrd_size = 0; 739 long load_limit, rtas_limit, fw_size; 740 char *filename; 741 742 msi_supported = true; 743 744 spapr = g_malloc0(sizeof(*spapr)); 745 QLIST_INIT(&spapr->phbs); 746 747 cpu_ppc_hypercall = emulate_spapr_hypercall; 748 749 /* Allocate RMA if necessary */ 750 rma_alloc_size = kvmppc_alloc_rma("ppc_spapr.rma", sysmem); 751 752 if (rma_alloc_size == -1) { 753 hw_error("qemu: Unable to create RMA\n"); 754 exit(1); 755 } 756 757 if (rma_alloc_size && (rma_alloc_size < ram_size)) { 758 spapr->rma_size = rma_alloc_size; 759 } else { 760 spapr->rma_size = ram_size; 761 762 /* With KVM, we don't actually know whether KVM supports an 763 * unbounded RMA (PR KVM) or is limited by the hash table size 764 * (HV KVM using VRMA), so we always assume the latter 765 * 766 * In that case, we also limit the initial allocations for RTAS 767 * etc... to 256M since we have no way to know what the VRMA size 768 * is going to be as it depends on the size of the hash table 769 * isn't determined yet. 770 */ 771 if (kvm_enabled()) { 772 spapr->vrma_adjust = 1; 773 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 774 } 775 } 776 777 /* We place the device tree and RTAS just below either the top of the RMA, 778 * or just below 2GB, whichever is lowere, so that it can be 779 * processed with 32-bit real mode code if necessary */ 780 rtas_limit = MIN(spapr->rma_size, 0x80000000); 781 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; 782 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; 783 load_limit = spapr->fdt_addr - FW_OVERHEAD; 784 785 /* We aim for a hash table of size 1/128 the size of RAM. The 786 * normal rule of thumb is 1/64 the size of RAM, but that's much 787 * more than needed for the Linux guests we support. */ 788 spapr->htab_shift = 18; /* Minimum architected size */ 789 while (spapr->htab_shift <= 46) { 790 if ((1ULL << (spapr->htab_shift + 7)) >= ram_size) { 791 break; 792 } 793 spapr->htab_shift++; 794 } 795 796 /* Set up Interrupt Controller before we create the VCPUs */ 797 spapr->icp = xics_system_init(smp_cpus * kvmppc_smt_threads() / smp_threads, 798 XICS_IRQS); 799 spapr->next_irq = XICS_IRQ_BASE; 800 801 /* init CPUs */ 802 if (cpu_model == NULL) { 803 cpu_model = kvm_enabled() ? "host" : "POWER7"; 804 } 805 for (i = 0; i < smp_cpus; i++) { 806 cpu = cpu_ppc_init(cpu_model); 807 if (cpu == NULL) { 808 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 809 exit(1); 810 } 811 env = &cpu->env; 812 813 xics_cpu_setup(spapr->icp, cpu); 814 815 /* Set time-base frequency to 512 MHz */ 816 cpu_ppc_tb_init(env, TIMEBASE_FREQ); 817 818 /* PAPR always has exception vectors in RAM not ROM. To ensure this, 819 * MSR[IP] should never be set. 820 */ 821 env->msr_mask &= ~(1 << 6); 822 823 /* Tell KVM that we're in PAPR mode */ 824 if (kvm_enabled()) { 825 kvmppc_set_papr(cpu); 826 } 827 828 qemu_register_reset(spapr_cpu_reset, cpu); 829 } 830 831 /* allocate RAM */ 832 spapr->ram_limit = ram_size; 833 if (spapr->ram_limit > rma_alloc_size) { 834 ram_addr_t nonrma_base = rma_alloc_size; 835 ram_addr_t nonrma_size = spapr->ram_limit - rma_alloc_size; 836 837 memory_region_init_ram(ram, NULL, "ppc_spapr.ram", nonrma_size); 838 vmstate_register_ram_global(ram); 839 memory_region_add_subregion(sysmem, nonrma_base, ram); 840 } 841 842 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 843 spapr->rtas_size = load_image_targphys(filename, spapr->rtas_addr, 844 rtas_limit - spapr->rtas_addr); 845 if (spapr->rtas_size < 0) { 846 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 847 exit(1); 848 } 849 if (spapr->rtas_size > RTAS_MAX_SIZE) { 850 hw_error("RTAS too big ! 0x%lx bytes (max is 0x%x)\n", 851 spapr->rtas_size, RTAS_MAX_SIZE); 852 exit(1); 853 } 854 g_free(filename); 855 856 /* Set up EPOW events infrastructure */ 857 spapr_events_init(spapr); 858 859 /* Set up IOMMU */ 860 spapr_iommu_init(); 861 862 /* Set up VIO bus */ 863 spapr->vio_bus = spapr_vio_bus_init(); 864 865 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 866 if (serial_hds[i]) { 867 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 868 } 869 } 870 871 /* We always have at least the nvram device on VIO */ 872 spapr_create_nvram(spapr); 873 874 /* Set up PCI */ 875 spapr_pci_rtas_init(); 876 877 phb = spapr_create_phb(spapr, 0); 878 879 for (i = 0; i < nb_nics; i++) { 880 NICInfo *nd = &nd_table[i]; 881 882 if (!nd->model) { 883 nd->model = g_strdup("ibmveth"); 884 } 885 886 if (strcmp(nd->model, "ibmveth") == 0) { 887 spapr_vlan_create(spapr->vio_bus, nd); 888 } else { 889 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 890 } 891 } 892 893 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 894 spapr_vscsi_create(spapr->vio_bus); 895 } 896 897 /* Graphics */ 898 if (spapr_vga_init(phb->bus)) { 899 spapr->has_graphics = true; 900 } 901 902 if (usb_enabled(spapr->has_graphics)) { 903 pci_create_simple(phb->bus, -1, "pci-ohci"); 904 if (spapr->has_graphics) { 905 usbdevice_create("keyboard"); 906 usbdevice_create("mouse"); 907 } 908 } 909 910 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 911 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= " 912 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF); 913 exit(1); 914 } 915 916 if (kernel_filename) { 917 uint64_t lowaddr = 0; 918 919 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 920 NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); 921 if (kernel_size < 0) { 922 kernel_size = load_image_targphys(kernel_filename, 923 KERNEL_LOAD_ADDR, 924 load_limit - KERNEL_LOAD_ADDR); 925 } 926 if (kernel_size < 0) { 927 fprintf(stderr, "qemu: could not load kernel '%s'\n", 928 kernel_filename); 929 exit(1); 930 } 931 932 /* load initrd */ 933 if (initrd_filename) { 934 /* Try to locate the initrd in the gap between the kernel 935 * and the firmware. Add a bit of space just in case 936 */ 937 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; 938 initrd_size = load_image_targphys(initrd_filename, initrd_base, 939 load_limit - initrd_base); 940 if (initrd_size < 0) { 941 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 942 initrd_filename); 943 exit(1); 944 } 945 } else { 946 initrd_base = 0; 947 initrd_size = 0; 948 } 949 } 950 951 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, FW_FILE_NAME); 952 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 953 if (fw_size < 0) { 954 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 955 exit(1); 956 } 957 g_free(filename); 958 959 spapr->entry_point = 0x100; 960 961 /* Prepare the device tree */ 962 spapr->fdt_skel = spapr_create_fdt_skel(cpu_model, 963 initrd_base, initrd_size, 964 kernel_size, 965 boot_device, kernel_cmdline, 966 spapr->epow_irq); 967 assert(spapr->fdt_skel != NULL); 968 } 969 970 static QEMUMachine spapr_machine = { 971 .name = "pseries", 972 .desc = "pSeries Logical Partition (PAPR compliant)", 973 .is_default = 1, 974 .init = ppc_spapr_init, 975 .reset = ppc_spapr_reset, 976 .block_default_type = IF_SCSI, 977 .max_cpus = MAX_CPUS, 978 .no_parallel = 1, 979 .boot_order = NULL, 980 }; 981 982 static void spapr_machine_init(void) 983 { 984 qemu_register_machine(&spapr_machine); 985 } 986 987 machine_init(spapr_machine_init); 988