1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/numa.h" 32 #include "hw/hw.h" 33 #include "qemu/log.h" 34 #include "hw/fw-path-provider.h" 35 #include "elf.h" 36 #include "net/net.h" 37 #include "sysemu/device_tree.h" 38 #include "sysemu/block-backend.h" 39 #include "sysemu/cpus.h" 40 #include "sysemu/hw_accel.h" 41 #include "kvm_ppc.h" 42 #include "migration/misc.h" 43 #include "migration/global_state.h" 44 #include "migration/register.h" 45 #include "mmu-hash64.h" 46 #include "mmu-book3s-v3.h" 47 #include "cpu-models.h" 48 #include "qom/cpu.h" 49 50 #include "hw/boards.h" 51 #include "hw/ppc/ppc.h" 52 #include "hw/loader.h" 53 54 #include "hw/ppc/fdt.h" 55 #include "hw/ppc/spapr.h" 56 #include "hw/ppc/spapr_vio.h" 57 #include "hw/pci-host/spapr.h" 58 #include "hw/ppc/xics.h" 59 #include "hw/pci/msi.h" 60 61 #include "hw/pci/pci.h" 62 #include "hw/scsi/scsi.h" 63 #include "hw/virtio/virtio-scsi.h" 64 #include "hw/virtio/vhost-scsi-common.h" 65 66 #include "exec/address-spaces.h" 67 #include "hw/usb.h" 68 #include "qemu/config-file.h" 69 #include "qemu/error-report.h" 70 #include "trace.h" 71 #include "hw/nmi.h" 72 #include "hw/intc/intc.h" 73 74 #include "hw/compat.h" 75 #include "qemu/cutils.h" 76 #include "hw/ppc/spapr_cpu_core.h" 77 78 #include <libfdt.h> 79 80 /* SLOF memory layout: 81 * 82 * SLOF raw image loaded at 0, copies its romfs right below the flat 83 * device-tree, then position SLOF itself 31M below that 84 * 85 * So we set FW_OVERHEAD to 40MB which should account for all of that 86 * and more 87 * 88 * We load our kernel at 4M, leaving space for SLOF initial image 89 */ 90 #define FDT_MAX_SIZE 0x100000 91 #define RTAS_MAX_SIZE 0x10000 92 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 93 #define FW_MAX_SIZE 0x400000 94 #define FW_FILE_NAME "slof.bin" 95 #define FW_OVERHEAD 0x2800000 96 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 97 98 #define MIN_RMA_SLOF 128UL 99 100 #define PHANDLE_XICP 0x00001111 101 102 /* These two functions implement the VCPU id numbering: one to compute them 103 * all and one to identify thread 0 of a VCORE. Any change to the first one 104 * is likely to have an impact on the second one, so let's keep them close. 105 */ 106 static int spapr_vcpu_id(sPAPRMachineState *spapr, int cpu_index) 107 { 108 assert(spapr->vsmt); 109 return 110 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 111 } 112 static bool spapr_is_thread0_in_vcore(sPAPRMachineState *spapr, 113 PowerPCCPU *cpu) 114 { 115 assert(spapr->vsmt); 116 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 117 } 118 119 static ICSState *spapr_ics_create(sPAPRMachineState *spapr, 120 const char *type_ics, 121 int nr_irqs, Error **errp) 122 { 123 Error *local_err = NULL; 124 Object *obj; 125 126 obj = object_new(type_ics); 127 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); 128 object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr), 129 &error_abort); 130 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err); 131 if (local_err) { 132 goto error; 133 } 134 object_property_set_bool(obj, true, "realized", &local_err); 135 if (local_err) { 136 goto error; 137 } 138 139 return ICS_SIMPLE(obj); 140 141 error: 142 error_propagate(errp, local_err); 143 return NULL; 144 } 145 146 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 147 { 148 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 149 * and newer QEMUs don't even have them. In both cases, we don't want 150 * to send anything on the wire. 151 */ 152 return false; 153 } 154 155 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 156 .name = "icp/server", 157 .version_id = 1, 158 .minimum_version_id = 1, 159 .needed = pre_2_10_vmstate_dummy_icp_needed, 160 .fields = (VMStateField[]) { 161 VMSTATE_UNUSED(4), /* uint32_t xirr */ 162 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 163 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 164 VMSTATE_END_OF_LIST() 165 }, 166 }; 167 168 static void pre_2_10_vmstate_register_dummy_icp(int i) 169 { 170 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 171 (void *)(uintptr_t) i); 172 } 173 174 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 175 { 176 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 177 (void *)(uintptr_t) i); 178 } 179 180 static int xics_max_server_number(sPAPRMachineState *spapr) 181 { 182 assert(spapr->vsmt); 183 return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads); 184 } 185 186 static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp) 187 { 188 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 189 190 if (kvm_enabled()) { 191 if (machine_kernel_irqchip_allowed(machine) && 192 !xics_kvm_init(spapr, errp)) { 193 spapr->icp_type = TYPE_KVM_ICP; 194 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp); 195 } 196 if (machine_kernel_irqchip_required(machine) && !spapr->ics) { 197 error_prepend(errp, "kernel_irqchip requested but unavailable: "); 198 return; 199 } 200 } 201 202 if (!spapr->ics) { 203 xics_spapr_init(spapr); 204 spapr->icp_type = TYPE_ICP; 205 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp); 206 if (!spapr->ics) { 207 return; 208 } 209 } 210 } 211 212 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 213 int smt_threads) 214 { 215 int i, ret = 0; 216 uint32_t servers_prop[smt_threads]; 217 uint32_t gservers_prop[smt_threads * 2]; 218 int index = spapr_get_vcpu_id(cpu); 219 220 if (cpu->compat_pvr) { 221 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 222 if (ret < 0) { 223 return ret; 224 } 225 } 226 227 /* Build interrupt servers and gservers properties */ 228 for (i = 0; i < smt_threads; i++) { 229 servers_prop[i] = cpu_to_be32(index + i); 230 /* Hack, direct the group queues back to cpu 0 */ 231 gservers_prop[i*2] = cpu_to_be32(index + i); 232 gservers_prop[i*2 + 1] = 0; 233 } 234 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 235 servers_prop, sizeof(servers_prop)); 236 if (ret < 0) { 237 return ret; 238 } 239 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 240 gservers_prop, sizeof(gservers_prop)); 241 242 return ret; 243 } 244 245 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 246 { 247 int index = spapr_get_vcpu_id(cpu); 248 uint32_t associativity[] = {cpu_to_be32(0x5), 249 cpu_to_be32(0x0), 250 cpu_to_be32(0x0), 251 cpu_to_be32(0x0), 252 cpu_to_be32(cpu->node_id), 253 cpu_to_be32(index)}; 254 255 /* Advertise NUMA via ibm,associativity */ 256 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 257 sizeof(associativity)); 258 } 259 260 /* Populate the "ibm,pa-features" property */ 261 static void spapr_populate_pa_features(sPAPRMachineState *spapr, 262 PowerPCCPU *cpu, 263 void *fdt, int offset, 264 bool legacy_guest) 265 { 266 CPUPPCState *env = &cpu->env; 267 uint8_t pa_features_206[] = { 6, 0, 268 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 269 uint8_t pa_features_207[] = { 24, 0, 270 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 271 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 272 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 273 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 274 uint8_t pa_features_300[] = { 66, 0, 275 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 276 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 277 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 278 /* 6: DS207 */ 279 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 280 /* 16: Vector */ 281 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 282 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 283 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 284 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 285 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 286 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 287 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 288 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 289 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 290 /* 42: PM, 44: PC RA, 46: SC vec'd */ 291 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 292 /* 48: SIMD, 50: QP BFP, 52: String */ 293 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 294 /* 54: DecFP, 56: DecI, 58: SHA */ 295 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 296 /* 60: NM atomic, 62: RNG */ 297 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 298 }; 299 uint8_t *pa_features = NULL; 300 size_t pa_size; 301 302 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 303 pa_features = pa_features_206; 304 pa_size = sizeof(pa_features_206); 305 } 306 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 307 pa_features = pa_features_207; 308 pa_size = sizeof(pa_features_207); 309 } 310 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 311 pa_features = pa_features_300; 312 pa_size = sizeof(pa_features_300); 313 } 314 if (!pa_features) { 315 return; 316 } 317 318 if (env->ci_large_pages) { 319 /* 320 * Note: we keep CI large pages off by default because a 64K capable 321 * guest provisioned with large pages might otherwise try to map a qemu 322 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 323 * even if that qemu runs on a 4k host. 324 * We dd this bit back here if we are confident this is not an issue 325 */ 326 pa_features[3] |= 0x20; 327 } 328 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 329 pa_features[24] |= 0x80; /* Transactional memory support */ 330 } 331 if (legacy_guest && pa_size > 40) { 332 /* Workaround for broken kernels that attempt (guest) radix 333 * mode when they can't handle it, if they see the radix bit set 334 * in pa-features. So hide it from them. */ 335 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 336 } 337 338 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 339 } 340 341 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 342 { 343 int ret = 0, offset, cpus_offset; 344 CPUState *cs; 345 char cpu_model[32]; 346 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 347 348 CPU_FOREACH(cs) { 349 PowerPCCPU *cpu = POWERPC_CPU(cs); 350 DeviceClass *dc = DEVICE_GET_CLASS(cs); 351 int index = spapr_get_vcpu_id(cpu); 352 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 353 354 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 355 continue; 356 } 357 358 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 359 360 cpus_offset = fdt_path_offset(fdt, "/cpus"); 361 if (cpus_offset < 0) { 362 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 363 if (cpus_offset < 0) { 364 return cpus_offset; 365 } 366 } 367 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 368 if (offset < 0) { 369 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 370 if (offset < 0) { 371 return offset; 372 } 373 } 374 375 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 376 pft_size_prop, sizeof(pft_size_prop)); 377 if (ret < 0) { 378 return ret; 379 } 380 381 if (nb_numa_nodes > 1) { 382 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); 383 if (ret < 0) { 384 return ret; 385 } 386 } 387 388 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 389 if (ret < 0) { 390 return ret; 391 } 392 393 spapr_populate_pa_features(spapr, cpu, fdt, offset, 394 spapr->cas_legacy_guest_workaround); 395 } 396 return ret; 397 } 398 399 static hwaddr spapr_node0_size(MachineState *machine) 400 { 401 if (nb_numa_nodes) { 402 int i; 403 for (i = 0; i < nb_numa_nodes; ++i) { 404 if (numa_info[i].node_mem) { 405 return MIN(pow2floor(numa_info[i].node_mem), 406 machine->ram_size); 407 } 408 } 409 } 410 return machine->ram_size; 411 } 412 413 static void add_str(GString *s, const gchar *s1) 414 { 415 g_string_append_len(s, s1, strlen(s1) + 1); 416 } 417 418 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 419 hwaddr size) 420 { 421 uint32_t associativity[] = { 422 cpu_to_be32(0x4), /* length */ 423 cpu_to_be32(0x0), cpu_to_be32(0x0), 424 cpu_to_be32(0x0), cpu_to_be32(nodeid) 425 }; 426 char mem_name[32]; 427 uint64_t mem_reg_property[2]; 428 int off; 429 430 mem_reg_property[0] = cpu_to_be64(start); 431 mem_reg_property[1] = cpu_to_be64(size); 432 433 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 434 off = fdt_add_subnode(fdt, 0, mem_name); 435 _FDT(off); 436 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 437 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 438 sizeof(mem_reg_property)))); 439 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 440 sizeof(associativity)))); 441 return off; 442 } 443 444 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 445 { 446 MachineState *machine = MACHINE(spapr); 447 hwaddr mem_start, node_size; 448 int i, nb_nodes = nb_numa_nodes; 449 NodeInfo *nodes = numa_info; 450 NodeInfo ramnode; 451 452 /* No NUMA nodes, assume there is just one node with whole RAM */ 453 if (!nb_numa_nodes) { 454 nb_nodes = 1; 455 ramnode.node_mem = machine->ram_size; 456 nodes = &ramnode; 457 } 458 459 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 460 if (!nodes[i].node_mem) { 461 continue; 462 } 463 if (mem_start >= machine->ram_size) { 464 node_size = 0; 465 } else { 466 node_size = nodes[i].node_mem; 467 if (node_size > machine->ram_size - mem_start) { 468 node_size = machine->ram_size - mem_start; 469 } 470 } 471 if (!mem_start) { 472 /* spapr_machine_init() checks for rma_size <= node0_size 473 * already */ 474 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 475 mem_start += spapr->rma_size; 476 node_size -= spapr->rma_size; 477 } 478 for ( ; node_size; ) { 479 hwaddr sizetmp = pow2floor(node_size); 480 481 /* mem_start != 0 here */ 482 if (ctzl(mem_start) < ctzl(sizetmp)) { 483 sizetmp = 1ULL << ctzl(mem_start); 484 } 485 486 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 487 node_size -= sizetmp; 488 mem_start += sizetmp; 489 } 490 } 491 492 return 0; 493 } 494 495 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 496 sPAPRMachineState *spapr) 497 { 498 PowerPCCPU *cpu = POWERPC_CPU(cs); 499 CPUPPCState *env = &cpu->env; 500 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 501 int index = spapr_get_vcpu_id(cpu); 502 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 503 0xffffffff, 0xffffffff}; 504 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 505 : SPAPR_TIMEBASE_FREQ; 506 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 507 uint32_t page_sizes_prop[64]; 508 size_t page_sizes_prop_size; 509 uint32_t vcpus_per_socket = smp_threads * smp_cores; 510 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 511 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 512 sPAPRDRConnector *drc; 513 int drc_index; 514 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 515 int i; 516 517 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 518 if (drc) { 519 drc_index = spapr_drc_index(drc); 520 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 521 } 522 523 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 524 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 525 526 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 527 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 528 env->dcache_line_size))); 529 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 530 env->dcache_line_size))); 531 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 532 env->icache_line_size))); 533 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 534 env->icache_line_size))); 535 536 if (pcc->l1_dcache_size) { 537 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 538 pcc->l1_dcache_size))); 539 } else { 540 warn_report("Unknown L1 dcache size for cpu"); 541 } 542 if (pcc->l1_icache_size) { 543 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 544 pcc->l1_icache_size))); 545 } else { 546 warn_report("Unknown L1 icache size for cpu"); 547 } 548 549 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 550 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 551 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 552 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 553 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 554 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 555 556 if (env->spr_cb[SPR_PURR].oea_read) { 557 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 558 } 559 560 if (env->mmu_model & POWERPC_MMU_1TSEG) { 561 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 562 segs, sizeof(segs)))); 563 } 564 565 /* Advertise VSX (vector extensions) if available 566 * 1 == VMX / Altivec available 567 * 2 == VSX available 568 * 569 * Only CPUs for which we create core types in spapr_cpu_core.c 570 * are possible, and all of those have VMX */ 571 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 572 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 573 } else { 574 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 575 } 576 577 /* Advertise DFP (Decimal Floating Point) if available 578 * 0 / no property == no DFP 579 * 1 == DFP available */ 580 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 581 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 582 } 583 584 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 585 sizeof(page_sizes_prop)); 586 if (page_sizes_prop_size) { 587 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 588 page_sizes_prop, page_sizes_prop_size))); 589 } 590 591 spapr_populate_pa_features(spapr, cpu, fdt, offset, false); 592 593 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 594 cs->cpu_index / vcpus_per_socket))); 595 596 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 597 pft_size_prop, sizeof(pft_size_prop)))); 598 599 if (nb_numa_nodes > 1) { 600 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 601 } 602 603 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 604 605 if (pcc->radix_page_info) { 606 for (i = 0; i < pcc->radix_page_info->count; i++) { 607 radix_AP_encodings[i] = 608 cpu_to_be32(pcc->radix_page_info->entries[i]); 609 } 610 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 611 radix_AP_encodings, 612 pcc->radix_page_info->count * 613 sizeof(radix_AP_encodings[0])))); 614 } 615 } 616 617 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 618 { 619 CPUState *cs; 620 int cpus_offset; 621 char *nodename; 622 623 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 624 _FDT(cpus_offset); 625 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 626 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 627 628 /* 629 * We walk the CPUs in reverse order to ensure that CPU DT nodes 630 * created by fdt_add_subnode() end up in the right order in FDT 631 * for the guest kernel the enumerate the CPUs correctly. 632 */ 633 CPU_FOREACH_REVERSE(cs) { 634 PowerPCCPU *cpu = POWERPC_CPU(cs); 635 int index = spapr_get_vcpu_id(cpu); 636 DeviceClass *dc = DEVICE_GET_CLASS(cs); 637 int offset; 638 639 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 640 continue; 641 } 642 643 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 644 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 645 g_free(nodename); 646 _FDT(offset); 647 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 648 } 649 650 } 651 652 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 653 { 654 MemoryDeviceInfoList *info; 655 656 for (info = list; info; info = info->next) { 657 MemoryDeviceInfo *value = info->value; 658 659 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 660 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 661 662 if (pcdimm_info->addr >= addr && 663 addr < (pcdimm_info->addr + pcdimm_info->size)) { 664 return pcdimm_info->node; 665 } 666 } 667 } 668 669 return -1; 670 } 671 672 /* 673 * Adds ibm,dynamic-reconfiguration-memory node. 674 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 675 * of this device tree node. 676 */ 677 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 678 { 679 MachineState *machine = MACHINE(spapr); 680 int ret, i, offset; 681 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 682 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 683 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 684 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 685 memory_region_size(&spapr->hotplug_memory.mr)) / 686 lmb_size; 687 uint32_t *int_buf, *cur_index, buf_len; 688 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 689 MemoryDeviceInfoList *dimms = NULL; 690 691 /* 692 * Don't create the node if there is no hotpluggable memory 693 */ 694 if (machine->ram_size == machine->maxram_size) { 695 return 0; 696 } 697 698 /* 699 * Allocate enough buffer size to fit in ibm,dynamic-memory 700 * or ibm,associativity-lookup-arrays 701 */ 702 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 703 * sizeof(uint32_t); 704 cur_index = int_buf = g_malloc0(buf_len); 705 706 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 707 708 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 709 sizeof(prop_lmb_size)); 710 if (ret < 0) { 711 goto out; 712 } 713 714 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 715 if (ret < 0) { 716 goto out; 717 } 718 719 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 720 if (ret < 0) { 721 goto out; 722 } 723 724 if (hotplug_lmb_start) { 725 dimms = qmp_pc_dimm_device_list(); 726 } 727 728 /* ibm,dynamic-memory */ 729 int_buf[0] = cpu_to_be32(nr_lmbs); 730 cur_index++; 731 for (i = 0; i < nr_lmbs; i++) { 732 uint64_t addr = i * lmb_size; 733 uint32_t *dynamic_memory = cur_index; 734 735 if (i >= hotplug_lmb_start) { 736 sPAPRDRConnector *drc; 737 738 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 739 g_assert(drc); 740 741 dynamic_memory[0] = cpu_to_be32(addr >> 32); 742 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 743 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 744 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 745 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 746 if (memory_region_present(get_system_memory(), addr)) { 747 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 748 } else { 749 dynamic_memory[5] = cpu_to_be32(0); 750 } 751 } else { 752 /* 753 * LMB information for RMA, boot time RAM and gap b/n RAM and 754 * hotplug memory region -- all these are marked as reserved 755 * and as having no valid DRC. 756 */ 757 dynamic_memory[0] = cpu_to_be32(addr >> 32); 758 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 759 dynamic_memory[2] = cpu_to_be32(0); 760 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 761 dynamic_memory[4] = cpu_to_be32(-1); 762 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 763 SPAPR_LMB_FLAGS_DRC_INVALID); 764 } 765 766 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 767 } 768 qapi_free_MemoryDeviceInfoList(dimms); 769 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 770 if (ret < 0) { 771 goto out; 772 } 773 774 /* ibm,associativity-lookup-arrays */ 775 cur_index = int_buf; 776 int_buf[0] = cpu_to_be32(nr_nodes); 777 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 778 cur_index += 2; 779 for (i = 0; i < nr_nodes; i++) { 780 uint32_t associativity[] = { 781 cpu_to_be32(0x0), 782 cpu_to_be32(0x0), 783 cpu_to_be32(0x0), 784 cpu_to_be32(i) 785 }; 786 memcpy(cur_index, associativity, sizeof(associativity)); 787 cur_index += 4; 788 } 789 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 790 (cur_index - int_buf) * sizeof(uint32_t)); 791 out: 792 g_free(int_buf); 793 return ret; 794 } 795 796 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 797 sPAPROptionVector *ov5_updates) 798 { 799 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 800 int ret = 0, offset; 801 802 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 803 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 804 g_assert(smc->dr_lmb_enabled); 805 ret = spapr_populate_drconf_memory(spapr, fdt); 806 if (ret) { 807 goto out; 808 } 809 } 810 811 offset = fdt_path_offset(fdt, "/chosen"); 812 if (offset < 0) { 813 offset = fdt_add_subnode(fdt, 0, "chosen"); 814 if (offset < 0) { 815 return offset; 816 } 817 } 818 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 819 "ibm,architecture-vec-5"); 820 821 out: 822 return ret; 823 } 824 825 static bool spapr_hotplugged_dev_before_cas(void) 826 { 827 Object *drc_container, *obj; 828 ObjectProperty *prop; 829 ObjectPropertyIterator iter; 830 831 drc_container = container_get(object_get_root(), "/dr-connector"); 832 object_property_iter_init(&iter, drc_container); 833 while ((prop = object_property_iter_next(&iter))) { 834 if (!strstart(prop->type, "link<", NULL)) { 835 continue; 836 } 837 obj = object_property_get_link(drc_container, prop->name, NULL); 838 if (spapr_drc_needed(obj)) { 839 return true; 840 } 841 } 842 return false; 843 } 844 845 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 846 target_ulong addr, target_ulong size, 847 sPAPROptionVector *ov5_updates) 848 { 849 void *fdt, *fdt_skel; 850 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 851 852 if (spapr_hotplugged_dev_before_cas()) { 853 return 1; 854 } 855 856 if (size < sizeof(hdr) || size > FW_MAX_SIZE) { 857 error_report("SLOF provided an unexpected CAS buffer size " 858 TARGET_FMT_lu " (min: %zu, max: %u)", 859 size, sizeof(hdr), FW_MAX_SIZE); 860 exit(EXIT_FAILURE); 861 } 862 863 size -= sizeof(hdr); 864 865 /* Create skeleton */ 866 fdt_skel = g_malloc0(size); 867 _FDT((fdt_create(fdt_skel, size))); 868 _FDT((fdt_begin_node(fdt_skel, ""))); 869 _FDT((fdt_end_node(fdt_skel))); 870 _FDT((fdt_finish(fdt_skel))); 871 fdt = g_malloc0(size); 872 _FDT((fdt_open_into(fdt_skel, fdt, size))); 873 g_free(fdt_skel); 874 875 /* Fixup cpu nodes */ 876 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 877 878 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 879 return -1; 880 } 881 882 /* Pack resulting tree */ 883 _FDT((fdt_pack(fdt))); 884 885 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 886 trace_spapr_cas_failed(size); 887 return -1; 888 } 889 890 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 891 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 892 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 893 g_free(fdt); 894 895 return 0; 896 } 897 898 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 899 { 900 int rtas; 901 GString *hypertas = g_string_sized_new(256); 902 GString *qemu_hypertas = g_string_sized_new(256); 903 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 904 uint64_t max_hotplug_addr = spapr->hotplug_memory.base + 905 memory_region_size(&spapr->hotplug_memory.mr); 906 uint32_t lrdr_capacity[] = { 907 cpu_to_be32(max_hotplug_addr >> 32), 908 cpu_to_be32(max_hotplug_addr & 0xffffffff), 909 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 910 cpu_to_be32(max_cpus / smp_threads), 911 }; 912 913 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 914 915 /* hypertas */ 916 add_str(hypertas, "hcall-pft"); 917 add_str(hypertas, "hcall-term"); 918 add_str(hypertas, "hcall-dabr"); 919 add_str(hypertas, "hcall-interrupt"); 920 add_str(hypertas, "hcall-tce"); 921 add_str(hypertas, "hcall-vio"); 922 add_str(hypertas, "hcall-splpar"); 923 add_str(hypertas, "hcall-bulk"); 924 add_str(hypertas, "hcall-set-mode"); 925 add_str(hypertas, "hcall-sprg0"); 926 add_str(hypertas, "hcall-copy"); 927 add_str(hypertas, "hcall-debug"); 928 add_str(qemu_hypertas, "hcall-memop1"); 929 930 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 931 add_str(hypertas, "hcall-multi-tce"); 932 } 933 934 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 935 add_str(hypertas, "hcall-hpt-resize"); 936 } 937 938 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 939 hypertas->str, hypertas->len)); 940 g_string_free(hypertas, TRUE); 941 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 942 qemu_hypertas->str, qemu_hypertas->len)); 943 g_string_free(qemu_hypertas, TRUE); 944 945 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 946 refpoints, sizeof(refpoints))); 947 948 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 949 RTAS_ERROR_LOG_MAX)); 950 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 951 RTAS_EVENT_SCAN_RATE)); 952 953 g_assert(msi_nonbroken); 954 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 955 956 /* 957 * According to PAPR, rtas ibm,os-term does not guarantee a return 958 * back to the guest cpu. 959 * 960 * While an additional ibm,extended-os-term property indicates 961 * that rtas call return will always occur. Set this property. 962 */ 963 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 964 965 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 966 lrdr_capacity, sizeof(lrdr_capacity))); 967 968 spapr_dt_rtas_tokens(fdt, rtas); 969 } 970 971 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features 972 * that the guest may request and thus the valid values for bytes 24..26 of 973 * option vector 5: */ 974 static void spapr_dt_ov5_platform_support(void *fdt, int chosen) 975 { 976 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 977 978 char val[2 * 4] = { 979 23, 0x00, /* Xive mode, filled in below. */ 980 24, 0x00, /* Hash/Radix, filled in below. */ 981 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 982 26, 0x40, /* Radix options: GTSE == yes. */ 983 }; 984 985 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 986 first_ppc_cpu->compat_pvr)) { 987 /* If we're in a pre POWER9 compat mode then the guest should do hash */ 988 val[3] = 0x00; /* Hash */ 989 } else if (kvm_enabled()) { 990 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 991 val[3] = 0x80; /* OV5_MMU_BOTH */ 992 } else if (kvmppc_has_cap_mmu_radix()) { 993 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 994 } else { 995 val[3] = 0x00; /* Hash */ 996 } 997 } else { 998 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 999 val[3] = 0xC0; 1000 } 1001 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1002 val, sizeof(val))); 1003 } 1004 1005 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 1006 { 1007 MachineState *machine = MACHINE(spapr); 1008 int chosen; 1009 const char *boot_device = machine->boot_order; 1010 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1011 size_t cb = 0; 1012 char *bootlist = get_boot_devices_list(&cb, true); 1013 1014 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1015 1016 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 1017 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1018 spapr->initrd_base)); 1019 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1020 spapr->initrd_base + spapr->initrd_size)); 1021 1022 if (spapr->kernel_size) { 1023 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 1024 cpu_to_be64(spapr->kernel_size) }; 1025 1026 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1027 &kprop, sizeof(kprop))); 1028 if (spapr->kernel_le) { 1029 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1030 } 1031 } 1032 if (boot_menu) { 1033 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1034 } 1035 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1036 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1037 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1038 1039 if (cb && bootlist) { 1040 int i; 1041 1042 for (i = 0; i < cb; i++) { 1043 if (bootlist[i] == '\n') { 1044 bootlist[i] = ' '; 1045 } 1046 } 1047 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1048 } 1049 1050 if (boot_device && strlen(boot_device)) { 1051 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1052 } 1053 1054 if (!spapr->has_graphics && stdout_path) { 1055 /* 1056 * "linux,stdout-path" and "stdout" properties are deprecated by linux 1057 * kernel. New platforms should only use the "stdout-path" property. Set 1058 * the new property and continue using older property to remain 1059 * compatible with the existing firmware. 1060 */ 1061 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1062 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1063 } 1064 1065 spapr_dt_ov5_platform_support(fdt, chosen); 1066 1067 g_free(stdout_path); 1068 g_free(bootlist); 1069 } 1070 1071 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 1072 { 1073 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1074 * KVM to work under pHyp with some guest co-operation */ 1075 int hypervisor; 1076 uint8_t hypercall[16]; 1077 1078 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1079 /* indicate KVM hypercall interface */ 1080 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1081 if (kvmppc_has_cap_fixup_hcalls()) { 1082 /* 1083 * Older KVM versions with older guest kernels were broken 1084 * with the magic page, don't allow the guest to map it. 1085 */ 1086 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1087 sizeof(hypercall))) { 1088 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1089 hypercall, sizeof(hypercall))); 1090 } 1091 } 1092 } 1093 1094 static void *spapr_build_fdt(sPAPRMachineState *spapr, 1095 hwaddr rtas_addr, 1096 hwaddr rtas_size) 1097 { 1098 MachineState *machine = MACHINE(spapr); 1099 MachineClass *mc = MACHINE_GET_CLASS(machine); 1100 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1101 int ret; 1102 void *fdt; 1103 sPAPRPHBState *phb; 1104 char *buf; 1105 1106 fdt = g_malloc0(FDT_MAX_SIZE); 1107 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 1108 1109 /* Root node */ 1110 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1111 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1112 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1113 1114 /* 1115 * Add info to guest to indentify which host is it being run on 1116 * and what is the uuid of the guest 1117 */ 1118 if (kvmppc_get_host_model(&buf)) { 1119 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1120 g_free(buf); 1121 } 1122 if (kvmppc_get_host_serial(&buf)) { 1123 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1124 g_free(buf); 1125 } 1126 1127 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1128 1129 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1130 if (qemu_uuid_set) { 1131 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1132 } 1133 g_free(buf); 1134 1135 if (qemu_get_vm_name()) { 1136 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1137 qemu_get_vm_name())); 1138 } 1139 1140 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1141 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1142 1143 /* /interrupt controller */ 1144 spapr_dt_xics(xics_max_server_number(spapr), fdt, PHANDLE_XICP); 1145 1146 ret = spapr_populate_memory(spapr, fdt); 1147 if (ret < 0) { 1148 error_report("couldn't setup memory nodes in fdt"); 1149 exit(1); 1150 } 1151 1152 /* /vdevice */ 1153 spapr_dt_vdevice(spapr->vio_bus, fdt); 1154 1155 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1156 ret = spapr_rng_populate_dt(fdt); 1157 if (ret < 0) { 1158 error_report("could not set up rng device in the fdt"); 1159 exit(1); 1160 } 1161 } 1162 1163 QLIST_FOREACH(phb, &spapr->phbs, list) { 1164 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 1165 if (ret < 0) { 1166 error_report("couldn't setup PCI devices in fdt"); 1167 exit(1); 1168 } 1169 } 1170 1171 /* cpus */ 1172 spapr_populate_cpus_dt_node(fdt, spapr); 1173 1174 if (smc->dr_lmb_enabled) { 1175 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1176 } 1177 1178 if (mc->has_hotpluggable_cpus) { 1179 int offset = fdt_path_offset(fdt, "/cpus"); 1180 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1181 SPAPR_DR_CONNECTOR_TYPE_CPU); 1182 if (ret < 0) { 1183 error_report("Couldn't set up CPU DR device tree properties"); 1184 exit(1); 1185 } 1186 } 1187 1188 /* /event-sources */ 1189 spapr_dt_events(spapr, fdt); 1190 1191 /* /rtas */ 1192 spapr_dt_rtas(spapr, fdt); 1193 1194 /* /chosen */ 1195 spapr_dt_chosen(spapr, fdt); 1196 1197 /* /hypervisor */ 1198 if (kvm_enabled()) { 1199 spapr_dt_hypervisor(spapr, fdt); 1200 } 1201 1202 /* Build memory reserve map */ 1203 if (spapr->kernel_size) { 1204 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1205 } 1206 if (spapr->initrd_size) { 1207 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1208 } 1209 1210 /* ibm,client-architecture-support updates */ 1211 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1212 if (ret < 0) { 1213 error_report("couldn't setup CAS properties fdt"); 1214 exit(1); 1215 } 1216 1217 return fdt; 1218 } 1219 1220 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1221 { 1222 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1223 } 1224 1225 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1226 PowerPCCPU *cpu) 1227 { 1228 CPUPPCState *env = &cpu->env; 1229 1230 /* The TCG path should also be holding the BQL at this point */ 1231 g_assert(qemu_mutex_iothread_locked()); 1232 1233 if (msr_pr) { 1234 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1235 env->gpr[3] = H_PRIVILEGE; 1236 } else { 1237 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1238 } 1239 } 1240 1241 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) 1242 { 1243 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1244 1245 return spapr->patb_entry; 1246 } 1247 1248 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1249 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1250 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1251 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1252 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1253 1254 /* 1255 * Get the fd to access the kernel htab, re-opening it if necessary 1256 */ 1257 static int get_htab_fd(sPAPRMachineState *spapr) 1258 { 1259 Error *local_err = NULL; 1260 1261 if (spapr->htab_fd >= 0) { 1262 return spapr->htab_fd; 1263 } 1264 1265 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1266 if (spapr->htab_fd < 0) { 1267 error_report_err(local_err); 1268 } 1269 1270 return spapr->htab_fd; 1271 } 1272 1273 void close_htab_fd(sPAPRMachineState *spapr) 1274 { 1275 if (spapr->htab_fd >= 0) { 1276 close(spapr->htab_fd); 1277 } 1278 spapr->htab_fd = -1; 1279 } 1280 1281 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1282 { 1283 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1284 1285 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1286 } 1287 1288 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1289 { 1290 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1291 1292 assert(kvm_enabled()); 1293 1294 if (!spapr->htab) { 1295 return 0; 1296 } 1297 1298 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1299 } 1300 1301 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1302 hwaddr ptex, int n) 1303 { 1304 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1305 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1306 1307 if (!spapr->htab) { 1308 /* 1309 * HTAB is controlled by KVM. Fetch into temporary buffer 1310 */ 1311 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1312 kvmppc_read_hptes(hptes, ptex, n); 1313 return hptes; 1314 } 1315 1316 /* 1317 * HTAB is controlled by QEMU. Just point to the internally 1318 * accessible PTEG. 1319 */ 1320 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1321 } 1322 1323 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1324 const ppc_hash_pte64_t *hptes, 1325 hwaddr ptex, int n) 1326 { 1327 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1328 1329 if (!spapr->htab) { 1330 g_free((void *)hptes); 1331 } 1332 1333 /* Nothing to do for qemu managed HPT */ 1334 } 1335 1336 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1337 uint64_t pte0, uint64_t pte1) 1338 { 1339 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1340 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1341 1342 if (!spapr->htab) { 1343 kvmppc_write_hpte(ptex, pte0, pte1); 1344 } else { 1345 stq_p(spapr->htab + offset, pte0); 1346 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1347 } 1348 } 1349 1350 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1351 { 1352 int shift; 1353 1354 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1355 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1356 * that's much more than is needed for Linux guests */ 1357 shift = ctz64(pow2ceil(ramsize)) - 7; 1358 shift = MAX(shift, 18); /* Minimum architected size */ 1359 shift = MIN(shift, 46); /* Maximum architected size */ 1360 return shift; 1361 } 1362 1363 void spapr_free_hpt(sPAPRMachineState *spapr) 1364 { 1365 g_free(spapr->htab); 1366 spapr->htab = NULL; 1367 spapr->htab_shift = 0; 1368 close_htab_fd(spapr); 1369 } 1370 1371 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1372 Error **errp) 1373 { 1374 long rc; 1375 1376 /* Clean up any HPT info from a previous boot */ 1377 spapr_free_hpt(spapr); 1378 1379 rc = kvmppc_reset_htab(shift); 1380 if (rc < 0) { 1381 /* kernel-side HPT needed, but couldn't allocate one */ 1382 error_setg_errno(errp, errno, 1383 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1384 shift); 1385 /* This is almost certainly fatal, but if the caller really 1386 * wants to carry on with shift == 0, it's welcome to try */ 1387 } else if (rc > 0) { 1388 /* kernel-side HPT allocated */ 1389 if (rc != shift) { 1390 error_setg(errp, 1391 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1392 shift, rc); 1393 } 1394 1395 spapr->htab_shift = shift; 1396 spapr->htab = NULL; 1397 } else { 1398 /* kernel-side HPT not needed, allocate in userspace instead */ 1399 size_t size = 1ULL << shift; 1400 int i; 1401 1402 spapr->htab = qemu_memalign(size, size); 1403 if (!spapr->htab) { 1404 error_setg_errno(errp, errno, 1405 "Could not allocate HPT of order %d", shift); 1406 return; 1407 } 1408 1409 memset(spapr->htab, 0, size); 1410 spapr->htab_shift = shift; 1411 1412 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1413 DIRTY_HPTE(HPTE(spapr->htab, i)); 1414 } 1415 } 1416 /* We're setting up a hash table, so that means we're not radix */ 1417 spapr->patb_entry = 0; 1418 } 1419 1420 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) 1421 { 1422 int hpt_shift; 1423 1424 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1425 || (spapr->cas_reboot 1426 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1427 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1428 } else { 1429 uint64_t current_ram_size; 1430 1431 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1432 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1433 } 1434 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1435 1436 if (spapr->vrma_adjust) { 1437 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), 1438 spapr->htab_shift); 1439 } 1440 } 1441 1442 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1443 { 1444 bool matched = false; 1445 1446 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1447 matched = true; 1448 } 1449 1450 if (!matched) { 1451 error_report("Device %s is not supported by this machine yet.", 1452 qdev_fw_name(DEVICE(sbdev))); 1453 exit(1); 1454 } 1455 } 1456 1457 static int spapr_reset_drcs(Object *child, void *opaque) 1458 { 1459 sPAPRDRConnector *drc = 1460 (sPAPRDRConnector *) object_dynamic_cast(child, 1461 TYPE_SPAPR_DR_CONNECTOR); 1462 1463 if (drc) { 1464 spapr_drc_reset(drc); 1465 } 1466 1467 return 0; 1468 } 1469 1470 static void spapr_machine_reset(void) 1471 { 1472 MachineState *machine = MACHINE(qdev_get_machine()); 1473 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1474 PowerPCCPU *first_ppc_cpu; 1475 uint32_t rtas_limit; 1476 hwaddr rtas_addr, fdt_addr; 1477 void *fdt; 1478 int rc; 1479 1480 /* Check for unknown sysbus devices */ 1481 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1482 1483 spapr_caps_reset(spapr); 1484 1485 first_ppc_cpu = POWERPC_CPU(first_cpu); 1486 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1487 ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1488 spapr->max_compat_pvr)) { 1489 /* If using KVM with radix mode available, VCPUs can be started 1490 * without a HPT because KVM will start them in radix mode. 1491 * Set the GR bit in PATB so that we know there is no HPT. */ 1492 spapr->patb_entry = PATBE1_GR; 1493 } else { 1494 spapr_setup_hpt_and_vrma(spapr); 1495 } 1496 1497 /* if this reset wasn't generated by CAS, we should reset our 1498 * negotiated options and start from scratch */ 1499 if (!spapr->cas_reboot) { 1500 spapr_ovec_cleanup(spapr->ov5_cas); 1501 spapr->ov5_cas = spapr_ovec_new(); 1502 1503 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal); 1504 } 1505 1506 qemu_devices_reset(); 1507 1508 /* DRC reset may cause a device to be unplugged. This will cause troubles 1509 * if this device is used by another device (eg, a running vhost backend 1510 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1511 * situations, we reset DRCs after all devices have been reset. 1512 */ 1513 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1514 1515 spapr_clear_pending_events(spapr); 1516 1517 /* 1518 * We place the device tree and RTAS just below either the top of the RMA, 1519 * or just below 2GB, whichever is lowere, so that it can be 1520 * processed with 32-bit real mode code if necessary 1521 */ 1522 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1523 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1524 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1525 1526 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1527 1528 spapr_load_rtas(spapr, fdt, rtas_addr); 1529 1530 rc = fdt_pack(fdt); 1531 1532 /* Should only fail if we've built a corrupted tree */ 1533 assert(rc == 0); 1534 1535 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1536 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1537 fdt_totalsize(fdt), FDT_MAX_SIZE); 1538 exit(1); 1539 } 1540 1541 /* Load the fdt */ 1542 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1543 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1544 g_free(fdt); 1545 1546 /* Set up the entry state */ 1547 first_ppc_cpu->env.gpr[3] = fdt_addr; 1548 first_ppc_cpu->env.gpr[5] = 0; 1549 first_cpu->halted = 0; 1550 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1551 1552 spapr->cas_reboot = false; 1553 } 1554 1555 static void spapr_create_nvram(sPAPRMachineState *spapr) 1556 { 1557 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1558 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1559 1560 if (dinfo) { 1561 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1562 &error_fatal); 1563 } 1564 1565 qdev_init_nofail(dev); 1566 1567 spapr->nvram = (struct sPAPRNVRAM *)dev; 1568 } 1569 1570 static void spapr_rtc_create(sPAPRMachineState *spapr) 1571 { 1572 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); 1573 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), 1574 &error_fatal); 1575 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1576 &error_fatal); 1577 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1578 "date", &error_fatal); 1579 } 1580 1581 /* Returns whether we want to use VGA or not */ 1582 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1583 { 1584 switch (vga_interface_type) { 1585 case VGA_NONE: 1586 return false; 1587 case VGA_DEVICE: 1588 return true; 1589 case VGA_STD: 1590 case VGA_VIRTIO: 1591 return pci_vga_init(pci_bus) != NULL; 1592 default: 1593 error_setg(errp, 1594 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1595 return false; 1596 } 1597 } 1598 1599 static int spapr_pre_load(void *opaque) 1600 { 1601 int rc; 1602 1603 rc = spapr_caps_pre_load(opaque); 1604 if (rc) { 1605 return rc; 1606 } 1607 1608 return 0; 1609 } 1610 1611 static int spapr_post_load(void *opaque, int version_id) 1612 { 1613 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1614 int err = 0; 1615 1616 err = spapr_caps_post_migration(spapr); 1617 if (err) { 1618 return err; 1619 } 1620 1621 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { 1622 CPUState *cs; 1623 CPU_FOREACH(cs) { 1624 PowerPCCPU *cpu = POWERPC_CPU(cs); 1625 icp_resend(ICP(cpu->intc)); 1626 } 1627 } 1628 1629 /* In earlier versions, there was no separate qdev for the PAPR 1630 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1631 * So when migrating from those versions, poke the incoming offset 1632 * value into the RTC device */ 1633 if (version_id < 3) { 1634 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1635 } 1636 1637 if (kvm_enabled() && spapr->patb_entry) { 1638 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1639 bool radix = !!(spapr->patb_entry & PATBE1_GR); 1640 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1641 1642 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1643 if (err) { 1644 error_report("Process table config unsupported by the host"); 1645 return -EINVAL; 1646 } 1647 } 1648 1649 return err; 1650 } 1651 1652 static int spapr_pre_save(void *opaque) 1653 { 1654 int rc; 1655 1656 rc = spapr_caps_pre_save(opaque); 1657 if (rc) { 1658 return rc; 1659 } 1660 1661 return 0; 1662 } 1663 1664 static bool version_before_3(void *opaque, int version_id) 1665 { 1666 return version_id < 3; 1667 } 1668 1669 static bool spapr_pending_events_needed(void *opaque) 1670 { 1671 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1672 return !QTAILQ_EMPTY(&spapr->pending_events); 1673 } 1674 1675 static const VMStateDescription vmstate_spapr_event_entry = { 1676 .name = "spapr_event_log_entry", 1677 .version_id = 1, 1678 .minimum_version_id = 1, 1679 .fields = (VMStateField[]) { 1680 VMSTATE_UINT32(summary, sPAPREventLogEntry), 1681 VMSTATE_UINT32(extended_length, sPAPREventLogEntry), 1682 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0, 1683 NULL, extended_length), 1684 VMSTATE_END_OF_LIST() 1685 }, 1686 }; 1687 1688 static const VMStateDescription vmstate_spapr_pending_events = { 1689 .name = "spapr_pending_events", 1690 .version_id = 1, 1691 .minimum_version_id = 1, 1692 .needed = spapr_pending_events_needed, 1693 .fields = (VMStateField[]) { 1694 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1, 1695 vmstate_spapr_event_entry, sPAPREventLogEntry, next), 1696 VMSTATE_END_OF_LIST() 1697 }, 1698 }; 1699 1700 static bool spapr_ov5_cas_needed(void *opaque) 1701 { 1702 sPAPRMachineState *spapr = opaque; 1703 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1704 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1705 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1706 bool cas_needed; 1707 1708 /* Prior to the introduction of sPAPROptionVector, we had two option 1709 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1710 * Both of these options encode machine topology into the device-tree 1711 * in such a way that the now-booted OS should still be able to interact 1712 * appropriately with QEMU regardless of what options were actually 1713 * negotiatied on the source side. 1714 * 1715 * As such, we can avoid migrating the CAS-negotiated options if these 1716 * are the only options available on the current machine/platform. 1717 * Since these are the only options available for pseries-2.7 and 1718 * earlier, this allows us to maintain old->new/new->old migration 1719 * compatibility. 1720 * 1721 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1722 * via default pseries-2.8 machines and explicit command-line parameters. 1723 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1724 * of the actual CAS-negotiated values to continue working properly. For 1725 * example, availability of memory unplug depends on knowing whether 1726 * OV5_HP_EVT was negotiated via CAS. 1727 * 1728 * Thus, for any cases where the set of available CAS-negotiatable 1729 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1730 * include the CAS-negotiated options in the migration stream. 1731 */ 1732 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1733 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1734 1735 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1736 * the mask itself since in the future it's possible "legacy" bits may be 1737 * removed via machine options, which could generate a false positive 1738 * that breaks migration. 1739 */ 1740 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1741 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1742 1743 spapr_ovec_cleanup(ov5_mask); 1744 spapr_ovec_cleanup(ov5_legacy); 1745 spapr_ovec_cleanup(ov5_removed); 1746 1747 return cas_needed; 1748 } 1749 1750 static const VMStateDescription vmstate_spapr_ov5_cas = { 1751 .name = "spapr_option_vector_ov5_cas", 1752 .version_id = 1, 1753 .minimum_version_id = 1, 1754 .needed = spapr_ov5_cas_needed, 1755 .fields = (VMStateField[]) { 1756 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1757 vmstate_spapr_ovec, sPAPROptionVector), 1758 VMSTATE_END_OF_LIST() 1759 }, 1760 }; 1761 1762 static bool spapr_patb_entry_needed(void *opaque) 1763 { 1764 sPAPRMachineState *spapr = opaque; 1765 1766 return !!spapr->patb_entry; 1767 } 1768 1769 static const VMStateDescription vmstate_spapr_patb_entry = { 1770 .name = "spapr_patb_entry", 1771 .version_id = 1, 1772 .minimum_version_id = 1, 1773 .needed = spapr_patb_entry_needed, 1774 .fields = (VMStateField[]) { 1775 VMSTATE_UINT64(patb_entry, sPAPRMachineState), 1776 VMSTATE_END_OF_LIST() 1777 }, 1778 }; 1779 1780 static const VMStateDescription vmstate_spapr = { 1781 .name = "spapr", 1782 .version_id = 3, 1783 .minimum_version_id = 1, 1784 .pre_load = spapr_pre_load, 1785 .post_load = spapr_post_load, 1786 .pre_save = spapr_pre_save, 1787 .fields = (VMStateField[]) { 1788 /* used to be @next_irq */ 1789 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1790 1791 /* RTC offset */ 1792 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1793 1794 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1795 VMSTATE_END_OF_LIST() 1796 }, 1797 .subsections = (const VMStateDescription*[]) { 1798 &vmstate_spapr_ov5_cas, 1799 &vmstate_spapr_patb_entry, 1800 &vmstate_spapr_pending_events, 1801 &vmstate_spapr_cap_htm, 1802 &vmstate_spapr_cap_vsx, 1803 &vmstate_spapr_cap_dfp, 1804 &vmstate_spapr_cap_cfpc, 1805 &vmstate_spapr_cap_sbbc, 1806 &vmstate_spapr_cap_ibs, 1807 NULL 1808 } 1809 }; 1810 1811 static int htab_save_setup(QEMUFile *f, void *opaque) 1812 { 1813 sPAPRMachineState *spapr = opaque; 1814 1815 /* "Iteration" header */ 1816 if (!spapr->htab_shift) { 1817 qemu_put_be32(f, -1); 1818 } else { 1819 qemu_put_be32(f, spapr->htab_shift); 1820 } 1821 1822 if (spapr->htab) { 1823 spapr->htab_save_index = 0; 1824 spapr->htab_first_pass = true; 1825 } else { 1826 if (spapr->htab_shift) { 1827 assert(kvm_enabled()); 1828 } 1829 } 1830 1831 1832 return 0; 1833 } 1834 1835 static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr, 1836 int chunkstart, int n_valid, int n_invalid) 1837 { 1838 qemu_put_be32(f, chunkstart); 1839 qemu_put_be16(f, n_valid); 1840 qemu_put_be16(f, n_invalid); 1841 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1842 HASH_PTE_SIZE_64 * n_valid); 1843 } 1844 1845 static void htab_save_end_marker(QEMUFile *f) 1846 { 1847 qemu_put_be32(f, 0); 1848 qemu_put_be16(f, 0); 1849 qemu_put_be16(f, 0); 1850 } 1851 1852 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1853 int64_t max_ns) 1854 { 1855 bool has_timeout = max_ns != -1; 1856 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1857 int index = spapr->htab_save_index; 1858 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1859 1860 assert(spapr->htab_first_pass); 1861 1862 do { 1863 int chunkstart; 1864 1865 /* Consume invalid HPTEs */ 1866 while ((index < htabslots) 1867 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1868 CLEAN_HPTE(HPTE(spapr->htab, index)); 1869 index++; 1870 } 1871 1872 /* Consume valid HPTEs */ 1873 chunkstart = index; 1874 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1875 && HPTE_VALID(HPTE(spapr->htab, index))) { 1876 CLEAN_HPTE(HPTE(spapr->htab, index)); 1877 index++; 1878 } 1879 1880 if (index > chunkstart) { 1881 int n_valid = index - chunkstart; 1882 1883 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 1884 1885 if (has_timeout && 1886 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1887 break; 1888 } 1889 } 1890 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1891 1892 if (index >= htabslots) { 1893 assert(index == htabslots); 1894 index = 0; 1895 spapr->htab_first_pass = false; 1896 } 1897 spapr->htab_save_index = index; 1898 } 1899 1900 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1901 int64_t max_ns) 1902 { 1903 bool final = max_ns < 0; 1904 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1905 int examined = 0, sent = 0; 1906 int index = spapr->htab_save_index; 1907 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1908 1909 assert(!spapr->htab_first_pass); 1910 1911 do { 1912 int chunkstart, invalidstart; 1913 1914 /* Consume non-dirty HPTEs */ 1915 while ((index < htabslots) 1916 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1917 index++; 1918 examined++; 1919 } 1920 1921 chunkstart = index; 1922 /* Consume valid dirty HPTEs */ 1923 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1924 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1925 && HPTE_VALID(HPTE(spapr->htab, index))) { 1926 CLEAN_HPTE(HPTE(spapr->htab, index)); 1927 index++; 1928 examined++; 1929 } 1930 1931 invalidstart = index; 1932 /* Consume invalid dirty HPTEs */ 1933 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1934 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1935 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1936 CLEAN_HPTE(HPTE(spapr->htab, index)); 1937 index++; 1938 examined++; 1939 } 1940 1941 if (index > chunkstart) { 1942 int n_valid = invalidstart - chunkstart; 1943 int n_invalid = index - invalidstart; 1944 1945 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 1946 sent += index - chunkstart; 1947 1948 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1949 break; 1950 } 1951 } 1952 1953 if (examined >= htabslots) { 1954 break; 1955 } 1956 1957 if (index >= htabslots) { 1958 assert(index == htabslots); 1959 index = 0; 1960 } 1961 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1962 1963 if (index >= htabslots) { 1964 assert(index == htabslots); 1965 index = 0; 1966 } 1967 1968 spapr->htab_save_index = index; 1969 1970 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1971 } 1972 1973 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1974 #define MAX_KVM_BUF_SIZE 2048 1975 1976 static int htab_save_iterate(QEMUFile *f, void *opaque) 1977 { 1978 sPAPRMachineState *spapr = opaque; 1979 int fd; 1980 int rc = 0; 1981 1982 /* Iteration header */ 1983 if (!spapr->htab_shift) { 1984 qemu_put_be32(f, -1); 1985 return 1; 1986 } else { 1987 qemu_put_be32(f, 0); 1988 } 1989 1990 if (!spapr->htab) { 1991 assert(kvm_enabled()); 1992 1993 fd = get_htab_fd(spapr); 1994 if (fd < 0) { 1995 return fd; 1996 } 1997 1998 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1999 if (rc < 0) { 2000 return rc; 2001 } 2002 } else if (spapr->htab_first_pass) { 2003 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2004 } else { 2005 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2006 } 2007 2008 htab_save_end_marker(f); 2009 2010 return rc; 2011 } 2012 2013 static int htab_save_complete(QEMUFile *f, void *opaque) 2014 { 2015 sPAPRMachineState *spapr = opaque; 2016 int fd; 2017 2018 /* Iteration header */ 2019 if (!spapr->htab_shift) { 2020 qemu_put_be32(f, -1); 2021 return 0; 2022 } else { 2023 qemu_put_be32(f, 0); 2024 } 2025 2026 if (!spapr->htab) { 2027 int rc; 2028 2029 assert(kvm_enabled()); 2030 2031 fd = get_htab_fd(spapr); 2032 if (fd < 0) { 2033 return fd; 2034 } 2035 2036 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2037 if (rc < 0) { 2038 return rc; 2039 } 2040 } else { 2041 if (spapr->htab_first_pass) { 2042 htab_save_first_pass(f, spapr, -1); 2043 } 2044 htab_save_later_pass(f, spapr, -1); 2045 } 2046 2047 /* End marker */ 2048 htab_save_end_marker(f); 2049 2050 return 0; 2051 } 2052 2053 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2054 { 2055 sPAPRMachineState *spapr = opaque; 2056 uint32_t section_hdr; 2057 int fd = -1; 2058 Error *local_err = NULL; 2059 2060 if (version_id < 1 || version_id > 1) { 2061 error_report("htab_load() bad version"); 2062 return -EINVAL; 2063 } 2064 2065 section_hdr = qemu_get_be32(f); 2066 2067 if (section_hdr == -1) { 2068 spapr_free_hpt(spapr); 2069 return 0; 2070 } 2071 2072 if (section_hdr) { 2073 /* First section gives the htab size */ 2074 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2075 if (local_err) { 2076 error_report_err(local_err); 2077 return -EINVAL; 2078 } 2079 return 0; 2080 } 2081 2082 if (!spapr->htab) { 2083 assert(kvm_enabled()); 2084 2085 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2086 if (fd < 0) { 2087 error_report_err(local_err); 2088 return fd; 2089 } 2090 } 2091 2092 while (true) { 2093 uint32_t index; 2094 uint16_t n_valid, n_invalid; 2095 2096 index = qemu_get_be32(f); 2097 n_valid = qemu_get_be16(f); 2098 n_invalid = qemu_get_be16(f); 2099 2100 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2101 /* End of Stream */ 2102 break; 2103 } 2104 2105 if ((index + n_valid + n_invalid) > 2106 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2107 /* Bad index in stream */ 2108 error_report( 2109 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2110 index, n_valid, n_invalid, spapr->htab_shift); 2111 return -EINVAL; 2112 } 2113 2114 if (spapr->htab) { 2115 if (n_valid) { 2116 qemu_get_buffer(f, HPTE(spapr->htab, index), 2117 HASH_PTE_SIZE_64 * n_valid); 2118 } 2119 if (n_invalid) { 2120 memset(HPTE(spapr->htab, index + n_valid), 0, 2121 HASH_PTE_SIZE_64 * n_invalid); 2122 } 2123 } else { 2124 int rc; 2125 2126 assert(fd >= 0); 2127 2128 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2129 if (rc < 0) { 2130 return rc; 2131 } 2132 } 2133 } 2134 2135 if (!spapr->htab) { 2136 assert(fd >= 0); 2137 close(fd); 2138 } 2139 2140 return 0; 2141 } 2142 2143 static void htab_save_cleanup(void *opaque) 2144 { 2145 sPAPRMachineState *spapr = opaque; 2146 2147 close_htab_fd(spapr); 2148 } 2149 2150 static SaveVMHandlers savevm_htab_handlers = { 2151 .save_setup = htab_save_setup, 2152 .save_live_iterate = htab_save_iterate, 2153 .save_live_complete_precopy = htab_save_complete, 2154 .save_cleanup = htab_save_cleanup, 2155 .load_state = htab_load, 2156 }; 2157 2158 static void spapr_boot_set(void *opaque, const char *boot_device, 2159 Error **errp) 2160 { 2161 MachineState *machine = MACHINE(opaque); 2162 machine->boot_order = g_strdup(boot_device); 2163 } 2164 2165 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 2166 { 2167 MachineState *machine = MACHINE(spapr); 2168 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2169 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2170 int i; 2171 2172 for (i = 0; i < nr_lmbs; i++) { 2173 uint64_t addr; 2174 2175 addr = i * lmb_size + spapr->hotplug_memory.base; 2176 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2177 addr / lmb_size); 2178 } 2179 } 2180 2181 /* 2182 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2183 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2184 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2185 */ 2186 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2187 { 2188 int i; 2189 2190 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2191 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2192 " is not aligned to %llu MiB", 2193 machine->ram_size, 2194 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2195 return; 2196 } 2197 2198 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2199 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2200 " is not aligned to %llu MiB", 2201 machine->ram_size, 2202 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2203 return; 2204 } 2205 2206 for (i = 0; i < nb_numa_nodes; i++) { 2207 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2208 error_setg(errp, 2209 "Node %d memory size 0x%" PRIx64 2210 " is not aligned to %llu MiB", 2211 i, numa_info[i].node_mem, 2212 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2213 return; 2214 } 2215 } 2216 } 2217 2218 /* find cpu slot in machine->possible_cpus by core_id */ 2219 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2220 { 2221 int index = id / smp_threads; 2222 2223 if (index >= ms->possible_cpus->len) { 2224 return NULL; 2225 } 2226 if (idx) { 2227 *idx = index; 2228 } 2229 return &ms->possible_cpus->cpus[index]; 2230 } 2231 2232 static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp) 2233 { 2234 Error *local_err = NULL; 2235 bool vsmt_user = !!spapr->vsmt; 2236 int kvm_smt = kvmppc_smt_threads(); 2237 int ret; 2238 2239 if (!kvm_enabled() && (smp_threads > 1)) { 2240 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2241 "on a pseries machine"); 2242 goto out; 2243 } 2244 if (!is_power_of_2(smp_threads)) { 2245 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2246 "machine because it must be a power of 2", smp_threads); 2247 goto out; 2248 } 2249 2250 /* Detemine the VSMT mode to use: */ 2251 if (vsmt_user) { 2252 if (spapr->vsmt < smp_threads) { 2253 error_setg(&local_err, "Cannot support VSMT mode %d" 2254 " because it must be >= threads/core (%d)", 2255 spapr->vsmt, smp_threads); 2256 goto out; 2257 } 2258 /* In this case, spapr->vsmt has been set by the command line */ 2259 } else { 2260 /* 2261 * Default VSMT value is tricky, because we need it to be as 2262 * consistent as possible (for migration), but this requires 2263 * changing it for at least some existing cases. We pick 8 as 2264 * the value that we'd get with KVM on POWER8, the 2265 * overwhelmingly common case in production systems. 2266 */ 2267 spapr->vsmt = MAX(8, smp_threads); 2268 } 2269 2270 /* KVM: If necessary, set the SMT mode: */ 2271 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2272 ret = kvmppc_set_smt_threads(spapr->vsmt); 2273 if (ret) { 2274 /* Looks like KVM isn't able to change VSMT mode */ 2275 error_setg(&local_err, 2276 "Failed to set KVM's VSMT mode to %d (errno %d)", 2277 spapr->vsmt, ret); 2278 /* We can live with that if the default one is big enough 2279 * for the number of threads, and a submultiple of the one 2280 * we want. In this case we'll waste some vcpu ids, but 2281 * behaviour will be correct */ 2282 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2283 warn_report_err(local_err); 2284 local_err = NULL; 2285 goto out; 2286 } else { 2287 if (!vsmt_user) { 2288 error_append_hint(&local_err, 2289 "On PPC, a VM with %d threads/core" 2290 " on a host with %d threads/core" 2291 " requires the use of VSMT mode %d.\n", 2292 smp_threads, kvm_smt, spapr->vsmt); 2293 } 2294 kvmppc_hint_smt_possible(&local_err); 2295 goto out; 2296 } 2297 } 2298 } 2299 /* else TCG: nothing to do currently */ 2300 out: 2301 error_propagate(errp, local_err); 2302 } 2303 2304 static void spapr_init_cpus(sPAPRMachineState *spapr) 2305 { 2306 MachineState *machine = MACHINE(spapr); 2307 MachineClass *mc = MACHINE_GET_CLASS(machine); 2308 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2309 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2310 const CPUArchIdList *possible_cpus; 2311 int boot_cores_nr = smp_cpus / smp_threads; 2312 int i; 2313 2314 possible_cpus = mc->possible_cpu_arch_ids(machine); 2315 if (mc->has_hotpluggable_cpus) { 2316 if (smp_cpus % smp_threads) { 2317 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2318 smp_cpus, smp_threads); 2319 exit(1); 2320 } 2321 if (max_cpus % smp_threads) { 2322 error_report("max_cpus (%u) must be multiple of threads (%u)", 2323 max_cpus, smp_threads); 2324 exit(1); 2325 } 2326 } else { 2327 if (max_cpus != smp_cpus) { 2328 error_report("This machine version does not support CPU hotplug"); 2329 exit(1); 2330 } 2331 boot_cores_nr = possible_cpus->len; 2332 } 2333 2334 /* VSMT must be set in order to be able to compute VCPU ids, ie to 2335 * call xics_max_server_number() or spapr_vcpu_id(). 2336 */ 2337 spapr_set_vsmt_mode(spapr, &error_fatal); 2338 2339 if (smc->pre_2_10_has_unused_icps) { 2340 int i; 2341 2342 for (i = 0; i < xics_max_server_number(spapr); i++) { 2343 /* Dummy entries get deregistered when real ICPState objects 2344 * are registered during CPU core hotplug. 2345 */ 2346 pre_2_10_vmstate_register_dummy_icp(i); 2347 } 2348 } 2349 2350 for (i = 0; i < possible_cpus->len; i++) { 2351 int core_id = i * smp_threads; 2352 2353 if (mc->has_hotpluggable_cpus) { 2354 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2355 spapr_vcpu_id(spapr, core_id)); 2356 } 2357 2358 if (i < boot_cores_nr) { 2359 Object *core = object_new(type); 2360 int nr_threads = smp_threads; 2361 2362 /* Handle the partially filled core for older machine types */ 2363 if ((i + 1) * smp_threads >= smp_cpus) { 2364 nr_threads = smp_cpus - i * smp_threads; 2365 } 2366 2367 object_property_set_int(core, nr_threads, "nr-threads", 2368 &error_fatal); 2369 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2370 &error_fatal); 2371 object_property_set_bool(core, true, "realized", &error_fatal); 2372 } 2373 } 2374 } 2375 2376 /* pSeries LPAR / sPAPR hardware init */ 2377 static void spapr_machine_init(MachineState *machine) 2378 { 2379 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2380 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2381 const char *kernel_filename = machine->kernel_filename; 2382 const char *initrd_filename = machine->initrd_filename; 2383 PCIHostState *phb; 2384 int i; 2385 MemoryRegion *sysmem = get_system_memory(); 2386 MemoryRegion *ram = g_new(MemoryRegion, 1); 2387 MemoryRegion *rma_region; 2388 void *rma = NULL; 2389 hwaddr rma_alloc_size; 2390 hwaddr node0_size = spapr_node0_size(machine); 2391 long load_limit, fw_size; 2392 char *filename; 2393 Error *resize_hpt_err = NULL; 2394 2395 msi_nonbroken = true; 2396 2397 QLIST_INIT(&spapr->phbs); 2398 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2399 2400 /* Check HPT resizing availability */ 2401 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2402 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2403 /* 2404 * If the user explicitly requested a mode we should either 2405 * supply it, or fail completely (which we do below). But if 2406 * it's not set explicitly, we reset our mode to something 2407 * that works 2408 */ 2409 if (resize_hpt_err) { 2410 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2411 error_free(resize_hpt_err); 2412 resize_hpt_err = NULL; 2413 } else { 2414 spapr->resize_hpt = smc->resize_hpt_default; 2415 } 2416 } 2417 2418 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2419 2420 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2421 /* 2422 * User requested HPT resize, but this host can't supply it. Bail out 2423 */ 2424 error_report_err(resize_hpt_err); 2425 exit(1); 2426 } 2427 2428 /* Allocate RMA if necessary */ 2429 rma_alloc_size = kvmppc_alloc_rma(&rma); 2430 2431 if (rma_alloc_size == -1) { 2432 error_report("Unable to create RMA"); 2433 exit(1); 2434 } 2435 2436 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 2437 spapr->rma_size = rma_alloc_size; 2438 } else { 2439 spapr->rma_size = node0_size; 2440 2441 /* With KVM, we don't actually know whether KVM supports an 2442 * unbounded RMA (PR KVM) or is limited by the hash table size 2443 * (HV KVM using VRMA), so we always assume the latter 2444 * 2445 * In that case, we also limit the initial allocations for RTAS 2446 * etc... to 256M since we have no way to know what the VRMA size 2447 * is going to be as it depends on the size of the hash table 2448 * isn't determined yet. 2449 */ 2450 if (kvm_enabled()) { 2451 spapr->vrma_adjust = 1; 2452 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2453 } 2454 2455 /* Actually we don't support unbounded RMA anymore since we 2456 * added proper emulation of HV mode. The max we can get is 2457 * 16G which also happens to be what we configure for PAPR 2458 * mode so make sure we don't do anything bigger than that 2459 */ 2460 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2461 } 2462 2463 if (spapr->rma_size > node0_size) { 2464 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2465 spapr->rma_size); 2466 exit(1); 2467 } 2468 2469 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2470 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2471 2472 /* Set up Interrupt Controller before we create the VCPUs */ 2473 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal); 2474 2475 /* Set up containers for ibm,client-architecture-support negotiated options 2476 */ 2477 spapr->ov5 = spapr_ovec_new(); 2478 spapr->ov5_cas = spapr_ovec_new(); 2479 2480 if (smc->dr_lmb_enabled) { 2481 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2482 spapr_validate_node_memory(machine, &error_fatal); 2483 } 2484 2485 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2486 if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) { 2487 /* KVM and TCG always allow GTSE with radix... */ 2488 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2489 } 2490 /* ... but not with hash (currently). */ 2491 2492 /* advertise support for dedicated HP event source to guests */ 2493 if (spapr->use_hotplug_event_source) { 2494 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2495 } 2496 2497 /* advertise support for HPT resizing */ 2498 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2499 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2500 } 2501 2502 /* init CPUs */ 2503 spapr_init_cpus(spapr); 2504 2505 if (kvm_enabled()) { 2506 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2507 kvmppc_enable_logical_ci_hcalls(); 2508 kvmppc_enable_set_mode_hcall(); 2509 2510 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2511 kvmppc_enable_clear_ref_mod_hcalls(); 2512 } 2513 2514 /* allocate RAM */ 2515 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2516 machine->ram_size); 2517 memory_region_add_subregion(sysmem, 0, ram); 2518 2519 if (rma_alloc_size && rma) { 2520 rma_region = g_new(MemoryRegion, 1); 2521 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 2522 rma_alloc_size, rma); 2523 vmstate_register_ram_global(rma_region); 2524 memory_region_add_subregion(sysmem, 0, rma_region); 2525 } 2526 2527 /* initialize hotplug memory address space */ 2528 if (machine->ram_size < machine->maxram_size) { 2529 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 2530 /* 2531 * Limit the number of hotpluggable memory slots to half the number 2532 * slots that KVM supports, leaving the other half for PCI and other 2533 * devices. However ensure that number of slots doesn't drop below 32. 2534 */ 2535 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2536 SPAPR_MAX_RAM_SLOTS; 2537 2538 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2539 max_memslots = SPAPR_MAX_RAM_SLOTS; 2540 } 2541 if (machine->ram_slots > max_memslots) { 2542 error_report("Specified number of memory slots %" 2543 PRIu64" exceeds max supported %d", 2544 machine->ram_slots, max_memslots); 2545 exit(1); 2546 } 2547 2548 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 2549 SPAPR_HOTPLUG_MEM_ALIGN); 2550 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 2551 "hotplug-memory", hotplug_mem_size); 2552 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 2553 &spapr->hotplug_memory.mr); 2554 } 2555 2556 if (smc->dr_lmb_enabled) { 2557 spapr_create_lmb_dr_connectors(spapr); 2558 } 2559 2560 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2561 if (!filename) { 2562 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2563 exit(1); 2564 } 2565 spapr->rtas_size = get_image_size(filename); 2566 if (spapr->rtas_size < 0) { 2567 error_report("Could not get size of LPAR rtas '%s'", filename); 2568 exit(1); 2569 } 2570 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2571 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2572 error_report("Could not load LPAR rtas '%s'", filename); 2573 exit(1); 2574 } 2575 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2576 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2577 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2578 exit(1); 2579 } 2580 g_free(filename); 2581 2582 /* Set up RTAS event infrastructure */ 2583 spapr_events_init(spapr); 2584 2585 /* Set up the RTC RTAS interfaces */ 2586 spapr_rtc_create(spapr); 2587 2588 /* Set up VIO bus */ 2589 spapr->vio_bus = spapr_vio_bus_init(); 2590 2591 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 2592 if (serial_hds[i]) { 2593 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 2594 } 2595 } 2596 2597 /* We always have at least the nvram device on VIO */ 2598 spapr_create_nvram(spapr); 2599 2600 /* Set up PCI */ 2601 spapr_pci_rtas_init(); 2602 2603 phb = spapr_create_phb(spapr, 0); 2604 2605 for (i = 0; i < nb_nics; i++) { 2606 NICInfo *nd = &nd_table[i]; 2607 2608 if (!nd->model) { 2609 nd->model = g_strdup("spapr-vlan"); 2610 } 2611 2612 if (g_str_equal(nd->model, "spapr-vlan") || 2613 g_str_equal(nd->model, "ibmveth")) { 2614 spapr_vlan_create(spapr->vio_bus, nd); 2615 } else { 2616 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2617 } 2618 } 2619 2620 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2621 spapr_vscsi_create(spapr->vio_bus); 2622 } 2623 2624 /* Graphics */ 2625 if (spapr_vga_init(phb->bus, &error_fatal)) { 2626 spapr->has_graphics = true; 2627 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2628 } 2629 2630 if (machine->usb) { 2631 if (smc->use_ohci_by_default) { 2632 pci_create_simple(phb->bus, -1, "pci-ohci"); 2633 } else { 2634 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2635 } 2636 2637 if (spapr->has_graphics) { 2638 USBBus *usb_bus = usb_bus_find(-1); 2639 2640 usb_create_simple(usb_bus, "usb-kbd"); 2641 usb_create_simple(usb_bus, "usb-mouse"); 2642 } 2643 } 2644 2645 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 2646 error_report( 2647 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2648 MIN_RMA_SLOF); 2649 exit(1); 2650 } 2651 2652 if (kernel_filename) { 2653 uint64_t lowaddr = 0; 2654 2655 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2656 NULL, NULL, &lowaddr, NULL, 1, 2657 PPC_ELF_MACHINE, 0, 0); 2658 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2659 spapr->kernel_size = load_elf(kernel_filename, 2660 translate_kernel_address, NULL, NULL, 2661 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2662 0, 0); 2663 spapr->kernel_le = spapr->kernel_size > 0; 2664 } 2665 if (spapr->kernel_size < 0) { 2666 error_report("error loading %s: %s", kernel_filename, 2667 load_elf_strerror(spapr->kernel_size)); 2668 exit(1); 2669 } 2670 2671 /* load initrd */ 2672 if (initrd_filename) { 2673 /* Try to locate the initrd in the gap between the kernel 2674 * and the firmware. Add a bit of space just in case 2675 */ 2676 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2677 + 0x1ffff) & ~0xffff; 2678 spapr->initrd_size = load_image_targphys(initrd_filename, 2679 spapr->initrd_base, 2680 load_limit 2681 - spapr->initrd_base); 2682 if (spapr->initrd_size < 0) { 2683 error_report("could not load initial ram disk '%s'", 2684 initrd_filename); 2685 exit(1); 2686 } 2687 } 2688 } 2689 2690 if (bios_name == NULL) { 2691 bios_name = FW_FILE_NAME; 2692 } 2693 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2694 if (!filename) { 2695 error_report("Could not find LPAR firmware '%s'", bios_name); 2696 exit(1); 2697 } 2698 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2699 if (fw_size <= 0) { 2700 error_report("Could not load LPAR firmware '%s'", filename); 2701 exit(1); 2702 } 2703 g_free(filename); 2704 2705 /* FIXME: Should register things through the MachineState's qdev 2706 * interface, this is a legacy from the sPAPREnvironment structure 2707 * which predated MachineState but had a similar function */ 2708 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2709 register_savevm_live(NULL, "spapr/htab", -1, 1, 2710 &savevm_htab_handlers, spapr); 2711 2712 qemu_register_boot_set(spapr_boot_set, spapr); 2713 2714 if (kvm_enabled()) { 2715 /* to stop and start vmclock */ 2716 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2717 &spapr->tb); 2718 2719 kvmppc_spapr_enable_inkernel_multitce(); 2720 } 2721 } 2722 2723 static int spapr_kvm_type(const char *vm_type) 2724 { 2725 if (!vm_type) { 2726 return 0; 2727 } 2728 2729 if (!strcmp(vm_type, "HV")) { 2730 return 1; 2731 } 2732 2733 if (!strcmp(vm_type, "PR")) { 2734 return 2; 2735 } 2736 2737 error_report("Unknown kvm-type specified '%s'", vm_type); 2738 exit(1); 2739 } 2740 2741 /* 2742 * Implementation of an interface to adjust firmware path 2743 * for the bootindex property handling. 2744 */ 2745 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2746 DeviceState *dev) 2747 { 2748 #define CAST(type, obj, name) \ 2749 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2750 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2751 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2752 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 2753 2754 if (d) { 2755 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2756 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2757 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2758 2759 if (spapr) { 2760 /* 2761 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2762 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2763 * in the top 16 bits of the 64-bit LUN 2764 */ 2765 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2766 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2767 (uint64_t)id << 48); 2768 } else if (virtio) { 2769 /* 2770 * We use SRP luns of the form 01000000 | (target << 8) | lun 2771 * in the top 32 bits of the 64-bit LUN 2772 * Note: the quote above is from SLOF and it is wrong, 2773 * the actual binding is: 2774 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2775 */ 2776 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2777 if (d->lun >= 256) { 2778 /* Use the LUN "flat space addressing method" */ 2779 id |= 0x4000; 2780 } 2781 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2782 (uint64_t)id << 32); 2783 } else if (usb) { 2784 /* 2785 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2786 * in the top 32 bits of the 64-bit LUN 2787 */ 2788 unsigned usb_port = atoi(usb->port->path); 2789 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2790 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2791 (uint64_t)id << 32); 2792 } 2793 } 2794 2795 /* 2796 * SLOF probes the USB devices, and if it recognizes that the device is a 2797 * storage device, it changes its name to "storage" instead of "usb-host", 2798 * and additionally adds a child node for the SCSI LUN, so the correct 2799 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2800 */ 2801 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2802 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2803 if (usb_host_dev_is_scsi_storage(usbdev)) { 2804 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2805 } 2806 } 2807 2808 if (phb) { 2809 /* Replace "pci" with "pci@800000020000000" */ 2810 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2811 } 2812 2813 if (vsc) { 2814 /* Same logic as virtio above */ 2815 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 2816 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 2817 } 2818 2819 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 2820 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 2821 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 2822 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 2823 } 2824 2825 return NULL; 2826 } 2827 2828 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2829 { 2830 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2831 2832 return g_strdup(spapr->kvm_type); 2833 } 2834 2835 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2836 { 2837 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2838 2839 g_free(spapr->kvm_type); 2840 spapr->kvm_type = g_strdup(value); 2841 } 2842 2843 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2844 { 2845 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2846 2847 return spapr->use_hotplug_event_source; 2848 } 2849 2850 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2851 Error **errp) 2852 { 2853 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2854 2855 spapr->use_hotplug_event_source = value; 2856 } 2857 2858 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 2859 { 2860 return true; 2861 } 2862 2863 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 2864 { 2865 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2866 2867 switch (spapr->resize_hpt) { 2868 case SPAPR_RESIZE_HPT_DEFAULT: 2869 return g_strdup("default"); 2870 case SPAPR_RESIZE_HPT_DISABLED: 2871 return g_strdup("disabled"); 2872 case SPAPR_RESIZE_HPT_ENABLED: 2873 return g_strdup("enabled"); 2874 case SPAPR_RESIZE_HPT_REQUIRED: 2875 return g_strdup("required"); 2876 } 2877 g_assert_not_reached(); 2878 } 2879 2880 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 2881 { 2882 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2883 2884 if (strcmp(value, "default") == 0) { 2885 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 2886 } else if (strcmp(value, "disabled") == 0) { 2887 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2888 } else if (strcmp(value, "enabled") == 0) { 2889 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 2890 } else if (strcmp(value, "required") == 0) { 2891 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 2892 } else { 2893 error_setg(errp, "Bad value for \"resize-hpt\" property"); 2894 } 2895 } 2896 2897 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 2898 void *opaque, Error **errp) 2899 { 2900 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 2901 } 2902 2903 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 2904 void *opaque, Error **errp) 2905 { 2906 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 2907 } 2908 2909 static void spapr_instance_init(Object *obj) 2910 { 2911 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2912 2913 spapr->htab_fd = -1; 2914 spapr->use_hotplug_event_source = true; 2915 object_property_add_str(obj, "kvm-type", 2916 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2917 object_property_set_description(obj, "kvm-type", 2918 "Specifies the KVM virtualization mode (HV, PR)", 2919 NULL); 2920 object_property_add_bool(obj, "modern-hotplug-events", 2921 spapr_get_modern_hotplug_events, 2922 spapr_set_modern_hotplug_events, 2923 NULL); 2924 object_property_set_description(obj, "modern-hotplug-events", 2925 "Use dedicated hotplug event mechanism in" 2926 " place of standard EPOW events when possible" 2927 " (required for memory hot-unplug support)", 2928 NULL); 2929 2930 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 2931 "Maximum permitted CPU compatibility mode", 2932 &error_fatal); 2933 2934 object_property_add_str(obj, "resize-hpt", 2935 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 2936 object_property_set_description(obj, "resize-hpt", 2937 "Resizing of the Hash Page Table (enabled, disabled, required)", 2938 NULL); 2939 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 2940 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 2941 object_property_set_description(obj, "vsmt", 2942 "Virtual SMT: KVM behaves as if this were" 2943 " the host's SMT mode", &error_abort); 2944 object_property_add_bool(obj, "vfio-no-msix-emulation", 2945 spapr_get_msix_emulation, NULL, NULL); 2946 } 2947 2948 static void spapr_machine_finalizefn(Object *obj) 2949 { 2950 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2951 2952 g_free(spapr->kvm_type); 2953 } 2954 2955 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 2956 { 2957 cpu_synchronize_state(cs); 2958 ppc_cpu_do_system_reset(cs); 2959 } 2960 2961 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2962 { 2963 CPUState *cs; 2964 2965 CPU_FOREACH(cs) { 2966 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 2967 } 2968 } 2969 2970 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2971 uint32_t node, bool dedicated_hp_event_source, 2972 Error **errp) 2973 { 2974 sPAPRDRConnector *drc; 2975 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2976 int i, fdt_offset, fdt_size; 2977 void *fdt; 2978 uint64_t addr = addr_start; 2979 bool hotplugged = spapr_drc_hotplugged(dev); 2980 Error *local_err = NULL; 2981 2982 for (i = 0; i < nr_lmbs; i++) { 2983 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2984 addr / SPAPR_MEMORY_BLOCK_SIZE); 2985 g_assert(drc); 2986 2987 fdt = create_device_tree(&fdt_size); 2988 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2989 SPAPR_MEMORY_BLOCK_SIZE); 2990 2991 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 2992 if (local_err) { 2993 while (addr > addr_start) { 2994 addr -= SPAPR_MEMORY_BLOCK_SIZE; 2995 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2996 addr / SPAPR_MEMORY_BLOCK_SIZE); 2997 spapr_drc_detach(drc); 2998 } 2999 g_free(fdt); 3000 error_propagate(errp, local_err); 3001 return; 3002 } 3003 if (!hotplugged) { 3004 spapr_drc_reset(drc); 3005 } 3006 addr += SPAPR_MEMORY_BLOCK_SIZE; 3007 } 3008 /* send hotplug notification to the 3009 * guest only in case of hotplugged memory 3010 */ 3011 if (hotplugged) { 3012 if (dedicated_hp_event_source) { 3013 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3014 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3015 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3016 nr_lmbs, 3017 spapr_drc_index(drc)); 3018 } else { 3019 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3020 nr_lmbs); 3021 } 3022 } 3023 } 3024 3025 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3026 uint32_t node, Error **errp) 3027 { 3028 Error *local_err = NULL; 3029 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3030 PCDIMMDevice *dimm = PC_DIMM(dev); 3031 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3032 MemoryRegion *mr; 3033 uint64_t align, size, addr; 3034 3035 mr = ddc->get_memory_region(dimm, &local_err); 3036 if (local_err) { 3037 goto out; 3038 } 3039 align = memory_region_get_alignment(mr); 3040 size = memory_region_size(mr); 3041 3042 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 3043 if (local_err) { 3044 goto out; 3045 } 3046 3047 addr = object_property_get_uint(OBJECT(dimm), 3048 PC_DIMM_ADDR_PROP, &local_err); 3049 if (local_err) { 3050 goto out_unplug; 3051 } 3052 3053 spapr_add_lmbs(dev, addr, size, node, 3054 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3055 &local_err); 3056 if (local_err) { 3057 goto out_unplug; 3058 } 3059 3060 return; 3061 3062 out_unplug: 3063 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 3064 out: 3065 error_propagate(errp, local_err); 3066 } 3067 3068 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3069 Error **errp) 3070 { 3071 PCDIMMDevice *dimm = PC_DIMM(dev); 3072 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3073 MemoryRegion *mr; 3074 uint64_t size; 3075 char *mem_dev; 3076 3077 mr = ddc->get_memory_region(dimm, errp); 3078 if (!mr) { 3079 return; 3080 } 3081 size = memory_region_size(mr); 3082 3083 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3084 error_setg(errp, "Hotplugged memory size must be a multiple of " 3085 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 3086 return; 3087 } 3088 3089 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); 3090 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { 3091 error_setg(errp, "Memory backend has bad page size. " 3092 "Use 'memory-backend-file' with correct mem-path."); 3093 goto out; 3094 } 3095 3096 out: 3097 g_free(mem_dev); 3098 } 3099 3100 struct sPAPRDIMMState { 3101 PCDIMMDevice *dimm; 3102 uint32_t nr_lmbs; 3103 QTAILQ_ENTRY(sPAPRDIMMState) next; 3104 }; 3105 3106 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, 3107 PCDIMMDevice *dimm) 3108 { 3109 sPAPRDIMMState *dimm_state = NULL; 3110 3111 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3112 if (dimm_state->dimm == dimm) { 3113 break; 3114 } 3115 } 3116 return dimm_state; 3117 } 3118 3119 static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, 3120 uint32_t nr_lmbs, 3121 PCDIMMDevice *dimm) 3122 { 3123 sPAPRDIMMState *ds = NULL; 3124 3125 /* 3126 * If this request is for a DIMM whose removal had failed earlier 3127 * (due to guest's refusal to remove the LMBs), we would have this 3128 * dimm already in the pending_dimm_unplugs list. In that 3129 * case don't add again. 3130 */ 3131 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3132 if (!ds) { 3133 ds = g_malloc0(sizeof(sPAPRDIMMState)); 3134 ds->nr_lmbs = nr_lmbs; 3135 ds->dimm = dimm; 3136 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3137 } 3138 return ds; 3139 } 3140 3141 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, 3142 sPAPRDIMMState *dimm_state) 3143 { 3144 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3145 g_free(dimm_state); 3146 } 3147 3148 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, 3149 PCDIMMDevice *dimm) 3150 { 3151 sPAPRDRConnector *drc; 3152 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3153 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); 3154 uint64_t size = memory_region_size(mr); 3155 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3156 uint32_t avail_lmbs = 0; 3157 uint64_t addr_start, addr; 3158 int i; 3159 3160 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3161 &error_abort); 3162 3163 addr = addr_start; 3164 for (i = 0; i < nr_lmbs; i++) { 3165 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3166 addr / SPAPR_MEMORY_BLOCK_SIZE); 3167 g_assert(drc); 3168 if (drc->dev) { 3169 avail_lmbs++; 3170 } 3171 addr += SPAPR_MEMORY_BLOCK_SIZE; 3172 } 3173 3174 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3175 } 3176 3177 /* Callback to be called during DRC release. */ 3178 void spapr_lmb_release(DeviceState *dev) 3179 { 3180 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_hotplug_handler(dev)); 3181 PCDIMMDevice *dimm = PC_DIMM(dev); 3182 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3183 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); 3184 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3185 3186 /* This information will get lost if a migration occurs 3187 * during the unplug process. In this case recover it. */ 3188 if (ds == NULL) { 3189 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3190 g_assert(ds); 3191 /* The DRC being examined by the caller at least must be counted */ 3192 g_assert(ds->nr_lmbs); 3193 } 3194 3195 if (--ds->nr_lmbs) { 3196 return; 3197 } 3198 3199 /* 3200 * Now that all the LMBs have been removed by the guest, call the 3201 * pc-dimm unplug handler to cleanup up the pc-dimm device. 3202 */ 3203 pc_dimm_memory_unplug(dev, &spapr->hotplug_memory, mr); 3204 object_unparent(OBJECT(dev)); 3205 spapr_pending_dimm_unplugs_remove(spapr, ds); 3206 } 3207 3208 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3209 DeviceState *dev, Error **errp) 3210 { 3211 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3212 Error *local_err = NULL; 3213 PCDIMMDevice *dimm = PC_DIMM(dev); 3214 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3215 MemoryRegion *mr; 3216 uint32_t nr_lmbs; 3217 uint64_t size, addr_start, addr; 3218 int i; 3219 sPAPRDRConnector *drc; 3220 3221 mr = ddc->get_memory_region(dimm, &local_err); 3222 if (local_err) { 3223 goto out; 3224 } 3225 size = memory_region_size(mr); 3226 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3227 3228 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3229 &local_err); 3230 if (local_err) { 3231 goto out; 3232 } 3233 3234 /* 3235 * An existing pending dimm state for this DIMM means that there is an 3236 * unplug operation in progress, waiting for the spapr_lmb_release 3237 * callback to complete the job (BQL can't cover that far). In this case, 3238 * bail out to avoid detaching DRCs that were already released. 3239 */ 3240 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3241 error_setg(&local_err, 3242 "Memory unplug already in progress for device %s", 3243 dev->id); 3244 goto out; 3245 } 3246 3247 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3248 3249 addr = addr_start; 3250 for (i = 0; i < nr_lmbs; i++) { 3251 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3252 addr / SPAPR_MEMORY_BLOCK_SIZE); 3253 g_assert(drc); 3254 3255 spapr_drc_detach(drc); 3256 addr += SPAPR_MEMORY_BLOCK_SIZE; 3257 } 3258 3259 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3260 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3261 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3262 nr_lmbs, spapr_drc_index(drc)); 3263 out: 3264 error_propagate(errp, local_err); 3265 } 3266 3267 static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 3268 sPAPRMachineState *spapr) 3269 { 3270 PowerPCCPU *cpu = POWERPC_CPU(cs); 3271 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3272 int id = spapr_get_vcpu_id(cpu); 3273 void *fdt; 3274 int offset, fdt_size; 3275 char *nodename; 3276 3277 fdt = create_device_tree(&fdt_size); 3278 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3279 offset = fdt_add_subnode(fdt, 0, nodename); 3280 3281 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3282 g_free(nodename); 3283 3284 *fdt_offset = offset; 3285 return fdt; 3286 } 3287 3288 /* Callback to be called during DRC release. */ 3289 void spapr_core_release(DeviceState *dev) 3290 { 3291 MachineState *ms = MACHINE(qdev_get_hotplug_handler(dev)); 3292 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3293 CPUCore *cc = CPU_CORE(dev); 3294 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3295 3296 if (smc->pre_2_10_has_unused_icps) { 3297 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3298 int i; 3299 3300 for (i = 0; i < cc->nr_threads; i++) { 3301 CPUState *cs = CPU(sc->threads[i]); 3302 3303 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3304 } 3305 } 3306 3307 assert(core_slot); 3308 core_slot->cpu = NULL; 3309 object_unparent(OBJECT(dev)); 3310 } 3311 3312 static 3313 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3314 Error **errp) 3315 { 3316 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3317 int index; 3318 sPAPRDRConnector *drc; 3319 CPUCore *cc = CPU_CORE(dev); 3320 3321 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3322 error_setg(errp, "Unable to find CPU core with core-id: %d", 3323 cc->core_id); 3324 return; 3325 } 3326 if (index == 0) { 3327 error_setg(errp, "Boot CPU core may not be unplugged"); 3328 return; 3329 } 3330 3331 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3332 spapr_vcpu_id(spapr, cc->core_id)); 3333 g_assert(drc); 3334 3335 spapr_drc_detach(drc); 3336 3337 spapr_hotplug_req_remove_by_index(drc); 3338 } 3339 3340 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3341 Error **errp) 3342 { 3343 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3344 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3345 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3346 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3347 CPUCore *cc = CPU_CORE(dev); 3348 CPUState *cs = CPU(core->threads[0]); 3349 sPAPRDRConnector *drc; 3350 Error *local_err = NULL; 3351 CPUArchId *core_slot; 3352 int index; 3353 bool hotplugged = spapr_drc_hotplugged(dev); 3354 3355 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3356 if (!core_slot) { 3357 error_setg(errp, "Unable to find CPU core with core-id: %d", 3358 cc->core_id); 3359 return; 3360 } 3361 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3362 spapr_vcpu_id(spapr, cc->core_id)); 3363 3364 g_assert(drc || !mc->has_hotpluggable_cpus); 3365 3366 if (drc) { 3367 void *fdt; 3368 int fdt_offset; 3369 3370 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 3371 3372 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 3373 if (local_err) { 3374 g_free(fdt); 3375 error_propagate(errp, local_err); 3376 return; 3377 } 3378 3379 if (hotplugged) { 3380 /* 3381 * Send hotplug notification interrupt to the guest only 3382 * in case of hotplugged CPUs. 3383 */ 3384 spapr_hotplug_req_add_by_index(drc); 3385 } else { 3386 spapr_drc_reset(drc); 3387 } 3388 } 3389 3390 core_slot->cpu = OBJECT(dev); 3391 3392 if (smc->pre_2_10_has_unused_icps) { 3393 int i; 3394 3395 for (i = 0; i < cc->nr_threads; i++) { 3396 cs = CPU(core->threads[i]); 3397 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3398 } 3399 } 3400 } 3401 3402 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3403 Error **errp) 3404 { 3405 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3406 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3407 Error *local_err = NULL; 3408 CPUCore *cc = CPU_CORE(dev); 3409 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3410 const char *type = object_get_typename(OBJECT(dev)); 3411 CPUArchId *core_slot; 3412 int index; 3413 3414 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3415 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3416 goto out; 3417 } 3418 3419 if (strcmp(base_core_type, type)) { 3420 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3421 goto out; 3422 } 3423 3424 if (cc->core_id % smp_threads) { 3425 error_setg(&local_err, "invalid core id %d", cc->core_id); 3426 goto out; 3427 } 3428 3429 /* 3430 * In general we should have homogeneous threads-per-core, but old 3431 * (pre hotplug support) machine types allow the last core to have 3432 * reduced threads as a compatibility hack for when we allowed 3433 * total vcpus not a multiple of threads-per-core. 3434 */ 3435 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3436 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3437 cc->nr_threads, smp_threads); 3438 goto out; 3439 } 3440 3441 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3442 if (!core_slot) { 3443 error_setg(&local_err, "core id %d out of range", cc->core_id); 3444 goto out; 3445 } 3446 3447 if (core_slot->cpu) { 3448 error_setg(&local_err, "core %d already populated", cc->core_id); 3449 goto out; 3450 } 3451 3452 numa_cpu_pre_plug(core_slot, dev, &local_err); 3453 3454 out: 3455 error_propagate(errp, local_err); 3456 } 3457 3458 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 3459 DeviceState *dev, Error **errp) 3460 { 3461 MachineState *ms = MACHINE(hotplug_dev); 3462 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3463 3464 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3465 int node; 3466 3467 if (!smc->dr_lmb_enabled) { 3468 error_setg(errp, "Memory hotplug not supported for this machine"); 3469 return; 3470 } 3471 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 3472 if (*errp) { 3473 return; 3474 } 3475 if (node < 0 || node >= MAX_NODES) { 3476 error_setg(errp, "Invaild node %d", node); 3477 return; 3478 } 3479 3480 /* 3481 * Currently PowerPC kernel doesn't allow hot-adding memory to 3482 * memory-less node, but instead will silently add the memory 3483 * to the first node that has some memory. This causes two 3484 * unexpected behaviours for the user. 3485 * 3486 * - Memory gets hotplugged to a different node than what the user 3487 * specified. 3488 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 3489 * to memory-less node, a reboot will set things accordingly 3490 * and the previously hotplugged memory now ends in the right node. 3491 * This appears as if some memory moved from one node to another. 3492 * 3493 * So until kernel starts supporting memory hotplug to memory-less 3494 * nodes, just prevent such attempts upfront in QEMU. 3495 */ 3496 if (nb_numa_nodes && !numa_info[node].node_mem) { 3497 error_setg(errp, "Can't hotplug memory to memory-less node %d", 3498 node); 3499 return; 3500 } 3501 3502 spapr_memory_plug(hotplug_dev, dev, node, errp); 3503 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3504 spapr_core_plug(hotplug_dev, dev, errp); 3505 } 3506 } 3507 3508 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 3509 DeviceState *dev, Error **errp) 3510 { 3511 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3512 MachineClass *mc = MACHINE_GET_CLASS(sms); 3513 3514 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3515 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3516 spapr_memory_unplug_request(hotplug_dev, dev, errp); 3517 } else { 3518 /* NOTE: this means there is a window after guest reset, prior to 3519 * CAS negotiation, where unplug requests will fail due to the 3520 * capability not being detected yet. This is a bit different than 3521 * the case with PCI unplug, where the events will be queued and 3522 * eventually handled by the guest after boot 3523 */ 3524 error_setg(errp, "Memory hot unplug not supported for this guest"); 3525 } 3526 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3527 if (!mc->has_hotpluggable_cpus) { 3528 error_setg(errp, "CPU hot unplug not supported on this machine"); 3529 return; 3530 } 3531 spapr_core_unplug_request(hotplug_dev, dev, errp); 3532 } 3533 } 3534 3535 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 3536 DeviceState *dev, Error **errp) 3537 { 3538 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3539 spapr_memory_pre_plug(hotplug_dev, dev, errp); 3540 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3541 spapr_core_pre_plug(hotplug_dev, dev, errp); 3542 } 3543 } 3544 3545 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 3546 DeviceState *dev) 3547 { 3548 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3549 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3550 return HOTPLUG_HANDLER(machine); 3551 } 3552 return NULL; 3553 } 3554 3555 static CpuInstanceProperties 3556 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 3557 { 3558 CPUArchId *core_slot; 3559 MachineClass *mc = MACHINE_GET_CLASS(machine); 3560 3561 /* make sure possible_cpu are intialized */ 3562 mc->possible_cpu_arch_ids(machine); 3563 /* get CPU core slot containing thread that matches cpu_index */ 3564 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 3565 assert(core_slot); 3566 return core_slot->props; 3567 } 3568 3569 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 3570 { 3571 return idx / smp_cores % nb_numa_nodes; 3572 } 3573 3574 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 3575 { 3576 int i; 3577 const char *core_type; 3578 int spapr_max_cores = max_cpus / smp_threads; 3579 MachineClass *mc = MACHINE_GET_CLASS(machine); 3580 3581 if (!mc->has_hotpluggable_cpus) { 3582 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 3583 } 3584 if (machine->possible_cpus) { 3585 assert(machine->possible_cpus->len == spapr_max_cores); 3586 return machine->possible_cpus; 3587 } 3588 3589 core_type = spapr_get_cpu_core_type(machine->cpu_type); 3590 if (!core_type) { 3591 error_report("Unable to find sPAPR CPU Core definition"); 3592 exit(1); 3593 } 3594 3595 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 3596 sizeof(CPUArchId) * spapr_max_cores); 3597 machine->possible_cpus->len = spapr_max_cores; 3598 for (i = 0; i < machine->possible_cpus->len; i++) { 3599 int core_id = i * smp_threads; 3600 3601 machine->possible_cpus->cpus[i].type = core_type; 3602 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 3603 machine->possible_cpus->cpus[i].arch_id = core_id; 3604 machine->possible_cpus->cpus[i].props.has_core_id = true; 3605 machine->possible_cpus->cpus[i].props.core_id = core_id; 3606 } 3607 return machine->possible_cpus; 3608 } 3609 3610 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 3611 uint64_t *buid, hwaddr *pio, 3612 hwaddr *mmio32, hwaddr *mmio64, 3613 unsigned n_dma, uint32_t *liobns, Error **errp) 3614 { 3615 /* 3616 * New-style PHB window placement. 3617 * 3618 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 3619 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 3620 * windows. 3621 * 3622 * Some guest kernels can't work with MMIO windows above 1<<46 3623 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 3624 * 3625 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 3626 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 3627 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 3628 * 1TiB 64-bit MMIO windows for each PHB. 3629 */ 3630 const uint64_t base_buid = 0x800000020000000ULL; 3631 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 3632 SPAPR_PCI_MEM64_WIN_SIZE - 1) 3633 int i; 3634 3635 /* Sanity check natural alignments */ 3636 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3637 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3638 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 3639 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 3640 /* Sanity check bounds */ 3641 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 3642 SPAPR_PCI_MEM32_WIN_SIZE); 3643 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 3644 SPAPR_PCI_MEM64_WIN_SIZE); 3645 3646 if (index >= SPAPR_MAX_PHBS) { 3647 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 3648 SPAPR_MAX_PHBS - 1); 3649 return; 3650 } 3651 3652 *buid = base_buid + index; 3653 for (i = 0; i < n_dma; ++i) { 3654 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3655 } 3656 3657 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 3658 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 3659 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 3660 } 3661 3662 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 3663 { 3664 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3665 3666 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 3667 } 3668 3669 static void spapr_ics_resend(XICSFabric *dev) 3670 { 3671 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3672 3673 ics_resend(spapr->ics); 3674 } 3675 3676 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 3677 { 3678 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 3679 3680 return cpu ? ICP(cpu->intc) : NULL; 3681 } 3682 3683 #define ICS_IRQ_FREE(ics, srcno) \ 3684 (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK))) 3685 3686 static int ics_find_free_block(ICSState *ics, int num, int alignnum) 3687 { 3688 int first, i; 3689 3690 for (first = 0; first < ics->nr_irqs; first += alignnum) { 3691 if (num > (ics->nr_irqs - first)) { 3692 return -1; 3693 } 3694 for (i = first; i < first + num; ++i) { 3695 if (!ICS_IRQ_FREE(ics, i)) { 3696 break; 3697 } 3698 } 3699 if (i == (first + num)) { 3700 return first; 3701 } 3702 } 3703 3704 return -1; 3705 } 3706 3707 /* 3708 * Allocate the IRQ number and set the IRQ type, LSI or MSI 3709 */ 3710 static void spapr_irq_set_lsi(sPAPRMachineState *spapr, int irq, bool lsi) 3711 { 3712 ics_set_irq_type(spapr->ics, irq - spapr->ics->offset, lsi); 3713 } 3714 3715 int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi, 3716 Error **errp) 3717 { 3718 ICSState *ics = spapr->ics; 3719 int irq; 3720 3721 if (!ics) { 3722 return -1; 3723 } 3724 if (irq_hint) { 3725 if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) { 3726 error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint); 3727 return -1; 3728 } 3729 irq = irq_hint; 3730 } else { 3731 irq = ics_find_free_block(ics, 1, 1); 3732 if (irq < 0) { 3733 error_setg(errp, "can't allocate IRQ: no IRQ left"); 3734 return -1; 3735 } 3736 irq += ics->offset; 3737 } 3738 3739 spapr_irq_set_lsi(spapr, irq, lsi); 3740 trace_spapr_irq_alloc(irq); 3741 3742 return irq; 3743 } 3744 3745 /* 3746 * Allocate block of consecutive IRQs, and return the number of the first IRQ in 3747 * the block. If align==true, aligns the first IRQ number to num. 3748 */ 3749 int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi, 3750 bool align, Error **errp) 3751 { 3752 ICSState *ics = spapr->ics; 3753 int i, first = -1; 3754 3755 if (!ics) { 3756 return -1; 3757 } 3758 3759 /* 3760 * MSIMesage::data is used for storing VIRQ so 3761 * it has to be aligned to num to support multiple 3762 * MSI vectors. MSI-X is not affected by this. 3763 * The hint is used for the first IRQ, the rest should 3764 * be allocated continuously. 3765 */ 3766 if (align) { 3767 assert((num == 1) || (num == 2) || (num == 4) || 3768 (num == 8) || (num == 16) || (num == 32)); 3769 first = ics_find_free_block(ics, num, num); 3770 } else { 3771 first = ics_find_free_block(ics, num, 1); 3772 } 3773 if (first < 0) { 3774 error_setg(errp, "can't find a free %d-IRQ block", num); 3775 return -1; 3776 } 3777 3778 first += ics->offset; 3779 for (i = first; i < first + num; ++i) { 3780 spapr_irq_set_lsi(spapr, i, lsi); 3781 } 3782 3783 trace_spapr_irq_alloc_block(first, num, lsi, align); 3784 3785 return first; 3786 } 3787 3788 void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num) 3789 { 3790 ICSState *ics = spapr->ics; 3791 int srcno = irq - ics->offset; 3792 int i; 3793 3794 if (ics_valid_irq(ics, irq)) { 3795 trace_spapr_irq_free(0, irq, num); 3796 for (i = srcno; i < srcno + num; ++i) { 3797 if (ICS_IRQ_FREE(ics, i)) { 3798 trace_spapr_irq_free_warn(0, i + ics->offset); 3799 } 3800 memset(&ics->irqs[i], 0, sizeof(ICSIRQState)); 3801 } 3802 } 3803 } 3804 3805 qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq) 3806 { 3807 ICSState *ics = spapr->ics; 3808 3809 if (ics_valid_irq(ics, irq)) { 3810 return ics->qirqs[irq - ics->offset]; 3811 } 3812 3813 return NULL; 3814 } 3815 3816 static void spapr_pic_print_info(InterruptStatsProvider *obj, 3817 Monitor *mon) 3818 { 3819 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3820 CPUState *cs; 3821 3822 CPU_FOREACH(cs) { 3823 PowerPCCPU *cpu = POWERPC_CPU(cs); 3824 3825 icp_pic_print_info(ICP(cpu->intc), mon); 3826 } 3827 3828 ics_pic_print_info(spapr->ics, mon); 3829 } 3830 3831 int spapr_get_vcpu_id(PowerPCCPU *cpu) 3832 { 3833 return cpu->vcpu_id; 3834 } 3835 3836 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 3837 { 3838 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3839 int vcpu_id; 3840 3841 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 3842 3843 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 3844 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 3845 error_append_hint(errp, "Adjust the number of cpus to %d " 3846 "or try to raise the number of threads per core\n", 3847 vcpu_id * smp_threads / spapr->vsmt); 3848 return; 3849 } 3850 3851 cpu->vcpu_id = vcpu_id; 3852 } 3853 3854 PowerPCCPU *spapr_find_cpu(int vcpu_id) 3855 { 3856 CPUState *cs; 3857 3858 CPU_FOREACH(cs) { 3859 PowerPCCPU *cpu = POWERPC_CPU(cs); 3860 3861 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 3862 return cpu; 3863 } 3864 } 3865 3866 return NULL; 3867 } 3868 3869 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3870 { 3871 MachineClass *mc = MACHINE_CLASS(oc); 3872 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3873 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3874 NMIClass *nc = NMI_CLASS(oc); 3875 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3876 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3877 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3878 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 3879 3880 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3881 3882 /* 3883 * We set up the default / latest behaviour here. The class_init 3884 * functions for the specific versioned machine types can override 3885 * these details for backwards compatibility 3886 */ 3887 mc->init = spapr_machine_init; 3888 mc->reset = spapr_machine_reset; 3889 mc->block_default_type = IF_SCSI; 3890 mc->max_cpus = 1024; 3891 mc->no_parallel = 1; 3892 mc->default_boot_order = ""; 3893 mc->default_ram_size = 512 * M_BYTE; 3894 mc->kvm_type = spapr_kvm_type; 3895 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 3896 mc->pci_allow_0_address = true; 3897 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3898 hc->pre_plug = spapr_machine_device_pre_plug; 3899 hc->plug = spapr_machine_device_plug; 3900 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 3901 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 3902 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3903 hc->unplug_request = spapr_machine_device_unplug_request; 3904 3905 smc->dr_lmb_enabled = true; 3906 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 3907 mc->has_hotpluggable_cpus = true; 3908 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 3909 fwc->get_dev_path = spapr_get_fw_dev_path; 3910 nc->nmi_monitor_handler = spapr_nmi; 3911 smc->phb_placement = spapr_phb_placement; 3912 vhc->hypercall = emulate_spapr_hypercall; 3913 vhc->hpt_mask = spapr_hpt_mask; 3914 vhc->map_hptes = spapr_map_hptes; 3915 vhc->unmap_hptes = spapr_unmap_hptes; 3916 vhc->store_hpte = spapr_store_hpte; 3917 vhc->get_patbe = spapr_get_patbe; 3918 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 3919 xic->ics_get = spapr_ics_get; 3920 xic->ics_resend = spapr_ics_resend; 3921 xic->icp_get = spapr_icp_get; 3922 ispc->print_info = spapr_pic_print_info; 3923 /* Force NUMA node memory size to be a multiple of 3924 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 3925 * in which LMBs are represented and hot-added 3926 */ 3927 mc->numa_mem_align_shift = 28; 3928 3929 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 3930 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 3931 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 3932 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 3933 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 3934 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 3935 spapr_caps_add_properties(smc, &error_abort); 3936 } 3937 3938 static const TypeInfo spapr_machine_info = { 3939 .name = TYPE_SPAPR_MACHINE, 3940 .parent = TYPE_MACHINE, 3941 .abstract = true, 3942 .instance_size = sizeof(sPAPRMachineState), 3943 .instance_init = spapr_instance_init, 3944 .instance_finalize = spapr_machine_finalizefn, 3945 .class_size = sizeof(sPAPRMachineClass), 3946 .class_init = spapr_machine_class_init, 3947 .interfaces = (InterfaceInfo[]) { 3948 { TYPE_FW_PATH_PROVIDER }, 3949 { TYPE_NMI }, 3950 { TYPE_HOTPLUG_HANDLER }, 3951 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 3952 { TYPE_XICS_FABRIC }, 3953 { TYPE_INTERRUPT_STATS_PROVIDER }, 3954 { } 3955 }, 3956 }; 3957 3958 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 3959 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 3960 void *data) \ 3961 { \ 3962 MachineClass *mc = MACHINE_CLASS(oc); \ 3963 spapr_machine_##suffix##_class_options(mc); \ 3964 if (latest) { \ 3965 mc->alias = "pseries"; \ 3966 mc->is_default = 1; \ 3967 } \ 3968 } \ 3969 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 3970 { \ 3971 MachineState *machine = MACHINE(obj); \ 3972 spapr_machine_##suffix##_instance_options(machine); \ 3973 } \ 3974 static const TypeInfo spapr_machine_##suffix##_info = { \ 3975 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 3976 .parent = TYPE_SPAPR_MACHINE, \ 3977 .class_init = spapr_machine_##suffix##_class_init, \ 3978 .instance_init = spapr_machine_##suffix##_instance_init, \ 3979 }; \ 3980 static void spapr_machine_register_##suffix(void) \ 3981 { \ 3982 type_register(&spapr_machine_##suffix##_info); \ 3983 } \ 3984 type_init(spapr_machine_register_##suffix) 3985 3986 /* 3987 * pseries-2.12 3988 */ 3989 static void spapr_machine_2_12_instance_options(MachineState *machine) 3990 { 3991 } 3992 3993 static void spapr_machine_2_12_class_options(MachineClass *mc) 3994 { 3995 /* Defaults for the latest behaviour inherited from the base class */ 3996 } 3997 3998 DEFINE_SPAPR_MACHINE(2_12, "2.12", true); 3999 4000 static void spapr_machine_2_12_sxxm_instance_options(MachineState *machine) 4001 { 4002 spapr_machine_2_12_instance_options(machine); 4003 } 4004 4005 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4006 { 4007 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4008 4009 spapr_machine_2_12_class_options(mc); 4010 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4011 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4012 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4013 } 4014 4015 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4016 4017 /* 4018 * pseries-2.11 4019 */ 4020 #define SPAPR_COMPAT_2_11 \ 4021 HW_COMPAT_2_11 4022 4023 static void spapr_machine_2_11_instance_options(MachineState *machine) 4024 { 4025 spapr_machine_2_12_instance_options(machine); 4026 } 4027 4028 static void spapr_machine_2_11_class_options(MachineClass *mc) 4029 { 4030 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4031 4032 spapr_machine_2_12_class_options(mc); 4033 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4034 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11); 4035 } 4036 4037 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4038 4039 /* 4040 * pseries-2.10 4041 */ 4042 #define SPAPR_COMPAT_2_10 \ 4043 HW_COMPAT_2_10 4044 4045 static void spapr_machine_2_10_instance_options(MachineState *machine) 4046 { 4047 spapr_machine_2_11_instance_options(machine); 4048 } 4049 4050 static void spapr_machine_2_10_class_options(MachineClass *mc) 4051 { 4052 spapr_machine_2_11_class_options(mc); 4053 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10); 4054 } 4055 4056 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4057 4058 /* 4059 * pseries-2.9 4060 */ 4061 #define SPAPR_COMPAT_2_9 \ 4062 HW_COMPAT_2_9 \ 4063 { \ 4064 .driver = TYPE_POWERPC_CPU, \ 4065 .property = "pre-2.10-migration", \ 4066 .value = "on", \ 4067 }, \ 4068 4069 static void spapr_machine_2_9_instance_options(MachineState *machine) 4070 { 4071 spapr_machine_2_10_instance_options(machine); 4072 } 4073 4074 static void spapr_machine_2_9_class_options(MachineClass *mc) 4075 { 4076 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4077 4078 spapr_machine_2_10_class_options(mc); 4079 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); 4080 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4081 smc->pre_2_10_has_unused_icps = true; 4082 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4083 } 4084 4085 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4086 4087 /* 4088 * pseries-2.8 4089 */ 4090 #define SPAPR_COMPAT_2_8 \ 4091 HW_COMPAT_2_8 \ 4092 { \ 4093 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4094 .property = "pcie-extended-configuration-space", \ 4095 .value = "off", \ 4096 }, 4097 4098 static void spapr_machine_2_8_instance_options(MachineState *machine) 4099 { 4100 spapr_machine_2_9_instance_options(machine); 4101 } 4102 4103 static void spapr_machine_2_8_class_options(MachineClass *mc) 4104 { 4105 spapr_machine_2_9_class_options(mc); 4106 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 4107 mc->numa_mem_align_shift = 23; 4108 } 4109 4110 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4111 4112 /* 4113 * pseries-2.7 4114 */ 4115 #define SPAPR_COMPAT_2_7 \ 4116 HW_COMPAT_2_7 \ 4117 { \ 4118 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4119 .property = "mem_win_size", \ 4120 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 4121 }, \ 4122 { \ 4123 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4124 .property = "mem64_win_size", \ 4125 .value = "0", \ 4126 }, \ 4127 { \ 4128 .driver = TYPE_POWERPC_CPU, \ 4129 .property = "pre-2.8-migration", \ 4130 .value = "on", \ 4131 }, \ 4132 { \ 4133 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4134 .property = "pre-2.8-migration", \ 4135 .value = "on", \ 4136 }, 4137 4138 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 4139 uint64_t *buid, hwaddr *pio, 4140 hwaddr *mmio32, hwaddr *mmio64, 4141 unsigned n_dma, uint32_t *liobns, Error **errp) 4142 { 4143 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4144 const uint64_t base_buid = 0x800000020000000ULL; 4145 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4146 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4147 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4148 const uint32_t max_index = 255; 4149 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4150 4151 uint64_t ram_top = MACHINE(spapr)->ram_size; 4152 hwaddr phb0_base, phb_base; 4153 int i; 4154 4155 /* Do we have hotpluggable memory? */ 4156 if (MACHINE(spapr)->maxram_size > ram_top) { 4157 /* Can't just use maxram_size, because there may be an 4158 * alignment gap between normal and hotpluggable memory 4159 * regions */ 4160 ram_top = spapr->hotplug_memory.base + 4161 memory_region_size(&spapr->hotplug_memory.mr); 4162 } 4163 4164 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4165 4166 if (index > max_index) { 4167 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4168 max_index); 4169 return; 4170 } 4171 4172 *buid = base_buid + index; 4173 for (i = 0; i < n_dma; ++i) { 4174 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4175 } 4176 4177 phb_base = phb0_base + index * phb_spacing; 4178 *pio = phb_base + pio_offset; 4179 *mmio32 = phb_base + mmio_offset; 4180 /* 4181 * We don't set the 64-bit MMIO window, relying on the PHB's 4182 * fallback behaviour of automatically splitting a large "32-bit" 4183 * window into contiguous 32-bit and 64-bit windows 4184 */ 4185 } 4186 4187 static void spapr_machine_2_7_instance_options(MachineState *machine) 4188 { 4189 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 4190 4191 spapr_machine_2_8_instance_options(machine); 4192 spapr->use_hotplug_event_source = false; 4193 } 4194 4195 static void spapr_machine_2_7_class_options(MachineClass *mc) 4196 { 4197 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4198 4199 spapr_machine_2_8_class_options(mc); 4200 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4201 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 4202 smc->phb_placement = phb_placement_2_7; 4203 } 4204 4205 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4206 4207 /* 4208 * pseries-2.6 4209 */ 4210 #define SPAPR_COMPAT_2_6 \ 4211 HW_COMPAT_2_6 \ 4212 { \ 4213 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 4214 .property = "ddw",\ 4215 .value = stringify(off),\ 4216 }, 4217 4218 static void spapr_machine_2_6_instance_options(MachineState *machine) 4219 { 4220 spapr_machine_2_7_instance_options(machine); 4221 } 4222 4223 static void spapr_machine_2_6_class_options(MachineClass *mc) 4224 { 4225 spapr_machine_2_7_class_options(mc); 4226 mc->has_hotpluggable_cpus = false; 4227 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 4228 } 4229 4230 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4231 4232 /* 4233 * pseries-2.5 4234 */ 4235 #define SPAPR_COMPAT_2_5 \ 4236 HW_COMPAT_2_5 \ 4237 { \ 4238 .driver = "spapr-vlan", \ 4239 .property = "use-rx-buffer-pools", \ 4240 .value = "off", \ 4241 }, 4242 4243 static void spapr_machine_2_5_instance_options(MachineState *machine) 4244 { 4245 spapr_machine_2_6_instance_options(machine); 4246 } 4247 4248 static void spapr_machine_2_5_class_options(MachineClass *mc) 4249 { 4250 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4251 4252 spapr_machine_2_6_class_options(mc); 4253 smc->use_ohci_by_default = true; 4254 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 4255 } 4256 4257 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4258 4259 /* 4260 * pseries-2.4 4261 */ 4262 #define SPAPR_COMPAT_2_4 \ 4263 HW_COMPAT_2_4 4264 4265 static void spapr_machine_2_4_instance_options(MachineState *machine) 4266 { 4267 spapr_machine_2_5_instance_options(machine); 4268 } 4269 4270 static void spapr_machine_2_4_class_options(MachineClass *mc) 4271 { 4272 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4273 4274 spapr_machine_2_5_class_options(mc); 4275 smc->dr_lmb_enabled = false; 4276 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 4277 } 4278 4279 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4280 4281 /* 4282 * pseries-2.3 4283 */ 4284 #define SPAPR_COMPAT_2_3 \ 4285 HW_COMPAT_2_3 \ 4286 {\ 4287 .driver = "spapr-pci-host-bridge",\ 4288 .property = "dynamic-reconfiguration",\ 4289 .value = "off",\ 4290 }, 4291 4292 static void spapr_machine_2_3_instance_options(MachineState *machine) 4293 { 4294 spapr_machine_2_4_instance_options(machine); 4295 } 4296 4297 static void spapr_machine_2_3_class_options(MachineClass *mc) 4298 { 4299 spapr_machine_2_4_class_options(mc); 4300 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 4301 } 4302 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4303 4304 /* 4305 * pseries-2.2 4306 */ 4307 4308 #define SPAPR_COMPAT_2_2 \ 4309 HW_COMPAT_2_2 \ 4310 {\ 4311 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 4312 .property = "mem_win_size",\ 4313 .value = "0x20000000",\ 4314 }, 4315 4316 static void spapr_machine_2_2_instance_options(MachineState *machine) 4317 { 4318 spapr_machine_2_3_instance_options(machine); 4319 machine->suppress_vmdesc = true; 4320 } 4321 4322 static void spapr_machine_2_2_class_options(MachineClass *mc) 4323 { 4324 spapr_machine_2_3_class_options(mc); 4325 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 4326 } 4327 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4328 4329 /* 4330 * pseries-2.1 4331 */ 4332 #define SPAPR_COMPAT_2_1 \ 4333 HW_COMPAT_2_1 4334 4335 static void spapr_machine_2_1_instance_options(MachineState *machine) 4336 { 4337 spapr_machine_2_2_instance_options(machine); 4338 } 4339 4340 static void spapr_machine_2_1_class_options(MachineClass *mc) 4341 { 4342 spapr_machine_2_2_class_options(mc); 4343 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 4344 } 4345 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4346 4347 static void spapr_machine_register_types(void) 4348 { 4349 type_register_static(&spapr_machine_info); 4350 } 4351 4352 type_init(spapr_machine_register_types) 4353