1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "sysemu/sysemu.h" 28 #include "sysemu/numa.h" 29 #include "hw/hw.h" 30 #include "hw/fw-path-provider.h" 31 #include "elf.h" 32 #include "net/net.h" 33 #include "sysemu/block-backend.h" 34 #include "sysemu/cpus.h" 35 #include "sysemu/kvm.h" 36 #include "kvm_ppc.h" 37 #include "mmu-hash64.h" 38 #include "qom/cpu.h" 39 40 #include "hw/boards.h" 41 #include "hw/ppc/ppc.h" 42 #include "hw/loader.h" 43 44 #include "hw/ppc/spapr.h" 45 #include "hw/ppc/spapr_vio.h" 46 #include "hw/pci-host/spapr.h" 47 #include "hw/ppc/xics.h" 48 #include "hw/pci/msi.h" 49 50 #include "hw/pci/pci.h" 51 #include "hw/scsi/scsi.h" 52 #include "hw/virtio/virtio-scsi.h" 53 54 #include "exec/address-spaces.h" 55 #include "hw/usb.h" 56 #include "qemu/config-file.h" 57 #include "qemu/error-report.h" 58 #include "trace.h" 59 #include "hw/nmi.h" 60 61 #include "hw/compat.h" 62 63 #include <libfdt.h> 64 65 /* SLOF memory layout: 66 * 67 * SLOF raw image loaded at 0, copies its romfs right below the flat 68 * device-tree, then position SLOF itself 31M below that 69 * 70 * So we set FW_OVERHEAD to 40MB which should account for all of that 71 * and more 72 * 73 * We load our kernel at 4M, leaving space for SLOF initial image 74 */ 75 #define FDT_MAX_SIZE 0x40000 76 #define RTAS_MAX_SIZE 0x10000 77 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 78 #define FW_MAX_SIZE 0x400000 79 #define FW_FILE_NAME "slof.bin" 80 #define FW_OVERHEAD 0x2800000 81 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 82 83 #define MIN_RMA_SLOF 128UL 84 85 #define TIMEBASE_FREQ 512000000ULL 86 87 #define MAX_CPUS 255 88 89 #define PHANDLE_XICP 0x00001111 90 91 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 92 93 static XICSState *try_create_xics(const char *type, int nr_servers, 94 int nr_irqs, Error **errp) 95 { 96 Error *err = NULL; 97 DeviceState *dev; 98 99 dev = qdev_create(NULL, type); 100 qdev_prop_set_uint32(dev, "nr_servers", nr_servers); 101 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); 102 object_property_set_bool(OBJECT(dev), true, "realized", &err); 103 if (err) { 104 error_propagate(errp, err); 105 object_unparent(OBJECT(dev)); 106 return NULL; 107 } 108 return XICS_COMMON(dev); 109 } 110 111 static XICSState *xics_system_init(MachineState *machine, 112 int nr_servers, int nr_irqs) 113 { 114 XICSState *icp = NULL; 115 116 if (kvm_enabled()) { 117 Error *err = NULL; 118 119 if (machine_kernel_irqchip_allowed(machine)) { 120 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs, &err); 121 } 122 if (machine_kernel_irqchip_required(machine) && !icp) { 123 error_report("kernel_irqchip requested but unavailable: %s", 124 error_get_pretty(err)); 125 } 126 } 127 128 if (!icp) { 129 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs, &error_abort); 130 } 131 132 return icp; 133 } 134 135 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 136 int smt_threads) 137 { 138 int i, ret = 0; 139 uint32_t servers_prop[smt_threads]; 140 uint32_t gservers_prop[smt_threads * 2]; 141 int index = ppc_get_vcpu_dt_id(cpu); 142 143 if (cpu->cpu_version) { 144 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version); 145 if (ret < 0) { 146 return ret; 147 } 148 } 149 150 /* Build interrupt servers and gservers properties */ 151 for (i = 0; i < smt_threads; i++) { 152 servers_prop[i] = cpu_to_be32(index + i); 153 /* Hack, direct the group queues back to cpu 0 */ 154 gservers_prop[i*2] = cpu_to_be32(index + i); 155 gservers_prop[i*2 + 1] = 0; 156 } 157 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 158 servers_prop, sizeof(servers_prop)); 159 if (ret < 0) { 160 return ret; 161 } 162 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 163 gservers_prop, sizeof(gservers_prop)); 164 165 return ret; 166 } 167 168 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 169 { 170 int ret = 0, offset, cpus_offset; 171 CPUState *cs; 172 char cpu_model[32]; 173 int smt = kvmppc_smt_threads(); 174 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 175 176 CPU_FOREACH(cs) { 177 PowerPCCPU *cpu = POWERPC_CPU(cs); 178 DeviceClass *dc = DEVICE_GET_CLASS(cs); 179 int index = ppc_get_vcpu_dt_id(cpu); 180 uint32_t associativity[] = {cpu_to_be32(0x5), 181 cpu_to_be32(0x0), 182 cpu_to_be32(0x0), 183 cpu_to_be32(0x0), 184 cpu_to_be32(cs->numa_node), 185 cpu_to_be32(index)}; 186 187 if ((index % smt) != 0) { 188 continue; 189 } 190 191 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 192 193 cpus_offset = fdt_path_offset(fdt, "/cpus"); 194 if (cpus_offset < 0) { 195 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 196 "cpus"); 197 if (cpus_offset < 0) { 198 return cpus_offset; 199 } 200 } 201 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 202 if (offset < 0) { 203 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 204 if (offset < 0) { 205 return offset; 206 } 207 } 208 209 if (nb_numa_nodes > 1) { 210 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 211 sizeof(associativity)); 212 if (ret < 0) { 213 return ret; 214 } 215 } 216 217 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 218 pft_size_prop, sizeof(pft_size_prop)); 219 if (ret < 0) { 220 return ret; 221 } 222 223 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 224 ppc_get_compat_smt_threads(cpu)); 225 if (ret < 0) { 226 return ret; 227 } 228 } 229 return ret; 230 } 231 232 233 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, 234 size_t maxsize) 235 { 236 size_t maxcells = maxsize / sizeof(uint32_t); 237 int i, j, count; 238 uint32_t *p = prop; 239 240 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 241 struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; 242 243 if (!sps->page_shift) { 244 break; 245 } 246 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { 247 if (sps->enc[count].page_shift == 0) { 248 break; 249 } 250 } 251 if ((p - prop) >= (maxcells - 3 - count * 2)) { 252 break; 253 } 254 *(p++) = cpu_to_be32(sps->page_shift); 255 *(p++) = cpu_to_be32(sps->slb_enc); 256 *(p++) = cpu_to_be32(count); 257 for (j = 0; j < count; j++) { 258 *(p++) = cpu_to_be32(sps->enc[j].page_shift); 259 *(p++) = cpu_to_be32(sps->enc[j].pte_enc); 260 } 261 } 262 263 return (p - prop) * sizeof(uint32_t); 264 } 265 266 static hwaddr spapr_node0_size(void) 267 { 268 MachineState *machine = MACHINE(qdev_get_machine()); 269 270 if (nb_numa_nodes) { 271 int i; 272 for (i = 0; i < nb_numa_nodes; ++i) { 273 if (numa_info[i].node_mem) { 274 return MIN(pow2floor(numa_info[i].node_mem), 275 machine->ram_size); 276 } 277 } 278 } 279 return machine->ram_size; 280 } 281 282 #define _FDT(exp) \ 283 do { \ 284 int ret = (exp); \ 285 if (ret < 0) { \ 286 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ 287 #exp, fdt_strerror(ret)); \ 288 exit(1); \ 289 } \ 290 } while (0) 291 292 static void add_str(GString *s, const gchar *s1) 293 { 294 g_string_append_len(s, s1, strlen(s1) + 1); 295 } 296 297 static void *spapr_create_fdt_skel(hwaddr initrd_base, 298 hwaddr initrd_size, 299 hwaddr kernel_size, 300 bool little_endian, 301 const char *kernel_cmdline, 302 uint32_t epow_irq) 303 { 304 void *fdt; 305 CPUState *cs; 306 uint32_t start_prop = cpu_to_be32(initrd_base); 307 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); 308 GString *hypertas = g_string_sized_new(256); 309 GString *qemu_hypertas = g_string_sized_new(256); 310 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; 311 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)}; 312 int smt = kvmppc_smt_threads(); 313 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; 314 QemuOpts *opts = qemu_opts_find(qemu_find_opts("smp-opts"), NULL); 315 unsigned sockets = opts ? qemu_opt_get_number(opts, "sockets", 0) : 0; 316 uint32_t cpus_per_socket = sockets ? (smp_cpus / sockets) : 1; 317 char *buf; 318 319 add_str(hypertas, "hcall-pft"); 320 add_str(hypertas, "hcall-term"); 321 add_str(hypertas, "hcall-dabr"); 322 add_str(hypertas, "hcall-interrupt"); 323 add_str(hypertas, "hcall-tce"); 324 add_str(hypertas, "hcall-vio"); 325 add_str(hypertas, "hcall-splpar"); 326 add_str(hypertas, "hcall-bulk"); 327 add_str(hypertas, "hcall-set-mode"); 328 add_str(qemu_hypertas, "hcall-memop1"); 329 330 fdt = g_malloc0(FDT_MAX_SIZE); 331 _FDT((fdt_create(fdt, FDT_MAX_SIZE))); 332 333 if (kernel_size) { 334 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); 335 } 336 if (initrd_size) { 337 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); 338 } 339 _FDT((fdt_finish_reservemap(fdt))); 340 341 /* Root node */ 342 _FDT((fdt_begin_node(fdt, ""))); 343 _FDT((fdt_property_string(fdt, "device_type", "chrp"))); 344 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); 345 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); 346 347 /* 348 * Add info to guest to indentify which host is it being run on 349 * and what is the uuid of the guest 350 */ 351 if (kvmppc_get_host_model(&buf)) { 352 _FDT((fdt_property_string(fdt, "host-model", buf))); 353 g_free(buf); 354 } 355 if (kvmppc_get_host_serial(&buf)) { 356 _FDT((fdt_property_string(fdt, "host-serial", buf))); 357 g_free(buf); 358 } 359 360 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1], 361 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4], 362 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7], 363 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10], 364 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13], 365 qemu_uuid[14], qemu_uuid[15]); 366 367 _FDT((fdt_property_string(fdt, "vm,uuid", buf))); 368 g_free(buf); 369 370 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); 371 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); 372 373 /* /chosen */ 374 _FDT((fdt_begin_node(fdt, "chosen"))); 375 376 /* Set Form1_affinity */ 377 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); 378 379 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); 380 _FDT((fdt_property(fdt, "linux,initrd-start", 381 &start_prop, sizeof(start_prop)))); 382 _FDT((fdt_property(fdt, "linux,initrd-end", 383 &end_prop, sizeof(end_prop)))); 384 if (kernel_size) { 385 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 386 cpu_to_be64(kernel_size) }; 387 388 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); 389 if (little_endian) { 390 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); 391 } 392 } 393 if (boot_menu) { 394 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu))); 395 } 396 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); 397 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); 398 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); 399 400 _FDT((fdt_end_node(fdt))); 401 402 /* cpus */ 403 _FDT((fdt_begin_node(fdt, "cpus"))); 404 405 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 406 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 407 408 CPU_FOREACH(cs) { 409 PowerPCCPU *cpu = POWERPC_CPU(cs); 410 CPUPPCState *env = &cpu->env; 411 DeviceClass *dc = DEVICE_GET_CLASS(cs); 412 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 413 int index = ppc_get_vcpu_dt_id(cpu); 414 char *nodename; 415 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 416 0xffffffff, 0xffffffff}; 417 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; 418 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 419 uint32_t page_sizes_prop[64]; 420 size_t page_sizes_prop_size; 421 422 if ((index % smt) != 0) { 423 continue; 424 } 425 426 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 427 428 _FDT((fdt_begin_node(fdt, nodename))); 429 430 g_free(nodename); 431 432 _FDT((fdt_property_cell(fdt, "reg", index))); 433 _FDT((fdt_property_string(fdt, "device_type", "cpu"))); 434 435 _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR]))); 436 _FDT((fdt_property_cell(fdt, "d-cache-block-size", 437 env->dcache_line_size))); 438 _FDT((fdt_property_cell(fdt, "d-cache-line-size", 439 env->dcache_line_size))); 440 _FDT((fdt_property_cell(fdt, "i-cache-block-size", 441 env->icache_line_size))); 442 _FDT((fdt_property_cell(fdt, "i-cache-line-size", 443 env->icache_line_size))); 444 445 if (pcc->l1_dcache_size) { 446 _FDT((fdt_property_cell(fdt, "d-cache-size", pcc->l1_dcache_size))); 447 } else { 448 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); 449 } 450 if (pcc->l1_icache_size) { 451 _FDT((fdt_property_cell(fdt, "i-cache-size", pcc->l1_icache_size))); 452 } else { 453 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); 454 } 455 456 _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq))); 457 _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq))); 458 _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr))); 459 _FDT((fdt_property_string(fdt, "status", "okay"))); 460 _FDT((fdt_property(fdt, "64-bit", NULL, 0))); 461 462 if (env->spr_cb[SPR_PURR].oea_read) { 463 _FDT((fdt_property(fdt, "ibm,purr", NULL, 0))); 464 } 465 466 if (env->mmu_model & POWERPC_MMU_1TSEG) { 467 _FDT((fdt_property(fdt, "ibm,processor-segment-sizes", 468 segs, sizeof(segs)))); 469 } 470 471 /* Advertise VMX/VSX (vector extensions) if available 472 * 0 / no property == no vector extensions 473 * 1 == VMX / Altivec available 474 * 2 == VSX available */ 475 if (env->insns_flags & PPC_ALTIVEC) { 476 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 477 478 _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx))); 479 } 480 481 /* Advertise DFP (Decimal Floating Point) if available 482 * 0 / no property == no DFP 483 * 1 == DFP available */ 484 if (env->insns_flags2 & PPC2_DFP) { 485 _FDT((fdt_property_cell(fdt, "ibm,dfp", 1))); 486 } 487 488 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, 489 sizeof(page_sizes_prop)); 490 if (page_sizes_prop_size) { 491 _FDT((fdt_property(fdt, "ibm,segment-page-sizes", 492 page_sizes_prop, page_sizes_prop_size))); 493 } 494 495 _FDT((fdt_property_cell(fdt, "ibm,chip-id", 496 cs->cpu_index / cpus_per_socket))); 497 498 _FDT((fdt_end_node(fdt))); 499 } 500 501 _FDT((fdt_end_node(fdt))); 502 503 /* RTAS */ 504 _FDT((fdt_begin_node(fdt, "rtas"))); 505 506 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 507 add_str(hypertas, "hcall-multi-tce"); 508 } 509 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str, 510 hypertas->len))); 511 g_string_free(hypertas, TRUE); 512 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str, 513 qemu_hypertas->len))); 514 g_string_free(qemu_hypertas, TRUE); 515 516 _FDT((fdt_property(fdt, "ibm,associativity-reference-points", 517 refpoints, sizeof(refpoints)))); 518 519 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); 520 _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate", 521 RTAS_EVENT_SCAN_RATE))); 522 523 /* 524 * According to PAPR, rtas ibm,os-term does not guarantee a return 525 * back to the guest cpu. 526 * 527 * While an additional ibm,extended-os-term property indicates that 528 * rtas call return will always occur. Set this property. 529 */ 530 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0))); 531 532 _FDT((fdt_end_node(fdt))); 533 534 /* interrupt controller */ 535 _FDT((fdt_begin_node(fdt, "interrupt-controller"))); 536 537 _FDT((fdt_property_string(fdt, "device_type", 538 "PowerPC-External-Interrupt-Presentation"))); 539 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); 540 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 541 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", 542 interrupt_server_ranges_prop, 543 sizeof(interrupt_server_ranges_prop)))); 544 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); 545 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); 546 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); 547 548 _FDT((fdt_end_node(fdt))); 549 550 /* vdevice */ 551 _FDT((fdt_begin_node(fdt, "vdevice"))); 552 553 _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); 554 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); 555 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 556 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 557 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); 558 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 559 560 _FDT((fdt_end_node(fdt))); 561 562 /* event-sources */ 563 spapr_events_fdt_skel(fdt, epow_irq); 564 565 /* /hypervisor node */ 566 if (kvm_enabled()) { 567 uint8_t hypercall[16]; 568 569 /* indicate KVM hypercall interface */ 570 _FDT((fdt_begin_node(fdt, "hypervisor"))); 571 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm"))); 572 if (kvmppc_has_cap_fixup_hcalls()) { 573 /* 574 * Older KVM versions with older guest kernels were broken with the 575 * magic page, don't allow the guest to map it. 576 */ 577 kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 578 sizeof(hypercall)); 579 _FDT((fdt_property(fdt, "hcall-instructions", hypercall, 580 sizeof(hypercall)))); 581 } 582 _FDT((fdt_end_node(fdt))); 583 } 584 585 _FDT((fdt_end_node(fdt))); /* close root node */ 586 _FDT((fdt_finish(fdt))); 587 588 return fdt; 589 } 590 591 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 592 target_ulong addr, target_ulong size) 593 { 594 void *fdt, *fdt_skel; 595 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 596 597 size -= sizeof(hdr); 598 599 /* Create sceleton */ 600 fdt_skel = g_malloc0(size); 601 _FDT((fdt_create(fdt_skel, size))); 602 _FDT((fdt_begin_node(fdt_skel, ""))); 603 _FDT((fdt_end_node(fdt_skel))); 604 _FDT((fdt_finish(fdt_skel))); 605 fdt = g_malloc0(size); 606 _FDT((fdt_open_into(fdt_skel, fdt, size))); 607 g_free(fdt_skel); 608 609 /* Fix skeleton up */ 610 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 611 612 /* Pack resulting tree */ 613 _FDT((fdt_pack(fdt))); 614 615 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 616 trace_spapr_cas_failed(size); 617 return -1; 618 } 619 620 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 621 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 622 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 623 g_free(fdt); 624 625 return 0; 626 } 627 628 static void spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 629 hwaddr size) 630 { 631 uint32_t associativity[] = { 632 cpu_to_be32(0x4), /* length */ 633 cpu_to_be32(0x0), cpu_to_be32(0x0), 634 cpu_to_be32(0x0), cpu_to_be32(nodeid) 635 }; 636 char mem_name[32]; 637 uint64_t mem_reg_property[2]; 638 int off; 639 640 mem_reg_property[0] = cpu_to_be64(start); 641 mem_reg_property[1] = cpu_to_be64(size); 642 643 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 644 off = fdt_add_subnode(fdt, 0, mem_name); 645 _FDT(off); 646 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 647 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 648 sizeof(mem_reg_property)))); 649 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 650 sizeof(associativity)))); 651 } 652 653 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 654 { 655 MachineState *machine = MACHINE(spapr); 656 hwaddr mem_start, node_size; 657 int i, nb_nodes = nb_numa_nodes; 658 NodeInfo *nodes = numa_info; 659 NodeInfo ramnode; 660 661 /* No NUMA nodes, assume there is just one node with whole RAM */ 662 if (!nb_numa_nodes) { 663 nb_nodes = 1; 664 ramnode.node_mem = machine->ram_size; 665 nodes = &ramnode; 666 } 667 668 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 669 if (!nodes[i].node_mem) { 670 continue; 671 } 672 if (mem_start >= machine->ram_size) { 673 node_size = 0; 674 } else { 675 node_size = nodes[i].node_mem; 676 if (node_size > machine->ram_size - mem_start) { 677 node_size = machine->ram_size - mem_start; 678 } 679 } 680 if (!mem_start) { 681 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 682 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 683 mem_start += spapr->rma_size; 684 node_size -= spapr->rma_size; 685 } 686 for ( ; node_size; ) { 687 hwaddr sizetmp = pow2floor(node_size); 688 689 /* mem_start != 0 here */ 690 if (ctzl(mem_start) < ctzl(sizetmp)) { 691 sizetmp = 1ULL << ctzl(mem_start); 692 } 693 694 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 695 node_size -= sizetmp; 696 mem_start += sizetmp; 697 } 698 } 699 700 return 0; 701 } 702 703 static void spapr_finalize_fdt(sPAPRMachineState *spapr, 704 hwaddr fdt_addr, 705 hwaddr rtas_addr, 706 hwaddr rtas_size) 707 { 708 MachineState *machine = MACHINE(qdev_get_machine()); 709 const char *boot_device = machine->boot_order; 710 int ret, i; 711 size_t cb = 0; 712 char *bootlist; 713 void *fdt; 714 sPAPRPHBState *phb; 715 716 fdt = g_malloc(FDT_MAX_SIZE); 717 718 /* open out the base tree into a temp buffer for the final tweaks */ 719 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); 720 721 ret = spapr_populate_memory(spapr, fdt); 722 if (ret < 0) { 723 fprintf(stderr, "couldn't setup memory nodes in fdt\n"); 724 exit(1); 725 } 726 727 ret = spapr_populate_vdevice(spapr->vio_bus, fdt); 728 if (ret < 0) { 729 fprintf(stderr, "couldn't setup vio devices in fdt\n"); 730 exit(1); 731 } 732 733 QLIST_FOREACH(phb, &spapr->phbs, list) { 734 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 735 } 736 737 if (ret < 0) { 738 fprintf(stderr, "couldn't setup PCI devices in fdt\n"); 739 exit(1); 740 } 741 742 /* RTAS */ 743 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); 744 if (ret < 0) { 745 fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); 746 } 747 748 /* Advertise NUMA via ibm,associativity */ 749 ret = spapr_fixup_cpu_dt(fdt, spapr); 750 if (ret < 0) { 751 fprintf(stderr, "Couldn't finalize CPU device tree properties\n"); 752 } 753 754 bootlist = get_boot_devices_list(&cb, true); 755 if (cb && bootlist) { 756 int offset = fdt_path_offset(fdt, "/chosen"); 757 if (offset < 0) { 758 exit(1); 759 } 760 for (i = 0; i < cb; i++) { 761 if (bootlist[i] == '\n') { 762 bootlist[i] = ' '; 763 } 764 765 } 766 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist); 767 } 768 769 if (boot_device && strlen(boot_device)) { 770 int offset = fdt_path_offset(fdt, "/chosen"); 771 772 if (offset < 0) { 773 exit(1); 774 } 775 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device); 776 } 777 778 if (!spapr->has_graphics) { 779 spapr_populate_chosen_stdout(fdt, spapr->vio_bus); 780 } 781 782 _FDT((fdt_pack(fdt))); 783 784 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 785 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 786 fdt_totalsize(fdt), FDT_MAX_SIZE); 787 exit(1); 788 } 789 790 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 791 792 g_free(bootlist); 793 g_free(fdt); 794 } 795 796 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 797 { 798 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 799 } 800 801 static void emulate_spapr_hypercall(PowerPCCPU *cpu) 802 { 803 CPUPPCState *env = &cpu->env; 804 805 if (msr_pr) { 806 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 807 env->gpr[3] = H_PRIVILEGE; 808 } else { 809 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 810 } 811 } 812 813 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 814 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 815 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 816 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 817 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 818 819 static void spapr_reset_htab(sPAPRMachineState *spapr) 820 { 821 long shift; 822 int index; 823 824 /* allocate hash page table. For now we always make this 16mb, 825 * later we should probably make it scale to the size of guest 826 * RAM */ 827 828 shift = kvmppc_reset_htab(spapr->htab_shift); 829 830 if (shift > 0) { 831 /* Kernel handles htab, we don't need to allocate one */ 832 spapr->htab_shift = shift; 833 kvmppc_kern_htab = true; 834 835 /* Tell readers to update their file descriptor */ 836 if (spapr->htab_fd >= 0) { 837 spapr->htab_fd_stale = true; 838 } 839 } else { 840 if (!spapr->htab) { 841 /* Allocate an htab if we don't yet have one */ 842 spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); 843 } 844 845 /* And clear it */ 846 memset(spapr->htab, 0, HTAB_SIZE(spapr)); 847 848 for (index = 0; index < HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; index++) { 849 DIRTY_HPTE(HPTE(spapr->htab, index)); 850 } 851 } 852 853 /* Update the RMA size if necessary */ 854 if (spapr->vrma_adjust) { 855 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 856 spapr->htab_shift); 857 } 858 } 859 860 static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 861 { 862 bool matched = false; 863 864 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 865 matched = true; 866 } 867 868 if (!matched) { 869 error_report("Device %s is not supported by this machine yet.", 870 qdev_fw_name(DEVICE(sbdev))); 871 exit(1); 872 } 873 874 return 0; 875 } 876 877 /* 878 * A guest reset will cause spapr->htab_fd to become stale if being used. 879 * Reopen the file descriptor to make sure the whole HTAB is properly read. 880 */ 881 static int spapr_check_htab_fd(sPAPRMachineState *spapr) 882 { 883 int rc = 0; 884 885 if (spapr->htab_fd_stale) { 886 close(spapr->htab_fd); 887 spapr->htab_fd = kvmppc_get_htab_fd(false); 888 if (spapr->htab_fd < 0) { 889 error_report("Unable to open fd for reading hash table from KVM: " 890 "%s", strerror(errno)); 891 rc = -1; 892 } 893 spapr->htab_fd_stale = false; 894 } 895 896 return rc; 897 } 898 899 static void ppc_spapr_reset(void) 900 { 901 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 902 PowerPCCPU *first_ppc_cpu; 903 uint32_t rtas_limit; 904 905 /* Check for unknown sysbus devices */ 906 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 907 908 /* Reset the hash table & recalc the RMA */ 909 spapr_reset_htab(spapr); 910 911 qemu_devices_reset(); 912 913 /* 914 * We place the device tree and RTAS just below either the top of the RMA, 915 * or just below 2GB, whichever is lowere, so that it can be 916 * processed with 32-bit real mode code if necessary 917 */ 918 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 919 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; 920 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; 921 922 /* Load the fdt */ 923 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, 924 spapr->rtas_size); 925 926 /* Copy RTAS over */ 927 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob, 928 spapr->rtas_size); 929 930 /* Set up the entry state */ 931 first_ppc_cpu = POWERPC_CPU(first_cpu); 932 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; 933 first_ppc_cpu->env.gpr[5] = 0; 934 first_cpu->halted = 0; 935 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 936 937 } 938 939 static void spapr_cpu_reset(void *opaque) 940 { 941 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 942 PowerPCCPU *cpu = opaque; 943 CPUState *cs = CPU(cpu); 944 CPUPPCState *env = &cpu->env; 945 946 cpu_reset(cs); 947 948 /* All CPUs start halted. CPU0 is unhalted from the machine level 949 * reset code and the rest are explicitly started up by the guest 950 * using an RTAS call */ 951 cs->halted = 1; 952 953 env->spr[SPR_HIOR] = 0; 954 955 env->external_htab = (uint8_t *)spapr->htab; 956 if (kvm_enabled() && !env->external_htab) { 957 /* 958 * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte* 959 * functions do the right thing. 960 */ 961 env->external_htab = (void *)1; 962 } 963 env->htab_base = -1; 964 /* 965 * htab_mask is the mask used to normalize hash value to PTEG index. 966 * htab_shift is log2 of hash table size. 967 * We have 8 hpte per group, and each hpte is 16 bytes. 968 * ie have 128 bytes per hpte entry. 969 */ 970 env->htab_mask = (1ULL << (spapr->htab_shift - 7)) - 1; 971 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | 972 (spapr->htab_shift - 18); 973 } 974 975 static void spapr_create_nvram(sPAPRMachineState *spapr) 976 { 977 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 978 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 979 980 if (dinfo) { 981 qdev_prop_set_drive_nofail(dev, "drive", blk_by_legacy_dinfo(dinfo)); 982 } 983 984 qdev_init_nofail(dev); 985 986 spapr->nvram = (struct sPAPRNVRAM *)dev; 987 } 988 989 static void spapr_rtc_create(sPAPRMachineState *spapr) 990 { 991 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC); 992 993 qdev_init_nofail(dev); 994 spapr->rtc = dev; 995 996 object_property_add_alias(qdev_get_machine(), "rtc-time", 997 OBJECT(spapr->rtc), "date", NULL); 998 } 999 1000 /* Returns whether we want to use VGA or not */ 1001 static int spapr_vga_init(PCIBus *pci_bus) 1002 { 1003 switch (vga_interface_type) { 1004 case VGA_NONE: 1005 return false; 1006 case VGA_DEVICE: 1007 return true; 1008 case VGA_STD: 1009 return pci_vga_init(pci_bus) != NULL; 1010 default: 1011 fprintf(stderr, "This vga model is not supported," 1012 "currently it only supports -vga std\n"); 1013 exit(0); 1014 } 1015 } 1016 1017 static int spapr_post_load(void *opaque, int version_id) 1018 { 1019 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1020 int err = 0; 1021 1022 /* In earlier versions, there was no separate qdev for the PAPR 1023 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1024 * So when migrating from those versions, poke the incoming offset 1025 * value into the RTC device */ 1026 if (version_id < 3) { 1027 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset); 1028 } 1029 1030 return err; 1031 } 1032 1033 static bool version_before_3(void *opaque, int version_id) 1034 { 1035 return version_id < 3; 1036 } 1037 1038 static const VMStateDescription vmstate_spapr = { 1039 .name = "spapr", 1040 .version_id = 3, 1041 .minimum_version_id = 1, 1042 .post_load = spapr_post_load, 1043 .fields = (VMStateField[]) { 1044 /* used to be @next_irq */ 1045 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1046 1047 /* RTC offset */ 1048 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1049 1050 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1051 VMSTATE_END_OF_LIST() 1052 }, 1053 }; 1054 1055 static int htab_save_setup(QEMUFile *f, void *opaque) 1056 { 1057 sPAPRMachineState *spapr = opaque; 1058 1059 /* "Iteration" header */ 1060 qemu_put_be32(f, spapr->htab_shift); 1061 1062 if (spapr->htab) { 1063 spapr->htab_save_index = 0; 1064 spapr->htab_first_pass = true; 1065 } else { 1066 assert(kvm_enabled()); 1067 1068 spapr->htab_fd = kvmppc_get_htab_fd(false); 1069 spapr->htab_fd_stale = false; 1070 if (spapr->htab_fd < 0) { 1071 fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n", 1072 strerror(errno)); 1073 return -1; 1074 } 1075 } 1076 1077 1078 return 0; 1079 } 1080 1081 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1082 int64_t max_ns) 1083 { 1084 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1085 int index = spapr->htab_save_index; 1086 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1087 1088 assert(spapr->htab_first_pass); 1089 1090 do { 1091 int chunkstart; 1092 1093 /* Consume invalid HPTEs */ 1094 while ((index < htabslots) 1095 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1096 index++; 1097 CLEAN_HPTE(HPTE(spapr->htab, index)); 1098 } 1099 1100 /* Consume valid HPTEs */ 1101 chunkstart = index; 1102 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1103 && HPTE_VALID(HPTE(spapr->htab, index))) { 1104 index++; 1105 CLEAN_HPTE(HPTE(spapr->htab, index)); 1106 } 1107 1108 if (index > chunkstart) { 1109 int n_valid = index - chunkstart; 1110 1111 qemu_put_be32(f, chunkstart); 1112 qemu_put_be16(f, n_valid); 1113 qemu_put_be16(f, 0); 1114 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1115 HASH_PTE_SIZE_64 * n_valid); 1116 1117 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1118 break; 1119 } 1120 } 1121 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1122 1123 if (index >= htabslots) { 1124 assert(index == htabslots); 1125 index = 0; 1126 spapr->htab_first_pass = false; 1127 } 1128 spapr->htab_save_index = index; 1129 } 1130 1131 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1132 int64_t max_ns) 1133 { 1134 bool final = max_ns < 0; 1135 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1136 int examined = 0, sent = 0; 1137 int index = spapr->htab_save_index; 1138 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1139 1140 assert(!spapr->htab_first_pass); 1141 1142 do { 1143 int chunkstart, invalidstart; 1144 1145 /* Consume non-dirty HPTEs */ 1146 while ((index < htabslots) 1147 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1148 index++; 1149 examined++; 1150 } 1151 1152 chunkstart = index; 1153 /* Consume valid dirty HPTEs */ 1154 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1155 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1156 && HPTE_VALID(HPTE(spapr->htab, index))) { 1157 CLEAN_HPTE(HPTE(spapr->htab, index)); 1158 index++; 1159 examined++; 1160 } 1161 1162 invalidstart = index; 1163 /* Consume invalid dirty HPTEs */ 1164 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1165 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1166 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1167 CLEAN_HPTE(HPTE(spapr->htab, index)); 1168 index++; 1169 examined++; 1170 } 1171 1172 if (index > chunkstart) { 1173 int n_valid = invalidstart - chunkstart; 1174 int n_invalid = index - invalidstart; 1175 1176 qemu_put_be32(f, chunkstart); 1177 qemu_put_be16(f, n_valid); 1178 qemu_put_be16(f, n_invalid); 1179 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1180 HASH_PTE_SIZE_64 * n_valid); 1181 sent += index - chunkstart; 1182 1183 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1184 break; 1185 } 1186 } 1187 1188 if (examined >= htabslots) { 1189 break; 1190 } 1191 1192 if (index >= htabslots) { 1193 assert(index == htabslots); 1194 index = 0; 1195 } 1196 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1197 1198 if (index >= htabslots) { 1199 assert(index == htabslots); 1200 index = 0; 1201 } 1202 1203 spapr->htab_save_index = index; 1204 1205 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1206 } 1207 1208 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1209 #define MAX_KVM_BUF_SIZE 2048 1210 1211 static int htab_save_iterate(QEMUFile *f, void *opaque) 1212 { 1213 sPAPRMachineState *spapr = opaque; 1214 int rc = 0; 1215 1216 /* Iteration header */ 1217 qemu_put_be32(f, 0); 1218 1219 if (!spapr->htab) { 1220 assert(kvm_enabled()); 1221 1222 rc = spapr_check_htab_fd(spapr); 1223 if (rc < 0) { 1224 return rc; 1225 } 1226 1227 rc = kvmppc_save_htab(f, spapr->htab_fd, 1228 MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1229 if (rc < 0) { 1230 return rc; 1231 } 1232 } else if (spapr->htab_first_pass) { 1233 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1234 } else { 1235 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1236 } 1237 1238 /* End marker */ 1239 qemu_put_be32(f, 0); 1240 qemu_put_be16(f, 0); 1241 qemu_put_be16(f, 0); 1242 1243 return rc; 1244 } 1245 1246 static int htab_save_complete(QEMUFile *f, void *opaque) 1247 { 1248 sPAPRMachineState *spapr = opaque; 1249 1250 /* Iteration header */ 1251 qemu_put_be32(f, 0); 1252 1253 if (!spapr->htab) { 1254 int rc; 1255 1256 assert(kvm_enabled()); 1257 1258 rc = spapr_check_htab_fd(spapr); 1259 if (rc < 0) { 1260 return rc; 1261 } 1262 1263 rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1); 1264 if (rc < 0) { 1265 return rc; 1266 } 1267 close(spapr->htab_fd); 1268 spapr->htab_fd = -1; 1269 } else { 1270 htab_save_later_pass(f, spapr, -1); 1271 } 1272 1273 /* End marker */ 1274 qemu_put_be32(f, 0); 1275 qemu_put_be16(f, 0); 1276 qemu_put_be16(f, 0); 1277 1278 return 0; 1279 } 1280 1281 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1282 { 1283 sPAPRMachineState *spapr = opaque; 1284 uint32_t section_hdr; 1285 int fd = -1; 1286 1287 if (version_id < 1 || version_id > 1) { 1288 fprintf(stderr, "htab_load() bad version\n"); 1289 return -EINVAL; 1290 } 1291 1292 section_hdr = qemu_get_be32(f); 1293 1294 if (section_hdr) { 1295 /* First section, just the hash shift */ 1296 if (spapr->htab_shift != section_hdr) { 1297 return -EINVAL; 1298 } 1299 return 0; 1300 } 1301 1302 if (!spapr->htab) { 1303 assert(kvm_enabled()); 1304 1305 fd = kvmppc_get_htab_fd(true); 1306 if (fd < 0) { 1307 fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n", 1308 strerror(errno)); 1309 } 1310 } 1311 1312 while (true) { 1313 uint32_t index; 1314 uint16_t n_valid, n_invalid; 1315 1316 index = qemu_get_be32(f); 1317 n_valid = qemu_get_be16(f); 1318 n_invalid = qemu_get_be16(f); 1319 1320 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1321 /* End of Stream */ 1322 break; 1323 } 1324 1325 if ((index + n_valid + n_invalid) > 1326 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1327 /* Bad index in stream */ 1328 fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) " 1329 "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid, 1330 spapr->htab_shift); 1331 return -EINVAL; 1332 } 1333 1334 if (spapr->htab) { 1335 if (n_valid) { 1336 qemu_get_buffer(f, HPTE(spapr->htab, index), 1337 HASH_PTE_SIZE_64 * n_valid); 1338 } 1339 if (n_invalid) { 1340 memset(HPTE(spapr->htab, index + n_valid), 0, 1341 HASH_PTE_SIZE_64 * n_invalid); 1342 } 1343 } else { 1344 int rc; 1345 1346 assert(fd >= 0); 1347 1348 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1349 if (rc < 0) { 1350 return rc; 1351 } 1352 } 1353 } 1354 1355 if (!spapr->htab) { 1356 assert(fd >= 0); 1357 close(fd); 1358 } 1359 1360 return 0; 1361 } 1362 1363 static SaveVMHandlers savevm_htab_handlers = { 1364 .save_live_setup = htab_save_setup, 1365 .save_live_iterate = htab_save_iterate, 1366 .save_live_complete = htab_save_complete, 1367 .load_state = htab_load, 1368 }; 1369 1370 static void spapr_boot_set(void *opaque, const char *boot_device, 1371 Error **errp) 1372 { 1373 MachineState *machine = MACHINE(qdev_get_machine()); 1374 machine->boot_order = g_strdup(boot_device); 1375 } 1376 1377 /* pSeries LPAR / sPAPR hardware init */ 1378 static void ppc_spapr_init(MachineState *machine) 1379 { 1380 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1381 const char *cpu_model = machine->cpu_model; 1382 const char *kernel_filename = machine->kernel_filename; 1383 const char *kernel_cmdline = machine->kernel_cmdline; 1384 const char *initrd_filename = machine->initrd_filename; 1385 PowerPCCPU *cpu; 1386 CPUPPCState *env; 1387 PCIHostState *phb; 1388 int i; 1389 MemoryRegion *sysmem = get_system_memory(); 1390 MemoryRegion *ram = g_new(MemoryRegion, 1); 1391 MemoryRegion *rma_region; 1392 void *rma = NULL; 1393 hwaddr rma_alloc_size; 1394 hwaddr node0_size = spapr_node0_size(); 1395 uint32_t initrd_base = 0; 1396 long kernel_size = 0, initrd_size = 0; 1397 long load_limit, fw_size; 1398 bool kernel_le = false; 1399 char *filename; 1400 1401 msi_supported = true; 1402 1403 QLIST_INIT(&spapr->phbs); 1404 1405 cpu_ppc_hypercall = emulate_spapr_hypercall; 1406 1407 /* Allocate RMA if necessary */ 1408 rma_alloc_size = kvmppc_alloc_rma(&rma); 1409 1410 if (rma_alloc_size == -1) { 1411 error_report("Unable to create RMA"); 1412 exit(1); 1413 } 1414 1415 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1416 spapr->rma_size = rma_alloc_size; 1417 } else { 1418 spapr->rma_size = node0_size; 1419 1420 /* With KVM, we don't actually know whether KVM supports an 1421 * unbounded RMA (PR KVM) or is limited by the hash table size 1422 * (HV KVM using VRMA), so we always assume the latter 1423 * 1424 * In that case, we also limit the initial allocations for RTAS 1425 * etc... to 256M since we have no way to know what the VRMA size 1426 * is going to be as it depends on the size of the hash table 1427 * isn't determined yet. 1428 */ 1429 if (kvm_enabled()) { 1430 spapr->vrma_adjust = 1; 1431 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1432 } 1433 } 1434 1435 if (spapr->rma_size > node0_size) { 1436 fprintf(stderr, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")\n", 1437 spapr->rma_size); 1438 exit(1); 1439 } 1440 1441 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 1442 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 1443 1444 /* We aim for a hash table of size 1/128 the size of RAM. The 1445 * normal rule of thumb is 1/64 the size of RAM, but that's much 1446 * more than needed for the Linux guests we support. */ 1447 spapr->htab_shift = 18; /* Minimum architected size */ 1448 while (spapr->htab_shift <= 46) { 1449 if ((1ULL << (spapr->htab_shift + 7)) >= machine->ram_size) { 1450 break; 1451 } 1452 spapr->htab_shift++; 1453 } 1454 1455 /* Set up Interrupt Controller before we create the VCPUs */ 1456 spapr->icp = xics_system_init(machine, 1457 DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(), 1458 smp_threads), 1459 XICS_IRQS); 1460 1461 /* init CPUs */ 1462 if (cpu_model == NULL) { 1463 cpu_model = kvm_enabled() ? "host" : "POWER7"; 1464 } 1465 for (i = 0; i < smp_cpus; i++) { 1466 cpu = cpu_ppc_init(cpu_model); 1467 if (cpu == NULL) { 1468 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 1469 exit(1); 1470 } 1471 env = &cpu->env; 1472 1473 /* Set time-base frequency to 512 MHz */ 1474 cpu_ppc_tb_init(env, TIMEBASE_FREQ); 1475 1476 /* PAPR always has exception vectors in RAM not ROM. To ensure this, 1477 * MSR[IP] should never be set. 1478 */ 1479 env->msr_mask &= ~(1 << 6); 1480 1481 /* Tell KVM that we're in PAPR mode */ 1482 if (kvm_enabled()) { 1483 kvmppc_set_papr(cpu); 1484 } 1485 1486 if (cpu->max_compat) { 1487 if (ppc_set_compat(cpu, cpu->max_compat) < 0) { 1488 exit(1); 1489 } 1490 } 1491 1492 xics_cpu_setup(spapr->icp, cpu); 1493 1494 qemu_register_reset(spapr_cpu_reset, cpu); 1495 } 1496 1497 if (kvm_enabled()) { 1498 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 1499 kvmppc_enable_logical_ci_hcalls(); 1500 } 1501 1502 /* allocate RAM */ 1503 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 1504 machine->ram_size); 1505 memory_region_add_subregion(sysmem, 0, ram); 1506 1507 if (rma_alloc_size && rma) { 1508 rma_region = g_new(MemoryRegion, 1); 1509 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 1510 rma_alloc_size, rma); 1511 vmstate_register_ram_global(rma_region); 1512 memory_region_add_subregion(sysmem, 0, rma_region); 1513 } 1514 1515 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 1516 if (!filename) { 1517 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 1518 exit(1); 1519 } 1520 spapr->rtas_size = get_image_size(filename); 1521 spapr->rtas_blob = g_malloc(spapr->rtas_size); 1522 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 1523 error_report("Could not load LPAR rtas '%s'", filename); 1524 exit(1); 1525 } 1526 if (spapr->rtas_size > RTAS_MAX_SIZE) { 1527 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 1528 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 1529 exit(1); 1530 } 1531 g_free(filename); 1532 1533 /* Set up EPOW events infrastructure */ 1534 spapr_events_init(spapr); 1535 1536 /* Set up the RTC RTAS interfaces */ 1537 spapr_rtc_create(spapr); 1538 1539 /* Set up VIO bus */ 1540 spapr->vio_bus = spapr_vio_bus_init(); 1541 1542 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 1543 if (serial_hds[i]) { 1544 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 1545 } 1546 } 1547 1548 /* We always have at least the nvram device on VIO */ 1549 spapr_create_nvram(spapr); 1550 1551 /* Set up PCI */ 1552 spapr_pci_rtas_init(); 1553 1554 phb = spapr_create_phb(spapr, 0); 1555 1556 for (i = 0; i < nb_nics; i++) { 1557 NICInfo *nd = &nd_table[i]; 1558 1559 if (!nd->model) { 1560 nd->model = g_strdup("ibmveth"); 1561 } 1562 1563 if (strcmp(nd->model, "ibmveth") == 0) { 1564 spapr_vlan_create(spapr->vio_bus, nd); 1565 } else { 1566 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 1567 } 1568 } 1569 1570 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 1571 spapr_vscsi_create(spapr->vio_bus); 1572 } 1573 1574 /* Graphics */ 1575 if (spapr_vga_init(phb->bus)) { 1576 spapr->has_graphics = true; 1577 machine->usb |= defaults_enabled() && !machine->usb_disabled; 1578 } 1579 1580 if (machine->usb) { 1581 pci_create_simple(phb->bus, -1, "pci-ohci"); 1582 1583 if (spapr->has_graphics) { 1584 USBBus *usb_bus = usb_bus_find(-1); 1585 1586 usb_create_simple(usb_bus, "usb-kbd"); 1587 usb_create_simple(usb_bus, "usb-mouse"); 1588 } 1589 } 1590 1591 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 1592 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= " 1593 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF); 1594 exit(1); 1595 } 1596 1597 if (kernel_filename) { 1598 uint64_t lowaddr = 0; 1599 1600 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 1601 NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); 1602 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) { 1603 kernel_size = load_elf(kernel_filename, 1604 translate_kernel_address, NULL, 1605 NULL, &lowaddr, NULL, 0, ELF_MACHINE, 0); 1606 kernel_le = kernel_size > 0; 1607 } 1608 if (kernel_size < 0) { 1609 fprintf(stderr, "qemu: error loading %s: %s\n", 1610 kernel_filename, load_elf_strerror(kernel_size)); 1611 exit(1); 1612 } 1613 1614 /* load initrd */ 1615 if (initrd_filename) { 1616 /* Try to locate the initrd in the gap between the kernel 1617 * and the firmware. Add a bit of space just in case 1618 */ 1619 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; 1620 initrd_size = load_image_targphys(initrd_filename, initrd_base, 1621 load_limit - initrd_base); 1622 if (initrd_size < 0) { 1623 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 1624 initrd_filename); 1625 exit(1); 1626 } 1627 } else { 1628 initrd_base = 0; 1629 initrd_size = 0; 1630 } 1631 } 1632 1633 if (bios_name == NULL) { 1634 bios_name = FW_FILE_NAME; 1635 } 1636 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1637 if (!filename) { 1638 error_report("Could not find LPAR firmware '%s'", bios_name); 1639 exit(1); 1640 } 1641 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 1642 if (fw_size <= 0) { 1643 error_report("Could not load LPAR firmware '%s'", filename); 1644 exit(1); 1645 } 1646 g_free(filename); 1647 1648 /* FIXME: Should register things through the MachineState's qdev 1649 * interface, this is a legacy from the sPAPREnvironment structure 1650 * which predated MachineState but had a similar function */ 1651 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 1652 register_savevm_live(NULL, "spapr/htab", -1, 1, 1653 &savevm_htab_handlers, spapr); 1654 1655 /* Prepare the device tree */ 1656 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, 1657 kernel_size, kernel_le, 1658 kernel_cmdline, 1659 spapr->check_exception_irq); 1660 assert(spapr->fdt_skel != NULL); 1661 1662 /* used by RTAS */ 1663 QTAILQ_INIT(&spapr->ccs_list); 1664 qemu_register_reset(spapr_ccs_reset_hook, spapr); 1665 1666 qemu_register_boot_set(spapr_boot_set, spapr); 1667 } 1668 1669 static int spapr_kvm_type(const char *vm_type) 1670 { 1671 if (!vm_type) { 1672 return 0; 1673 } 1674 1675 if (!strcmp(vm_type, "HV")) { 1676 return 1; 1677 } 1678 1679 if (!strcmp(vm_type, "PR")) { 1680 return 2; 1681 } 1682 1683 error_report("Unknown kvm-type specified '%s'", vm_type); 1684 exit(1); 1685 } 1686 1687 /* 1688 * Implementation of an interface to adjust firmware path 1689 * for the bootindex property handling. 1690 */ 1691 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 1692 DeviceState *dev) 1693 { 1694 #define CAST(type, obj, name) \ 1695 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 1696 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 1697 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 1698 1699 if (d) { 1700 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 1701 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 1702 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 1703 1704 if (spapr) { 1705 /* 1706 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 1707 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 1708 * in the top 16 bits of the 64-bit LUN 1709 */ 1710 unsigned id = 0x8000 | (d->id << 8) | d->lun; 1711 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1712 (uint64_t)id << 48); 1713 } else if (virtio) { 1714 /* 1715 * We use SRP luns of the form 01000000 | (target << 8) | lun 1716 * in the top 32 bits of the 64-bit LUN 1717 * Note: the quote above is from SLOF and it is wrong, 1718 * the actual binding is: 1719 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 1720 */ 1721 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 1722 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1723 (uint64_t)id << 32); 1724 } else if (usb) { 1725 /* 1726 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 1727 * in the top 32 bits of the 64-bit LUN 1728 */ 1729 unsigned usb_port = atoi(usb->port->path); 1730 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 1731 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1732 (uint64_t)id << 32); 1733 } 1734 } 1735 1736 if (phb) { 1737 /* Replace "pci" with "pci@800000020000000" */ 1738 return g_strdup_printf("pci@%"PRIX64, phb->buid); 1739 } 1740 1741 return NULL; 1742 } 1743 1744 static char *spapr_get_kvm_type(Object *obj, Error **errp) 1745 { 1746 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 1747 1748 return g_strdup(spapr->kvm_type); 1749 } 1750 1751 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 1752 { 1753 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 1754 1755 g_free(spapr->kvm_type); 1756 spapr->kvm_type = g_strdup(value); 1757 } 1758 1759 static void spapr_machine_initfn(Object *obj) 1760 { 1761 object_property_add_str(obj, "kvm-type", 1762 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 1763 object_property_set_description(obj, "kvm-type", 1764 "Specifies the KVM virtualization mode (HV, PR)", 1765 NULL); 1766 } 1767 1768 static void ppc_cpu_do_nmi_on_cpu(void *arg) 1769 { 1770 CPUState *cs = arg; 1771 1772 cpu_synchronize_state(cs); 1773 ppc_cpu_do_system_reset(cs); 1774 } 1775 1776 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 1777 { 1778 CPUState *cs; 1779 1780 CPU_FOREACH(cs) { 1781 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs); 1782 } 1783 } 1784 1785 static void spapr_machine_class_init(ObjectClass *oc, void *data) 1786 { 1787 MachineClass *mc = MACHINE_CLASS(oc); 1788 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 1789 NMIClass *nc = NMI_CLASS(oc); 1790 1791 mc->init = ppc_spapr_init; 1792 mc->reset = ppc_spapr_reset; 1793 mc->block_default_type = IF_SCSI; 1794 mc->max_cpus = MAX_CPUS; 1795 mc->no_parallel = 1; 1796 mc->default_boot_order = ""; 1797 mc->default_ram_size = 512 * M_BYTE; 1798 mc->kvm_type = spapr_kvm_type; 1799 mc->has_dynamic_sysbus = true; 1800 1801 fwc->get_dev_path = spapr_get_fw_dev_path; 1802 nc->nmi_monitor_handler = spapr_nmi; 1803 } 1804 1805 static const TypeInfo spapr_machine_info = { 1806 .name = TYPE_SPAPR_MACHINE, 1807 .parent = TYPE_MACHINE, 1808 .abstract = true, 1809 .instance_size = sizeof(sPAPRMachineState), 1810 .instance_init = spapr_machine_initfn, 1811 .class_size = sizeof(sPAPRMachineClass), 1812 .class_init = spapr_machine_class_init, 1813 .interfaces = (InterfaceInfo[]) { 1814 { TYPE_FW_PATH_PROVIDER }, 1815 { TYPE_NMI }, 1816 { } 1817 }, 1818 }; 1819 1820 #define SPAPR_COMPAT_2_3 \ 1821 HW_COMPAT_2_3 \ 1822 {\ 1823 .driver = "spapr-pci-host-bridge",\ 1824 .property = "dynamic-reconfiguration",\ 1825 .value = "off",\ 1826 }, 1827 1828 #define SPAPR_COMPAT_2_2 \ 1829 SPAPR_COMPAT_2_3 \ 1830 HW_COMPAT_2_2 \ 1831 {\ 1832 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 1833 .property = "mem_win_size",\ 1834 .value = "0x20000000",\ 1835 }, 1836 1837 #define SPAPR_COMPAT_2_1 \ 1838 SPAPR_COMPAT_2_2 \ 1839 HW_COMPAT_2_1 1840 1841 static void spapr_compat_2_3(Object *obj) 1842 { 1843 } 1844 1845 static void spapr_compat_2_2(Object *obj) 1846 { 1847 spapr_compat_2_3(obj); 1848 } 1849 1850 static void spapr_compat_2_1(Object *obj) 1851 { 1852 spapr_compat_2_2(obj); 1853 } 1854 1855 static void spapr_machine_2_3_instance_init(Object *obj) 1856 { 1857 spapr_compat_2_3(obj); 1858 spapr_machine_initfn(obj); 1859 } 1860 1861 static void spapr_machine_2_2_instance_init(Object *obj) 1862 { 1863 spapr_compat_2_2(obj); 1864 spapr_machine_initfn(obj); 1865 } 1866 1867 static void spapr_machine_2_1_instance_init(Object *obj) 1868 { 1869 spapr_compat_2_1(obj); 1870 spapr_machine_initfn(obj); 1871 } 1872 1873 static void spapr_machine_2_1_class_init(ObjectClass *oc, void *data) 1874 { 1875 MachineClass *mc = MACHINE_CLASS(oc); 1876 static GlobalProperty compat_props[] = { 1877 SPAPR_COMPAT_2_1 1878 { /* end of list */ } 1879 }; 1880 1881 mc->name = "pseries-2.1"; 1882 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.1"; 1883 mc->compat_props = compat_props; 1884 } 1885 1886 static const TypeInfo spapr_machine_2_1_info = { 1887 .name = TYPE_SPAPR_MACHINE "2.1", 1888 .parent = TYPE_SPAPR_MACHINE, 1889 .class_init = spapr_machine_2_1_class_init, 1890 .instance_init = spapr_machine_2_1_instance_init, 1891 }; 1892 1893 static void spapr_machine_2_2_class_init(ObjectClass *oc, void *data) 1894 { 1895 static GlobalProperty compat_props[] = { 1896 SPAPR_COMPAT_2_2 1897 { /* end of list */ } 1898 }; 1899 MachineClass *mc = MACHINE_CLASS(oc); 1900 1901 mc->name = "pseries-2.2"; 1902 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.2"; 1903 mc->compat_props = compat_props; 1904 } 1905 1906 static const TypeInfo spapr_machine_2_2_info = { 1907 .name = TYPE_SPAPR_MACHINE "2.2", 1908 .parent = TYPE_SPAPR_MACHINE, 1909 .class_init = spapr_machine_2_2_class_init, 1910 .instance_init = spapr_machine_2_2_instance_init, 1911 }; 1912 1913 static void spapr_machine_2_3_class_init(ObjectClass *oc, void *data) 1914 { 1915 static GlobalProperty compat_props[] = { 1916 SPAPR_COMPAT_2_3 1917 { /* end of list */ } 1918 }; 1919 MachineClass *mc = MACHINE_CLASS(oc); 1920 1921 mc->name = "pseries-2.3"; 1922 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.3"; 1923 mc->compat_props = compat_props; 1924 } 1925 1926 static const TypeInfo spapr_machine_2_3_info = { 1927 .name = TYPE_SPAPR_MACHINE "2.3", 1928 .parent = TYPE_SPAPR_MACHINE, 1929 .class_init = spapr_machine_2_3_class_init, 1930 .instance_init = spapr_machine_2_3_instance_init, 1931 }; 1932 1933 static void spapr_machine_2_4_class_init(ObjectClass *oc, void *data) 1934 { 1935 MachineClass *mc = MACHINE_CLASS(oc); 1936 1937 mc->name = "pseries-2.4"; 1938 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.4"; 1939 mc->alias = "pseries"; 1940 mc->is_default = 1; 1941 } 1942 1943 static const TypeInfo spapr_machine_2_4_info = { 1944 .name = TYPE_SPAPR_MACHINE "2.4", 1945 .parent = TYPE_SPAPR_MACHINE, 1946 .class_init = spapr_machine_2_4_class_init, 1947 }; 1948 1949 static void spapr_machine_register_types(void) 1950 { 1951 type_register_static(&spapr_machine_info); 1952 type_register_static(&spapr_machine_2_1_info); 1953 type_register_static(&spapr_machine_2_2_info); 1954 type_register_static(&spapr_machine_2_3_info); 1955 type_register_static(&spapr_machine_2_4_info); 1956 } 1957 1958 type_init(spapr_machine_register_types) 1959