1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "sysemu/sysemu.h" 28 #include "sysemu/numa.h" 29 #include "hw/hw.h" 30 #include "hw/fw-path-provider.h" 31 #include "elf.h" 32 #include "net/net.h" 33 #include "sysemu/device_tree.h" 34 #include "sysemu/block-backend.h" 35 #include "sysemu/cpus.h" 36 #include "sysemu/kvm.h" 37 #include "sysemu/device_tree.h" 38 #include "kvm_ppc.h" 39 #include "migration/migration.h" 40 #include "mmu-hash64.h" 41 #include "qom/cpu.h" 42 43 #include "hw/boards.h" 44 #include "hw/ppc/ppc.h" 45 #include "hw/loader.h" 46 47 #include "hw/ppc/spapr.h" 48 #include "hw/ppc/spapr_vio.h" 49 #include "hw/pci-host/spapr.h" 50 #include "hw/ppc/xics.h" 51 #include "hw/pci/msi.h" 52 53 #include "hw/pci/pci.h" 54 #include "hw/scsi/scsi.h" 55 #include "hw/virtio/virtio-scsi.h" 56 57 #include "exec/address-spaces.h" 58 #include "hw/usb.h" 59 #include "qemu/config-file.h" 60 #include "qemu/error-report.h" 61 #include "trace.h" 62 #include "hw/nmi.h" 63 64 #include "hw/compat.h" 65 #include "qemu-common.h" 66 67 #include <libfdt.h> 68 69 /* SLOF memory layout: 70 * 71 * SLOF raw image loaded at 0, copies its romfs right below the flat 72 * device-tree, then position SLOF itself 31M below that 73 * 74 * So we set FW_OVERHEAD to 40MB which should account for all of that 75 * and more 76 * 77 * We load our kernel at 4M, leaving space for SLOF initial image 78 */ 79 #define FDT_MAX_SIZE 0x100000 80 #define RTAS_MAX_SIZE 0x10000 81 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 82 #define FW_MAX_SIZE 0x400000 83 #define FW_FILE_NAME "slof.bin" 84 #define FW_OVERHEAD 0x2800000 85 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 86 87 #define MIN_RMA_SLOF 128UL 88 89 #define TIMEBASE_FREQ 512000000ULL 90 91 #define PHANDLE_XICP 0x00001111 92 93 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 94 95 static XICSState *try_create_xics(const char *type, int nr_servers, 96 int nr_irqs, Error **errp) 97 { 98 Error *err = NULL; 99 DeviceState *dev; 100 101 dev = qdev_create(NULL, type); 102 qdev_prop_set_uint32(dev, "nr_servers", nr_servers); 103 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); 104 object_property_set_bool(OBJECT(dev), true, "realized", &err); 105 if (err) { 106 error_propagate(errp, err); 107 object_unparent(OBJECT(dev)); 108 return NULL; 109 } 110 return XICS_COMMON(dev); 111 } 112 113 static XICSState *xics_system_init(MachineState *machine, 114 int nr_servers, int nr_irqs) 115 { 116 XICSState *icp = NULL; 117 118 if (kvm_enabled()) { 119 Error *err = NULL; 120 121 if (machine_kernel_irqchip_allowed(machine)) { 122 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs, &err); 123 } 124 if (machine_kernel_irqchip_required(machine) && !icp) { 125 error_report("kernel_irqchip requested but unavailable: %s", 126 error_get_pretty(err)); 127 } 128 } 129 130 if (!icp) { 131 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs, &error_abort); 132 } 133 134 return icp; 135 } 136 137 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 138 int smt_threads) 139 { 140 int i, ret = 0; 141 uint32_t servers_prop[smt_threads]; 142 uint32_t gservers_prop[smt_threads * 2]; 143 int index = ppc_get_vcpu_dt_id(cpu); 144 145 if (cpu->cpu_version) { 146 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version); 147 if (ret < 0) { 148 return ret; 149 } 150 } 151 152 /* Build interrupt servers and gservers properties */ 153 for (i = 0; i < smt_threads; i++) { 154 servers_prop[i] = cpu_to_be32(index + i); 155 /* Hack, direct the group queues back to cpu 0 */ 156 gservers_prop[i*2] = cpu_to_be32(index + i); 157 gservers_prop[i*2 + 1] = 0; 158 } 159 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 160 servers_prop, sizeof(servers_prop)); 161 if (ret < 0) { 162 return ret; 163 } 164 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 165 gservers_prop, sizeof(gservers_prop)); 166 167 return ret; 168 } 169 170 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs) 171 { 172 int ret = 0; 173 PowerPCCPU *cpu = POWERPC_CPU(cs); 174 int index = ppc_get_vcpu_dt_id(cpu); 175 uint32_t associativity[] = {cpu_to_be32(0x5), 176 cpu_to_be32(0x0), 177 cpu_to_be32(0x0), 178 cpu_to_be32(0x0), 179 cpu_to_be32(cs->numa_node), 180 cpu_to_be32(index)}; 181 182 /* Advertise NUMA via ibm,associativity */ 183 if (nb_numa_nodes > 1) { 184 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 185 sizeof(associativity)); 186 } 187 188 return ret; 189 } 190 191 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 192 { 193 int ret = 0, offset, cpus_offset; 194 CPUState *cs; 195 char cpu_model[32]; 196 int smt = kvmppc_smt_threads(); 197 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 198 199 CPU_FOREACH(cs) { 200 PowerPCCPU *cpu = POWERPC_CPU(cs); 201 DeviceClass *dc = DEVICE_GET_CLASS(cs); 202 int index = ppc_get_vcpu_dt_id(cpu); 203 204 if ((index % smt) != 0) { 205 continue; 206 } 207 208 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 209 210 cpus_offset = fdt_path_offset(fdt, "/cpus"); 211 if (cpus_offset < 0) { 212 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 213 "cpus"); 214 if (cpus_offset < 0) { 215 return cpus_offset; 216 } 217 } 218 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 219 if (offset < 0) { 220 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 221 if (offset < 0) { 222 return offset; 223 } 224 } 225 226 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 227 pft_size_prop, sizeof(pft_size_prop)); 228 if (ret < 0) { 229 return ret; 230 } 231 232 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs); 233 if (ret < 0) { 234 return ret; 235 } 236 237 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 238 ppc_get_compat_smt_threads(cpu)); 239 if (ret < 0) { 240 return ret; 241 } 242 } 243 return ret; 244 } 245 246 247 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, 248 size_t maxsize) 249 { 250 size_t maxcells = maxsize / sizeof(uint32_t); 251 int i, j, count; 252 uint32_t *p = prop; 253 254 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 255 struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; 256 257 if (!sps->page_shift) { 258 break; 259 } 260 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { 261 if (sps->enc[count].page_shift == 0) { 262 break; 263 } 264 } 265 if ((p - prop) >= (maxcells - 3 - count * 2)) { 266 break; 267 } 268 *(p++) = cpu_to_be32(sps->page_shift); 269 *(p++) = cpu_to_be32(sps->slb_enc); 270 *(p++) = cpu_to_be32(count); 271 for (j = 0; j < count; j++) { 272 *(p++) = cpu_to_be32(sps->enc[j].page_shift); 273 *(p++) = cpu_to_be32(sps->enc[j].pte_enc); 274 } 275 } 276 277 return (p - prop) * sizeof(uint32_t); 278 } 279 280 static hwaddr spapr_node0_size(void) 281 { 282 MachineState *machine = MACHINE(qdev_get_machine()); 283 284 if (nb_numa_nodes) { 285 int i; 286 for (i = 0; i < nb_numa_nodes; ++i) { 287 if (numa_info[i].node_mem) { 288 return MIN(pow2floor(numa_info[i].node_mem), 289 machine->ram_size); 290 } 291 } 292 } 293 return machine->ram_size; 294 } 295 296 #define _FDT(exp) \ 297 do { \ 298 int ret = (exp); \ 299 if (ret < 0) { \ 300 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ 301 #exp, fdt_strerror(ret)); \ 302 exit(1); \ 303 } \ 304 } while (0) 305 306 static void add_str(GString *s, const gchar *s1) 307 { 308 g_string_append_len(s, s1, strlen(s1) + 1); 309 } 310 311 static void *spapr_create_fdt_skel(hwaddr initrd_base, 312 hwaddr initrd_size, 313 hwaddr kernel_size, 314 bool little_endian, 315 const char *kernel_cmdline, 316 uint32_t epow_irq) 317 { 318 void *fdt; 319 uint32_t start_prop = cpu_to_be32(initrd_base); 320 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); 321 GString *hypertas = g_string_sized_new(256); 322 GString *qemu_hypertas = g_string_sized_new(256); 323 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; 324 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)}; 325 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; 326 char *buf; 327 328 add_str(hypertas, "hcall-pft"); 329 add_str(hypertas, "hcall-term"); 330 add_str(hypertas, "hcall-dabr"); 331 add_str(hypertas, "hcall-interrupt"); 332 add_str(hypertas, "hcall-tce"); 333 add_str(hypertas, "hcall-vio"); 334 add_str(hypertas, "hcall-splpar"); 335 add_str(hypertas, "hcall-bulk"); 336 add_str(hypertas, "hcall-set-mode"); 337 add_str(qemu_hypertas, "hcall-memop1"); 338 339 fdt = g_malloc0(FDT_MAX_SIZE); 340 _FDT((fdt_create(fdt, FDT_MAX_SIZE))); 341 342 if (kernel_size) { 343 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); 344 } 345 if (initrd_size) { 346 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); 347 } 348 _FDT((fdt_finish_reservemap(fdt))); 349 350 /* Root node */ 351 _FDT((fdt_begin_node(fdt, ""))); 352 _FDT((fdt_property_string(fdt, "device_type", "chrp"))); 353 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); 354 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); 355 356 /* 357 * Add info to guest to indentify which host is it being run on 358 * and what is the uuid of the guest 359 */ 360 if (kvmppc_get_host_model(&buf)) { 361 _FDT((fdt_property_string(fdt, "host-model", buf))); 362 g_free(buf); 363 } 364 if (kvmppc_get_host_serial(&buf)) { 365 _FDT((fdt_property_string(fdt, "host-serial", buf))); 366 g_free(buf); 367 } 368 369 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1], 370 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4], 371 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7], 372 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10], 373 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13], 374 qemu_uuid[14], qemu_uuid[15]); 375 376 _FDT((fdt_property_string(fdt, "vm,uuid", buf))); 377 g_free(buf); 378 379 if (qemu_get_vm_name()) { 380 _FDT((fdt_property_string(fdt, "ibm,partition-name", 381 qemu_get_vm_name()))); 382 } 383 384 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); 385 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); 386 387 /* /chosen */ 388 _FDT((fdt_begin_node(fdt, "chosen"))); 389 390 /* Set Form1_affinity */ 391 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); 392 393 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); 394 _FDT((fdt_property(fdt, "linux,initrd-start", 395 &start_prop, sizeof(start_prop)))); 396 _FDT((fdt_property(fdt, "linux,initrd-end", 397 &end_prop, sizeof(end_prop)))); 398 if (kernel_size) { 399 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 400 cpu_to_be64(kernel_size) }; 401 402 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); 403 if (little_endian) { 404 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); 405 } 406 } 407 if (boot_menu) { 408 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu))); 409 } 410 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); 411 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); 412 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); 413 414 _FDT((fdt_end_node(fdt))); 415 416 /* RTAS */ 417 _FDT((fdt_begin_node(fdt, "rtas"))); 418 419 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 420 add_str(hypertas, "hcall-multi-tce"); 421 } 422 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str, 423 hypertas->len))); 424 g_string_free(hypertas, TRUE); 425 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str, 426 qemu_hypertas->len))); 427 g_string_free(qemu_hypertas, TRUE); 428 429 _FDT((fdt_property(fdt, "ibm,associativity-reference-points", 430 refpoints, sizeof(refpoints)))); 431 432 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); 433 _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate", 434 RTAS_EVENT_SCAN_RATE))); 435 436 if (msi_supported) { 437 _FDT((fdt_property(fdt, "ibm,change-msix-capable", NULL, 0))); 438 } 439 440 /* 441 * According to PAPR, rtas ibm,os-term does not guarantee a return 442 * back to the guest cpu. 443 * 444 * While an additional ibm,extended-os-term property indicates that 445 * rtas call return will always occur. Set this property. 446 */ 447 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0))); 448 449 _FDT((fdt_end_node(fdt))); 450 451 /* interrupt controller */ 452 _FDT((fdt_begin_node(fdt, "interrupt-controller"))); 453 454 _FDT((fdt_property_string(fdt, "device_type", 455 "PowerPC-External-Interrupt-Presentation"))); 456 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); 457 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 458 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", 459 interrupt_server_ranges_prop, 460 sizeof(interrupt_server_ranges_prop)))); 461 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); 462 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); 463 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); 464 465 _FDT((fdt_end_node(fdt))); 466 467 /* vdevice */ 468 _FDT((fdt_begin_node(fdt, "vdevice"))); 469 470 _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); 471 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); 472 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 473 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 474 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); 475 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 476 477 _FDT((fdt_end_node(fdt))); 478 479 /* event-sources */ 480 spapr_events_fdt_skel(fdt, epow_irq); 481 482 /* /hypervisor node */ 483 if (kvm_enabled()) { 484 uint8_t hypercall[16]; 485 486 /* indicate KVM hypercall interface */ 487 _FDT((fdt_begin_node(fdt, "hypervisor"))); 488 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm"))); 489 if (kvmppc_has_cap_fixup_hcalls()) { 490 /* 491 * Older KVM versions with older guest kernels were broken with the 492 * magic page, don't allow the guest to map it. 493 */ 494 kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 495 sizeof(hypercall)); 496 _FDT((fdt_property(fdt, "hcall-instructions", hypercall, 497 sizeof(hypercall)))); 498 } 499 _FDT((fdt_end_node(fdt))); 500 } 501 502 _FDT((fdt_end_node(fdt))); /* close root node */ 503 _FDT((fdt_finish(fdt))); 504 505 return fdt; 506 } 507 508 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 509 hwaddr size) 510 { 511 uint32_t associativity[] = { 512 cpu_to_be32(0x4), /* length */ 513 cpu_to_be32(0x0), cpu_to_be32(0x0), 514 cpu_to_be32(0x0), cpu_to_be32(nodeid) 515 }; 516 char mem_name[32]; 517 uint64_t mem_reg_property[2]; 518 int off; 519 520 mem_reg_property[0] = cpu_to_be64(start); 521 mem_reg_property[1] = cpu_to_be64(size); 522 523 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 524 off = fdt_add_subnode(fdt, 0, mem_name); 525 _FDT(off); 526 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 527 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 528 sizeof(mem_reg_property)))); 529 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 530 sizeof(associativity)))); 531 return off; 532 } 533 534 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 535 { 536 MachineState *machine = MACHINE(spapr); 537 hwaddr mem_start, node_size; 538 int i, nb_nodes = nb_numa_nodes; 539 NodeInfo *nodes = numa_info; 540 NodeInfo ramnode; 541 542 /* No NUMA nodes, assume there is just one node with whole RAM */ 543 if (!nb_numa_nodes) { 544 nb_nodes = 1; 545 ramnode.node_mem = machine->ram_size; 546 nodes = &ramnode; 547 } 548 549 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 550 if (!nodes[i].node_mem) { 551 continue; 552 } 553 if (mem_start >= machine->ram_size) { 554 node_size = 0; 555 } else { 556 node_size = nodes[i].node_mem; 557 if (node_size > machine->ram_size - mem_start) { 558 node_size = machine->ram_size - mem_start; 559 } 560 } 561 if (!mem_start) { 562 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 563 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 564 mem_start += spapr->rma_size; 565 node_size -= spapr->rma_size; 566 } 567 for ( ; node_size; ) { 568 hwaddr sizetmp = pow2floor(node_size); 569 570 /* mem_start != 0 here */ 571 if (ctzl(mem_start) < ctzl(sizetmp)) { 572 sizetmp = 1ULL << ctzl(mem_start); 573 } 574 575 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 576 node_size -= sizetmp; 577 mem_start += sizetmp; 578 } 579 } 580 581 return 0; 582 } 583 584 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 585 sPAPRMachineState *spapr) 586 { 587 PowerPCCPU *cpu = POWERPC_CPU(cs); 588 CPUPPCState *env = &cpu->env; 589 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 590 int index = ppc_get_vcpu_dt_id(cpu); 591 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 592 0xffffffff, 0xffffffff}; 593 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; 594 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 595 uint32_t page_sizes_prop[64]; 596 size_t page_sizes_prop_size; 597 uint32_t vcpus_per_socket = smp_threads * smp_cores; 598 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 599 600 /* Note: we keep CI large pages off for now because a 64K capable guest 601 * provisioned with large pages might otherwise try to map a qemu 602 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 603 * even if that qemu runs on a 4k host. 604 * 605 * We can later add this bit back when we are confident this is not 606 * an issue (!HV KVM or 64K host) 607 */ 608 uint8_t pa_features_206[] = { 6, 0, 609 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 610 uint8_t pa_features_207[] = { 24, 0, 611 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 612 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 613 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 614 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 615 uint8_t *pa_features; 616 size_t pa_size; 617 618 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 619 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 620 621 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 622 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 623 env->dcache_line_size))); 624 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 625 env->dcache_line_size))); 626 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 627 env->icache_line_size))); 628 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 629 env->icache_line_size))); 630 631 if (pcc->l1_dcache_size) { 632 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 633 pcc->l1_dcache_size))); 634 } else { 635 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); 636 } 637 if (pcc->l1_icache_size) { 638 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 639 pcc->l1_icache_size))); 640 } else { 641 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); 642 } 643 644 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 645 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 646 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 647 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 648 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 649 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 650 651 if (env->spr_cb[SPR_PURR].oea_read) { 652 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 653 } 654 655 if (env->mmu_model & POWERPC_MMU_1TSEG) { 656 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 657 segs, sizeof(segs)))); 658 } 659 660 /* Advertise VMX/VSX (vector extensions) if available 661 * 0 / no property == no vector extensions 662 * 1 == VMX / Altivec available 663 * 2 == VSX available */ 664 if (env->insns_flags & PPC_ALTIVEC) { 665 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 666 667 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 668 } 669 670 /* Advertise DFP (Decimal Floating Point) if available 671 * 0 / no property == no DFP 672 * 1 == DFP available */ 673 if (env->insns_flags2 & PPC2_DFP) { 674 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 675 } 676 677 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, 678 sizeof(page_sizes_prop)); 679 if (page_sizes_prop_size) { 680 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 681 page_sizes_prop, page_sizes_prop_size))); 682 } 683 684 /* Do the ibm,pa-features property, adjust it for ci-large-pages */ 685 if (env->mmu_model == POWERPC_MMU_2_06) { 686 pa_features = pa_features_206; 687 pa_size = sizeof(pa_features_206); 688 } else /* env->mmu_model == POWERPC_MMU_2_07 */ { 689 pa_features = pa_features_207; 690 pa_size = sizeof(pa_features_207); 691 } 692 if (env->ci_large_pages) { 693 pa_features[3] |= 0x20; 694 } 695 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 696 697 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 698 cs->cpu_index / vcpus_per_socket))); 699 700 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 701 pft_size_prop, sizeof(pft_size_prop)))); 702 703 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs)); 704 705 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 706 ppc_get_compat_smt_threads(cpu))); 707 } 708 709 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 710 { 711 CPUState *cs; 712 int cpus_offset; 713 char *nodename; 714 int smt = kvmppc_smt_threads(); 715 716 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 717 _FDT(cpus_offset); 718 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 719 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 720 721 /* 722 * We walk the CPUs in reverse order to ensure that CPU DT nodes 723 * created by fdt_add_subnode() end up in the right order in FDT 724 * for the guest kernel the enumerate the CPUs correctly. 725 */ 726 CPU_FOREACH_REVERSE(cs) { 727 PowerPCCPU *cpu = POWERPC_CPU(cs); 728 int index = ppc_get_vcpu_dt_id(cpu); 729 DeviceClass *dc = DEVICE_GET_CLASS(cs); 730 int offset; 731 732 if ((index % smt) != 0) { 733 continue; 734 } 735 736 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 737 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 738 g_free(nodename); 739 _FDT(offset); 740 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 741 } 742 743 } 744 745 /* 746 * Adds ibm,dynamic-reconfiguration-memory node. 747 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 748 * of this device tree node. 749 */ 750 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 751 { 752 MachineState *machine = MACHINE(spapr); 753 int ret, i, offset; 754 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 755 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 756 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 757 uint32_t *int_buf, *cur_index, buf_len; 758 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 759 760 /* 761 * Allocate enough buffer size to fit in ibm,dynamic-memory 762 * or ibm,associativity-lookup-arrays 763 */ 764 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 765 * sizeof(uint32_t); 766 cur_index = int_buf = g_malloc0(buf_len); 767 768 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 769 770 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 771 sizeof(prop_lmb_size)); 772 if (ret < 0) { 773 goto out; 774 } 775 776 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 777 if (ret < 0) { 778 goto out; 779 } 780 781 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 782 if (ret < 0) { 783 goto out; 784 } 785 786 /* ibm,dynamic-memory */ 787 int_buf[0] = cpu_to_be32(nr_lmbs); 788 cur_index++; 789 for (i = 0; i < nr_lmbs; i++) { 790 sPAPRDRConnector *drc; 791 sPAPRDRConnectorClass *drck; 792 uint64_t addr = i * lmb_size + spapr->hotplug_memory.base;; 793 uint32_t *dynamic_memory = cur_index; 794 795 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 796 addr/lmb_size); 797 g_assert(drc); 798 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 799 800 dynamic_memory[0] = cpu_to_be32(addr >> 32); 801 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 802 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); 803 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 804 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); 805 if (addr < machine->ram_size || 806 memory_region_present(get_system_memory(), addr)) { 807 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 808 } else { 809 dynamic_memory[5] = cpu_to_be32(0); 810 } 811 812 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 813 } 814 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 815 if (ret < 0) { 816 goto out; 817 } 818 819 /* ibm,associativity-lookup-arrays */ 820 cur_index = int_buf; 821 int_buf[0] = cpu_to_be32(nr_nodes); 822 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 823 cur_index += 2; 824 for (i = 0; i < nr_nodes; i++) { 825 uint32_t associativity[] = { 826 cpu_to_be32(0x0), 827 cpu_to_be32(0x0), 828 cpu_to_be32(0x0), 829 cpu_to_be32(i) 830 }; 831 memcpy(cur_index, associativity, sizeof(associativity)); 832 cur_index += 4; 833 } 834 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 835 (cur_index - int_buf) * sizeof(uint32_t)); 836 out: 837 g_free(int_buf); 838 return ret; 839 } 840 841 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 842 target_ulong addr, target_ulong size, 843 bool cpu_update, bool memory_update) 844 { 845 void *fdt, *fdt_skel; 846 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 847 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 848 849 size -= sizeof(hdr); 850 851 /* Create sceleton */ 852 fdt_skel = g_malloc0(size); 853 _FDT((fdt_create(fdt_skel, size))); 854 _FDT((fdt_begin_node(fdt_skel, ""))); 855 _FDT((fdt_end_node(fdt_skel))); 856 _FDT((fdt_finish(fdt_skel))); 857 fdt = g_malloc0(size); 858 _FDT((fdt_open_into(fdt_skel, fdt, size))); 859 g_free(fdt_skel); 860 861 /* Fixup cpu nodes */ 862 if (cpu_update) { 863 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 864 } 865 866 /* Generate memory nodes or ibm,dynamic-reconfiguration-memory node */ 867 if (memory_update && smc->dr_lmb_enabled) { 868 _FDT((spapr_populate_drconf_memory(spapr, fdt))); 869 } 870 871 /* Pack resulting tree */ 872 _FDT((fdt_pack(fdt))); 873 874 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 875 trace_spapr_cas_failed(size); 876 return -1; 877 } 878 879 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 880 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 881 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 882 g_free(fdt); 883 884 return 0; 885 } 886 887 static void spapr_finalize_fdt(sPAPRMachineState *spapr, 888 hwaddr fdt_addr, 889 hwaddr rtas_addr, 890 hwaddr rtas_size) 891 { 892 MachineState *machine = MACHINE(qdev_get_machine()); 893 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 894 const char *boot_device = machine->boot_order; 895 int ret, i; 896 size_t cb = 0; 897 char *bootlist; 898 void *fdt; 899 sPAPRPHBState *phb; 900 901 fdt = g_malloc(FDT_MAX_SIZE); 902 903 /* open out the base tree into a temp buffer for the final tweaks */ 904 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); 905 906 ret = spapr_populate_memory(spapr, fdt); 907 if (ret < 0) { 908 fprintf(stderr, "couldn't setup memory nodes in fdt\n"); 909 exit(1); 910 } 911 912 ret = spapr_populate_vdevice(spapr->vio_bus, fdt); 913 if (ret < 0) { 914 fprintf(stderr, "couldn't setup vio devices in fdt\n"); 915 exit(1); 916 } 917 918 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 919 ret = spapr_rng_populate_dt(fdt); 920 if (ret < 0) { 921 fprintf(stderr, "could not set up rng device in the fdt\n"); 922 exit(1); 923 } 924 } 925 926 QLIST_FOREACH(phb, &spapr->phbs, list) { 927 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 928 } 929 930 if (ret < 0) { 931 fprintf(stderr, "couldn't setup PCI devices in fdt\n"); 932 exit(1); 933 } 934 935 /* RTAS */ 936 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); 937 if (ret < 0) { 938 fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); 939 } 940 941 /* cpus */ 942 spapr_populate_cpus_dt_node(fdt, spapr); 943 944 bootlist = get_boot_devices_list(&cb, true); 945 if (cb && bootlist) { 946 int offset = fdt_path_offset(fdt, "/chosen"); 947 if (offset < 0) { 948 exit(1); 949 } 950 for (i = 0; i < cb; i++) { 951 if (bootlist[i] == '\n') { 952 bootlist[i] = ' '; 953 } 954 955 } 956 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist); 957 } 958 959 if (boot_device && strlen(boot_device)) { 960 int offset = fdt_path_offset(fdt, "/chosen"); 961 962 if (offset < 0) { 963 exit(1); 964 } 965 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device); 966 } 967 968 if (!spapr->has_graphics) { 969 spapr_populate_chosen_stdout(fdt, spapr->vio_bus); 970 } 971 972 if (smc->dr_lmb_enabled) { 973 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 974 } 975 976 _FDT((fdt_pack(fdt))); 977 978 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 979 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 980 fdt_totalsize(fdt), FDT_MAX_SIZE); 981 exit(1); 982 } 983 984 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 985 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 986 987 g_free(bootlist); 988 g_free(fdt); 989 } 990 991 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 992 { 993 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 994 } 995 996 static void emulate_spapr_hypercall(PowerPCCPU *cpu) 997 { 998 CPUPPCState *env = &cpu->env; 999 1000 if (msr_pr) { 1001 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1002 env->gpr[3] = H_PRIVILEGE; 1003 } else { 1004 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1005 } 1006 } 1007 1008 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1009 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1010 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1011 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1012 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1013 1014 static void spapr_alloc_htab(sPAPRMachineState *spapr) 1015 { 1016 long shift; 1017 int index; 1018 1019 /* allocate hash page table. For now we always make this 16mb, 1020 * later we should probably make it scale to the size of guest 1021 * RAM */ 1022 1023 shift = kvmppc_reset_htab(spapr->htab_shift); 1024 1025 if (shift > 0) { 1026 /* Kernel handles htab, we don't need to allocate one */ 1027 if (shift != spapr->htab_shift) { 1028 error_setg(&error_abort, "Failed to allocate HTAB of requested size, try with smaller maxmem"); 1029 } 1030 1031 spapr->htab_shift = shift; 1032 kvmppc_kern_htab = true; 1033 } else { 1034 /* Allocate htab */ 1035 spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); 1036 1037 /* And clear it */ 1038 memset(spapr->htab, 0, HTAB_SIZE(spapr)); 1039 1040 for (index = 0; index < HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; index++) { 1041 DIRTY_HPTE(HPTE(spapr->htab, index)); 1042 } 1043 } 1044 } 1045 1046 /* 1047 * Clear HTAB entries during reset. 1048 * 1049 * If host kernel has allocated HTAB, KVM_PPC_ALLOCATE_HTAB ioctl is 1050 * used to clear HTAB. Otherwise QEMU-allocated HTAB is cleared manually. 1051 */ 1052 static void spapr_reset_htab(sPAPRMachineState *spapr) 1053 { 1054 long shift; 1055 int index; 1056 1057 shift = kvmppc_reset_htab(spapr->htab_shift); 1058 if (shift > 0) { 1059 if (shift != spapr->htab_shift) { 1060 error_setg(&error_abort, "Requested HTAB allocation failed during reset"); 1061 } 1062 1063 /* Tell readers to update their file descriptor */ 1064 if (spapr->htab_fd >= 0) { 1065 spapr->htab_fd_stale = true; 1066 } 1067 } else { 1068 memset(spapr->htab, 0, HTAB_SIZE(spapr)); 1069 1070 for (index = 0; index < HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; index++) { 1071 DIRTY_HPTE(HPTE(spapr->htab, index)); 1072 } 1073 } 1074 1075 /* Update the RMA size if necessary */ 1076 if (spapr->vrma_adjust) { 1077 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 1078 spapr->htab_shift); 1079 } 1080 } 1081 1082 static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1083 { 1084 bool matched = false; 1085 1086 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1087 matched = true; 1088 } 1089 1090 if (!matched) { 1091 error_report("Device %s is not supported by this machine yet.", 1092 qdev_fw_name(DEVICE(sbdev))); 1093 exit(1); 1094 } 1095 1096 return 0; 1097 } 1098 1099 /* 1100 * A guest reset will cause spapr->htab_fd to become stale if being used. 1101 * Reopen the file descriptor to make sure the whole HTAB is properly read. 1102 */ 1103 static int spapr_check_htab_fd(sPAPRMachineState *spapr) 1104 { 1105 int rc = 0; 1106 1107 if (spapr->htab_fd_stale) { 1108 close(spapr->htab_fd); 1109 spapr->htab_fd = kvmppc_get_htab_fd(false); 1110 if (spapr->htab_fd < 0) { 1111 error_report("Unable to open fd for reading hash table from KVM: " 1112 "%s", strerror(errno)); 1113 rc = -1; 1114 } 1115 spapr->htab_fd_stale = false; 1116 } 1117 1118 return rc; 1119 } 1120 1121 static void ppc_spapr_reset(void) 1122 { 1123 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1124 PowerPCCPU *first_ppc_cpu; 1125 uint32_t rtas_limit; 1126 1127 /* Check for unknown sysbus devices */ 1128 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1129 1130 /* Reset the hash table & recalc the RMA */ 1131 spapr_reset_htab(spapr); 1132 1133 qemu_devices_reset(); 1134 1135 /* 1136 * We place the device tree and RTAS just below either the top of the RMA, 1137 * or just below 2GB, whichever is lowere, so that it can be 1138 * processed with 32-bit real mode code if necessary 1139 */ 1140 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1141 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1142 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; 1143 1144 /* Load the fdt */ 1145 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, 1146 spapr->rtas_size); 1147 1148 /* Copy RTAS over */ 1149 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob, 1150 spapr->rtas_size); 1151 1152 /* Set up the entry state */ 1153 first_ppc_cpu = POWERPC_CPU(first_cpu); 1154 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; 1155 first_ppc_cpu->env.gpr[5] = 0; 1156 first_cpu->halted = 0; 1157 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1158 1159 } 1160 1161 static void spapr_cpu_reset(void *opaque) 1162 { 1163 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1164 PowerPCCPU *cpu = opaque; 1165 CPUState *cs = CPU(cpu); 1166 CPUPPCState *env = &cpu->env; 1167 1168 cpu_reset(cs); 1169 1170 /* All CPUs start halted. CPU0 is unhalted from the machine level 1171 * reset code and the rest are explicitly started up by the guest 1172 * using an RTAS call */ 1173 cs->halted = 1; 1174 1175 env->spr[SPR_HIOR] = 0; 1176 1177 env->external_htab = (uint8_t *)spapr->htab; 1178 if (kvm_enabled() && !env->external_htab) { 1179 /* 1180 * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte* 1181 * functions do the right thing. 1182 */ 1183 env->external_htab = (void *)1; 1184 } 1185 env->htab_base = -1; 1186 /* 1187 * htab_mask is the mask used to normalize hash value to PTEG index. 1188 * htab_shift is log2 of hash table size. 1189 * We have 8 hpte per group, and each hpte is 16 bytes. 1190 * ie have 128 bytes per hpte entry. 1191 */ 1192 env->htab_mask = (1ULL << (spapr->htab_shift - 7)) - 1; 1193 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | 1194 (spapr->htab_shift - 18); 1195 } 1196 1197 static void spapr_create_nvram(sPAPRMachineState *spapr) 1198 { 1199 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1200 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1201 1202 if (dinfo) { 1203 qdev_prop_set_drive_nofail(dev, "drive", blk_by_legacy_dinfo(dinfo)); 1204 } 1205 1206 qdev_init_nofail(dev); 1207 1208 spapr->nvram = (struct sPAPRNVRAM *)dev; 1209 } 1210 1211 static void spapr_rtc_create(sPAPRMachineState *spapr) 1212 { 1213 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC); 1214 1215 qdev_init_nofail(dev); 1216 spapr->rtc = dev; 1217 1218 object_property_add_alias(qdev_get_machine(), "rtc-time", 1219 OBJECT(spapr->rtc), "date", NULL); 1220 } 1221 1222 /* Returns whether we want to use VGA or not */ 1223 static int spapr_vga_init(PCIBus *pci_bus) 1224 { 1225 switch (vga_interface_type) { 1226 case VGA_NONE: 1227 return false; 1228 case VGA_DEVICE: 1229 return true; 1230 case VGA_STD: 1231 case VGA_VIRTIO: 1232 return pci_vga_init(pci_bus) != NULL; 1233 default: 1234 fprintf(stderr, "This vga model is not supported," 1235 "currently it only supports -vga std\n"); 1236 exit(0); 1237 } 1238 } 1239 1240 static int spapr_post_load(void *opaque, int version_id) 1241 { 1242 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1243 int err = 0; 1244 1245 /* In earlier versions, there was no separate qdev for the PAPR 1246 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1247 * So when migrating from those versions, poke the incoming offset 1248 * value into the RTC device */ 1249 if (version_id < 3) { 1250 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset); 1251 } 1252 1253 return err; 1254 } 1255 1256 static bool version_before_3(void *opaque, int version_id) 1257 { 1258 return version_id < 3; 1259 } 1260 1261 static const VMStateDescription vmstate_spapr = { 1262 .name = "spapr", 1263 .version_id = 3, 1264 .minimum_version_id = 1, 1265 .post_load = spapr_post_load, 1266 .fields = (VMStateField[]) { 1267 /* used to be @next_irq */ 1268 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1269 1270 /* RTC offset */ 1271 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1272 1273 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1274 VMSTATE_END_OF_LIST() 1275 }, 1276 }; 1277 1278 static int htab_save_setup(QEMUFile *f, void *opaque) 1279 { 1280 sPAPRMachineState *spapr = opaque; 1281 1282 /* "Iteration" header */ 1283 qemu_put_be32(f, spapr->htab_shift); 1284 1285 if (spapr->htab) { 1286 spapr->htab_save_index = 0; 1287 spapr->htab_first_pass = true; 1288 } else { 1289 assert(kvm_enabled()); 1290 1291 spapr->htab_fd = kvmppc_get_htab_fd(false); 1292 spapr->htab_fd_stale = false; 1293 if (spapr->htab_fd < 0) { 1294 fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n", 1295 strerror(errno)); 1296 return -1; 1297 } 1298 } 1299 1300 1301 return 0; 1302 } 1303 1304 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1305 int64_t max_ns) 1306 { 1307 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1308 int index = spapr->htab_save_index; 1309 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1310 1311 assert(spapr->htab_first_pass); 1312 1313 do { 1314 int chunkstart; 1315 1316 /* Consume invalid HPTEs */ 1317 while ((index < htabslots) 1318 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1319 index++; 1320 CLEAN_HPTE(HPTE(spapr->htab, index)); 1321 } 1322 1323 /* Consume valid HPTEs */ 1324 chunkstart = index; 1325 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1326 && HPTE_VALID(HPTE(spapr->htab, index))) { 1327 index++; 1328 CLEAN_HPTE(HPTE(spapr->htab, index)); 1329 } 1330 1331 if (index > chunkstart) { 1332 int n_valid = index - chunkstart; 1333 1334 qemu_put_be32(f, chunkstart); 1335 qemu_put_be16(f, n_valid); 1336 qemu_put_be16(f, 0); 1337 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1338 HASH_PTE_SIZE_64 * n_valid); 1339 1340 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1341 break; 1342 } 1343 } 1344 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1345 1346 if (index >= htabslots) { 1347 assert(index == htabslots); 1348 index = 0; 1349 spapr->htab_first_pass = false; 1350 } 1351 spapr->htab_save_index = index; 1352 } 1353 1354 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1355 int64_t max_ns) 1356 { 1357 bool final = max_ns < 0; 1358 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1359 int examined = 0, sent = 0; 1360 int index = spapr->htab_save_index; 1361 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1362 1363 assert(!spapr->htab_first_pass); 1364 1365 do { 1366 int chunkstart, invalidstart; 1367 1368 /* Consume non-dirty HPTEs */ 1369 while ((index < htabslots) 1370 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1371 index++; 1372 examined++; 1373 } 1374 1375 chunkstart = index; 1376 /* Consume valid dirty HPTEs */ 1377 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1378 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1379 && HPTE_VALID(HPTE(spapr->htab, index))) { 1380 CLEAN_HPTE(HPTE(spapr->htab, index)); 1381 index++; 1382 examined++; 1383 } 1384 1385 invalidstart = index; 1386 /* Consume invalid dirty HPTEs */ 1387 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1388 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1389 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1390 CLEAN_HPTE(HPTE(spapr->htab, index)); 1391 index++; 1392 examined++; 1393 } 1394 1395 if (index > chunkstart) { 1396 int n_valid = invalidstart - chunkstart; 1397 int n_invalid = index - invalidstart; 1398 1399 qemu_put_be32(f, chunkstart); 1400 qemu_put_be16(f, n_valid); 1401 qemu_put_be16(f, n_invalid); 1402 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1403 HASH_PTE_SIZE_64 * n_valid); 1404 sent += index - chunkstart; 1405 1406 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1407 break; 1408 } 1409 } 1410 1411 if (examined >= htabslots) { 1412 break; 1413 } 1414 1415 if (index >= htabslots) { 1416 assert(index == htabslots); 1417 index = 0; 1418 } 1419 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1420 1421 if (index >= htabslots) { 1422 assert(index == htabslots); 1423 index = 0; 1424 } 1425 1426 spapr->htab_save_index = index; 1427 1428 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1429 } 1430 1431 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1432 #define MAX_KVM_BUF_SIZE 2048 1433 1434 static int htab_save_iterate(QEMUFile *f, void *opaque) 1435 { 1436 sPAPRMachineState *spapr = opaque; 1437 int rc = 0; 1438 1439 /* Iteration header */ 1440 qemu_put_be32(f, 0); 1441 1442 if (!spapr->htab) { 1443 assert(kvm_enabled()); 1444 1445 rc = spapr_check_htab_fd(spapr); 1446 if (rc < 0) { 1447 return rc; 1448 } 1449 1450 rc = kvmppc_save_htab(f, spapr->htab_fd, 1451 MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1452 if (rc < 0) { 1453 return rc; 1454 } 1455 } else if (spapr->htab_first_pass) { 1456 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1457 } else { 1458 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1459 } 1460 1461 /* End marker */ 1462 qemu_put_be32(f, 0); 1463 qemu_put_be16(f, 0); 1464 qemu_put_be16(f, 0); 1465 1466 return rc; 1467 } 1468 1469 static int htab_save_complete(QEMUFile *f, void *opaque) 1470 { 1471 sPAPRMachineState *spapr = opaque; 1472 1473 /* Iteration header */ 1474 qemu_put_be32(f, 0); 1475 1476 if (!spapr->htab) { 1477 int rc; 1478 1479 assert(kvm_enabled()); 1480 1481 rc = spapr_check_htab_fd(spapr); 1482 if (rc < 0) { 1483 return rc; 1484 } 1485 1486 rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1); 1487 if (rc < 0) { 1488 return rc; 1489 } 1490 close(spapr->htab_fd); 1491 spapr->htab_fd = -1; 1492 } else { 1493 htab_save_later_pass(f, spapr, -1); 1494 } 1495 1496 /* End marker */ 1497 qemu_put_be32(f, 0); 1498 qemu_put_be16(f, 0); 1499 qemu_put_be16(f, 0); 1500 1501 return 0; 1502 } 1503 1504 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1505 { 1506 sPAPRMachineState *spapr = opaque; 1507 uint32_t section_hdr; 1508 int fd = -1; 1509 1510 if (version_id < 1 || version_id > 1) { 1511 fprintf(stderr, "htab_load() bad version\n"); 1512 return -EINVAL; 1513 } 1514 1515 section_hdr = qemu_get_be32(f); 1516 1517 if (section_hdr) { 1518 /* First section, just the hash shift */ 1519 if (spapr->htab_shift != section_hdr) { 1520 error_report("htab_shift mismatch: source %d target %d", 1521 section_hdr, spapr->htab_shift); 1522 return -EINVAL; 1523 } 1524 return 0; 1525 } 1526 1527 if (!spapr->htab) { 1528 assert(kvm_enabled()); 1529 1530 fd = kvmppc_get_htab_fd(true); 1531 if (fd < 0) { 1532 fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n", 1533 strerror(errno)); 1534 } 1535 } 1536 1537 while (true) { 1538 uint32_t index; 1539 uint16_t n_valid, n_invalid; 1540 1541 index = qemu_get_be32(f); 1542 n_valid = qemu_get_be16(f); 1543 n_invalid = qemu_get_be16(f); 1544 1545 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1546 /* End of Stream */ 1547 break; 1548 } 1549 1550 if ((index + n_valid + n_invalid) > 1551 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1552 /* Bad index in stream */ 1553 fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) " 1554 "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid, 1555 spapr->htab_shift); 1556 return -EINVAL; 1557 } 1558 1559 if (spapr->htab) { 1560 if (n_valid) { 1561 qemu_get_buffer(f, HPTE(spapr->htab, index), 1562 HASH_PTE_SIZE_64 * n_valid); 1563 } 1564 if (n_invalid) { 1565 memset(HPTE(spapr->htab, index + n_valid), 0, 1566 HASH_PTE_SIZE_64 * n_invalid); 1567 } 1568 } else { 1569 int rc; 1570 1571 assert(fd >= 0); 1572 1573 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1574 if (rc < 0) { 1575 return rc; 1576 } 1577 } 1578 } 1579 1580 if (!spapr->htab) { 1581 assert(fd >= 0); 1582 close(fd); 1583 } 1584 1585 return 0; 1586 } 1587 1588 static SaveVMHandlers savevm_htab_handlers = { 1589 .save_live_setup = htab_save_setup, 1590 .save_live_iterate = htab_save_iterate, 1591 .save_live_complete = htab_save_complete, 1592 .load_state = htab_load, 1593 }; 1594 1595 static void spapr_boot_set(void *opaque, const char *boot_device, 1596 Error **errp) 1597 { 1598 MachineState *machine = MACHINE(qdev_get_machine()); 1599 machine->boot_order = g_strdup(boot_device); 1600 } 1601 1602 static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu) 1603 { 1604 CPUPPCState *env = &cpu->env; 1605 1606 /* Set time-base frequency to 512 MHz */ 1607 cpu_ppc_tb_init(env, TIMEBASE_FREQ); 1608 1609 /* PAPR always has exception vectors in RAM not ROM. To ensure this, 1610 * MSR[IP] should never be set. 1611 */ 1612 env->msr_mask &= ~(1 << 6); 1613 1614 /* Tell KVM that we're in PAPR mode */ 1615 if (kvm_enabled()) { 1616 kvmppc_set_papr(cpu); 1617 } 1618 1619 if (cpu->max_compat) { 1620 if (ppc_set_compat(cpu, cpu->max_compat) < 0) { 1621 exit(1); 1622 } 1623 } 1624 1625 xics_cpu_setup(spapr->icp, cpu); 1626 1627 qemu_register_reset(spapr_cpu_reset, cpu); 1628 } 1629 1630 /* 1631 * Reset routine for LMB DR devices. 1632 * 1633 * Unlike PCI DR devices, LMB DR devices explicitly register this reset 1634 * routine. Reset for PCI DR devices will be handled by PHB reset routine 1635 * when it walks all its children devices. LMB devices reset occurs 1636 * as part of spapr_ppc_reset(). 1637 */ 1638 static void spapr_drc_reset(void *opaque) 1639 { 1640 sPAPRDRConnector *drc = opaque; 1641 DeviceState *d = DEVICE(drc); 1642 1643 if (d) { 1644 device_reset(d); 1645 } 1646 } 1647 1648 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 1649 { 1650 MachineState *machine = MACHINE(spapr); 1651 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 1652 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 1653 int i; 1654 1655 for (i = 0; i < nr_lmbs; i++) { 1656 sPAPRDRConnector *drc; 1657 uint64_t addr; 1658 1659 addr = i * lmb_size + spapr->hotplug_memory.base; 1660 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB, 1661 addr/lmb_size); 1662 qemu_register_reset(spapr_drc_reset, drc); 1663 } 1664 } 1665 1666 /* 1667 * If RAM size, maxmem size and individual node mem sizes aren't aligned 1668 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 1669 * since we can't support such unaligned sizes with DRCONF_MEMORY. 1670 */ 1671 static void spapr_validate_node_memory(MachineState *machine) 1672 { 1673 int i; 1674 1675 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE || 1676 machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1677 error_report("Can't support memory configuration where RAM size " 1678 "0x" RAM_ADDR_FMT " or maxmem size " 1679 "0x" RAM_ADDR_FMT " isn't aligned to %llu MB", 1680 machine->ram_size, machine->maxram_size, 1681 SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); 1682 exit(EXIT_FAILURE); 1683 } 1684 1685 for (i = 0; i < nb_numa_nodes; i++) { 1686 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 1687 error_report("Can't support memory configuration where memory size" 1688 " %" PRIx64 " of node %d isn't aligned to %llu MB", 1689 numa_info[i].node_mem, i, 1690 SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); 1691 exit(EXIT_FAILURE); 1692 } 1693 } 1694 } 1695 1696 /* pSeries LPAR / sPAPR hardware init */ 1697 static void ppc_spapr_init(MachineState *machine) 1698 { 1699 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1700 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1701 const char *kernel_filename = machine->kernel_filename; 1702 const char *kernel_cmdline = machine->kernel_cmdline; 1703 const char *initrd_filename = machine->initrd_filename; 1704 PowerPCCPU *cpu; 1705 PCIHostState *phb; 1706 int i; 1707 MemoryRegion *sysmem = get_system_memory(); 1708 MemoryRegion *ram = g_new(MemoryRegion, 1); 1709 MemoryRegion *rma_region; 1710 void *rma = NULL; 1711 hwaddr rma_alloc_size; 1712 hwaddr node0_size = spapr_node0_size(); 1713 uint32_t initrd_base = 0; 1714 long kernel_size = 0, initrd_size = 0; 1715 long load_limit, fw_size; 1716 bool kernel_le = false; 1717 char *filename; 1718 1719 msi_supported = true; 1720 1721 QLIST_INIT(&spapr->phbs); 1722 1723 cpu_ppc_hypercall = emulate_spapr_hypercall; 1724 1725 /* Allocate RMA if necessary */ 1726 rma_alloc_size = kvmppc_alloc_rma(&rma); 1727 1728 if (rma_alloc_size == -1) { 1729 error_report("Unable to create RMA"); 1730 exit(1); 1731 } 1732 1733 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1734 spapr->rma_size = rma_alloc_size; 1735 } else { 1736 spapr->rma_size = node0_size; 1737 1738 /* With KVM, we don't actually know whether KVM supports an 1739 * unbounded RMA (PR KVM) or is limited by the hash table size 1740 * (HV KVM using VRMA), so we always assume the latter 1741 * 1742 * In that case, we also limit the initial allocations for RTAS 1743 * etc... to 256M since we have no way to know what the VRMA size 1744 * is going to be as it depends on the size of the hash table 1745 * isn't determined yet. 1746 */ 1747 if (kvm_enabled()) { 1748 spapr->vrma_adjust = 1; 1749 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1750 } 1751 } 1752 1753 if (spapr->rma_size > node0_size) { 1754 fprintf(stderr, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")\n", 1755 spapr->rma_size); 1756 exit(1); 1757 } 1758 1759 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 1760 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 1761 1762 /* We aim for a hash table of size 1/128 the size of RAM. The 1763 * normal rule of thumb is 1/64 the size of RAM, but that's much 1764 * more than needed for the Linux guests we support. */ 1765 spapr->htab_shift = 18; /* Minimum architected size */ 1766 while (spapr->htab_shift <= 46) { 1767 if ((1ULL << (spapr->htab_shift + 7)) >= machine->maxram_size) { 1768 break; 1769 } 1770 spapr->htab_shift++; 1771 } 1772 spapr_alloc_htab(spapr); 1773 1774 /* Set up Interrupt Controller before we create the VCPUs */ 1775 spapr->icp = xics_system_init(machine, 1776 DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(), 1777 smp_threads), 1778 XICS_IRQS); 1779 1780 if (smc->dr_lmb_enabled) { 1781 spapr_validate_node_memory(machine); 1782 } 1783 1784 /* init CPUs */ 1785 if (machine->cpu_model == NULL) { 1786 machine->cpu_model = kvm_enabled() ? "host" : "POWER7"; 1787 } 1788 for (i = 0; i < smp_cpus; i++) { 1789 cpu = cpu_ppc_init(machine->cpu_model); 1790 if (cpu == NULL) { 1791 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 1792 exit(1); 1793 } 1794 spapr_cpu_init(spapr, cpu); 1795 } 1796 1797 if (kvm_enabled()) { 1798 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 1799 kvmppc_enable_logical_ci_hcalls(); 1800 kvmppc_enable_set_mode_hcall(); 1801 } 1802 1803 /* allocate RAM */ 1804 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 1805 machine->ram_size); 1806 memory_region_add_subregion(sysmem, 0, ram); 1807 1808 if (rma_alloc_size && rma) { 1809 rma_region = g_new(MemoryRegion, 1); 1810 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 1811 rma_alloc_size, rma); 1812 vmstate_register_ram_global(rma_region); 1813 memory_region_add_subregion(sysmem, 0, rma_region); 1814 } 1815 1816 /* initialize hotplug memory address space */ 1817 if (machine->ram_size < machine->maxram_size) { 1818 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 1819 1820 if (machine->ram_slots > SPAPR_MAX_RAM_SLOTS) { 1821 error_report("Specified number of memory slots %"PRIu64" exceeds max supported %d\n", 1822 machine->ram_slots, SPAPR_MAX_RAM_SLOTS); 1823 exit(EXIT_FAILURE); 1824 } 1825 1826 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 1827 SPAPR_HOTPLUG_MEM_ALIGN); 1828 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 1829 "hotplug-memory", hotplug_mem_size); 1830 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 1831 &spapr->hotplug_memory.mr); 1832 } 1833 1834 if (smc->dr_lmb_enabled) { 1835 spapr_create_lmb_dr_connectors(spapr); 1836 } 1837 1838 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 1839 if (!filename) { 1840 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 1841 exit(1); 1842 } 1843 spapr->rtas_size = get_image_size(filename); 1844 spapr->rtas_blob = g_malloc(spapr->rtas_size); 1845 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 1846 error_report("Could not load LPAR rtas '%s'", filename); 1847 exit(1); 1848 } 1849 if (spapr->rtas_size > RTAS_MAX_SIZE) { 1850 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 1851 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 1852 exit(1); 1853 } 1854 g_free(filename); 1855 1856 /* Set up EPOW events infrastructure */ 1857 spapr_events_init(spapr); 1858 1859 /* Set up the RTC RTAS interfaces */ 1860 spapr_rtc_create(spapr); 1861 1862 /* Set up VIO bus */ 1863 spapr->vio_bus = spapr_vio_bus_init(); 1864 1865 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 1866 if (serial_hds[i]) { 1867 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 1868 } 1869 } 1870 1871 /* We always have at least the nvram device on VIO */ 1872 spapr_create_nvram(spapr); 1873 1874 /* Set up PCI */ 1875 spapr_pci_rtas_init(); 1876 1877 phb = spapr_create_phb(spapr, 0); 1878 1879 for (i = 0; i < nb_nics; i++) { 1880 NICInfo *nd = &nd_table[i]; 1881 1882 if (!nd->model) { 1883 nd->model = g_strdup("ibmveth"); 1884 } 1885 1886 if (strcmp(nd->model, "ibmveth") == 0) { 1887 spapr_vlan_create(spapr->vio_bus, nd); 1888 } else { 1889 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 1890 } 1891 } 1892 1893 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 1894 spapr_vscsi_create(spapr->vio_bus); 1895 } 1896 1897 /* Graphics */ 1898 if (spapr_vga_init(phb->bus)) { 1899 spapr->has_graphics = true; 1900 machine->usb |= defaults_enabled() && !machine->usb_disabled; 1901 } 1902 1903 if (machine->usb) { 1904 pci_create_simple(phb->bus, -1, "pci-ohci"); 1905 1906 if (spapr->has_graphics) { 1907 USBBus *usb_bus = usb_bus_find(-1); 1908 1909 usb_create_simple(usb_bus, "usb-kbd"); 1910 usb_create_simple(usb_bus, "usb-mouse"); 1911 } 1912 } 1913 1914 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 1915 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= " 1916 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF); 1917 exit(1); 1918 } 1919 1920 if (kernel_filename) { 1921 uint64_t lowaddr = 0; 1922 1923 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 1924 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 0); 1925 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) { 1926 kernel_size = load_elf(kernel_filename, 1927 translate_kernel_address, NULL, 1928 NULL, &lowaddr, NULL, 0, PPC_ELF_MACHINE, 0); 1929 kernel_le = kernel_size > 0; 1930 } 1931 if (kernel_size < 0) { 1932 fprintf(stderr, "qemu: error loading %s: %s\n", 1933 kernel_filename, load_elf_strerror(kernel_size)); 1934 exit(1); 1935 } 1936 1937 /* load initrd */ 1938 if (initrd_filename) { 1939 /* Try to locate the initrd in the gap between the kernel 1940 * and the firmware. Add a bit of space just in case 1941 */ 1942 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; 1943 initrd_size = load_image_targphys(initrd_filename, initrd_base, 1944 load_limit - initrd_base); 1945 if (initrd_size < 0) { 1946 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 1947 initrd_filename); 1948 exit(1); 1949 } 1950 } else { 1951 initrd_base = 0; 1952 initrd_size = 0; 1953 } 1954 } 1955 1956 if (bios_name == NULL) { 1957 bios_name = FW_FILE_NAME; 1958 } 1959 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1960 if (!filename) { 1961 error_report("Could not find LPAR firmware '%s'", bios_name); 1962 exit(1); 1963 } 1964 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 1965 if (fw_size <= 0) { 1966 error_report("Could not load LPAR firmware '%s'", filename); 1967 exit(1); 1968 } 1969 g_free(filename); 1970 1971 /* FIXME: Should register things through the MachineState's qdev 1972 * interface, this is a legacy from the sPAPREnvironment structure 1973 * which predated MachineState but had a similar function */ 1974 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 1975 register_savevm_live(NULL, "spapr/htab", -1, 1, 1976 &savevm_htab_handlers, spapr); 1977 1978 /* Prepare the device tree */ 1979 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, 1980 kernel_size, kernel_le, 1981 kernel_cmdline, 1982 spapr->check_exception_irq); 1983 assert(spapr->fdt_skel != NULL); 1984 1985 /* used by RTAS */ 1986 QTAILQ_INIT(&spapr->ccs_list); 1987 qemu_register_reset(spapr_ccs_reset_hook, spapr); 1988 1989 qemu_register_boot_set(spapr_boot_set, spapr); 1990 } 1991 1992 static int spapr_kvm_type(const char *vm_type) 1993 { 1994 if (!vm_type) { 1995 return 0; 1996 } 1997 1998 if (!strcmp(vm_type, "HV")) { 1999 return 1; 2000 } 2001 2002 if (!strcmp(vm_type, "PR")) { 2003 return 2; 2004 } 2005 2006 error_report("Unknown kvm-type specified '%s'", vm_type); 2007 exit(1); 2008 } 2009 2010 /* 2011 * Implementation of an interface to adjust firmware path 2012 * for the bootindex property handling. 2013 */ 2014 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2015 DeviceState *dev) 2016 { 2017 #define CAST(type, obj, name) \ 2018 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2019 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2020 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2021 2022 if (d) { 2023 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2024 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2025 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2026 2027 if (spapr) { 2028 /* 2029 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2030 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2031 * in the top 16 bits of the 64-bit LUN 2032 */ 2033 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2034 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2035 (uint64_t)id << 48); 2036 } else if (virtio) { 2037 /* 2038 * We use SRP luns of the form 01000000 | (target << 8) | lun 2039 * in the top 32 bits of the 64-bit LUN 2040 * Note: the quote above is from SLOF and it is wrong, 2041 * the actual binding is: 2042 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2043 */ 2044 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2045 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2046 (uint64_t)id << 32); 2047 } else if (usb) { 2048 /* 2049 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2050 * in the top 32 bits of the 64-bit LUN 2051 */ 2052 unsigned usb_port = atoi(usb->port->path); 2053 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2054 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2055 (uint64_t)id << 32); 2056 } 2057 } 2058 2059 if (phb) { 2060 /* Replace "pci" with "pci@800000020000000" */ 2061 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2062 } 2063 2064 return NULL; 2065 } 2066 2067 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2068 { 2069 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2070 2071 return g_strdup(spapr->kvm_type); 2072 } 2073 2074 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2075 { 2076 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2077 2078 g_free(spapr->kvm_type); 2079 spapr->kvm_type = g_strdup(value); 2080 } 2081 2082 static void spapr_machine_initfn(Object *obj) 2083 { 2084 object_property_add_str(obj, "kvm-type", 2085 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2086 object_property_set_description(obj, "kvm-type", 2087 "Specifies the KVM virtualization mode (HV, PR)", 2088 NULL); 2089 } 2090 2091 static void ppc_cpu_do_nmi_on_cpu(void *arg) 2092 { 2093 CPUState *cs = arg; 2094 2095 cpu_synchronize_state(cs); 2096 ppc_cpu_do_system_reset(cs); 2097 } 2098 2099 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2100 { 2101 CPUState *cs; 2102 2103 CPU_FOREACH(cs) { 2104 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs); 2105 } 2106 } 2107 2108 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size, 2109 uint32_t node, Error **errp) 2110 { 2111 sPAPRDRConnector *drc; 2112 sPAPRDRConnectorClass *drck; 2113 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2114 int i, fdt_offset, fdt_size; 2115 void *fdt; 2116 2117 /* 2118 * Check for DRC connectors and send hotplug notification to the 2119 * guest only in case of hotplugged memory. This allows cold plugged 2120 * memory to be specified at boot time. 2121 */ 2122 if (!dev->hotplugged) { 2123 return; 2124 } 2125 2126 for (i = 0; i < nr_lmbs; i++) { 2127 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2128 addr/SPAPR_MEMORY_BLOCK_SIZE); 2129 g_assert(drc); 2130 2131 fdt = create_device_tree(&fdt_size); 2132 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2133 SPAPR_MEMORY_BLOCK_SIZE); 2134 2135 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2136 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); 2137 addr += SPAPR_MEMORY_BLOCK_SIZE; 2138 } 2139 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs); 2140 } 2141 2142 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2143 uint32_t node, Error **errp) 2144 { 2145 Error *local_err = NULL; 2146 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2147 PCDIMMDevice *dimm = PC_DIMM(dev); 2148 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2149 MemoryRegion *mr = ddc->get_memory_region(dimm); 2150 uint64_t align = memory_region_get_alignment(mr); 2151 uint64_t size = memory_region_size(mr); 2152 uint64_t addr; 2153 2154 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 2155 error_setg(&local_err, "Hotplugged memory size must be a multiple of " 2156 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); 2157 goto out; 2158 } 2159 2160 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 2161 if (local_err) { 2162 goto out; 2163 } 2164 2165 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2166 if (local_err) { 2167 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2168 goto out; 2169 } 2170 2171 spapr_add_lmbs(dev, addr, size, node, &error_abort); 2172 2173 out: 2174 error_propagate(errp, local_err); 2175 } 2176 2177 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 2178 DeviceState *dev, Error **errp) 2179 { 2180 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 2181 2182 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2183 int node; 2184 2185 if (!smc->dr_lmb_enabled) { 2186 error_setg(errp, "Memory hotplug not supported for this machine"); 2187 return; 2188 } 2189 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 2190 if (*errp) { 2191 return; 2192 } 2193 2194 /* 2195 * Currently PowerPC kernel doesn't allow hot-adding memory to 2196 * memory-less node, but instead will silently add the memory 2197 * to the first node that has some memory. This causes two 2198 * unexpected behaviours for the user. 2199 * 2200 * - Memory gets hotplugged to a different node than what the user 2201 * specified. 2202 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 2203 * to memory-less node, a reboot will set things accordingly 2204 * and the previously hotplugged memory now ends in the right node. 2205 * This appears as if some memory moved from one node to another. 2206 * 2207 * So until kernel starts supporting memory hotplug to memory-less 2208 * nodes, just prevent such attempts upfront in QEMU. 2209 */ 2210 if (nb_numa_nodes && !numa_info[node].node_mem) { 2211 error_setg(errp, "Can't hotplug memory to memory-less node %d", 2212 node); 2213 return; 2214 } 2215 2216 spapr_memory_plug(hotplug_dev, dev, node, errp); 2217 } 2218 } 2219 2220 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 2221 DeviceState *dev, Error **errp) 2222 { 2223 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2224 error_setg(errp, "Memory hot unplug not supported by sPAPR"); 2225 } 2226 } 2227 2228 static HotplugHandler *spapr_get_hotpug_handler(MachineState *machine, 2229 DeviceState *dev) 2230 { 2231 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2232 return HOTPLUG_HANDLER(machine); 2233 } 2234 return NULL; 2235 } 2236 2237 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index) 2238 { 2239 /* Allocate to NUMA nodes on a "socket" basis (not that concept of 2240 * socket means much for the paravirtualized PAPR platform) */ 2241 return cpu_index / smp_threads / smp_cores; 2242 } 2243 2244 static void spapr_machine_class_init(ObjectClass *oc, void *data) 2245 { 2246 MachineClass *mc = MACHINE_CLASS(oc); 2247 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 2248 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 2249 NMIClass *nc = NMI_CLASS(oc); 2250 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2251 2252 mc->init = ppc_spapr_init; 2253 mc->reset = ppc_spapr_reset; 2254 mc->block_default_type = IF_SCSI; 2255 mc->max_cpus = MAX_CPUMASK_BITS; 2256 mc->no_parallel = 1; 2257 mc->default_boot_order = ""; 2258 mc->default_ram_size = 512 * M_BYTE; 2259 mc->kvm_type = spapr_kvm_type; 2260 mc->has_dynamic_sysbus = true; 2261 mc->pci_allow_0_address = true; 2262 mc->get_hotplug_handler = spapr_get_hotpug_handler; 2263 hc->plug = spapr_machine_device_plug; 2264 hc->unplug = spapr_machine_device_unplug; 2265 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id; 2266 2267 smc->dr_lmb_enabled = false; 2268 fwc->get_dev_path = spapr_get_fw_dev_path; 2269 nc->nmi_monitor_handler = spapr_nmi; 2270 } 2271 2272 static const TypeInfo spapr_machine_info = { 2273 .name = TYPE_SPAPR_MACHINE, 2274 .parent = TYPE_MACHINE, 2275 .abstract = true, 2276 .instance_size = sizeof(sPAPRMachineState), 2277 .instance_init = spapr_machine_initfn, 2278 .class_size = sizeof(sPAPRMachineClass), 2279 .class_init = spapr_machine_class_init, 2280 .interfaces = (InterfaceInfo[]) { 2281 { TYPE_FW_PATH_PROVIDER }, 2282 { TYPE_NMI }, 2283 { TYPE_HOTPLUG_HANDLER }, 2284 { } 2285 }, 2286 }; 2287 2288 #define SPAPR_COMPAT_2_4 \ 2289 HW_COMPAT_2_4 2290 2291 #define SPAPR_COMPAT_2_3 \ 2292 SPAPR_COMPAT_2_4 \ 2293 HW_COMPAT_2_3 \ 2294 {\ 2295 .driver = "spapr-pci-host-bridge",\ 2296 .property = "dynamic-reconfiguration",\ 2297 .value = "off",\ 2298 }, 2299 2300 #define SPAPR_COMPAT_2_2 \ 2301 SPAPR_COMPAT_2_3 \ 2302 HW_COMPAT_2_2 \ 2303 {\ 2304 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 2305 .property = "mem_win_size",\ 2306 .value = "0x20000000",\ 2307 }, 2308 2309 #define SPAPR_COMPAT_2_1 \ 2310 SPAPR_COMPAT_2_2 \ 2311 HW_COMPAT_2_1 2312 2313 static void spapr_compat_2_3(Object *obj) 2314 { 2315 savevm_skip_section_footers(); 2316 global_state_set_optional(); 2317 } 2318 2319 static void spapr_compat_2_2(Object *obj) 2320 { 2321 spapr_compat_2_3(obj); 2322 } 2323 2324 static void spapr_compat_2_1(Object *obj) 2325 { 2326 spapr_compat_2_2(obj); 2327 } 2328 2329 static void spapr_machine_2_3_instance_init(Object *obj) 2330 { 2331 spapr_compat_2_3(obj); 2332 spapr_machine_initfn(obj); 2333 } 2334 2335 static void spapr_machine_2_2_instance_init(Object *obj) 2336 { 2337 spapr_compat_2_2(obj); 2338 spapr_machine_initfn(obj); 2339 } 2340 2341 static void spapr_machine_2_1_instance_init(Object *obj) 2342 { 2343 spapr_compat_2_1(obj); 2344 spapr_machine_initfn(obj); 2345 } 2346 2347 static void spapr_machine_2_1_class_init(ObjectClass *oc, void *data) 2348 { 2349 MachineClass *mc = MACHINE_CLASS(oc); 2350 static GlobalProperty compat_props[] = { 2351 SPAPR_COMPAT_2_1 2352 { /* end of list */ } 2353 }; 2354 2355 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.1"; 2356 mc->compat_props = compat_props; 2357 } 2358 2359 static const TypeInfo spapr_machine_2_1_info = { 2360 .name = MACHINE_TYPE_NAME("pseries-2.1"), 2361 .parent = TYPE_SPAPR_MACHINE, 2362 .class_init = spapr_machine_2_1_class_init, 2363 .instance_init = spapr_machine_2_1_instance_init, 2364 }; 2365 2366 static void spapr_machine_2_2_class_init(ObjectClass *oc, void *data) 2367 { 2368 static GlobalProperty compat_props[] = { 2369 SPAPR_COMPAT_2_2 2370 { /* end of list */ } 2371 }; 2372 MachineClass *mc = MACHINE_CLASS(oc); 2373 2374 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.2"; 2375 mc->compat_props = compat_props; 2376 } 2377 2378 static const TypeInfo spapr_machine_2_2_info = { 2379 .name = MACHINE_TYPE_NAME("pseries-2.2"), 2380 .parent = TYPE_SPAPR_MACHINE, 2381 .class_init = spapr_machine_2_2_class_init, 2382 .instance_init = spapr_machine_2_2_instance_init, 2383 }; 2384 2385 static void spapr_machine_2_3_class_init(ObjectClass *oc, void *data) 2386 { 2387 static GlobalProperty compat_props[] = { 2388 SPAPR_COMPAT_2_3 2389 { /* end of list */ } 2390 }; 2391 MachineClass *mc = MACHINE_CLASS(oc); 2392 2393 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.3"; 2394 mc->compat_props = compat_props; 2395 } 2396 2397 static const TypeInfo spapr_machine_2_3_info = { 2398 .name = MACHINE_TYPE_NAME("pseries-2.3"), 2399 .parent = TYPE_SPAPR_MACHINE, 2400 .class_init = spapr_machine_2_3_class_init, 2401 .instance_init = spapr_machine_2_3_instance_init, 2402 }; 2403 2404 static void spapr_machine_2_4_class_init(ObjectClass *oc, void *data) 2405 { 2406 static GlobalProperty compat_props[] = { 2407 SPAPR_COMPAT_2_4 2408 { /* end of list */ } 2409 }; 2410 MachineClass *mc = MACHINE_CLASS(oc); 2411 2412 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.4"; 2413 mc->alias = "pseries"; 2414 mc->is_default = 0; 2415 mc->compat_props = compat_props; 2416 } 2417 2418 static const TypeInfo spapr_machine_2_4_info = { 2419 .name = MACHINE_TYPE_NAME("pseries-2.4"), 2420 .parent = TYPE_SPAPR_MACHINE, 2421 .class_init = spapr_machine_2_4_class_init, 2422 }; 2423 2424 static void spapr_machine_2_5_class_init(ObjectClass *oc, void *data) 2425 { 2426 MachineClass *mc = MACHINE_CLASS(oc); 2427 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 2428 2429 mc->name = "pseries-2.5"; 2430 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.5"; 2431 mc->alias = "pseries"; 2432 mc->is_default = 1; 2433 smc->dr_lmb_enabled = true; 2434 } 2435 2436 static const TypeInfo spapr_machine_2_5_info = { 2437 .name = MACHINE_TYPE_NAME("pseries-2.5"), 2438 .parent = TYPE_SPAPR_MACHINE, 2439 .class_init = spapr_machine_2_5_class_init, 2440 }; 2441 2442 static void spapr_machine_register_types(void) 2443 { 2444 type_register_static(&spapr_machine_info); 2445 type_register_static(&spapr_machine_2_1_info); 2446 type_register_static(&spapr_machine_2_2_info); 2447 type_register_static(&spapr_machine_2_3_info); 2448 type_register_static(&spapr_machine_2_4_info); 2449 type_register_static(&spapr_machine_2_5_info); 2450 } 2451 2452 type_init(spapr_machine_register_types) 2453