1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "sysemu/sysemu.h" 28 #include "hw/hw.h" 29 #include "elf.h" 30 #include "net/net.h" 31 #include "sysemu/blockdev.h" 32 #include "sysemu/cpus.h" 33 #include "sysemu/kvm.h" 34 #include "kvm_ppc.h" 35 #include "mmu-hash64.h" 36 37 #include "hw/boards.h" 38 #include "hw/ppc/ppc.h" 39 #include "hw/loader.h" 40 41 #include "hw/ppc/spapr.h" 42 #include "hw/ppc/spapr_vio.h" 43 #include "hw/pci-host/spapr.h" 44 #include "hw/ppc/xics.h" 45 #include "hw/pci/msi.h" 46 47 #include "hw/pci/pci.h" 48 49 #include "exec/address-spaces.h" 50 #include "hw/usb.h" 51 #include "qemu/config-file.h" 52 53 #include <libfdt.h> 54 55 /* SLOF memory layout: 56 * 57 * SLOF raw image loaded at 0, copies its romfs right below the flat 58 * device-tree, then position SLOF itself 31M below that 59 * 60 * So we set FW_OVERHEAD to 40MB which should account for all of that 61 * and more 62 * 63 * We load our kernel at 4M, leaving space for SLOF initial image 64 */ 65 #define FDT_MAX_SIZE 0x40000 66 #define RTAS_MAX_SIZE 0x10000 67 #define FW_MAX_SIZE 0x400000 68 #define FW_FILE_NAME "slof.bin" 69 #define FW_OVERHEAD 0x2800000 70 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 71 72 #define MIN_RMA_SLOF 128UL 73 74 #define TIMEBASE_FREQ 512000000ULL 75 76 #define MAX_CPUS 256 77 #define XICS_IRQS 1024 78 79 #define PHANDLE_XICP 0x00001111 80 81 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 82 83 sPAPREnvironment *spapr; 84 85 int spapr_allocate_irq(int hint, bool lsi) 86 { 87 int irq; 88 89 if (hint) { 90 irq = hint; 91 if (hint >= spapr->next_irq) { 92 spapr->next_irq = hint + 1; 93 } 94 /* FIXME: we should probably check for collisions somehow */ 95 } else { 96 irq = spapr->next_irq++; 97 } 98 99 /* Configure irq type */ 100 if (!xics_get_qirq(spapr->icp, irq)) { 101 return 0; 102 } 103 104 xics_set_irq_type(spapr->icp, irq, lsi); 105 106 return irq; 107 } 108 109 /* 110 * Allocate block of consequtive IRQs, returns a number of the first. 111 * If msi==true, aligns the first IRQ number to num. 112 */ 113 int spapr_allocate_irq_block(int num, bool lsi, bool msi) 114 { 115 int first = -1; 116 int i, hint = 0; 117 118 /* 119 * MSIMesage::data is used for storing VIRQ so 120 * it has to be aligned to num to support multiple 121 * MSI vectors. MSI-X is not affected by this. 122 * The hint is used for the first IRQ, the rest should 123 * be allocated continuously. 124 */ 125 if (msi) { 126 assert((num == 1) || (num == 2) || (num == 4) || 127 (num == 8) || (num == 16) || (num == 32)); 128 hint = (spapr->next_irq + num - 1) & ~(num - 1); 129 } 130 131 for (i = 0; i < num; ++i) { 132 int irq; 133 134 irq = spapr_allocate_irq(hint, lsi); 135 if (!irq) { 136 return -1; 137 } 138 139 if (0 == i) { 140 first = irq; 141 hint = 0; 142 } 143 144 /* If the above doesn't create a consecutive block then that's 145 * an internal bug */ 146 assert(irq == (first + i)); 147 } 148 149 return first; 150 } 151 152 static XICSState *try_create_xics(const char *type, int nr_servers, 153 int nr_irqs) 154 { 155 DeviceState *dev; 156 157 dev = qdev_create(NULL, type); 158 qdev_prop_set_uint32(dev, "nr_servers", nr_servers); 159 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); 160 if (qdev_init(dev) < 0) { 161 return NULL; 162 } 163 164 return XICS_COMMON(dev); 165 } 166 167 static XICSState *xics_system_init(int nr_servers, int nr_irqs) 168 { 169 XICSState *icp = NULL; 170 171 if (kvm_enabled()) { 172 QemuOpts *machine_opts = qemu_get_machine_opts(); 173 bool irqchip_allowed = qemu_opt_get_bool(machine_opts, 174 "kernel_irqchip", true); 175 bool irqchip_required = qemu_opt_get_bool(machine_opts, 176 "kernel_irqchip", false); 177 if (irqchip_allowed) { 178 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs); 179 } 180 181 if (irqchip_required && !icp) { 182 perror("Failed to create in-kernel XICS\n"); 183 abort(); 184 } 185 } 186 187 if (!icp) { 188 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs); 189 } 190 191 if (!icp) { 192 perror("Failed to create XICS\n"); 193 abort(); 194 } 195 196 return icp; 197 } 198 199 static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr) 200 { 201 int ret = 0, offset; 202 CPUState *cpu; 203 char cpu_model[32]; 204 int smt = kvmppc_smt_threads(); 205 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 206 207 CPU_FOREACH(cpu) { 208 DeviceClass *dc = DEVICE_GET_CLASS(cpu); 209 uint32_t associativity[] = {cpu_to_be32(0x5), 210 cpu_to_be32(0x0), 211 cpu_to_be32(0x0), 212 cpu_to_be32(0x0), 213 cpu_to_be32(cpu->numa_node), 214 cpu_to_be32(cpu->cpu_index)}; 215 216 if ((cpu->cpu_index % smt) != 0) { 217 continue; 218 } 219 220 snprintf(cpu_model, 32, "/cpus/%s@%x", dc->fw_name, 221 cpu->cpu_index); 222 223 offset = fdt_path_offset(fdt, cpu_model); 224 if (offset < 0) { 225 return offset; 226 } 227 228 if (nb_numa_nodes > 1) { 229 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 230 sizeof(associativity)); 231 if (ret < 0) { 232 return ret; 233 } 234 } 235 236 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 237 pft_size_prop, sizeof(pft_size_prop)); 238 if (ret < 0) { 239 return ret; 240 } 241 } 242 return ret; 243 } 244 245 246 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, 247 size_t maxsize) 248 { 249 size_t maxcells = maxsize / sizeof(uint32_t); 250 int i, j, count; 251 uint32_t *p = prop; 252 253 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 254 struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; 255 256 if (!sps->page_shift) { 257 break; 258 } 259 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { 260 if (sps->enc[count].page_shift == 0) { 261 break; 262 } 263 } 264 if ((p - prop) >= (maxcells - 3 - count * 2)) { 265 break; 266 } 267 *(p++) = cpu_to_be32(sps->page_shift); 268 *(p++) = cpu_to_be32(sps->slb_enc); 269 *(p++) = cpu_to_be32(count); 270 for (j = 0; j < count; j++) { 271 *(p++) = cpu_to_be32(sps->enc[j].page_shift); 272 *(p++) = cpu_to_be32(sps->enc[j].pte_enc); 273 } 274 } 275 276 return (p - prop) * sizeof(uint32_t); 277 } 278 279 #define _FDT(exp) \ 280 do { \ 281 int ret = (exp); \ 282 if (ret < 0) { \ 283 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ 284 #exp, fdt_strerror(ret)); \ 285 exit(1); \ 286 } \ 287 } while (0) 288 289 290 static void *spapr_create_fdt_skel(hwaddr initrd_base, 291 hwaddr initrd_size, 292 hwaddr kernel_size, 293 bool little_endian, 294 const char *boot_device, 295 const char *kernel_cmdline, 296 uint32_t epow_irq) 297 { 298 void *fdt; 299 CPUState *cs; 300 uint32_t start_prop = cpu_to_be32(initrd_base); 301 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); 302 char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt" 303 "\0hcall-tce\0hcall-vio\0hcall-splpar\0hcall-bulk\0hcall-set-mode"; 304 char qemu_hypertas_prop[] = "hcall-memop1"; 305 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; 306 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)}; 307 int i, smt = kvmppc_smt_threads(); 308 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; 309 310 fdt = g_malloc0(FDT_MAX_SIZE); 311 _FDT((fdt_create(fdt, FDT_MAX_SIZE))); 312 313 if (kernel_size) { 314 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); 315 } 316 if (initrd_size) { 317 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); 318 } 319 _FDT((fdt_finish_reservemap(fdt))); 320 321 /* Root node */ 322 _FDT((fdt_begin_node(fdt, ""))); 323 _FDT((fdt_property_string(fdt, "device_type", "chrp"))); 324 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); 325 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); 326 327 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); 328 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); 329 330 /* /chosen */ 331 _FDT((fdt_begin_node(fdt, "chosen"))); 332 333 /* Set Form1_affinity */ 334 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); 335 336 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); 337 _FDT((fdt_property(fdt, "linux,initrd-start", 338 &start_prop, sizeof(start_prop)))); 339 _FDT((fdt_property(fdt, "linux,initrd-end", 340 &end_prop, sizeof(end_prop)))); 341 if (kernel_size) { 342 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 343 cpu_to_be64(kernel_size) }; 344 345 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); 346 if (little_endian) { 347 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); 348 } 349 } 350 if (boot_device) { 351 _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device))); 352 } 353 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); 354 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); 355 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); 356 357 _FDT((fdt_end_node(fdt))); 358 359 /* cpus */ 360 _FDT((fdt_begin_node(fdt, "cpus"))); 361 362 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 363 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 364 365 CPU_FOREACH(cs) { 366 PowerPCCPU *cpu = POWERPC_CPU(cs); 367 CPUPPCState *env = &cpu->env; 368 DeviceClass *dc = DEVICE_GET_CLASS(cs); 369 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 370 int index = cs->cpu_index; 371 uint32_t servers_prop[smp_threads]; 372 uint32_t gservers_prop[smp_threads * 2]; 373 char *nodename; 374 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 375 0xffffffff, 0xffffffff}; 376 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; 377 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 378 uint32_t page_sizes_prop[64]; 379 size_t page_sizes_prop_size; 380 381 if ((index % smt) != 0) { 382 continue; 383 } 384 385 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 386 387 _FDT((fdt_begin_node(fdt, nodename))); 388 389 g_free(nodename); 390 391 _FDT((fdt_property_cell(fdt, "reg", index))); 392 _FDT((fdt_property_string(fdt, "device_type", "cpu"))); 393 394 _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR]))); 395 _FDT((fdt_property_cell(fdt, "d-cache-block-size", 396 env->dcache_line_size))); 397 _FDT((fdt_property_cell(fdt, "d-cache-line-size", 398 env->dcache_line_size))); 399 _FDT((fdt_property_cell(fdt, "i-cache-block-size", 400 env->icache_line_size))); 401 _FDT((fdt_property_cell(fdt, "i-cache-line-size", 402 env->icache_line_size))); 403 404 if (pcc->l1_dcache_size) { 405 _FDT((fdt_property_cell(fdt, "d-cache-size", pcc->l1_dcache_size))); 406 } else { 407 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); 408 } 409 if (pcc->l1_icache_size) { 410 _FDT((fdt_property_cell(fdt, "i-cache-size", pcc->l1_icache_size))); 411 } else { 412 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); 413 } 414 415 _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq))); 416 _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq))); 417 _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr))); 418 _FDT((fdt_property_string(fdt, "status", "okay"))); 419 _FDT((fdt_property(fdt, "64-bit", NULL, 0))); 420 421 /* Build interrupt servers and gservers properties */ 422 for (i = 0; i < smp_threads; i++) { 423 servers_prop[i] = cpu_to_be32(index + i); 424 /* Hack, direct the group queues back to cpu 0 */ 425 gservers_prop[i*2] = cpu_to_be32(index + i); 426 gservers_prop[i*2 + 1] = 0; 427 } 428 _FDT((fdt_property(fdt, "ibm,ppc-interrupt-server#s", 429 servers_prop, sizeof(servers_prop)))); 430 _FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s", 431 gservers_prop, sizeof(gservers_prop)))); 432 433 if (env->spr_cb[SPR_PURR].oea_read) { 434 _FDT((fdt_property(fdt, "ibm,purr", NULL, 0))); 435 } 436 437 if (env->mmu_model & POWERPC_MMU_1TSEG) { 438 _FDT((fdt_property(fdt, "ibm,processor-segment-sizes", 439 segs, sizeof(segs)))); 440 } 441 442 /* Advertise VMX/VSX (vector extensions) if available 443 * 0 / no property == no vector extensions 444 * 1 == VMX / Altivec available 445 * 2 == VSX available */ 446 if (env->insns_flags & PPC_ALTIVEC) { 447 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 448 449 _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx))); 450 } 451 452 /* Advertise DFP (Decimal Floating Point) if available 453 * 0 / no property == no DFP 454 * 1 == DFP available */ 455 if (env->insns_flags2 & PPC2_DFP) { 456 _FDT((fdt_property_cell(fdt, "ibm,dfp", 1))); 457 } 458 459 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, 460 sizeof(page_sizes_prop)); 461 if (page_sizes_prop_size) { 462 _FDT((fdt_property(fdt, "ibm,segment-page-sizes", 463 page_sizes_prop, page_sizes_prop_size))); 464 } 465 466 _FDT((fdt_end_node(fdt))); 467 } 468 469 _FDT((fdt_end_node(fdt))); 470 471 /* RTAS */ 472 _FDT((fdt_begin_node(fdt, "rtas"))); 473 474 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop, 475 sizeof(hypertas_prop)))); 476 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas_prop, 477 sizeof(qemu_hypertas_prop)))); 478 479 _FDT((fdt_property(fdt, "ibm,associativity-reference-points", 480 refpoints, sizeof(refpoints)))); 481 482 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); 483 484 _FDT((fdt_end_node(fdt))); 485 486 /* interrupt controller */ 487 _FDT((fdt_begin_node(fdt, "interrupt-controller"))); 488 489 _FDT((fdt_property_string(fdt, "device_type", 490 "PowerPC-External-Interrupt-Presentation"))); 491 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); 492 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 493 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", 494 interrupt_server_ranges_prop, 495 sizeof(interrupt_server_ranges_prop)))); 496 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); 497 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); 498 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); 499 500 _FDT((fdt_end_node(fdt))); 501 502 /* vdevice */ 503 _FDT((fdt_begin_node(fdt, "vdevice"))); 504 505 _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); 506 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); 507 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 508 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 509 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); 510 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 511 512 _FDT((fdt_end_node(fdt))); 513 514 /* event-sources */ 515 spapr_events_fdt_skel(fdt, epow_irq); 516 517 _FDT((fdt_end_node(fdt))); /* close root node */ 518 _FDT((fdt_finish(fdt))); 519 520 return fdt; 521 } 522 523 static int spapr_populate_memory(sPAPREnvironment *spapr, void *fdt) 524 { 525 uint32_t associativity[] = {cpu_to_be32(0x4), cpu_to_be32(0x0), 526 cpu_to_be32(0x0), cpu_to_be32(0x0), 527 cpu_to_be32(0x0)}; 528 char mem_name[32]; 529 hwaddr node0_size, mem_start, node_size; 530 uint64_t mem_reg_property[2]; 531 int i, off; 532 533 /* memory node(s) */ 534 if (nb_numa_nodes > 1 && node_mem[0] < ram_size) { 535 node0_size = node_mem[0]; 536 } else { 537 node0_size = ram_size; 538 } 539 540 /* RMA */ 541 mem_reg_property[0] = 0; 542 mem_reg_property[1] = cpu_to_be64(spapr->rma_size); 543 off = fdt_add_subnode(fdt, 0, "memory@0"); 544 _FDT(off); 545 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 546 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 547 sizeof(mem_reg_property)))); 548 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 549 sizeof(associativity)))); 550 551 /* RAM: Node 0 */ 552 if (node0_size > spapr->rma_size) { 553 mem_reg_property[0] = cpu_to_be64(spapr->rma_size); 554 mem_reg_property[1] = cpu_to_be64(node0_size - spapr->rma_size); 555 556 sprintf(mem_name, "memory@" TARGET_FMT_lx, spapr->rma_size); 557 off = fdt_add_subnode(fdt, 0, mem_name); 558 _FDT(off); 559 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 560 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 561 sizeof(mem_reg_property)))); 562 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 563 sizeof(associativity)))); 564 } 565 566 /* RAM: Node 1 and beyond */ 567 mem_start = node0_size; 568 for (i = 1; i < nb_numa_nodes; i++) { 569 mem_reg_property[0] = cpu_to_be64(mem_start); 570 if (mem_start >= ram_size) { 571 node_size = 0; 572 } else { 573 node_size = node_mem[i]; 574 if (node_size > ram_size - mem_start) { 575 node_size = ram_size - mem_start; 576 } 577 } 578 mem_reg_property[1] = cpu_to_be64(node_size); 579 associativity[3] = associativity[4] = cpu_to_be32(i); 580 sprintf(mem_name, "memory@" TARGET_FMT_lx, mem_start); 581 off = fdt_add_subnode(fdt, 0, mem_name); 582 _FDT(off); 583 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 584 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 585 sizeof(mem_reg_property)))); 586 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 587 sizeof(associativity)))); 588 mem_start += node_size; 589 } 590 591 return 0; 592 } 593 594 static void spapr_finalize_fdt(sPAPREnvironment *spapr, 595 hwaddr fdt_addr, 596 hwaddr rtas_addr, 597 hwaddr rtas_size) 598 { 599 int ret; 600 void *fdt; 601 sPAPRPHBState *phb; 602 603 fdt = g_malloc(FDT_MAX_SIZE); 604 605 /* open out the base tree into a temp buffer for the final tweaks */ 606 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); 607 608 ret = spapr_populate_memory(spapr, fdt); 609 if (ret < 0) { 610 fprintf(stderr, "couldn't setup memory nodes in fdt\n"); 611 exit(1); 612 } 613 614 ret = spapr_populate_vdevice(spapr->vio_bus, fdt); 615 if (ret < 0) { 616 fprintf(stderr, "couldn't setup vio devices in fdt\n"); 617 exit(1); 618 } 619 620 QLIST_FOREACH(phb, &spapr->phbs, list) { 621 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 622 } 623 624 if (ret < 0) { 625 fprintf(stderr, "couldn't setup PCI devices in fdt\n"); 626 exit(1); 627 } 628 629 /* RTAS */ 630 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); 631 if (ret < 0) { 632 fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); 633 } 634 635 /* Advertise NUMA via ibm,associativity */ 636 ret = spapr_fixup_cpu_dt(fdt, spapr); 637 if (ret < 0) { 638 fprintf(stderr, "Couldn't finalize CPU device tree properties\n"); 639 } 640 641 if (!spapr->has_graphics) { 642 spapr_populate_chosen_stdout(fdt, spapr->vio_bus); 643 } 644 645 _FDT((fdt_pack(fdt))); 646 647 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 648 hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n", 649 fdt_totalsize(fdt), FDT_MAX_SIZE); 650 exit(1); 651 } 652 653 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 654 655 g_free(fdt); 656 } 657 658 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 659 { 660 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 661 } 662 663 static void emulate_spapr_hypercall(PowerPCCPU *cpu) 664 { 665 CPUPPCState *env = &cpu->env; 666 667 if (msr_pr) { 668 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 669 env->gpr[3] = H_PRIVILEGE; 670 } else { 671 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 672 } 673 } 674 675 static void spapr_reset_htab(sPAPREnvironment *spapr) 676 { 677 long shift; 678 679 /* allocate hash page table. For now we always make this 16mb, 680 * later we should probably make it scale to the size of guest 681 * RAM */ 682 683 shift = kvmppc_reset_htab(spapr->htab_shift); 684 685 if (shift > 0) { 686 /* Kernel handles htab, we don't need to allocate one */ 687 spapr->htab_shift = shift; 688 } else { 689 if (!spapr->htab) { 690 /* Allocate an htab if we don't yet have one */ 691 spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); 692 } 693 694 /* And clear it */ 695 memset(spapr->htab, 0, HTAB_SIZE(spapr)); 696 } 697 698 /* Update the RMA size if necessary */ 699 if (spapr->vrma_adjust) { 700 hwaddr node0_size = (nb_numa_nodes > 1) ? node_mem[0] : ram_size; 701 spapr->rma_size = kvmppc_rma_size(node0_size, spapr->htab_shift); 702 } 703 } 704 705 static void ppc_spapr_reset(void) 706 { 707 PowerPCCPU *first_ppc_cpu; 708 709 /* Reset the hash table & recalc the RMA */ 710 spapr_reset_htab(spapr); 711 712 qemu_devices_reset(); 713 714 /* Load the fdt */ 715 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, 716 spapr->rtas_size); 717 718 /* Set up the entry state */ 719 first_ppc_cpu = POWERPC_CPU(first_cpu); 720 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; 721 first_ppc_cpu->env.gpr[5] = 0; 722 first_cpu->halted = 0; 723 first_ppc_cpu->env.nip = spapr->entry_point; 724 725 } 726 727 static void spapr_cpu_reset(void *opaque) 728 { 729 PowerPCCPU *cpu = opaque; 730 CPUState *cs = CPU(cpu); 731 CPUPPCState *env = &cpu->env; 732 733 cpu_reset(cs); 734 735 /* All CPUs start halted. CPU0 is unhalted from the machine level 736 * reset code and the rest are explicitly started up by the guest 737 * using an RTAS call */ 738 cs->halted = 1; 739 740 env->spr[SPR_HIOR] = 0; 741 742 env->external_htab = (uint8_t *)spapr->htab; 743 env->htab_base = -1; 744 env->htab_mask = HTAB_SIZE(spapr) - 1; 745 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | 746 (spapr->htab_shift - 18); 747 } 748 749 static void spapr_create_nvram(sPAPREnvironment *spapr) 750 { 751 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 752 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 753 754 if (dinfo) { 755 qdev_prop_set_drive_nofail(dev, "drive", dinfo->bdrv); 756 } 757 758 qdev_init_nofail(dev); 759 760 spapr->nvram = (struct sPAPRNVRAM *)dev; 761 } 762 763 /* Returns whether we want to use VGA or not */ 764 static int spapr_vga_init(PCIBus *pci_bus) 765 { 766 switch (vga_interface_type) { 767 case VGA_NONE: 768 case VGA_STD: 769 return pci_vga_init(pci_bus) != NULL; 770 default: 771 fprintf(stderr, "This vga model is not supported," 772 "currently it only supports -vga std\n"); 773 exit(0); 774 break; 775 } 776 } 777 778 static const VMStateDescription vmstate_spapr = { 779 .name = "spapr", 780 .version_id = 1, 781 .minimum_version_id = 1, 782 .minimum_version_id_old = 1, 783 .fields = (VMStateField []) { 784 VMSTATE_UINT32(next_irq, sPAPREnvironment), 785 786 /* RTC offset */ 787 VMSTATE_UINT64(rtc_offset, sPAPREnvironment), 788 789 VMSTATE_END_OF_LIST() 790 }, 791 }; 792 793 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 794 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 795 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 796 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 797 798 static int htab_save_setup(QEMUFile *f, void *opaque) 799 { 800 sPAPREnvironment *spapr = opaque; 801 802 /* "Iteration" header */ 803 qemu_put_be32(f, spapr->htab_shift); 804 805 if (spapr->htab) { 806 spapr->htab_save_index = 0; 807 spapr->htab_first_pass = true; 808 } else { 809 assert(kvm_enabled()); 810 811 spapr->htab_fd = kvmppc_get_htab_fd(false); 812 if (spapr->htab_fd < 0) { 813 fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n", 814 strerror(errno)); 815 return -1; 816 } 817 } 818 819 820 return 0; 821 } 822 823 static void htab_save_first_pass(QEMUFile *f, sPAPREnvironment *spapr, 824 int64_t max_ns) 825 { 826 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 827 int index = spapr->htab_save_index; 828 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 829 830 assert(spapr->htab_first_pass); 831 832 do { 833 int chunkstart; 834 835 /* Consume invalid HPTEs */ 836 while ((index < htabslots) 837 && !HPTE_VALID(HPTE(spapr->htab, index))) { 838 index++; 839 CLEAN_HPTE(HPTE(spapr->htab, index)); 840 } 841 842 /* Consume valid HPTEs */ 843 chunkstart = index; 844 while ((index < htabslots) 845 && HPTE_VALID(HPTE(spapr->htab, index))) { 846 index++; 847 CLEAN_HPTE(HPTE(spapr->htab, index)); 848 } 849 850 if (index > chunkstart) { 851 int n_valid = index - chunkstart; 852 853 qemu_put_be32(f, chunkstart); 854 qemu_put_be16(f, n_valid); 855 qemu_put_be16(f, 0); 856 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 857 HASH_PTE_SIZE_64 * n_valid); 858 859 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 860 break; 861 } 862 } 863 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 864 865 if (index >= htabslots) { 866 assert(index == htabslots); 867 index = 0; 868 spapr->htab_first_pass = false; 869 } 870 spapr->htab_save_index = index; 871 } 872 873 static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr, 874 int64_t max_ns) 875 { 876 bool final = max_ns < 0; 877 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 878 int examined = 0, sent = 0; 879 int index = spapr->htab_save_index; 880 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 881 882 assert(!spapr->htab_first_pass); 883 884 do { 885 int chunkstart, invalidstart; 886 887 /* Consume non-dirty HPTEs */ 888 while ((index < htabslots) 889 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 890 index++; 891 examined++; 892 } 893 894 chunkstart = index; 895 /* Consume valid dirty HPTEs */ 896 while ((index < htabslots) 897 && HPTE_DIRTY(HPTE(spapr->htab, index)) 898 && HPTE_VALID(HPTE(spapr->htab, index))) { 899 CLEAN_HPTE(HPTE(spapr->htab, index)); 900 index++; 901 examined++; 902 } 903 904 invalidstart = index; 905 /* Consume invalid dirty HPTEs */ 906 while ((index < htabslots) 907 && HPTE_DIRTY(HPTE(spapr->htab, index)) 908 && !HPTE_VALID(HPTE(spapr->htab, index))) { 909 CLEAN_HPTE(HPTE(spapr->htab, index)); 910 index++; 911 examined++; 912 } 913 914 if (index > chunkstart) { 915 int n_valid = invalidstart - chunkstart; 916 int n_invalid = index - invalidstart; 917 918 qemu_put_be32(f, chunkstart); 919 qemu_put_be16(f, n_valid); 920 qemu_put_be16(f, n_invalid); 921 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 922 HASH_PTE_SIZE_64 * n_valid); 923 sent += index - chunkstart; 924 925 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 926 break; 927 } 928 } 929 930 if (examined >= htabslots) { 931 break; 932 } 933 934 if (index >= htabslots) { 935 assert(index == htabslots); 936 index = 0; 937 } 938 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 939 940 if (index >= htabslots) { 941 assert(index == htabslots); 942 index = 0; 943 } 944 945 spapr->htab_save_index = index; 946 947 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 948 } 949 950 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 951 #define MAX_KVM_BUF_SIZE 2048 952 953 static int htab_save_iterate(QEMUFile *f, void *opaque) 954 { 955 sPAPREnvironment *spapr = opaque; 956 int rc = 0; 957 958 /* Iteration header */ 959 qemu_put_be32(f, 0); 960 961 if (!spapr->htab) { 962 assert(kvm_enabled()); 963 964 rc = kvmppc_save_htab(f, spapr->htab_fd, 965 MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 966 if (rc < 0) { 967 return rc; 968 } 969 } else if (spapr->htab_first_pass) { 970 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 971 } else { 972 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 973 } 974 975 /* End marker */ 976 qemu_put_be32(f, 0); 977 qemu_put_be16(f, 0); 978 qemu_put_be16(f, 0); 979 980 return rc; 981 } 982 983 static int htab_save_complete(QEMUFile *f, void *opaque) 984 { 985 sPAPREnvironment *spapr = opaque; 986 987 /* Iteration header */ 988 qemu_put_be32(f, 0); 989 990 if (!spapr->htab) { 991 int rc; 992 993 assert(kvm_enabled()); 994 995 rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1); 996 if (rc < 0) { 997 return rc; 998 } 999 close(spapr->htab_fd); 1000 spapr->htab_fd = -1; 1001 } else { 1002 htab_save_later_pass(f, spapr, -1); 1003 } 1004 1005 /* End marker */ 1006 qemu_put_be32(f, 0); 1007 qemu_put_be16(f, 0); 1008 qemu_put_be16(f, 0); 1009 1010 return 0; 1011 } 1012 1013 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1014 { 1015 sPAPREnvironment *spapr = opaque; 1016 uint32_t section_hdr; 1017 int fd = -1; 1018 1019 if (version_id < 1 || version_id > 1) { 1020 fprintf(stderr, "htab_load() bad version\n"); 1021 return -EINVAL; 1022 } 1023 1024 section_hdr = qemu_get_be32(f); 1025 1026 if (section_hdr) { 1027 /* First section, just the hash shift */ 1028 if (spapr->htab_shift != section_hdr) { 1029 return -EINVAL; 1030 } 1031 return 0; 1032 } 1033 1034 if (!spapr->htab) { 1035 assert(kvm_enabled()); 1036 1037 fd = kvmppc_get_htab_fd(true); 1038 if (fd < 0) { 1039 fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n", 1040 strerror(errno)); 1041 } 1042 } 1043 1044 while (true) { 1045 uint32_t index; 1046 uint16_t n_valid, n_invalid; 1047 1048 index = qemu_get_be32(f); 1049 n_valid = qemu_get_be16(f); 1050 n_invalid = qemu_get_be16(f); 1051 1052 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1053 /* End of Stream */ 1054 break; 1055 } 1056 1057 if ((index + n_valid + n_invalid) > 1058 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1059 /* Bad index in stream */ 1060 fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) " 1061 "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid, 1062 spapr->htab_shift); 1063 return -EINVAL; 1064 } 1065 1066 if (spapr->htab) { 1067 if (n_valid) { 1068 qemu_get_buffer(f, HPTE(spapr->htab, index), 1069 HASH_PTE_SIZE_64 * n_valid); 1070 } 1071 if (n_invalid) { 1072 memset(HPTE(spapr->htab, index + n_valid), 0, 1073 HASH_PTE_SIZE_64 * n_invalid); 1074 } 1075 } else { 1076 int rc; 1077 1078 assert(fd >= 0); 1079 1080 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1081 if (rc < 0) { 1082 return rc; 1083 } 1084 } 1085 } 1086 1087 if (!spapr->htab) { 1088 assert(fd >= 0); 1089 close(fd); 1090 } 1091 1092 return 0; 1093 } 1094 1095 static SaveVMHandlers savevm_htab_handlers = { 1096 .save_live_setup = htab_save_setup, 1097 .save_live_iterate = htab_save_iterate, 1098 .save_live_complete = htab_save_complete, 1099 .load_state = htab_load, 1100 }; 1101 1102 /* pSeries LPAR / sPAPR hardware init */ 1103 static void ppc_spapr_init(QEMUMachineInitArgs *args) 1104 { 1105 ram_addr_t ram_size = args->ram_size; 1106 const char *cpu_model = args->cpu_model; 1107 const char *kernel_filename = args->kernel_filename; 1108 const char *kernel_cmdline = args->kernel_cmdline; 1109 const char *initrd_filename = args->initrd_filename; 1110 const char *boot_device = args->boot_order; 1111 PowerPCCPU *cpu; 1112 CPUPPCState *env; 1113 PCIHostState *phb; 1114 int i; 1115 MemoryRegion *sysmem = get_system_memory(); 1116 MemoryRegion *ram = g_new(MemoryRegion, 1); 1117 hwaddr rma_alloc_size; 1118 hwaddr node0_size = (nb_numa_nodes > 1) ? node_mem[0] : ram_size; 1119 uint32_t initrd_base = 0; 1120 long kernel_size = 0, initrd_size = 0; 1121 long load_limit, rtas_limit, fw_size; 1122 bool kernel_le = false; 1123 char *filename; 1124 1125 msi_supported = true; 1126 1127 spapr = g_malloc0(sizeof(*spapr)); 1128 QLIST_INIT(&spapr->phbs); 1129 1130 cpu_ppc_hypercall = emulate_spapr_hypercall; 1131 1132 /* Allocate RMA if necessary */ 1133 rma_alloc_size = kvmppc_alloc_rma("ppc_spapr.rma", sysmem); 1134 1135 if (rma_alloc_size == -1) { 1136 hw_error("qemu: Unable to create RMA\n"); 1137 exit(1); 1138 } 1139 1140 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1141 spapr->rma_size = rma_alloc_size; 1142 } else { 1143 spapr->rma_size = node0_size; 1144 1145 /* With KVM, we don't actually know whether KVM supports an 1146 * unbounded RMA (PR KVM) or is limited by the hash table size 1147 * (HV KVM using VRMA), so we always assume the latter 1148 * 1149 * In that case, we also limit the initial allocations for RTAS 1150 * etc... to 256M since we have no way to know what the VRMA size 1151 * is going to be as it depends on the size of the hash table 1152 * isn't determined yet. 1153 */ 1154 if (kvm_enabled()) { 1155 spapr->vrma_adjust = 1; 1156 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1157 } 1158 } 1159 1160 if (spapr->rma_size > node0_size) { 1161 fprintf(stderr, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")\n", 1162 spapr->rma_size); 1163 exit(1); 1164 } 1165 1166 /* We place the device tree and RTAS just below either the top of the RMA, 1167 * or just below 2GB, whichever is lowere, so that it can be 1168 * processed with 32-bit real mode code if necessary */ 1169 rtas_limit = MIN(spapr->rma_size, 0x80000000); 1170 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1171 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; 1172 load_limit = spapr->fdt_addr - FW_OVERHEAD; 1173 1174 /* We aim for a hash table of size 1/128 the size of RAM. The 1175 * normal rule of thumb is 1/64 the size of RAM, but that's much 1176 * more than needed for the Linux guests we support. */ 1177 spapr->htab_shift = 18; /* Minimum architected size */ 1178 while (spapr->htab_shift <= 46) { 1179 if ((1ULL << (spapr->htab_shift + 7)) >= ram_size) { 1180 break; 1181 } 1182 spapr->htab_shift++; 1183 } 1184 1185 /* Set up Interrupt Controller before we create the VCPUs */ 1186 spapr->icp = xics_system_init(smp_cpus * kvmppc_smt_threads() / smp_threads, 1187 XICS_IRQS); 1188 spapr->next_irq = XICS_IRQ_BASE; 1189 1190 /* init CPUs */ 1191 if (cpu_model == NULL) { 1192 cpu_model = kvm_enabled() ? "host" : "POWER7"; 1193 } 1194 for (i = 0; i < smp_cpus; i++) { 1195 cpu = cpu_ppc_init(cpu_model); 1196 if (cpu == NULL) { 1197 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 1198 exit(1); 1199 } 1200 env = &cpu->env; 1201 1202 /* Set time-base frequency to 512 MHz */ 1203 cpu_ppc_tb_init(env, TIMEBASE_FREQ); 1204 1205 /* PAPR always has exception vectors in RAM not ROM. To ensure this, 1206 * MSR[IP] should never be set. 1207 */ 1208 env->msr_mask &= ~(1 << 6); 1209 1210 /* Tell KVM that we're in PAPR mode */ 1211 if (kvm_enabled()) { 1212 kvmppc_set_papr(cpu); 1213 } 1214 1215 xics_cpu_setup(spapr->icp, cpu); 1216 1217 qemu_register_reset(spapr_cpu_reset, cpu); 1218 } 1219 1220 /* allocate RAM */ 1221 spapr->ram_limit = ram_size; 1222 if (spapr->ram_limit > rma_alloc_size) { 1223 ram_addr_t nonrma_base = rma_alloc_size; 1224 ram_addr_t nonrma_size = spapr->ram_limit - rma_alloc_size; 1225 1226 memory_region_init_ram(ram, NULL, "ppc_spapr.ram", nonrma_size); 1227 vmstate_register_ram_global(ram); 1228 memory_region_add_subregion(sysmem, nonrma_base, ram); 1229 } 1230 1231 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 1232 spapr->rtas_size = load_image_targphys(filename, spapr->rtas_addr, 1233 rtas_limit - spapr->rtas_addr); 1234 if (spapr->rtas_size < 0) { 1235 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 1236 exit(1); 1237 } 1238 if (spapr->rtas_size > RTAS_MAX_SIZE) { 1239 hw_error("RTAS too big ! 0x%lx bytes (max is 0x%x)\n", 1240 spapr->rtas_size, RTAS_MAX_SIZE); 1241 exit(1); 1242 } 1243 g_free(filename); 1244 1245 /* Set up EPOW events infrastructure */ 1246 spapr_events_init(spapr); 1247 1248 /* Set up VIO bus */ 1249 spapr->vio_bus = spapr_vio_bus_init(); 1250 1251 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 1252 if (serial_hds[i]) { 1253 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 1254 } 1255 } 1256 1257 /* We always have at least the nvram device on VIO */ 1258 spapr_create_nvram(spapr); 1259 1260 /* Set up PCI */ 1261 spapr_pci_msi_init(spapr, SPAPR_PCI_MSI_WINDOW); 1262 spapr_pci_rtas_init(); 1263 1264 phb = spapr_create_phb(spapr, 0); 1265 1266 for (i = 0; i < nb_nics; i++) { 1267 NICInfo *nd = &nd_table[i]; 1268 1269 if (!nd->model) { 1270 nd->model = g_strdup("ibmveth"); 1271 } 1272 1273 if (strcmp(nd->model, "ibmveth") == 0) { 1274 spapr_vlan_create(spapr->vio_bus, nd); 1275 } else { 1276 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 1277 } 1278 } 1279 1280 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 1281 spapr_vscsi_create(spapr->vio_bus); 1282 } 1283 1284 /* Graphics */ 1285 if (spapr_vga_init(phb->bus)) { 1286 spapr->has_graphics = true; 1287 } 1288 1289 if (usb_enabled(spapr->has_graphics)) { 1290 pci_create_simple(phb->bus, -1, "pci-ohci"); 1291 if (spapr->has_graphics) { 1292 usbdevice_create("keyboard"); 1293 usbdevice_create("mouse"); 1294 } 1295 } 1296 1297 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 1298 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= " 1299 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF); 1300 exit(1); 1301 } 1302 1303 if (kernel_filename) { 1304 uint64_t lowaddr = 0; 1305 1306 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 1307 NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); 1308 if (kernel_size < 0) { 1309 kernel_size = load_elf(kernel_filename, 1310 translate_kernel_address, NULL, 1311 NULL, &lowaddr, NULL, 0, ELF_MACHINE, 0); 1312 kernel_le = kernel_size > 0; 1313 } 1314 if (kernel_size < 0) { 1315 kernel_size = load_image_targphys(kernel_filename, 1316 KERNEL_LOAD_ADDR, 1317 load_limit - KERNEL_LOAD_ADDR); 1318 } 1319 if (kernel_size < 0) { 1320 fprintf(stderr, "qemu: could not load kernel '%s'\n", 1321 kernel_filename); 1322 exit(1); 1323 } 1324 1325 /* load initrd */ 1326 if (initrd_filename) { 1327 /* Try to locate the initrd in the gap between the kernel 1328 * and the firmware. Add a bit of space just in case 1329 */ 1330 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; 1331 initrd_size = load_image_targphys(initrd_filename, initrd_base, 1332 load_limit - initrd_base); 1333 if (initrd_size < 0) { 1334 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 1335 initrd_filename); 1336 exit(1); 1337 } 1338 } else { 1339 initrd_base = 0; 1340 initrd_size = 0; 1341 } 1342 } 1343 1344 if (bios_name == NULL) { 1345 bios_name = FW_FILE_NAME; 1346 } 1347 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1348 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 1349 if (fw_size < 0) { 1350 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 1351 exit(1); 1352 } 1353 g_free(filename); 1354 1355 spapr->entry_point = 0x100; 1356 1357 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 1358 register_savevm_live(NULL, "spapr/htab", -1, 1, 1359 &savevm_htab_handlers, spapr); 1360 1361 /* Prepare the device tree */ 1362 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, 1363 kernel_size, kernel_le, 1364 boot_device, kernel_cmdline, 1365 spapr->epow_irq); 1366 assert(spapr->fdt_skel != NULL); 1367 } 1368 1369 static QEMUMachine spapr_machine = { 1370 .name = "pseries", 1371 .desc = "pSeries Logical Partition (PAPR compliant)", 1372 .is_default = 1, 1373 .init = ppc_spapr_init, 1374 .reset = ppc_spapr_reset, 1375 .block_default_type = IF_SCSI, 1376 .max_cpus = MAX_CPUS, 1377 .no_parallel = 1, 1378 .default_boot_order = NULL, 1379 }; 1380 1381 static void spapr_machine_init(void) 1382 { 1383 qemu_register_machine(&spapr_machine); 1384 } 1385 1386 machine_init(spapr_machine_init); 1387