1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qemu/datadir.h" 30 #include "qapi/error.h" 31 #include "qapi/qapi-events-machine.h" 32 #include "qapi/visitor.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/hostmem.h" 35 #include "sysemu/numa.h" 36 #include "sysemu/qtest.h" 37 #include "sysemu/reset.h" 38 #include "sysemu/runstate.h" 39 #include "qemu/log.h" 40 #include "hw/fw-path-provider.h" 41 #include "elf.h" 42 #include "net/net.h" 43 #include "sysemu/device_tree.h" 44 #include "sysemu/cpus.h" 45 #include "sysemu/hw_accel.h" 46 #include "kvm_ppc.h" 47 #include "migration/misc.h" 48 #include "migration/qemu-file-types.h" 49 #include "migration/global_state.h" 50 #include "migration/register.h" 51 #include "migration/blocker.h" 52 #include "mmu-hash64.h" 53 #include "mmu-book3s-v3.h" 54 #include "cpu-models.h" 55 #include "hw/core/cpu.h" 56 57 #include "hw/boards.h" 58 #include "hw/ppc/ppc.h" 59 #include "hw/loader.h" 60 61 #include "hw/ppc/fdt.h" 62 #include "hw/ppc/spapr.h" 63 #include "hw/ppc/spapr_vio.h" 64 #include "hw/qdev-properties.h" 65 #include "hw/pci-host/spapr.h" 66 #include "hw/pci/msi.h" 67 68 #include "hw/pci/pci.h" 69 #include "hw/scsi/scsi.h" 70 #include "hw/virtio/virtio-scsi.h" 71 #include "hw/virtio/vhost-scsi-common.h" 72 73 #include "exec/address-spaces.h" 74 #include "exec/ram_addr.h" 75 #include "hw/usb.h" 76 #include "qemu/config-file.h" 77 #include "qemu/error-report.h" 78 #include "trace.h" 79 #include "hw/nmi.h" 80 #include "hw/intc/intc.h" 81 82 #include "hw/ppc/spapr_cpu_core.h" 83 #include "hw/mem/memory-device.h" 84 #include "hw/ppc/spapr_tpm_proxy.h" 85 #include "hw/ppc/spapr_nvdimm.h" 86 #include "hw/ppc/spapr_numa.h" 87 #include "hw/ppc/pef.h" 88 89 #include "monitor/monitor.h" 90 91 #include <libfdt.h> 92 93 /* SLOF memory layout: 94 * 95 * SLOF raw image loaded at 0, copies its romfs right below the flat 96 * device-tree, then position SLOF itself 31M below that 97 * 98 * So we set FW_OVERHEAD to 40MB which should account for all of that 99 * and more 100 * 101 * We load our kernel at 4M, leaving space for SLOF initial image 102 */ 103 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 104 #define FW_MAX_SIZE 0x400000 105 #define FW_FILE_NAME "slof.bin" 106 #define FW_OVERHEAD 0x2800000 107 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 108 109 #define MIN_RMA_SLOF (128 * MiB) 110 111 #define PHANDLE_INTC 0x00001111 112 113 /* These two functions implement the VCPU id numbering: one to compute them 114 * all and one to identify thread 0 of a VCORE. Any change to the first one 115 * is likely to have an impact on the second one, so let's keep them close. 116 */ 117 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 118 { 119 MachineState *ms = MACHINE(spapr); 120 unsigned int smp_threads = ms->smp.threads; 121 122 assert(spapr->vsmt); 123 return 124 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 125 } 126 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 127 PowerPCCPU *cpu) 128 { 129 assert(spapr->vsmt); 130 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 131 } 132 133 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 134 { 135 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 136 * and newer QEMUs don't even have them. In both cases, we don't want 137 * to send anything on the wire. 138 */ 139 return false; 140 } 141 142 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 143 .name = "icp/server", 144 .version_id = 1, 145 .minimum_version_id = 1, 146 .needed = pre_2_10_vmstate_dummy_icp_needed, 147 .fields = (VMStateField[]) { 148 VMSTATE_UNUSED(4), /* uint32_t xirr */ 149 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 150 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 151 VMSTATE_END_OF_LIST() 152 }, 153 }; 154 155 static void pre_2_10_vmstate_register_dummy_icp(int i) 156 { 157 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 158 (void *)(uintptr_t) i); 159 } 160 161 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 162 { 163 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 164 (void *)(uintptr_t) i); 165 } 166 167 int spapr_max_server_number(SpaprMachineState *spapr) 168 { 169 MachineState *ms = MACHINE(spapr); 170 171 assert(spapr->vsmt); 172 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 173 } 174 175 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 176 int smt_threads) 177 { 178 int i, ret = 0; 179 uint32_t servers_prop[smt_threads]; 180 uint32_t gservers_prop[smt_threads * 2]; 181 int index = spapr_get_vcpu_id(cpu); 182 183 if (cpu->compat_pvr) { 184 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 185 if (ret < 0) { 186 return ret; 187 } 188 } 189 190 /* Build interrupt servers and gservers properties */ 191 for (i = 0; i < smt_threads; i++) { 192 servers_prop[i] = cpu_to_be32(index + i); 193 /* Hack, direct the group queues back to cpu 0 */ 194 gservers_prop[i*2] = cpu_to_be32(index + i); 195 gservers_prop[i*2 + 1] = 0; 196 } 197 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 198 servers_prop, sizeof(servers_prop)); 199 if (ret < 0) { 200 return ret; 201 } 202 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 203 gservers_prop, sizeof(gservers_prop)); 204 205 return ret; 206 } 207 208 static void spapr_dt_pa_features(SpaprMachineState *spapr, 209 PowerPCCPU *cpu, 210 void *fdt, int offset) 211 { 212 uint8_t pa_features_206[] = { 6, 0, 213 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 214 uint8_t pa_features_207[] = { 24, 0, 215 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 216 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 217 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 218 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 219 uint8_t pa_features_300[] = { 66, 0, 220 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 221 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 222 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 223 /* 6: DS207 */ 224 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 225 /* 16: Vector */ 226 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 227 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 228 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 229 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 230 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 231 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 232 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 233 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 235 /* 42: PM, 44: PC RA, 46: SC vec'd */ 236 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 237 /* 48: SIMD, 50: QP BFP, 52: String */ 238 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 239 /* 54: DecFP, 56: DecI, 58: SHA */ 240 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 241 /* 60: NM atomic, 62: RNG */ 242 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 243 }; 244 uint8_t *pa_features = NULL; 245 size_t pa_size; 246 247 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 248 pa_features = pa_features_206; 249 pa_size = sizeof(pa_features_206); 250 } 251 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 252 pa_features = pa_features_207; 253 pa_size = sizeof(pa_features_207); 254 } 255 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 256 pa_features = pa_features_300; 257 pa_size = sizeof(pa_features_300); 258 } 259 if (!pa_features) { 260 return; 261 } 262 263 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 264 /* 265 * Note: we keep CI large pages off by default because a 64K capable 266 * guest provisioned with large pages might otherwise try to map a qemu 267 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 268 * even if that qemu runs on a 4k host. 269 * We dd this bit back here if we are confident this is not an issue 270 */ 271 pa_features[3] |= 0x20; 272 } 273 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 274 pa_features[24] |= 0x80; /* Transactional memory support */ 275 } 276 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 277 /* Workaround for broken kernels that attempt (guest) radix 278 * mode when they can't handle it, if they see the radix bit set 279 * in pa-features. So hide it from them. */ 280 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 281 } 282 283 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 284 } 285 286 static hwaddr spapr_node0_size(MachineState *machine) 287 { 288 if (machine->numa_state->num_nodes) { 289 int i; 290 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 291 if (machine->numa_state->nodes[i].node_mem) { 292 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 293 machine->ram_size); 294 } 295 } 296 } 297 return machine->ram_size; 298 } 299 300 static void add_str(GString *s, const gchar *s1) 301 { 302 g_string_append_len(s, s1, strlen(s1) + 1); 303 } 304 305 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 306 hwaddr start, hwaddr size) 307 { 308 char mem_name[32]; 309 uint64_t mem_reg_property[2]; 310 int off; 311 312 mem_reg_property[0] = cpu_to_be64(start); 313 mem_reg_property[1] = cpu_to_be64(size); 314 315 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 316 off = fdt_add_subnode(fdt, 0, mem_name); 317 _FDT(off); 318 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 319 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 320 sizeof(mem_reg_property)))); 321 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 322 return off; 323 } 324 325 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 326 { 327 MemoryDeviceInfoList *info; 328 329 for (info = list; info; info = info->next) { 330 MemoryDeviceInfo *value = info->value; 331 332 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 333 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 334 335 if (addr >= pcdimm_info->addr && 336 addr < (pcdimm_info->addr + pcdimm_info->size)) { 337 return pcdimm_info->node; 338 } 339 } 340 } 341 342 return -1; 343 } 344 345 struct sPAPRDrconfCellV2 { 346 uint32_t seq_lmbs; 347 uint64_t base_addr; 348 uint32_t drc_index; 349 uint32_t aa_index; 350 uint32_t flags; 351 } QEMU_PACKED; 352 353 typedef struct DrconfCellQueue { 354 struct sPAPRDrconfCellV2 cell; 355 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 356 } DrconfCellQueue; 357 358 static DrconfCellQueue * 359 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 360 uint32_t drc_index, uint32_t aa_index, 361 uint32_t flags) 362 { 363 DrconfCellQueue *elem; 364 365 elem = g_malloc0(sizeof(*elem)); 366 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 367 elem->cell.base_addr = cpu_to_be64(base_addr); 368 elem->cell.drc_index = cpu_to_be32(drc_index); 369 elem->cell.aa_index = cpu_to_be32(aa_index); 370 elem->cell.flags = cpu_to_be32(flags); 371 372 return elem; 373 } 374 375 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 376 int offset, MemoryDeviceInfoList *dimms) 377 { 378 MachineState *machine = MACHINE(spapr); 379 uint8_t *int_buf, *cur_index; 380 int ret; 381 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 382 uint64_t addr, cur_addr, size; 383 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 384 uint64_t mem_end = machine->device_memory->base + 385 memory_region_size(&machine->device_memory->mr); 386 uint32_t node, buf_len, nr_entries = 0; 387 SpaprDrc *drc; 388 DrconfCellQueue *elem, *next; 389 MemoryDeviceInfoList *info; 390 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 391 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 392 393 /* Entry to cover RAM and the gap area */ 394 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 395 SPAPR_LMB_FLAGS_RESERVED | 396 SPAPR_LMB_FLAGS_DRC_INVALID); 397 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 398 nr_entries++; 399 400 cur_addr = machine->device_memory->base; 401 for (info = dimms; info; info = info->next) { 402 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 403 404 addr = di->addr; 405 size = di->size; 406 node = di->node; 407 408 /* 409 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 410 * area is marked hotpluggable in the next iteration for the bigger 411 * chunk including the NVDIMM occupied area. 412 */ 413 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 414 continue; 415 416 /* Entry for hot-pluggable area */ 417 if (cur_addr < addr) { 418 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 419 g_assert(drc); 420 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 421 cur_addr, spapr_drc_index(drc), -1, 0); 422 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 423 nr_entries++; 424 } 425 426 /* Entry for DIMM */ 427 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 428 g_assert(drc); 429 elem = spapr_get_drconf_cell(size / lmb_size, addr, 430 spapr_drc_index(drc), node, 431 (SPAPR_LMB_FLAGS_ASSIGNED | 432 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 433 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 434 nr_entries++; 435 cur_addr = addr + size; 436 } 437 438 /* Entry for remaining hotpluggable area */ 439 if (cur_addr < mem_end) { 440 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 441 g_assert(drc); 442 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 443 cur_addr, spapr_drc_index(drc), -1, 0); 444 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 445 nr_entries++; 446 } 447 448 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 449 int_buf = cur_index = g_malloc0(buf_len); 450 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 451 cur_index += sizeof(nr_entries); 452 453 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 454 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 455 cur_index += sizeof(elem->cell); 456 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 457 g_free(elem); 458 } 459 460 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 461 g_free(int_buf); 462 if (ret < 0) { 463 return -1; 464 } 465 return 0; 466 } 467 468 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 469 int offset, MemoryDeviceInfoList *dimms) 470 { 471 MachineState *machine = MACHINE(spapr); 472 int i, ret; 473 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 474 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 475 uint32_t nr_lmbs = (machine->device_memory->base + 476 memory_region_size(&machine->device_memory->mr)) / 477 lmb_size; 478 uint32_t *int_buf, *cur_index, buf_len; 479 480 /* 481 * Allocate enough buffer size to fit in ibm,dynamic-memory 482 */ 483 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 484 cur_index = int_buf = g_malloc0(buf_len); 485 int_buf[0] = cpu_to_be32(nr_lmbs); 486 cur_index++; 487 for (i = 0; i < nr_lmbs; i++) { 488 uint64_t addr = i * lmb_size; 489 uint32_t *dynamic_memory = cur_index; 490 491 if (i >= device_lmb_start) { 492 SpaprDrc *drc; 493 494 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 495 g_assert(drc); 496 497 dynamic_memory[0] = cpu_to_be32(addr >> 32); 498 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 499 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 500 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 501 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 502 if (memory_region_present(get_system_memory(), addr)) { 503 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 504 } else { 505 dynamic_memory[5] = cpu_to_be32(0); 506 } 507 } else { 508 /* 509 * LMB information for RMA, boot time RAM and gap b/n RAM and 510 * device memory region -- all these are marked as reserved 511 * and as having no valid DRC. 512 */ 513 dynamic_memory[0] = cpu_to_be32(addr >> 32); 514 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 515 dynamic_memory[2] = cpu_to_be32(0); 516 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 517 dynamic_memory[4] = cpu_to_be32(-1); 518 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 519 SPAPR_LMB_FLAGS_DRC_INVALID); 520 } 521 522 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 523 } 524 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 525 g_free(int_buf); 526 if (ret < 0) { 527 return -1; 528 } 529 return 0; 530 } 531 532 /* 533 * Adds ibm,dynamic-reconfiguration-memory node. 534 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 535 * of this device tree node. 536 */ 537 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 538 void *fdt) 539 { 540 MachineState *machine = MACHINE(spapr); 541 int ret, offset; 542 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 543 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 544 cpu_to_be32(lmb_size & 0xffffffff)}; 545 MemoryDeviceInfoList *dimms = NULL; 546 547 /* 548 * Don't create the node if there is no device memory 549 */ 550 if (machine->ram_size == machine->maxram_size) { 551 return 0; 552 } 553 554 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 555 556 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 557 sizeof(prop_lmb_size)); 558 if (ret < 0) { 559 return ret; 560 } 561 562 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 563 if (ret < 0) { 564 return ret; 565 } 566 567 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 568 if (ret < 0) { 569 return ret; 570 } 571 572 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 573 dimms = qmp_memory_device_list(); 574 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 575 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 576 } else { 577 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 578 } 579 qapi_free_MemoryDeviceInfoList(dimms); 580 581 if (ret < 0) { 582 return ret; 583 } 584 585 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 586 587 return ret; 588 } 589 590 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 591 { 592 MachineState *machine = MACHINE(spapr); 593 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 594 hwaddr mem_start, node_size; 595 int i, nb_nodes = machine->numa_state->num_nodes; 596 NodeInfo *nodes = machine->numa_state->nodes; 597 598 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 599 if (!nodes[i].node_mem) { 600 continue; 601 } 602 if (mem_start >= machine->ram_size) { 603 node_size = 0; 604 } else { 605 node_size = nodes[i].node_mem; 606 if (node_size > machine->ram_size - mem_start) { 607 node_size = machine->ram_size - mem_start; 608 } 609 } 610 if (!mem_start) { 611 /* spapr_machine_init() checks for rma_size <= node0_size 612 * already */ 613 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 614 mem_start += spapr->rma_size; 615 node_size -= spapr->rma_size; 616 } 617 for ( ; node_size; ) { 618 hwaddr sizetmp = pow2floor(node_size); 619 620 /* mem_start != 0 here */ 621 if (ctzl(mem_start) < ctzl(sizetmp)) { 622 sizetmp = 1ULL << ctzl(mem_start); 623 } 624 625 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 626 node_size -= sizetmp; 627 mem_start += sizetmp; 628 } 629 } 630 631 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 632 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 633 int ret; 634 635 g_assert(smc->dr_lmb_enabled); 636 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 637 if (ret) { 638 return ret; 639 } 640 } 641 642 return 0; 643 } 644 645 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 646 SpaprMachineState *spapr) 647 { 648 MachineState *ms = MACHINE(spapr); 649 PowerPCCPU *cpu = POWERPC_CPU(cs); 650 CPUPPCState *env = &cpu->env; 651 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 652 int index = spapr_get_vcpu_id(cpu); 653 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 654 0xffffffff, 0xffffffff}; 655 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 656 : SPAPR_TIMEBASE_FREQ; 657 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 658 uint32_t page_sizes_prop[64]; 659 size_t page_sizes_prop_size; 660 unsigned int smp_threads = ms->smp.threads; 661 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 662 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 663 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 664 SpaprDrc *drc; 665 int drc_index; 666 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 667 int i; 668 669 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 670 if (drc) { 671 drc_index = spapr_drc_index(drc); 672 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 673 } 674 675 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 676 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 677 678 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 679 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 680 env->dcache_line_size))); 681 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 682 env->dcache_line_size))); 683 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 684 env->icache_line_size))); 685 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 686 env->icache_line_size))); 687 688 if (pcc->l1_dcache_size) { 689 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 690 pcc->l1_dcache_size))); 691 } else { 692 warn_report("Unknown L1 dcache size for cpu"); 693 } 694 if (pcc->l1_icache_size) { 695 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 696 pcc->l1_icache_size))); 697 } else { 698 warn_report("Unknown L1 icache size for cpu"); 699 } 700 701 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 702 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 703 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 704 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 705 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 706 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 707 708 if (env->spr_cb[SPR_PURR].oea_read) { 709 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 710 } 711 if (env->spr_cb[SPR_SPURR].oea_read) { 712 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 713 } 714 715 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 716 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 717 segs, sizeof(segs)))); 718 } 719 720 /* Advertise VSX (vector extensions) if available 721 * 1 == VMX / Altivec available 722 * 2 == VSX available 723 * 724 * Only CPUs for which we create core types in spapr_cpu_core.c 725 * are possible, and all of those have VMX */ 726 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 727 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 728 } else { 729 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 730 } 731 732 /* Advertise DFP (Decimal Floating Point) if available 733 * 0 / no property == no DFP 734 * 1 == DFP available */ 735 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 736 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 737 } 738 739 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 740 sizeof(page_sizes_prop)); 741 if (page_sizes_prop_size) { 742 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 743 page_sizes_prop, page_sizes_prop_size))); 744 } 745 746 spapr_dt_pa_features(spapr, cpu, fdt, offset); 747 748 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 749 cs->cpu_index / vcpus_per_socket))); 750 751 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 752 pft_size_prop, sizeof(pft_size_prop)))); 753 754 if (ms->numa_state->num_nodes > 1) { 755 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 756 } 757 758 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 759 760 if (pcc->radix_page_info) { 761 for (i = 0; i < pcc->radix_page_info->count; i++) { 762 radix_AP_encodings[i] = 763 cpu_to_be32(pcc->radix_page_info->entries[i]); 764 } 765 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 766 radix_AP_encodings, 767 pcc->radix_page_info->count * 768 sizeof(radix_AP_encodings[0])))); 769 } 770 771 /* 772 * We set this property to let the guest know that it can use the large 773 * decrementer and its width in bits. 774 */ 775 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 776 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 777 pcc->lrg_decr_bits))); 778 } 779 780 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 781 { 782 CPUState **rev; 783 CPUState *cs; 784 int n_cpus; 785 int cpus_offset; 786 int i; 787 788 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 789 _FDT(cpus_offset); 790 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 791 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 792 793 /* 794 * We walk the CPUs in reverse order to ensure that CPU DT nodes 795 * created by fdt_add_subnode() end up in the right order in FDT 796 * for the guest kernel the enumerate the CPUs correctly. 797 * 798 * The CPU list cannot be traversed in reverse order, so we need 799 * to do extra work. 800 */ 801 n_cpus = 0; 802 rev = NULL; 803 CPU_FOREACH(cs) { 804 rev = g_renew(CPUState *, rev, n_cpus + 1); 805 rev[n_cpus++] = cs; 806 } 807 808 for (i = n_cpus - 1; i >= 0; i--) { 809 CPUState *cs = rev[i]; 810 PowerPCCPU *cpu = POWERPC_CPU(cs); 811 int index = spapr_get_vcpu_id(cpu); 812 DeviceClass *dc = DEVICE_GET_CLASS(cs); 813 g_autofree char *nodename = NULL; 814 int offset; 815 816 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 817 continue; 818 } 819 820 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 821 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 822 _FDT(offset); 823 spapr_dt_cpu(cs, fdt, offset, spapr); 824 } 825 826 g_free(rev); 827 } 828 829 static int spapr_dt_rng(void *fdt) 830 { 831 int node; 832 int ret; 833 834 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 835 if (node <= 0) { 836 return -1; 837 } 838 ret = fdt_setprop_string(fdt, node, "device_type", 839 "ibm,platform-facilities"); 840 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 841 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 842 843 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 844 if (node <= 0) { 845 return -1; 846 } 847 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 848 849 return ret ? -1 : 0; 850 } 851 852 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 853 { 854 MachineState *ms = MACHINE(spapr); 855 int rtas; 856 GString *hypertas = g_string_sized_new(256); 857 GString *qemu_hypertas = g_string_sized_new(256); 858 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 859 memory_region_size(&MACHINE(spapr)->device_memory->mr); 860 uint32_t lrdr_capacity[] = { 861 cpu_to_be32(max_device_addr >> 32), 862 cpu_to_be32(max_device_addr & 0xffffffff), 863 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 864 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 865 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 866 }; 867 868 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 869 870 /* hypertas */ 871 add_str(hypertas, "hcall-pft"); 872 add_str(hypertas, "hcall-term"); 873 add_str(hypertas, "hcall-dabr"); 874 add_str(hypertas, "hcall-interrupt"); 875 add_str(hypertas, "hcall-tce"); 876 add_str(hypertas, "hcall-vio"); 877 add_str(hypertas, "hcall-splpar"); 878 add_str(hypertas, "hcall-join"); 879 add_str(hypertas, "hcall-bulk"); 880 add_str(hypertas, "hcall-set-mode"); 881 add_str(hypertas, "hcall-sprg0"); 882 add_str(hypertas, "hcall-copy"); 883 add_str(hypertas, "hcall-debug"); 884 add_str(hypertas, "hcall-vphn"); 885 add_str(qemu_hypertas, "hcall-memop1"); 886 887 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 888 add_str(hypertas, "hcall-multi-tce"); 889 } 890 891 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 892 add_str(hypertas, "hcall-hpt-resize"); 893 } 894 895 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 896 hypertas->str, hypertas->len)); 897 g_string_free(hypertas, TRUE); 898 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 899 qemu_hypertas->str, qemu_hypertas->len)); 900 g_string_free(qemu_hypertas, TRUE); 901 902 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 903 904 /* 905 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 906 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 907 * 908 * The system reset requirements are driven by existing Linux and PowerVM 909 * implementation which (contrary to PAPR) saves r3 in the error log 910 * structure like machine check, so Linux expects to find the saved r3 911 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 912 * does not look at the error value). 913 * 914 * System reset interrupts are not subject to interlock like machine 915 * check, so this memory area could be corrupted if the sreset is 916 * interrupted by a machine check (or vice versa) if it was shared. To 917 * prevent this, system reset uses per-CPU areas for the sreset save 918 * area. A system reset that interrupts a system reset handler could 919 * still overwrite this area, but Linux doesn't try to recover in that 920 * case anyway. 921 * 922 * The extra 8 bytes is required because Linux's FWNMI error log check 923 * is off-by-one. 924 */ 925 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_ERROR_LOG_MAX + 926 ms->smp.max_cpus * sizeof(uint64_t)*2 + sizeof(uint64_t))); 927 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 928 RTAS_ERROR_LOG_MAX)); 929 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 930 RTAS_EVENT_SCAN_RATE)); 931 932 g_assert(msi_nonbroken); 933 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 934 935 /* 936 * According to PAPR, rtas ibm,os-term does not guarantee a return 937 * back to the guest cpu. 938 * 939 * While an additional ibm,extended-os-term property indicates 940 * that rtas call return will always occur. Set this property. 941 */ 942 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 943 944 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 945 lrdr_capacity, sizeof(lrdr_capacity))); 946 947 spapr_dt_rtas_tokens(fdt, rtas); 948 } 949 950 /* 951 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 952 * and the XIVE features that the guest may request and thus the valid 953 * values for bytes 23..26 of option vector 5: 954 */ 955 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 956 int chosen) 957 { 958 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 959 960 char val[2 * 4] = { 961 23, 0x00, /* XICS / XIVE mode */ 962 24, 0x00, /* Hash/Radix, filled in below. */ 963 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 964 26, 0x40, /* Radix options: GTSE == yes. */ 965 }; 966 967 if (spapr->irq->xics && spapr->irq->xive) { 968 val[1] = SPAPR_OV5_XIVE_BOTH; 969 } else if (spapr->irq->xive) { 970 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 971 } else { 972 assert(spapr->irq->xics); 973 val[1] = SPAPR_OV5_XIVE_LEGACY; 974 } 975 976 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 977 first_ppc_cpu->compat_pvr)) { 978 /* 979 * If we're in a pre POWER9 compat mode then the guest should 980 * do hash and use the legacy interrupt mode 981 */ 982 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 983 val[3] = 0x00; /* Hash */ 984 } else if (kvm_enabled()) { 985 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 986 val[3] = 0x80; /* OV5_MMU_BOTH */ 987 } else if (kvmppc_has_cap_mmu_radix()) { 988 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 989 } else { 990 val[3] = 0x00; /* Hash */ 991 } 992 } else { 993 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 994 val[3] = 0xC0; 995 } 996 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 997 val, sizeof(val))); 998 } 999 1000 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1001 { 1002 MachineState *machine = MACHINE(spapr); 1003 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1004 int chosen; 1005 1006 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1007 1008 if (reset) { 1009 const char *boot_device = machine->boot_order; 1010 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1011 size_t cb = 0; 1012 char *bootlist = get_boot_devices_list(&cb); 1013 1014 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1015 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1016 machine->kernel_cmdline)); 1017 } 1018 1019 if (spapr->initrd_size) { 1020 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1021 spapr->initrd_base)); 1022 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1023 spapr->initrd_base + spapr->initrd_size)); 1024 } 1025 1026 if (spapr->kernel_size) { 1027 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1028 cpu_to_be64(spapr->kernel_size) }; 1029 1030 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1031 &kprop, sizeof(kprop))); 1032 if (spapr->kernel_le) { 1033 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1034 } 1035 } 1036 if (boot_menu) { 1037 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1038 } 1039 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1040 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1041 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1042 1043 if (cb && bootlist) { 1044 int i; 1045 1046 for (i = 0; i < cb; i++) { 1047 if (bootlist[i] == '\n') { 1048 bootlist[i] = ' '; 1049 } 1050 } 1051 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1052 } 1053 1054 if (boot_device && strlen(boot_device)) { 1055 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1056 } 1057 1058 if (!spapr->has_graphics && stdout_path) { 1059 /* 1060 * "linux,stdout-path" and "stdout" properties are 1061 * deprecated by linux kernel. New platforms should only 1062 * use the "stdout-path" property. Set the new property 1063 * and continue using older property to remain compatible 1064 * with the existing firmware. 1065 */ 1066 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1067 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1068 } 1069 1070 /* 1071 * We can deal with BAR reallocation just fine, advertise it 1072 * to the guest 1073 */ 1074 if (smc->linux_pci_probe) { 1075 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1076 } 1077 1078 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1079 1080 g_free(stdout_path); 1081 g_free(bootlist); 1082 } 1083 1084 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1085 } 1086 1087 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1088 { 1089 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1090 * KVM to work under pHyp with some guest co-operation */ 1091 int hypervisor; 1092 uint8_t hypercall[16]; 1093 1094 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1095 /* indicate KVM hypercall interface */ 1096 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1097 if (kvmppc_has_cap_fixup_hcalls()) { 1098 /* 1099 * Older KVM versions with older guest kernels were broken 1100 * with the magic page, don't allow the guest to map it. 1101 */ 1102 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1103 sizeof(hypercall))) { 1104 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1105 hypercall, sizeof(hypercall))); 1106 } 1107 } 1108 } 1109 1110 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1111 { 1112 MachineState *machine = MACHINE(spapr); 1113 MachineClass *mc = MACHINE_GET_CLASS(machine); 1114 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1115 uint32_t root_drc_type_mask = 0; 1116 int ret; 1117 void *fdt; 1118 SpaprPhbState *phb; 1119 char *buf; 1120 1121 fdt = g_malloc0(space); 1122 _FDT((fdt_create_empty_tree(fdt, space))); 1123 1124 /* Root node */ 1125 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1126 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1127 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1128 1129 /* Guest UUID & Name*/ 1130 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1131 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1132 if (qemu_uuid_set) { 1133 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1134 } 1135 g_free(buf); 1136 1137 if (qemu_get_vm_name()) { 1138 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1139 qemu_get_vm_name())); 1140 } 1141 1142 /* Host Model & Serial Number */ 1143 if (spapr->host_model) { 1144 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1145 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1146 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1147 g_free(buf); 1148 } 1149 1150 if (spapr->host_serial) { 1151 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1152 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1153 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1154 g_free(buf); 1155 } 1156 1157 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1158 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1159 1160 /* /interrupt controller */ 1161 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1162 1163 ret = spapr_dt_memory(spapr, fdt); 1164 if (ret < 0) { 1165 error_report("couldn't setup memory nodes in fdt"); 1166 exit(1); 1167 } 1168 1169 /* /vdevice */ 1170 spapr_dt_vdevice(spapr->vio_bus, fdt); 1171 1172 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1173 ret = spapr_dt_rng(fdt); 1174 if (ret < 0) { 1175 error_report("could not set up rng device in the fdt"); 1176 exit(1); 1177 } 1178 } 1179 1180 QLIST_FOREACH(phb, &spapr->phbs, list) { 1181 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1182 if (ret < 0) { 1183 error_report("couldn't setup PCI devices in fdt"); 1184 exit(1); 1185 } 1186 } 1187 1188 spapr_dt_cpus(fdt, spapr); 1189 1190 /* ibm,drc-indexes and friends */ 1191 if (smc->dr_lmb_enabled) { 1192 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; 1193 } 1194 if (smc->dr_phb_enabled) { 1195 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; 1196 } 1197 if (mc->nvdimm_supported) { 1198 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM; 1199 } 1200 if (root_drc_type_mask) { 1201 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask)); 1202 } 1203 1204 if (mc->has_hotpluggable_cpus) { 1205 int offset = fdt_path_offset(fdt, "/cpus"); 1206 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1207 if (ret < 0) { 1208 error_report("Couldn't set up CPU DR device tree properties"); 1209 exit(1); 1210 } 1211 } 1212 1213 /* /event-sources */ 1214 spapr_dt_events(spapr, fdt); 1215 1216 /* /rtas */ 1217 spapr_dt_rtas(spapr, fdt); 1218 1219 /* /chosen */ 1220 spapr_dt_chosen(spapr, fdt, reset); 1221 1222 /* /hypervisor */ 1223 if (kvm_enabled()) { 1224 spapr_dt_hypervisor(spapr, fdt); 1225 } 1226 1227 /* Build memory reserve map */ 1228 if (reset) { 1229 if (spapr->kernel_size) { 1230 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1231 spapr->kernel_size))); 1232 } 1233 if (spapr->initrd_size) { 1234 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1235 spapr->initrd_size))); 1236 } 1237 } 1238 1239 /* NVDIMM devices */ 1240 if (mc->nvdimm_supported) { 1241 spapr_dt_persistent_memory(spapr, fdt); 1242 } 1243 1244 return fdt; 1245 } 1246 1247 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1248 { 1249 SpaprMachineState *spapr = opaque; 1250 1251 return (addr & 0x0fffffff) + spapr->kernel_addr; 1252 } 1253 1254 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1255 PowerPCCPU *cpu) 1256 { 1257 CPUPPCState *env = &cpu->env; 1258 1259 /* The TCG path should also be holding the BQL at this point */ 1260 g_assert(qemu_mutex_iothread_locked()); 1261 1262 if (msr_pr) { 1263 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1264 env->gpr[3] = H_PRIVILEGE; 1265 } else { 1266 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1267 } 1268 } 1269 1270 struct LPCRSyncState { 1271 target_ulong value; 1272 target_ulong mask; 1273 }; 1274 1275 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1276 { 1277 struct LPCRSyncState *s = arg.host_ptr; 1278 PowerPCCPU *cpu = POWERPC_CPU(cs); 1279 CPUPPCState *env = &cpu->env; 1280 target_ulong lpcr; 1281 1282 cpu_synchronize_state(cs); 1283 lpcr = env->spr[SPR_LPCR]; 1284 lpcr &= ~s->mask; 1285 lpcr |= s->value; 1286 ppc_store_lpcr(cpu, lpcr); 1287 } 1288 1289 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1290 { 1291 CPUState *cs; 1292 struct LPCRSyncState s = { 1293 .value = value, 1294 .mask = mask 1295 }; 1296 CPU_FOREACH(cs) { 1297 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1298 } 1299 } 1300 1301 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1302 { 1303 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1304 1305 /* Copy PATE1:GR into PATE0:HR */ 1306 entry->dw0 = spapr->patb_entry & PATE0_HR; 1307 entry->dw1 = spapr->patb_entry; 1308 } 1309 1310 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1311 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1312 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1313 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1314 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1315 1316 /* 1317 * Get the fd to access the kernel htab, re-opening it if necessary 1318 */ 1319 static int get_htab_fd(SpaprMachineState *spapr) 1320 { 1321 Error *local_err = NULL; 1322 1323 if (spapr->htab_fd >= 0) { 1324 return spapr->htab_fd; 1325 } 1326 1327 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1328 if (spapr->htab_fd < 0) { 1329 error_report_err(local_err); 1330 } 1331 1332 return spapr->htab_fd; 1333 } 1334 1335 void close_htab_fd(SpaprMachineState *spapr) 1336 { 1337 if (spapr->htab_fd >= 0) { 1338 close(spapr->htab_fd); 1339 } 1340 spapr->htab_fd = -1; 1341 } 1342 1343 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1344 { 1345 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1346 1347 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1348 } 1349 1350 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1351 { 1352 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1353 1354 assert(kvm_enabled()); 1355 1356 if (!spapr->htab) { 1357 return 0; 1358 } 1359 1360 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1361 } 1362 1363 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1364 hwaddr ptex, int n) 1365 { 1366 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1367 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1368 1369 if (!spapr->htab) { 1370 /* 1371 * HTAB is controlled by KVM. Fetch into temporary buffer 1372 */ 1373 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1374 kvmppc_read_hptes(hptes, ptex, n); 1375 return hptes; 1376 } 1377 1378 /* 1379 * HTAB is controlled by QEMU. Just point to the internally 1380 * accessible PTEG. 1381 */ 1382 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1383 } 1384 1385 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1386 const ppc_hash_pte64_t *hptes, 1387 hwaddr ptex, int n) 1388 { 1389 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1390 1391 if (!spapr->htab) { 1392 g_free((void *)hptes); 1393 } 1394 1395 /* Nothing to do for qemu managed HPT */ 1396 } 1397 1398 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1399 uint64_t pte0, uint64_t pte1) 1400 { 1401 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1402 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1403 1404 if (!spapr->htab) { 1405 kvmppc_write_hpte(ptex, pte0, pte1); 1406 } else { 1407 if (pte0 & HPTE64_V_VALID) { 1408 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1409 /* 1410 * When setting valid, we write PTE1 first. This ensures 1411 * proper synchronization with the reading code in 1412 * ppc_hash64_pteg_search() 1413 */ 1414 smp_wmb(); 1415 stq_p(spapr->htab + offset, pte0); 1416 } else { 1417 stq_p(spapr->htab + offset, pte0); 1418 /* 1419 * When clearing it we set PTE0 first. This ensures proper 1420 * synchronization with the reading code in 1421 * ppc_hash64_pteg_search() 1422 */ 1423 smp_wmb(); 1424 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1425 } 1426 } 1427 } 1428 1429 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1430 uint64_t pte1) 1431 { 1432 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1433 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1434 1435 if (!spapr->htab) { 1436 /* There should always be a hash table when this is called */ 1437 error_report("spapr_hpte_set_c called with no hash table !"); 1438 return; 1439 } 1440 1441 /* The HW performs a non-atomic byte update */ 1442 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1443 } 1444 1445 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1446 uint64_t pte1) 1447 { 1448 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1449 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1450 1451 if (!spapr->htab) { 1452 /* There should always be a hash table when this is called */ 1453 error_report("spapr_hpte_set_r called with no hash table !"); 1454 return; 1455 } 1456 1457 /* The HW performs a non-atomic byte update */ 1458 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1459 } 1460 1461 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1462 { 1463 int shift; 1464 1465 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1466 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1467 * that's much more than is needed for Linux guests */ 1468 shift = ctz64(pow2ceil(ramsize)) - 7; 1469 shift = MAX(shift, 18); /* Minimum architected size */ 1470 shift = MIN(shift, 46); /* Maximum architected size */ 1471 return shift; 1472 } 1473 1474 void spapr_free_hpt(SpaprMachineState *spapr) 1475 { 1476 g_free(spapr->htab); 1477 spapr->htab = NULL; 1478 spapr->htab_shift = 0; 1479 close_htab_fd(spapr); 1480 } 1481 1482 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1483 { 1484 ERRP_GUARD(); 1485 long rc; 1486 1487 /* Clean up any HPT info from a previous boot */ 1488 spapr_free_hpt(spapr); 1489 1490 rc = kvmppc_reset_htab(shift); 1491 1492 if (rc == -EOPNOTSUPP) { 1493 error_setg(errp, "HPT not supported in nested guests"); 1494 return -EOPNOTSUPP; 1495 } 1496 1497 if (rc < 0) { 1498 /* kernel-side HPT needed, but couldn't allocate one */ 1499 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1500 shift); 1501 error_append_hint(errp, "Try smaller maxmem?\n"); 1502 return -errno; 1503 } else if (rc > 0) { 1504 /* kernel-side HPT allocated */ 1505 if (rc != shift) { 1506 error_setg(errp, 1507 "Requested order %d HPT, but kernel allocated order %ld", 1508 shift, rc); 1509 error_append_hint(errp, "Try smaller maxmem?\n"); 1510 return -ENOSPC; 1511 } 1512 1513 spapr->htab_shift = shift; 1514 spapr->htab = NULL; 1515 } else { 1516 /* kernel-side HPT not needed, allocate in userspace instead */ 1517 size_t size = 1ULL << shift; 1518 int i; 1519 1520 spapr->htab = qemu_memalign(size, size); 1521 memset(spapr->htab, 0, size); 1522 spapr->htab_shift = shift; 1523 1524 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1525 DIRTY_HPTE(HPTE(spapr->htab, i)); 1526 } 1527 } 1528 /* We're setting up a hash table, so that means we're not radix */ 1529 spapr->patb_entry = 0; 1530 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1531 return 0; 1532 } 1533 1534 void spapr_setup_hpt(SpaprMachineState *spapr) 1535 { 1536 int hpt_shift; 1537 1538 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1539 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1540 } else { 1541 uint64_t current_ram_size; 1542 1543 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1544 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1545 } 1546 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1547 1548 if (kvm_enabled()) { 1549 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1550 1551 /* Check our RMA fits in the possible VRMA */ 1552 if (vrma_limit < spapr->rma_size) { 1553 error_report("Unable to create %" HWADDR_PRIu 1554 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1555 spapr->rma_size / MiB, vrma_limit / MiB); 1556 exit(EXIT_FAILURE); 1557 } 1558 } 1559 } 1560 1561 static void spapr_machine_reset(MachineState *machine) 1562 { 1563 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1564 PowerPCCPU *first_ppc_cpu; 1565 hwaddr fdt_addr; 1566 void *fdt; 1567 int rc; 1568 1569 pef_kvm_reset(machine->cgs, &error_fatal); 1570 spapr_caps_apply(spapr); 1571 1572 first_ppc_cpu = POWERPC_CPU(first_cpu); 1573 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1574 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1575 spapr->max_compat_pvr)) { 1576 /* 1577 * If using KVM with radix mode available, VCPUs can be started 1578 * without a HPT because KVM will start them in radix mode. 1579 * Set the GR bit in PATE so that we know there is no HPT. 1580 */ 1581 spapr->patb_entry = PATE1_GR; 1582 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1583 } else { 1584 spapr_setup_hpt(spapr); 1585 } 1586 1587 qemu_devices_reset(); 1588 1589 spapr_ovec_cleanup(spapr->ov5_cas); 1590 spapr->ov5_cas = spapr_ovec_new(); 1591 1592 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1593 1594 /* 1595 * This is fixing some of the default configuration of the XIVE 1596 * devices. To be called after the reset of the machine devices. 1597 */ 1598 spapr_irq_reset(spapr, &error_fatal); 1599 1600 /* 1601 * There is no CAS under qtest. Simulate one to please the code that 1602 * depends on spapr->ov5_cas. This is especially needed to test device 1603 * unplug, so we do that before resetting the DRCs. 1604 */ 1605 if (qtest_enabled()) { 1606 spapr_ovec_cleanup(spapr->ov5_cas); 1607 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1608 } 1609 1610 /* DRC reset may cause a device to be unplugged. This will cause troubles 1611 * if this device is used by another device (eg, a running vhost backend 1612 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1613 * situations, we reset DRCs after all devices have been reset. 1614 */ 1615 spapr_drc_reset_all(spapr); 1616 1617 spapr_clear_pending_events(spapr); 1618 1619 /* 1620 * We place the device tree and RTAS just below either the top of the RMA, 1621 * or just below 2GB, whichever is lower, so that it can be 1622 * processed with 32-bit real mode code if necessary 1623 */ 1624 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; 1625 1626 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1627 1628 rc = fdt_pack(fdt); 1629 1630 /* Should only fail if we've built a corrupted tree */ 1631 assert(rc == 0); 1632 1633 /* Load the fdt */ 1634 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1635 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1636 g_free(spapr->fdt_blob); 1637 spapr->fdt_size = fdt_totalsize(fdt); 1638 spapr->fdt_initial_size = spapr->fdt_size; 1639 spapr->fdt_blob = fdt; 1640 1641 /* Set up the entry state */ 1642 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0); 1643 first_ppc_cpu->env.gpr[5] = 0; 1644 1645 spapr->fwnmi_system_reset_addr = -1; 1646 spapr->fwnmi_machine_check_addr = -1; 1647 spapr->fwnmi_machine_check_interlock = -1; 1648 1649 /* Signal all vCPUs waiting on this condition */ 1650 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1651 1652 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1653 } 1654 1655 static void spapr_create_nvram(SpaprMachineState *spapr) 1656 { 1657 DeviceState *dev = qdev_new("spapr-nvram"); 1658 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1659 1660 if (dinfo) { 1661 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1662 &error_fatal); 1663 } 1664 1665 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1666 1667 spapr->nvram = (struct SpaprNvram *)dev; 1668 } 1669 1670 static void spapr_rtc_create(SpaprMachineState *spapr) 1671 { 1672 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1673 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1674 &error_fatal, NULL); 1675 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1676 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1677 "date"); 1678 } 1679 1680 /* Returns whether we want to use VGA or not */ 1681 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1682 { 1683 switch (vga_interface_type) { 1684 case VGA_NONE: 1685 return false; 1686 case VGA_DEVICE: 1687 return true; 1688 case VGA_STD: 1689 case VGA_VIRTIO: 1690 case VGA_CIRRUS: 1691 return pci_vga_init(pci_bus) != NULL; 1692 default: 1693 error_setg(errp, 1694 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1695 return false; 1696 } 1697 } 1698 1699 static int spapr_pre_load(void *opaque) 1700 { 1701 int rc; 1702 1703 rc = spapr_caps_pre_load(opaque); 1704 if (rc) { 1705 return rc; 1706 } 1707 1708 return 0; 1709 } 1710 1711 static int spapr_post_load(void *opaque, int version_id) 1712 { 1713 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1714 int err = 0; 1715 1716 err = spapr_caps_post_migration(spapr); 1717 if (err) { 1718 return err; 1719 } 1720 1721 /* 1722 * In earlier versions, there was no separate qdev for the PAPR 1723 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1724 * So when migrating from those versions, poke the incoming offset 1725 * value into the RTC device 1726 */ 1727 if (version_id < 3) { 1728 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1729 if (err) { 1730 return err; 1731 } 1732 } 1733 1734 if (kvm_enabled() && spapr->patb_entry) { 1735 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1736 bool radix = !!(spapr->patb_entry & PATE1_GR); 1737 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1738 1739 /* 1740 * Update LPCR:HR and UPRT as they may not be set properly in 1741 * the stream 1742 */ 1743 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1744 LPCR_HR | LPCR_UPRT); 1745 1746 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1747 if (err) { 1748 error_report("Process table config unsupported by the host"); 1749 return -EINVAL; 1750 } 1751 } 1752 1753 err = spapr_irq_post_load(spapr, version_id); 1754 if (err) { 1755 return err; 1756 } 1757 1758 return err; 1759 } 1760 1761 static int spapr_pre_save(void *opaque) 1762 { 1763 int rc; 1764 1765 rc = spapr_caps_pre_save(opaque); 1766 if (rc) { 1767 return rc; 1768 } 1769 1770 return 0; 1771 } 1772 1773 static bool version_before_3(void *opaque, int version_id) 1774 { 1775 return version_id < 3; 1776 } 1777 1778 static bool spapr_pending_events_needed(void *opaque) 1779 { 1780 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1781 return !QTAILQ_EMPTY(&spapr->pending_events); 1782 } 1783 1784 static const VMStateDescription vmstate_spapr_event_entry = { 1785 .name = "spapr_event_log_entry", 1786 .version_id = 1, 1787 .minimum_version_id = 1, 1788 .fields = (VMStateField[]) { 1789 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1790 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1791 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1792 NULL, extended_length), 1793 VMSTATE_END_OF_LIST() 1794 }, 1795 }; 1796 1797 static const VMStateDescription vmstate_spapr_pending_events = { 1798 .name = "spapr_pending_events", 1799 .version_id = 1, 1800 .minimum_version_id = 1, 1801 .needed = spapr_pending_events_needed, 1802 .fields = (VMStateField[]) { 1803 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1804 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1805 VMSTATE_END_OF_LIST() 1806 }, 1807 }; 1808 1809 static bool spapr_ov5_cas_needed(void *opaque) 1810 { 1811 SpaprMachineState *spapr = opaque; 1812 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1813 bool cas_needed; 1814 1815 /* Prior to the introduction of SpaprOptionVector, we had two option 1816 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1817 * Both of these options encode machine topology into the device-tree 1818 * in such a way that the now-booted OS should still be able to interact 1819 * appropriately with QEMU regardless of what options were actually 1820 * negotiatied on the source side. 1821 * 1822 * As such, we can avoid migrating the CAS-negotiated options if these 1823 * are the only options available on the current machine/platform. 1824 * Since these are the only options available for pseries-2.7 and 1825 * earlier, this allows us to maintain old->new/new->old migration 1826 * compatibility. 1827 * 1828 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1829 * via default pseries-2.8 machines and explicit command-line parameters. 1830 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1831 * of the actual CAS-negotiated values to continue working properly. For 1832 * example, availability of memory unplug depends on knowing whether 1833 * OV5_HP_EVT was negotiated via CAS. 1834 * 1835 * Thus, for any cases where the set of available CAS-negotiatable 1836 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1837 * include the CAS-negotiated options in the migration stream, unless 1838 * if they affect boot time behaviour only. 1839 */ 1840 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1841 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1842 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1843 1844 /* We need extra information if we have any bits outside the mask 1845 * defined above */ 1846 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1847 1848 spapr_ovec_cleanup(ov5_mask); 1849 1850 return cas_needed; 1851 } 1852 1853 static const VMStateDescription vmstate_spapr_ov5_cas = { 1854 .name = "spapr_option_vector_ov5_cas", 1855 .version_id = 1, 1856 .minimum_version_id = 1, 1857 .needed = spapr_ov5_cas_needed, 1858 .fields = (VMStateField[]) { 1859 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1860 vmstate_spapr_ovec, SpaprOptionVector), 1861 VMSTATE_END_OF_LIST() 1862 }, 1863 }; 1864 1865 static bool spapr_patb_entry_needed(void *opaque) 1866 { 1867 SpaprMachineState *spapr = opaque; 1868 1869 return !!spapr->patb_entry; 1870 } 1871 1872 static const VMStateDescription vmstate_spapr_patb_entry = { 1873 .name = "spapr_patb_entry", 1874 .version_id = 1, 1875 .minimum_version_id = 1, 1876 .needed = spapr_patb_entry_needed, 1877 .fields = (VMStateField[]) { 1878 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1879 VMSTATE_END_OF_LIST() 1880 }, 1881 }; 1882 1883 static bool spapr_irq_map_needed(void *opaque) 1884 { 1885 SpaprMachineState *spapr = opaque; 1886 1887 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1888 } 1889 1890 static const VMStateDescription vmstate_spapr_irq_map = { 1891 .name = "spapr_irq_map", 1892 .version_id = 1, 1893 .minimum_version_id = 1, 1894 .needed = spapr_irq_map_needed, 1895 .fields = (VMStateField[]) { 1896 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1897 VMSTATE_END_OF_LIST() 1898 }, 1899 }; 1900 1901 static bool spapr_dtb_needed(void *opaque) 1902 { 1903 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1904 1905 return smc->update_dt_enabled; 1906 } 1907 1908 static int spapr_dtb_pre_load(void *opaque) 1909 { 1910 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1911 1912 g_free(spapr->fdt_blob); 1913 spapr->fdt_blob = NULL; 1914 spapr->fdt_size = 0; 1915 1916 return 0; 1917 } 1918 1919 static const VMStateDescription vmstate_spapr_dtb = { 1920 .name = "spapr_dtb", 1921 .version_id = 1, 1922 .minimum_version_id = 1, 1923 .needed = spapr_dtb_needed, 1924 .pre_load = spapr_dtb_pre_load, 1925 .fields = (VMStateField[]) { 1926 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1927 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1928 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1929 fdt_size), 1930 VMSTATE_END_OF_LIST() 1931 }, 1932 }; 1933 1934 static bool spapr_fwnmi_needed(void *opaque) 1935 { 1936 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1937 1938 return spapr->fwnmi_machine_check_addr != -1; 1939 } 1940 1941 static int spapr_fwnmi_pre_save(void *opaque) 1942 { 1943 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1944 1945 /* 1946 * Check if machine check handling is in progress and print a 1947 * warning message. 1948 */ 1949 if (spapr->fwnmi_machine_check_interlock != -1) { 1950 warn_report("A machine check is being handled during migration. The" 1951 "handler may run and log hardware error on the destination"); 1952 } 1953 1954 return 0; 1955 } 1956 1957 static const VMStateDescription vmstate_spapr_fwnmi = { 1958 .name = "spapr_fwnmi", 1959 .version_id = 1, 1960 .minimum_version_id = 1, 1961 .needed = spapr_fwnmi_needed, 1962 .pre_save = spapr_fwnmi_pre_save, 1963 .fields = (VMStateField[]) { 1964 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 1965 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 1966 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 1967 VMSTATE_END_OF_LIST() 1968 }, 1969 }; 1970 1971 static const VMStateDescription vmstate_spapr = { 1972 .name = "spapr", 1973 .version_id = 3, 1974 .minimum_version_id = 1, 1975 .pre_load = spapr_pre_load, 1976 .post_load = spapr_post_load, 1977 .pre_save = spapr_pre_save, 1978 .fields = (VMStateField[]) { 1979 /* used to be @next_irq */ 1980 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1981 1982 /* RTC offset */ 1983 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 1984 1985 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 1986 VMSTATE_END_OF_LIST() 1987 }, 1988 .subsections = (const VMStateDescription*[]) { 1989 &vmstate_spapr_ov5_cas, 1990 &vmstate_spapr_patb_entry, 1991 &vmstate_spapr_pending_events, 1992 &vmstate_spapr_cap_htm, 1993 &vmstate_spapr_cap_vsx, 1994 &vmstate_spapr_cap_dfp, 1995 &vmstate_spapr_cap_cfpc, 1996 &vmstate_spapr_cap_sbbc, 1997 &vmstate_spapr_cap_ibs, 1998 &vmstate_spapr_cap_hpt_maxpagesize, 1999 &vmstate_spapr_irq_map, 2000 &vmstate_spapr_cap_nested_kvm_hv, 2001 &vmstate_spapr_dtb, 2002 &vmstate_spapr_cap_large_decr, 2003 &vmstate_spapr_cap_ccf_assist, 2004 &vmstate_spapr_cap_fwnmi, 2005 &vmstate_spapr_fwnmi, 2006 NULL 2007 } 2008 }; 2009 2010 static int htab_save_setup(QEMUFile *f, void *opaque) 2011 { 2012 SpaprMachineState *spapr = opaque; 2013 2014 /* "Iteration" header */ 2015 if (!spapr->htab_shift) { 2016 qemu_put_be32(f, -1); 2017 } else { 2018 qemu_put_be32(f, spapr->htab_shift); 2019 } 2020 2021 if (spapr->htab) { 2022 spapr->htab_save_index = 0; 2023 spapr->htab_first_pass = true; 2024 } else { 2025 if (spapr->htab_shift) { 2026 assert(kvm_enabled()); 2027 } 2028 } 2029 2030 2031 return 0; 2032 } 2033 2034 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2035 int chunkstart, int n_valid, int n_invalid) 2036 { 2037 qemu_put_be32(f, chunkstart); 2038 qemu_put_be16(f, n_valid); 2039 qemu_put_be16(f, n_invalid); 2040 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2041 HASH_PTE_SIZE_64 * n_valid); 2042 } 2043 2044 static void htab_save_end_marker(QEMUFile *f) 2045 { 2046 qemu_put_be32(f, 0); 2047 qemu_put_be16(f, 0); 2048 qemu_put_be16(f, 0); 2049 } 2050 2051 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2052 int64_t max_ns) 2053 { 2054 bool has_timeout = max_ns != -1; 2055 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2056 int index = spapr->htab_save_index; 2057 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2058 2059 assert(spapr->htab_first_pass); 2060 2061 do { 2062 int chunkstart; 2063 2064 /* Consume invalid HPTEs */ 2065 while ((index < htabslots) 2066 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2067 CLEAN_HPTE(HPTE(spapr->htab, index)); 2068 index++; 2069 } 2070 2071 /* Consume valid HPTEs */ 2072 chunkstart = index; 2073 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2074 && HPTE_VALID(HPTE(spapr->htab, index))) { 2075 CLEAN_HPTE(HPTE(spapr->htab, index)); 2076 index++; 2077 } 2078 2079 if (index > chunkstart) { 2080 int n_valid = index - chunkstart; 2081 2082 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2083 2084 if (has_timeout && 2085 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2086 break; 2087 } 2088 } 2089 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2090 2091 if (index >= htabslots) { 2092 assert(index == htabslots); 2093 index = 0; 2094 spapr->htab_first_pass = false; 2095 } 2096 spapr->htab_save_index = index; 2097 } 2098 2099 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2100 int64_t max_ns) 2101 { 2102 bool final = max_ns < 0; 2103 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2104 int examined = 0, sent = 0; 2105 int index = spapr->htab_save_index; 2106 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2107 2108 assert(!spapr->htab_first_pass); 2109 2110 do { 2111 int chunkstart, invalidstart; 2112 2113 /* Consume non-dirty HPTEs */ 2114 while ((index < htabslots) 2115 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2116 index++; 2117 examined++; 2118 } 2119 2120 chunkstart = index; 2121 /* Consume valid dirty HPTEs */ 2122 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2123 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2124 && HPTE_VALID(HPTE(spapr->htab, index))) { 2125 CLEAN_HPTE(HPTE(spapr->htab, index)); 2126 index++; 2127 examined++; 2128 } 2129 2130 invalidstart = index; 2131 /* Consume invalid dirty HPTEs */ 2132 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2133 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2134 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2135 CLEAN_HPTE(HPTE(spapr->htab, index)); 2136 index++; 2137 examined++; 2138 } 2139 2140 if (index > chunkstart) { 2141 int n_valid = invalidstart - chunkstart; 2142 int n_invalid = index - invalidstart; 2143 2144 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2145 sent += index - chunkstart; 2146 2147 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2148 break; 2149 } 2150 } 2151 2152 if (examined >= htabslots) { 2153 break; 2154 } 2155 2156 if (index >= htabslots) { 2157 assert(index == htabslots); 2158 index = 0; 2159 } 2160 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2161 2162 if (index >= htabslots) { 2163 assert(index == htabslots); 2164 index = 0; 2165 } 2166 2167 spapr->htab_save_index = index; 2168 2169 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2170 } 2171 2172 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2173 #define MAX_KVM_BUF_SIZE 2048 2174 2175 static int htab_save_iterate(QEMUFile *f, void *opaque) 2176 { 2177 SpaprMachineState *spapr = opaque; 2178 int fd; 2179 int rc = 0; 2180 2181 /* Iteration header */ 2182 if (!spapr->htab_shift) { 2183 qemu_put_be32(f, -1); 2184 return 1; 2185 } else { 2186 qemu_put_be32(f, 0); 2187 } 2188 2189 if (!spapr->htab) { 2190 assert(kvm_enabled()); 2191 2192 fd = get_htab_fd(spapr); 2193 if (fd < 0) { 2194 return fd; 2195 } 2196 2197 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2198 if (rc < 0) { 2199 return rc; 2200 } 2201 } else if (spapr->htab_first_pass) { 2202 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2203 } else { 2204 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2205 } 2206 2207 htab_save_end_marker(f); 2208 2209 return rc; 2210 } 2211 2212 static int htab_save_complete(QEMUFile *f, void *opaque) 2213 { 2214 SpaprMachineState *spapr = opaque; 2215 int fd; 2216 2217 /* Iteration header */ 2218 if (!spapr->htab_shift) { 2219 qemu_put_be32(f, -1); 2220 return 0; 2221 } else { 2222 qemu_put_be32(f, 0); 2223 } 2224 2225 if (!spapr->htab) { 2226 int rc; 2227 2228 assert(kvm_enabled()); 2229 2230 fd = get_htab_fd(spapr); 2231 if (fd < 0) { 2232 return fd; 2233 } 2234 2235 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2236 if (rc < 0) { 2237 return rc; 2238 } 2239 } else { 2240 if (spapr->htab_first_pass) { 2241 htab_save_first_pass(f, spapr, -1); 2242 } 2243 htab_save_later_pass(f, spapr, -1); 2244 } 2245 2246 /* End marker */ 2247 htab_save_end_marker(f); 2248 2249 return 0; 2250 } 2251 2252 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2253 { 2254 SpaprMachineState *spapr = opaque; 2255 uint32_t section_hdr; 2256 int fd = -1; 2257 Error *local_err = NULL; 2258 2259 if (version_id < 1 || version_id > 1) { 2260 error_report("htab_load() bad version"); 2261 return -EINVAL; 2262 } 2263 2264 section_hdr = qemu_get_be32(f); 2265 2266 if (section_hdr == -1) { 2267 spapr_free_hpt(spapr); 2268 return 0; 2269 } 2270 2271 if (section_hdr) { 2272 int ret; 2273 2274 /* First section gives the htab size */ 2275 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2276 if (ret < 0) { 2277 error_report_err(local_err); 2278 return ret; 2279 } 2280 return 0; 2281 } 2282 2283 if (!spapr->htab) { 2284 assert(kvm_enabled()); 2285 2286 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2287 if (fd < 0) { 2288 error_report_err(local_err); 2289 return fd; 2290 } 2291 } 2292 2293 while (true) { 2294 uint32_t index; 2295 uint16_t n_valid, n_invalid; 2296 2297 index = qemu_get_be32(f); 2298 n_valid = qemu_get_be16(f); 2299 n_invalid = qemu_get_be16(f); 2300 2301 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2302 /* End of Stream */ 2303 break; 2304 } 2305 2306 if ((index + n_valid + n_invalid) > 2307 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2308 /* Bad index in stream */ 2309 error_report( 2310 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2311 index, n_valid, n_invalid, spapr->htab_shift); 2312 return -EINVAL; 2313 } 2314 2315 if (spapr->htab) { 2316 if (n_valid) { 2317 qemu_get_buffer(f, HPTE(spapr->htab, index), 2318 HASH_PTE_SIZE_64 * n_valid); 2319 } 2320 if (n_invalid) { 2321 memset(HPTE(spapr->htab, index + n_valid), 0, 2322 HASH_PTE_SIZE_64 * n_invalid); 2323 } 2324 } else { 2325 int rc; 2326 2327 assert(fd >= 0); 2328 2329 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2330 &local_err); 2331 if (rc < 0) { 2332 error_report_err(local_err); 2333 return rc; 2334 } 2335 } 2336 } 2337 2338 if (!spapr->htab) { 2339 assert(fd >= 0); 2340 close(fd); 2341 } 2342 2343 return 0; 2344 } 2345 2346 static void htab_save_cleanup(void *opaque) 2347 { 2348 SpaprMachineState *spapr = opaque; 2349 2350 close_htab_fd(spapr); 2351 } 2352 2353 static SaveVMHandlers savevm_htab_handlers = { 2354 .save_setup = htab_save_setup, 2355 .save_live_iterate = htab_save_iterate, 2356 .save_live_complete_precopy = htab_save_complete, 2357 .save_cleanup = htab_save_cleanup, 2358 .load_state = htab_load, 2359 }; 2360 2361 static void spapr_boot_set(void *opaque, const char *boot_device, 2362 Error **errp) 2363 { 2364 MachineState *machine = MACHINE(opaque); 2365 machine->boot_order = g_strdup(boot_device); 2366 } 2367 2368 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2369 { 2370 MachineState *machine = MACHINE(spapr); 2371 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2372 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2373 int i; 2374 2375 for (i = 0; i < nr_lmbs; i++) { 2376 uint64_t addr; 2377 2378 addr = i * lmb_size + machine->device_memory->base; 2379 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2380 addr / lmb_size); 2381 } 2382 } 2383 2384 /* 2385 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2386 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2387 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2388 */ 2389 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2390 { 2391 int i; 2392 2393 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2394 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2395 " is not aligned to %" PRIu64 " MiB", 2396 machine->ram_size, 2397 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2398 return; 2399 } 2400 2401 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2402 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2403 " is not aligned to %" PRIu64 " MiB", 2404 machine->ram_size, 2405 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2406 return; 2407 } 2408 2409 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2410 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2411 error_setg(errp, 2412 "Node %d memory size 0x%" PRIx64 2413 " is not aligned to %" PRIu64 " MiB", 2414 i, machine->numa_state->nodes[i].node_mem, 2415 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2416 return; 2417 } 2418 } 2419 } 2420 2421 /* find cpu slot in machine->possible_cpus by core_id */ 2422 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2423 { 2424 int index = id / ms->smp.threads; 2425 2426 if (index >= ms->possible_cpus->len) { 2427 return NULL; 2428 } 2429 if (idx) { 2430 *idx = index; 2431 } 2432 return &ms->possible_cpus->cpus[index]; 2433 } 2434 2435 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2436 { 2437 MachineState *ms = MACHINE(spapr); 2438 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2439 Error *local_err = NULL; 2440 bool vsmt_user = !!spapr->vsmt; 2441 int kvm_smt = kvmppc_smt_threads(); 2442 int ret; 2443 unsigned int smp_threads = ms->smp.threads; 2444 2445 if (!kvm_enabled() && (smp_threads > 1)) { 2446 error_setg(errp, "TCG cannot support more than 1 thread/core " 2447 "on a pseries machine"); 2448 return; 2449 } 2450 if (!is_power_of_2(smp_threads)) { 2451 error_setg(errp, "Cannot support %d threads/core on a pseries " 2452 "machine because it must be a power of 2", smp_threads); 2453 return; 2454 } 2455 2456 /* Detemine the VSMT mode to use: */ 2457 if (vsmt_user) { 2458 if (spapr->vsmt < smp_threads) { 2459 error_setg(errp, "Cannot support VSMT mode %d" 2460 " because it must be >= threads/core (%d)", 2461 spapr->vsmt, smp_threads); 2462 return; 2463 } 2464 /* In this case, spapr->vsmt has been set by the command line */ 2465 } else if (!smc->smp_threads_vsmt) { 2466 /* 2467 * Default VSMT value is tricky, because we need it to be as 2468 * consistent as possible (for migration), but this requires 2469 * changing it for at least some existing cases. We pick 8 as 2470 * the value that we'd get with KVM on POWER8, the 2471 * overwhelmingly common case in production systems. 2472 */ 2473 spapr->vsmt = MAX(8, smp_threads); 2474 } else { 2475 spapr->vsmt = smp_threads; 2476 } 2477 2478 /* KVM: If necessary, set the SMT mode: */ 2479 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2480 ret = kvmppc_set_smt_threads(spapr->vsmt); 2481 if (ret) { 2482 /* Looks like KVM isn't able to change VSMT mode */ 2483 error_setg(&local_err, 2484 "Failed to set KVM's VSMT mode to %d (errno %d)", 2485 spapr->vsmt, ret); 2486 /* We can live with that if the default one is big enough 2487 * for the number of threads, and a submultiple of the one 2488 * we want. In this case we'll waste some vcpu ids, but 2489 * behaviour will be correct */ 2490 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2491 warn_report_err(local_err); 2492 } else { 2493 if (!vsmt_user) { 2494 error_append_hint(&local_err, 2495 "On PPC, a VM with %d threads/core" 2496 " on a host with %d threads/core" 2497 " requires the use of VSMT mode %d.\n", 2498 smp_threads, kvm_smt, spapr->vsmt); 2499 } 2500 kvmppc_error_append_smt_possible_hint(&local_err); 2501 error_propagate(errp, local_err); 2502 } 2503 } 2504 } 2505 /* else TCG: nothing to do currently */ 2506 } 2507 2508 static void spapr_init_cpus(SpaprMachineState *spapr) 2509 { 2510 MachineState *machine = MACHINE(spapr); 2511 MachineClass *mc = MACHINE_GET_CLASS(machine); 2512 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2513 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2514 const CPUArchIdList *possible_cpus; 2515 unsigned int smp_cpus = machine->smp.cpus; 2516 unsigned int smp_threads = machine->smp.threads; 2517 unsigned int max_cpus = machine->smp.max_cpus; 2518 int boot_cores_nr = smp_cpus / smp_threads; 2519 int i; 2520 2521 possible_cpus = mc->possible_cpu_arch_ids(machine); 2522 if (mc->has_hotpluggable_cpus) { 2523 if (smp_cpus % smp_threads) { 2524 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2525 smp_cpus, smp_threads); 2526 exit(1); 2527 } 2528 if (max_cpus % smp_threads) { 2529 error_report("max_cpus (%u) must be multiple of threads (%u)", 2530 max_cpus, smp_threads); 2531 exit(1); 2532 } 2533 } else { 2534 if (max_cpus != smp_cpus) { 2535 error_report("This machine version does not support CPU hotplug"); 2536 exit(1); 2537 } 2538 boot_cores_nr = possible_cpus->len; 2539 } 2540 2541 if (smc->pre_2_10_has_unused_icps) { 2542 int i; 2543 2544 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2545 /* Dummy entries get deregistered when real ICPState objects 2546 * are registered during CPU core hotplug. 2547 */ 2548 pre_2_10_vmstate_register_dummy_icp(i); 2549 } 2550 } 2551 2552 for (i = 0; i < possible_cpus->len; i++) { 2553 int core_id = i * smp_threads; 2554 2555 if (mc->has_hotpluggable_cpus) { 2556 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2557 spapr_vcpu_id(spapr, core_id)); 2558 } 2559 2560 if (i < boot_cores_nr) { 2561 Object *core = object_new(type); 2562 int nr_threads = smp_threads; 2563 2564 /* Handle the partially filled core for older machine types */ 2565 if ((i + 1) * smp_threads >= smp_cpus) { 2566 nr_threads = smp_cpus - i * smp_threads; 2567 } 2568 2569 object_property_set_int(core, "nr-threads", nr_threads, 2570 &error_fatal); 2571 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2572 &error_fatal); 2573 qdev_realize(DEVICE(core), NULL, &error_fatal); 2574 2575 object_unref(core); 2576 } 2577 } 2578 } 2579 2580 static PCIHostState *spapr_create_default_phb(void) 2581 { 2582 DeviceState *dev; 2583 2584 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2585 qdev_prop_set_uint32(dev, "index", 0); 2586 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2587 2588 return PCI_HOST_BRIDGE(dev); 2589 } 2590 2591 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2592 { 2593 MachineState *machine = MACHINE(spapr); 2594 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2595 hwaddr rma_size = machine->ram_size; 2596 hwaddr node0_size = spapr_node0_size(machine); 2597 2598 /* RMA has to fit in the first NUMA node */ 2599 rma_size = MIN(rma_size, node0_size); 2600 2601 /* 2602 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2603 * never exceed that 2604 */ 2605 rma_size = MIN(rma_size, 1 * TiB); 2606 2607 /* 2608 * Clamp the RMA size based on machine type. This is for 2609 * migration compatibility with older qemu versions, which limited 2610 * the RMA size for complicated and mostly bad reasons. 2611 */ 2612 if (smc->rma_limit) { 2613 rma_size = MIN(rma_size, smc->rma_limit); 2614 } 2615 2616 if (rma_size < MIN_RMA_SLOF) { 2617 error_setg(errp, 2618 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2619 "ldMiB guest RMA (Real Mode Area memory)", 2620 MIN_RMA_SLOF / MiB); 2621 return 0; 2622 } 2623 2624 return rma_size; 2625 } 2626 2627 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2628 { 2629 MachineState *machine = MACHINE(spapr); 2630 int i; 2631 2632 for (i = 0; i < machine->ram_slots; i++) { 2633 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2634 } 2635 } 2636 2637 /* pSeries LPAR / sPAPR hardware init */ 2638 static void spapr_machine_init(MachineState *machine) 2639 { 2640 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2641 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2642 MachineClass *mc = MACHINE_GET_CLASS(machine); 2643 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 2644 const char *kernel_filename = machine->kernel_filename; 2645 const char *initrd_filename = machine->initrd_filename; 2646 PCIHostState *phb; 2647 int i; 2648 MemoryRegion *sysmem = get_system_memory(); 2649 long load_limit, fw_size; 2650 char *filename; 2651 Error *resize_hpt_err = NULL; 2652 2653 /* 2654 * if Secure VM (PEF) support is configured, then initialize it 2655 */ 2656 pef_kvm_init(machine->cgs, &error_fatal); 2657 2658 msi_nonbroken = true; 2659 2660 QLIST_INIT(&spapr->phbs); 2661 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2662 2663 /* Determine capabilities to run with */ 2664 spapr_caps_init(spapr); 2665 2666 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2667 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2668 /* 2669 * If the user explicitly requested a mode we should either 2670 * supply it, or fail completely (which we do below). But if 2671 * it's not set explicitly, we reset our mode to something 2672 * that works 2673 */ 2674 if (resize_hpt_err) { 2675 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2676 error_free(resize_hpt_err); 2677 resize_hpt_err = NULL; 2678 } else { 2679 spapr->resize_hpt = smc->resize_hpt_default; 2680 } 2681 } 2682 2683 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2684 2685 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2686 /* 2687 * User requested HPT resize, but this host can't supply it. Bail out 2688 */ 2689 error_report_err(resize_hpt_err); 2690 exit(1); 2691 } 2692 error_free(resize_hpt_err); 2693 2694 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2695 2696 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2697 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2698 2699 /* 2700 * VSMT must be set in order to be able to compute VCPU ids, ie to 2701 * call spapr_max_server_number() or spapr_vcpu_id(). 2702 */ 2703 spapr_set_vsmt_mode(spapr, &error_fatal); 2704 2705 /* Set up Interrupt Controller before we create the VCPUs */ 2706 spapr_irq_init(spapr, &error_fatal); 2707 2708 /* Set up containers for ibm,client-architecture-support negotiated options 2709 */ 2710 spapr->ov5 = spapr_ovec_new(); 2711 spapr->ov5_cas = spapr_ovec_new(); 2712 2713 if (smc->dr_lmb_enabled) { 2714 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2715 spapr_validate_node_memory(machine, &error_fatal); 2716 } 2717 2718 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2719 2720 /* advertise support for dedicated HP event source to guests */ 2721 if (spapr->use_hotplug_event_source) { 2722 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2723 } 2724 2725 /* advertise support for HPT resizing */ 2726 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2727 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2728 } 2729 2730 /* advertise support for ibm,dyamic-memory-v2 */ 2731 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2732 2733 /* advertise XIVE on POWER9 machines */ 2734 if (spapr->irq->xive) { 2735 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2736 } 2737 2738 /* init CPUs */ 2739 spapr_init_cpus(spapr); 2740 2741 /* 2742 * check we don't have a memory-less/cpu-less NUMA node 2743 * Firmware relies on the existing memory/cpu topology to provide the 2744 * NUMA topology to the kernel. 2745 * And the linux kernel needs to know the NUMA topology at start 2746 * to be able to hotplug CPUs later. 2747 */ 2748 if (machine->numa_state->num_nodes) { 2749 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2750 /* check for memory-less node */ 2751 if (machine->numa_state->nodes[i].node_mem == 0) { 2752 CPUState *cs; 2753 int found = 0; 2754 /* check for cpu-less node */ 2755 CPU_FOREACH(cs) { 2756 PowerPCCPU *cpu = POWERPC_CPU(cs); 2757 if (cpu->node_id == i) { 2758 found = 1; 2759 break; 2760 } 2761 } 2762 /* memory-less and cpu-less node */ 2763 if (!found) { 2764 error_report( 2765 "Memory-less/cpu-less nodes are not supported (node %d)", 2766 i); 2767 exit(1); 2768 } 2769 } 2770 } 2771 2772 } 2773 2774 spapr->gpu_numa_id = spapr_numa_initial_nvgpu_numa_id(machine); 2775 2776 /* Init numa_assoc_array */ 2777 spapr_numa_associativity_init(spapr, machine); 2778 2779 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2780 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2781 spapr->max_compat_pvr)) { 2782 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2783 /* KVM and TCG always allow GTSE with radix... */ 2784 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2785 } 2786 /* ... but not with hash (currently). */ 2787 2788 if (kvm_enabled()) { 2789 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2790 kvmppc_enable_logical_ci_hcalls(); 2791 kvmppc_enable_set_mode_hcall(); 2792 2793 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2794 kvmppc_enable_clear_ref_mod_hcalls(); 2795 2796 /* Enable H_PAGE_INIT */ 2797 kvmppc_enable_h_page_init(); 2798 } 2799 2800 /* map RAM */ 2801 memory_region_add_subregion(sysmem, 0, machine->ram); 2802 2803 /* always allocate the device memory information */ 2804 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2805 2806 /* initialize hotplug memory address space */ 2807 if (machine->ram_size < machine->maxram_size) { 2808 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2809 /* 2810 * Limit the number of hotpluggable memory slots to half the number 2811 * slots that KVM supports, leaving the other half for PCI and other 2812 * devices. However ensure that number of slots doesn't drop below 32. 2813 */ 2814 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2815 SPAPR_MAX_RAM_SLOTS; 2816 2817 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2818 max_memslots = SPAPR_MAX_RAM_SLOTS; 2819 } 2820 if (machine->ram_slots > max_memslots) { 2821 error_report("Specified number of memory slots %" 2822 PRIu64" exceeds max supported %d", 2823 machine->ram_slots, max_memslots); 2824 exit(1); 2825 } 2826 2827 machine->device_memory->base = ROUND_UP(machine->ram_size, 2828 SPAPR_DEVICE_MEM_ALIGN); 2829 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2830 "device-memory", device_mem_size); 2831 memory_region_add_subregion(sysmem, machine->device_memory->base, 2832 &machine->device_memory->mr); 2833 } 2834 2835 if (smc->dr_lmb_enabled) { 2836 spapr_create_lmb_dr_connectors(spapr); 2837 } 2838 2839 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { 2840 /* Create the error string for live migration blocker */ 2841 error_setg(&spapr->fwnmi_migration_blocker, 2842 "A machine check is being handled during migration. The handler" 2843 "may run and log hardware error on the destination"); 2844 } 2845 2846 if (mc->nvdimm_supported) { 2847 spapr_create_nvdimm_dr_connectors(spapr); 2848 } 2849 2850 /* Set up RTAS event infrastructure */ 2851 spapr_events_init(spapr); 2852 2853 /* Set up the RTC RTAS interfaces */ 2854 spapr_rtc_create(spapr); 2855 2856 /* Set up VIO bus */ 2857 spapr->vio_bus = spapr_vio_bus_init(); 2858 2859 for (i = 0; serial_hd(i); i++) { 2860 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2861 } 2862 2863 /* We always have at least the nvram device on VIO */ 2864 spapr_create_nvram(spapr); 2865 2866 /* 2867 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2868 * connectors (described in root DT node's "ibm,drc-types" property) 2869 * are pre-initialized here. additional child connectors (such as 2870 * connectors for a PHBs PCI slots) are added as needed during their 2871 * parent's realization. 2872 */ 2873 if (smc->dr_phb_enabled) { 2874 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2875 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2876 } 2877 } 2878 2879 /* Set up PCI */ 2880 spapr_pci_rtas_init(); 2881 2882 phb = spapr_create_default_phb(); 2883 2884 for (i = 0; i < nb_nics; i++) { 2885 NICInfo *nd = &nd_table[i]; 2886 2887 if (!nd->model) { 2888 nd->model = g_strdup("spapr-vlan"); 2889 } 2890 2891 if (g_str_equal(nd->model, "spapr-vlan") || 2892 g_str_equal(nd->model, "ibmveth")) { 2893 spapr_vlan_create(spapr->vio_bus, nd); 2894 } else { 2895 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2896 } 2897 } 2898 2899 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2900 spapr_vscsi_create(spapr->vio_bus); 2901 } 2902 2903 /* Graphics */ 2904 if (spapr_vga_init(phb->bus, &error_fatal)) { 2905 spapr->has_graphics = true; 2906 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2907 } 2908 2909 if (machine->usb) { 2910 if (smc->use_ohci_by_default) { 2911 pci_create_simple(phb->bus, -1, "pci-ohci"); 2912 } else { 2913 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2914 } 2915 2916 if (spapr->has_graphics) { 2917 USBBus *usb_bus = usb_bus_find(-1); 2918 2919 usb_create_simple(usb_bus, "usb-kbd"); 2920 usb_create_simple(usb_bus, "usb-mouse"); 2921 } 2922 } 2923 2924 if (kernel_filename) { 2925 spapr->kernel_size = load_elf(kernel_filename, NULL, 2926 translate_kernel_address, spapr, 2927 NULL, NULL, NULL, NULL, 1, 2928 PPC_ELF_MACHINE, 0, 0); 2929 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2930 spapr->kernel_size = load_elf(kernel_filename, NULL, 2931 translate_kernel_address, spapr, 2932 NULL, NULL, NULL, NULL, 0, 2933 PPC_ELF_MACHINE, 0, 0); 2934 spapr->kernel_le = spapr->kernel_size > 0; 2935 } 2936 if (spapr->kernel_size < 0) { 2937 error_report("error loading %s: %s", kernel_filename, 2938 load_elf_strerror(spapr->kernel_size)); 2939 exit(1); 2940 } 2941 2942 /* load initrd */ 2943 if (initrd_filename) { 2944 /* Try to locate the initrd in the gap between the kernel 2945 * and the firmware. Add a bit of space just in case 2946 */ 2947 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 2948 + 0x1ffff) & ~0xffff; 2949 spapr->initrd_size = load_image_targphys(initrd_filename, 2950 spapr->initrd_base, 2951 load_limit 2952 - spapr->initrd_base); 2953 if (spapr->initrd_size < 0) { 2954 error_report("could not load initial ram disk '%s'", 2955 initrd_filename); 2956 exit(1); 2957 } 2958 } 2959 } 2960 2961 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2962 if (!filename) { 2963 error_report("Could not find LPAR firmware '%s'", bios_name); 2964 exit(1); 2965 } 2966 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2967 if (fw_size <= 0) { 2968 error_report("Could not load LPAR firmware '%s'", filename); 2969 exit(1); 2970 } 2971 g_free(filename); 2972 2973 /* FIXME: Should register things through the MachineState's qdev 2974 * interface, this is a legacy from the sPAPREnvironment structure 2975 * which predated MachineState but had a similar function */ 2976 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2977 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 2978 &savevm_htab_handlers, spapr); 2979 2980 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 2981 2982 qemu_register_boot_set(spapr_boot_set, spapr); 2983 2984 /* 2985 * Nothing needs to be done to resume a suspended guest because 2986 * suspending does not change the machine state, so no need for 2987 * a ->wakeup method. 2988 */ 2989 qemu_register_wakeup_support(); 2990 2991 if (kvm_enabled()) { 2992 /* to stop and start vmclock */ 2993 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2994 &spapr->tb); 2995 2996 kvmppc_spapr_enable_inkernel_multitce(); 2997 } 2998 2999 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3000 } 3001 3002 #define DEFAULT_KVM_TYPE "auto" 3003 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3004 { 3005 /* 3006 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to 3007 * accomodate the 'HV' and 'PV' formats that exists in the 3008 * wild. The 'auto' mode is being introduced already as 3009 * lower-case, thus we don't need to bother checking for 3010 * "AUTO". 3011 */ 3012 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) { 3013 return 0; 3014 } 3015 3016 if (!g_ascii_strcasecmp(vm_type, "hv")) { 3017 return 1; 3018 } 3019 3020 if (!g_ascii_strcasecmp(vm_type, "pr")) { 3021 return 2; 3022 } 3023 3024 error_report("Unknown kvm-type specified '%s'", vm_type); 3025 exit(1); 3026 } 3027 3028 /* 3029 * Implementation of an interface to adjust firmware path 3030 * for the bootindex property handling. 3031 */ 3032 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3033 DeviceState *dev) 3034 { 3035 #define CAST(type, obj, name) \ 3036 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3037 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3038 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3039 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3040 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3041 3042 if (d) { 3043 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3044 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3045 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3046 3047 if (spapr) { 3048 /* 3049 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3050 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3051 * 0x8000 | (target << 8) | (bus << 5) | lun 3052 * (see the "Logical unit addressing format" table in SAM5) 3053 */ 3054 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3055 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3056 (uint64_t)id << 48); 3057 } else if (virtio) { 3058 /* 3059 * We use SRP luns of the form 01000000 | (target << 8) | lun 3060 * in the top 32 bits of the 64-bit LUN 3061 * Note: the quote above is from SLOF and it is wrong, 3062 * the actual binding is: 3063 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3064 */ 3065 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3066 if (d->lun >= 256) { 3067 /* Use the LUN "flat space addressing method" */ 3068 id |= 0x4000; 3069 } 3070 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3071 (uint64_t)id << 32); 3072 } else if (usb) { 3073 /* 3074 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3075 * in the top 32 bits of the 64-bit LUN 3076 */ 3077 unsigned usb_port = atoi(usb->port->path); 3078 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3079 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3080 (uint64_t)id << 32); 3081 } 3082 } 3083 3084 /* 3085 * SLOF probes the USB devices, and if it recognizes that the device is a 3086 * storage device, it changes its name to "storage" instead of "usb-host", 3087 * and additionally adds a child node for the SCSI LUN, so the correct 3088 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3089 */ 3090 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3091 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3092 if (usb_host_dev_is_scsi_storage(usbdev)) { 3093 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3094 } 3095 } 3096 3097 if (phb) { 3098 /* Replace "pci" with "pci@800000020000000" */ 3099 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3100 } 3101 3102 if (vsc) { 3103 /* Same logic as virtio above */ 3104 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3105 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3106 } 3107 3108 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3109 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3110 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3111 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3112 } 3113 3114 if (pcidev) { 3115 return spapr_pci_fw_dev_name(pcidev); 3116 } 3117 3118 return NULL; 3119 } 3120 3121 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3122 { 3123 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3124 3125 return g_strdup(spapr->kvm_type); 3126 } 3127 3128 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3129 { 3130 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3131 3132 g_free(spapr->kvm_type); 3133 spapr->kvm_type = g_strdup(value); 3134 } 3135 3136 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3137 { 3138 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3139 3140 return spapr->use_hotplug_event_source; 3141 } 3142 3143 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3144 Error **errp) 3145 { 3146 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3147 3148 spapr->use_hotplug_event_source = value; 3149 } 3150 3151 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3152 { 3153 return true; 3154 } 3155 3156 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3157 { 3158 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3159 3160 switch (spapr->resize_hpt) { 3161 case SPAPR_RESIZE_HPT_DEFAULT: 3162 return g_strdup("default"); 3163 case SPAPR_RESIZE_HPT_DISABLED: 3164 return g_strdup("disabled"); 3165 case SPAPR_RESIZE_HPT_ENABLED: 3166 return g_strdup("enabled"); 3167 case SPAPR_RESIZE_HPT_REQUIRED: 3168 return g_strdup("required"); 3169 } 3170 g_assert_not_reached(); 3171 } 3172 3173 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3174 { 3175 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3176 3177 if (strcmp(value, "default") == 0) { 3178 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3179 } else if (strcmp(value, "disabled") == 0) { 3180 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3181 } else if (strcmp(value, "enabled") == 0) { 3182 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3183 } else if (strcmp(value, "required") == 0) { 3184 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3185 } else { 3186 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3187 } 3188 } 3189 3190 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3191 { 3192 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3193 3194 if (spapr->irq == &spapr_irq_xics_legacy) { 3195 return g_strdup("legacy"); 3196 } else if (spapr->irq == &spapr_irq_xics) { 3197 return g_strdup("xics"); 3198 } else if (spapr->irq == &spapr_irq_xive) { 3199 return g_strdup("xive"); 3200 } else if (spapr->irq == &spapr_irq_dual) { 3201 return g_strdup("dual"); 3202 } 3203 g_assert_not_reached(); 3204 } 3205 3206 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3207 { 3208 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3209 3210 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3211 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3212 return; 3213 } 3214 3215 /* The legacy IRQ backend can not be set */ 3216 if (strcmp(value, "xics") == 0) { 3217 spapr->irq = &spapr_irq_xics; 3218 } else if (strcmp(value, "xive") == 0) { 3219 spapr->irq = &spapr_irq_xive; 3220 } else if (strcmp(value, "dual") == 0) { 3221 spapr->irq = &spapr_irq_dual; 3222 } else { 3223 error_setg(errp, "Bad value for \"ic-mode\" property"); 3224 } 3225 } 3226 3227 static char *spapr_get_host_model(Object *obj, Error **errp) 3228 { 3229 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3230 3231 return g_strdup(spapr->host_model); 3232 } 3233 3234 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3235 { 3236 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3237 3238 g_free(spapr->host_model); 3239 spapr->host_model = g_strdup(value); 3240 } 3241 3242 static char *spapr_get_host_serial(Object *obj, Error **errp) 3243 { 3244 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3245 3246 return g_strdup(spapr->host_serial); 3247 } 3248 3249 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3250 { 3251 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3252 3253 g_free(spapr->host_serial); 3254 spapr->host_serial = g_strdup(value); 3255 } 3256 3257 static void spapr_instance_init(Object *obj) 3258 { 3259 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3260 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3261 MachineState *ms = MACHINE(spapr); 3262 MachineClass *mc = MACHINE_GET_CLASS(ms); 3263 3264 /* 3265 * NVDIMM support went live in 5.1 without considering that, in 3266 * other archs, the user needs to enable NVDIMM support with the 3267 * 'nvdimm' machine option and the default behavior is NVDIMM 3268 * support disabled. It is too late to roll back to the standard 3269 * behavior without breaking 5.1 guests. 3270 */ 3271 if (mc->nvdimm_supported) { 3272 ms->nvdimms_state->is_enabled = true; 3273 } 3274 3275 spapr->htab_fd = -1; 3276 spapr->use_hotplug_event_source = true; 3277 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE); 3278 object_property_add_str(obj, "kvm-type", 3279 spapr_get_kvm_type, spapr_set_kvm_type); 3280 object_property_set_description(obj, "kvm-type", 3281 "Specifies the KVM virtualization mode (auto," 3282 " hv, pr). Defaults to 'auto'. This mode will use" 3283 " any available KVM module loaded in the host," 3284 " where kvm_hv takes precedence if both kvm_hv and" 3285 " kvm_pr are loaded."); 3286 object_property_add_bool(obj, "modern-hotplug-events", 3287 spapr_get_modern_hotplug_events, 3288 spapr_set_modern_hotplug_events); 3289 object_property_set_description(obj, "modern-hotplug-events", 3290 "Use dedicated hotplug event mechanism in" 3291 " place of standard EPOW events when possible" 3292 " (required for memory hot-unplug support)"); 3293 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3294 "Maximum permitted CPU compatibility mode"); 3295 3296 object_property_add_str(obj, "resize-hpt", 3297 spapr_get_resize_hpt, spapr_set_resize_hpt); 3298 object_property_set_description(obj, "resize-hpt", 3299 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3300 object_property_add_uint32_ptr(obj, "vsmt", 3301 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3302 object_property_set_description(obj, "vsmt", 3303 "Virtual SMT: KVM behaves as if this were" 3304 " the host's SMT mode"); 3305 3306 object_property_add_bool(obj, "vfio-no-msix-emulation", 3307 spapr_get_msix_emulation, NULL); 3308 3309 object_property_add_uint64_ptr(obj, "kernel-addr", 3310 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3311 object_property_set_description(obj, "kernel-addr", 3312 stringify(KERNEL_LOAD_ADDR) 3313 " for -kernel is the default"); 3314 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3315 /* The machine class defines the default interrupt controller mode */ 3316 spapr->irq = smc->irq; 3317 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3318 spapr_set_ic_mode); 3319 object_property_set_description(obj, "ic-mode", 3320 "Specifies the interrupt controller mode (xics, xive, dual)"); 3321 3322 object_property_add_str(obj, "host-model", 3323 spapr_get_host_model, spapr_set_host_model); 3324 object_property_set_description(obj, "host-model", 3325 "Host model to advertise in guest device tree"); 3326 object_property_add_str(obj, "host-serial", 3327 spapr_get_host_serial, spapr_set_host_serial); 3328 object_property_set_description(obj, "host-serial", 3329 "Host serial number to advertise in guest device tree"); 3330 } 3331 3332 static void spapr_machine_finalizefn(Object *obj) 3333 { 3334 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3335 3336 g_free(spapr->kvm_type); 3337 } 3338 3339 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3340 { 3341 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3342 PowerPCCPU *cpu = POWERPC_CPU(cs); 3343 CPUPPCState *env = &cpu->env; 3344 3345 cpu_synchronize_state(cs); 3346 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3347 if (spapr->fwnmi_system_reset_addr != -1) { 3348 uint64_t rtas_addr, addr; 3349 3350 /* get rtas addr from fdt */ 3351 rtas_addr = spapr_get_rtas_addr(); 3352 if (!rtas_addr) { 3353 qemu_system_guest_panicked(NULL); 3354 return; 3355 } 3356 3357 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3358 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3359 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3360 env->gpr[3] = addr; 3361 } 3362 ppc_cpu_do_system_reset(cs); 3363 if (spapr->fwnmi_system_reset_addr != -1) { 3364 env->nip = spapr->fwnmi_system_reset_addr; 3365 } 3366 } 3367 3368 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3369 { 3370 CPUState *cs; 3371 3372 CPU_FOREACH(cs) { 3373 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3374 } 3375 } 3376 3377 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3378 void *fdt, int *fdt_start_offset, Error **errp) 3379 { 3380 uint64_t addr; 3381 uint32_t node; 3382 3383 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3384 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3385 &error_abort); 3386 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3387 SPAPR_MEMORY_BLOCK_SIZE); 3388 return 0; 3389 } 3390 3391 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3392 bool dedicated_hp_event_source) 3393 { 3394 SpaprDrc *drc; 3395 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3396 int i; 3397 uint64_t addr = addr_start; 3398 bool hotplugged = spapr_drc_hotplugged(dev); 3399 3400 for (i = 0; i < nr_lmbs; i++) { 3401 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3402 addr / SPAPR_MEMORY_BLOCK_SIZE); 3403 g_assert(drc); 3404 3405 /* 3406 * memory_device_get_free_addr() provided a range of free addresses 3407 * that doesn't overlap with any existing mapping at pre-plug. The 3408 * corresponding LMB DRCs are thus assumed to be all attachable. 3409 */ 3410 spapr_drc_attach(drc, dev); 3411 if (!hotplugged) { 3412 spapr_drc_reset(drc); 3413 } 3414 addr += SPAPR_MEMORY_BLOCK_SIZE; 3415 } 3416 /* send hotplug notification to the 3417 * guest only in case of hotplugged memory 3418 */ 3419 if (hotplugged) { 3420 if (dedicated_hp_event_source) { 3421 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3422 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3423 g_assert(drc); 3424 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3425 nr_lmbs, 3426 spapr_drc_index(drc)); 3427 } else { 3428 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3429 nr_lmbs); 3430 } 3431 } 3432 } 3433 3434 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3435 { 3436 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3437 PCDIMMDevice *dimm = PC_DIMM(dev); 3438 uint64_t size, addr; 3439 int64_t slot; 3440 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3441 3442 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3443 3444 pc_dimm_plug(dimm, MACHINE(ms)); 3445 3446 if (!is_nvdimm) { 3447 addr = object_property_get_uint(OBJECT(dimm), 3448 PC_DIMM_ADDR_PROP, &error_abort); 3449 spapr_add_lmbs(dev, addr, size, 3450 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT)); 3451 } else { 3452 slot = object_property_get_int(OBJECT(dimm), 3453 PC_DIMM_SLOT_PROP, &error_abort); 3454 /* We should have valid slot number at this point */ 3455 g_assert(slot >= 0); 3456 spapr_add_nvdimm(dev, slot); 3457 } 3458 } 3459 3460 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3461 Error **errp) 3462 { 3463 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3464 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3465 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3466 PCDIMMDevice *dimm = PC_DIMM(dev); 3467 Error *local_err = NULL; 3468 uint64_t size; 3469 Object *memdev; 3470 hwaddr pagesize; 3471 3472 if (!smc->dr_lmb_enabled) { 3473 error_setg(errp, "Memory hotplug not supported for this machine"); 3474 return; 3475 } 3476 3477 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3478 if (local_err) { 3479 error_propagate(errp, local_err); 3480 return; 3481 } 3482 3483 if (is_nvdimm) { 3484 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3485 return; 3486 } 3487 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3488 error_setg(errp, "Hotplugged memory size must be a multiple of " 3489 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3490 return; 3491 } 3492 3493 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3494 &error_abort); 3495 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3496 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3497 return; 3498 } 3499 3500 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3501 } 3502 3503 struct SpaprDimmState { 3504 PCDIMMDevice *dimm; 3505 uint32_t nr_lmbs; 3506 QTAILQ_ENTRY(SpaprDimmState) next; 3507 }; 3508 3509 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3510 PCDIMMDevice *dimm) 3511 { 3512 SpaprDimmState *dimm_state = NULL; 3513 3514 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3515 if (dimm_state->dimm == dimm) { 3516 break; 3517 } 3518 } 3519 return dimm_state; 3520 } 3521 3522 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3523 uint32_t nr_lmbs, 3524 PCDIMMDevice *dimm) 3525 { 3526 SpaprDimmState *ds = NULL; 3527 3528 /* 3529 * If this request is for a DIMM whose removal had failed earlier 3530 * (due to guest's refusal to remove the LMBs), we would have this 3531 * dimm already in the pending_dimm_unplugs list. In that 3532 * case don't add again. 3533 */ 3534 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3535 if (!ds) { 3536 ds = g_malloc0(sizeof(SpaprDimmState)); 3537 ds->nr_lmbs = nr_lmbs; 3538 ds->dimm = dimm; 3539 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3540 } 3541 return ds; 3542 } 3543 3544 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3545 SpaprDimmState *dimm_state) 3546 { 3547 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3548 g_free(dimm_state); 3549 } 3550 3551 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3552 PCDIMMDevice *dimm) 3553 { 3554 SpaprDrc *drc; 3555 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3556 &error_abort); 3557 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3558 uint32_t avail_lmbs = 0; 3559 uint64_t addr_start, addr; 3560 int i; 3561 3562 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3563 &error_abort); 3564 3565 addr = addr_start; 3566 for (i = 0; i < nr_lmbs; i++) { 3567 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3568 addr / SPAPR_MEMORY_BLOCK_SIZE); 3569 g_assert(drc); 3570 if (drc->dev) { 3571 avail_lmbs++; 3572 } 3573 addr += SPAPR_MEMORY_BLOCK_SIZE; 3574 } 3575 3576 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3577 } 3578 3579 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev) 3580 { 3581 SpaprDimmState *ds; 3582 PCDIMMDevice *dimm; 3583 SpaprDrc *drc; 3584 uint32_t nr_lmbs; 3585 uint64_t size, addr_start, addr; 3586 g_autofree char *qapi_error = NULL; 3587 int i; 3588 3589 if (!dev) { 3590 return; 3591 } 3592 3593 dimm = PC_DIMM(dev); 3594 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3595 3596 /* 3597 * 'ds == NULL' would mean that the DIMM doesn't have a pending 3598 * unplug state, but one of its DRC is marked as unplug_requested. 3599 * This is bad and weird enough to g_assert() out. 3600 */ 3601 g_assert(ds); 3602 3603 spapr_pending_dimm_unplugs_remove(spapr, ds); 3604 3605 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3606 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3607 3608 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3609 &error_abort); 3610 3611 addr = addr_start; 3612 for (i = 0; i < nr_lmbs; i++) { 3613 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3614 addr / SPAPR_MEMORY_BLOCK_SIZE); 3615 g_assert(drc); 3616 3617 drc->unplug_requested = false; 3618 addr += SPAPR_MEMORY_BLOCK_SIZE; 3619 } 3620 3621 /* 3622 * Tell QAPI that something happened and the memory 3623 * hotunplug wasn't successful. 3624 */ 3625 qapi_error = g_strdup_printf("Memory hotunplug rejected by the guest " 3626 "for device %s", dev->id); 3627 qapi_event_send_mem_unplug_error(dev->id, qapi_error); 3628 } 3629 3630 /* Callback to be called during DRC release. */ 3631 void spapr_lmb_release(DeviceState *dev) 3632 { 3633 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3634 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3635 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3636 3637 /* This information will get lost if a migration occurs 3638 * during the unplug process. In this case recover it. */ 3639 if (ds == NULL) { 3640 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3641 g_assert(ds); 3642 /* The DRC being examined by the caller at least must be counted */ 3643 g_assert(ds->nr_lmbs); 3644 } 3645 3646 if (--ds->nr_lmbs) { 3647 return; 3648 } 3649 3650 /* 3651 * Now that all the LMBs have been removed by the guest, call the 3652 * unplug handler chain. This can never fail. 3653 */ 3654 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3655 object_unparent(OBJECT(dev)); 3656 } 3657 3658 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3659 { 3660 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3661 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3662 3663 /* We really shouldn't get this far without anything to unplug */ 3664 g_assert(ds); 3665 3666 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3667 qdev_unrealize(dev); 3668 spapr_pending_dimm_unplugs_remove(spapr, ds); 3669 } 3670 3671 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3672 DeviceState *dev, Error **errp) 3673 { 3674 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3675 PCDIMMDevice *dimm = PC_DIMM(dev); 3676 uint32_t nr_lmbs; 3677 uint64_t size, addr_start, addr; 3678 int i; 3679 SpaprDrc *drc; 3680 3681 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3682 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3683 return; 3684 } 3685 3686 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3687 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3688 3689 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3690 &error_abort); 3691 3692 /* 3693 * An existing pending dimm state for this DIMM means that there is an 3694 * unplug operation in progress, waiting for the spapr_lmb_release 3695 * callback to complete the job (BQL can't cover that far). In this case, 3696 * bail out to avoid detaching DRCs that were already released. 3697 */ 3698 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3699 error_setg(errp, "Memory unplug already in progress for device %s", 3700 dev->id); 3701 return; 3702 } 3703 3704 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3705 3706 addr = addr_start; 3707 for (i = 0; i < nr_lmbs; i++) { 3708 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3709 addr / SPAPR_MEMORY_BLOCK_SIZE); 3710 g_assert(drc); 3711 3712 spapr_drc_unplug_request(drc); 3713 addr += SPAPR_MEMORY_BLOCK_SIZE; 3714 } 3715 3716 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3717 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3718 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3719 nr_lmbs, spapr_drc_index(drc)); 3720 } 3721 3722 /* Callback to be called during DRC release. */ 3723 void spapr_core_release(DeviceState *dev) 3724 { 3725 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3726 3727 /* Call the unplug handler chain. This can never fail. */ 3728 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3729 object_unparent(OBJECT(dev)); 3730 } 3731 3732 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3733 { 3734 MachineState *ms = MACHINE(hotplug_dev); 3735 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3736 CPUCore *cc = CPU_CORE(dev); 3737 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3738 3739 if (smc->pre_2_10_has_unused_icps) { 3740 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3741 int i; 3742 3743 for (i = 0; i < cc->nr_threads; i++) { 3744 CPUState *cs = CPU(sc->threads[i]); 3745 3746 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3747 } 3748 } 3749 3750 assert(core_slot); 3751 core_slot->cpu = NULL; 3752 qdev_unrealize(dev); 3753 } 3754 3755 static 3756 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3757 Error **errp) 3758 { 3759 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3760 int index; 3761 SpaprDrc *drc; 3762 CPUCore *cc = CPU_CORE(dev); 3763 3764 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3765 error_setg(errp, "Unable to find CPU core with core-id: %d", 3766 cc->core_id); 3767 return; 3768 } 3769 if (index == 0) { 3770 error_setg(errp, "Boot CPU core may not be unplugged"); 3771 return; 3772 } 3773 3774 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3775 spapr_vcpu_id(spapr, cc->core_id)); 3776 g_assert(drc); 3777 3778 if (!spapr_drc_unplug_requested(drc)) { 3779 spapr_drc_unplug_request(drc); 3780 } 3781 3782 /* 3783 * spapr_hotplug_req_remove_by_index is left unguarded, out of the 3784 * "!spapr_drc_unplug_requested" check, to allow for multiple IRQ 3785 * pulses removing the same CPU. Otherwise, in an failed hotunplug 3786 * attempt (e.g. the kernel will refuse to remove the last online 3787 * CPU), we will never attempt it again because unplug_requested 3788 * will still be 'true' in that case. 3789 */ 3790 spapr_hotplug_req_remove_by_index(drc); 3791 } 3792 3793 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3794 void *fdt, int *fdt_start_offset, Error **errp) 3795 { 3796 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3797 CPUState *cs = CPU(core->threads[0]); 3798 PowerPCCPU *cpu = POWERPC_CPU(cs); 3799 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3800 int id = spapr_get_vcpu_id(cpu); 3801 g_autofree char *nodename = NULL; 3802 int offset; 3803 3804 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3805 offset = fdt_add_subnode(fdt, 0, nodename); 3806 3807 spapr_dt_cpu(cs, fdt, offset, spapr); 3808 3809 /* 3810 * spapr_dt_cpu() does not fill the 'name' property in the 3811 * CPU node. The function is called during boot process, before 3812 * and after CAS, and overwriting the 'name' property written 3813 * by SLOF is not allowed. 3814 * 3815 * Write it manually after spapr_dt_cpu(). This makes the hotplug 3816 * CPUs more compatible with the coldplugged ones, which have 3817 * the 'name' property. Linux Kernel also relies on this 3818 * property to identify CPU nodes. 3819 */ 3820 _FDT((fdt_setprop_string(fdt, offset, "name", nodename))); 3821 3822 *fdt_start_offset = offset; 3823 return 0; 3824 } 3825 3826 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3827 { 3828 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3829 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3830 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3831 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3832 CPUCore *cc = CPU_CORE(dev); 3833 CPUState *cs; 3834 SpaprDrc *drc; 3835 CPUArchId *core_slot; 3836 int index; 3837 bool hotplugged = spapr_drc_hotplugged(dev); 3838 int i; 3839 3840 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3841 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */ 3842 3843 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3844 spapr_vcpu_id(spapr, cc->core_id)); 3845 3846 g_assert(drc || !mc->has_hotpluggable_cpus); 3847 3848 if (drc) { 3849 /* 3850 * spapr_core_pre_plug() already buys us this is a brand new 3851 * core being plugged into a free slot. Nothing should already 3852 * be attached to the corresponding DRC. 3853 */ 3854 spapr_drc_attach(drc, dev); 3855 3856 if (hotplugged) { 3857 /* 3858 * Send hotplug notification interrupt to the guest only 3859 * in case of hotplugged CPUs. 3860 */ 3861 spapr_hotplug_req_add_by_index(drc); 3862 } else { 3863 spapr_drc_reset(drc); 3864 } 3865 } 3866 3867 core_slot->cpu = OBJECT(dev); 3868 3869 /* 3870 * Set compatibility mode to match the boot CPU, which was either set 3871 * by the machine reset code or by CAS. This really shouldn't fail at 3872 * this point. 3873 */ 3874 if (hotplugged) { 3875 for (i = 0; i < cc->nr_threads; i++) { 3876 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3877 &error_abort); 3878 } 3879 } 3880 3881 if (smc->pre_2_10_has_unused_icps) { 3882 for (i = 0; i < cc->nr_threads; i++) { 3883 cs = CPU(core->threads[i]); 3884 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3885 } 3886 } 3887 } 3888 3889 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3890 Error **errp) 3891 { 3892 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3893 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3894 CPUCore *cc = CPU_CORE(dev); 3895 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3896 const char *type = object_get_typename(OBJECT(dev)); 3897 CPUArchId *core_slot; 3898 int index; 3899 unsigned int smp_threads = machine->smp.threads; 3900 3901 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3902 error_setg(errp, "CPU hotplug not supported for this machine"); 3903 return; 3904 } 3905 3906 if (strcmp(base_core_type, type)) { 3907 error_setg(errp, "CPU core type should be %s", base_core_type); 3908 return; 3909 } 3910 3911 if (cc->core_id % smp_threads) { 3912 error_setg(errp, "invalid core id %d", cc->core_id); 3913 return; 3914 } 3915 3916 /* 3917 * In general we should have homogeneous threads-per-core, but old 3918 * (pre hotplug support) machine types allow the last core to have 3919 * reduced threads as a compatibility hack for when we allowed 3920 * total vcpus not a multiple of threads-per-core. 3921 */ 3922 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3923 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 3924 smp_threads); 3925 return; 3926 } 3927 3928 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3929 if (!core_slot) { 3930 error_setg(errp, "core id %d out of range", cc->core_id); 3931 return; 3932 } 3933 3934 if (core_slot->cpu) { 3935 error_setg(errp, "core %d already populated", cc->core_id); 3936 return; 3937 } 3938 3939 numa_cpu_pre_plug(core_slot, dev, errp); 3940 } 3941 3942 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3943 void *fdt, int *fdt_start_offset, Error **errp) 3944 { 3945 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3946 int intc_phandle; 3947 3948 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3949 if (intc_phandle <= 0) { 3950 return -1; 3951 } 3952 3953 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3954 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3955 return -1; 3956 } 3957 3958 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3959 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3960 3961 return 0; 3962 } 3963 3964 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3965 Error **errp) 3966 { 3967 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3968 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3969 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3970 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3971 SpaprDrc *drc; 3972 3973 if (dev->hotplugged && !smc->dr_phb_enabled) { 3974 error_setg(errp, "PHB hotplug not supported for this machine"); 3975 return false; 3976 } 3977 3978 if (sphb->index == (uint32_t)-1) { 3979 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3980 return false; 3981 } 3982 3983 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3984 if (drc && drc->dev) { 3985 error_setg(errp, "PHB %d already attached", sphb->index); 3986 return false; 3987 } 3988 3989 /* 3990 * This will check that sphb->index doesn't exceed the maximum number of 3991 * PHBs for the current machine type. 3992 */ 3993 return 3994 smc->phb_placement(spapr, sphb->index, 3995 &sphb->buid, &sphb->io_win_addr, 3996 &sphb->mem_win_addr, &sphb->mem64_win_addr, 3997 windows_supported, sphb->dma_liobn, 3998 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 3999 errp); 4000 } 4001 4002 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4003 { 4004 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4005 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4006 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4007 SpaprDrc *drc; 4008 bool hotplugged = spapr_drc_hotplugged(dev); 4009 4010 if (!smc->dr_phb_enabled) { 4011 return; 4012 } 4013 4014 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4015 /* hotplug hooks should check it's enabled before getting this far */ 4016 assert(drc); 4017 4018 /* spapr_phb_pre_plug() already checked the DRC is attachable */ 4019 spapr_drc_attach(drc, dev); 4020 4021 if (hotplugged) { 4022 spapr_hotplug_req_add_by_index(drc); 4023 } else { 4024 spapr_drc_reset(drc); 4025 } 4026 } 4027 4028 void spapr_phb_release(DeviceState *dev) 4029 { 4030 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4031 4032 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4033 object_unparent(OBJECT(dev)); 4034 } 4035 4036 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4037 { 4038 qdev_unrealize(dev); 4039 } 4040 4041 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4042 DeviceState *dev, Error **errp) 4043 { 4044 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4045 SpaprDrc *drc; 4046 4047 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4048 assert(drc); 4049 4050 if (!spapr_drc_unplug_requested(drc)) { 4051 spapr_drc_unplug_request(drc); 4052 spapr_hotplug_req_remove_by_index(drc); 4053 } else { 4054 error_setg(errp, 4055 "PCI Host Bridge unplug already in progress for device %s", 4056 dev->id); 4057 } 4058 } 4059 4060 static 4061 bool spapr_tpm_proxy_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4062 Error **errp) 4063 { 4064 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4065 4066 if (spapr->tpm_proxy != NULL) { 4067 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4068 return false; 4069 } 4070 4071 return true; 4072 } 4073 4074 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4075 { 4076 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4077 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4078 4079 /* Already checked in spapr_tpm_proxy_pre_plug() */ 4080 g_assert(spapr->tpm_proxy == NULL); 4081 4082 spapr->tpm_proxy = tpm_proxy; 4083 } 4084 4085 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4086 { 4087 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4088 4089 qdev_unrealize(dev); 4090 object_unparent(OBJECT(dev)); 4091 spapr->tpm_proxy = NULL; 4092 } 4093 4094 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4095 DeviceState *dev, Error **errp) 4096 { 4097 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4098 spapr_memory_plug(hotplug_dev, dev); 4099 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4100 spapr_core_plug(hotplug_dev, dev); 4101 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4102 spapr_phb_plug(hotplug_dev, dev); 4103 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4104 spapr_tpm_proxy_plug(hotplug_dev, dev); 4105 } 4106 } 4107 4108 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4109 DeviceState *dev, Error **errp) 4110 { 4111 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4112 spapr_memory_unplug(hotplug_dev, dev); 4113 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4114 spapr_core_unplug(hotplug_dev, dev); 4115 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4116 spapr_phb_unplug(hotplug_dev, dev); 4117 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4118 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4119 } 4120 } 4121 4122 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr) 4123 { 4124 return spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT) || 4125 /* 4126 * CAS will process all pending unplug requests. 4127 * 4128 * HACK: a guest could theoretically have cleared all bits in OV5, 4129 * but none of the guests we care for do. 4130 */ 4131 spapr_ovec_empty(spapr->ov5_cas); 4132 } 4133 4134 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4135 DeviceState *dev, Error **errp) 4136 { 4137 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4138 MachineClass *mc = MACHINE_GET_CLASS(sms); 4139 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4140 4141 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4142 if (spapr_memory_hot_unplug_supported(sms)) { 4143 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4144 } else { 4145 error_setg(errp, "Memory hot unplug not supported for this guest"); 4146 } 4147 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4148 if (!mc->has_hotpluggable_cpus) { 4149 error_setg(errp, "CPU hot unplug not supported on this machine"); 4150 return; 4151 } 4152 spapr_core_unplug_request(hotplug_dev, dev, errp); 4153 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4154 if (!smc->dr_phb_enabled) { 4155 error_setg(errp, "PHB hot unplug not supported on this machine"); 4156 return; 4157 } 4158 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4159 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4160 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4161 } 4162 } 4163 4164 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4165 DeviceState *dev, Error **errp) 4166 { 4167 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4168 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4169 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4170 spapr_core_pre_plug(hotplug_dev, dev, errp); 4171 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4172 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4173 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4174 spapr_tpm_proxy_pre_plug(hotplug_dev, dev, errp); 4175 } 4176 } 4177 4178 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4179 DeviceState *dev) 4180 { 4181 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4182 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4183 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4184 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4185 return HOTPLUG_HANDLER(machine); 4186 } 4187 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4188 PCIDevice *pcidev = PCI_DEVICE(dev); 4189 PCIBus *root = pci_device_root_bus(pcidev); 4190 SpaprPhbState *phb = 4191 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4192 TYPE_SPAPR_PCI_HOST_BRIDGE); 4193 4194 if (phb) { 4195 return HOTPLUG_HANDLER(phb); 4196 } 4197 } 4198 return NULL; 4199 } 4200 4201 static CpuInstanceProperties 4202 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4203 { 4204 CPUArchId *core_slot; 4205 MachineClass *mc = MACHINE_GET_CLASS(machine); 4206 4207 /* make sure possible_cpu are intialized */ 4208 mc->possible_cpu_arch_ids(machine); 4209 /* get CPU core slot containing thread that matches cpu_index */ 4210 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4211 assert(core_slot); 4212 return core_slot->props; 4213 } 4214 4215 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4216 { 4217 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4218 } 4219 4220 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4221 { 4222 int i; 4223 unsigned int smp_threads = machine->smp.threads; 4224 unsigned int smp_cpus = machine->smp.cpus; 4225 const char *core_type; 4226 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4227 MachineClass *mc = MACHINE_GET_CLASS(machine); 4228 4229 if (!mc->has_hotpluggable_cpus) { 4230 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4231 } 4232 if (machine->possible_cpus) { 4233 assert(machine->possible_cpus->len == spapr_max_cores); 4234 return machine->possible_cpus; 4235 } 4236 4237 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4238 if (!core_type) { 4239 error_report("Unable to find sPAPR CPU Core definition"); 4240 exit(1); 4241 } 4242 4243 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4244 sizeof(CPUArchId) * spapr_max_cores); 4245 machine->possible_cpus->len = spapr_max_cores; 4246 for (i = 0; i < machine->possible_cpus->len; i++) { 4247 int core_id = i * smp_threads; 4248 4249 machine->possible_cpus->cpus[i].type = core_type; 4250 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4251 machine->possible_cpus->cpus[i].arch_id = core_id; 4252 machine->possible_cpus->cpus[i].props.has_core_id = true; 4253 machine->possible_cpus->cpus[i].props.core_id = core_id; 4254 } 4255 return machine->possible_cpus; 4256 } 4257 4258 static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4259 uint64_t *buid, hwaddr *pio, 4260 hwaddr *mmio32, hwaddr *mmio64, 4261 unsigned n_dma, uint32_t *liobns, 4262 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4263 { 4264 /* 4265 * New-style PHB window placement. 4266 * 4267 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4268 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4269 * windows. 4270 * 4271 * Some guest kernels can't work with MMIO windows above 1<<46 4272 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4273 * 4274 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4275 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4276 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4277 * 1TiB 64-bit MMIO windows for each PHB. 4278 */ 4279 const uint64_t base_buid = 0x800000020000000ULL; 4280 int i; 4281 4282 /* Sanity check natural alignments */ 4283 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4284 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4285 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4286 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4287 /* Sanity check bounds */ 4288 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4289 SPAPR_PCI_MEM32_WIN_SIZE); 4290 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4291 SPAPR_PCI_MEM64_WIN_SIZE); 4292 4293 if (index >= SPAPR_MAX_PHBS) { 4294 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4295 SPAPR_MAX_PHBS - 1); 4296 return false; 4297 } 4298 4299 *buid = base_buid + index; 4300 for (i = 0; i < n_dma; ++i) { 4301 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4302 } 4303 4304 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4305 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4306 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4307 4308 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4309 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4310 return true; 4311 } 4312 4313 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4314 { 4315 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4316 4317 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4318 } 4319 4320 static void spapr_ics_resend(XICSFabric *dev) 4321 { 4322 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4323 4324 ics_resend(spapr->ics); 4325 } 4326 4327 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4328 { 4329 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4330 4331 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4332 } 4333 4334 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4335 Monitor *mon) 4336 { 4337 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4338 4339 spapr_irq_print_info(spapr, mon); 4340 monitor_printf(mon, "irqchip: %s\n", 4341 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4342 } 4343 4344 /* 4345 * This is a XIVE only operation 4346 */ 4347 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4348 uint8_t nvt_blk, uint32_t nvt_idx, 4349 bool cam_ignore, uint8_t priority, 4350 uint32_t logic_serv, XiveTCTXMatch *match) 4351 { 4352 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4353 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4354 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4355 int count; 4356 4357 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4358 priority, logic_serv, match); 4359 if (count < 0) { 4360 return count; 4361 } 4362 4363 /* 4364 * When we implement the save and restore of the thread interrupt 4365 * contexts in the enter/exit CPU handlers of the machine and the 4366 * escalations in QEMU, we should be able to handle non dispatched 4367 * vCPUs. 4368 * 4369 * Until this is done, the sPAPR machine should find at least one 4370 * matching context always. 4371 */ 4372 if (count == 0) { 4373 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4374 nvt_blk, nvt_idx); 4375 } 4376 4377 return count; 4378 } 4379 4380 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4381 { 4382 return cpu->vcpu_id; 4383 } 4384 4385 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4386 { 4387 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4388 MachineState *ms = MACHINE(spapr); 4389 int vcpu_id; 4390 4391 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4392 4393 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4394 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4395 error_append_hint(errp, "Adjust the number of cpus to %d " 4396 "or try to raise the number of threads per core\n", 4397 vcpu_id * ms->smp.threads / spapr->vsmt); 4398 return false; 4399 } 4400 4401 cpu->vcpu_id = vcpu_id; 4402 return true; 4403 } 4404 4405 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4406 { 4407 CPUState *cs; 4408 4409 CPU_FOREACH(cs) { 4410 PowerPCCPU *cpu = POWERPC_CPU(cs); 4411 4412 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4413 return cpu; 4414 } 4415 } 4416 4417 return NULL; 4418 } 4419 4420 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4421 { 4422 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4423 4424 /* These are only called by TCG, KVM maintains dispatch state */ 4425 4426 spapr_cpu->prod = false; 4427 if (spapr_cpu->vpa_addr) { 4428 CPUState *cs = CPU(cpu); 4429 uint32_t dispatch; 4430 4431 dispatch = ldl_be_phys(cs->as, 4432 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4433 dispatch++; 4434 if ((dispatch & 1) != 0) { 4435 qemu_log_mask(LOG_GUEST_ERROR, 4436 "VPA: incorrect dispatch counter value for " 4437 "dispatched partition %u, correcting.\n", dispatch); 4438 dispatch++; 4439 } 4440 stl_be_phys(cs->as, 4441 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4442 } 4443 } 4444 4445 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4446 { 4447 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4448 4449 if (spapr_cpu->vpa_addr) { 4450 CPUState *cs = CPU(cpu); 4451 uint32_t dispatch; 4452 4453 dispatch = ldl_be_phys(cs->as, 4454 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4455 dispatch++; 4456 if ((dispatch & 1) != 1) { 4457 qemu_log_mask(LOG_GUEST_ERROR, 4458 "VPA: incorrect dispatch counter value for " 4459 "preempted partition %u, correcting.\n", dispatch); 4460 dispatch++; 4461 } 4462 stl_be_phys(cs->as, 4463 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4464 } 4465 } 4466 4467 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4468 { 4469 MachineClass *mc = MACHINE_CLASS(oc); 4470 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4471 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4472 NMIClass *nc = NMI_CLASS(oc); 4473 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4474 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4475 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4476 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4477 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4478 4479 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4480 mc->ignore_boot_device_suffixes = true; 4481 4482 /* 4483 * We set up the default / latest behaviour here. The class_init 4484 * functions for the specific versioned machine types can override 4485 * these details for backwards compatibility 4486 */ 4487 mc->init = spapr_machine_init; 4488 mc->reset = spapr_machine_reset; 4489 mc->block_default_type = IF_SCSI; 4490 mc->max_cpus = 1024; 4491 mc->no_parallel = 1; 4492 mc->default_boot_order = ""; 4493 mc->default_ram_size = 512 * MiB; 4494 mc->default_ram_id = "ppc_spapr.ram"; 4495 mc->default_display = "std"; 4496 mc->kvm_type = spapr_kvm_type; 4497 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4498 mc->pci_allow_0_address = true; 4499 assert(!mc->get_hotplug_handler); 4500 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4501 hc->pre_plug = spapr_machine_device_pre_plug; 4502 hc->plug = spapr_machine_device_plug; 4503 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4504 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4505 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4506 hc->unplug_request = spapr_machine_device_unplug_request; 4507 hc->unplug = spapr_machine_device_unplug; 4508 4509 smc->dr_lmb_enabled = true; 4510 smc->update_dt_enabled = true; 4511 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4512 mc->has_hotpluggable_cpus = true; 4513 mc->nvdimm_supported = true; 4514 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4515 fwc->get_dev_path = spapr_get_fw_dev_path; 4516 nc->nmi_monitor_handler = spapr_nmi; 4517 smc->phb_placement = spapr_phb_placement; 4518 vhc->hypercall = emulate_spapr_hypercall; 4519 vhc->hpt_mask = spapr_hpt_mask; 4520 vhc->map_hptes = spapr_map_hptes; 4521 vhc->unmap_hptes = spapr_unmap_hptes; 4522 vhc->hpte_set_c = spapr_hpte_set_c; 4523 vhc->hpte_set_r = spapr_hpte_set_r; 4524 vhc->get_pate = spapr_get_pate; 4525 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4526 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4527 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4528 xic->ics_get = spapr_ics_get; 4529 xic->ics_resend = spapr_ics_resend; 4530 xic->icp_get = spapr_icp_get; 4531 ispc->print_info = spapr_pic_print_info; 4532 /* Force NUMA node memory size to be a multiple of 4533 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4534 * in which LMBs are represented and hot-added 4535 */ 4536 mc->numa_mem_align_shift = 28; 4537 mc->auto_enable_numa = true; 4538 4539 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4540 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4541 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4542 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4543 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4544 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4545 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4546 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4547 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4548 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4549 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4550 spapr_caps_add_properties(smc); 4551 smc->irq = &spapr_irq_dual; 4552 smc->dr_phb_enabled = true; 4553 smc->linux_pci_probe = true; 4554 smc->smp_threads_vsmt = true; 4555 smc->nr_xirqs = SPAPR_NR_XIRQS; 4556 xfc->match_nvt = spapr_match_nvt; 4557 } 4558 4559 static const TypeInfo spapr_machine_info = { 4560 .name = TYPE_SPAPR_MACHINE, 4561 .parent = TYPE_MACHINE, 4562 .abstract = true, 4563 .instance_size = sizeof(SpaprMachineState), 4564 .instance_init = spapr_instance_init, 4565 .instance_finalize = spapr_machine_finalizefn, 4566 .class_size = sizeof(SpaprMachineClass), 4567 .class_init = spapr_machine_class_init, 4568 .interfaces = (InterfaceInfo[]) { 4569 { TYPE_FW_PATH_PROVIDER }, 4570 { TYPE_NMI }, 4571 { TYPE_HOTPLUG_HANDLER }, 4572 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4573 { TYPE_XICS_FABRIC }, 4574 { TYPE_INTERRUPT_STATS_PROVIDER }, 4575 { TYPE_XIVE_FABRIC }, 4576 { } 4577 }, 4578 }; 4579 4580 static void spapr_machine_latest_class_options(MachineClass *mc) 4581 { 4582 mc->alias = "pseries"; 4583 mc->is_default = true; 4584 } 4585 4586 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4587 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4588 void *data) \ 4589 { \ 4590 MachineClass *mc = MACHINE_CLASS(oc); \ 4591 spapr_machine_##suffix##_class_options(mc); \ 4592 if (latest) { \ 4593 spapr_machine_latest_class_options(mc); \ 4594 } \ 4595 } \ 4596 static const TypeInfo spapr_machine_##suffix##_info = { \ 4597 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4598 .parent = TYPE_SPAPR_MACHINE, \ 4599 .class_init = spapr_machine_##suffix##_class_init, \ 4600 }; \ 4601 static void spapr_machine_register_##suffix(void) \ 4602 { \ 4603 type_register(&spapr_machine_##suffix##_info); \ 4604 } \ 4605 type_init(spapr_machine_register_##suffix) 4606 4607 /* 4608 * pseries-6.0 4609 */ 4610 static void spapr_machine_6_0_class_options(MachineClass *mc) 4611 { 4612 /* Defaults for the latest behaviour inherited from the base class */ 4613 } 4614 4615 DEFINE_SPAPR_MACHINE(6_0, "6.0", true); 4616 4617 /* 4618 * pseries-5.2 4619 */ 4620 static void spapr_machine_5_2_class_options(MachineClass *mc) 4621 { 4622 spapr_machine_6_0_class_options(mc); 4623 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 4624 } 4625 4626 DEFINE_SPAPR_MACHINE(5_2, "5.2", false); 4627 4628 /* 4629 * pseries-5.1 4630 */ 4631 static void spapr_machine_5_1_class_options(MachineClass *mc) 4632 { 4633 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4634 4635 spapr_machine_5_2_class_options(mc); 4636 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4637 smc->pre_5_2_numa_associativity = true; 4638 } 4639 4640 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4641 4642 /* 4643 * pseries-5.0 4644 */ 4645 static void spapr_machine_5_0_class_options(MachineClass *mc) 4646 { 4647 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4648 static GlobalProperty compat[] = { 4649 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4650 }; 4651 4652 spapr_machine_5_1_class_options(mc); 4653 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4654 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4655 mc->numa_mem_supported = true; 4656 smc->pre_5_1_assoc_refpoints = true; 4657 } 4658 4659 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4660 4661 /* 4662 * pseries-4.2 4663 */ 4664 static void spapr_machine_4_2_class_options(MachineClass *mc) 4665 { 4666 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4667 4668 spapr_machine_5_0_class_options(mc); 4669 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4670 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4671 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4672 smc->rma_limit = 16 * GiB; 4673 mc->nvdimm_supported = false; 4674 } 4675 4676 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4677 4678 /* 4679 * pseries-4.1 4680 */ 4681 static void spapr_machine_4_1_class_options(MachineClass *mc) 4682 { 4683 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4684 static GlobalProperty compat[] = { 4685 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4686 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4687 }; 4688 4689 spapr_machine_4_2_class_options(mc); 4690 smc->linux_pci_probe = false; 4691 smc->smp_threads_vsmt = false; 4692 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4693 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4694 } 4695 4696 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4697 4698 /* 4699 * pseries-4.0 4700 */ 4701 static bool phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4702 uint64_t *buid, hwaddr *pio, 4703 hwaddr *mmio32, hwaddr *mmio64, 4704 unsigned n_dma, uint32_t *liobns, 4705 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4706 { 4707 if (!spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, 4708 liobns, nv2gpa, nv2atsd, errp)) { 4709 return false; 4710 } 4711 4712 *nv2gpa = 0; 4713 *nv2atsd = 0; 4714 return true; 4715 } 4716 static void spapr_machine_4_0_class_options(MachineClass *mc) 4717 { 4718 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4719 4720 spapr_machine_4_1_class_options(mc); 4721 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4722 smc->phb_placement = phb_placement_4_0; 4723 smc->irq = &spapr_irq_xics; 4724 smc->pre_4_1_migration = true; 4725 } 4726 4727 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4728 4729 /* 4730 * pseries-3.1 4731 */ 4732 static void spapr_machine_3_1_class_options(MachineClass *mc) 4733 { 4734 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4735 4736 spapr_machine_4_0_class_options(mc); 4737 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4738 4739 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4740 smc->update_dt_enabled = false; 4741 smc->dr_phb_enabled = false; 4742 smc->broken_host_serial_model = true; 4743 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4744 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4745 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4746 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4747 } 4748 4749 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4750 4751 /* 4752 * pseries-3.0 4753 */ 4754 4755 static void spapr_machine_3_0_class_options(MachineClass *mc) 4756 { 4757 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4758 4759 spapr_machine_3_1_class_options(mc); 4760 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4761 4762 smc->legacy_irq_allocation = true; 4763 smc->nr_xirqs = 0x400; 4764 smc->irq = &spapr_irq_xics_legacy; 4765 } 4766 4767 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4768 4769 /* 4770 * pseries-2.12 4771 */ 4772 static void spapr_machine_2_12_class_options(MachineClass *mc) 4773 { 4774 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4775 static GlobalProperty compat[] = { 4776 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4777 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4778 }; 4779 4780 spapr_machine_3_0_class_options(mc); 4781 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4782 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4783 4784 /* We depend on kvm_enabled() to choose a default value for the 4785 * hpt-max-page-size capability. Of course we can't do it here 4786 * because this is too early and the HW accelerator isn't initialzed 4787 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4788 */ 4789 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4790 } 4791 4792 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4793 4794 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4795 { 4796 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4797 4798 spapr_machine_2_12_class_options(mc); 4799 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4800 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4801 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4802 } 4803 4804 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4805 4806 /* 4807 * pseries-2.11 4808 */ 4809 4810 static void spapr_machine_2_11_class_options(MachineClass *mc) 4811 { 4812 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4813 4814 spapr_machine_2_12_class_options(mc); 4815 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4816 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4817 } 4818 4819 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4820 4821 /* 4822 * pseries-2.10 4823 */ 4824 4825 static void spapr_machine_2_10_class_options(MachineClass *mc) 4826 { 4827 spapr_machine_2_11_class_options(mc); 4828 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4829 } 4830 4831 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4832 4833 /* 4834 * pseries-2.9 4835 */ 4836 4837 static void spapr_machine_2_9_class_options(MachineClass *mc) 4838 { 4839 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4840 static GlobalProperty compat[] = { 4841 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4842 }; 4843 4844 spapr_machine_2_10_class_options(mc); 4845 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4846 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4847 smc->pre_2_10_has_unused_icps = true; 4848 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4849 } 4850 4851 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4852 4853 /* 4854 * pseries-2.8 4855 */ 4856 4857 static void spapr_machine_2_8_class_options(MachineClass *mc) 4858 { 4859 static GlobalProperty compat[] = { 4860 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4861 }; 4862 4863 spapr_machine_2_9_class_options(mc); 4864 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4865 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4866 mc->numa_mem_align_shift = 23; 4867 } 4868 4869 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4870 4871 /* 4872 * pseries-2.7 4873 */ 4874 4875 static bool phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4876 uint64_t *buid, hwaddr *pio, 4877 hwaddr *mmio32, hwaddr *mmio64, 4878 unsigned n_dma, uint32_t *liobns, 4879 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4880 { 4881 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4882 const uint64_t base_buid = 0x800000020000000ULL; 4883 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4884 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4885 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4886 const uint32_t max_index = 255; 4887 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4888 4889 uint64_t ram_top = MACHINE(spapr)->ram_size; 4890 hwaddr phb0_base, phb_base; 4891 int i; 4892 4893 /* Do we have device memory? */ 4894 if (MACHINE(spapr)->maxram_size > ram_top) { 4895 /* Can't just use maxram_size, because there may be an 4896 * alignment gap between normal and device memory regions 4897 */ 4898 ram_top = MACHINE(spapr)->device_memory->base + 4899 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4900 } 4901 4902 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4903 4904 if (index > max_index) { 4905 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4906 max_index); 4907 return false; 4908 } 4909 4910 *buid = base_buid + index; 4911 for (i = 0; i < n_dma; ++i) { 4912 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4913 } 4914 4915 phb_base = phb0_base + index * phb_spacing; 4916 *pio = phb_base + pio_offset; 4917 *mmio32 = phb_base + mmio_offset; 4918 /* 4919 * We don't set the 64-bit MMIO window, relying on the PHB's 4920 * fallback behaviour of automatically splitting a large "32-bit" 4921 * window into contiguous 32-bit and 64-bit windows 4922 */ 4923 4924 *nv2gpa = 0; 4925 *nv2atsd = 0; 4926 return true; 4927 } 4928 4929 static void spapr_machine_2_7_class_options(MachineClass *mc) 4930 { 4931 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4932 static GlobalProperty compat[] = { 4933 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4934 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4935 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4936 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4937 }; 4938 4939 spapr_machine_2_8_class_options(mc); 4940 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4941 mc->default_machine_opts = "modern-hotplug-events=off"; 4942 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4943 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4944 smc->phb_placement = phb_placement_2_7; 4945 } 4946 4947 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4948 4949 /* 4950 * pseries-2.6 4951 */ 4952 4953 static void spapr_machine_2_6_class_options(MachineClass *mc) 4954 { 4955 static GlobalProperty compat[] = { 4956 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4957 }; 4958 4959 spapr_machine_2_7_class_options(mc); 4960 mc->has_hotpluggable_cpus = false; 4961 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4962 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4963 } 4964 4965 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4966 4967 /* 4968 * pseries-2.5 4969 */ 4970 4971 static void spapr_machine_2_5_class_options(MachineClass *mc) 4972 { 4973 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4974 static GlobalProperty compat[] = { 4975 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4976 }; 4977 4978 spapr_machine_2_6_class_options(mc); 4979 smc->use_ohci_by_default = true; 4980 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4981 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4982 } 4983 4984 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4985 4986 /* 4987 * pseries-2.4 4988 */ 4989 4990 static void spapr_machine_2_4_class_options(MachineClass *mc) 4991 { 4992 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4993 4994 spapr_machine_2_5_class_options(mc); 4995 smc->dr_lmb_enabled = false; 4996 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4997 } 4998 4999 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 5000 5001 /* 5002 * pseries-2.3 5003 */ 5004 5005 static void spapr_machine_2_3_class_options(MachineClass *mc) 5006 { 5007 static GlobalProperty compat[] = { 5008 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 5009 }; 5010 spapr_machine_2_4_class_options(mc); 5011 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 5012 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5013 } 5014 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 5015 5016 /* 5017 * pseries-2.2 5018 */ 5019 5020 static void spapr_machine_2_2_class_options(MachineClass *mc) 5021 { 5022 static GlobalProperty compat[] = { 5023 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 5024 }; 5025 5026 spapr_machine_2_3_class_options(mc); 5027 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 5028 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5029 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 5030 } 5031 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 5032 5033 /* 5034 * pseries-2.1 5035 */ 5036 5037 static void spapr_machine_2_1_class_options(MachineClass *mc) 5038 { 5039 spapr_machine_2_2_class_options(mc); 5040 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 5041 } 5042 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 5043 5044 static void spapr_machine_register_types(void) 5045 { 5046 type_register_static(&spapr_machine_info); 5047 } 5048 5049 type_init(spapr_machine_register_types) 5050