1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/numa.h" 32 #include "hw/hw.h" 33 #include "qemu/log.h" 34 #include "hw/fw-path-provider.h" 35 #include "elf.h" 36 #include "net/net.h" 37 #include "sysemu/device_tree.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/hw_accel.h" 40 #include "kvm_ppc.h" 41 #include "migration/misc.h" 42 #include "migration/global_state.h" 43 #include "migration/register.h" 44 #include "mmu-hash64.h" 45 #include "mmu-book3s-v3.h" 46 #include "cpu-models.h" 47 #include "qom/cpu.h" 48 49 #include "hw/boards.h" 50 #include "hw/ppc/ppc.h" 51 #include "hw/loader.h" 52 53 #include "hw/ppc/fdt.h" 54 #include "hw/ppc/spapr.h" 55 #include "hw/ppc/spapr_vio.h" 56 #include "hw/pci-host/spapr.h" 57 #include "hw/pci/msi.h" 58 59 #include "hw/pci/pci.h" 60 #include "hw/scsi/scsi.h" 61 #include "hw/virtio/virtio-scsi.h" 62 #include "hw/virtio/vhost-scsi-common.h" 63 64 #include "exec/address-spaces.h" 65 #include "exec/ram_addr.h" 66 #include "hw/usb.h" 67 #include "qemu/config-file.h" 68 #include "qemu/error-report.h" 69 #include "trace.h" 70 #include "hw/nmi.h" 71 #include "hw/intc/intc.h" 72 73 #include "qemu/cutils.h" 74 #include "hw/ppc/spapr_cpu_core.h" 75 #include "hw/mem/memory-device.h" 76 77 #include <libfdt.h> 78 79 /* SLOF memory layout: 80 * 81 * SLOF raw image loaded at 0, copies its romfs right below the flat 82 * device-tree, then position SLOF itself 31M below that 83 * 84 * So we set FW_OVERHEAD to 40MB which should account for all of that 85 * and more 86 * 87 * We load our kernel at 4M, leaving space for SLOF initial image 88 */ 89 #define FDT_MAX_SIZE 0x100000 90 #define RTAS_MAX_SIZE 0x10000 91 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 92 #define FW_MAX_SIZE 0x400000 93 #define FW_FILE_NAME "slof.bin" 94 #define FW_OVERHEAD 0x2800000 95 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 96 97 #define MIN_RMA_SLOF 128UL 98 99 #define PHANDLE_XICP 0x00001111 100 101 /* These two functions implement the VCPU id numbering: one to compute them 102 * all and one to identify thread 0 of a VCORE. Any change to the first one 103 * is likely to have an impact on the second one, so let's keep them close. 104 */ 105 static int spapr_vcpu_id(sPAPRMachineState *spapr, int cpu_index) 106 { 107 assert(spapr->vsmt); 108 return 109 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 110 } 111 static bool spapr_is_thread0_in_vcore(sPAPRMachineState *spapr, 112 PowerPCCPU *cpu) 113 { 114 assert(spapr->vsmt); 115 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 116 } 117 118 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 119 { 120 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 121 * and newer QEMUs don't even have them. In both cases, we don't want 122 * to send anything on the wire. 123 */ 124 return false; 125 } 126 127 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 128 .name = "icp/server", 129 .version_id = 1, 130 .minimum_version_id = 1, 131 .needed = pre_2_10_vmstate_dummy_icp_needed, 132 .fields = (VMStateField[]) { 133 VMSTATE_UNUSED(4), /* uint32_t xirr */ 134 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 135 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 136 VMSTATE_END_OF_LIST() 137 }, 138 }; 139 140 static void pre_2_10_vmstate_register_dummy_icp(int i) 141 { 142 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 143 (void *)(uintptr_t) i); 144 } 145 146 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 147 { 148 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 149 (void *)(uintptr_t) i); 150 } 151 152 int spapr_max_server_number(sPAPRMachineState *spapr) 153 { 154 assert(spapr->vsmt); 155 return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads); 156 } 157 158 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 159 int smt_threads) 160 { 161 int i, ret = 0; 162 uint32_t servers_prop[smt_threads]; 163 uint32_t gservers_prop[smt_threads * 2]; 164 int index = spapr_get_vcpu_id(cpu); 165 166 if (cpu->compat_pvr) { 167 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 168 if (ret < 0) { 169 return ret; 170 } 171 } 172 173 /* Build interrupt servers and gservers properties */ 174 for (i = 0; i < smt_threads; i++) { 175 servers_prop[i] = cpu_to_be32(index + i); 176 /* Hack, direct the group queues back to cpu 0 */ 177 gservers_prop[i*2] = cpu_to_be32(index + i); 178 gservers_prop[i*2 + 1] = 0; 179 } 180 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 181 servers_prop, sizeof(servers_prop)); 182 if (ret < 0) { 183 return ret; 184 } 185 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 186 gservers_prop, sizeof(gservers_prop)); 187 188 return ret; 189 } 190 191 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 192 { 193 int index = spapr_get_vcpu_id(cpu); 194 uint32_t associativity[] = {cpu_to_be32(0x5), 195 cpu_to_be32(0x0), 196 cpu_to_be32(0x0), 197 cpu_to_be32(0x0), 198 cpu_to_be32(cpu->node_id), 199 cpu_to_be32(index)}; 200 201 /* Advertise NUMA via ibm,associativity */ 202 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 203 sizeof(associativity)); 204 } 205 206 /* Populate the "ibm,pa-features" property */ 207 static void spapr_populate_pa_features(sPAPRMachineState *spapr, 208 PowerPCCPU *cpu, 209 void *fdt, int offset, 210 bool legacy_guest) 211 { 212 uint8_t pa_features_206[] = { 6, 0, 213 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 214 uint8_t pa_features_207[] = { 24, 0, 215 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 216 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 217 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 218 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 219 uint8_t pa_features_300[] = { 66, 0, 220 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 221 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 222 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 223 /* 6: DS207 */ 224 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 225 /* 16: Vector */ 226 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 227 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 228 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 229 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 230 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 231 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 232 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 233 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 235 /* 42: PM, 44: PC RA, 46: SC vec'd */ 236 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 237 /* 48: SIMD, 50: QP BFP, 52: String */ 238 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 239 /* 54: DecFP, 56: DecI, 58: SHA */ 240 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 241 /* 60: NM atomic, 62: RNG */ 242 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 243 }; 244 uint8_t *pa_features = NULL; 245 size_t pa_size; 246 247 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 248 pa_features = pa_features_206; 249 pa_size = sizeof(pa_features_206); 250 } 251 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 252 pa_features = pa_features_207; 253 pa_size = sizeof(pa_features_207); 254 } 255 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 256 pa_features = pa_features_300; 257 pa_size = sizeof(pa_features_300); 258 } 259 if (!pa_features) { 260 return; 261 } 262 263 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 264 /* 265 * Note: we keep CI large pages off by default because a 64K capable 266 * guest provisioned with large pages might otherwise try to map a qemu 267 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 268 * even if that qemu runs on a 4k host. 269 * We dd this bit back here if we are confident this is not an issue 270 */ 271 pa_features[3] |= 0x20; 272 } 273 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 274 pa_features[24] |= 0x80; /* Transactional memory support */ 275 } 276 if (legacy_guest && pa_size > 40) { 277 /* Workaround for broken kernels that attempt (guest) radix 278 * mode when they can't handle it, if they see the radix bit set 279 * in pa-features. So hide it from them. */ 280 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 281 } 282 283 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 284 } 285 286 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 287 { 288 int ret = 0, offset, cpus_offset; 289 CPUState *cs; 290 char cpu_model[32]; 291 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 292 293 CPU_FOREACH(cs) { 294 PowerPCCPU *cpu = POWERPC_CPU(cs); 295 DeviceClass *dc = DEVICE_GET_CLASS(cs); 296 int index = spapr_get_vcpu_id(cpu); 297 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 298 299 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 300 continue; 301 } 302 303 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 304 305 cpus_offset = fdt_path_offset(fdt, "/cpus"); 306 if (cpus_offset < 0) { 307 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 308 if (cpus_offset < 0) { 309 return cpus_offset; 310 } 311 } 312 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 313 if (offset < 0) { 314 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 315 if (offset < 0) { 316 return offset; 317 } 318 } 319 320 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 321 pft_size_prop, sizeof(pft_size_prop)); 322 if (ret < 0) { 323 return ret; 324 } 325 326 if (nb_numa_nodes > 1) { 327 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); 328 if (ret < 0) { 329 return ret; 330 } 331 } 332 333 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 334 if (ret < 0) { 335 return ret; 336 } 337 338 spapr_populate_pa_features(spapr, cpu, fdt, offset, 339 spapr->cas_legacy_guest_workaround); 340 } 341 return ret; 342 } 343 344 static hwaddr spapr_node0_size(MachineState *machine) 345 { 346 if (nb_numa_nodes) { 347 int i; 348 for (i = 0; i < nb_numa_nodes; ++i) { 349 if (numa_info[i].node_mem) { 350 return MIN(pow2floor(numa_info[i].node_mem), 351 machine->ram_size); 352 } 353 } 354 } 355 return machine->ram_size; 356 } 357 358 static void add_str(GString *s, const gchar *s1) 359 { 360 g_string_append_len(s, s1, strlen(s1) + 1); 361 } 362 363 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 364 hwaddr size) 365 { 366 uint32_t associativity[] = { 367 cpu_to_be32(0x4), /* length */ 368 cpu_to_be32(0x0), cpu_to_be32(0x0), 369 cpu_to_be32(0x0), cpu_to_be32(nodeid) 370 }; 371 char mem_name[32]; 372 uint64_t mem_reg_property[2]; 373 int off; 374 375 mem_reg_property[0] = cpu_to_be64(start); 376 mem_reg_property[1] = cpu_to_be64(size); 377 378 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 379 off = fdt_add_subnode(fdt, 0, mem_name); 380 _FDT(off); 381 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 382 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 383 sizeof(mem_reg_property)))); 384 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 385 sizeof(associativity)))); 386 return off; 387 } 388 389 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 390 { 391 MachineState *machine = MACHINE(spapr); 392 hwaddr mem_start, node_size; 393 int i, nb_nodes = nb_numa_nodes; 394 NodeInfo *nodes = numa_info; 395 NodeInfo ramnode; 396 397 /* No NUMA nodes, assume there is just one node with whole RAM */ 398 if (!nb_numa_nodes) { 399 nb_nodes = 1; 400 ramnode.node_mem = machine->ram_size; 401 nodes = &ramnode; 402 } 403 404 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 405 if (!nodes[i].node_mem) { 406 continue; 407 } 408 if (mem_start >= machine->ram_size) { 409 node_size = 0; 410 } else { 411 node_size = nodes[i].node_mem; 412 if (node_size > machine->ram_size - mem_start) { 413 node_size = machine->ram_size - mem_start; 414 } 415 } 416 if (!mem_start) { 417 /* spapr_machine_init() checks for rma_size <= node0_size 418 * already */ 419 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 420 mem_start += spapr->rma_size; 421 node_size -= spapr->rma_size; 422 } 423 for ( ; node_size; ) { 424 hwaddr sizetmp = pow2floor(node_size); 425 426 /* mem_start != 0 here */ 427 if (ctzl(mem_start) < ctzl(sizetmp)) { 428 sizetmp = 1ULL << ctzl(mem_start); 429 } 430 431 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 432 node_size -= sizetmp; 433 mem_start += sizetmp; 434 } 435 } 436 437 return 0; 438 } 439 440 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 441 sPAPRMachineState *spapr) 442 { 443 PowerPCCPU *cpu = POWERPC_CPU(cs); 444 CPUPPCState *env = &cpu->env; 445 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 446 int index = spapr_get_vcpu_id(cpu); 447 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 448 0xffffffff, 0xffffffff}; 449 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 450 : SPAPR_TIMEBASE_FREQ; 451 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 452 uint32_t page_sizes_prop[64]; 453 size_t page_sizes_prop_size; 454 uint32_t vcpus_per_socket = smp_threads * smp_cores; 455 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 456 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 457 sPAPRDRConnector *drc; 458 int drc_index; 459 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 460 int i; 461 462 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 463 if (drc) { 464 drc_index = spapr_drc_index(drc); 465 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 466 } 467 468 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 469 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 470 471 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 472 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 473 env->dcache_line_size))); 474 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 475 env->dcache_line_size))); 476 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 477 env->icache_line_size))); 478 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 479 env->icache_line_size))); 480 481 if (pcc->l1_dcache_size) { 482 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 483 pcc->l1_dcache_size))); 484 } else { 485 warn_report("Unknown L1 dcache size for cpu"); 486 } 487 if (pcc->l1_icache_size) { 488 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 489 pcc->l1_icache_size))); 490 } else { 491 warn_report("Unknown L1 icache size for cpu"); 492 } 493 494 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 495 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 496 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 497 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 498 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 499 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 500 501 if (env->spr_cb[SPR_PURR].oea_read) { 502 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 503 } 504 505 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 506 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 507 segs, sizeof(segs)))); 508 } 509 510 /* Advertise VSX (vector extensions) if available 511 * 1 == VMX / Altivec available 512 * 2 == VSX available 513 * 514 * Only CPUs for which we create core types in spapr_cpu_core.c 515 * are possible, and all of those have VMX */ 516 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 517 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 518 } else { 519 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 520 } 521 522 /* Advertise DFP (Decimal Floating Point) if available 523 * 0 / no property == no DFP 524 * 1 == DFP available */ 525 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 526 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 527 } 528 529 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 530 sizeof(page_sizes_prop)); 531 if (page_sizes_prop_size) { 532 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 533 page_sizes_prop, page_sizes_prop_size))); 534 } 535 536 spapr_populate_pa_features(spapr, cpu, fdt, offset, false); 537 538 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 539 cs->cpu_index / vcpus_per_socket))); 540 541 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 542 pft_size_prop, sizeof(pft_size_prop)))); 543 544 if (nb_numa_nodes > 1) { 545 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 546 } 547 548 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 549 550 if (pcc->radix_page_info) { 551 for (i = 0; i < pcc->radix_page_info->count; i++) { 552 radix_AP_encodings[i] = 553 cpu_to_be32(pcc->radix_page_info->entries[i]); 554 } 555 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 556 radix_AP_encodings, 557 pcc->radix_page_info->count * 558 sizeof(radix_AP_encodings[0])))); 559 } 560 } 561 562 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 563 { 564 CPUState **rev; 565 CPUState *cs; 566 int n_cpus; 567 int cpus_offset; 568 char *nodename; 569 int i; 570 571 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 572 _FDT(cpus_offset); 573 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 574 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 575 576 /* 577 * We walk the CPUs in reverse order to ensure that CPU DT nodes 578 * created by fdt_add_subnode() end up in the right order in FDT 579 * for the guest kernel the enumerate the CPUs correctly. 580 * 581 * The CPU list cannot be traversed in reverse order, so we need 582 * to do extra work. 583 */ 584 n_cpus = 0; 585 rev = NULL; 586 CPU_FOREACH(cs) { 587 rev = g_renew(CPUState *, rev, n_cpus + 1); 588 rev[n_cpus++] = cs; 589 } 590 591 for (i = n_cpus - 1; i >= 0; i--) { 592 CPUState *cs = rev[i]; 593 PowerPCCPU *cpu = POWERPC_CPU(cs); 594 int index = spapr_get_vcpu_id(cpu); 595 DeviceClass *dc = DEVICE_GET_CLASS(cs); 596 int offset; 597 598 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 599 continue; 600 } 601 602 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 603 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 604 g_free(nodename); 605 _FDT(offset); 606 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 607 } 608 609 g_free(rev); 610 } 611 612 static int spapr_rng_populate_dt(void *fdt) 613 { 614 int node; 615 int ret; 616 617 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 618 if (node <= 0) { 619 return -1; 620 } 621 ret = fdt_setprop_string(fdt, node, "device_type", 622 "ibm,platform-facilities"); 623 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 624 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 625 626 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 627 if (node <= 0) { 628 return -1; 629 } 630 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 631 632 return ret ? -1 : 0; 633 } 634 635 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 636 { 637 MemoryDeviceInfoList *info; 638 639 for (info = list; info; info = info->next) { 640 MemoryDeviceInfo *value = info->value; 641 642 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 643 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 644 645 if (addr >= pcdimm_info->addr && 646 addr < (pcdimm_info->addr + pcdimm_info->size)) { 647 return pcdimm_info->node; 648 } 649 } 650 } 651 652 return -1; 653 } 654 655 struct sPAPRDrconfCellV2 { 656 uint32_t seq_lmbs; 657 uint64_t base_addr; 658 uint32_t drc_index; 659 uint32_t aa_index; 660 uint32_t flags; 661 } QEMU_PACKED; 662 663 typedef struct DrconfCellQueue { 664 struct sPAPRDrconfCellV2 cell; 665 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 666 } DrconfCellQueue; 667 668 static DrconfCellQueue * 669 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 670 uint32_t drc_index, uint32_t aa_index, 671 uint32_t flags) 672 { 673 DrconfCellQueue *elem; 674 675 elem = g_malloc0(sizeof(*elem)); 676 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 677 elem->cell.base_addr = cpu_to_be64(base_addr); 678 elem->cell.drc_index = cpu_to_be32(drc_index); 679 elem->cell.aa_index = cpu_to_be32(aa_index); 680 elem->cell.flags = cpu_to_be32(flags); 681 682 return elem; 683 } 684 685 /* ibm,dynamic-memory-v2 */ 686 static int spapr_populate_drmem_v2(sPAPRMachineState *spapr, void *fdt, 687 int offset, MemoryDeviceInfoList *dimms) 688 { 689 MachineState *machine = MACHINE(spapr); 690 uint8_t *int_buf, *cur_index, buf_len; 691 int ret; 692 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 693 uint64_t addr, cur_addr, size; 694 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 695 uint64_t mem_end = machine->device_memory->base + 696 memory_region_size(&machine->device_memory->mr); 697 uint32_t node, nr_entries = 0; 698 sPAPRDRConnector *drc; 699 DrconfCellQueue *elem, *next; 700 MemoryDeviceInfoList *info; 701 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 702 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 703 704 /* Entry to cover RAM and the gap area */ 705 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 706 SPAPR_LMB_FLAGS_RESERVED | 707 SPAPR_LMB_FLAGS_DRC_INVALID); 708 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 709 nr_entries++; 710 711 cur_addr = machine->device_memory->base; 712 for (info = dimms; info; info = info->next) { 713 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 714 715 addr = di->addr; 716 size = di->size; 717 node = di->node; 718 719 /* Entry for hot-pluggable area */ 720 if (cur_addr < addr) { 721 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 722 g_assert(drc); 723 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 724 cur_addr, spapr_drc_index(drc), -1, 0); 725 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 726 nr_entries++; 727 } 728 729 /* Entry for DIMM */ 730 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 731 g_assert(drc); 732 elem = spapr_get_drconf_cell(size / lmb_size, addr, 733 spapr_drc_index(drc), node, 734 SPAPR_LMB_FLAGS_ASSIGNED); 735 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 736 nr_entries++; 737 cur_addr = addr + size; 738 } 739 740 /* Entry for remaining hotpluggable area */ 741 if (cur_addr < mem_end) { 742 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 743 g_assert(drc); 744 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 745 cur_addr, spapr_drc_index(drc), -1, 0); 746 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 747 nr_entries++; 748 } 749 750 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 751 int_buf = cur_index = g_malloc0(buf_len); 752 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 753 cur_index += sizeof(nr_entries); 754 755 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 756 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 757 cur_index += sizeof(elem->cell); 758 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 759 g_free(elem); 760 } 761 762 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 763 g_free(int_buf); 764 if (ret < 0) { 765 return -1; 766 } 767 return 0; 768 } 769 770 /* ibm,dynamic-memory */ 771 static int spapr_populate_drmem_v1(sPAPRMachineState *spapr, void *fdt, 772 int offset, MemoryDeviceInfoList *dimms) 773 { 774 MachineState *machine = MACHINE(spapr); 775 int i, ret; 776 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 777 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 778 uint32_t nr_lmbs = (machine->device_memory->base + 779 memory_region_size(&machine->device_memory->mr)) / 780 lmb_size; 781 uint32_t *int_buf, *cur_index, buf_len; 782 783 /* 784 * Allocate enough buffer size to fit in ibm,dynamic-memory 785 */ 786 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 787 cur_index = int_buf = g_malloc0(buf_len); 788 int_buf[0] = cpu_to_be32(nr_lmbs); 789 cur_index++; 790 for (i = 0; i < nr_lmbs; i++) { 791 uint64_t addr = i * lmb_size; 792 uint32_t *dynamic_memory = cur_index; 793 794 if (i >= device_lmb_start) { 795 sPAPRDRConnector *drc; 796 797 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 798 g_assert(drc); 799 800 dynamic_memory[0] = cpu_to_be32(addr >> 32); 801 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 802 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 803 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 804 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 805 if (memory_region_present(get_system_memory(), addr)) { 806 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 807 } else { 808 dynamic_memory[5] = cpu_to_be32(0); 809 } 810 } else { 811 /* 812 * LMB information for RMA, boot time RAM and gap b/n RAM and 813 * device memory region -- all these are marked as reserved 814 * and as having no valid DRC. 815 */ 816 dynamic_memory[0] = cpu_to_be32(addr >> 32); 817 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 818 dynamic_memory[2] = cpu_to_be32(0); 819 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 820 dynamic_memory[4] = cpu_to_be32(-1); 821 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 822 SPAPR_LMB_FLAGS_DRC_INVALID); 823 } 824 825 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 826 } 827 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 828 g_free(int_buf); 829 if (ret < 0) { 830 return -1; 831 } 832 return 0; 833 } 834 835 /* 836 * Adds ibm,dynamic-reconfiguration-memory node. 837 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 838 * of this device tree node. 839 */ 840 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 841 { 842 MachineState *machine = MACHINE(spapr); 843 int ret, i, offset; 844 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 845 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 846 uint32_t *int_buf, *cur_index, buf_len; 847 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 848 MemoryDeviceInfoList *dimms = NULL; 849 850 /* 851 * Don't create the node if there is no device memory 852 */ 853 if (machine->ram_size == machine->maxram_size) { 854 return 0; 855 } 856 857 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 858 859 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 860 sizeof(prop_lmb_size)); 861 if (ret < 0) { 862 return ret; 863 } 864 865 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 866 if (ret < 0) { 867 return ret; 868 } 869 870 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 871 if (ret < 0) { 872 return ret; 873 } 874 875 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 876 dimms = qmp_memory_device_list(); 877 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 878 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); 879 } else { 880 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); 881 } 882 qapi_free_MemoryDeviceInfoList(dimms); 883 884 if (ret < 0) { 885 return ret; 886 } 887 888 /* ibm,associativity-lookup-arrays */ 889 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 890 cur_index = int_buf = g_malloc0(buf_len); 891 int_buf[0] = cpu_to_be32(nr_nodes); 892 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 893 cur_index += 2; 894 for (i = 0; i < nr_nodes; i++) { 895 uint32_t associativity[] = { 896 cpu_to_be32(0x0), 897 cpu_to_be32(0x0), 898 cpu_to_be32(0x0), 899 cpu_to_be32(i) 900 }; 901 memcpy(cur_index, associativity, sizeof(associativity)); 902 cur_index += 4; 903 } 904 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 905 (cur_index - int_buf) * sizeof(uint32_t)); 906 g_free(int_buf); 907 908 return ret; 909 } 910 911 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 912 sPAPROptionVector *ov5_updates) 913 { 914 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 915 int ret = 0, offset; 916 917 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 918 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 919 g_assert(smc->dr_lmb_enabled); 920 ret = spapr_populate_drconf_memory(spapr, fdt); 921 if (ret) { 922 goto out; 923 } 924 } 925 926 offset = fdt_path_offset(fdt, "/chosen"); 927 if (offset < 0) { 928 offset = fdt_add_subnode(fdt, 0, "chosen"); 929 if (offset < 0) { 930 return offset; 931 } 932 } 933 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 934 "ibm,architecture-vec-5"); 935 936 out: 937 return ret; 938 } 939 940 static bool spapr_hotplugged_dev_before_cas(void) 941 { 942 Object *drc_container, *obj; 943 ObjectProperty *prop; 944 ObjectPropertyIterator iter; 945 946 drc_container = container_get(object_get_root(), "/dr-connector"); 947 object_property_iter_init(&iter, drc_container); 948 while ((prop = object_property_iter_next(&iter))) { 949 if (!strstart(prop->type, "link<", NULL)) { 950 continue; 951 } 952 obj = object_property_get_link(drc_container, prop->name, NULL); 953 if (spapr_drc_needed(obj)) { 954 return true; 955 } 956 } 957 return false; 958 } 959 960 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 961 target_ulong addr, target_ulong size, 962 sPAPROptionVector *ov5_updates) 963 { 964 void *fdt, *fdt_skel; 965 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 966 967 if (spapr_hotplugged_dev_before_cas()) { 968 return 1; 969 } 970 971 if (size < sizeof(hdr) || size > FW_MAX_SIZE) { 972 error_report("SLOF provided an unexpected CAS buffer size " 973 TARGET_FMT_lu " (min: %zu, max: %u)", 974 size, sizeof(hdr), FW_MAX_SIZE); 975 exit(EXIT_FAILURE); 976 } 977 978 size -= sizeof(hdr); 979 980 /* Create skeleton */ 981 fdt_skel = g_malloc0(size); 982 _FDT((fdt_create(fdt_skel, size))); 983 _FDT((fdt_finish_reservemap(fdt_skel))); 984 _FDT((fdt_begin_node(fdt_skel, ""))); 985 _FDT((fdt_end_node(fdt_skel))); 986 _FDT((fdt_finish(fdt_skel))); 987 fdt = g_malloc0(size); 988 _FDT((fdt_open_into(fdt_skel, fdt, size))); 989 g_free(fdt_skel); 990 991 /* Fixup cpu nodes */ 992 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 993 994 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 995 return -1; 996 } 997 998 /* Pack resulting tree */ 999 _FDT((fdt_pack(fdt))); 1000 1001 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 1002 trace_spapr_cas_failed(size); 1003 return -1; 1004 } 1005 1006 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 1007 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 1008 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 1009 g_free(fdt); 1010 1011 return 0; 1012 } 1013 1014 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 1015 { 1016 int rtas; 1017 GString *hypertas = g_string_sized_new(256); 1018 GString *qemu_hypertas = g_string_sized_new(256); 1019 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 1020 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 1021 memory_region_size(&MACHINE(spapr)->device_memory->mr); 1022 uint32_t lrdr_capacity[] = { 1023 cpu_to_be32(max_device_addr >> 32), 1024 cpu_to_be32(max_device_addr & 0xffffffff), 1025 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 1026 cpu_to_be32(max_cpus / smp_threads), 1027 }; 1028 uint32_t maxdomains[] = { 1029 cpu_to_be32(4), 1030 cpu_to_be32(0), 1031 cpu_to_be32(0), 1032 cpu_to_be32(0), 1033 cpu_to_be32(nb_numa_nodes ? nb_numa_nodes : 1), 1034 }; 1035 1036 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 1037 1038 /* hypertas */ 1039 add_str(hypertas, "hcall-pft"); 1040 add_str(hypertas, "hcall-term"); 1041 add_str(hypertas, "hcall-dabr"); 1042 add_str(hypertas, "hcall-interrupt"); 1043 add_str(hypertas, "hcall-tce"); 1044 add_str(hypertas, "hcall-vio"); 1045 add_str(hypertas, "hcall-splpar"); 1046 add_str(hypertas, "hcall-bulk"); 1047 add_str(hypertas, "hcall-set-mode"); 1048 add_str(hypertas, "hcall-sprg0"); 1049 add_str(hypertas, "hcall-copy"); 1050 add_str(hypertas, "hcall-debug"); 1051 add_str(qemu_hypertas, "hcall-memop1"); 1052 1053 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 1054 add_str(hypertas, "hcall-multi-tce"); 1055 } 1056 1057 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 1058 add_str(hypertas, "hcall-hpt-resize"); 1059 } 1060 1061 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 1062 hypertas->str, hypertas->len)); 1063 g_string_free(hypertas, TRUE); 1064 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 1065 qemu_hypertas->str, qemu_hypertas->len)); 1066 g_string_free(qemu_hypertas, TRUE); 1067 1068 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 1069 refpoints, sizeof(refpoints))); 1070 1071 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 1072 maxdomains, sizeof(maxdomains))); 1073 1074 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 1075 RTAS_ERROR_LOG_MAX)); 1076 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 1077 RTAS_EVENT_SCAN_RATE)); 1078 1079 g_assert(msi_nonbroken); 1080 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 1081 1082 /* 1083 * According to PAPR, rtas ibm,os-term does not guarantee a return 1084 * back to the guest cpu. 1085 * 1086 * While an additional ibm,extended-os-term property indicates 1087 * that rtas call return will always occur. Set this property. 1088 */ 1089 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 1090 1091 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 1092 lrdr_capacity, sizeof(lrdr_capacity))); 1093 1094 spapr_dt_rtas_tokens(fdt, rtas); 1095 } 1096 1097 /* 1098 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 1099 * and the XIVE features that the guest may request and thus the valid 1100 * values for bytes 23..26 of option vector 5: 1101 */ 1102 static void spapr_dt_ov5_platform_support(sPAPRMachineState *spapr, void *fdt, 1103 int chosen) 1104 { 1105 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1106 1107 char val[2 * 4] = { 1108 23, spapr->irq->ov5, /* Xive mode. */ 1109 24, 0x00, /* Hash/Radix, filled in below. */ 1110 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1111 26, 0x40, /* Radix options: GTSE == yes. */ 1112 }; 1113 1114 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1115 first_ppc_cpu->compat_pvr)) { 1116 /* 1117 * If we're in a pre POWER9 compat mode then the guest should 1118 * do hash and use the legacy interrupt mode 1119 */ 1120 val[1] = 0x00; /* XICS */ 1121 val[3] = 0x00; /* Hash */ 1122 } else if (kvm_enabled()) { 1123 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1124 val[3] = 0x80; /* OV5_MMU_BOTH */ 1125 } else if (kvmppc_has_cap_mmu_radix()) { 1126 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1127 } else { 1128 val[3] = 0x00; /* Hash */ 1129 } 1130 } else { 1131 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1132 val[3] = 0xC0; 1133 } 1134 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1135 val, sizeof(val))); 1136 } 1137 1138 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 1139 { 1140 MachineState *machine = MACHINE(spapr); 1141 int chosen; 1142 const char *boot_device = machine->boot_order; 1143 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1144 size_t cb = 0; 1145 char *bootlist = get_boot_devices_list(&cb); 1146 1147 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1148 1149 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 1150 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1151 spapr->initrd_base)); 1152 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1153 spapr->initrd_base + spapr->initrd_size)); 1154 1155 if (spapr->kernel_size) { 1156 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 1157 cpu_to_be64(spapr->kernel_size) }; 1158 1159 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1160 &kprop, sizeof(kprop))); 1161 if (spapr->kernel_le) { 1162 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1163 } 1164 } 1165 if (boot_menu) { 1166 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1167 } 1168 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1169 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1170 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1171 1172 if (cb && bootlist) { 1173 int i; 1174 1175 for (i = 0; i < cb; i++) { 1176 if (bootlist[i] == '\n') { 1177 bootlist[i] = ' '; 1178 } 1179 } 1180 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1181 } 1182 1183 if (boot_device && strlen(boot_device)) { 1184 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1185 } 1186 1187 if (!spapr->has_graphics && stdout_path) { 1188 /* 1189 * "linux,stdout-path" and "stdout" properties are deprecated by linux 1190 * kernel. New platforms should only use the "stdout-path" property. Set 1191 * the new property and continue using older property to remain 1192 * compatible with the existing firmware. 1193 */ 1194 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1195 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1196 } 1197 1198 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1199 1200 g_free(stdout_path); 1201 g_free(bootlist); 1202 } 1203 1204 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 1205 { 1206 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1207 * KVM to work under pHyp with some guest co-operation */ 1208 int hypervisor; 1209 uint8_t hypercall[16]; 1210 1211 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1212 /* indicate KVM hypercall interface */ 1213 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1214 if (kvmppc_has_cap_fixup_hcalls()) { 1215 /* 1216 * Older KVM versions with older guest kernels were broken 1217 * with the magic page, don't allow the guest to map it. 1218 */ 1219 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1220 sizeof(hypercall))) { 1221 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1222 hypercall, sizeof(hypercall))); 1223 } 1224 } 1225 } 1226 1227 static void *spapr_build_fdt(sPAPRMachineState *spapr, 1228 hwaddr rtas_addr, 1229 hwaddr rtas_size) 1230 { 1231 MachineState *machine = MACHINE(spapr); 1232 MachineClass *mc = MACHINE_GET_CLASS(machine); 1233 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1234 int ret; 1235 void *fdt; 1236 sPAPRPHBState *phb; 1237 char *buf; 1238 1239 fdt = g_malloc0(FDT_MAX_SIZE); 1240 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 1241 1242 /* Root node */ 1243 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1244 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1245 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1246 1247 /* 1248 * Add info to guest to indentify which host is it being run on 1249 * and what is the uuid of the guest 1250 */ 1251 if (kvmppc_get_host_model(&buf)) { 1252 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1253 g_free(buf); 1254 } 1255 if (kvmppc_get_host_serial(&buf)) { 1256 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1257 g_free(buf); 1258 } 1259 1260 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1261 1262 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1263 if (qemu_uuid_set) { 1264 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1265 } 1266 g_free(buf); 1267 1268 if (qemu_get_vm_name()) { 1269 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1270 qemu_get_vm_name())); 1271 } 1272 1273 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1274 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1275 1276 /* /interrupt controller */ 1277 spapr->irq->dt_populate(spapr, spapr_max_server_number(spapr), fdt, 1278 PHANDLE_XICP); 1279 1280 ret = spapr_populate_memory(spapr, fdt); 1281 if (ret < 0) { 1282 error_report("couldn't setup memory nodes in fdt"); 1283 exit(1); 1284 } 1285 1286 /* /vdevice */ 1287 spapr_dt_vdevice(spapr->vio_bus, fdt); 1288 1289 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1290 ret = spapr_rng_populate_dt(fdt); 1291 if (ret < 0) { 1292 error_report("could not set up rng device in the fdt"); 1293 exit(1); 1294 } 1295 } 1296 1297 QLIST_FOREACH(phb, &spapr->phbs, list) { 1298 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt, 1299 spapr->irq->nr_msis); 1300 if (ret < 0) { 1301 error_report("couldn't setup PCI devices in fdt"); 1302 exit(1); 1303 } 1304 } 1305 1306 /* cpus */ 1307 spapr_populate_cpus_dt_node(fdt, spapr); 1308 1309 if (smc->dr_lmb_enabled) { 1310 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1311 } 1312 1313 if (mc->has_hotpluggable_cpus) { 1314 int offset = fdt_path_offset(fdt, "/cpus"); 1315 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1316 SPAPR_DR_CONNECTOR_TYPE_CPU); 1317 if (ret < 0) { 1318 error_report("Couldn't set up CPU DR device tree properties"); 1319 exit(1); 1320 } 1321 } 1322 1323 /* /event-sources */ 1324 spapr_dt_events(spapr, fdt); 1325 1326 /* /rtas */ 1327 spapr_dt_rtas(spapr, fdt); 1328 1329 /* /chosen */ 1330 spapr_dt_chosen(spapr, fdt); 1331 1332 /* /hypervisor */ 1333 if (kvm_enabled()) { 1334 spapr_dt_hypervisor(spapr, fdt); 1335 } 1336 1337 /* Build memory reserve map */ 1338 if (spapr->kernel_size) { 1339 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1340 } 1341 if (spapr->initrd_size) { 1342 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1343 } 1344 1345 /* ibm,client-architecture-support updates */ 1346 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1347 if (ret < 0) { 1348 error_report("couldn't setup CAS properties fdt"); 1349 exit(1); 1350 } 1351 1352 return fdt; 1353 } 1354 1355 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1356 { 1357 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1358 } 1359 1360 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1361 PowerPCCPU *cpu) 1362 { 1363 CPUPPCState *env = &cpu->env; 1364 1365 /* The TCG path should also be holding the BQL at this point */ 1366 g_assert(qemu_mutex_iothread_locked()); 1367 1368 if (msr_pr) { 1369 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1370 env->gpr[3] = H_PRIVILEGE; 1371 } else { 1372 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1373 } 1374 } 1375 1376 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) 1377 { 1378 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1379 1380 return spapr->patb_entry; 1381 } 1382 1383 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1384 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1385 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1386 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1387 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1388 1389 /* 1390 * Get the fd to access the kernel htab, re-opening it if necessary 1391 */ 1392 static int get_htab_fd(sPAPRMachineState *spapr) 1393 { 1394 Error *local_err = NULL; 1395 1396 if (spapr->htab_fd >= 0) { 1397 return spapr->htab_fd; 1398 } 1399 1400 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1401 if (spapr->htab_fd < 0) { 1402 error_report_err(local_err); 1403 } 1404 1405 return spapr->htab_fd; 1406 } 1407 1408 void close_htab_fd(sPAPRMachineState *spapr) 1409 { 1410 if (spapr->htab_fd >= 0) { 1411 close(spapr->htab_fd); 1412 } 1413 spapr->htab_fd = -1; 1414 } 1415 1416 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1417 { 1418 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1419 1420 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1421 } 1422 1423 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1424 { 1425 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1426 1427 assert(kvm_enabled()); 1428 1429 if (!spapr->htab) { 1430 return 0; 1431 } 1432 1433 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1434 } 1435 1436 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1437 hwaddr ptex, int n) 1438 { 1439 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1440 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1441 1442 if (!spapr->htab) { 1443 /* 1444 * HTAB is controlled by KVM. Fetch into temporary buffer 1445 */ 1446 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1447 kvmppc_read_hptes(hptes, ptex, n); 1448 return hptes; 1449 } 1450 1451 /* 1452 * HTAB is controlled by QEMU. Just point to the internally 1453 * accessible PTEG. 1454 */ 1455 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1456 } 1457 1458 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1459 const ppc_hash_pte64_t *hptes, 1460 hwaddr ptex, int n) 1461 { 1462 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1463 1464 if (!spapr->htab) { 1465 g_free((void *)hptes); 1466 } 1467 1468 /* Nothing to do for qemu managed HPT */ 1469 } 1470 1471 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1472 uint64_t pte0, uint64_t pte1) 1473 { 1474 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1475 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1476 1477 if (!spapr->htab) { 1478 kvmppc_write_hpte(ptex, pte0, pte1); 1479 } else { 1480 stq_p(spapr->htab + offset, pte0); 1481 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1482 } 1483 } 1484 1485 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1486 { 1487 int shift; 1488 1489 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1490 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1491 * that's much more than is needed for Linux guests */ 1492 shift = ctz64(pow2ceil(ramsize)) - 7; 1493 shift = MAX(shift, 18); /* Minimum architected size */ 1494 shift = MIN(shift, 46); /* Maximum architected size */ 1495 return shift; 1496 } 1497 1498 void spapr_free_hpt(sPAPRMachineState *spapr) 1499 { 1500 g_free(spapr->htab); 1501 spapr->htab = NULL; 1502 spapr->htab_shift = 0; 1503 close_htab_fd(spapr); 1504 } 1505 1506 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1507 Error **errp) 1508 { 1509 long rc; 1510 1511 /* Clean up any HPT info from a previous boot */ 1512 spapr_free_hpt(spapr); 1513 1514 rc = kvmppc_reset_htab(shift); 1515 if (rc < 0) { 1516 /* kernel-side HPT needed, but couldn't allocate one */ 1517 error_setg_errno(errp, errno, 1518 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1519 shift); 1520 /* This is almost certainly fatal, but if the caller really 1521 * wants to carry on with shift == 0, it's welcome to try */ 1522 } else if (rc > 0) { 1523 /* kernel-side HPT allocated */ 1524 if (rc != shift) { 1525 error_setg(errp, 1526 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1527 shift, rc); 1528 } 1529 1530 spapr->htab_shift = shift; 1531 spapr->htab = NULL; 1532 } else { 1533 /* kernel-side HPT not needed, allocate in userspace instead */ 1534 size_t size = 1ULL << shift; 1535 int i; 1536 1537 spapr->htab = qemu_memalign(size, size); 1538 if (!spapr->htab) { 1539 error_setg_errno(errp, errno, 1540 "Could not allocate HPT of order %d", shift); 1541 return; 1542 } 1543 1544 memset(spapr->htab, 0, size); 1545 spapr->htab_shift = shift; 1546 1547 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1548 DIRTY_HPTE(HPTE(spapr->htab, i)); 1549 } 1550 } 1551 /* We're setting up a hash table, so that means we're not radix */ 1552 spapr->patb_entry = 0; 1553 } 1554 1555 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) 1556 { 1557 int hpt_shift; 1558 1559 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1560 || (spapr->cas_reboot 1561 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1562 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1563 } else { 1564 uint64_t current_ram_size; 1565 1566 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1567 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1568 } 1569 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1570 1571 if (spapr->vrma_adjust) { 1572 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), 1573 spapr->htab_shift); 1574 } 1575 } 1576 1577 static int spapr_reset_drcs(Object *child, void *opaque) 1578 { 1579 sPAPRDRConnector *drc = 1580 (sPAPRDRConnector *) object_dynamic_cast(child, 1581 TYPE_SPAPR_DR_CONNECTOR); 1582 1583 if (drc) { 1584 spapr_drc_reset(drc); 1585 } 1586 1587 return 0; 1588 } 1589 1590 static void spapr_machine_reset(void) 1591 { 1592 MachineState *machine = MACHINE(qdev_get_machine()); 1593 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1594 PowerPCCPU *first_ppc_cpu; 1595 uint32_t rtas_limit; 1596 hwaddr rtas_addr, fdt_addr; 1597 void *fdt; 1598 int rc; 1599 1600 spapr_caps_apply(spapr); 1601 1602 first_ppc_cpu = POWERPC_CPU(first_cpu); 1603 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1604 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1605 spapr->max_compat_pvr)) { 1606 /* If using KVM with radix mode available, VCPUs can be started 1607 * without a HPT because KVM will start them in radix mode. 1608 * Set the GR bit in PATB so that we know there is no HPT. */ 1609 spapr->patb_entry = PATBE1_GR; 1610 } else { 1611 spapr_setup_hpt_and_vrma(spapr); 1612 } 1613 1614 /* if this reset wasn't generated by CAS, we should reset our 1615 * negotiated options and start from scratch */ 1616 if (!spapr->cas_reboot) { 1617 spapr_ovec_cleanup(spapr->ov5_cas); 1618 spapr->ov5_cas = spapr_ovec_new(); 1619 1620 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal); 1621 } 1622 1623 if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 1624 spapr_irq_msi_reset(spapr); 1625 } 1626 1627 qemu_devices_reset(); 1628 1629 /* 1630 * This is fixing some of the default configuration of the XIVE 1631 * devices. To be called after the reset of the machine devices. 1632 */ 1633 spapr_irq_reset(spapr, &error_fatal); 1634 1635 /* DRC reset may cause a device to be unplugged. This will cause troubles 1636 * if this device is used by another device (eg, a running vhost backend 1637 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1638 * situations, we reset DRCs after all devices have been reset. 1639 */ 1640 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1641 1642 spapr_clear_pending_events(spapr); 1643 1644 /* 1645 * We place the device tree and RTAS just below either the top of the RMA, 1646 * or just below 2GB, whichever is lowere, so that it can be 1647 * processed with 32-bit real mode code if necessary 1648 */ 1649 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1650 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1651 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1652 1653 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1654 1655 spapr_load_rtas(spapr, fdt, rtas_addr); 1656 1657 rc = fdt_pack(fdt); 1658 1659 /* Should only fail if we've built a corrupted tree */ 1660 assert(rc == 0); 1661 1662 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1663 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1664 fdt_totalsize(fdt), FDT_MAX_SIZE); 1665 exit(1); 1666 } 1667 1668 /* Load the fdt */ 1669 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1670 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1671 g_free(fdt); 1672 1673 /* Set up the entry state */ 1674 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); 1675 first_ppc_cpu->env.gpr[5] = 0; 1676 1677 spapr->cas_reboot = false; 1678 } 1679 1680 static void spapr_create_nvram(sPAPRMachineState *spapr) 1681 { 1682 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1683 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1684 1685 if (dinfo) { 1686 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1687 &error_fatal); 1688 } 1689 1690 qdev_init_nofail(dev); 1691 1692 spapr->nvram = (struct sPAPRNVRAM *)dev; 1693 } 1694 1695 static void spapr_rtc_create(sPAPRMachineState *spapr) 1696 { 1697 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); 1698 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), 1699 &error_fatal); 1700 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1701 &error_fatal); 1702 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1703 "date", &error_fatal); 1704 } 1705 1706 /* Returns whether we want to use VGA or not */ 1707 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1708 { 1709 switch (vga_interface_type) { 1710 case VGA_NONE: 1711 return false; 1712 case VGA_DEVICE: 1713 return true; 1714 case VGA_STD: 1715 case VGA_VIRTIO: 1716 return pci_vga_init(pci_bus) != NULL; 1717 default: 1718 error_setg(errp, 1719 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1720 return false; 1721 } 1722 } 1723 1724 static int spapr_pre_load(void *opaque) 1725 { 1726 int rc; 1727 1728 rc = spapr_caps_pre_load(opaque); 1729 if (rc) { 1730 return rc; 1731 } 1732 1733 return 0; 1734 } 1735 1736 static int spapr_post_load(void *opaque, int version_id) 1737 { 1738 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1739 int err = 0; 1740 1741 err = spapr_caps_post_migration(spapr); 1742 if (err) { 1743 return err; 1744 } 1745 1746 /* In earlier versions, there was no separate qdev for the PAPR 1747 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1748 * So when migrating from those versions, poke the incoming offset 1749 * value into the RTC device */ 1750 if (version_id < 3) { 1751 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1752 } 1753 1754 if (kvm_enabled() && spapr->patb_entry) { 1755 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1756 bool radix = !!(spapr->patb_entry & PATBE1_GR); 1757 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1758 1759 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1760 if (err) { 1761 error_report("Process table config unsupported by the host"); 1762 return -EINVAL; 1763 } 1764 } 1765 1766 err = spapr_irq_post_load(spapr, version_id); 1767 if (err) { 1768 return err; 1769 } 1770 1771 return err; 1772 } 1773 1774 static int spapr_pre_save(void *opaque) 1775 { 1776 int rc; 1777 1778 rc = spapr_caps_pre_save(opaque); 1779 if (rc) { 1780 return rc; 1781 } 1782 1783 return 0; 1784 } 1785 1786 static bool version_before_3(void *opaque, int version_id) 1787 { 1788 return version_id < 3; 1789 } 1790 1791 static bool spapr_pending_events_needed(void *opaque) 1792 { 1793 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1794 return !QTAILQ_EMPTY(&spapr->pending_events); 1795 } 1796 1797 static const VMStateDescription vmstate_spapr_event_entry = { 1798 .name = "spapr_event_log_entry", 1799 .version_id = 1, 1800 .minimum_version_id = 1, 1801 .fields = (VMStateField[]) { 1802 VMSTATE_UINT32(summary, sPAPREventLogEntry), 1803 VMSTATE_UINT32(extended_length, sPAPREventLogEntry), 1804 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0, 1805 NULL, extended_length), 1806 VMSTATE_END_OF_LIST() 1807 }, 1808 }; 1809 1810 static const VMStateDescription vmstate_spapr_pending_events = { 1811 .name = "spapr_pending_events", 1812 .version_id = 1, 1813 .minimum_version_id = 1, 1814 .needed = spapr_pending_events_needed, 1815 .fields = (VMStateField[]) { 1816 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1, 1817 vmstate_spapr_event_entry, sPAPREventLogEntry, next), 1818 VMSTATE_END_OF_LIST() 1819 }, 1820 }; 1821 1822 static bool spapr_ov5_cas_needed(void *opaque) 1823 { 1824 sPAPRMachineState *spapr = opaque; 1825 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1826 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1827 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1828 bool cas_needed; 1829 1830 /* Prior to the introduction of sPAPROptionVector, we had two option 1831 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1832 * Both of these options encode machine topology into the device-tree 1833 * in such a way that the now-booted OS should still be able to interact 1834 * appropriately with QEMU regardless of what options were actually 1835 * negotiatied on the source side. 1836 * 1837 * As such, we can avoid migrating the CAS-negotiated options if these 1838 * are the only options available on the current machine/platform. 1839 * Since these are the only options available for pseries-2.7 and 1840 * earlier, this allows us to maintain old->new/new->old migration 1841 * compatibility. 1842 * 1843 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1844 * via default pseries-2.8 machines and explicit command-line parameters. 1845 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1846 * of the actual CAS-negotiated values to continue working properly. For 1847 * example, availability of memory unplug depends on knowing whether 1848 * OV5_HP_EVT was negotiated via CAS. 1849 * 1850 * Thus, for any cases where the set of available CAS-negotiatable 1851 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1852 * include the CAS-negotiated options in the migration stream, unless 1853 * if they affect boot time behaviour only. 1854 */ 1855 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1856 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1857 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1858 1859 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1860 * the mask itself since in the future it's possible "legacy" bits may be 1861 * removed via machine options, which could generate a false positive 1862 * that breaks migration. 1863 */ 1864 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1865 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1866 1867 spapr_ovec_cleanup(ov5_mask); 1868 spapr_ovec_cleanup(ov5_legacy); 1869 spapr_ovec_cleanup(ov5_removed); 1870 1871 return cas_needed; 1872 } 1873 1874 static const VMStateDescription vmstate_spapr_ov5_cas = { 1875 .name = "spapr_option_vector_ov5_cas", 1876 .version_id = 1, 1877 .minimum_version_id = 1, 1878 .needed = spapr_ov5_cas_needed, 1879 .fields = (VMStateField[]) { 1880 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1881 vmstate_spapr_ovec, sPAPROptionVector), 1882 VMSTATE_END_OF_LIST() 1883 }, 1884 }; 1885 1886 static bool spapr_patb_entry_needed(void *opaque) 1887 { 1888 sPAPRMachineState *spapr = opaque; 1889 1890 return !!spapr->patb_entry; 1891 } 1892 1893 static const VMStateDescription vmstate_spapr_patb_entry = { 1894 .name = "spapr_patb_entry", 1895 .version_id = 1, 1896 .minimum_version_id = 1, 1897 .needed = spapr_patb_entry_needed, 1898 .fields = (VMStateField[]) { 1899 VMSTATE_UINT64(patb_entry, sPAPRMachineState), 1900 VMSTATE_END_OF_LIST() 1901 }, 1902 }; 1903 1904 static bool spapr_irq_map_needed(void *opaque) 1905 { 1906 sPAPRMachineState *spapr = opaque; 1907 1908 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1909 } 1910 1911 static const VMStateDescription vmstate_spapr_irq_map = { 1912 .name = "spapr_irq_map", 1913 .version_id = 1, 1914 .minimum_version_id = 1, 1915 .needed = spapr_irq_map_needed, 1916 .fields = (VMStateField[]) { 1917 VMSTATE_BITMAP(irq_map, sPAPRMachineState, 0, irq_map_nr), 1918 VMSTATE_END_OF_LIST() 1919 }, 1920 }; 1921 1922 static const VMStateDescription vmstate_spapr = { 1923 .name = "spapr", 1924 .version_id = 3, 1925 .minimum_version_id = 1, 1926 .pre_load = spapr_pre_load, 1927 .post_load = spapr_post_load, 1928 .pre_save = spapr_pre_save, 1929 .fields = (VMStateField[]) { 1930 /* used to be @next_irq */ 1931 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1932 1933 /* RTC offset */ 1934 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1935 1936 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1937 VMSTATE_END_OF_LIST() 1938 }, 1939 .subsections = (const VMStateDescription*[]) { 1940 &vmstate_spapr_ov5_cas, 1941 &vmstate_spapr_patb_entry, 1942 &vmstate_spapr_pending_events, 1943 &vmstate_spapr_cap_htm, 1944 &vmstate_spapr_cap_vsx, 1945 &vmstate_spapr_cap_dfp, 1946 &vmstate_spapr_cap_cfpc, 1947 &vmstate_spapr_cap_sbbc, 1948 &vmstate_spapr_cap_ibs, 1949 &vmstate_spapr_irq_map, 1950 &vmstate_spapr_cap_nested_kvm_hv, 1951 NULL 1952 } 1953 }; 1954 1955 static int htab_save_setup(QEMUFile *f, void *opaque) 1956 { 1957 sPAPRMachineState *spapr = opaque; 1958 1959 /* "Iteration" header */ 1960 if (!spapr->htab_shift) { 1961 qemu_put_be32(f, -1); 1962 } else { 1963 qemu_put_be32(f, spapr->htab_shift); 1964 } 1965 1966 if (spapr->htab) { 1967 spapr->htab_save_index = 0; 1968 spapr->htab_first_pass = true; 1969 } else { 1970 if (spapr->htab_shift) { 1971 assert(kvm_enabled()); 1972 } 1973 } 1974 1975 1976 return 0; 1977 } 1978 1979 static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr, 1980 int chunkstart, int n_valid, int n_invalid) 1981 { 1982 qemu_put_be32(f, chunkstart); 1983 qemu_put_be16(f, n_valid); 1984 qemu_put_be16(f, n_invalid); 1985 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1986 HASH_PTE_SIZE_64 * n_valid); 1987 } 1988 1989 static void htab_save_end_marker(QEMUFile *f) 1990 { 1991 qemu_put_be32(f, 0); 1992 qemu_put_be16(f, 0); 1993 qemu_put_be16(f, 0); 1994 } 1995 1996 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1997 int64_t max_ns) 1998 { 1999 bool has_timeout = max_ns != -1; 2000 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2001 int index = spapr->htab_save_index; 2002 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2003 2004 assert(spapr->htab_first_pass); 2005 2006 do { 2007 int chunkstart; 2008 2009 /* Consume invalid HPTEs */ 2010 while ((index < htabslots) 2011 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2012 CLEAN_HPTE(HPTE(spapr->htab, index)); 2013 index++; 2014 } 2015 2016 /* Consume valid HPTEs */ 2017 chunkstart = index; 2018 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2019 && HPTE_VALID(HPTE(spapr->htab, index))) { 2020 CLEAN_HPTE(HPTE(spapr->htab, index)); 2021 index++; 2022 } 2023 2024 if (index > chunkstart) { 2025 int n_valid = index - chunkstart; 2026 2027 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2028 2029 if (has_timeout && 2030 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2031 break; 2032 } 2033 } 2034 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2035 2036 if (index >= htabslots) { 2037 assert(index == htabslots); 2038 index = 0; 2039 spapr->htab_first_pass = false; 2040 } 2041 spapr->htab_save_index = index; 2042 } 2043 2044 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 2045 int64_t max_ns) 2046 { 2047 bool final = max_ns < 0; 2048 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2049 int examined = 0, sent = 0; 2050 int index = spapr->htab_save_index; 2051 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2052 2053 assert(!spapr->htab_first_pass); 2054 2055 do { 2056 int chunkstart, invalidstart; 2057 2058 /* Consume non-dirty HPTEs */ 2059 while ((index < htabslots) 2060 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2061 index++; 2062 examined++; 2063 } 2064 2065 chunkstart = index; 2066 /* Consume valid dirty HPTEs */ 2067 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2068 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2069 && HPTE_VALID(HPTE(spapr->htab, index))) { 2070 CLEAN_HPTE(HPTE(spapr->htab, index)); 2071 index++; 2072 examined++; 2073 } 2074 2075 invalidstart = index; 2076 /* Consume invalid dirty HPTEs */ 2077 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2078 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2079 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2080 CLEAN_HPTE(HPTE(spapr->htab, index)); 2081 index++; 2082 examined++; 2083 } 2084 2085 if (index > chunkstart) { 2086 int n_valid = invalidstart - chunkstart; 2087 int n_invalid = index - invalidstart; 2088 2089 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2090 sent += index - chunkstart; 2091 2092 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2093 break; 2094 } 2095 } 2096 2097 if (examined >= htabslots) { 2098 break; 2099 } 2100 2101 if (index >= htabslots) { 2102 assert(index == htabslots); 2103 index = 0; 2104 } 2105 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2106 2107 if (index >= htabslots) { 2108 assert(index == htabslots); 2109 index = 0; 2110 } 2111 2112 spapr->htab_save_index = index; 2113 2114 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2115 } 2116 2117 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2118 #define MAX_KVM_BUF_SIZE 2048 2119 2120 static int htab_save_iterate(QEMUFile *f, void *opaque) 2121 { 2122 sPAPRMachineState *spapr = opaque; 2123 int fd; 2124 int rc = 0; 2125 2126 /* Iteration header */ 2127 if (!spapr->htab_shift) { 2128 qemu_put_be32(f, -1); 2129 return 1; 2130 } else { 2131 qemu_put_be32(f, 0); 2132 } 2133 2134 if (!spapr->htab) { 2135 assert(kvm_enabled()); 2136 2137 fd = get_htab_fd(spapr); 2138 if (fd < 0) { 2139 return fd; 2140 } 2141 2142 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2143 if (rc < 0) { 2144 return rc; 2145 } 2146 } else if (spapr->htab_first_pass) { 2147 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2148 } else { 2149 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2150 } 2151 2152 htab_save_end_marker(f); 2153 2154 return rc; 2155 } 2156 2157 static int htab_save_complete(QEMUFile *f, void *opaque) 2158 { 2159 sPAPRMachineState *spapr = opaque; 2160 int fd; 2161 2162 /* Iteration header */ 2163 if (!spapr->htab_shift) { 2164 qemu_put_be32(f, -1); 2165 return 0; 2166 } else { 2167 qemu_put_be32(f, 0); 2168 } 2169 2170 if (!spapr->htab) { 2171 int rc; 2172 2173 assert(kvm_enabled()); 2174 2175 fd = get_htab_fd(spapr); 2176 if (fd < 0) { 2177 return fd; 2178 } 2179 2180 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2181 if (rc < 0) { 2182 return rc; 2183 } 2184 } else { 2185 if (spapr->htab_first_pass) { 2186 htab_save_first_pass(f, spapr, -1); 2187 } 2188 htab_save_later_pass(f, spapr, -1); 2189 } 2190 2191 /* End marker */ 2192 htab_save_end_marker(f); 2193 2194 return 0; 2195 } 2196 2197 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2198 { 2199 sPAPRMachineState *spapr = opaque; 2200 uint32_t section_hdr; 2201 int fd = -1; 2202 Error *local_err = NULL; 2203 2204 if (version_id < 1 || version_id > 1) { 2205 error_report("htab_load() bad version"); 2206 return -EINVAL; 2207 } 2208 2209 section_hdr = qemu_get_be32(f); 2210 2211 if (section_hdr == -1) { 2212 spapr_free_hpt(spapr); 2213 return 0; 2214 } 2215 2216 if (section_hdr) { 2217 /* First section gives the htab size */ 2218 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2219 if (local_err) { 2220 error_report_err(local_err); 2221 return -EINVAL; 2222 } 2223 return 0; 2224 } 2225 2226 if (!spapr->htab) { 2227 assert(kvm_enabled()); 2228 2229 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2230 if (fd < 0) { 2231 error_report_err(local_err); 2232 return fd; 2233 } 2234 } 2235 2236 while (true) { 2237 uint32_t index; 2238 uint16_t n_valid, n_invalid; 2239 2240 index = qemu_get_be32(f); 2241 n_valid = qemu_get_be16(f); 2242 n_invalid = qemu_get_be16(f); 2243 2244 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2245 /* End of Stream */ 2246 break; 2247 } 2248 2249 if ((index + n_valid + n_invalid) > 2250 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2251 /* Bad index in stream */ 2252 error_report( 2253 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2254 index, n_valid, n_invalid, spapr->htab_shift); 2255 return -EINVAL; 2256 } 2257 2258 if (spapr->htab) { 2259 if (n_valid) { 2260 qemu_get_buffer(f, HPTE(spapr->htab, index), 2261 HASH_PTE_SIZE_64 * n_valid); 2262 } 2263 if (n_invalid) { 2264 memset(HPTE(spapr->htab, index + n_valid), 0, 2265 HASH_PTE_SIZE_64 * n_invalid); 2266 } 2267 } else { 2268 int rc; 2269 2270 assert(fd >= 0); 2271 2272 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2273 if (rc < 0) { 2274 return rc; 2275 } 2276 } 2277 } 2278 2279 if (!spapr->htab) { 2280 assert(fd >= 0); 2281 close(fd); 2282 } 2283 2284 return 0; 2285 } 2286 2287 static void htab_save_cleanup(void *opaque) 2288 { 2289 sPAPRMachineState *spapr = opaque; 2290 2291 close_htab_fd(spapr); 2292 } 2293 2294 static SaveVMHandlers savevm_htab_handlers = { 2295 .save_setup = htab_save_setup, 2296 .save_live_iterate = htab_save_iterate, 2297 .save_live_complete_precopy = htab_save_complete, 2298 .save_cleanup = htab_save_cleanup, 2299 .load_state = htab_load, 2300 }; 2301 2302 static void spapr_boot_set(void *opaque, const char *boot_device, 2303 Error **errp) 2304 { 2305 MachineState *machine = MACHINE(opaque); 2306 machine->boot_order = g_strdup(boot_device); 2307 } 2308 2309 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 2310 { 2311 MachineState *machine = MACHINE(spapr); 2312 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2313 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2314 int i; 2315 2316 for (i = 0; i < nr_lmbs; i++) { 2317 uint64_t addr; 2318 2319 addr = i * lmb_size + machine->device_memory->base; 2320 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2321 addr / lmb_size); 2322 } 2323 } 2324 2325 /* 2326 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2327 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2328 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2329 */ 2330 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2331 { 2332 int i; 2333 2334 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2335 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2336 " is not aligned to %" PRIu64 " MiB", 2337 machine->ram_size, 2338 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2339 return; 2340 } 2341 2342 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2343 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2344 " is not aligned to %" PRIu64 " MiB", 2345 machine->ram_size, 2346 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2347 return; 2348 } 2349 2350 for (i = 0; i < nb_numa_nodes; i++) { 2351 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2352 error_setg(errp, 2353 "Node %d memory size 0x%" PRIx64 2354 " is not aligned to %" PRIu64 " MiB", 2355 i, numa_info[i].node_mem, 2356 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2357 return; 2358 } 2359 } 2360 } 2361 2362 /* find cpu slot in machine->possible_cpus by core_id */ 2363 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2364 { 2365 int index = id / smp_threads; 2366 2367 if (index >= ms->possible_cpus->len) { 2368 return NULL; 2369 } 2370 if (idx) { 2371 *idx = index; 2372 } 2373 return &ms->possible_cpus->cpus[index]; 2374 } 2375 2376 static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp) 2377 { 2378 Error *local_err = NULL; 2379 bool vsmt_user = !!spapr->vsmt; 2380 int kvm_smt = kvmppc_smt_threads(); 2381 int ret; 2382 2383 if (!kvm_enabled() && (smp_threads > 1)) { 2384 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2385 "on a pseries machine"); 2386 goto out; 2387 } 2388 if (!is_power_of_2(smp_threads)) { 2389 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2390 "machine because it must be a power of 2", smp_threads); 2391 goto out; 2392 } 2393 2394 /* Detemine the VSMT mode to use: */ 2395 if (vsmt_user) { 2396 if (spapr->vsmt < smp_threads) { 2397 error_setg(&local_err, "Cannot support VSMT mode %d" 2398 " because it must be >= threads/core (%d)", 2399 spapr->vsmt, smp_threads); 2400 goto out; 2401 } 2402 /* In this case, spapr->vsmt has been set by the command line */ 2403 } else { 2404 /* 2405 * Default VSMT value is tricky, because we need it to be as 2406 * consistent as possible (for migration), but this requires 2407 * changing it for at least some existing cases. We pick 8 as 2408 * the value that we'd get with KVM on POWER8, the 2409 * overwhelmingly common case in production systems. 2410 */ 2411 spapr->vsmt = MAX(8, smp_threads); 2412 } 2413 2414 /* KVM: If necessary, set the SMT mode: */ 2415 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2416 ret = kvmppc_set_smt_threads(spapr->vsmt); 2417 if (ret) { 2418 /* Looks like KVM isn't able to change VSMT mode */ 2419 error_setg(&local_err, 2420 "Failed to set KVM's VSMT mode to %d (errno %d)", 2421 spapr->vsmt, ret); 2422 /* We can live with that if the default one is big enough 2423 * for the number of threads, and a submultiple of the one 2424 * we want. In this case we'll waste some vcpu ids, but 2425 * behaviour will be correct */ 2426 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2427 warn_report_err(local_err); 2428 local_err = NULL; 2429 goto out; 2430 } else { 2431 if (!vsmt_user) { 2432 error_append_hint(&local_err, 2433 "On PPC, a VM with %d threads/core" 2434 " on a host with %d threads/core" 2435 " requires the use of VSMT mode %d.\n", 2436 smp_threads, kvm_smt, spapr->vsmt); 2437 } 2438 kvmppc_hint_smt_possible(&local_err); 2439 goto out; 2440 } 2441 } 2442 } 2443 /* else TCG: nothing to do currently */ 2444 out: 2445 error_propagate(errp, local_err); 2446 } 2447 2448 static void spapr_init_cpus(sPAPRMachineState *spapr) 2449 { 2450 MachineState *machine = MACHINE(spapr); 2451 MachineClass *mc = MACHINE_GET_CLASS(machine); 2452 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2453 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2454 const CPUArchIdList *possible_cpus; 2455 int boot_cores_nr = smp_cpus / smp_threads; 2456 int i; 2457 2458 possible_cpus = mc->possible_cpu_arch_ids(machine); 2459 if (mc->has_hotpluggable_cpus) { 2460 if (smp_cpus % smp_threads) { 2461 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2462 smp_cpus, smp_threads); 2463 exit(1); 2464 } 2465 if (max_cpus % smp_threads) { 2466 error_report("max_cpus (%u) must be multiple of threads (%u)", 2467 max_cpus, smp_threads); 2468 exit(1); 2469 } 2470 } else { 2471 if (max_cpus != smp_cpus) { 2472 error_report("This machine version does not support CPU hotplug"); 2473 exit(1); 2474 } 2475 boot_cores_nr = possible_cpus->len; 2476 } 2477 2478 if (smc->pre_2_10_has_unused_icps) { 2479 int i; 2480 2481 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2482 /* Dummy entries get deregistered when real ICPState objects 2483 * are registered during CPU core hotplug. 2484 */ 2485 pre_2_10_vmstate_register_dummy_icp(i); 2486 } 2487 } 2488 2489 for (i = 0; i < possible_cpus->len; i++) { 2490 int core_id = i * smp_threads; 2491 2492 if (mc->has_hotpluggable_cpus) { 2493 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2494 spapr_vcpu_id(spapr, core_id)); 2495 } 2496 2497 if (i < boot_cores_nr) { 2498 Object *core = object_new(type); 2499 int nr_threads = smp_threads; 2500 2501 /* Handle the partially filled core for older machine types */ 2502 if ((i + 1) * smp_threads >= smp_cpus) { 2503 nr_threads = smp_cpus - i * smp_threads; 2504 } 2505 2506 object_property_set_int(core, nr_threads, "nr-threads", 2507 &error_fatal); 2508 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2509 &error_fatal); 2510 object_property_set_bool(core, true, "realized", &error_fatal); 2511 2512 object_unref(core); 2513 } 2514 } 2515 } 2516 2517 /* pSeries LPAR / sPAPR hardware init */ 2518 static void spapr_machine_init(MachineState *machine) 2519 { 2520 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2521 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2522 const char *kernel_filename = machine->kernel_filename; 2523 const char *initrd_filename = machine->initrd_filename; 2524 PCIHostState *phb; 2525 int i; 2526 MemoryRegion *sysmem = get_system_memory(); 2527 MemoryRegion *ram = g_new(MemoryRegion, 1); 2528 hwaddr node0_size = spapr_node0_size(machine); 2529 long load_limit, fw_size; 2530 char *filename; 2531 Error *resize_hpt_err = NULL; 2532 2533 msi_nonbroken = true; 2534 2535 QLIST_INIT(&spapr->phbs); 2536 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2537 2538 /* Determine capabilities to run with */ 2539 spapr_caps_init(spapr); 2540 2541 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2542 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2543 /* 2544 * If the user explicitly requested a mode we should either 2545 * supply it, or fail completely (which we do below). But if 2546 * it's not set explicitly, we reset our mode to something 2547 * that works 2548 */ 2549 if (resize_hpt_err) { 2550 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2551 error_free(resize_hpt_err); 2552 resize_hpt_err = NULL; 2553 } else { 2554 spapr->resize_hpt = smc->resize_hpt_default; 2555 } 2556 } 2557 2558 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2559 2560 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2561 /* 2562 * User requested HPT resize, but this host can't supply it. Bail out 2563 */ 2564 error_report_err(resize_hpt_err); 2565 exit(1); 2566 } 2567 2568 spapr->rma_size = node0_size; 2569 2570 /* With KVM, we don't actually know whether KVM supports an 2571 * unbounded RMA (PR KVM) or is limited by the hash table size 2572 * (HV KVM using VRMA), so we always assume the latter 2573 * 2574 * In that case, we also limit the initial allocations for RTAS 2575 * etc... to 256M since we have no way to know what the VRMA size 2576 * is going to be as it depends on the size of the hash table 2577 * which isn't determined yet. 2578 */ 2579 if (kvm_enabled()) { 2580 spapr->vrma_adjust = 1; 2581 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2582 } 2583 2584 /* Actually we don't support unbounded RMA anymore since we added 2585 * proper emulation of HV mode. The max we can get is 16G which 2586 * also happens to be what we configure for PAPR mode so make sure 2587 * we don't do anything bigger than that 2588 */ 2589 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2590 2591 if (spapr->rma_size > node0_size) { 2592 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2593 spapr->rma_size); 2594 exit(1); 2595 } 2596 2597 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2598 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2599 2600 /* 2601 * VSMT must be set in order to be able to compute VCPU ids, ie to 2602 * call spapr_max_server_number() or spapr_vcpu_id(). 2603 */ 2604 spapr_set_vsmt_mode(spapr, &error_fatal); 2605 2606 /* Set up Interrupt Controller before we create the VCPUs */ 2607 spapr_irq_init(spapr, &error_fatal); 2608 2609 /* Set up containers for ibm,client-architecture-support negotiated options 2610 */ 2611 spapr->ov5 = spapr_ovec_new(); 2612 spapr->ov5_cas = spapr_ovec_new(); 2613 2614 if (smc->dr_lmb_enabled) { 2615 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2616 spapr_validate_node_memory(machine, &error_fatal); 2617 } 2618 2619 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2620 2621 /* advertise support for dedicated HP event source to guests */ 2622 if (spapr->use_hotplug_event_source) { 2623 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2624 } 2625 2626 /* advertise support for HPT resizing */ 2627 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2628 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2629 } 2630 2631 /* advertise support for ibm,dyamic-memory-v2 */ 2632 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2633 2634 /* advertise XIVE on POWER9 machines */ 2635 if (spapr->irq->ov5 & SPAPR_OV5_XIVE_EXPLOIT) { 2636 if (ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 2637 0, spapr->max_compat_pvr)) { 2638 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2639 } else { 2640 error_report("XIVE-only machines require a POWER9 CPU"); 2641 exit(1); 2642 } 2643 } 2644 2645 /* init CPUs */ 2646 spapr_init_cpus(spapr); 2647 2648 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2649 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2650 spapr->max_compat_pvr)) { 2651 /* KVM and TCG always allow GTSE with radix... */ 2652 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2653 } 2654 /* ... but not with hash (currently). */ 2655 2656 if (kvm_enabled()) { 2657 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2658 kvmppc_enable_logical_ci_hcalls(); 2659 kvmppc_enable_set_mode_hcall(); 2660 2661 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2662 kvmppc_enable_clear_ref_mod_hcalls(); 2663 } 2664 2665 /* allocate RAM */ 2666 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2667 machine->ram_size); 2668 memory_region_add_subregion(sysmem, 0, ram); 2669 2670 /* always allocate the device memory information */ 2671 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2672 2673 /* initialize hotplug memory address space */ 2674 if (machine->ram_size < machine->maxram_size) { 2675 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2676 /* 2677 * Limit the number of hotpluggable memory slots to half the number 2678 * slots that KVM supports, leaving the other half for PCI and other 2679 * devices. However ensure that number of slots doesn't drop below 32. 2680 */ 2681 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2682 SPAPR_MAX_RAM_SLOTS; 2683 2684 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2685 max_memslots = SPAPR_MAX_RAM_SLOTS; 2686 } 2687 if (machine->ram_slots > max_memslots) { 2688 error_report("Specified number of memory slots %" 2689 PRIu64" exceeds max supported %d", 2690 machine->ram_slots, max_memslots); 2691 exit(1); 2692 } 2693 2694 machine->device_memory->base = ROUND_UP(machine->ram_size, 2695 SPAPR_DEVICE_MEM_ALIGN); 2696 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2697 "device-memory", device_mem_size); 2698 memory_region_add_subregion(sysmem, machine->device_memory->base, 2699 &machine->device_memory->mr); 2700 } 2701 2702 if (smc->dr_lmb_enabled) { 2703 spapr_create_lmb_dr_connectors(spapr); 2704 } 2705 2706 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2707 if (!filename) { 2708 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2709 exit(1); 2710 } 2711 spapr->rtas_size = get_image_size(filename); 2712 if (spapr->rtas_size < 0) { 2713 error_report("Could not get size of LPAR rtas '%s'", filename); 2714 exit(1); 2715 } 2716 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2717 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2718 error_report("Could not load LPAR rtas '%s'", filename); 2719 exit(1); 2720 } 2721 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2722 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2723 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2724 exit(1); 2725 } 2726 g_free(filename); 2727 2728 /* Set up RTAS event infrastructure */ 2729 spapr_events_init(spapr); 2730 2731 /* Set up the RTC RTAS interfaces */ 2732 spapr_rtc_create(spapr); 2733 2734 /* Set up VIO bus */ 2735 spapr->vio_bus = spapr_vio_bus_init(); 2736 2737 for (i = 0; i < serial_max_hds(); i++) { 2738 if (serial_hd(i)) { 2739 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2740 } 2741 } 2742 2743 /* We always have at least the nvram device on VIO */ 2744 spapr_create_nvram(spapr); 2745 2746 /* Set up PCI */ 2747 spapr_pci_rtas_init(); 2748 2749 phb = spapr_create_phb(spapr, 0); 2750 2751 for (i = 0; i < nb_nics; i++) { 2752 NICInfo *nd = &nd_table[i]; 2753 2754 if (!nd->model) { 2755 nd->model = g_strdup("spapr-vlan"); 2756 } 2757 2758 if (g_str_equal(nd->model, "spapr-vlan") || 2759 g_str_equal(nd->model, "ibmveth")) { 2760 spapr_vlan_create(spapr->vio_bus, nd); 2761 } else { 2762 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2763 } 2764 } 2765 2766 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2767 spapr_vscsi_create(spapr->vio_bus); 2768 } 2769 2770 /* Graphics */ 2771 if (spapr_vga_init(phb->bus, &error_fatal)) { 2772 spapr->has_graphics = true; 2773 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2774 } 2775 2776 if (machine->usb) { 2777 if (smc->use_ohci_by_default) { 2778 pci_create_simple(phb->bus, -1, "pci-ohci"); 2779 } else { 2780 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2781 } 2782 2783 if (spapr->has_graphics) { 2784 USBBus *usb_bus = usb_bus_find(-1); 2785 2786 usb_create_simple(usb_bus, "usb-kbd"); 2787 usb_create_simple(usb_bus, "usb-mouse"); 2788 } 2789 } 2790 2791 if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) { 2792 error_report( 2793 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2794 MIN_RMA_SLOF); 2795 exit(1); 2796 } 2797 2798 if (kernel_filename) { 2799 uint64_t lowaddr = 0; 2800 2801 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2802 NULL, NULL, &lowaddr, NULL, 1, 2803 PPC_ELF_MACHINE, 0, 0); 2804 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2805 spapr->kernel_size = load_elf(kernel_filename, 2806 translate_kernel_address, NULL, NULL, 2807 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2808 0, 0); 2809 spapr->kernel_le = spapr->kernel_size > 0; 2810 } 2811 if (spapr->kernel_size < 0) { 2812 error_report("error loading %s: %s", kernel_filename, 2813 load_elf_strerror(spapr->kernel_size)); 2814 exit(1); 2815 } 2816 2817 /* load initrd */ 2818 if (initrd_filename) { 2819 /* Try to locate the initrd in the gap between the kernel 2820 * and the firmware. Add a bit of space just in case 2821 */ 2822 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2823 + 0x1ffff) & ~0xffff; 2824 spapr->initrd_size = load_image_targphys(initrd_filename, 2825 spapr->initrd_base, 2826 load_limit 2827 - spapr->initrd_base); 2828 if (spapr->initrd_size < 0) { 2829 error_report("could not load initial ram disk '%s'", 2830 initrd_filename); 2831 exit(1); 2832 } 2833 } 2834 } 2835 2836 if (bios_name == NULL) { 2837 bios_name = FW_FILE_NAME; 2838 } 2839 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2840 if (!filename) { 2841 error_report("Could not find LPAR firmware '%s'", bios_name); 2842 exit(1); 2843 } 2844 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2845 if (fw_size <= 0) { 2846 error_report("Could not load LPAR firmware '%s'", filename); 2847 exit(1); 2848 } 2849 g_free(filename); 2850 2851 /* FIXME: Should register things through the MachineState's qdev 2852 * interface, this is a legacy from the sPAPREnvironment structure 2853 * which predated MachineState but had a similar function */ 2854 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2855 register_savevm_live(NULL, "spapr/htab", -1, 1, 2856 &savevm_htab_handlers, spapr); 2857 2858 qemu_register_boot_set(spapr_boot_set, spapr); 2859 2860 if (kvm_enabled()) { 2861 /* to stop and start vmclock */ 2862 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2863 &spapr->tb); 2864 2865 kvmppc_spapr_enable_inkernel_multitce(); 2866 } 2867 } 2868 2869 static int spapr_kvm_type(const char *vm_type) 2870 { 2871 if (!vm_type) { 2872 return 0; 2873 } 2874 2875 if (!strcmp(vm_type, "HV")) { 2876 return 1; 2877 } 2878 2879 if (!strcmp(vm_type, "PR")) { 2880 return 2; 2881 } 2882 2883 error_report("Unknown kvm-type specified '%s'", vm_type); 2884 exit(1); 2885 } 2886 2887 /* 2888 * Implementation of an interface to adjust firmware path 2889 * for the bootindex property handling. 2890 */ 2891 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2892 DeviceState *dev) 2893 { 2894 #define CAST(type, obj, name) \ 2895 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2896 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2897 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2898 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 2899 2900 if (d) { 2901 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2902 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2903 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2904 2905 if (spapr) { 2906 /* 2907 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2908 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2909 * in the top 16 bits of the 64-bit LUN 2910 */ 2911 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2912 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2913 (uint64_t)id << 48); 2914 } else if (virtio) { 2915 /* 2916 * We use SRP luns of the form 01000000 | (target << 8) | lun 2917 * in the top 32 bits of the 64-bit LUN 2918 * Note: the quote above is from SLOF and it is wrong, 2919 * the actual binding is: 2920 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2921 */ 2922 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2923 if (d->lun >= 256) { 2924 /* Use the LUN "flat space addressing method" */ 2925 id |= 0x4000; 2926 } 2927 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2928 (uint64_t)id << 32); 2929 } else if (usb) { 2930 /* 2931 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2932 * in the top 32 bits of the 64-bit LUN 2933 */ 2934 unsigned usb_port = atoi(usb->port->path); 2935 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2936 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2937 (uint64_t)id << 32); 2938 } 2939 } 2940 2941 /* 2942 * SLOF probes the USB devices, and if it recognizes that the device is a 2943 * storage device, it changes its name to "storage" instead of "usb-host", 2944 * and additionally adds a child node for the SCSI LUN, so the correct 2945 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2946 */ 2947 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2948 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2949 if (usb_host_dev_is_scsi_storage(usbdev)) { 2950 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2951 } 2952 } 2953 2954 if (phb) { 2955 /* Replace "pci" with "pci@800000020000000" */ 2956 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2957 } 2958 2959 if (vsc) { 2960 /* Same logic as virtio above */ 2961 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 2962 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 2963 } 2964 2965 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 2966 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 2967 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 2968 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 2969 } 2970 2971 return NULL; 2972 } 2973 2974 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2975 { 2976 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2977 2978 return g_strdup(spapr->kvm_type); 2979 } 2980 2981 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2982 { 2983 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2984 2985 g_free(spapr->kvm_type); 2986 spapr->kvm_type = g_strdup(value); 2987 } 2988 2989 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2990 { 2991 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2992 2993 return spapr->use_hotplug_event_source; 2994 } 2995 2996 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2997 Error **errp) 2998 { 2999 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3000 3001 spapr->use_hotplug_event_source = value; 3002 } 3003 3004 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3005 { 3006 return true; 3007 } 3008 3009 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3010 { 3011 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3012 3013 switch (spapr->resize_hpt) { 3014 case SPAPR_RESIZE_HPT_DEFAULT: 3015 return g_strdup("default"); 3016 case SPAPR_RESIZE_HPT_DISABLED: 3017 return g_strdup("disabled"); 3018 case SPAPR_RESIZE_HPT_ENABLED: 3019 return g_strdup("enabled"); 3020 case SPAPR_RESIZE_HPT_REQUIRED: 3021 return g_strdup("required"); 3022 } 3023 g_assert_not_reached(); 3024 } 3025 3026 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3027 { 3028 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3029 3030 if (strcmp(value, "default") == 0) { 3031 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3032 } else if (strcmp(value, "disabled") == 0) { 3033 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3034 } else if (strcmp(value, "enabled") == 0) { 3035 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3036 } else if (strcmp(value, "required") == 0) { 3037 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3038 } else { 3039 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3040 } 3041 } 3042 3043 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 3044 void *opaque, Error **errp) 3045 { 3046 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3047 } 3048 3049 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 3050 void *opaque, Error **errp) 3051 { 3052 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3053 } 3054 3055 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3056 { 3057 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3058 3059 if (spapr->irq == &spapr_irq_xics_legacy) { 3060 return g_strdup("legacy"); 3061 } else if (spapr->irq == &spapr_irq_xics) { 3062 return g_strdup("xics"); 3063 } else if (spapr->irq == &spapr_irq_xive) { 3064 return g_strdup("xive"); 3065 } 3066 g_assert_not_reached(); 3067 } 3068 3069 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3070 { 3071 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3072 3073 /* The legacy IRQ backend can not be set */ 3074 if (strcmp(value, "xics") == 0) { 3075 spapr->irq = &spapr_irq_xics; 3076 } else if (strcmp(value, "xive") == 0) { 3077 spapr->irq = &spapr_irq_xive; 3078 } else { 3079 error_setg(errp, "Bad value for \"ic-mode\" property"); 3080 } 3081 } 3082 3083 static void spapr_instance_init(Object *obj) 3084 { 3085 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3086 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3087 3088 spapr->htab_fd = -1; 3089 spapr->use_hotplug_event_source = true; 3090 object_property_add_str(obj, "kvm-type", 3091 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 3092 object_property_set_description(obj, "kvm-type", 3093 "Specifies the KVM virtualization mode (HV, PR)", 3094 NULL); 3095 object_property_add_bool(obj, "modern-hotplug-events", 3096 spapr_get_modern_hotplug_events, 3097 spapr_set_modern_hotplug_events, 3098 NULL); 3099 object_property_set_description(obj, "modern-hotplug-events", 3100 "Use dedicated hotplug event mechanism in" 3101 " place of standard EPOW events when possible" 3102 " (required for memory hot-unplug support)", 3103 NULL); 3104 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3105 "Maximum permitted CPU compatibility mode", 3106 &error_fatal); 3107 3108 object_property_add_str(obj, "resize-hpt", 3109 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 3110 object_property_set_description(obj, "resize-hpt", 3111 "Resizing of the Hash Page Table (enabled, disabled, required)", 3112 NULL); 3113 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 3114 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 3115 object_property_set_description(obj, "vsmt", 3116 "Virtual SMT: KVM behaves as if this were" 3117 " the host's SMT mode", &error_abort); 3118 object_property_add_bool(obj, "vfio-no-msix-emulation", 3119 spapr_get_msix_emulation, NULL, NULL); 3120 3121 /* The machine class defines the default interrupt controller mode */ 3122 spapr->irq = smc->irq; 3123 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3124 spapr_set_ic_mode, NULL); 3125 object_property_set_description(obj, "ic-mode", 3126 "Specifies the interrupt controller mode (xics, xive)", 3127 NULL); 3128 } 3129 3130 static void spapr_machine_finalizefn(Object *obj) 3131 { 3132 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3133 3134 g_free(spapr->kvm_type); 3135 } 3136 3137 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3138 { 3139 cpu_synchronize_state(cs); 3140 ppc_cpu_do_system_reset(cs); 3141 } 3142 3143 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3144 { 3145 CPUState *cs; 3146 3147 CPU_FOREACH(cs) { 3148 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3149 } 3150 } 3151 3152 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3153 uint32_t node, bool dedicated_hp_event_source, 3154 Error **errp) 3155 { 3156 sPAPRDRConnector *drc; 3157 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3158 int i, fdt_offset, fdt_size; 3159 void *fdt; 3160 uint64_t addr = addr_start; 3161 bool hotplugged = spapr_drc_hotplugged(dev); 3162 Error *local_err = NULL; 3163 3164 for (i = 0; i < nr_lmbs; i++) { 3165 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3166 addr / SPAPR_MEMORY_BLOCK_SIZE); 3167 g_assert(drc); 3168 3169 fdt = create_device_tree(&fdt_size); 3170 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 3171 SPAPR_MEMORY_BLOCK_SIZE); 3172 3173 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 3174 if (local_err) { 3175 while (addr > addr_start) { 3176 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3177 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3178 addr / SPAPR_MEMORY_BLOCK_SIZE); 3179 spapr_drc_detach(drc); 3180 } 3181 g_free(fdt); 3182 error_propagate(errp, local_err); 3183 return; 3184 } 3185 if (!hotplugged) { 3186 spapr_drc_reset(drc); 3187 } 3188 addr += SPAPR_MEMORY_BLOCK_SIZE; 3189 } 3190 /* send hotplug notification to the 3191 * guest only in case of hotplugged memory 3192 */ 3193 if (hotplugged) { 3194 if (dedicated_hp_event_source) { 3195 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3196 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3197 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3198 nr_lmbs, 3199 spapr_drc_index(drc)); 3200 } else { 3201 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3202 nr_lmbs); 3203 } 3204 } 3205 } 3206 3207 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3208 Error **errp) 3209 { 3210 Error *local_err = NULL; 3211 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3212 PCDIMMDevice *dimm = PC_DIMM(dev); 3213 uint64_t size, addr; 3214 uint32_t node; 3215 3216 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3217 3218 pc_dimm_plug(dimm, MACHINE(ms), &local_err); 3219 if (local_err) { 3220 goto out; 3221 } 3222 3223 addr = object_property_get_uint(OBJECT(dimm), 3224 PC_DIMM_ADDR_PROP, &local_err); 3225 if (local_err) { 3226 goto out_unplug; 3227 } 3228 3229 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, 3230 &error_abort); 3231 spapr_add_lmbs(dev, addr, size, node, 3232 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3233 &local_err); 3234 if (local_err) { 3235 goto out_unplug; 3236 } 3237 3238 return; 3239 3240 out_unplug: 3241 pc_dimm_unplug(dimm, MACHINE(ms)); 3242 out: 3243 error_propagate(errp, local_err); 3244 } 3245 3246 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3247 Error **errp) 3248 { 3249 const sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3250 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3251 PCDIMMDevice *dimm = PC_DIMM(dev); 3252 Error *local_err = NULL; 3253 uint64_t size; 3254 Object *memdev; 3255 hwaddr pagesize; 3256 3257 if (!smc->dr_lmb_enabled) { 3258 error_setg(errp, "Memory hotplug not supported for this machine"); 3259 return; 3260 } 3261 3262 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3263 if (local_err) { 3264 error_propagate(errp, local_err); 3265 return; 3266 } 3267 3268 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3269 error_setg(errp, "Hotplugged memory size must be a multiple of " 3270 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3271 return; 3272 } 3273 3274 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3275 &error_abort); 3276 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3277 spapr_check_pagesize(spapr, pagesize, &local_err); 3278 if (local_err) { 3279 error_propagate(errp, local_err); 3280 return; 3281 } 3282 3283 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3284 } 3285 3286 struct sPAPRDIMMState { 3287 PCDIMMDevice *dimm; 3288 uint32_t nr_lmbs; 3289 QTAILQ_ENTRY(sPAPRDIMMState) next; 3290 }; 3291 3292 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, 3293 PCDIMMDevice *dimm) 3294 { 3295 sPAPRDIMMState *dimm_state = NULL; 3296 3297 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3298 if (dimm_state->dimm == dimm) { 3299 break; 3300 } 3301 } 3302 return dimm_state; 3303 } 3304 3305 static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, 3306 uint32_t nr_lmbs, 3307 PCDIMMDevice *dimm) 3308 { 3309 sPAPRDIMMState *ds = NULL; 3310 3311 /* 3312 * If this request is for a DIMM whose removal had failed earlier 3313 * (due to guest's refusal to remove the LMBs), we would have this 3314 * dimm already in the pending_dimm_unplugs list. In that 3315 * case don't add again. 3316 */ 3317 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3318 if (!ds) { 3319 ds = g_malloc0(sizeof(sPAPRDIMMState)); 3320 ds->nr_lmbs = nr_lmbs; 3321 ds->dimm = dimm; 3322 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3323 } 3324 return ds; 3325 } 3326 3327 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, 3328 sPAPRDIMMState *dimm_state) 3329 { 3330 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3331 g_free(dimm_state); 3332 } 3333 3334 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, 3335 PCDIMMDevice *dimm) 3336 { 3337 sPAPRDRConnector *drc; 3338 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3339 &error_abort); 3340 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3341 uint32_t avail_lmbs = 0; 3342 uint64_t addr_start, addr; 3343 int i; 3344 3345 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3346 &error_abort); 3347 3348 addr = addr_start; 3349 for (i = 0; i < nr_lmbs; i++) { 3350 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3351 addr / SPAPR_MEMORY_BLOCK_SIZE); 3352 g_assert(drc); 3353 if (drc->dev) { 3354 avail_lmbs++; 3355 } 3356 addr += SPAPR_MEMORY_BLOCK_SIZE; 3357 } 3358 3359 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3360 } 3361 3362 /* Callback to be called during DRC release. */ 3363 void spapr_lmb_release(DeviceState *dev) 3364 { 3365 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3366 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3367 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3368 3369 /* This information will get lost if a migration occurs 3370 * during the unplug process. In this case recover it. */ 3371 if (ds == NULL) { 3372 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3373 g_assert(ds); 3374 /* The DRC being examined by the caller at least must be counted */ 3375 g_assert(ds->nr_lmbs); 3376 } 3377 3378 if (--ds->nr_lmbs) { 3379 return; 3380 } 3381 3382 /* 3383 * Now that all the LMBs have been removed by the guest, call the 3384 * unplug handler chain. This can never fail. 3385 */ 3386 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3387 } 3388 3389 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3390 { 3391 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3392 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3393 3394 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3395 object_unparent(OBJECT(dev)); 3396 spapr_pending_dimm_unplugs_remove(spapr, ds); 3397 } 3398 3399 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3400 DeviceState *dev, Error **errp) 3401 { 3402 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3403 Error *local_err = NULL; 3404 PCDIMMDevice *dimm = PC_DIMM(dev); 3405 uint32_t nr_lmbs; 3406 uint64_t size, addr_start, addr; 3407 int i; 3408 sPAPRDRConnector *drc; 3409 3410 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3411 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3412 3413 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3414 &local_err); 3415 if (local_err) { 3416 goto out; 3417 } 3418 3419 /* 3420 * An existing pending dimm state for this DIMM means that there is an 3421 * unplug operation in progress, waiting for the spapr_lmb_release 3422 * callback to complete the job (BQL can't cover that far). In this case, 3423 * bail out to avoid detaching DRCs that were already released. 3424 */ 3425 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3426 error_setg(&local_err, 3427 "Memory unplug already in progress for device %s", 3428 dev->id); 3429 goto out; 3430 } 3431 3432 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3433 3434 addr = addr_start; 3435 for (i = 0; i < nr_lmbs; i++) { 3436 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3437 addr / SPAPR_MEMORY_BLOCK_SIZE); 3438 g_assert(drc); 3439 3440 spapr_drc_detach(drc); 3441 addr += SPAPR_MEMORY_BLOCK_SIZE; 3442 } 3443 3444 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3445 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3446 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3447 nr_lmbs, spapr_drc_index(drc)); 3448 out: 3449 error_propagate(errp, local_err); 3450 } 3451 3452 static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 3453 sPAPRMachineState *spapr) 3454 { 3455 PowerPCCPU *cpu = POWERPC_CPU(cs); 3456 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3457 int id = spapr_get_vcpu_id(cpu); 3458 void *fdt; 3459 int offset, fdt_size; 3460 char *nodename; 3461 3462 fdt = create_device_tree(&fdt_size); 3463 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3464 offset = fdt_add_subnode(fdt, 0, nodename); 3465 3466 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3467 g_free(nodename); 3468 3469 *fdt_offset = offset; 3470 return fdt; 3471 } 3472 3473 /* Callback to be called during DRC release. */ 3474 void spapr_core_release(DeviceState *dev) 3475 { 3476 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3477 3478 /* Call the unplug handler chain. This can never fail. */ 3479 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3480 } 3481 3482 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3483 { 3484 MachineState *ms = MACHINE(hotplug_dev); 3485 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3486 CPUCore *cc = CPU_CORE(dev); 3487 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3488 3489 if (smc->pre_2_10_has_unused_icps) { 3490 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3491 int i; 3492 3493 for (i = 0; i < cc->nr_threads; i++) { 3494 CPUState *cs = CPU(sc->threads[i]); 3495 3496 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3497 } 3498 } 3499 3500 assert(core_slot); 3501 core_slot->cpu = NULL; 3502 object_unparent(OBJECT(dev)); 3503 } 3504 3505 static 3506 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3507 Error **errp) 3508 { 3509 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3510 int index; 3511 sPAPRDRConnector *drc; 3512 CPUCore *cc = CPU_CORE(dev); 3513 3514 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3515 error_setg(errp, "Unable to find CPU core with core-id: %d", 3516 cc->core_id); 3517 return; 3518 } 3519 if (index == 0) { 3520 error_setg(errp, "Boot CPU core may not be unplugged"); 3521 return; 3522 } 3523 3524 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3525 spapr_vcpu_id(spapr, cc->core_id)); 3526 g_assert(drc); 3527 3528 spapr_drc_detach(drc); 3529 3530 spapr_hotplug_req_remove_by_index(drc); 3531 } 3532 3533 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3534 Error **errp) 3535 { 3536 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3537 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3538 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3539 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3540 CPUCore *cc = CPU_CORE(dev); 3541 CPUState *cs = CPU(core->threads[0]); 3542 sPAPRDRConnector *drc; 3543 Error *local_err = NULL; 3544 CPUArchId *core_slot; 3545 int index; 3546 bool hotplugged = spapr_drc_hotplugged(dev); 3547 3548 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3549 if (!core_slot) { 3550 error_setg(errp, "Unable to find CPU core with core-id: %d", 3551 cc->core_id); 3552 return; 3553 } 3554 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3555 spapr_vcpu_id(spapr, cc->core_id)); 3556 3557 g_assert(drc || !mc->has_hotpluggable_cpus); 3558 3559 if (drc) { 3560 void *fdt; 3561 int fdt_offset; 3562 3563 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 3564 3565 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 3566 if (local_err) { 3567 g_free(fdt); 3568 error_propagate(errp, local_err); 3569 return; 3570 } 3571 3572 if (hotplugged) { 3573 /* 3574 * Send hotplug notification interrupt to the guest only 3575 * in case of hotplugged CPUs. 3576 */ 3577 spapr_hotplug_req_add_by_index(drc); 3578 } else { 3579 spapr_drc_reset(drc); 3580 } 3581 } 3582 3583 core_slot->cpu = OBJECT(dev); 3584 3585 if (smc->pre_2_10_has_unused_icps) { 3586 int i; 3587 3588 for (i = 0; i < cc->nr_threads; i++) { 3589 cs = CPU(core->threads[i]); 3590 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3591 } 3592 } 3593 } 3594 3595 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3596 Error **errp) 3597 { 3598 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3599 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3600 Error *local_err = NULL; 3601 CPUCore *cc = CPU_CORE(dev); 3602 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3603 const char *type = object_get_typename(OBJECT(dev)); 3604 CPUArchId *core_slot; 3605 int index; 3606 3607 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3608 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3609 goto out; 3610 } 3611 3612 if (strcmp(base_core_type, type)) { 3613 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3614 goto out; 3615 } 3616 3617 if (cc->core_id % smp_threads) { 3618 error_setg(&local_err, "invalid core id %d", cc->core_id); 3619 goto out; 3620 } 3621 3622 /* 3623 * In general we should have homogeneous threads-per-core, but old 3624 * (pre hotplug support) machine types allow the last core to have 3625 * reduced threads as a compatibility hack for when we allowed 3626 * total vcpus not a multiple of threads-per-core. 3627 */ 3628 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3629 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3630 cc->nr_threads, smp_threads); 3631 goto out; 3632 } 3633 3634 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3635 if (!core_slot) { 3636 error_setg(&local_err, "core id %d out of range", cc->core_id); 3637 goto out; 3638 } 3639 3640 if (core_slot->cpu) { 3641 error_setg(&local_err, "core %d already populated", cc->core_id); 3642 goto out; 3643 } 3644 3645 numa_cpu_pre_plug(core_slot, dev, &local_err); 3646 3647 out: 3648 error_propagate(errp, local_err); 3649 } 3650 3651 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 3652 DeviceState *dev, Error **errp) 3653 { 3654 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3655 spapr_memory_plug(hotplug_dev, dev, errp); 3656 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3657 spapr_core_plug(hotplug_dev, dev, errp); 3658 } 3659 } 3660 3661 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 3662 DeviceState *dev, Error **errp) 3663 { 3664 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3665 spapr_memory_unplug(hotplug_dev, dev); 3666 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3667 spapr_core_unplug(hotplug_dev, dev); 3668 } 3669 } 3670 3671 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 3672 DeviceState *dev, Error **errp) 3673 { 3674 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3675 MachineClass *mc = MACHINE_GET_CLASS(sms); 3676 3677 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3678 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3679 spapr_memory_unplug_request(hotplug_dev, dev, errp); 3680 } else { 3681 /* NOTE: this means there is a window after guest reset, prior to 3682 * CAS negotiation, where unplug requests will fail due to the 3683 * capability not being detected yet. This is a bit different than 3684 * the case with PCI unplug, where the events will be queued and 3685 * eventually handled by the guest after boot 3686 */ 3687 error_setg(errp, "Memory hot unplug not supported for this guest"); 3688 } 3689 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3690 if (!mc->has_hotpluggable_cpus) { 3691 error_setg(errp, "CPU hot unplug not supported on this machine"); 3692 return; 3693 } 3694 spapr_core_unplug_request(hotplug_dev, dev, errp); 3695 } 3696 } 3697 3698 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 3699 DeviceState *dev, Error **errp) 3700 { 3701 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3702 spapr_memory_pre_plug(hotplug_dev, dev, errp); 3703 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3704 spapr_core_pre_plug(hotplug_dev, dev, errp); 3705 } 3706 } 3707 3708 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 3709 DeviceState *dev) 3710 { 3711 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3712 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3713 return HOTPLUG_HANDLER(machine); 3714 } 3715 return NULL; 3716 } 3717 3718 static CpuInstanceProperties 3719 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 3720 { 3721 CPUArchId *core_slot; 3722 MachineClass *mc = MACHINE_GET_CLASS(machine); 3723 3724 /* make sure possible_cpu are intialized */ 3725 mc->possible_cpu_arch_ids(machine); 3726 /* get CPU core slot containing thread that matches cpu_index */ 3727 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 3728 assert(core_slot); 3729 return core_slot->props; 3730 } 3731 3732 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 3733 { 3734 return idx / smp_cores % nb_numa_nodes; 3735 } 3736 3737 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 3738 { 3739 int i; 3740 const char *core_type; 3741 int spapr_max_cores = max_cpus / smp_threads; 3742 MachineClass *mc = MACHINE_GET_CLASS(machine); 3743 3744 if (!mc->has_hotpluggable_cpus) { 3745 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 3746 } 3747 if (machine->possible_cpus) { 3748 assert(machine->possible_cpus->len == spapr_max_cores); 3749 return machine->possible_cpus; 3750 } 3751 3752 core_type = spapr_get_cpu_core_type(machine->cpu_type); 3753 if (!core_type) { 3754 error_report("Unable to find sPAPR CPU Core definition"); 3755 exit(1); 3756 } 3757 3758 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 3759 sizeof(CPUArchId) * spapr_max_cores); 3760 machine->possible_cpus->len = spapr_max_cores; 3761 for (i = 0; i < machine->possible_cpus->len; i++) { 3762 int core_id = i * smp_threads; 3763 3764 machine->possible_cpus->cpus[i].type = core_type; 3765 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 3766 machine->possible_cpus->cpus[i].arch_id = core_id; 3767 machine->possible_cpus->cpus[i].props.has_core_id = true; 3768 machine->possible_cpus->cpus[i].props.core_id = core_id; 3769 } 3770 return machine->possible_cpus; 3771 } 3772 3773 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 3774 uint64_t *buid, hwaddr *pio, 3775 hwaddr *mmio32, hwaddr *mmio64, 3776 unsigned n_dma, uint32_t *liobns, Error **errp) 3777 { 3778 /* 3779 * New-style PHB window placement. 3780 * 3781 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 3782 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 3783 * windows. 3784 * 3785 * Some guest kernels can't work with MMIO windows above 1<<46 3786 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 3787 * 3788 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 3789 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 3790 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 3791 * 1TiB 64-bit MMIO windows for each PHB. 3792 */ 3793 const uint64_t base_buid = 0x800000020000000ULL; 3794 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 3795 SPAPR_PCI_MEM64_WIN_SIZE - 1) 3796 int i; 3797 3798 /* Sanity check natural alignments */ 3799 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3800 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3801 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 3802 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 3803 /* Sanity check bounds */ 3804 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 3805 SPAPR_PCI_MEM32_WIN_SIZE); 3806 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 3807 SPAPR_PCI_MEM64_WIN_SIZE); 3808 3809 if (index >= SPAPR_MAX_PHBS) { 3810 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 3811 SPAPR_MAX_PHBS - 1); 3812 return; 3813 } 3814 3815 *buid = base_buid + index; 3816 for (i = 0; i < n_dma; ++i) { 3817 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3818 } 3819 3820 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 3821 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 3822 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 3823 } 3824 3825 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 3826 { 3827 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3828 3829 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 3830 } 3831 3832 static void spapr_ics_resend(XICSFabric *dev) 3833 { 3834 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3835 3836 ics_resend(spapr->ics); 3837 } 3838 3839 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 3840 { 3841 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 3842 3843 return cpu ? ICP(cpu->intc) : NULL; 3844 } 3845 3846 static void spapr_pic_print_info(InterruptStatsProvider *obj, 3847 Monitor *mon) 3848 { 3849 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3850 3851 spapr->irq->print_info(spapr, mon); 3852 } 3853 3854 int spapr_get_vcpu_id(PowerPCCPU *cpu) 3855 { 3856 return cpu->vcpu_id; 3857 } 3858 3859 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 3860 { 3861 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3862 int vcpu_id; 3863 3864 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 3865 3866 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 3867 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 3868 error_append_hint(errp, "Adjust the number of cpus to %d " 3869 "or try to raise the number of threads per core\n", 3870 vcpu_id * smp_threads / spapr->vsmt); 3871 return; 3872 } 3873 3874 cpu->vcpu_id = vcpu_id; 3875 } 3876 3877 PowerPCCPU *spapr_find_cpu(int vcpu_id) 3878 { 3879 CPUState *cs; 3880 3881 CPU_FOREACH(cs) { 3882 PowerPCCPU *cpu = POWERPC_CPU(cs); 3883 3884 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 3885 return cpu; 3886 } 3887 } 3888 3889 return NULL; 3890 } 3891 3892 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3893 { 3894 MachineClass *mc = MACHINE_CLASS(oc); 3895 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3896 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3897 NMIClass *nc = NMI_CLASS(oc); 3898 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3899 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3900 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3901 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 3902 3903 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3904 mc->ignore_boot_device_suffixes = true; 3905 3906 /* 3907 * We set up the default / latest behaviour here. The class_init 3908 * functions for the specific versioned machine types can override 3909 * these details for backwards compatibility 3910 */ 3911 mc->init = spapr_machine_init; 3912 mc->reset = spapr_machine_reset; 3913 mc->block_default_type = IF_SCSI; 3914 mc->max_cpus = 1024; 3915 mc->no_parallel = 1; 3916 mc->default_boot_order = ""; 3917 mc->default_ram_size = 512 * MiB; 3918 mc->default_display = "std"; 3919 mc->kvm_type = spapr_kvm_type; 3920 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 3921 mc->pci_allow_0_address = true; 3922 assert(!mc->get_hotplug_handler); 3923 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3924 hc->pre_plug = spapr_machine_device_pre_plug; 3925 hc->plug = spapr_machine_device_plug; 3926 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 3927 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 3928 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3929 hc->unplug_request = spapr_machine_device_unplug_request; 3930 hc->unplug = spapr_machine_device_unplug; 3931 3932 smc->dr_lmb_enabled = true; 3933 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 3934 mc->has_hotpluggable_cpus = true; 3935 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 3936 fwc->get_dev_path = spapr_get_fw_dev_path; 3937 nc->nmi_monitor_handler = spapr_nmi; 3938 smc->phb_placement = spapr_phb_placement; 3939 vhc->hypercall = emulate_spapr_hypercall; 3940 vhc->hpt_mask = spapr_hpt_mask; 3941 vhc->map_hptes = spapr_map_hptes; 3942 vhc->unmap_hptes = spapr_unmap_hptes; 3943 vhc->store_hpte = spapr_store_hpte; 3944 vhc->get_patbe = spapr_get_patbe; 3945 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 3946 xic->ics_get = spapr_ics_get; 3947 xic->ics_resend = spapr_ics_resend; 3948 xic->icp_get = spapr_icp_get; 3949 ispc->print_info = spapr_pic_print_info; 3950 /* Force NUMA node memory size to be a multiple of 3951 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 3952 * in which LMBs are represented and hot-added 3953 */ 3954 mc->numa_mem_align_shift = 28; 3955 3956 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 3957 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 3958 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 3959 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 3960 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 3961 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 3962 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 3963 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 3964 spapr_caps_add_properties(smc, &error_abort); 3965 smc->irq = &spapr_irq_xics; 3966 } 3967 3968 static const TypeInfo spapr_machine_info = { 3969 .name = TYPE_SPAPR_MACHINE, 3970 .parent = TYPE_MACHINE, 3971 .abstract = true, 3972 .instance_size = sizeof(sPAPRMachineState), 3973 .instance_init = spapr_instance_init, 3974 .instance_finalize = spapr_machine_finalizefn, 3975 .class_size = sizeof(sPAPRMachineClass), 3976 .class_init = spapr_machine_class_init, 3977 .interfaces = (InterfaceInfo[]) { 3978 { TYPE_FW_PATH_PROVIDER }, 3979 { TYPE_NMI }, 3980 { TYPE_HOTPLUG_HANDLER }, 3981 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 3982 { TYPE_XICS_FABRIC }, 3983 { TYPE_INTERRUPT_STATS_PROVIDER }, 3984 { } 3985 }, 3986 }; 3987 3988 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 3989 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 3990 void *data) \ 3991 { \ 3992 MachineClass *mc = MACHINE_CLASS(oc); \ 3993 spapr_machine_##suffix##_class_options(mc); \ 3994 if (latest) { \ 3995 mc->alias = "pseries"; \ 3996 mc->is_default = 1; \ 3997 } \ 3998 } \ 3999 static const TypeInfo spapr_machine_##suffix##_info = { \ 4000 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4001 .parent = TYPE_SPAPR_MACHINE, \ 4002 .class_init = spapr_machine_##suffix##_class_init, \ 4003 }; \ 4004 static void spapr_machine_register_##suffix(void) \ 4005 { \ 4006 type_register(&spapr_machine_##suffix##_info); \ 4007 } \ 4008 type_init(spapr_machine_register_##suffix) 4009 4010 /* 4011 * pseries-4.0 4012 */ 4013 static void spapr_machine_4_0_class_options(MachineClass *mc) 4014 { 4015 /* Defaults for the latest behaviour inherited from the base class */ 4016 } 4017 4018 DEFINE_SPAPR_MACHINE(4_0, "4.0", true); 4019 4020 /* 4021 * pseries-3.1 4022 */ 4023 static void spapr_machine_3_1_class_options(MachineClass *mc) 4024 { 4025 spapr_machine_4_0_class_options(mc); 4026 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4027 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4028 } 4029 4030 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4031 4032 /* 4033 * pseries-3.0 4034 */ 4035 4036 static void spapr_machine_3_0_class_options(MachineClass *mc) 4037 { 4038 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4039 4040 spapr_machine_3_1_class_options(mc); 4041 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4042 4043 smc->legacy_irq_allocation = true; 4044 smc->irq = &spapr_irq_xics_legacy; 4045 } 4046 4047 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4048 4049 /* 4050 * pseries-2.12 4051 */ 4052 static void spapr_machine_2_12_class_options(MachineClass *mc) 4053 { 4054 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4055 static GlobalProperty compat[] = { 4056 { 4057 .driver = TYPE_POWERPC_CPU, 4058 .property = "pre-3.0-migration", 4059 .value = "on", 4060 }, 4061 { 4062 .driver = TYPE_SPAPR_CPU_CORE, 4063 .property = "pre-3.0-migration", 4064 .value = "on", 4065 }, 4066 }; 4067 4068 spapr_machine_3_0_class_options(mc); 4069 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4070 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4071 4072 /* We depend on kvm_enabled() to choose a default value for the 4073 * hpt-max-page-size capability. Of course we can't do it here 4074 * because this is too early and the HW accelerator isn't initialzed 4075 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4076 */ 4077 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4078 } 4079 4080 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4081 4082 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4083 { 4084 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4085 4086 spapr_machine_2_12_class_options(mc); 4087 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4088 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4089 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4090 } 4091 4092 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4093 4094 /* 4095 * pseries-2.11 4096 */ 4097 4098 static void spapr_machine_2_11_class_options(MachineClass *mc) 4099 { 4100 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4101 4102 spapr_machine_2_12_class_options(mc); 4103 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4104 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4105 } 4106 4107 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4108 4109 /* 4110 * pseries-2.10 4111 */ 4112 4113 static void spapr_machine_2_10_class_options(MachineClass *mc) 4114 { 4115 spapr_machine_2_11_class_options(mc); 4116 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4117 } 4118 4119 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4120 4121 /* 4122 * pseries-2.9 4123 */ 4124 4125 static void spapr_machine_2_9_class_options(MachineClass *mc) 4126 { 4127 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4128 static GlobalProperty compat[] = { 4129 { 4130 .driver = TYPE_POWERPC_CPU, 4131 .property = "pre-2.10-migration", 4132 .value = "on", 4133 }, 4134 }; 4135 4136 spapr_machine_2_10_class_options(mc); 4137 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4138 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4139 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4140 smc->pre_2_10_has_unused_icps = true; 4141 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4142 } 4143 4144 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4145 4146 /* 4147 * pseries-2.8 4148 */ 4149 4150 static void spapr_machine_2_8_class_options(MachineClass *mc) 4151 { 4152 static GlobalProperty compat[] = { 4153 { 4154 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, 4155 .property = "pcie-extended-configuration-space", 4156 .value = "off", 4157 }, 4158 }; 4159 4160 spapr_machine_2_9_class_options(mc); 4161 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4162 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4163 mc->numa_mem_align_shift = 23; 4164 } 4165 4166 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4167 4168 /* 4169 * pseries-2.7 4170 */ 4171 4172 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 4173 uint64_t *buid, hwaddr *pio, 4174 hwaddr *mmio32, hwaddr *mmio64, 4175 unsigned n_dma, uint32_t *liobns, Error **errp) 4176 { 4177 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4178 const uint64_t base_buid = 0x800000020000000ULL; 4179 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4180 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4181 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4182 const uint32_t max_index = 255; 4183 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4184 4185 uint64_t ram_top = MACHINE(spapr)->ram_size; 4186 hwaddr phb0_base, phb_base; 4187 int i; 4188 4189 /* Do we have device memory? */ 4190 if (MACHINE(spapr)->maxram_size > ram_top) { 4191 /* Can't just use maxram_size, because there may be an 4192 * alignment gap between normal and device memory regions 4193 */ 4194 ram_top = MACHINE(spapr)->device_memory->base + 4195 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4196 } 4197 4198 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4199 4200 if (index > max_index) { 4201 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4202 max_index); 4203 return; 4204 } 4205 4206 *buid = base_buid + index; 4207 for (i = 0; i < n_dma; ++i) { 4208 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4209 } 4210 4211 phb_base = phb0_base + index * phb_spacing; 4212 *pio = phb_base + pio_offset; 4213 *mmio32 = phb_base + mmio_offset; 4214 /* 4215 * We don't set the 64-bit MMIO window, relying on the PHB's 4216 * fallback behaviour of automatically splitting a large "32-bit" 4217 * window into contiguous 32-bit and 64-bit windows 4218 */ 4219 } 4220 4221 static void spapr_machine_2_7_class_options(MachineClass *mc) 4222 { 4223 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4224 static GlobalProperty compat[] = { 4225 { 4226 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, 4227 .property = "mem_win_size", 4228 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE), 4229 }, 4230 { 4231 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, 4232 .property = "mem64_win_size", 4233 .value = "0", 4234 }, 4235 { 4236 .driver = TYPE_POWERPC_CPU, 4237 .property = "pre-2.8-migration", 4238 .value = "on", 4239 }, 4240 { 4241 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, 4242 .property = "pre-2.8-migration", 4243 .value = "on", 4244 }, 4245 }; 4246 4247 spapr_machine_2_8_class_options(mc); 4248 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4249 mc->default_machine_opts = "modern-hotplug-events=off"; 4250 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4251 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4252 smc->phb_placement = phb_placement_2_7; 4253 } 4254 4255 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4256 4257 /* 4258 * pseries-2.6 4259 */ 4260 4261 static void spapr_machine_2_6_class_options(MachineClass *mc) 4262 { 4263 static GlobalProperty compat[] = { 4264 { 4265 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, 4266 .property = "ddw", 4267 .value = stringify(off), 4268 }, 4269 }; 4270 4271 spapr_machine_2_7_class_options(mc); 4272 mc->has_hotpluggable_cpus = false; 4273 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4274 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4275 } 4276 4277 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4278 4279 /* 4280 * pseries-2.5 4281 */ 4282 4283 static void spapr_machine_2_5_class_options(MachineClass *mc) 4284 { 4285 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4286 static GlobalProperty compat[] = { 4287 { 4288 .driver = "spapr-vlan", 4289 .property = "use-rx-buffer-pools", 4290 .value = "off", 4291 }, 4292 }; 4293 4294 spapr_machine_2_6_class_options(mc); 4295 smc->use_ohci_by_default = true; 4296 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4297 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4298 } 4299 4300 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4301 4302 /* 4303 * pseries-2.4 4304 */ 4305 4306 static void spapr_machine_2_4_class_options(MachineClass *mc) 4307 { 4308 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4309 4310 spapr_machine_2_5_class_options(mc); 4311 smc->dr_lmb_enabled = false; 4312 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4313 } 4314 4315 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4316 4317 /* 4318 * pseries-2.3 4319 */ 4320 4321 static void spapr_machine_2_3_class_options(MachineClass *mc) 4322 { 4323 static GlobalProperty compat[] = { 4324 { 4325 .driver = "spapr-pci-host-bridge", 4326 .property = "dynamic-reconfiguration", 4327 .value = "off", 4328 }, 4329 }; 4330 spapr_machine_2_4_class_options(mc); 4331 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4332 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4333 } 4334 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4335 4336 /* 4337 * pseries-2.2 4338 */ 4339 4340 static void spapr_machine_2_2_class_options(MachineClass *mc) 4341 { 4342 static GlobalProperty compat[] = { 4343 { 4344 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, 4345 .property = "mem_win_size", 4346 .value = "0x20000000", 4347 }, 4348 }; 4349 4350 spapr_machine_2_3_class_options(mc); 4351 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4352 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4353 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4354 } 4355 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4356 4357 /* 4358 * pseries-2.1 4359 */ 4360 4361 static void spapr_machine_2_1_class_options(MachineClass *mc) 4362 { 4363 spapr_machine_2_2_class_options(mc); 4364 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4365 } 4366 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4367 4368 static void spapr_machine_register_types(void) 4369 { 4370 type_register_static(&spapr_machine_info); 4371 } 4372 4373 type_init(spapr_machine_register_types) 4374