1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qemu/datadir.h" 30 #include "qapi/error.h" 31 #include "qapi/qapi-events-machine.h" 32 #include "qapi/qapi-events-qdev.h" 33 #include "qapi/visitor.h" 34 #include "sysemu/sysemu.h" 35 #include "sysemu/hostmem.h" 36 #include "sysemu/numa.h" 37 #include "sysemu/qtest.h" 38 #include "sysemu/reset.h" 39 #include "sysemu/runstate.h" 40 #include "qemu/log.h" 41 #include "hw/fw-path-provider.h" 42 #include "elf.h" 43 #include "net/net.h" 44 #include "sysemu/device_tree.h" 45 #include "sysemu/cpus.h" 46 #include "sysemu/hw_accel.h" 47 #include "kvm_ppc.h" 48 #include "migration/misc.h" 49 #include "migration/qemu-file-types.h" 50 #include "migration/global_state.h" 51 #include "migration/register.h" 52 #include "migration/blocker.h" 53 #include "mmu-hash64.h" 54 #include "mmu-book3s-v3.h" 55 #include "cpu-models.h" 56 #include "hw/core/cpu.h" 57 58 #include "hw/ppc/ppc.h" 59 #include "hw/loader.h" 60 61 #include "hw/ppc/fdt.h" 62 #include "hw/ppc/spapr.h" 63 #include "hw/ppc/spapr_vio.h" 64 #include "hw/qdev-properties.h" 65 #include "hw/pci-host/spapr.h" 66 #include "hw/pci/msi.h" 67 68 #include "hw/pci/pci.h" 69 #include "hw/scsi/scsi.h" 70 #include "hw/virtio/virtio-scsi.h" 71 #include "hw/virtio/vhost-scsi-common.h" 72 73 #include "exec/ram_addr.h" 74 #include "hw/usb.h" 75 #include "qemu/config-file.h" 76 #include "qemu/error-report.h" 77 #include "trace.h" 78 #include "hw/nmi.h" 79 #include "hw/intc/intc.h" 80 81 #include "hw/ppc/spapr_cpu_core.h" 82 #include "hw/mem/memory-device.h" 83 #include "hw/ppc/spapr_tpm_proxy.h" 84 #include "hw/ppc/spapr_nvdimm.h" 85 #include "hw/ppc/spapr_numa.h" 86 #include "hw/ppc/pef.h" 87 88 #include "monitor/monitor.h" 89 90 #include <libfdt.h> 91 92 /* SLOF memory layout: 93 * 94 * SLOF raw image loaded at 0, copies its romfs right below the flat 95 * device-tree, then position SLOF itself 31M below that 96 * 97 * So we set FW_OVERHEAD to 40MB which should account for all of that 98 * and more 99 * 100 * We load our kernel at 4M, leaving space for SLOF initial image 101 */ 102 #define FDT_MAX_ADDR 0x80000000 /* FDT must stay below that */ 103 #define FW_MAX_SIZE 0x400000 104 #define FW_FILE_NAME "slof.bin" 105 #define FW_FILE_NAME_VOF "vof.bin" 106 #define FW_OVERHEAD 0x2800000 107 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 108 109 #define MIN_RMA_SLOF (128 * MiB) 110 111 #define PHANDLE_INTC 0x00001111 112 113 /* These two functions implement the VCPU id numbering: one to compute them 114 * all and one to identify thread 0 of a VCORE. Any change to the first one 115 * is likely to have an impact on the second one, so let's keep them close. 116 */ 117 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 118 { 119 MachineState *ms = MACHINE(spapr); 120 unsigned int smp_threads = ms->smp.threads; 121 122 assert(spapr->vsmt); 123 return 124 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 125 } 126 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 127 PowerPCCPU *cpu) 128 { 129 assert(spapr->vsmt); 130 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 131 } 132 133 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 134 { 135 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 136 * and newer QEMUs don't even have them. In both cases, we don't want 137 * to send anything on the wire. 138 */ 139 return false; 140 } 141 142 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 143 .name = "icp/server", 144 .version_id = 1, 145 .minimum_version_id = 1, 146 .needed = pre_2_10_vmstate_dummy_icp_needed, 147 .fields = (VMStateField[]) { 148 VMSTATE_UNUSED(4), /* uint32_t xirr */ 149 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 150 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 151 VMSTATE_END_OF_LIST() 152 }, 153 }; 154 155 static void pre_2_10_vmstate_register_dummy_icp(int i) 156 { 157 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 158 (void *)(uintptr_t) i); 159 } 160 161 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 162 { 163 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 164 (void *)(uintptr_t) i); 165 } 166 167 int spapr_max_server_number(SpaprMachineState *spapr) 168 { 169 MachineState *ms = MACHINE(spapr); 170 171 assert(spapr->vsmt); 172 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 173 } 174 175 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 176 int smt_threads) 177 { 178 int i, ret = 0; 179 uint32_t servers_prop[smt_threads]; 180 uint32_t gservers_prop[smt_threads * 2]; 181 int index = spapr_get_vcpu_id(cpu); 182 183 if (cpu->compat_pvr) { 184 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 185 if (ret < 0) { 186 return ret; 187 } 188 } 189 190 /* Build interrupt servers and gservers properties */ 191 for (i = 0; i < smt_threads; i++) { 192 servers_prop[i] = cpu_to_be32(index + i); 193 /* Hack, direct the group queues back to cpu 0 */ 194 gservers_prop[i*2] = cpu_to_be32(index + i); 195 gservers_prop[i*2 + 1] = 0; 196 } 197 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 198 servers_prop, sizeof(servers_prop)); 199 if (ret < 0) { 200 return ret; 201 } 202 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 203 gservers_prop, sizeof(gservers_prop)); 204 205 return ret; 206 } 207 208 static void spapr_dt_pa_features(SpaprMachineState *spapr, 209 PowerPCCPU *cpu, 210 void *fdt, int offset) 211 { 212 uint8_t pa_features_206[] = { 6, 0, 213 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 214 uint8_t pa_features_207[] = { 24, 0, 215 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 216 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 217 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 218 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 219 uint8_t pa_features_300[] = { 66, 0, 220 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 221 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 222 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 223 /* 6: DS207 */ 224 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 225 /* 16: Vector */ 226 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 227 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 228 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 229 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 230 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 231 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 232 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 233 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 235 /* 42: PM, 44: PC RA, 46: SC vec'd */ 236 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 237 /* 48: SIMD, 50: QP BFP, 52: String */ 238 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 239 /* 54: DecFP, 56: DecI, 58: SHA */ 240 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 241 /* 60: NM atomic, 62: RNG */ 242 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 243 }; 244 uint8_t *pa_features = NULL; 245 size_t pa_size; 246 247 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 248 pa_features = pa_features_206; 249 pa_size = sizeof(pa_features_206); 250 } 251 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 252 pa_features = pa_features_207; 253 pa_size = sizeof(pa_features_207); 254 } 255 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 256 pa_features = pa_features_300; 257 pa_size = sizeof(pa_features_300); 258 } 259 if (!pa_features) { 260 return; 261 } 262 263 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 264 /* 265 * Note: we keep CI large pages off by default because a 64K capable 266 * guest provisioned with large pages might otherwise try to map a qemu 267 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 268 * even if that qemu runs on a 4k host. 269 * We dd this bit back here if we are confident this is not an issue 270 */ 271 pa_features[3] |= 0x20; 272 } 273 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 274 pa_features[24] |= 0x80; /* Transactional memory support */ 275 } 276 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 277 /* Workaround for broken kernels that attempt (guest) radix 278 * mode when they can't handle it, if they see the radix bit set 279 * in pa-features. So hide it from them. */ 280 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 281 } 282 283 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 284 } 285 286 static hwaddr spapr_node0_size(MachineState *machine) 287 { 288 if (machine->numa_state->num_nodes) { 289 int i; 290 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 291 if (machine->numa_state->nodes[i].node_mem) { 292 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 293 machine->ram_size); 294 } 295 } 296 } 297 return machine->ram_size; 298 } 299 300 static void add_str(GString *s, const gchar *s1) 301 { 302 g_string_append_len(s, s1, strlen(s1) + 1); 303 } 304 305 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 306 hwaddr start, hwaddr size) 307 { 308 char mem_name[32]; 309 uint64_t mem_reg_property[2]; 310 int off; 311 312 mem_reg_property[0] = cpu_to_be64(start); 313 mem_reg_property[1] = cpu_to_be64(size); 314 315 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 316 off = fdt_add_subnode(fdt, 0, mem_name); 317 _FDT(off); 318 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 319 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 320 sizeof(mem_reg_property)))); 321 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 322 return off; 323 } 324 325 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 326 { 327 MemoryDeviceInfoList *info; 328 329 for (info = list; info; info = info->next) { 330 MemoryDeviceInfo *value = info->value; 331 332 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 333 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 334 335 if (addr >= pcdimm_info->addr && 336 addr < (pcdimm_info->addr + pcdimm_info->size)) { 337 return pcdimm_info->node; 338 } 339 } 340 } 341 342 return -1; 343 } 344 345 struct sPAPRDrconfCellV2 { 346 uint32_t seq_lmbs; 347 uint64_t base_addr; 348 uint32_t drc_index; 349 uint32_t aa_index; 350 uint32_t flags; 351 } QEMU_PACKED; 352 353 typedef struct DrconfCellQueue { 354 struct sPAPRDrconfCellV2 cell; 355 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 356 } DrconfCellQueue; 357 358 static DrconfCellQueue * 359 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 360 uint32_t drc_index, uint32_t aa_index, 361 uint32_t flags) 362 { 363 DrconfCellQueue *elem; 364 365 elem = g_malloc0(sizeof(*elem)); 366 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 367 elem->cell.base_addr = cpu_to_be64(base_addr); 368 elem->cell.drc_index = cpu_to_be32(drc_index); 369 elem->cell.aa_index = cpu_to_be32(aa_index); 370 elem->cell.flags = cpu_to_be32(flags); 371 372 return elem; 373 } 374 375 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 376 int offset, MemoryDeviceInfoList *dimms) 377 { 378 MachineState *machine = MACHINE(spapr); 379 uint8_t *int_buf, *cur_index; 380 int ret; 381 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 382 uint64_t addr, cur_addr, size; 383 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 384 uint64_t mem_end = machine->device_memory->base + 385 memory_region_size(&machine->device_memory->mr); 386 uint32_t node, buf_len, nr_entries = 0; 387 SpaprDrc *drc; 388 DrconfCellQueue *elem, *next; 389 MemoryDeviceInfoList *info; 390 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 391 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 392 393 /* Entry to cover RAM and the gap area */ 394 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 395 SPAPR_LMB_FLAGS_RESERVED | 396 SPAPR_LMB_FLAGS_DRC_INVALID); 397 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 398 nr_entries++; 399 400 cur_addr = machine->device_memory->base; 401 for (info = dimms; info; info = info->next) { 402 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 403 404 addr = di->addr; 405 size = di->size; 406 node = di->node; 407 408 /* 409 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 410 * area is marked hotpluggable in the next iteration for the bigger 411 * chunk including the NVDIMM occupied area. 412 */ 413 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 414 continue; 415 416 /* Entry for hot-pluggable area */ 417 if (cur_addr < addr) { 418 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 419 g_assert(drc); 420 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 421 cur_addr, spapr_drc_index(drc), -1, 0); 422 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 423 nr_entries++; 424 } 425 426 /* Entry for DIMM */ 427 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 428 g_assert(drc); 429 elem = spapr_get_drconf_cell(size / lmb_size, addr, 430 spapr_drc_index(drc), node, 431 (SPAPR_LMB_FLAGS_ASSIGNED | 432 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 433 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 434 nr_entries++; 435 cur_addr = addr + size; 436 } 437 438 /* Entry for remaining hotpluggable area */ 439 if (cur_addr < mem_end) { 440 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 441 g_assert(drc); 442 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 443 cur_addr, spapr_drc_index(drc), -1, 0); 444 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 445 nr_entries++; 446 } 447 448 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 449 int_buf = cur_index = g_malloc0(buf_len); 450 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 451 cur_index += sizeof(nr_entries); 452 453 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 454 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 455 cur_index += sizeof(elem->cell); 456 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 457 g_free(elem); 458 } 459 460 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 461 g_free(int_buf); 462 if (ret < 0) { 463 return -1; 464 } 465 return 0; 466 } 467 468 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 469 int offset, MemoryDeviceInfoList *dimms) 470 { 471 MachineState *machine = MACHINE(spapr); 472 int i, ret; 473 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 474 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 475 uint32_t nr_lmbs = (machine->device_memory->base + 476 memory_region_size(&machine->device_memory->mr)) / 477 lmb_size; 478 uint32_t *int_buf, *cur_index, buf_len; 479 480 /* 481 * Allocate enough buffer size to fit in ibm,dynamic-memory 482 */ 483 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 484 cur_index = int_buf = g_malloc0(buf_len); 485 int_buf[0] = cpu_to_be32(nr_lmbs); 486 cur_index++; 487 for (i = 0; i < nr_lmbs; i++) { 488 uint64_t addr = i * lmb_size; 489 uint32_t *dynamic_memory = cur_index; 490 491 if (i >= device_lmb_start) { 492 SpaprDrc *drc; 493 494 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 495 g_assert(drc); 496 497 dynamic_memory[0] = cpu_to_be32(addr >> 32); 498 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 499 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 500 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 501 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 502 if (memory_region_present(get_system_memory(), addr)) { 503 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 504 } else { 505 dynamic_memory[5] = cpu_to_be32(0); 506 } 507 } else { 508 /* 509 * LMB information for RMA, boot time RAM and gap b/n RAM and 510 * device memory region -- all these are marked as reserved 511 * and as having no valid DRC. 512 */ 513 dynamic_memory[0] = cpu_to_be32(addr >> 32); 514 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 515 dynamic_memory[2] = cpu_to_be32(0); 516 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 517 dynamic_memory[4] = cpu_to_be32(-1); 518 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 519 SPAPR_LMB_FLAGS_DRC_INVALID); 520 } 521 522 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 523 } 524 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 525 g_free(int_buf); 526 if (ret < 0) { 527 return -1; 528 } 529 return 0; 530 } 531 532 /* 533 * Adds ibm,dynamic-reconfiguration-memory node. 534 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 535 * of this device tree node. 536 */ 537 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 538 void *fdt) 539 { 540 MachineState *machine = MACHINE(spapr); 541 int ret, offset; 542 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 543 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 544 cpu_to_be32(lmb_size & 0xffffffff)}; 545 MemoryDeviceInfoList *dimms = NULL; 546 547 /* 548 * Don't create the node if there is no device memory 549 */ 550 if (machine->ram_size == machine->maxram_size) { 551 return 0; 552 } 553 554 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 555 556 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 557 sizeof(prop_lmb_size)); 558 if (ret < 0) { 559 return ret; 560 } 561 562 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 563 if (ret < 0) { 564 return ret; 565 } 566 567 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 568 if (ret < 0) { 569 return ret; 570 } 571 572 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 573 dimms = qmp_memory_device_list(); 574 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 575 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 576 } else { 577 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 578 } 579 qapi_free_MemoryDeviceInfoList(dimms); 580 581 if (ret < 0) { 582 return ret; 583 } 584 585 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 586 587 return ret; 588 } 589 590 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 591 { 592 MachineState *machine = MACHINE(spapr); 593 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 594 hwaddr mem_start, node_size; 595 int i, nb_nodes = machine->numa_state->num_nodes; 596 NodeInfo *nodes = machine->numa_state->nodes; 597 598 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 599 if (!nodes[i].node_mem) { 600 continue; 601 } 602 if (mem_start >= machine->ram_size) { 603 node_size = 0; 604 } else { 605 node_size = nodes[i].node_mem; 606 if (node_size > machine->ram_size - mem_start) { 607 node_size = machine->ram_size - mem_start; 608 } 609 } 610 if (!mem_start) { 611 /* spapr_machine_init() checks for rma_size <= node0_size 612 * already */ 613 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 614 mem_start += spapr->rma_size; 615 node_size -= spapr->rma_size; 616 } 617 for ( ; node_size; ) { 618 hwaddr sizetmp = pow2floor(node_size); 619 620 /* mem_start != 0 here */ 621 if (ctzl(mem_start) < ctzl(sizetmp)) { 622 sizetmp = 1ULL << ctzl(mem_start); 623 } 624 625 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 626 node_size -= sizetmp; 627 mem_start += sizetmp; 628 } 629 } 630 631 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 632 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 633 int ret; 634 635 g_assert(smc->dr_lmb_enabled); 636 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 637 if (ret) { 638 return ret; 639 } 640 } 641 642 return 0; 643 } 644 645 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 646 SpaprMachineState *spapr) 647 { 648 MachineState *ms = MACHINE(spapr); 649 PowerPCCPU *cpu = POWERPC_CPU(cs); 650 CPUPPCState *env = &cpu->env; 651 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 652 int index = spapr_get_vcpu_id(cpu); 653 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 654 0xffffffff, 0xffffffff}; 655 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 656 : SPAPR_TIMEBASE_FREQ; 657 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 658 uint32_t page_sizes_prop[64]; 659 size_t page_sizes_prop_size; 660 unsigned int smp_threads = ms->smp.threads; 661 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 662 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 663 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 664 SpaprDrc *drc; 665 int drc_index; 666 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 667 int i; 668 669 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 670 if (drc) { 671 drc_index = spapr_drc_index(drc); 672 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 673 } 674 675 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 676 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 677 678 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 679 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 680 env->dcache_line_size))); 681 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 682 env->dcache_line_size))); 683 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 684 env->icache_line_size))); 685 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 686 env->icache_line_size))); 687 688 if (pcc->l1_dcache_size) { 689 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 690 pcc->l1_dcache_size))); 691 } else { 692 warn_report("Unknown L1 dcache size for cpu"); 693 } 694 if (pcc->l1_icache_size) { 695 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 696 pcc->l1_icache_size))); 697 } else { 698 warn_report("Unknown L1 icache size for cpu"); 699 } 700 701 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 702 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 703 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 704 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 705 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 706 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 707 708 if (ppc_has_spr(cpu, SPR_PURR)) { 709 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 710 } 711 if (ppc_has_spr(cpu, SPR_PURR)) { 712 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 713 } 714 715 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 716 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 717 segs, sizeof(segs)))); 718 } 719 720 /* Advertise VSX (vector extensions) if available 721 * 1 == VMX / Altivec available 722 * 2 == VSX available 723 * 724 * Only CPUs for which we create core types in spapr_cpu_core.c 725 * are possible, and all of those have VMX */ 726 if (env->insns_flags & PPC_ALTIVEC) { 727 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 728 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 729 } else { 730 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 731 } 732 } 733 734 /* Advertise DFP (Decimal Floating Point) if available 735 * 0 / no property == no DFP 736 * 1 == DFP available */ 737 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 738 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 739 } 740 741 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 742 sizeof(page_sizes_prop)); 743 if (page_sizes_prop_size) { 744 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 745 page_sizes_prop, page_sizes_prop_size))); 746 } 747 748 spapr_dt_pa_features(spapr, cpu, fdt, offset); 749 750 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 751 cs->cpu_index / vcpus_per_socket))); 752 753 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 754 pft_size_prop, sizeof(pft_size_prop)))); 755 756 if (ms->numa_state->num_nodes > 1) { 757 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 758 } 759 760 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 761 762 if (pcc->radix_page_info) { 763 for (i = 0; i < pcc->radix_page_info->count; i++) { 764 radix_AP_encodings[i] = 765 cpu_to_be32(pcc->radix_page_info->entries[i]); 766 } 767 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 768 radix_AP_encodings, 769 pcc->radix_page_info->count * 770 sizeof(radix_AP_encodings[0])))); 771 } 772 773 /* 774 * We set this property to let the guest know that it can use the large 775 * decrementer and its width in bits. 776 */ 777 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 778 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 779 pcc->lrg_decr_bits))); 780 } 781 782 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 783 { 784 CPUState **rev; 785 CPUState *cs; 786 int n_cpus; 787 int cpus_offset; 788 int i; 789 790 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 791 _FDT(cpus_offset); 792 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 793 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 794 795 /* 796 * We walk the CPUs in reverse order to ensure that CPU DT nodes 797 * created by fdt_add_subnode() end up in the right order in FDT 798 * for the guest kernel the enumerate the CPUs correctly. 799 * 800 * The CPU list cannot be traversed in reverse order, so we need 801 * to do extra work. 802 */ 803 n_cpus = 0; 804 rev = NULL; 805 CPU_FOREACH(cs) { 806 rev = g_renew(CPUState *, rev, n_cpus + 1); 807 rev[n_cpus++] = cs; 808 } 809 810 for (i = n_cpus - 1; i >= 0; i--) { 811 CPUState *cs = rev[i]; 812 PowerPCCPU *cpu = POWERPC_CPU(cs); 813 int index = spapr_get_vcpu_id(cpu); 814 DeviceClass *dc = DEVICE_GET_CLASS(cs); 815 g_autofree char *nodename = NULL; 816 int offset; 817 818 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 819 continue; 820 } 821 822 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 823 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 824 _FDT(offset); 825 spapr_dt_cpu(cs, fdt, offset, spapr); 826 } 827 828 g_free(rev); 829 } 830 831 static int spapr_dt_rng(void *fdt) 832 { 833 int node; 834 int ret; 835 836 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 837 if (node <= 0) { 838 return -1; 839 } 840 ret = fdt_setprop_string(fdt, node, "device_type", 841 "ibm,platform-facilities"); 842 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 843 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 844 845 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 846 if (node <= 0) { 847 return -1; 848 } 849 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 850 851 return ret ? -1 : 0; 852 } 853 854 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 855 { 856 MachineState *ms = MACHINE(spapr); 857 int rtas; 858 GString *hypertas = g_string_sized_new(256); 859 GString *qemu_hypertas = g_string_sized_new(256); 860 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 861 memory_region_size(&MACHINE(spapr)->device_memory->mr); 862 uint32_t lrdr_capacity[] = { 863 cpu_to_be32(max_device_addr >> 32), 864 cpu_to_be32(max_device_addr & 0xffffffff), 865 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 866 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 867 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 868 }; 869 870 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 871 872 /* hypertas */ 873 add_str(hypertas, "hcall-pft"); 874 add_str(hypertas, "hcall-term"); 875 add_str(hypertas, "hcall-dabr"); 876 add_str(hypertas, "hcall-interrupt"); 877 add_str(hypertas, "hcall-tce"); 878 add_str(hypertas, "hcall-vio"); 879 add_str(hypertas, "hcall-splpar"); 880 add_str(hypertas, "hcall-join"); 881 add_str(hypertas, "hcall-bulk"); 882 add_str(hypertas, "hcall-set-mode"); 883 add_str(hypertas, "hcall-sprg0"); 884 add_str(hypertas, "hcall-copy"); 885 add_str(hypertas, "hcall-debug"); 886 add_str(hypertas, "hcall-vphn"); 887 if (spapr_get_cap(spapr, SPAPR_CAP_RPT_INVALIDATE) == SPAPR_CAP_ON) { 888 add_str(hypertas, "hcall-rpt-invalidate"); 889 } 890 891 add_str(qemu_hypertas, "hcall-memop1"); 892 893 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 894 add_str(hypertas, "hcall-multi-tce"); 895 } 896 897 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 898 add_str(hypertas, "hcall-hpt-resize"); 899 } 900 901 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 902 hypertas->str, hypertas->len)); 903 g_string_free(hypertas, TRUE); 904 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 905 qemu_hypertas->str, qemu_hypertas->len)); 906 g_string_free(qemu_hypertas, TRUE); 907 908 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 909 910 /* 911 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 912 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 913 * 914 * The system reset requirements are driven by existing Linux and PowerVM 915 * implementation which (contrary to PAPR) saves r3 in the error log 916 * structure like machine check, so Linux expects to find the saved r3 917 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 918 * does not look at the error value). 919 * 920 * System reset interrupts are not subject to interlock like machine 921 * check, so this memory area could be corrupted if the sreset is 922 * interrupted by a machine check (or vice versa) if it was shared. To 923 * prevent this, system reset uses per-CPU areas for the sreset save 924 * area. A system reset that interrupts a system reset handler could 925 * still overwrite this area, but Linux doesn't try to recover in that 926 * case anyway. 927 * 928 * The extra 8 bytes is required because Linux's FWNMI error log check 929 * is off-by-one. 930 * 931 * RTAS_MIN_SIZE is required for the RTAS blob itself. 932 */ 933 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_MIN_SIZE + 934 RTAS_ERROR_LOG_MAX + 935 ms->smp.max_cpus * sizeof(uint64_t) * 2 + 936 sizeof(uint64_t))); 937 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 938 RTAS_ERROR_LOG_MAX)); 939 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 940 RTAS_EVENT_SCAN_RATE)); 941 942 g_assert(msi_nonbroken); 943 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 944 945 /* 946 * According to PAPR, rtas ibm,os-term does not guarantee a return 947 * back to the guest cpu. 948 * 949 * While an additional ibm,extended-os-term property indicates 950 * that rtas call return will always occur. Set this property. 951 */ 952 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 953 954 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 955 lrdr_capacity, sizeof(lrdr_capacity))); 956 957 spapr_dt_rtas_tokens(fdt, rtas); 958 } 959 960 /* 961 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 962 * and the XIVE features that the guest may request and thus the valid 963 * values for bytes 23..26 of option vector 5: 964 */ 965 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 966 int chosen) 967 { 968 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 969 970 char val[2 * 4] = { 971 23, 0x00, /* XICS / XIVE mode */ 972 24, 0x00, /* Hash/Radix, filled in below. */ 973 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 974 26, 0x40, /* Radix options: GTSE == yes. */ 975 }; 976 977 if (spapr->irq->xics && spapr->irq->xive) { 978 val[1] = SPAPR_OV5_XIVE_BOTH; 979 } else if (spapr->irq->xive) { 980 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 981 } else { 982 assert(spapr->irq->xics); 983 val[1] = SPAPR_OV5_XIVE_LEGACY; 984 } 985 986 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 987 first_ppc_cpu->compat_pvr)) { 988 /* 989 * If we're in a pre POWER9 compat mode then the guest should 990 * do hash and use the legacy interrupt mode 991 */ 992 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 993 val[3] = 0x00; /* Hash */ 994 spapr_check_mmu_mode(false); 995 } else if (kvm_enabled()) { 996 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 997 val[3] = 0x80; /* OV5_MMU_BOTH */ 998 } else if (kvmppc_has_cap_mmu_radix()) { 999 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1000 } else { 1001 val[3] = 0x00; /* Hash */ 1002 } 1003 } else { 1004 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1005 val[3] = 0xC0; 1006 } 1007 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1008 val, sizeof(val))); 1009 } 1010 1011 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1012 { 1013 MachineState *machine = MACHINE(spapr); 1014 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1015 int chosen; 1016 1017 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1018 1019 if (reset) { 1020 const char *boot_device = spapr->boot_device; 1021 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1022 size_t cb = 0; 1023 char *bootlist = get_boot_devices_list(&cb); 1024 1025 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1026 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1027 machine->kernel_cmdline)); 1028 } 1029 1030 if (spapr->initrd_size) { 1031 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1032 spapr->initrd_base)); 1033 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1034 spapr->initrd_base + spapr->initrd_size)); 1035 } 1036 1037 if (spapr->kernel_size) { 1038 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1039 cpu_to_be64(spapr->kernel_size) }; 1040 1041 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1042 &kprop, sizeof(kprop))); 1043 if (spapr->kernel_le) { 1044 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1045 } 1046 } 1047 if (boot_menu) { 1048 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1049 } 1050 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1051 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1052 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1053 1054 if (cb && bootlist) { 1055 int i; 1056 1057 for (i = 0; i < cb; i++) { 1058 if (bootlist[i] == '\n') { 1059 bootlist[i] = ' '; 1060 } 1061 } 1062 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1063 } 1064 1065 if (boot_device && strlen(boot_device)) { 1066 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1067 } 1068 1069 if (!spapr->has_graphics && stdout_path) { 1070 /* 1071 * "linux,stdout-path" and "stdout" properties are 1072 * deprecated by linux kernel. New platforms should only 1073 * use the "stdout-path" property. Set the new property 1074 * and continue using older property to remain compatible 1075 * with the existing firmware. 1076 */ 1077 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1078 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1079 } 1080 1081 /* 1082 * We can deal with BAR reallocation just fine, advertise it 1083 * to the guest 1084 */ 1085 if (smc->linux_pci_probe) { 1086 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1087 } 1088 1089 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1090 1091 g_free(stdout_path); 1092 g_free(bootlist); 1093 } 1094 1095 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1096 } 1097 1098 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1099 { 1100 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1101 * KVM to work under pHyp with some guest co-operation */ 1102 int hypervisor; 1103 uint8_t hypercall[16]; 1104 1105 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1106 /* indicate KVM hypercall interface */ 1107 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1108 if (kvmppc_has_cap_fixup_hcalls()) { 1109 /* 1110 * Older KVM versions with older guest kernels were broken 1111 * with the magic page, don't allow the guest to map it. 1112 */ 1113 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1114 sizeof(hypercall))) { 1115 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1116 hypercall, sizeof(hypercall))); 1117 } 1118 } 1119 } 1120 1121 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1122 { 1123 MachineState *machine = MACHINE(spapr); 1124 MachineClass *mc = MACHINE_GET_CLASS(machine); 1125 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1126 uint32_t root_drc_type_mask = 0; 1127 int ret; 1128 void *fdt; 1129 SpaprPhbState *phb; 1130 char *buf; 1131 1132 fdt = g_malloc0(space); 1133 _FDT((fdt_create_empty_tree(fdt, space))); 1134 1135 /* Root node */ 1136 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1137 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1138 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1139 1140 /* Guest UUID & Name*/ 1141 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1142 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1143 if (qemu_uuid_set) { 1144 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1145 } 1146 g_free(buf); 1147 1148 if (qemu_get_vm_name()) { 1149 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1150 qemu_get_vm_name())); 1151 } 1152 1153 /* Host Model & Serial Number */ 1154 if (spapr->host_model) { 1155 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1156 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1157 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1158 g_free(buf); 1159 } 1160 1161 if (spapr->host_serial) { 1162 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1163 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1164 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1165 g_free(buf); 1166 } 1167 1168 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1169 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1170 1171 /* /interrupt controller */ 1172 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1173 1174 ret = spapr_dt_memory(spapr, fdt); 1175 if (ret < 0) { 1176 error_report("couldn't setup memory nodes in fdt"); 1177 exit(1); 1178 } 1179 1180 /* /vdevice */ 1181 spapr_dt_vdevice(spapr->vio_bus, fdt); 1182 1183 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1184 ret = spapr_dt_rng(fdt); 1185 if (ret < 0) { 1186 error_report("could not set up rng device in the fdt"); 1187 exit(1); 1188 } 1189 } 1190 1191 QLIST_FOREACH(phb, &spapr->phbs, list) { 1192 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1193 if (ret < 0) { 1194 error_report("couldn't setup PCI devices in fdt"); 1195 exit(1); 1196 } 1197 } 1198 1199 spapr_dt_cpus(fdt, spapr); 1200 1201 /* ibm,drc-indexes and friends */ 1202 if (smc->dr_lmb_enabled) { 1203 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; 1204 } 1205 if (smc->dr_phb_enabled) { 1206 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; 1207 } 1208 if (mc->nvdimm_supported) { 1209 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM; 1210 } 1211 if (root_drc_type_mask) { 1212 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask)); 1213 } 1214 1215 if (mc->has_hotpluggable_cpus) { 1216 int offset = fdt_path_offset(fdt, "/cpus"); 1217 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1218 if (ret < 0) { 1219 error_report("Couldn't set up CPU DR device tree properties"); 1220 exit(1); 1221 } 1222 } 1223 1224 /* /event-sources */ 1225 spapr_dt_events(spapr, fdt); 1226 1227 /* /rtas */ 1228 spapr_dt_rtas(spapr, fdt); 1229 1230 /* /chosen */ 1231 spapr_dt_chosen(spapr, fdt, reset); 1232 1233 /* /hypervisor */ 1234 if (kvm_enabled()) { 1235 spapr_dt_hypervisor(spapr, fdt); 1236 } 1237 1238 /* Build memory reserve map */ 1239 if (reset) { 1240 if (spapr->kernel_size) { 1241 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1242 spapr->kernel_size))); 1243 } 1244 if (spapr->initrd_size) { 1245 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1246 spapr->initrd_size))); 1247 } 1248 } 1249 1250 /* NVDIMM devices */ 1251 if (mc->nvdimm_supported) { 1252 spapr_dt_persistent_memory(spapr, fdt); 1253 } 1254 1255 return fdt; 1256 } 1257 1258 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1259 { 1260 SpaprMachineState *spapr = opaque; 1261 1262 return (addr & 0x0fffffff) + spapr->kernel_addr; 1263 } 1264 1265 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1266 PowerPCCPU *cpu) 1267 { 1268 CPUPPCState *env = &cpu->env; 1269 1270 /* The TCG path should also be holding the BQL at this point */ 1271 g_assert(qemu_mutex_iothread_locked()); 1272 1273 g_assert(!vhyp_cpu_in_nested(cpu)); 1274 1275 if (msr_pr) { 1276 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1277 env->gpr[3] = H_PRIVILEGE; 1278 } else { 1279 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1280 } 1281 } 1282 1283 struct LPCRSyncState { 1284 target_ulong value; 1285 target_ulong mask; 1286 }; 1287 1288 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1289 { 1290 struct LPCRSyncState *s = arg.host_ptr; 1291 PowerPCCPU *cpu = POWERPC_CPU(cs); 1292 CPUPPCState *env = &cpu->env; 1293 target_ulong lpcr; 1294 1295 cpu_synchronize_state(cs); 1296 lpcr = env->spr[SPR_LPCR]; 1297 lpcr &= ~s->mask; 1298 lpcr |= s->value; 1299 ppc_store_lpcr(cpu, lpcr); 1300 } 1301 1302 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1303 { 1304 CPUState *cs; 1305 struct LPCRSyncState s = { 1306 .value = value, 1307 .mask = mask 1308 }; 1309 CPU_FOREACH(cs) { 1310 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1311 } 1312 } 1313 1314 static bool spapr_get_pate(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu, 1315 target_ulong lpid, ppc_v3_pate_t *entry) 1316 { 1317 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1318 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 1319 1320 if (!spapr_cpu->in_nested) { 1321 assert(lpid == 0); 1322 1323 /* Copy PATE1:GR into PATE0:HR */ 1324 entry->dw0 = spapr->patb_entry & PATE0_HR; 1325 entry->dw1 = spapr->patb_entry; 1326 1327 } else { 1328 uint64_t patb, pats; 1329 1330 assert(lpid != 0); 1331 1332 patb = spapr->nested_ptcr & PTCR_PATB; 1333 pats = spapr->nested_ptcr & PTCR_PATS; 1334 1335 /* Calculate number of entries */ 1336 pats = 1ull << (pats + 12 - 4); 1337 if (pats <= lpid) { 1338 return false; 1339 } 1340 1341 /* Grab entry */ 1342 patb += 16 * lpid; 1343 entry->dw0 = ldq_phys(CPU(cpu)->as, patb); 1344 entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8); 1345 } 1346 1347 return true; 1348 } 1349 1350 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1351 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1352 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1353 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1354 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1355 1356 /* 1357 * Get the fd to access the kernel htab, re-opening it if necessary 1358 */ 1359 static int get_htab_fd(SpaprMachineState *spapr) 1360 { 1361 Error *local_err = NULL; 1362 1363 if (spapr->htab_fd >= 0) { 1364 return spapr->htab_fd; 1365 } 1366 1367 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1368 if (spapr->htab_fd < 0) { 1369 error_report_err(local_err); 1370 } 1371 1372 return spapr->htab_fd; 1373 } 1374 1375 void close_htab_fd(SpaprMachineState *spapr) 1376 { 1377 if (spapr->htab_fd >= 0) { 1378 close(spapr->htab_fd); 1379 } 1380 spapr->htab_fd = -1; 1381 } 1382 1383 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1384 { 1385 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1386 1387 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1388 } 1389 1390 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1391 { 1392 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1393 1394 assert(kvm_enabled()); 1395 1396 if (!spapr->htab) { 1397 return 0; 1398 } 1399 1400 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1401 } 1402 1403 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1404 hwaddr ptex, int n) 1405 { 1406 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1407 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1408 1409 if (!spapr->htab) { 1410 /* 1411 * HTAB is controlled by KVM. Fetch into temporary buffer 1412 */ 1413 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1414 kvmppc_read_hptes(hptes, ptex, n); 1415 return hptes; 1416 } 1417 1418 /* 1419 * HTAB is controlled by QEMU. Just point to the internally 1420 * accessible PTEG. 1421 */ 1422 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1423 } 1424 1425 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1426 const ppc_hash_pte64_t *hptes, 1427 hwaddr ptex, int n) 1428 { 1429 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1430 1431 if (!spapr->htab) { 1432 g_free((void *)hptes); 1433 } 1434 1435 /* Nothing to do for qemu managed HPT */ 1436 } 1437 1438 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1439 uint64_t pte0, uint64_t pte1) 1440 { 1441 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1442 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1443 1444 if (!spapr->htab) { 1445 kvmppc_write_hpte(ptex, pte0, pte1); 1446 } else { 1447 if (pte0 & HPTE64_V_VALID) { 1448 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1449 /* 1450 * When setting valid, we write PTE1 first. This ensures 1451 * proper synchronization with the reading code in 1452 * ppc_hash64_pteg_search() 1453 */ 1454 smp_wmb(); 1455 stq_p(spapr->htab + offset, pte0); 1456 } else { 1457 stq_p(spapr->htab + offset, pte0); 1458 /* 1459 * When clearing it we set PTE0 first. This ensures proper 1460 * synchronization with the reading code in 1461 * ppc_hash64_pteg_search() 1462 */ 1463 smp_wmb(); 1464 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1465 } 1466 } 1467 } 1468 1469 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1470 uint64_t pte1) 1471 { 1472 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_C; 1473 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1474 1475 if (!spapr->htab) { 1476 /* There should always be a hash table when this is called */ 1477 error_report("spapr_hpte_set_c called with no hash table !"); 1478 return; 1479 } 1480 1481 /* The HW performs a non-atomic byte update */ 1482 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1483 } 1484 1485 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1486 uint64_t pte1) 1487 { 1488 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_R; 1489 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1490 1491 if (!spapr->htab) { 1492 /* There should always be a hash table when this is called */ 1493 error_report("spapr_hpte_set_r called with no hash table !"); 1494 return; 1495 } 1496 1497 /* The HW performs a non-atomic byte update */ 1498 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1499 } 1500 1501 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1502 { 1503 int shift; 1504 1505 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1506 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1507 * that's much more than is needed for Linux guests */ 1508 shift = ctz64(pow2ceil(ramsize)) - 7; 1509 shift = MAX(shift, 18); /* Minimum architected size */ 1510 shift = MIN(shift, 46); /* Maximum architected size */ 1511 return shift; 1512 } 1513 1514 void spapr_free_hpt(SpaprMachineState *spapr) 1515 { 1516 g_free(spapr->htab); 1517 spapr->htab = NULL; 1518 spapr->htab_shift = 0; 1519 close_htab_fd(spapr); 1520 } 1521 1522 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1523 { 1524 ERRP_GUARD(); 1525 long rc; 1526 1527 /* Clean up any HPT info from a previous boot */ 1528 spapr_free_hpt(spapr); 1529 1530 rc = kvmppc_reset_htab(shift); 1531 1532 if (rc == -EOPNOTSUPP) { 1533 error_setg(errp, "HPT not supported in nested guests"); 1534 return -EOPNOTSUPP; 1535 } 1536 1537 if (rc < 0) { 1538 /* kernel-side HPT needed, but couldn't allocate one */ 1539 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1540 shift); 1541 error_append_hint(errp, "Try smaller maxmem?\n"); 1542 return -errno; 1543 } else if (rc > 0) { 1544 /* kernel-side HPT allocated */ 1545 if (rc != shift) { 1546 error_setg(errp, 1547 "Requested order %d HPT, but kernel allocated order %ld", 1548 shift, rc); 1549 error_append_hint(errp, "Try smaller maxmem?\n"); 1550 return -ENOSPC; 1551 } 1552 1553 spapr->htab_shift = shift; 1554 spapr->htab = NULL; 1555 } else { 1556 /* kernel-side HPT not needed, allocate in userspace instead */ 1557 size_t size = 1ULL << shift; 1558 int i; 1559 1560 spapr->htab = qemu_memalign(size, size); 1561 memset(spapr->htab, 0, size); 1562 spapr->htab_shift = shift; 1563 1564 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1565 DIRTY_HPTE(HPTE(spapr->htab, i)); 1566 } 1567 } 1568 /* We're setting up a hash table, so that means we're not radix */ 1569 spapr->patb_entry = 0; 1570 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1571 return 0; 1572 } 1573 1574 void spapr_setup_hpt(SpaprMachineState *spapr) 1575 { 1576 int hpt_shift; 1577 1578 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1579 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1580 } else { 1581 uint64_t current_ram_size; 1582 1583 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1584 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1585 } 1586 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1587 1588 if (kvm_enabled()) { 1589 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1590 1591 /* Check our RMA fits in the possible VRMA */ 1592 if (vrma_limit < spapr->rma_size) { 1593 error_report("Unable to create %" HWADDR_PRIu 1594 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1595 spapr->rma_size / MiB, vrma_limit / MiB); 1596 exit(EXIT_FAILURE); 1597 } 1598 } 1599 } 1600 1601 void spapr_check_mmu_mode(bool guest_radix) 1602 { 1603 if (guest_radix) { 1604 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 1605 error_report("Guest requested unavailable MMU mode (radix)."); 1606 exit(EXIT_FAILURE); 1607 } 1608 } else { 1609 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 1610 && !kvmppc_has_cap_mmu_hash_v3()) { 1611 error_report("Guest requested unavailable MMU mode (hash)."); 1612 exit(EXIT_FAILURE); 1613 } 1614 } 1615 } 1616 1617 static void spapr_machine_reset(MachineState *machine) 1618 { 1619 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1620 PowerPCCPU *first_ppc_cpu; 1621 hwaddr fdt_addr; 1622 void *fdt; 1623 int rc; 1624 1625 pef_kvm_reset(machine->cgs, &error_fatal); 1626 spapr_caps_apply(spapr); 1627 1628 first_ppc_cpu = POWERPC_CPU(first_cpu); 1629 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1630 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1631 spapr->max_compat_pvr)) { 1632 /* 1633 * If using KVM with radix mode available, VCPUs can be started 1634 * without a HPT because KVM will start them in radix mode. 1635 * Set the GR bit in PATE so that we know there is no HPT. 1636 */ 1637 spapr->patb_entry = PATE1_GR; 1638 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1639 } else { 1640 spapr_setup_hpt(spapr); 1641 } 1642 1643 qemu_devices_reset(); 1644 1645 spapr_ovec_cleanup(spapr->ov5_cas); 1646 spapr->ov5_cas = spapr_ovec_new(); 1647 1648 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1649 1650 /* 1651 * This is fixing some of the default configuration of the XIVE 1652 * devices. To be called after the reset of the machine devices. 1653 */ 1654 spapr_irq_reset(spapr, &error_fatal); 1655 1656 /* 1657 * There is no CAS under qtest. Simulate one to please the code that 1658 * depends on spapr->ov5_cas. This is especially needed to test device 1659 * unplug, so we do that before resetting the DRCs. 1660 */ 1661 if (qtest_enabled()) { 1662 spapr_ovec_cleanup(spapr->ov5_cas); 1663 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1664 } 1665 1666 spapr_nvdimm_finish_flushes(); 1667 1668 /* DRC reset may cause a device to be unplugged. This will cause troubles 1669 * if this device is used by another device (eg, a running vhost backend 1670 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1671 * situations, we reset DRCs after all devices have been reset. 1672 */ 1673 spapr_drc_reset_all(spapr); 1674 1675 spapr_clear_pending_events(spapr); 1676 1677 /* 1678 * We place the device tree just below either the top of the RMA, 1679 * or just below 2GB, whichever is lower, so that it can be 1680 * processed with 32-bit real mode code if necessary 1681 */ 1682 fdt_addr = MIN(spapr->rma_size, FDT_MAX_ADDR) - FDT_MAX_SIZE; 1683 1684 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1685 if (spapr->vof) { 1686 spapr_vof_reset(spapr, fdt, &error_fatal); 1687 /* 1688 * Do not pack the FDT as the client may change properties. 1689 * VOF client does not expect the FDT so we do not load it to the VM. 1690 */ 1691 } else { 1692 rc = fdt_pack(fdt); 1693 /* Should only fail if we've built a corrupted tree */ 1694 assert(rc == 0); 1695 1696 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 1697 0, fdt_addr, 0); 1698 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1699 } 1700 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1701 1702 g_free(spapr->fdt_blob); 1703 spapr->fdt_size = fdt_totalsize(fdt); 1704 spapr->fdt_initial_size = spapr->fdt_size; 1705 spapr->fdt_blob = fdt; 1706 1707 /* Set up the entry state */ 1708 first_ppc_cpu->env.gpr[5] = 0; 1709 1710 spapr->fwnmi_system_reset_addr = -1; 1711 spapr->fwnmi_machine_check_addr = -1; 1712 spapr->fwnmi_machine_check_interlock = -1; 1713 1714 /* Signal all vCPUs waiting on this condition */ 1715 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1716 1717 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1718 } 1719 1720 static void spapr_create_nvram(SpaprMachineState *spapr) 1721 { 1722 DeviceState *dev = qdev_new("spapr-nvram"); 1723 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1724 1725 if (dinfo) { 1726 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1727 &error_fatal); 1728 } 1729 1730 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1731 1732 spapr->nvram = (struct SpaprNvram *)dev; 1733 } 1734 1735 static void spapr_rtc_create(SpaprMachineState *spapr) 1736 { 1737 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1738 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1739 &error_fatal, NULL); 1740 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1741 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1742 "date"); 1743 } 1744 1745 /* Returns whether we want to use VGA or not */ 1746 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1747 { 1748 switch (vga_interface_type) { 1749 case VGA_NONE: 1750 return false; 1751 case VGA_DEVICE: 1752 return true; 1753 case VGA_STD: 1754 case VGA_VIRTIO: 1755 case VGA_CIRRUS: 1756 return pci_vga_init(pci_bus) != NULL; 1757 default: 1758 error_setg(errp, 1759 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1760 return false; 1761 } 1762 } 1763 1764 static int spapr_pre_load(void *opaque) 1765 { 1766 int rc; 1767 1768 rc = spapr_caps_pre_load(opaque); 1769 if (rc) { 1770 return rc; 1771 } 1772 1773 return 0; 1774 } 1775 1776 static int spapr_post_load(void *opaque, int version_id) 1777 { 1778 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1779 int err = 0; 1780 1781 err = spapr_caps_post_migration(spapr); 1782 if (err) { 1783 return err; 1784 } 1785 1786 /* 1787 * In earlier versions, there was no separate qdev for the PAPR 1788 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1789 * So when migrating from those versions, poke the incoming offset 1790 * value into the RTC device 1791 */ 1792 if (version_id < 3) { 1793 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1794 if (err) { 1795 return err; 1796 } 1797 } 1798 1799 if (kvm_enabled() && spapr->patb_entry) { 1800 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1801 bool radix = !!(spapr->patb_entry & PATE1_GR); 1802 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1803 1804 /* 1805 * Update LPCR:HR and UPRT as they may not be set properly in 1806 * the stream 1807 */ 1808 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1809 LPCR_HR | LPCR_UPRT); 1810 1811 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1812 if (err) { 1813 error_report("Process table config unsupported by the host"); 1814 return -EINVAL; 1815 } 1816 } 1817 1818 err = spapr_irq_post_load(spapr, version_id); 1819 if (err) { 1820 return err; 1821 } 1822 1823 return err; 1824 } 1825 1826 static int spapr_pre_save(void *opaque) 1827 { 1828 int rc; 1829 1830 rc = spapr_caps_pre_save(opaque); 1831 if (rc) { 1832 return rc; 1833 } 1834 1835 return 0; 1836 } 1837 1838 static bool version_before_3(void *opaque, int version_id) 1839 { 1840 return version_id < 3; 1841 } 1842 1843 static bool spapr_pending_events_needed(void *opaque) 1844 { 1845 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1846 return !QTAILQ_EMPTY(&spapr->pending_events); 1847 } 1848 1849 static const VMStateDescription vmstate_spapr_event_entry = { 1850 .name = "spapr_event_log_entry", 1851 .version_id = 1, 1852 .minimum_version_id = 1, 1853 .fields = (VMStateField[]) { 1854 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1855 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1856 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1857 NULL, extended_length), 1858 VMSTATE_END_OF_LIST() 1859 }, 1860 }; 1861 1862 static const VMStateDescription vmstate_spapr_pending_events = { 1863 .name = "spapr_pending_events", 1864 .version_id = 1, 1865 .minimum_version_id = 1, 1866 .needed = spapr_pending_events_needed, 1867 .fields = (VMStateField[]) { 1868 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1869 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1870 VMSTATE_END_OF_LIST() 1871 }, 1872 }; 1873 1874 static bool spapr_ov5_cas_needed(void *opaque) 1875 { 1876 SpaprMachineState *spapr = opaque; 1877 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1878 bool cas_needed; 1879 1880 /* Prior to the introduction of SpaprOptionVector, we had two option 1881 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1882 * Both of these options encode machine topology into the device-tree 1883 * in such a way that the now-booted OS should still be able to interact 1884 * appropriately with QEMU regardless of what options were actually 1885 * negotiatied on the source side. 1886 * 1887 * As such, we can avoid migrating the CAS-negotiated options if these 1888 * are the only options available on the current machine/platform. 1889 * Since these are the only options available for pseries-2.7 and 1890 * earlier, this allows us to maintain old->new/new->old migration 1891 * compatibility. 1892 * 1893 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1894 * via default pseries-2.8 machines and explicit command-line parameters. 1895 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1896 * of the actual CAS-negotiated values to continue working properly. For 1897 * example, availability of memory unplug depends on knowing whether 1898 * OV5_HP_EVT was negotiated via CAS. 1899 * 1900 * Thus, for any cases where the set of available CAS-negotiatable 1901 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1902 * include the CAS-negotiated options in the migration stream, unless 1903 * if they affect boot time behaviour only. 1904 */ 1905 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1906 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1907 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1908 1909 /* We need extra information if we have any bits outside the mask 1910 * defined above */ 1911 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1912 1913 spapr_ovec_cleanup(ov5_mask); 1914 1915 return cas_needed; 1916 } 1917 1918 static const VMStateDescription vmstate_spapr_ov5_cas = { 1919 .name = "spapr_option_vector_ov5_cas", 1920 .version_id = 1, 1921 .minimum_version_id = 1, 1922 .needed = spapr_ov5_cas_needed, 1923 .fields = (VMStateField[]) { 1924 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1925 vmstate_spapr_ovec, SpaprOptionVector), 1926 VMSTATE_END_OF_LIST() 1927 }, 1928 }; 1929 1930 static bool spapr_patb_entry_needed(void *opaque) 1931 { 1932 SpaprMachineState *spapr = opaque; 1933 1934 return !!spapr->patb_entry; 1935 } 1936 1937 static const VMStateDescription vmstate_spapr_patb_entry = { 1938 .name = "spapr_patb_entry", 1939 .version_id = 1, 1940 .minimum_version_id = 1, 1941 .needed = spapr_patb_entry_needed, 1942 .fields = (VMStateField[]) { 1943 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1944 VMSTATE_END_OF_LIST() 1945 }, 1946 }; 1947 1948 static bool spapr_irq_map_needed(void *opaque) 1949 { 1950 SpaprMachineState *spapr = opaque; 1951 1952 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1953 } 1954 1955 static const VMStateDescription vmstate_spapr_irq_map = { 1956 .name = "spapr_irq_map", 1957 .version_id = 1, 1958 .minimum_version_id = 1, 1959 .needed = spapr_irq_map_needed, 1960 .fields = (VMStateField[]) { 1961 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1962 VMSTATE_END_OF_LIST() 1963 }, 1964 }; 1965 1966 static bool spapr_dtb_needed(void *opaque) 1967 { 1968 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1969 1970 return smc->update_dt_enabled; 1971 } 1972 1973 static int spapr_dtb_pre_load(void *opaque) 1974 { 1975 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1976 1977 g_free(spapr->fdt_blob); 1978 spapr->fdt_blob = NULL; 1979 spapr->fdt_size = 0; 1980 1981 return 0; 1982 } 1983 1984 static const VMStateDescription vmstate_spapr_dtb = { 1985 .name = "spapr_dtb", 1986 .version_id = 1, 1987 .minimum_version_id = 1, 1988 .needed = spapr_dtb_needed, 1989 .pre_load = spapr_dtb_pre_load, 1990 .fields = (VMStateField[]) { 1991 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1992 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1993 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1994 fdt_size), 1995 VMSTATE_END_OF_LIST() 1996 }, 1997 }; 1998 1999 static bool spapr_fwnmi_needed(void *opaque) 2000 { 2001 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2002 2003 return spapr->fwnmi_machine_check_addr != -1; 2004 } 2005 2006 static int spapr_fwnmi_pre_save(void *opaque) 2007 { 2008 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2009 2010 /* 2011 * Check if machine check handling is in progress and print a 2012 * warning message. 2013 */ 2014 if (spapr->fwnmi_machine_check_interlock != -1) { 2015 warn_report("A machine check is being handled during migration. The" 2016 "handler may run and log hardware error on the destination"); 2017 } 2018 2019 return 0; 2020 } 2021 2022 static const VMStateDescription vmstate_spapr_fwnmi = { 2023 .name = "spapr_fwnmi", 2024 .version_id = 1, 2025 .minimum_version_id = 1, 2026 .needed = spapr_fwnmi_needed, 2027 .pre_save = spapr_fwnmi_pre_save, 2028 .fields = (VMStateField[]) { 2029 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 2030 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 2031 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 2032 VMSTATE_END_OF_LIST() 2033 }, 2034 }; 2035 2036 static const VMStateDescription vmstate_spapr = { 2037 .name = "spapr", 2038 .version_id = 3, 2039 .minimum_version_id = 1, 2040 .pre_load = spapr_pre_load, 2041 .post_load = spapr_post_load, 2042 .pre_save = spapr_pre_save, 2043 .fields = (VMStateField[]) { 2044 /* used to be @next_irq */ 2045 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2046 2047 /* RTC offset */ 2048 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2049 2050 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2051 VMSTATE_END_OF_LIST() 2052 }, 2053 .subsections = (const VMStateDescription*[]) { 2054 &vmstate_spapr_ov5_cas, 2055 &vmstate_spapr_patb_entry, 2056 &vmstate_spapr_pending_events, 2057 &vmstate_spapr_cap_htm, 2058 &vmstate_spapr_cap_vsx, 2059 &vmstate_spapr_cap_dfp, 2060 &vmstate_spapr_cap_cfpc, 2061 &vmstate_spapr_cap_sbbc, 2062 &vmstate_spapr_cap_ibs, 2063 &vmstate_spapr_cap_hpt_maxpagesize, 2064 &vmstate_spapr_irq_map, 2065 &vmstate_spapr_cap_nested_kvm_hv, 2066 &vmstate_spapr_dtb, 2067 &vmstate_spapr_cap_large_decr, 2068 &vmstate_spapr_cap_ccf_assist, 2069 &vmstate_spapr_cap_fwnmi, 2070 &vmstate_spapr_fwnmi, 2071 &vmstate_spapr_cap_rpt_invalidate, 2072 NULL 2073 } 2074 }; 2075 2076 static int htab_save_setup(QEMUFile *f, void *opaque) 2077 { 2078 SpaprMachineState *spapr = opaque; 2079 2080 /* "Iteration" header */ 2081 if (!spapr->htab_shift) { 2082 qemu_put_be32(f, -1); 2083 } else { 2084 qemu_put_be32(f, spapr->htab_shift); 2085 } 2086 2087 if (spapr->htab) { 2088 spapr->htab_save_index = 0; 2089 spapr->htab_first_pass = true; 2090 } else { 2091 if (spapr->htab_shift) { 2092 assert(kvm_enabled()); 2093 } 2094 } 2095 2096 2097 return 0; 2098 } 2099 2100 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2101 int chunkstart, int n_valid, int n_invalid) 2102 { 2103 qemu_put_be32(f, chunkstart); 2104 qemu_put_be16(f, n_valid); 2105 qemu_put_be16(f, n_invalid); 2106 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2107 HASH_PTE_SIZE_64 * n_valid); 2108 } 2109 2110 static void htab_save_end_marker(QEMUFile *f) 2111 { 2112 qemu_put_be32(f, 0); 2113 qemu_put_be16(f, 0); 2114 qemu_put_be16(f, 0); 2115 } 2116 2117 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2118 int64_t max_ns) 2119 { 2120 bool has_timeout = max_ns != -1; 2121 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2122 int index = spapr->htab_save_index; 2123 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2124 2125 assert(spapr->htab_first_pass); 2126 2127 do { 2128 int chunkstart; 2129 2130 /* Consume invalid HPTEs */ 2131 while ((index < htabslots) 2132 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2133 CLEAN_HPTE(HPTE(spapr->htab, index)); 2134 index++; 2135 } 2136 2137 /* Consume valid HPTEs */ 2138 chunkstart = index; 2139 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2140 && HPTE_VALID(HPTE(spapr->htab, index))) { 2141 CLEAN_HPTE(HPTE(spapr->htab, index)); 2142 index++; 2143 } 2144 2145 if (index > chunkstart) { 2146 int n_valid = index - chunkstart; 2147 2148 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2149 2150 if (has_timeout && 2151 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2152 break; 2153 } 2154 } 2155 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2156 2157 if (index >= htabslots) { 2158 assert(index == htabslots); 2159 index = 0; 2160 spapr->htab_first_pass = false; 2161 } 2162 spapr->htab_save_index = index; 2163 } 2164 2165 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2166 int64_t max_ns) 2167 { 2168 bool final = max_ns < 0; 2169 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2170 int examined = 0, sent = 0; 2171 int index = spapr->htab_save_index; 2172 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2173 2174 assert(!spapr->htab_first_pass); 2175 2176 do { 2177 int chunkstart, invalidstart; 2178 2179 /* Consume non-dirty HPTEs */ 2180 while ((index < htabslots) 2181 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2182 index++; 2183 examined++; 2184 } 2185 2186 chunkstart = index; 2187 /* Consume valid dirty HPTEs */ 2188 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2189 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2190 && HPTE_VALID(HPTE(spapr->htab, index))) { 2191 CLEAN_HPTE(HPTE(spapr->htab, index)); 2192 index++; 2193 examined++; 2194 } 2195 2196 invalidstart = index; 2197 /* Consume invalid dirty HPTEs */ 2198 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2199 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2200 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2201 CLEAN_HPTE(HPTE(spapr->htab, index)); 2202 index++; 2203 examined++; 2204 } 2205 2206 if (index > chunkstart) { 2207 int n_valid = invalidstart - chunkstart; 2208 int n_invalid = index - invalidstart; 2209 2210 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2211 sent += index - chunkstart; 2212 2213 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2214 break; 2215 } 2216 } 2217 2218 if (examined >= htabslots) { 2219 break; 2220 } 2221 2222 if (index >= htabslots) { 2223 assert(index == htabslots); 2224 index = 0; 2225 } 2226 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2227 2228 if (index >= htabslots) { 2229 assert(index == htabslots); 2230 index = 0; 2231 } 2232 2233 spapr->htab_save_index = index; 2234 2235 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2236 } 2237 2238 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2239 #define MAX_KVM_BUF_SIZE 2048 2240 2241 static int htab_save_iterate(QEMUFile *f, void *opaque) 2242 { 2243 SpaprMachineState *spapr = opaque; 2244 int fd; 2245 int rc = 0; 2246 2247 /* Iteration header */ 2248 if (!spapr->htab_shift) { 2249 qemu_put_be32(f, -1); 2250 return 1; 2251 } else { 2252 qemu_put_be32(f, 0); 2253 } 2254 2255 if (!spapr->htab) { 2256 assert(kvm_enabled()); 2257 2258 fd = get_htab_fd(spapr); 2259 if (fd < 0) { 2260 return fd; 2261 } 2262 2263 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2264 if (rc < 0) { 2265 return rc; 2266 } 2267 } else if (spapr->htab_first_pass) { 2268 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2269 } else { 2270 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2271 } 2272 2273 htab_save_end_marker(f); 2274 2275 return rc; 2276 } 2277 2278 static int htab_save_complete(QEMUFile *f, void *opaque) 2279 { 2280 SpaprMachineState *spapr = opaque; 2281 int fd; 2282 2283 /* Iteration header */ 2284 if (!spapr->htab_shift) { 2285 qemu_put_be32(f, -1); 2286 return 0; 2287 } else { 2288 qemu_put_be32(f, 0); 2289 } 2290 2291 if (!spapr->htab) { 2292 int rc; 2293 2294 assert(kvm_enabled()); 2295 2296 fd = get_htab_fd(spapr); 2297 if (fd < 0) { 2298 return fd; 2299 } 2300 2301 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2302 if (rc < 0) { 2303 return rc; 2304 } 2305 } else { 2306 if (spapr->htab_first_pass) { 2307 htab_save_first_pass(f, spapr, -1); 2308 } 2309 htab_save_later_pass(f, spapr, -1); 2310 } 2311 2312 /* End marker */ 2313 htab_save_end_marker(f); 2314 2315 return 0; 2316 } 2317 2318 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2319 { 2320 SpaprMachineState *spapr = opaque; 2321 uint32_t section_hdr; 2322 int fd = -1; 2323 Error *local_err = NULL; 2324 2325 if (version_id < 1 || version_id > 1) { 2326 error_report("htab_load() bad version"); 2327 return -EINVAL; 2328 } 2329 2330 section_hdr = qemu_get_be32(f); 2331 2332 if (section_hdr == -1) { 2333 spapr_free_hpt(spapr); 2334 return 0; 2335 } 2336 2337 if (section_hdr) { 2338 int ret; 2339 2340 /* First section gives the htab size */ 2341 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2342 if (ret < 0) { 2343 error_report_err(local_err); 2344 return ret; 2345 } 2346 return 0; 2347 } 2348 2349 if (!spapr->htab) { 2350 assert(kvm_enabled()); 2351 2352 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2353 if (fd < 0) { 2354 error_report_err(local_err); 2355 return fd; 2356 } 2357 } 2358 2359 while (true) { 2360 uint32_t index; 2361 uint16_t n_valid, n_invalid; 2362 2363 index = qemu_get_be32(f); 2364 n_valid = qemu_get_be16(f); 2365 n_invalid = qemu_get_be16(f); 2366 2367 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2368 /* End of Stream */ 2369 break; 2370 } 2371 2372 if ((index + n_valid + n_invalid) > 2373 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2374 /* Bad index in stream */ 2375 error_report( 2376 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2377 index, n_valid, n_invalid, spapr->htab_shift); 2378 return -EINVAL; 2379 } 2380 2381 if (spapr->htab) { 2382 if (n_valid) { 2383 qemu_get_buffer(f, HPTE(spapr->htab, index), 2384 HASH_PTE_SIZE_64 * n_valid); 2385 } 2386 if (n_invalid) { 2387 memset(HPTE(spapr->htab, index + n_valid), 0, 2388 HASH_PTE_SIZE_64 * n_invalid); 2389 } 2390 } else { 2391 int rc; 2392 2393 assert(fd >= 0); 2394 2395 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2396 &local_err); 2397 if (rc < 0) { 2398 error_report_err(local_err); 2399 return rc; 2400 } 2401 } 2402 } 2403 2404 if (!spapr->htab) { 2405 assert(fd >= 0); 2406 close(fd); 2407 } 2408 2409 return 0; 2410 } 2411 2412 static void htab_save_cleanup(void *opaque) 2413 { 2414 SpaprMachineState *spapr = opaque; 2415 2416 close_htab_fd(spapr); 2417 } 2418 2419 static SaveVMHandlers savevm_htab_handlers = { 2420 .save_setup = htab_save_setup, 2421 .save_live_iterate = htab_save_iterate, 2422 .save_live_complete_precopy = htab_save_complete, 2423 .save_cleanup = htab_save_cleanup, 2424 .load_state = htab_load, 2425 }; 2426 2427 static void spapr_boot_set(void *opaque, const char *boot_device, 2428 Error **errp) 2429 { 2430 SpaprMachineState *spapr = SPAPR_MACHINE(opaque); 2431 2432 g_free(spapr->boot_device); 2433 spapr->boot_device = g_strdup(boot_device); 2434 } 2435 2436 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2437 { 2438 MachineState *machine = MACHINE(spapr); 2439 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2440 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2441 int i; 2442 2443 for (i = 0; i < nr_lmbs; i++) { 2444 uint64_t addr; 2445 2446 addr = i * lmb_size + machine->device_memory->base; 2447 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2448 addr / lmb_size); 2449 } 2450 } 2451 2452 /* 2453 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2454 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2455 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2456 */ 2457 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2458 { 2459 int i; 2460 2461 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2462 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2463 " is not aligned to %" PRIu64 " MiB", 2464 machine->ram_size, 2465 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2466 return; 2467 } 2468 2469 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2470 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2471 " is not aligned to %" PRIu64 " MiB", 2472 machine->ram_size, 2473 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2474 return; 2475 } 2476 2477 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2478 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2479 error_setg(errp, 2480 "Node %d memory size 0x%" PRIx64 2481 " is not aligned to %" PRIu64 " MiB", 2482 i, machine->numa_state->nodes[i].node_mem, 2483 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2484 return; 2485 } 2486 } 2487 } 2488 2489 /* find cpu slot in machine->possible_cpus by core_id */ 2490 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2491 { 2492 int index = id / ms->smp.threads; 2493 2494 if (index >= ms->possible_cpus->len) { 2495 return NULL; 2496 } 2497 if (idx) { 2498 *idx = index; 2499 } 2500 return &ms->possible_cpus->cpus[index]; 2501 } 2502 2503 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2504 { 2505 MachineState *ms = MACHINE(spapr); 2506 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2507 Error *local_err = NULL; 2508 bool vsmt_user = !!spapr->vsmt; 2509 int kvm_smt = kvmppc_smt_threads(); 2510 int ret; 2511 unsigned int smp_threads = ms->smp.threads; 2512 2513 if (!kvm_enabled() && (smp_threads > 1)) { 2514 error_setg(errp, "TCG cannot support more than 1 thread/core " 2515 "on a pseries machine"); 2516 return; 2517 } 2518 if (!is_power_of_2(smp_threads)) { 2519 error_setg(errp, "Cannot support %d threads/core on a pseries " 2520 "machine because it must be a power of 2", smp_threads); 2521 return; 2522 } 2523 2524 /* Detemine the VSMT mode to use: */ 2525 if (vsmt_user) { 2526 if (spapr->vsmt < smp_threads) { 2527 error_setg(errp, "Cannot support VSMT mode %d" 2528 " because it must be >= threads/core (%d)", 2529 spapr->vsmt, smp_threads); 2530 return; 2531 } 2532 /* In this case, spapr->vsmt has been set by the command line */ 2533 } else if (!smc->smp_threads_vsmt) { 2534 /* 2535 * Default VSMT value is tricky, because we need it to be as 2536 * consistent as possible (for migration), but this requires 2537 * changing it for at least some existing cases. We pick 8 as 2538 * the value that we'd get with KVM on POWER8, the 2539 * overwhelmingly common case in production systems. 2540 */ 2541 spapr->vsmt = MAX(8, smp_threads); 2542 } else { 2543 spapr->vsmt = smp_threads; 2544 } 2545 2546 /* KVM: If necessary, set the SMT mode: */ 2547 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2548 ret = kvmppc_set_smt_threads(spapr->vsmt); 2549 if (ret) { 2550 /* Looks like KVM isn't able to change VSMT mode */ 2551 error_setg(&local_err, 2552 "Failed to set KVM's VSMT mode to %d (errno %d)", 2553 spapr->vsmt, ret); 2554 /* We can live with that if the default one is big enough 2555 * for the number of threads, and a submultiple of the one 2556 * we want. In this case we'll waste some vcpu ids, but 2557 * behaviour will be correct */ 2558 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2559 warn_report_err(local_err); 2560 } else { 2561 if (!vsmt_user) { 2562 error_append_hint(&local_err, 2563 "On PPC, a VM with %d threads/core" 2564 " on a host with %d threads/core" 2565 " requires the use of VSMT mode %d.\n", 2566 smp_threads, kvm_smt, spapr->vsmt); 2567 } 2568 kvmppc_error_append_smt_possible_hint(&local_err); 2569 error_propagate(errp, local_err); 2570 } 2571 } 2572 } 2573 /* else TCG: nothing to do currently */ 2574 } 2575 2576 static void spapr_init_cpus(SpaprMachineState *spapr) 2577 { 2578 MachineState *machine = MACHINE(spapr); 2579 MachineClass *mc = MACHINE_GET_CLASS(machine); 2580 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2581 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2582 const CPUArchIdList *possible_cpus; 2583 unsigned int smp_cpus = machine->smp.cpus; 2584 unsigned int smp_threads = machine->smp.threads; 2585 unsigned int max_cpus = machine->smp.max_cpus; 2586 int boot_cores_nr = smp_cpus / smp_threads; 2587 int i; 2588 2589 possible_cpus = mc->possible_cpu_arch_ids(machine); 2590 if (mc->has_hotpluggable_cpus) { 2591 if (smp_cpus % smp_threads) { 2592 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2593 smp_cpus, smp_threads); 2594 exit(1); 2595 } 2596 if (max_cpus % smp_threads) { 2597 error_report("max_cpus (%u) must be multiple of threads (%u)", 2598 max_cpus, smp_threads); 2599 exit(1); 2600 } 2601 } else { 2602 if (max_cpus != smp_cpus) { 2603 error_report("This machine version does not support CPU hotplug"); 2604 exit(1); 2605 } 2606 boot_cores_nr = possible_cpus->len; 2607 } 2608 2609 if (smc->pre_2_10_has_unused_icps) { 2610 int i; 2611 2612 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2613 /* Dummy entries get deregistered when real ICPState objects 2614 * are registered during CPU core hotplug. 2615 */ 2616 pre_2_10_vmstate_register_dummy_icp(i); 2617 } 2618 } 2619 2620 for (i = 0; i < possible_cpus->len; i++) { 2621 int core_id = i * smp_threads; 2622 2623 if (mc->has_hotpluggable_cpus) { 2624 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2625 spapr_vcpu_id(spapr, core_id)); 2626 } 2627 2628 if (i < boot_cores_nr) { 2629 Object *core = object_new(type); 2630 int nr_threads = smp_threads; 2631 2632 /* Handle the partially filled core for older machine types */ 2633 if ((i + 1) * smp_threads >= smp_cpus) { 2634 nr_threads = smp_cpus - i * smp_threads; 2635 } 2636 2637 object_property_set_int(core, "nr-threads", nr_threads, 2638 &error_fatal); 2639 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2640 &error_fatal); 2641 qdev_realize(DEVICE(core), NULL, &error_fatal); 2642 2643 object_unref(core); 2644 } 2645 } 2646 } 2647 2648 static PCIHostState *spapr_create_default_phb(void) 2649 { 2650 DeviceState *dev; 2651 2652 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2653 qdev_prop_set_uint32(dev, "index", 0); 2654 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2655 2656 return PCI_HOST_BRIDGE(dev); 2657 } 2658 2659 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2660 { 2661 MachineState *machine = MACHINE(spapr); 2662 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2663 hwaddr rma_size = machine->ram_size; 2664 hwaddr node0_size = spapr_node0_size(machine); 2665 2666 /* RMA has to fit in the first NUMA node */ 2667 rma_size = MIN(rma_size, node0_size); 2668 2669 /* 2670 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2671 * never exceed that 2672 */ 2673 rma_size = MIN(rma_size, 1 * TiB); 2674 2675 /* 2676 * Clamp the RMA size based on machine type. This is for 2677 * migration compatibility with older qemu versions, which limited 2678 * the RMA size for complicated and mostly bad reasons. 2679 */ 2680 if (smc->rma_limit) { 2681 rma_size = MIN(rma_size, smc->rma_limit); 2682 } 2683 2684 if (rma_size < MIN_RMA_SLOF) { 2685 error_setg(errp, 2686 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2687 "ldMiB guest RMA (Real Mode Area memory)", 2688 MIN_RMA_SLOF / MiB); 2689 return 0; 2690 } 2691 2692 return rma_size; 2693 } 2694 2695 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2696 { 2697 MachineState *machine = MACHINE(spapr); 2698 int i; 2699 2700 for (i = 0; i < machine->ram_slots; i++) { 2701 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2702 } 2703 } 2704 2705 /* pSeries LPAR / sPAPR hardware init */ 2706 static void spapr_machine_init(MachineState *machine) 2707 { 2708 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2709 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2710 MachineClass *mc = MACHINE_GET_CLASS(machine); 2711 const char *bios_default = spapr->vof ? FW_FILE_NAME_VOF : FW_FILE_NAME; 2712 const char *bios_name = machine->firmware ?: bios_default; 2713 const char *kernel_filename = machine->kernel_filename; 2714 const char *initrd_filename = machine->initrd_filename; 2715 PCIHostState *phb; 2716 int i; 2717 MemoryRegion *sysmem = get_system_memory(); 2718 long load_limit, fw_size; 2719 char *filename; 2720 Error *resize_hpt_err = NULL; 2721 2722 /* 2723 * if Secure VM (PEF) support is configured, then initialize it 2724 */ 2725 pef_kvm_init(machine->cgs, &error_fatal); 2726 2727 msi_nonbroken = true; 2728 2729 QLIST_INIT(&spapr->phbs); 2730 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2731 2732 /* Determine capabilities to run with */ 2733 spapr_caps_init(spapr); 2734 2735 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2736 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2737 /* 2738 * If the user explicitly requested a mode we should either 2739 * supply it, or fail completely (which we do below). But if 2740 * it's not set explicitly, we reset our mode to something 2741 * that works 2742 */ 2743 if (resize_hpt_err) { 2744 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2745 error_free(resize_hpt_err); 2746 resize_hpt_err = NULL; 2747 } else { 2748 spapr->resize_hpt = smc->resize_hpt_default; 2749 } 2750 } 2751 2752 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2753 2754 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2755 /* 2756 * User requested HPT resize, but this host can't supply it. Bail out 2757 */ 2758 error_report_err(resize_hpt_err); 2759 exit(1); 2760 } 2761 error_free(resize_hpt_err); 2762 2763 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2764 2765 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2766 load_limit = MIN(spapr->rma_size, FDT_MAX_ADDR) - FW_OVERHEAD; 2767 2768 /* 2769 * VSMT must be set in order to be able to compute VCPU ids, ie to 2770 * call spapr_max_server_number() or spapr_vcpu_id(). 2771 */ 2772 spapr_set_vsmt_mode(spapr, &error_fatal); 2773 2774 /* Set up Interrupt Controller before we create the VCPUs */ 2775 spapr_irq_init(spapr, &error_fatal); 2776 2777 /* Set up containers for ibm,client-architecture-support negotiated options 2778 */ 2779 spapr->ov5 = spapr_ovec_new(); 2780 spapr->ov5_cas = spapr_ovec_new(); 2781 2782 if (smc->dr_lmb_enabled) { 2783 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2784 spapr_validate_node_memory(machine, &error_fatal); 2785 } 2786 2787 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2788 2789 /* Do not advertise FORM2 NUMA support for pseries-6.1 and older */ 2790 if (!smc->pre_6_2_numa_affinity) { 2791 spapr_ovec_set(spapr->ov5, OV5_FORM2_AFFINITY); 2792 } 2793 2794 /* advertise support for dedicated HP event source to guests */ 2795 if (spapr->use_hotplug_event_source) { 2796 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2797 } 2798 2799 /* advertise support for HPT resizing */ 2800 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2801 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2802 } 2803 2804 /* advertise support for ibm,dyamic-memory-v2 */ 2805 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2806 2807 /* advertise XIVE on POWER9 machines */ 2808 if (spapr->irq->xive) { 2809 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2810 } 2811 2812 /* init CPUs */ 2813 spapr_init_cpus(spapr); 2814 2815 spapr->gpu_numa_id = spapr_numa_initial_nvgpu_numa_id(machine); 2816 2817 /* Init numa_assoc_array */ 2818 spapr_numa_associativity_init(spapr, machine); 2819 2820 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2821 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2822 spapr->max_compat_pvr)) { 2823 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2824 /* KVM and TCG always allow GTSE with radix... */ 2825 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2826 } 2827 /* ... but not with hash (currently). */ 2828 2829 if (kvm_enabled()) { 2830 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2831 kvmppc_enable_logical_ci_hcalls(); 2832 kvmppc_enable_set_mode_hcall(); 2833 2834 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2835 kvmppc_enable_clear_ref_mod_hcalls(); 2836 2837 /* Enable H_PAGE_INIT */ 2838 kvmppc_enable_h_page_init(); 2839 } 2840 2841 /* map RAM */ 2842 memory_region_add_subregion(sysmem, 0, machine->ram); 2843 2844 /* always allocate the device memory information */ 2845 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2846 2847 /* initialize hotplug memory address space */ 2848 if (machine->ram_size < machine->maxram_size) { 2849 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2850 /* 2851 * Limit the number of hotpluggable memory slots to half the number 2852 * slots that KVM supports, leaving the other half for PCI and other 2853 * devices. However ensure that number of slots doesn't drop below 32. 2854 */ 2855 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2856 SPAPR_MAX_RAM_SLOTS; 2857 2858 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2859 max_memslots = SPAPR_MAX_RAM_SLOTS; 2860 } 2861 if (machine->ram_slots > max_memslots) { 2862 error_report("Specified number of memory slots %" 2863 PRIu64" exceeds max supported %d", 2864 machine->ram_slots, max_memslots); 2865 exit(1); 2866 } 2867 2868 machine->device_memory->base = ROUND_UP(machine->ram_size, 2869 SPAPR_DEVICE_MEM_ALIGN); 2870 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2871 "device-memory", device_mem_size); 2872 memory_region_add_subregion(sysmem, machine->device_memory->base, 2873 &machine->device_memory->mr); 2874 } 2875 2876 if (smc->dr_lmb_enabled) { 2877 spapr_create_lmb_dr_connectors(spapr); 2878 } 2879 2880 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { 2881 /* Create the error string for live migration blocker */ 2882 error_setg(&spapr->fwnmi_migration_blocker, 2883 "A machine check is being handled during migration. The handler" 2884 "may run and log hardware error on the destination"); 2885 } 2886 2887 if (mc->nvdimm_supported) { 2888 spapr_create_nvdimm_dr_connectors(spapr); 2889 } 2890 2891 /* Set up RTAS event infrastructure */ 2892 spapr_events_init(spapr); 2893 2894 /* Set up the RTC RTAS interfaces */ 2895 spapr_rtc_create(spapr); 2896 2897 /* Set up VIO bus */ 2898 spapr->vio_bus = spapr_vio_bus_init(); 2899 2900 for (i = 0; serial_hd(i); i++) { 2901 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2902 } 2903 2904 /* We always have at least the nvram device on VIO */ 2905 spapr_create_nvram(spapr); 2906 2907 /* 2908 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2909 * connectors (described in root DT node's "ibm,drc-types" property) 2910 * are pre-initialized here. additional child connectors (such as 2911 * connectors for a PHBs PCI slots) are added as needed during their 2912 * parent's realization. 2913 */ 2914 if (smc->dr_phb_enabled) { 2915 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2916 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2917 } 2918 } 2919 2920 /* Set up PCI */ 2921 spapr_pci_rtas_init(); 2922 2923 phb = spapr_create_default_phb(); 2924 2925 for (i = 0; i < nb_nics; i++) { 2926 NICInfo *nd = &nd_table[i]; 2927 2928 if (!nd->model) { 2929 nd->model = g_strdup("spapr-vlan"); 2930 } 2931 2932 if (g_str_equal(nd->model, "spapr-vlan") || 2933 g_str_equal(nd->model, "ibmveth")) { 2934 spapr_vlan_create(spapr->vio_bus, nd); 2935 } else { 2936 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2937 } 2938 } 2939 2940 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2941 spapr_vscsi_create(spapr->vio_bus); 2942 } 2943 2944 /* Graphics */ 2945 if (spapr_vga_init(phb->bus, &error_fatal)) { 2946 spapr->has_graphics = true; 2947 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2948 } 2949 2950 if (machine->usb) { 2951 if (smc->use_ohci_by_default) { 2952 pci_create_simple(phb->bus, -1, "pci-ohci"); 2953 } else { 2954 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2955 } 2956 2957 if (spapr->has_graphics) { 2958 USBBus *usb_bus = usb_bus_find(-1); 2959 2960 usb_create_simple(usb_bus, "usb-kbd"); 2961 usb_create_simple(usb_bus, "usb-mouse"); 2962 } 2963 } 2964 2965 if (kernel_filename) { 2966 spapr->kernel_size = load_elf(kernel_filename, NULL, 2967 translate_kernel_address, spapr, 2968 NULL, NULL, NULL, NULL, 1, 2969 PPC_ELF_MACHINE, 0, 0); 2970 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2971 spapr->kernel_size = load_elf(kernel_filename, NULL, 2972 translate_kernel_address, spapr, 2973 NULL, NULL, NULL, NULL, 0, 2974 PPC_ELF_MACHINE, 0, 0); 2975 spapr->kernel_le = spapr->kernel_size > 0; 2976 } 2977 if (spapr->kernel_size < 0) { 2978 error_report("error loading %s: %s", kernel_filename, 2979 load_elf_strerror(spapr->kernel_size)); 2980 exit(1); 2981 } 2982 2983 /* load initrd */ 2984 if (initrd_filename) { 2985 /* Try to locate the initrd in the gap between the kernel 2986 * and the firmware. Add a bit of space just in case 2987 */ 2988 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 2989 + 0x1ffff) & ~0xffff; 2990 spapr->initrd_size = load_image_targphys(initrd_filename, 2991 spapr->initrd_base, 2992 load_limit 2993 - spapr->initrd_base); 2994 if (spapr->initrd_size < 0) { 2995 error_report("could not load initial ram disk '%s'", 2996 initrd_filename); 2997 exit(1); 2998 } 2999 } 3000 } 3001 3002 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 3003 if (!filename) { 3004 error_report("Could not find LPAR firmware '%s'", bios_name); 3005 exit(1); 3006 } 3007 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 3008 if (fw_size <= 0) { 3009 error_report("Could not load LPAR firmware '%s'", filename); 3010 exit(1); 3011 } 3012 g_free(filename); 3013 3014 /* FIXME: Should register things through the MachineState's qdev 3015 * interface, this is a legacy from the sPAPREnvironment structure 3016 * which predated MachineState but had a similar function */ 3017 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3018 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3019 &savevm_htab_handlers, spapr); 3020 3021 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 3022 3023 qemu_register_boot_set(spapr_boot_set, spapr); 3024 3025 /* 3026 * Nothing needs to be done to resume a suspended guest because 3027 * suspending does not change the machine state, so no need for 3028 * a ->wakeup method. 3029 */ 3030 qemu_register_wakeup_support(); 3031 3032 if (kvm_enabled()) { 3033 /* to stop and start vmclock */ 3034 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3035 &spapr->tb); 3036 3037 kvmppc_spapr_enable_inkernel_multitce(); 3038 } 3039 3040 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3041 if (spapr->vof) { 3042 spapr->vof->fw_size = fw_size; /* for claim() on itself */ 3043 spapr_register_hypercall(KVMPPC_H_VOF_CLIENT, spapr_h_vof_client); 3044 } 3045 } 3046 3047 #define DEFAULT_KVM_TYPE "auto" 3048 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3049 { 3050 /* 3051 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to 3052 * accomodate the 'HV' and 'PV' formats that exists in the 3053 * wild. The 'auto' mode is being introduced already as 3054 * lower-case, thus we don't need to bother checking for 3055 * "AUTO". 3056 */ 3057 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) { 3058 return 0; 3059 } 3060 3061 if (!g_ascii_strcasecmp(vm_type, "hv")) { 3062 return 1; 3063 } 3064 3065 if (!g_ascii_strcasecmp(vm_type, "pr")) { 3066 return 2; 3067 } 3068 3069 error_report("Unknown kvm-type specified '%s'", vm_type); 3070 exit(1); 3071 } 3072 3073 /* 3074 * Implementation of an interface to adjust firmware path 3075 * for the bootindex property handling. 3076 */ 3077 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3078 DeviceState *dev) 3079 { 3080 #define CAST(type, obj, name) \ 3081 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3082 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3083 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3084 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3085 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3086 3087 if (d && bus) { 3088 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3089 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3090 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3091 3092 if (spapr) { 3093 /* 3094 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3095 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3096 * 0x8000 | (target << 8) | (bus << 5) | lun 3097 * (see the "Logical unit addressing format" table in SAM5) 3098 */ 3099 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3100 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3101 (uint64_t)id << 48); 3102 } else if (virtio) { 3103 /* 3104 * We use SRP luns of the form 01000000 | (target << 8) | lun 3105 * in the top 32 bits of the 64-bit LUN 3106 * Note: the quote above is from SLOF and it is wrong, 3107 * the actual binding is: 3108 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3109 */ 3110 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3111 if (d->lun >= 256) { 3112 /* Use the LUN "flat space addressing method" */ 3113 id |= 0x4000; 3114 } 3115 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3116 (uint64_t)id << 32); 3117 } else if (usb) { 3118 /* 3119 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3120 * in the top 32 bits of the 64-bit LUN 3121 */ 3122 unsigned usb_port = atoi(usb->port->path); 3123 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3124 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3125 (uint64_t)id << 32); 3126 } 3127 } 3128 3129 /* 3130 * SLOF probes the USB devices, and if it recognizes that the device is a 3131 * storage device, it changes its name to "storage" instead of "usb-host", 3132 * and additionally adds a child node for the SCSI LUN, so the correct 3133 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3134 */ 3135 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3136 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3137 if (usb_device_is_scsi_storage(usbdev)) { 3138 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3139 } 3140 } 3141 3142 if (phb) { 3143 /* Replace "pci" with "pci@800000020000000" */ 3144 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3145 } 3146 3147 if (vsc) { 3148 /* Same logic as virtio above */ 3149 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3150 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3151 } 3152 3153 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3154 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3155 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3156 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3157 } 3158 3159 if (pcidev) { 3160 return spapr_pci_fw_dev_name(pcidev); 3161 } 3162 3163 return NULL; 3164 } 3165 3166 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3167 { 3168 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3169 3170 return g_strdup(spapr->kvm_type); 3171 } 3172 3173 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3174 { 3175 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3176 3177 g_free(spapr->kvm_type); 3178 spapr->kvm_type = g_strdup(value); 3179 } 3180 3181 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3182 { 3183 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3184 3185 return spapr->use_hotplug_event_source; 3186 } 3187 3188 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3189 Error **errp) 3190 { 3191 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3192 3193 spapr->use_hotplug_event_source = value; 3194 } 3195 3196 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3197 { 3198 return true; 3199 } 3200 3201 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3202 { 3203 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3204 3205 switch (spapr->resize_hpt) { 3206 case SPAPR_RESIZE_HPT_DEFAULT: 3207 return g_strdup("default"); 3208 case SPAPR_RESIZE_HPT_DISABLED: 3209 return g_strdup("disabled"); 3210 case SPAPR_RESIZE_HPT_ENABLED: 3211 return g_strdup("enabled"); 3212 case SPAPR_RESIZE_HPT_REQUIRED: 3213 return g_strdup("required"); 3214 } 3215 g_assert_not_reached(); 3216 } 3217 3218 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3219 { 3220 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3221 3222 if (strcmp(value, "default") == 0) { 3223 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3224 } else if (strcmp(value, "disabled") == 0) { 3225 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3226 } else if (strcmp(value, "enabled") == 0) { 3227 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3228 } else if (strcmp(value, "required") == 0) { 3229 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3230 } else { 3231 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3232 } 3233 } 3234 3235 static bool spapr_get_vof(Object *obj, Error **errp) 3236 { 3237 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3238 3239 return spapr->vof != NULL; 3240 } 3241 3242 static void spapr_set_vof(Object *obj, bool value, Error **errp) 3243 { 3244 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3245 3246 if (spapr->vof) { 3247 vof_cleanup(spapr->vof); 3248 g_free(spapr->vof); 3249 spapr->vof = NULL; 3250 } 3251 if (!value) { 3252 return; 3253 } 3254 spapr->vof = g_malloc0(sizeof(*spapr->vof)); 3255 } 3256 3257 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3258 { 3259 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3260 3261 if (spapr->irq == &spapr_irq_xics_legacy) { 3262 return g_strdup("legacy"); 3263 } else if (spapr->irq == &spapr_irq_xics) { 3264 return g_strdup("xics"); 3265 } else if (spapr->irq == &spapr_irq_xive) { 3266 return g_strdup("xive"); 3267 } else if (spapr->irq == &spapr_irq_dual) { 3268 return g_strdup("dual"); 3269 } 3270 g_assert_not_reached(); 3271 } 3272 3273 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3274 { 3275 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3276 3277 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3278 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3279 return; 3280 } 3281 3282 /* The legacy IRQ backend can not be set */ 3283 if (strcmp(value, "xics") == 0) { 3284 spapr->irq = &spapr_irq_xics; 3285 } else if (strcmp(value, "xive") == 0) { 3286 spapr->irq = &spapr_irq_xive; 3287 } else if (strcmp(value, "dual") == 0) { 3288 spapr->irq = &spapr_irq_dual; 3289 } else { 3290 error_setg(errp, "Bad value for \"ic-mode\" property"); 3291 } 3292 } 3293 3294 static char *spapr_get_host_model(Object *obj, Error **errp) 3295 { 3296 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3297 3298 return g_strdup(spapr->host_model); 3299 } 3300 3301 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3302 { 3303 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3304 3305 g_free(spapr->host_model); 3306 spapr->host_model = g_strdup(value); 3307 } 3308 3309 static char *spapr_get_host_serial(Object *obj, Error **errp) 3310 { 3311 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3312 3313 return g_strdup(spapr->host_serial); 3314 } 3315 3316 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3317 { 3318 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3319 3320 g_free(spapr->host_serial); 3321 spapr->host_serial = g_strdup(value); 3322 } 3323 3324 static void spapr_instance_init(Object *obj) 3325 { 3326 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3327 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3328 MachineState *ms = MACHINE(spapr); 3329 MachineClass *mc = MACHINE_GET_CLASS(ms); 3330 3331 /* 3332 * NVDIMM support went live in 5.1 without considering that, in 3333 * other archs, the user needs to enable NVDIMM support with the 3334 * 'nvdimm' machine option and the default behavior is NVDIMM 3335 * support disabled. It is too late to roll back to the standard 3336 * behavior without breaking 5.1 guests. 3337 */ 3338 if (mc->nvdimm_supported) { 3339 ms->nvdimms_state->is_enabled = true; 3340 } 3341 3342 spapr->htab_fd = -1; 3343 spapr->use_hotplug_event_source = true; 3344 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE); 3345 object_property_add_str(obj, "kvm-type", 3346 spapr_get_kvm_type, spapr_set_kvm_type); 3347 object_property_set_description(obj, "kvm-type", 3348 "Specifies the KVM virtualization mode (auto," 3349 " hv, pr). Defaults to 'auto'. This mode will use" 3350 " any available KVM module loaded in the host," 3351 " where kvm_hv takes precedence if both kvm_hv and" 3352 " kvm_pr are loaded."); 3353 object_property_add_bool(obj, "modern-hotplug-events", 3354 spapr_get_modern_hotplug_events, 3355 spapr_set_modern_hotplug_events); 3356 object_property_set_description(obj, "modern-hotplug-events", 3357 "Use dedicated hotplug event mechanism in" 3358 " place of standard EPOW events when possible" 3359 " (required for memory hot-unplug support)"); 3360 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3361 "Maximum permitted CPU compatibility mode"); 3362 3363 object_property_add_str(obj, "resize-hpt", 3364 spapr_get_resize_hpt, spapr_set_resize_hpt); 3365 object_property_set_description(obj, "resize-hpt", 3366 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3367 object_property_add_uint32_ptr(obj, "vsmt", 3368 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3369 object_property_set_description(obj, "vsmt", 3370 "Virtual SMT: KVM behaves as if this were" 3371 " the host's SMT mode"); 3372 3373 object_property_add_bool(obj, "vfio-no-msix-emulation", 3374 spapr_get_msix_emulation, NULL); 3375 3376 object_property_add_uint64_ptr(obj, "kernel-addr", 3377 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3378 object_property_set_description(obj, "kernel-addr", 3379 stringify(KERNEL_LOAD_ADDR) 3380 " for -kernel is the default"); 3381 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3382 3383 object_property_add_bool(obj, "x-vof", spapr_get_vof, spapr_set_vof); 3384 object_property_set_description(obj, "x-vof", 3385 "Enable Virtual Open Firmware (experimental)"); 3386 3387 /* The machine class defines the default interrupt controller mode */ 3388 spapr->irq = smc->irq; 3389 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3390 spapr_set_ic_mode); 3391 object_property_set_description(obj, "ic-mode", 3392 "Specifies the interrupt controller mode (xics, xive, dual)"); 3393 3394 object_property_add_str(obj, "host-model", 3395 spapr_get_host_model, spapr_set_host_model); 3396 object_property_set_description(obj, "host-model", 3397 "Host model to advertise in guest device tree"); 3398 object_property_add_str(obj, "host-serial", 3399 spapr_get_host_serial, spapr_set_host_serial); 3400 object_property_set_description(obj, "host-serial", 3401 "Host serial number to advertise in guest device tree"); 3402 } 3403 3404 static void spapr_machine_finalizefn(Object *obj) 3405 { 3406 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3407 3408 g_free(spapr->kvm_type); 3409 } 3410 3411 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3412 { 3413 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3414 PowerPCCPU *cpu = POWERPC_CPU(cs); 3415 CPUPPCState *env = &cpu->env; 3416 3417 cpu_synchronize_state(cs); 3418 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3419 if (spapr->fwnmi_system_reset_addr != -1) { 3420 uint64_t rtas_addr, addr; 3421 3422 /* get rtas addr from fdt */ 3423 rtas_addr = spapr_get_rtas_addr(); 3424 if (!rtas_addr) { 3425 qemu_system_guest_panicked(NULL); 3426 return; 3427 } 3428 3429 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3430 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3431 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3432 env->gpr[3] = addr; 3433 } 3434 ppc_cpu_do_system_reset(cs); 3435 if (spapr->fwnmi_system_reset_addr != -1) { 3436 env->nip = spapr->fwnmi_system_reset_addr; 3437 } 3438 } 3439 3440 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3441 { 3442 CPUState *cs; 3443 3444 CPU_FOREACH(cs) { 3445 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3446 } 3447 } 3448 3449 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3450 void *fdt, int *fdt_start_offset, Error **errp) 3451 { 3452 uint64_t addr; 3453 uint32_t node; 3454 3455 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3456 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3457 &error_abort); 3458 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3459 SPAPR_MEMORY_BLOCK_SIZE); 3460 return 0; 3461 } 3462 3463 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3464 bool dedicated_hp_event_source) 3465 { 3466 SpaprDrc *drc; 3467 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3468 int i; 3469 uint64_t addr = addr_start; 3470 bool hotplugged = spapr_drc_hotplugged(dev); 3471 3472 for (i = 0; i < nr_lmbs; i++) { 3473 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3474 addr / SPAPR_MEMORY_BLOCK_SIZE); 3475 g_assert(drc); 3476 3477 /* 3478 * memory_device_get_free_addr() provided a range of free addresses 3479 * that doesn't overlap with any existing mapping at pre-plug. The 3480 * corresponding LMB DRCs are thus assumed to be all attachable. 3481 */ 3482 spapr_drc_attach(drc, dev); 3483 if (!hotplugged) { 3484 spapr_drc_reset(drc); 3485 } 3486 addr += SPAPR_MEMORY_BLOCK_SIZE; 3487 } 3488 /* send hotplug notification to the 3489 * guest only in case of hotplugged memory 3490 */ 3491 if (hotplugged) { 3492 if (dedicated_hp_event_source) { 3493 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3494 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3495 g_assert(drc); 3496 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3497 nr_lmbs, 3498 spapr_drc_index(drc)); 3499 } else { 3500 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3501 nr_lmbs); 3502 } 3503 } 3504 } 3505 3506 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3507 { 3508 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3509 PCDIMMDevice *dimm = PC_DIMM(dev); 3510 uint64_t size, addr; 3511 int64_t slot; 3512 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3513 3514 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3515 3516 pc_dimm_plug(dimm, MACHINE(ms)); 3517 3518 if (!is_nvdimm) { 3519 addr = object_property_get_uint(OBJECT(dimm), 3520 PC_DIMM_ADDR_PROP, &error_abort); 3521 spapr_add_lmbs(dev, addr, size, 3522 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT)); 3523 } else { 3524 slot = object_property_get_int(OBJECT(dimm), 3525 PC_DIMM_SLOT_PROP, &error_abort); 3526 /* We should have valid slot number at this point */ 3527 g_assert(slot >= 0); 3528 spapr_add_nvdimm(dev, slot); 3529 } 3530 } 3531 3532 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3533 Error **errp) 3534 { 3535 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3536 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3537 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3538 PCDIMMDevice *dimm = PC_DIMM(dev); 3539 Error *local_err = NULL; 3540 uint64_t size; 3541 Object *memdev; 3542 hwaddr pagesize; 3543 3544 if (!smc->dr_lmb_enabled) { 3545 error_setg(errp, "Memory hotplug not supported for this machine"); 3546 return; 3547 } 3548 3549 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3550 if (local_err) { 3551 error_propagate(errp, local_err); 3552 return; 3553 } 3554 3555 if (is_nvdimm) { 3556 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3557 return; 3558 } 3559 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3560 error_setg(errp, "Hotplugged memory size must be a multiple of " 3561 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3562 return; 3563 } 3564 3565 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3566 &error_abort); 3567 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3568 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3569 return; 3570 } 3571 3572 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3573 } 3574 3575 struct SpaprDimmState { 3576 PCDIMMDevice *dimm; 3577 uint32_t nr_lmbs; 3578 QTAILQ_ENTRY(SpaprDimmState) next; 3579 }; 3580 3581 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3582 PCDIMMDevice *dimm) 3583 { 3584 SpaprDimmState *dimm_state = NULL; 3585 3586 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3587 if (dimm_state->dimm == dimm) { 3588 break; 3589 } 3590 } 3591 return dimm_state; 3592 } 3593 3594 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3595 uint32_t nr_lmbs, 3596 PCDIMMDevice *dimm) 3597 { 3598 SpaprDimmState *ds = NULL; 3599 3600 /* 3601 * If this request is for a DIMM whose removal had failed earlier 3602 * (due to guest's refusal to remove the LMBs), we would have this 3603 * dimm already in the pending_dimm_unplugs list. In that 3604 * case don't add again. 3605 */ 3606 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3607 if (!ds) { 3608 ds = g_malloc0(sizeof(SpaprDimmState)); 3609 ds->nr_lmbs = nr_lmbs; 3610 ds->dimm = dimm; 3611 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3612 } 3613 return ds; 3614 } 3615 3616 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3617 SpaprDimmState *dimm_state) 3618 { 3619 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3620 g_free(dimm_state); 3621 } 3622 3623 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3624 PCDIMMDevice *dimm) 3625 { 3626 SpaprDrc *drc; 3627 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3628 &error_abort); 3629 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3630 uint32_t avail_lmbs = 0; 3631 uint64_t addr_start, addr; 3632 int i; 3633 3634 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3635 &error_abort); 3636 3637 addr = addr_start; 3638 for (i = 0; i < nr_lmbs; i++) { 3639 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3640 addr / SPAPR_MEMORY_BLOCK_SIZE); 3641 g_assert(drc); 3642 if (drc->dev) { 3643 avail_lmbs++; 3644 } 3645 addr += SPAPR_MEMORY_BLOCK_SIZE; 3646 } 3647 3648 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3649 } 3650 3651 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev) 3652 { 3653 SpaprDimmState *ds; 3654 PCDIMMDevice *dimm; 3655 SpaprDrc *drc; 3656 uint32_t nr_lmbs; 3657 uint64_t size, addr_start, addr; 3658 g_autofree char *qapi_error = NULL; 3659 int i; 3660 3661 if (!dev) { 3662 return; 3663 } 3664 3665 dimm = PC_DIMM(dev); 3666 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3667 3668 /* 3669 * 'ds == NULL' would mean that the DIMM doesn't have a pending 3670 * unplug state, but one of its DRC is marked as unplug_requested. 3671 * This is bad and weird enough to g_assert() out. 3672 */ 3673 g_assert(ds); 3674 3675 spapr_pending_dimm_unplugs_remove(spapr, ds); 3676 3677 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3678 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3679 3680 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3681 &error_abort); 3682 3683 addr = addr_start; 3684 for (i = 0; i < nr_lmbs; i++) { 3685 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3686 addr / SPAPR_MEMORY_BLOCK_SIZE); 3687 g_assert(drc); 3688 3689 drc->unplug_requested = false; 3690 addr += SPAPR_MEMORY_BLOCK_SIZE; 3691 } 3692 3693 /* 3694 * Tell QAPI that something happened and the memory 3695 * hotunplug wasn't successful. Keep sending 3696 * MEM_UNPLUG_ERROR even while sending 3697 * DEVICE_UNPLUG_GUEST_ERROR until the deprecation of 3698 * MEM_UNPLUG_ERROR is due. 3699 */ 3700 qapi_error = g_strdup_printf("Memory hotunplug rejected by the guest " 3701 "for device %s", dev->id); 3702 3703 qapi_event_send_mem_unplug_error(dev->id ? : "", qapi_error); 3704 3705 qapi_event_send_device_unplug_guest_error(!!dev->id, dev->id, 3706 dev->canonical_path); 3707 } 3708 3709 /* Callback to be called during DRC release. */ 3710 void spapr_lmb_release(DeviceState *dev) 3711 { 3712 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3713 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3714 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3715 3716 /* This information will get lost if a migration occurs 3717 * during the unplug process. In this case recover it. */ 3718 if (ds == NULL) { 3719 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3720 g_assert(ds); 3721 /* The DRC being examined by the caller at least must be counted */ 3722 g_assert(ds->nr_lmbs); 3723 } 3724 3725 if (--ds->nr_lmbs) { 3726 return; 3727 } 3728 3729 /* 3730 * Now that all the LMBs have been removed by the guest, call the 3731 * unplug handler chain. This can never fail. 3732 */ 3733 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3734 object_unparent(OBJECT(dev)); 3735 } 3736 3737 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3738 { 3739 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3740 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3741 3742 /* We really shouldn't get this far without anything to unplug */ 3743 g_assert(ds); 3744 3745 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3746 qdev_unrealize(dev); 3747 spapr_pending_dimm_unplugs_remove(spapr, ds); 3748 } 3749 3750 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3751 DeviceState *dev, Error **errp) 3752 { 3753 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3754 PCDIMMDevice *dimm = PC_DIMM(dev); 3755 uint32_t nr_lmbs; 3756 uint64_t size, addr_start, addr; 3757 int i; 3758 SpaprDrc *drc; 3759 3760 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3761 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3762 return; 3763 } 3764 3765 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3766 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3767 3768 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3769 &error_abort); 3770 3771 /* 3772 * An existing pending dimm state for this DIMM means that there is an 3773 * unplug operation in progress, waiting for the spapr_lmb_release 3774 * callback to complete the job (BQL can't cover that far). In this case, 3775 * bail out to avoid detaching DRCs that were already released. 3776 */ 3777 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3778 error_setg(errp, "Memory unplug already in progress for device %s", 3779 dev->id); 3780 return; 3781 } 3782 3783 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3784 3785 addr = addr_start; 3786 for (i = 0; i < nr_lmbs; i++) { 3787 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3788 addr / SPAPR_MEMORY_BLOCK_SIZE); 3789 g_assert(drc); 3790 3791 spapr_drc_unplug_request(drc); 3792 addr += SPAPR_MEMORY_BLOCK_SIZE; 3793 } 3794 3795 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3796 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3797 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3798 nr_lmbs, spapr_drc_index(drc)); 3799 } 3800 3801 /* Callback to be called during DRC release. */ 3802 void spapr_core_release(DeviceState *dev) 3803 { 3804 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3805 3806 /* Call the unplug handler chain. This can never fail. */ 3807 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3808 object_unparent(OBJECT(dev)); 3809 } 3810 3811 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3812 { 3813 MachineState *ms = MACHINE(hotplug_dev); 3814 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3815 CPUCore *cc = CPU_CORE(dev); 3816 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3817 3818 if (smc->pre_2_10_has_unused_icps) { 3819 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3820 int i; 3821 3822 for (i = 0; i < cc->nr_threads; i++) { 3823 CPUState *cs = CPU(sc->threads[i]); 3824 3825 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3826 } 3827 } 3828 3829 assert(core_slot); 3830 core_slot->cpu = NULL; 3831 qdev_unrealize(dev); 3832 } 3833 3834 static 3835 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3836 Error **errp) 3837 { 3838 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3839 int index; 3840 SpaprDrc *drc; 3841 CPUCore *cc = CPU_CORE(dev); 3842 3843 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3844 error_setg(errp, "Unable to find CPU core with core-id: %d", 3845 cc->core_id); 3846 return; 3847 } 3848 if (index == 0) { 3849 error_setg(errp, "Boot CPU core may not be unplugged"); 3850 return; 3851 } 3852 3853 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3854 spapr_vcpu_id(spapr, cc->core_id)); 3855 g_assert(drc); 3856 3857 if (!spapr_drc_unplug_requested(drc)) { 3858 spapr_drc_unplug_request(drc); 3859 } 3860 3861 /* 3862 * spapr_hotplug_req_remove_by_index is left unguarded, out of the 3863 * "!spapr_drc_unplug_requested" check, to allow for multiple IRQ 3864 * pulses removing the same CPU. Otherwise, in an failed hotunplug 3865 * attempt (e.g. the kernel will refuse to remove the last online 3866 * CPU), we will never attempt it again because unplug_requested 3867 * will still be 'true' in that case. 3868 */ 3869 spapr_hotplug_req_remove_by_index(drc); 3870 } 3871 3872 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3873 void *fdt, int *fdt_start_offset, Error **errp) 3874 { 3875 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3876 CPUState *cs = CPU(core->threads[0]); 3877 PowerPCCPU *cpu = POWERPC_CPU(cs); 3878 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3879 int id = spapr_get_vcpu_id(cpu); 3880 g_autofree char *nodename = NULL; 3881 int offset; 3882 3883 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3884 offset = fdt_add_subnode(fdt, 0, nodename); 3885 3886 spapr_dt_cpu(cs, fdt, offset, spapr); 3887 3888 /* 3889 * spapr_dt_cpu() does not fill the 'name' property in the 3890 * CPU node. The function is called during boot process, before 3891 * and after CAS, and overwriting the 'name' property written 3892 * by SLOF is not allowed. 3893 * 3894 * Write it manually after spapr_dt_cpu(). This makes the hotplug 3895 * CPUs more compatible with the coldplugged ones, which have 3896 * the 'name' property. Linux Kernel also relies on this 3897 * property to identify CPU nodes. 3898 */ 3899 _FDT((fdt_setprop_string(fdt, offset, "name", nodename))); 3900 3901 *fdt_start_offset = offset; 3902 return 0; 3903 } 3904 3905 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3906 { 3907 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3908 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3909 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3910 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3911 CPUCore *cc = CPU_CORE(dev); 3912 CPUState *cs; 3913 SpaprDrc *drc; 3914 CPUArchId *core_slot; 3915 int index; 3916 bool hotplugged = spapr_drc_hotplugged(dev); 3917 int i; 3918 3919 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3920 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */ 3921 3922 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3923 spapr_vcpu_id(spapr, cc->core_id)); 3924 3925 g_assert(drc || !mc->has_hotpluggable_cpus); 3926 3927 if (drc) { 3928 /* 3929 * spapr_core_pre_plug() already buys us this is a brand new 3930 * core being plugged into a free slot. Nothing should already 3931 * be attached to the corresponding DRC. 3932 */ 3933 spapr_drc_attach(drc, dev); 3934 3935 if (hotplugged) { 3936 /* 3937 * Send hotplug notification interrupt to the guest only 3938 * in case of hotplugged CPUs. 3939 */ 3940 spapr_hotplug_req_add_by_index(drc); 3941 } else { 3942 spapr_drc_reset(drc); 3943 } 3944 } 3945 3946 core_slot->cpu = OBJECT(dev); 3947 3948 /* 3949 * Set compatibility mode to match the boot CPU, which was either set 3950 * by the machine reset code or by CAS. This really shouldn't fail at 3951 * this point. 3952 */ 3953 if (hotplugged) { 3954 for (i = 0; i < cc->nr_threads; i++) { 3955 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3956 &error_abort); 3957 } 3958 } 3959 3960 if (smc->pre_2_10_has_unused_icps) { 3961 for (i = 0; i < cc->nr_threads; i++) { 3962 cs = CPU(core->threads[i]); 3963 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3964 } 3965 } 3966 } 3967 3968 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3969 Error **errp) 3970 { 3971 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3972 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3973 CPUCore *cc = CPU_CORE(dev); 3974 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3975 const char *type = object_get_typename(OBJECT(dev)); 3976 CPUArchId *core_slot; 3977 int index; 3978 unsigned int smp_threads = machine->smp.threads; 3979 3980 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3981 error_setg(errp, "CPU hotplug not supported for this machine"); 3982 return; 3983 } 3984 3985 if (strcmp(base_core_type, type)) { 3986 error_setg(errp, "CPU core type should be %s", base_core_type); 3987 return; 3988 } 3989 3990 if (cc->core_id % smp_threads) { 3991 error_setg(errp, "invalid core id %d", cc->core_id); 3992 return; 3993 } 3994 3995 /* 3996 * In general we should have homogeneous threads-per-core, but old 3997 * (pre hotplug support) machine types allow the last core to have 3998 * reduced threads as a compatibility hack for when we allowed 3999 * total vcpus not a multiple of threads-per-core. 4000 */ 4001 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 4002 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 4003 smp_threads); 4004 return; 4005 } 4006 4007 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 4008 if (!core_slot) { 4009 error_setg(errp, "core id %d out of range", cc->core_id); 4010 return; 4011 } 4012 4013 if (core_slot->cpu) { 4014 error_setg(errp, "core %d already populated", cc->core_id); 4015 return; 4016 } 4017 4018 numa_cpu_pre_plug(core_slot, dev, errp); 4019 } 4020 4021 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 4022 void *fdt, int *fdt_start_offset, Error **errp) 4023 { 4024 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 4025 int intc_phandle; 4026 4027 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 4028 if (intc_phandle <= 0) { 4029 return -1; 4030 } 4031 4032 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 4033 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 4034 return -1; 4035 } 4036 4037 /* generally SLOF creates these, for hotplug it's up to QEMU */ 4038 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 4039 4040 return 0; 4041 } 4042 4043 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4044 Error **errp) 4045 { 4046 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4047 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4048 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4049 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 4050 SpaprDrc *drc; 4051 4052 if (dev->hotplugged && !smc->dr_phb_enabled) { 4053 error_setg(errp, "PHB hotplug not supported for this machine"); 4054 return false; 4055 } 4056 4057 if (sphb->index == (uint32_t)-1) { 4058 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 4059 return false; 4060 } 4061 4062 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4063 if (drc && drc->dev) { 4064 error_setg(errp, "PHB %d already attached", sphb->index); 4065 return false; 4066 } 4067 4068 /* 4069 * This will check that sphb->index doesn't exceed the maximum number of 4070 * PHBs for the current machine type. 4071 */ 4072 return 4073 smc->phb_placement(spapr, sphb->index, 4074 &sphb->buid, &sphb->io_win_addr, 4075 &sphb->mem_win_addr, &sphb->mem64_win_addr, 4076 windows_supported, sphb->dma_liobn, 4077 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 4078 errp); 4079 } 4080 4081 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4082 { 4083 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4084 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4085 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4086 SpaprDrc *drc; 4087 bool hotplugged = spapr_drc_hotplugged(dev); 4088 4089 if (!smc->dr_phb_enabled) { 4090 return; 4091 } 4092 4093 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4094 /* hotplug hooks should check it's enabled before getting this far */ 4095 assert(drc); 4096 4097 /* spapr_phb_pre_plug() already checked the DRC is attachable */ 4098 spapr_drc_attach(drc, dev); 4099 4100 if (hotplugged) { 4101 spapr_hotplug_req_add_by_index(drc); 4102 } else { 4103 spapr_drc_reset(drc); 4104 } 4105 } 4106 4107 void spapr_phb_release(DeviceState *dev) 4108 { 4109 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4110 4111 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4112 object_unparent(OBJECT(dev)); 4113 } 4114 4115 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4116 { 4117 qdev_unrealize(dev); 4118 } 4119 4120 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4121 DeviceState *dev, Error **errp) 4122 { 4123 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4124 SpaprDrc *drc; 4125 4126 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4127 assert(drc); 4128 4129 if (!spapr_drc_unplug_requested(drc)) { 4130 spapr_drc_unplug_request(drc); 4131 spapr_hotplug_req_remove_by_index(drc); 4132 } else { 4133 error_setg(errp, 4134 "PCI Host Bridge unplug already in progress for device %s", 4135 dev->id); 4136 } 4137 } 4138 4139 static 4140 bool spapr_tpm_proxy_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4141 Error **errp) 4142 { 4143 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4144 4145 if (spapr->tpm_proxy != NULL) { 4146 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4147 return false; 4148 } 4149 4150 return true; 4151 } 4152 4153 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4154 { 4155 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4156 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4157 4158 /* Already checked in spapr_tpm_proxy_pre_plug() */ 4159 g_assert(spapr->tpm_proxy == NULL); 4160 4161 spapr->tpm_proxy = tpm_proxy; 4162 } 4163 4164 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4165 { 4166 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4167 4168 qdev_unrealize(dev); 4169 object_unparent(OBJECT(dev)); 4170 spapr->tpm_proxy = NULL; 4171 } 4172 4173 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4174 DeviceState *dev, Error **errp) 4175 { 4176 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4177 spapr_memory_plug(hotplug_dev, dev); 4178 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4179 spapr_core_plug(hotplug_dev, dev); 4180 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4181 spapr_phb_plug(hotplug_dev, dev); 4182 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4183 spapr_tpm_proxy_plug(hotplug_dev, dev); 4184 } 4185 } 4186 4187 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4188 DeviceState *dev, Error **errp) 4189 { 4190 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4191 spapr_memory_unplug(hotplug_dev, dev); 4192 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4193 spapr_core_unplug(hotplug_dev, dev); 4194 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4195 spapr_phb_unplug(hotplug_dev, dev); 4196 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4197 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4198 } 4199 } 4200 4201 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr) 4202 { 4203 return spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT) || 4204 /* 4205 * CAS will process all pending unplug requests. 4206 * 4207 * HACK: a guest could theoretically have cleared all bits in OV5, 4208 * but none of the guests we care for do. 4209 */ 4210 spapr_ovec_empty(spapr->ov5_cas); 4211 } 4212 4213 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4214 DeviceState *dev, Error **errp) 4215 { 4216 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4217 MachineClass *mc = MACHINE_GET_CLASS(sms); 4218 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4219 4220 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4221 if (spapr_memory_hot_unplug_supported(sms)) { 4222 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4223 } else { 4224 error_setg(errp, "Memory hot unplug not supported for this guest"); 4225 } 4226 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4227 if (!mc->has_hotpluggable_cpus) { 4228 error_setg(errp, "CPU hot unplug not supported on this machine"); 4229 return; 4230 } 4231 spapr_core_unplug_request(hotplug_dev, dev, errp); 4232 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4233 if (!smc->dr_phb_enabled) { 4234 error_setg(errp, "PHB hot unplug not supported on this machine"); 4235 return; 4236 } 4237 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4238 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4239 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4240 } 4241 } 4242 4243 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4244 DeviceState *dev, Error **errp) 4245 { 4246 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4247 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4248 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4249 spapr_core_pre_plug(hotplug_dev, dev, errp); 4250 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4251 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4252 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4253 spapr_tpm_proxy_pre_plug(hotplug_dev, dev, errp); 4254 } 4255 } 4256 4257 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4258 DeviceState *dev) 4259 { 4260 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4261 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4262 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4263 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4264 return HOTPLUG_HANDLER(machine); 4265 } 4266 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4267 PCIDevice *pcidev = PCI_DEVICE(dev); 4268 PCIBus *root = pci_device_root_bus(pcidev); 4269 SpaprPhbState *phb = 4270 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4271 TYPE_SPAPR_PCI_HOST_BRIDGE); 4272 4273 if (phb) { 4274 return HOTPLUG_HANDLER(phb); 4275 } 4276 } 4277 return NULL; 4278 } 4279 4280 static CpuInstanceProperties 4281 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4282 { 4283 CPUArchId *core_slot; 4284 MachineClass *mc = MACHINE_GET_CLASS(machine); 4285 4286 /* make sure possible_cpu are intialized */ 4287 mc->possible_cpu_arch_ids(machine); 4288 /* get CPU core slot containing thread that matches cpu_index */ 4289 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4290 assert(core_slot); 4291 return core_slot->props; 4292 } 4293 4294 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4295 { 4296 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4297 } 4298 4299 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4300 { 4301 int i; 4302 unsigned int smp_threads = machine->smp.threads; 4303 unsigned int smp_cpus = machine->smp.cpus; 4304 const char *core_type; 4305 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4306 MachineClass *mc = MACHINE_GET_CLASS(machine); 4307 4308 if (!mc->has_hotpluggable_cpus) { 4309 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4310 } 4311 if (machine->possible_cpus) { 4312 assert(machine->possible_cpus->len == spapr_max_cores); 4313 return machine->possible_cpus; 4314 } 4315 4316 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4317 if (!core_type) { 4318 error_report("Unable to find sPAPR CPU Core definition"); 4319 exit(1); 4320 } 4321 4322 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4323 sizeof(CPUArchId) * spapr_max_cores); 4324 machine->possible_cpus->len = spapr_max_cores; 4325 for (i = 0; i < machine->possible_cpus->len; i++) { 4326 int core_id = i * smp_threads; 4327 4328 machine->possible_cpus->cpus[i].type = core_type; 4329 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4330 machine->possible_cpus->cpus[i].arch_id = core_id; 4331 machine->possible_cpus->cpus[i].props.has_core_id = true; 4332 machine->possible_cpus->cpus[i].props.core_id = core_id; 4333 } 4334 return machine->possible_cpus; 4335 } 4336 4337 static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4338 uint64_t *buid, hwaddr *pio, 4339 hwaddr *mmio32, hwaddr *mmio64, 4340 unsigned n_dma, uint32_t *liobns, 4341 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4342 { 4343 /* 4344 * New-style PHB window placement. 4345 * 4346 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4347 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4348 * windows. 4349 * 4350 * Some guest kernels can't work with MMIO windows above 1<<46 4351 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4352 * 4353 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4354 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4355 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4356 * 1TiB 64-bit MMIO windows for each PHB. 4357 */ 4358 const uint64_t base_buid = 0x800000020000000ULL; 4359 int i; 4360 4361 /* Sanity check natural alignments */ 4362 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4363 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4364 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4365 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4366 /* Sanity check bounds */ 4367 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4368 SPAPR_PCI_MEM32_WIN_SIZE); 4369 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4370 SPAPR_PCI_MEM64_WIN_SIZE); 4371 4372 if (index >= SPAPR_MAX_PHBS) { 4373 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4374 SPAPR_MAX_PHBS - 1); 4375 return false; 4376 } 4377 4378 *buid = base_buid + index; 4379 for (i = 0; i < n_dma; ++i) { 4380 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4381 } 4382 4383 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4384 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4385 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4386 4387 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4388 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4389 return true; 4390 } 4391 4392 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4393 { 4394 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4395 4396 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4397 } 4398 4399 static void spapr_ics_resend(XICSFabric *dev) 4400 { 4401 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4402 4403 ics_resend(spapr->ics); 4404 } 4405 4406 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4407 { 4408 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4409 4410 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4411 } 4412 4413 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4414 Monitor *mon) 4415 { 4416 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4417 4418 spapr_irq_print_info(spapr, mon); 4419 monitor_printf(mon, "irqchip: %s\n", 4420 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4421 } 4422 4423 /* 4424 * This is a XIVE only operation 4425 */ 4426 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4427 uint8_t nvt_blk, uint32_t nvt_idx, 4428 bool cam_ignore, uint8_t priority, 4429 uint32_t logic_serv, XiveTCTXMatch *match) 4430 { 4431 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4432 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4433 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4434 int count; 4435 4436 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4437 priority, logic_serv, match); 4438 if (count < 0) { 4439 return count; 4440 } 4441 4442 /* 4443 * When we implement the save and restore of the thread interrupt 4444 * contexts in the enter/exit CPU handlers of the machine and the 4445 * escalations in QEMU, we should be able to handle non dispatched 4446 * vCPUs. 4447 * 4448 * Until this is done, the sPAPR machine should find at least one 4449 * matching context always. 4450 */ 4451 if (count == 0) { 4452 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4453 nvt_blk, nvt_idx); 4454 } 4455 4456 return count; 4457 } 4458 4459 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4460 { 4461 return cpu->vcpu_id; 4462 } 4463 4464 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4465 { 4466 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4467 MachineState *ms = MACHINE(spapr); 4468 int vcpu_id; 4469 4470 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4471 4472 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4473 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4474 error_append_hint(errp, "Adjust the number of cpus to %d " 4475 "or try to raise the number of threads per core\n", 4476 vcpu_id * ms->smp.threads / spapr->vsmt); 4477 return false; 4478 } 4479 4480 cpu->vcpu_id = vcpu_id; 4481 return true; 4482 } 4483 4484 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4485 { 4486 CPUState *cs; 4487 4488 CPU_FOREACH(cs) { 4489 PowerPCCPU *cpu = POWERPC_CPU(cs); 4490 4491 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4492 return cpu; 4493 } 4494 } 4495 4496 return NULL; 4497 } 4498 4499 static bool spapr_cpu_in_nested(PowerPCCPU *cpu) 4500 { 4501 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4502 4503 return spapr_cpu->in_nested; 4504 } 4505 4506 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4507 { 4508 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4509 4510 /* These are only called by TCG, KVM maintains dispatch state */ 4511 4512 spapr_cpu->prod = false; 4513 if (spapr_cpu->vpa_addr) { 4514 CPUState *cs = CPU(cpu); 4515 uint32_t dispatch; 4516 4517 dispatch = ldl_be_phys(cs->as, 4518 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4519 dispatch++; 4520 if ((dispatch & 1) != 0) { 4521 qemu_log_mask(LOG_GUEST_ERROR, 4522 "VPA: incorrect dispatch counter value for " 4523 "dispatched partition %u, correcting.\n", dispatch); 4524 dispatch++; 4525 } 4526 stl_be_phys(cs->as, 4527 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4528 } 4529 } 4530 4531 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4532 { 4533 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4534 4535 if (spapr_cpu->vpa_addr) { 4536 CPUState *cs = CPU(cpu); 4537 uint32_t dispatch; 4538 4539 dispatch = ldl_be_phys(cs->as, 4540 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4541 dispatch++; 4542 if ((dispatch & 1) != 1) { 4543 qemu_log_mask(LOG_GUEST_ERROR, 4544 "VPA: incorrect dispatch counter value for " 4545 "preempted partition %u, correcting.\n", dispatch); 4546 dispatch++; 4547 } 4548 stl_be_phys(cs->as, 4549 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4550 } 4551 } 4552 4553 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4554 { 4555 MachineClass *mc = MACHINE_CLASS(oc); 4556 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4557 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4558 NMIClass *nc = NMI_CLASS(oc); 4559 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4560 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4561 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4562 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4563 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4564 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc); 4565 4566 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4567 mc->ignore_boot_device_suffixes = true; 4568 4569 /* 4570 * We set up the default / latest behaviour here. The class_init 4571 * functions for the specific versioned machine types can override 4572 * these details for backwards compatibility 4573 */ 4574 mc->init = spapr_machine_init; 4575 mc->reset = spapr_machine_reset; 4576 mc->block_default_type = IF_SCSI; 4577 4578 /* 4579 * Setting max_cpus to INT32_MAX. Both KVM and TCG max_cpus values 4580 * should be limited by the host capability instead of hardcoded. 4581 * max_cpus for KVM guests will be checked in kvm_init(), and TCG 4582 * guests are welcome to have as many CPUs as the host are capable 4583 * of emulate. 4584 */ 4585 mc->max_cpus = INT32_MAX; 4586 4587 mc->no_parallel = 1; 4588 mc->default_boot_order = ""; 4589 mc->default_ram_size = 512 * MiB; 4590 mc->default_ram_id = "ppc_spapr.ram"; 4591 mc->default_display = "std"; 4592 mc->kvm_type = spapr_kvm_type; 4593 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4594 mc->pci_allow_0_address = true; 4595 assert(!mc->get_hotplug_handler); 4596 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4597 hc->pre_plug = spapr_machine_device_pre_plug; 4598 hc->plug = spapr_machine_device_plug; 4599 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4600 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4601 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4602 hc->unplug_request = spapr_machine_device_unplug_request; 4603 hc->unplug = spapr_machine_device_unplug; 4604 4605 smc->dr_lmb_enabled = true; 4606 smc->update_dt_enabled = true; 4607 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4608 mc->has_hotpluggable_cpus = true; 4609 mc->nvdimm_supported = true; 4610 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4611 fwc->get_dev_path = spapr_get_fw_dev_path; 4612 nc->nmi_monitor_handler = spapr_nmi; 4613 smc->phb_placement = spapr_phb_placement; 4614 vhc->cpu_in_nested = spapr_cpu_in_nested; 4615 vhc->deliver_hv_excp = spapr_exit_nested; 4616 vhc->hypercall = emulate_spapr_hypercall; 4617 vhc->hpt_mask = spapr_hpt_mask; 4618 vhc->map_hptes = spapr_map_hptes; 4619 vhc->unmap_hptes = spapr_unmap_hptes; 4620 vhc->hpte_set_c = spapr_hpte_set_c; 4621 vhc->hpte_set_r = spapr_hpte_set_r; 4622 vhc->get_pate = spapr_get_pate; 4623 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4624 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4625 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4626 xic->ics_get = spapr_ics_get; 4627 xic->ics_resend = spapr_ics_resend; 4628 xic->icp_get = spapr_icp_get; 4629 ispc->print_info = spapr_pic_print_info; 4630 /* Force NUMA node memory size to be a multiple of 4631 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4632 * in which LMBs are represented and hot-added 4633 */ 4634 mc->numa_mem_align_shift = 28; 4635 mc->auto_enable_numa = true; 4636 4637 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4638 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4639 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4640 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4641 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4642 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4643 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4644 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4645 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4646 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4647 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4648 smc->default_caps.caps[SPAPR_CAP_RPT_INVALIDATE] = SPAPR_CAP_OFF; 4649 spapr_caps_add_properties(smc); 4650 smc->irq = &spapr_irq_dual; 4651 smc->dr_phb_enabled = true; 4652 smc->linux_pci_probe = true; 4653 smc->smp_threads_vsmt = true; 4654 smc->nr_xirqs = SPAPR_NR_XIRQS; 4655 xfc->match_nvt = spapr_match_nvt; 4656 vmc->client_architecture_support = spapr_vof_client_architecture_support; 4657 vmc->quiesce = spapr_vof_quiesce; 4658 vmc->setprop = spapr_vof_setprop; 4659 } 4660 4661 static const TypeInfo spapr_machine_info = { 4662 .name = TYPE_SPAPR_MACHINE, 4663 .parent = TYPE_MACHINE, 4664 .abstract = true, 4665 .instance_size = sizeof(SpaprMachineState), 4666 .instance_init = spapr_instance_init, 4667 .instance_finalize = spapr_machine_finalizefn, 4668 .class_size = sizeof(SpaprMachineClass), 4669 .class_init = spapr_machine_class_init, 4670 .interfaces = (InterfaceInfo[]) { 4671 { TYPE_FW_PATH_PROVIDER }, 4672 { TYPE_NMI }, 4673 { TYPE_HOTPLUG_HANDLER }, 4674 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4675 { TYPE_XICS_FABRIC }, 4676 { TYPE_INTERRUPT_STATS_PROVIDER }, 4677 { TYPE_XIVE_FABRIC }, 4678 { TYPE_VOF_MACHINE_IF }, 4679 { } 4680 }, 4681 }; 4682 4683 static void spapr_machine_latest_class_options(MachineClass *mc) 4684 { 4685 mc->alias = "pseries"; 4686 mc->is_default = true; 4687 } 4688 4689 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4690 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4691 void *data) \ 4692 { \ 4693 MachineClass *mc = MACHINE_CLASS(oc); \ 4694 spapr_machine_##suffix##_class_options(mc); \ 4695 if (latest) { \ 4696 spapr_machine_latest_class_options(mc); \ 4697 } \ 4698 } \ 4699 static const TypeInfo spapr_machine_##suffix##_info = { \ 4700 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4701 .parent = TYPE_SPAPR_MACHINE, \ 4702 .class_init = spapr_machine_##suffix##_class_init, \ 4703 }; \ 4704 static void spapr_machine_register_##suffix(void) \ 4705 { \ 4706 type_register(&spapr_machine_##suffix##_info); \ 4707 } \ 4708 type_init(spapr_machine_register_##suffix) 4709 4710 /* 4711 * pseries-7.0 4712 */ 4713 static void spapr_machine_7_0_class_options(MachineClass *mc) 4714 { 4715 /* Defaults for the latest behaviour inherited from the base class */ 4716 } 4717 4718 DEFINE_SPAPR_MACHINE(7_0, "7.0", true); 4719 4720 /* 4721 * pseries-6.2 4722 */ 4723 static void spapr_machine_6_2_class_options(MachineClass *mc) 4724 { 4725 spapr_machine_7_0_class_options(mc); 4726 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 4727 } 4728 4729 DEFINE_SPAPR_MACHINE(6_2, "6.2", false); 4730 4731 /* 4732 * pseries-6.1 4733 */ 4734 static void spapr_machine_6_1_class_options(MachineClass *mc) 4735 { 4736 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4737 4738 spapr_machine_6_2_class_options(mc); 4739 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 4740 smc->pre_6_2_numa_affinity = true; 4741 mc->smp_props.prefer_sockets = true; 4742 } 4743 4744 DEFINE_SPAPR_MACHINE(6_1, "6.1", false); 4745 4746 /* 4747 * pseries-6.0 4748 */ 4749 static void spapr_machine_6_0_class_options(MachineClass *mc) 4750 { 4751 spapr_machine_6_1_class_options(mc); 4752 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 4753 } 4754 4755 DEFINE_SPAPR_MACHINE(6_0, "6.0", false); 4756 4757 /* 4758 * pseries-5.2 4759 */ 4760 static void spapr_machine_5_2_class_options(MachineClass *mc) 4761 { 4762 spapr_machine_6_0_class_options(mc); 4763 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 4764 } 4765 4766 DEFINE_SPAPR_MACHINE(5_2, "5.2", false); 4767 4768 /* 4769 * pseries-5.1 4770 */ 4771 static void spapr_machine_5_1_class_options(MachineClass *mc) 4772 { 4773 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4774 4775 spapr_machine_5_2_class_options(mc); 4776 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4777 smc->pre_5_2_numa_associativity = true; 4778 } 4779 4780 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4781 4782 /* 4783 * pseries-5.0 4784 */ 4785 static void spapr_machine_5_0_class_options(MachineClass *mc) 4786 { 4787 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4788 static GlobalProperty compat[] = { 4789 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4790 }; 4791 4792 spapr_machine_5_1_class_options(mc); 4793 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4794 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4795 mc->numa_mem_supported = true; 4796 smc->pre_5_1_assoc_refpoints = true; 4797 } 4798 4799 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4800 4801 /* 4802 * pseries-4.2 4803 */ 4804 static void spapr_machine_4_2_class_options(MachineClass *mc) 4805 { 4806 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4807 4808 spapr_machine_5_0_class_options(mc); 4809 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4810 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4811 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4812 smc->rma_limit = 16 * GiB; 4813 mc->nvdimm_supported = false; 4814 } 4815 4816 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4817 4818 /* 4819 * pseries-4.1 4820 */ 4821 static void spapr_machine_4_1_class_options(MachineClass *mc) 4822 { 4823 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4824 static GlobalProperty compat[] = { 4825 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4826 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4827 }; 4828 4829 spapr_machine_4_2_class_options(mc); 4830 smc->linux_pci_probe = false; 4831 smc->smp_threads_vsmt = false; 4832 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4833 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4834 } 4835 4836 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4837 4838 /* 4839 * pseries-4.0 4840 */ 4841 static bool phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4842 uint64_t *buid, hwaddr *pio, 4843 hwaddr *mmio32, hwaddr *mmio64, 4844 unsigned n_dma, uint32_t *liobns, 4845 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4846 { 4847 if (!spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, 4848 liobns, nv2gpa, nv2atsd, errp)) { 4849 return false; 4850 } 4851 4852 *nv2gpa = 0; 4853 *nv2atsd = 0; 4854 return true; 4855 } 4856 static void spapr_machine_4_0_class_options(MachineClass *mc) 4857 { 4858 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4859 4860 spapr_machine_4_1_class_options(mc); 4861 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4862 smc->phb_placement = phb_placement_4_0; 4863 smc->irq = &spapr_irq_xics; 4864 smc->pre_4_1_migration = true; 4865 } 4866 4867 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4868 4869 /* 4870 * pseries-3.1 4871 */ 4872 static void spapr_machine_3_1_class_options(MachineClass *mc) 4873 { 4874 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4875 4876 spapr_machine_4_0_class_options(mc); 4877 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4878 4879 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4880 smc->update_dt_enabled = false; 4881 smc->dr_phb_enabled = false; 4882 smc->broken_host_serial_model = true; 4883 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4884 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4885 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4886 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4887 } 4888 4889 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4890 4891 /* 4892 * pseries-3.0 4893 */ 4894 4895 static void spapr_machine_3_0_class_options(MachineClass *mc) 4896 { 4897 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4898 4899 spapr_machine_3_1_class_options(mc); 4900 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4901 4902 smc->legacy_irq_allocation = true; 4903 smc->nr_xirqs = 0x400; 4904 smc->irq = &spapr_irq_xics_legacy; 4905 } 4906 4907 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4908 4909 /* 4910 * pseries-2.12 4911 */ 4912 static void spapr_machine_2_12_class_options(MachineClass *mc) 4913 { 4914 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4915 static GlobalProperty compat[] = { 4916 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4917 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4918 }; 4919 4920 spapr_machine_3_0_class_options(mc); 4921 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4922 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4923 4924 /* We depend on kvm_enabled() to choose a default value for the 4925 * hpt-max-page-size capability. Of course we can't do it here 4926 * because this is too early and the HW accelerator isn't initialzed 4927 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4928 */ 4929 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4930 } 4931 4932 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4933 4934 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4935 { 4936 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4937 4938 spapr_machine_2_12_class_options(mc); 4939 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4940 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4941 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4942 } 4943 4944 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4945 4946 /* 4947 * pseries-2.11 4948 */ 4949 4950 static void spapr_machine_2_11_class_options(MachineClass *mc) 4951 { 4952 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4953 4954 spapr_machine_2_12_class_options(mc); 4955 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4956 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4957 } 4958 4959 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4960 4961 /* 4962 * pseries-2.10 4963 */ 4964 4965 static void spapr_machine_2_10_class_options(MachineClass *mc) 4966 { 4967 spapr_machine_2_11_class_options(mc); 4968 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4969 } 4970 4971 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4972 4973 /* 4974 * pseries-2.9 4975 */ 4976 4977 static void spapr_machine_2_9_class_options(MachineClass *mc) 4978 { 4979 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4980 static GlobalProperty compat[] = { 4981 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4982 }; 4983 4984 spapr_machine_2_10_class_options(mc); 4985 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4986 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4987 smc->pre_2_10_has_unused_icps = true; 4988 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4989 } 4990 4991 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4992 4993 /* 4994 * pseries-2.8 4995 */ 4996 4997 static void spapr_machine_2_8_class_options(MachineClass *mc) 4998 { 4999 static GlobalProperty compat[] = { 5000 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 5001 }; 5002 5003 spapr_machine_2_9_class_options(mc); 5004 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 5005 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5006 mc->numa_mem_align_shift = 23; 5007 } 5008 5009 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 5010 5011 /* 5012 * pseries-2.7 5013 */ 5014 5015 static bool phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 5016 uint64_t *buid, hwaddr *pio, 5017 hwaddr *mmio32, hwaddr *mmio64, 5018 unsigned n_dma, uint32_t *liobns, 5019 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 5020 { 5021 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 5022 const uint64_t base_buid = 0x800000020000000ULL; 5023 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 5024 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 5025 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 5026 const uint32_t max_index = 255; 5027 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 5028 5029 uint64_t ram_top = MACHINE(spapr)->ram_size; 5030 hwaddr phb0_base, phb_base; 5031 int i; 5032 5033 /* Do we have device memory? */ 5034 if (MACHINE(spapr)->maxram_size > ram_top) { 5035 /* Can't just use maxram_size, because there may be an 5036 * alignment gap between normal and device memory regions 5037 */ 5038 ram_top = MACHINE(spapr)->device_memory->base + 5039 memory_region_size(&MACHINE(spapr)->device_memory->mr); 5040 } 5041 5042 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 5043 5044 if (index > max_index) { 5045 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 5046 max_index); 5047 return false; 5048 } 5049 5050 *buid = base_buid + index; 5051 for (i = 0; i < n_dma; ++i) { 5052 liobns[i] = SPAPR_PCI_LIOBN(index, i); 5053 } 5054 5055 phb_base = phb0_base + index * phb_spacing; 5056 *pio = phb_base + pio_offset; 5057 *mmio32 = phb_base + mmio_offset; 5058 /* 5059 * We don't set the 64-bit MMIO window, relying on the PHB's 5060 * fallback behaviour of automatically splitting a large "32-bit" 5061 * window into contiguous 32-bit and 64-bit windows 5062 */ 5063 5064 *nv2gpa = 0; 5065 *nv2atsd = 0; 5066 return true; 5067 } 5068 5069 static void spapr_machine_2_7_class_options(MachineClass *mc) 5070 { 5071 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5072 static GlobalProperty compat[] = { 5073 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 5074 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 5075 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 5076 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 5077 }; 5078 5079 spapr_machine_2_8_class_options(mc); 5080 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 5081 mc->default_machine_opts = "modern-hotplug-events=off"; 5082 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 5083 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5084 smc->phb_placement = phb_placement_2_7; 5085 } 5086 5087 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 5088 5089 /* 5090 * pseries-2.6 5091 */ 5092 5093 static void spapr_machine_2_6_class_options(MachineClass *mc) 5094 { 5095 static GlobalProperty compat[] = { 5096 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 5097 }; 5098 5099 spapr_machine_2_7_class_options(mc); 5100 mc->has_hotpluggable_cpus = false; 5101 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 5102 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5103 } 5104 5105 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 5106 5107 /* 5108 * pseries-2.5 5109 */ 5110 5111 static void spapr_machine_2_5_class_options(MachineClass *mc) 5112 { 5113 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5114 static GlobalProperty compat[] = { 5115 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 5116 }; 5117 5118 spapr_machine_2_6_class_options(mc); 5119 smc->use_ohci_by_default = true; 5120 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 5121 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5122 } 5123 5124 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 5125 5126 /* 5127 * pseries-2.4 5128 */ 5129 5130 static void spapr_machine_2_4_class_options(MachineClass *mc) 5131 { 5132 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5133 5134 spapr_machine_2_5_class_options(mc); 5135 smc->dr_lmb_enabled = false; 5136 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 5137 } 5138 5139 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 5140 5141 /* 5142 * pseries-2.3 5143 */ 5144 5145 static void spapr_machine_2_3_class_options(MachineClass *mc) 5146 { 5147 static GlobalProperty compat[] = { 5148 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 5149 }; 5150 spapr_machine_2_4_class_options(mc); 5151 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 5152 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5153 } 5154 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 5155 5156 /* 5157 * pseries-2.2 5158 */ 5159 5160 static void spapr_machine_2_2_class_options(MachineClass *mc) 5161 { 5162 static GlobalProperty compat[] = { 5163 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 5164 }; 5165 5166 spapr_machine_2_3_class_options(mc); 5167 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 5168 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5169 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 5170 } 5171 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 5172 5173 /* 5174 * pseries-2.1 5175 */ 5176 5177 static void spapr_machine_2_1_class_options(MachineClass *mc) 5178 { 5179 spapr_machine_2_2_class_options(mc); 5180 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 5181 } 5182 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 5183 5184 static void spapr_machine_register_types(void) 5185 { 5186 type_register_static(&spapr_machine_info); 5187 } 5188 5189 type_init(spapr_machine_register_types) 5190