1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/numa.h" 31 #include "hw/hw.h" 32 #include "qemu/log.h" 33 #include "hw/fw-path-provider.h" 34 #include "elf.h" 35 #include "net/net.h" 36 #include "sysemu/device_tree.h" 37 #include "sysemu/block-backend.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/hw_accel.h" 40 #include "kvm_ppc.h" 41 #include "migration/migration.h" 42 #include "mmu-hash64.h" 43 #include "qom/cpu.h" 44 45 #include "hw/boards.h" 46 #include "hw/ppc/ppc.h" 47 #include "hw/loader.h" 48 49 #include "hw/ppc/fdt.h" 50 #include "hw/ppc/spapr.h" 51 #include "hw/ppc/spapr_vio.h" 52 #include "hw/pci-host/spapr.h" 53 #include "hw/ppc/xics.h" 54 #include "hw/pci/msi.h" 55 56 #include "hw/pci/pci.h" 57 #include "hw/scsi/scsi.h" 58 #include "hw/virtio/virtio-scsi.h" 59 60 #include "exec/address-spaces.h" 61 #include "hw/usb.h" 62 #include "qemu/config-file.h" 63 #include "qemu/error-report.h" 64 #include "trace.h" 65 #include "hw/nmi.h" 66 67 #include "hw/compat.h" 68 #include "qemu/cutils.h" 69 #include "hw/ppc/spapr_cpu_core.h" 70 #include "qmp-commands.h" 71 72 #include <libfdt.h> 73 74 /* SLOF memory layout: 75 * 76 * SLOF raw image loaded at 0, copies its romfs right below the flat 77 * device-tree, then position SLOF itself 31M below that 78 * 79 * So we set FW_OVERHEAD to 40MB which should account for all of that 80 * and more 81 * 82 * We load our kernel at 4M, leaving space for SLOF initial image 83 */ 84 #define FDT_MAX_SIZE 0x100000 85 #define RTAS_MAX_SIZE 0x10000 86 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 87 #define FW_MAX_SIZE 0x400000 88 #define FW_FILE_NAME "slof.bin" 89 #define FW_OVERHEAD 0x2800000 90 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 91 92 #define MIN_RMA_SLOF 128UL 93 94 #define PHANDLE_XICP 0x00001111 95 96 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 97 98 static XICSState *try_create_xics(sPAPRMachineState *spapr, 99 const char *type, const char *type_ics, 100 const char *type_icp, int nr_servers, 101 int nr_irqs, Error **errp) 102 { 103 XICSFabric *xi = XICS_FABRIC(spapr); 104 Error *err = NULL, *local_err = NULL; 105 XICSState *xics; 106 ICSState *ics = NULL; 107 int i; 108 109 xics = XICS_COMMON(object_new(type)); 110 qdev_set_parent_bus(DEVICE(xics), sysbus_get_default()); 111 object_property_set_bool(OBJECT(xics), true, "realized", &err); 112 if (err) { 113 goto error; 114 } 115 116 ics = ICS_SIMPLE(object_new(type_ics)); 117 qdev_set_parent_bus(DEVICE(ics), sysbus_get_default()); 118 object_property_add_child(OBJECT(spapr), "ics", OBJECT(ics), NULL); 119 object_property_set_int(OBJECT(ics), nr_irqs, "nr-irqs", &err); 120 object_property_add_const_link(OBJECT(ics), "xics", OBJECT(xi), NULL); 121 object_property_set_bool(OBJECT(ics), true, "realized", &local_err); 122 error_propagate(&err, local_err); 123 if (err) { 124 goto error; 125 } 126 127 xics->ss = g_malloc0(nr_servers * sizeof(ICPState)); 128 xics->nr_servers = nr_servers; 129 130 for (i = 0; i < nr_servers; i++) { 131 ICPState *icp = &xics->ss[i]; 132 133 object_initialize(icp, sizeof(*icp), type_icp); 134 object_property_add_child(OBJECT(xics), "icp[*]", OBJECT(icp), NULL); 135 object_property_add_const_link(OBJECT(icp), "xics", OBJECT(xi), NULL); 136 object_property_set_bool(OBJECT(icp), true, "realized", &err); 137 if (err) { 138 goto error; 139 } 140 object_unref(OBJECT(icp)); 141 } 142 143 spapr->ics = ics; 144 return xics; 145 146 error: 147 error_propagate(errp, err); 148 if (ics) { 149 object_unparent(OBJECT(ics)); 150 } 151 object_unparent(OBJECT(xics)); 152 return NULL; 153 } 154 155 static XICSState *xics_system_init(MachineState *machine, 156 int nr_servers, int nr_irqs, Error **errp) 157 { 158 XICSState *xics = NULL; 159 160 if (kvm_enabled()) { 161 Error *err = NULL; 162 163 if (machine_kernel_irqchip_allowed(machine)) { 164 xics = try_create_xics(SPAPR_MACHINE(machine), 165 TYPE_XICS_SPAPR_KVM, TYPE_ICS_KVM, 166 TYPE_KVM_ICP, nr_servers, nr_irqs, &err); 167 } 168 if (machine_kernel_irqchip_required(machine) && !xics) { 169 error_reportf_err(err, 170 "kernel_irqchip requested but unavailable: "); 171 } else { 172 error_free(err); 173 } 174 } 175 176 if (!xics) { 177 xics = try_create_xics(SPAPR_MACHINE(machine), 178 TYPE_XICS_SPAPR, TYPE_ICS_SIMPLE, 179 TYPE_ICP, nr_servers, nr_irqs, errp); 180 } 181 182 return xics; 183 } 184 185 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 186 int smt_threads) 187 { 188 int i, ret = 0; 189 uint32_t servers_prop[smt_threads]; 190 uint32_t gservers_prop[smt_threads * 2]; 191 int index = ppc_get_vcpu_dt_id(cpu); 192 193 if (cpu->compat_pvr) { 194 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 195 if (ret < 0) { 196 return ret; 197 } 198 } 199 200 /* Build interrupt servers and gservers properties */ 201 for (i = 0; i < smt_threads; i++) { 202 servers_prop[i] = cpu_to_be32(index + i); 203 /* Hack, direct the group queues back to cpu 0 */ 204 gservers_prop[i*2] = cpu_to_be32(index + i); 205 gservers_prop[i*2 + 1] = 0; 206 } 207 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 208 servers_prop, sizeof(servers_prop)); 209 if (ret < 0) { 210 return ret; 211 } 212 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 213 gservers_prop, sizeof(gservers_prop)); 214 215 return ret; 216 } 217 218 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs) 219 { 220 int ret = 0; 221 PowerPCCPU *cpu = POWERPC_CPU(cs); 222 int index = ppc_get_vcpu_dt_id(cpu); 223 uint32_t associativity[] = {cpu_to_be32(0x5), 224 cpu_to_be32(0x0), 225 cpu_to_be32(0x0), 226 cpu_to_be32(0x0), 227 cpu_to_be32(cs->numa_node), 228 cpu_to_be32(index)}; 229 230 /* Advertise NUMA via ibm,associativity */ 231 if (nb_numa_nodes > 1) { 232 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 233 sizeof(associativity)); 234 } 235 236 return ret; 237 } 238 239 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 240 { 241 int ret = 0, offset, cpus_offset; 242 CPUState *cs; 243 char cpu_model[32]; 244 int smt = kvmppc_smt_threads(); 245 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 246 247 CPU_FOREACH(cs) { 248 PowerPCCPU *cpu = POWERPC_CPU(cs); 249 DeviceClass *dc = DEVICE_GET_CLASS(cs); 250 int index = ppc_get_vcpu_dt_id(cpu); 251 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 252 253 if ((index % smt) != 0) { 254 continue; 255 } 256 257 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 258 259 cpus_offset = fdt_path_offset(fdt, "/cpus"); 260 if (cpus_offset < 0) { 261 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 262 "cpus"); 263 if (cpus_offset < 0) { 264 return cpus_offset; 265 } 266 } 267 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 268 if (offset < 0) { 269 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 270 if (offset < 0) { 271 return offset; 272 } 273 } 274 275 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 276 pft_size_prop, sizeof(pft_size_prop)); 277 if (ret < 0) { 278 return ret; 279 } 280 281 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs); 282 if (ret < 0) { 283 return ret; 284 } 285 286 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 287 if (ret < 0) { 288 return ret; 289 } 290 } 291 return ret; 292 } 293 294 static hwaddr spapr_node0_size(void) 295 { 296 MachineState *machine = MACHINE(qdev_get_machine()); 297 298 if (nb_numa_nodes) { 299 int i; 300 for (i = 0; i < nb_numa_nodes; ++i) { 301 if (numa_info[i].node_mem) { 302 return MIN(pow2floor(numa_info[i].node_mem), 303 machine->ram_size); 304 } 305 } 306 } 307 return machine->ram_size; 308 } 309 310 static void add_str(GString *s, const gchar *s1) 311 { 312 g_string_append_len(s, s1, strlen(s1) + 1); 313 } 314 315 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 316 hwaddr size) 317 { 318 uint32_t associativity[] = { 319 cpu_to_be32(0x4), /* length */ 320 cpu_to_be32(0x0), cpu_to_be32(0x0), 321 cpu_to_be32(0x0), cpu_to_be32(nodeid) 322 }; 323 char mem_name[32]; 324 uint64_t mem_reg_property[2]; 325 int off; 326 327 mem_reg_property[0] = cpu_to_be64(start); 328 mem_reg_property[1] = cpu_to_be64(size); 329 330 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 331 off = fdt_add_subnode(fdt, 0, mem_name); 332 _FDT(off); 333 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 334 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 335 sizeof(mem_reg_property)))); 336 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 337 sizeof(associativity)))); 338 return off; 339 } 340 341 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 342 { 343 MachineState *machine = MACHINE(spapr); 344 hwaddr mem_start, node_size; 345 int i, nb_nodes = nb_numa_nodes; 346 NodeInfo *nodes = numa_info; 347 NodeInfo ramnode; 348 349 /* No NUMA nodes, assume there is just one node with whole RAM */ 350 if (!nb_numa_nodes) { 351 nb_nodes = 1; 352 ramnode.node_mem = machine->ram_size; 353 nodes = &ramnode; 354 } 355 356 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 357 if (!nodes[i].node_mem) { 358 continue; 359 } 360 if (mem_start >= machine->ram_size) { 361 node_size = 0; 362 } else { 363 node_size = nodes[i].node_mem; 364 if (node_size > machine->ram_size - mem_start) { 365 node_size = machine->ram_size - mem_start; 366 } 367 } 368 if (!mem_start) { 369 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 370 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 371 mem_start += spapr->rma_size; 372 node_size -= spapr->rma_size; 373 } 374 for ( ; node_size; ) { 375 hwaddr sizetmp = pow2floor(node_size); 376 377 /* mem_start != 0 here */ 378 if (ctzl(mem_start) < ctzl(sizetmp)) { 379 sizetmp = 1ULL << ctzl(mem_start); 380 } 381 382 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 383 node_size -= sizetmp; 384 mem_start += sizetmp; 385 } 386 } 387 388 return 0; 389 } 390 391 /* Populate the "ibm,pa-features" property */ 392 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset) 393 { 394 uint8_t pa_features_206[] = { 6, 0, 395 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 396 uint8_t pa_features_207[] = { 24, 0, 397 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 398 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 399 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 400 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 401 uint8_t *pa_features; 402 size_t pa_size; 403 404 switch (env->mmu_model) { 405 case POWERPC_MMU_2_06: 406 case POWERPC_MMU_2_06a: 407 pa_features = pa_features_206; 408 pa_size = sizeof(pa_features_206); 409 break; 410 case POWERPC_MMU_2_07: 411 case POWERPC_MMU_2_07a: 412 pa_features = pa_features_207; 413 pa_size = sizeof(pa_features_207); 414 break; 415 default: 416 return; 417 } 418 419 if (env->ci_large_pages) { 420 /* 421 * Note: we keep CI large pages off by default because a 64K capable 422 * guest provisioned with large pages might otherwise try to map a qemu 423 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 424 * even if that qemu runs on a 4k host. 425 * We dd this bit back here if we are confident this is not an issue 426 */ 427 pa_features[3] |= 0x20; 428 } 429 if (kvmppc_has_cap_htm() && pa_size > 24) { 430 pa_features[24] |= 0x80; /* Transactional memory support */ 431 } 432 433 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 434 } 435 436 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 437 sPAPRMachineState *spapr) 438 { 439 PowerPCCPU *cpu = POWERPC_CPU(cs); 440 CPUPPCState *env = &cpu->env; 441 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 442 int index = ppc_get_vcpu_dt_id(cpu); 443 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 444 0xffffffff, 0xffffffff}; 445 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 446 : SPAPR_TIMEBASE_FREQ; 447 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 448 uint32_t page_sizes_prop[64]; 449 size_t page_sizes_prop_size; 450 uint32_t vcpus_per_socket = smp_threads * smp_cores; 451 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 452 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 453 sPAPRDRConnector *drc; 454 sPAPRDRConnectorClass *drck; 455 int drc_index; 456 457 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index); 458 if (drc) { 459 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 460 drc_index = drck->get_index(drc); 461 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 462 } 463 464 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 465 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 466 467 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 468 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 469 env->dcache_line_size))); 470 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 471 env->dcache_line_size))); 472 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 473 env->icache_line_size))); 474 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 475 env->icache_line_size))); 476 477 if (pcc->l1_dcache_size) { 478 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 479 pcc->l1_dcache_size))); 480 } else { 481 error_report("Warning: Unknown L1 dcache size for cpu"); 482 } 483 if (pcc->l1_icache_size) { 484 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 485 pcc->l1_icache_size))); 486 } else { 487 error_report("Warning: Unknown L1 icache size for cpu"); 488 } 489 490 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 491 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 492 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 493 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 494 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 495 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 496 497 if (env->spr_cb[SPR_PURR].oea_read) { 498 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 499 } 500 501 if (env->mmu_model & POWERPC_MMU_1TSEG) { 502 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 503 segs, sizeof(segs)))); 504 } 505 506 /* Advertise VMX/VSX (vector extensions) if available 507 * 0 / no property == no vector extensions 508 * 1 == VMX / Altivec available 509 * 2 == VSX available */ 510 if (env->insns_flags & PPC_ALTIVEC) { 511 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 512 513 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 514 } 515 516 /* Advertise DFP (Decimal Floating Point) if available 517 * 0 / no property == no DFP 518 * 1 == DFP available */ 519 if (env->insns_flags2 & PPC2_DFP) { 520 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 521 } 522 523 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 524 sizeof(page_sizes_prop)); 525 if (page_sizes_prop_size) { 526 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 527 page_sizes_prop, page_sizes_prop_size))); 528 } 529 530 spapr_populate_pa_features(env, fdt, offset); 531 532 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 533 cs->cpu_index / vcpus_per_socket))); 534 535 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 536 pft_size_prop, sizeof(pft_size_prop)))); 537 538 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs)); 539 540 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 541 } 542 543 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 544 { 545 CPUState *cs; 546 int cpus_offset; 547 char *nodename; 548 int smt = kvmppc_smt_threads(); 549 550 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 551 _FDT(cpus_offset); 552 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 553 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 554 555 /* 556 * We walk the CPUs in reverse order to ensure that CPU DT nodes 557 * created by fdt_add_subnode() end up in the right order in FDT 558 * for the guest kernel the enumerate the CPUs correctly. 559 */ 560 CPU_FOREACH_REVERSE(cs) { 561 PowerPCCPU *cpu = POWERPC_CPU(cs); 562 int index = ppc_get_vcpu_dt_id(cpu); 563 DeviceClass *dc = DEVICE_GET_CLASS(cs); 564 int offset; 565 566 if ((index % smt) != 0) { 567 continue; 568 } 569 570 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 571 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 572 g_free(nodename); 573 _FDT(offset); 574 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 575 } 576 577 } 578 579 /* 580 * Adds ibm,dynamic-reconfiguration-memory node. 581 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 582 * of this device tree node. 583 */ 584 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 585 { 586 MachineState *machine = MACHINE(spapr); 587 int ret, i, offset; 588 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 589 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 590 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 591 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 592 memory_region_size(&spapr->hotplug_memory.mr)) / 593 lmb_size; 594 uint32_t *int_buf, *cur_index, buf_len; 595 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 596 597 /* 598 * Don't create the node if there is no hotpluggable memory 599 */ 600 if (machine->ram_size == machine->maxram_size) { 601 return 0; 602 } 603 604 /* 605 * Allocate enough buffer size to fit in ibm,dynamic-memory 606 * or ibm,associativity-lookup-arrays 607 */ 608 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 609 * sizeof(uint32_t); 610 cur_index = int_buf = g_malloc0(buf_len); 611 612 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 613 614 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 615 sizeof(prop_lmb_size)); 616 if (ret < 0) { 617 goto out; 618 } 619 620 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 621 if (ret < 0) { 622 goto out; 623 } 624 625 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 626 if (ret < 0) { 627 goto out; 628 } 629 630 /* ibm,dynamic-memory */ 631 int_buf[0] = cpu_to_be32(nr_lmbs); 632 cur_index++; 633 for (i = 0; i < nr_lmbs; i++) { 634 uint64_t addr = i * lmb_size; 635 uint32_t *dynamic_memory = cur_index; 636 637 if (i >= hotplug_lmb_start) { 638 sPAPRDRConnector *drc; 639 sPAPRDRConnectorClass *drck; 640 641 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i); 642 g_assert(drc); 643 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 644 645 dynamic_memory[0] = cpu_to_be32(addr >> 32); 646 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 647 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); 648 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 649 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); 650 if (memory_region_present(get_system_memory(), addr)) { 651 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 652 } else { 653 dynamic_memory[5] = cpu_to_be32(0); 654 } 655 } else { 656 /* 657 * LMB information for RMA, boot time RAM and gap b/n RAM and 658 * hotplug memory region -- all these are marked as reserved 659 * and as having no valid DRC. 660 */ 661 dynamic_memory[0] = cpu_to_be32(addr >> 32); 662 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 663 dynamic_memory[2] = cpu_to_be32(0); 664 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 665 dynamic_memory[4] = cpu_to_be32(-1); 666 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 667 SPAPR_LMB_FLAGS_DRC_INVALID); 668 } 669 670 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 671 } 672 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 673 if (ret < 0) { 674 goto out; 675 } 676 677 /* ibm,associativity-lookup-arrays */ 678 cur_index = int_buf; 679 int_buf[0] = cpu_to_be32(nr_nodes); 680 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 681 cur_index += 2; 682 for (i = 0; i < nr_nodes; i++) { 683 uint32_t associativity[] = { 684 cpu_to_be32(0x0), 685 cpu_to_be32(0x0), 686 cpu_to_be32(0x0), 687 cpu_to_be32(i) 688 }; 689 memcpy(cur_index, associativity, sizeof(associativity)); 690 cur_index += 4; 691 } 692 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 693 (cur_index - int_buf) * sizeof(uint32_t)); 694 out: 695 g_free(int_buf); 696 return ret; 697 } 698 699 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 700 sPAPROptionVector *ov5_updates) 701 { 702 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 703 int ret = 0, offset; 704 705 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 706 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 707 g_assert(smc->dr_lmb_enabled); 708 ret = spapr_populate_drconf_memory(spapr, fdt); 709 if (ret) { 710 goto out; 711 } 712 } 713 714 offset = fdt_path_offset(fdt, "/chosen"); 715 if (offset < 0) { 716 offset = fdt_add_subnode(fdt, 0, "chosen"); 717 if (offset < 0) { 718 return offset; 719 } 720 } 721 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 722 "ibm,architecture-vec-5"); 723 724 out: 725 return ret; 726 } 727 728 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 729 target_ulong addr, target_ulong size, 730 sPAPROptionVector *ov5_updates) 731 { 732 void *fdt, *fdt_skel; 733 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 734 735 size -= sizeof(hdr); 736 737 /* Create sceleton */ 738 fdt_skel = g_malloc0(size); 739 _FDT((fdt_create(fdt_skel, size))); 740 _FDT((fdt_begin_node(fdt_skel, ""))); 741 _FDT((fdt_end_node(fdt_skel))); 742 _FDT((fdt_finish(fdt_skel))); 743 fdt = g_malloc0(size); 744 _FDT((fdt_open_into(fdt_skel, fdt, size))); 745 g_free(fdt_skel); 746 747 /* Fixup cpu nodes */ 748 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 749 750 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 751 return -1; 752 } 753 754 /* Pack resulting tree */ 755 _FDT((fdt_pack(fdt))); 756 757 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 758 trace_spapr_cas_failed(size); 759 return -1; 760 } 761 762 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 763 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 764 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 765 g_free(fdt); 766 767 return 0; 768 } 769 770 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 771 { 772 int rtas; 773 GString *hypertas = g_string_sized_new(256); 774 GString *qemu_hypertas = g_string_sized_new(256); 775 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 776 uint64_t max_hotplug_addr = spapr->hotplug_memory.base + 777 memory_region_size(&spapr->hotplug_memory.mr); 778 uint32_t lrdr_capacity[] = { 779 cpu_to_be32(max_hotplug_addr >> 32), 780 cpu_to_be32(max_hotplug_addr & 0xffffffff), 781 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 782 cpu_to_be32(max_cpus / smp_threads), 783 }; 784 785 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 786 787 /* hypertas */ 788 add_str(hypertas, "hcall-pft"); 789 add_str(hypertas, "hcall-term"); 790 add_str(hypertas, "hcall-dabr"); 791 add_str(hypertas, "hcall-interrupt"); 792 add_str(hypertas, "hcall-tce"); 793 add_str(hypertas, "hcall-vio"); 794 add_str(hypertas, "hcall-splpar"); 795 add_str(hypertas, "hcall-bulk"); 796 add_str(hypertas, "hcall-set-mode"); 797 add_str(hypertas, "hcall-sprg0"); 798 add_str(hypertas, "hcall-copy"); 799 add_str(hypertas, "hcall-debug"); 800 add_str(qemu_hypertas, "hcall-memop1"); 801 802 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 803 add_str(hypertas, "hcall-multi-tce"); 804 } 805 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 806 hypertas->str, hypertas->len)); 807 g_string_free(hypertas, TRUE); 808 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 809 qemu_hypertas->str, qemu_hypertas->len)); 810 g_string_free(qemu_hypertas, TRUE); 811 812 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 813 refpoints, sizeof(refpoints))); 814 815 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 816 RTAS_ERROR_LOG_MAX)); 817 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 818 RTAS_EVENT_SCAN_RATE)); 819 820 if (msi_nonbroken) { 821 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 822 } 823 824 /* 825 * According to PAPR, rtas ibm,os-term does not guarantee a return 826 * back to the guest cpu. 827 * 828 * While an additional ibm,extended-os-term property indicates 829 * that rtas call return will always occur. Set this property. 830 */ 831 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 832 833 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 834 lrdr_capacity, sizeof(lrdr_capacity))); 835 836 spapr_dt_rtas_tokens(fdt, rtas); 837 } 838 839 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 840 { 841 MachineState *machine = MACHINE(spapr); 842 int chosen; 843 const char *boot_device = machine->boot_order; 844 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 845 size_t cb = 0; 846 char *bootlist = get_boot_devices_list(&cb, true); 847 848 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 849 850 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 851 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 852 spapr->initrd_base)); 853 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 854 spapr->initrd_base + spapr->initrd_size)); 855 856 if (spapr->kernel_size) { 857 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 858 cpu_to_be64(spapr->kernel_size) }; 859 860 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 861 &kprop, sizeof(kprop))); 862 if (spapr->kernel_le) { 863 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 864 } 865 } 866 if (boot_menu) { 867 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 868 } 869 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 870 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 871 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 872 873 if (cb && bootlist) { 874 int i; 875 876 for (i = 0; i < cb; i++) { 877 if (bootlist[i] == '\n') { 878 bootlist[i] = ' '; 879 } 880 } 881 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 882 } 883 884 if (boot_device && strlen(boot_device)) { 885 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 886 } 887 888 if (!spapr->has_graphics && stdout_path) { 889 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 890 } 891 892 g_free(stdout_path); 893 g_free(bootlist); 894 } 895 896 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 897 { 898 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 899 * KVM to work under pHyp with some guest co-operation */ 900 int hypervisor; 901 uint8_t hypercall[16]; 902 903 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 904 /* indicate KVM hypercall interface */ 905 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 906 if (kvmppc_has_cap_fixup_hcalls()) { 907 /* 908 * Older KVM versions with older guest kernels were broken 909 * with the magic page, don't allow the guest to map it. 910 */ 911 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 912 sizeof(hypercall))) { 913 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 914 hypercall, sizeof(hypercall))); 915 } 916 } 917 } 918 919 static void *spapr_build_fdt(sPAPRMachineState *spapr, 920 hwaddr rtas_addr, 921 hwaddr rtas_size) 922 { 923 MachineState *machine = MACHINE(qdev_get_machine()); 924 MachineClass *mc = MACHINE_GET_CLASS(machine); 925 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 926 int ret; 927 void *fdt; 928 sPAPRPHBState *phb; 929 char *buf; 930 931 fdt = g_malloc0(FDT_MAX_SIZE); 932 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 933 934 /* Root node */ 935 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 936 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 937 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 938 939 /* 940 * Add info to guest to indentify which host is it being run on 941 * and what is the uuid of the guest 942 */ 943 if (kvmppc_get_host_model(&buf)) { 944 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 945 g_free(buf); 946 } 947 if (kvmppc_get_host_serial(&buf)) { 948 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 949 g_free(buf); 950 } 951 952 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 953 954 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 955 if (qemu_uuid_set) { 956 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 957 } 958 g_free(buf); 959 960 if (qemu_get_vm_name()) { 961 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 962 qemu_get_vm_name())); 963 } 964 965 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 966 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 967 968 /* /interrupt controller */ 969 spapr_dt_xics(spapr->xics, fdt, PHANDLE_XICP); 970 971 ret = spapr_populate_memory(spapr, fdt); 972 if (ret < 0) { 973 error_report("couldn't setup memory nodes in fdt"); 974 exit(1); 975 } 976 977 /* /vdevice */ 978 spapr_dt_vdevice(spapr->vio_bus, fdt); 979 980 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 981 ret = spapr_rng_populate_dt(fdt); 982 if (ret < 0) { 983 error_report("could not set up rng device in the fdt"); 984 exit(1); 985 } 986 } 987 988 QLIST_FOREACH(phb, &spapr->phbs, list) { 989 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 990 if (ret < 0) { 991 error_report("couldn't setup PCI devices in fdt"); 992 exit(1); 993 } 994 } 995 996 /* cpus */ 997 spapr_populate_cpus_dt_node(fdt, spapr); 998 999 if (smc->dr_lmb_enabled) { 1000 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1001 } 1002 1003 if (mc->has_hotpluggable_cpus) { 1004 int offset = fdt_path_offset(fdt, "/cpus"); 1005 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1006 SPAPR_DR_CONNECTOR_TYPE_CPU); 1007 if (ret < 0) { 1008 error_report("Couldn't set up CPU DR device tree properties"); 1009 exit(1); 1010 } 1011 } 1012 1013 /* /event-sources */ 1014 spapr_dt_events(spapr, fdt); 1015 1016 /* /rtas */ 1017 spapr_dt_rtas(spapr, fdt); 1018 1019 /* /chosen */ 1020 spapr_dt_chosen(spapr, fdt); 1021 1022 /* /hypervisor */ 1023 if (kvm_enabled()) { 1024 spapr_dt_hypervisor(spapr, fdt); 1025 } 1026 1027 /* Build memory reserve map */ 1028 if (spapr->kernel_size) { 1029 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1030 } 1031 if (spapr->initrd_size) { 1032 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1033 } 1034 1035 /* ibm,client-architecture-support updates */ 1036 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1037 if (ret < 0) { 1038 error_report("couldn't setup CAS properties fdt"); 1039 exit(1); 1040 } 1041 1042 return fdt; 1043 } 1044 1045 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1046 { 1047 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1048 } 1049 1050 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1051 PowerPCCPU *cpu) 1052 { 1053 CPUPPCState *env = &cpu->env; 1054 1055 /* The TCG path should also be holding the BQL at this point */ 1056 g_assert(qemu_mutex_iothread_locked()); 1057 1058 if (msr_pr) { 1059 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1060 env->gpr[3] = H_PRIVILEGE; 1061 } else { 1062 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1063 } 1064 } 1065 1066 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1067 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1068 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1069 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1070 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1071 1072 /* 1073 * Get the fd to access the kernel htab, re-opening it if necessary 1074 */ 1075 static int get_htab_fd(sPAPRMachineState *spapr) 1076 { 1077 if (spapr->htab_fd >= 0) { 1078 return spapr->htab_fd; 1079 } 1080 1081 spapr->htab_fd = kvmppc_get_htab_fd(false); 1082 if (spapr->htab_fd < 0) { 1083 error_report("Unable to open fd for reading hash table from KVM: %s", 1084 strerror(errno)); 1085 } 1086 1087 return spapr->htab_fd; 1088 } 1089 1090 static void close_htab_fd(sPAPRMachineState *spapr) 1091 { 1092 if (spapr->htab_fd >= 0) { 1093 close(spapr->htab_fd); 1094 } 1095 spapr->htab_fd = -1; 1096 } 1097 1098 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1099 { 1100 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1101 1102 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1103 } 1104 1105 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1106 hwaddr ptex, int n) 1107 { 1108 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1109 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1110 1111 if (!spapr->htab) { 1112 /* 1113 * HTAB is controlled by KVM. Fetch into temporary buffer 1114 */ 1115 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1116 kvmppc_read_hptes(hptes, ptex, n); 1117 return hptes; 1118 } 1119 1120 /* 1121 * HTAB is controlled by QEMU. Just point to the internally 1122 * accessible PTEG. 1123 */ 1124 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1125 } 1126 1127 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1128 const ppc_hash_pte64_t *hptes, 1129 hwaddr ptex, int n) 1130 { 1131 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1132 1133 if (!spapr->htab) { 1134 g_free((void *)hptes); 1135 } 1136 1137 /* Nothing to do for qemu managed HPT */ 1138 } 1139 1140 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1141 uint64_t pte0, uint64_t pte1) 1142 { 1143 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1144 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1145 1146 if (!spapr->htab) { 1147 kvmppc_write_hpte(ptex, pte0, pte1); 1148 } else { 1149 stq_p(spapr->htab + offset, pte0); 1150 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1151 } 1152 } 1153 1154 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1155 { 1156 int shift; 1157 1158 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1159 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1160 * that's much more than is needed for Linux guests */ 1161 shift = ctz64(pow2ceil(ramsize)) - 7; 1162 shift = MAX(shift, 18); /* Minimum architected size */ 1163 shift = MIN(shift, 46); /* Maximum architected size */ 1164 return shift; 1165 } 1166 1167 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1168 Error **errp) 1169 { 1170 long rc; 1171 1172 /* Clean up any HPT info from a previous boot */ 1173 g_free(spapr->htab); 1174 spapr->htab = NULL; 1175 spapr->htab_shift = 0; 1176 close_htab_fd(spapr); 1177 1178 rc = kvmppc_reset_htab(shift); 1179 if (rc < 0) { 1180 /* kernel-side HPT needed, but couldn't allocate one */ 1181 error_setg_errno(errp, errno, 1182 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1183 shift); 1184 /* This is almost certainly fatal, but if the caller really 1185 * wants to carry on with shift == 0, it's welcome to try */ 1186 } else if (rc > 0) { 1187 /* kernel-side HPT allocated */ 1188 if (rc != shift) { 1189 error_setg(errp, 1190 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1191 shift, rc); 1192 } 1193 1194 spapr->htab_shift = shift; 1195 spapr->htab = NULL; 1196 } else { 1197 /* kernel-side HPT not needed, allocate in userspace instead */ 1198 size_t size = 1ULL << shift; 1199 int i; 1200 1201 spapr->htab = qemu_memalign(size, size); 1202 if (!spapr->htab) { 1203 error_setg_errno(errp, errno, 1204 "Could not allocate HPT of order %d", shift); 1205 return; 1206 } 1207 1208 memset(spapr->htab, 0, size); 1209 spapr->htab_shift = shift; 1210 1211 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1212 DIRTY_HPTE(HPTE(spapr->htab, i)); 1213 } 1214 } 1215 } 1216 1217 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1218 { 1219 bool matched = false; 1220 1221 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1222 matched = true; 1223 } 1224 1225 if (!matched) { 1226 error_report("Device %s is not supported by this machine yet.", 1227 qdev_fw_name(DEVICE(sbdev))); 1228 exit(1); 1229 } 1230 } 1231 1232 static void ppc_spapr_reset(void) 1233 { 1234 MachineState *machine = MACHINE(qdev_get_machine()); 1235 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1236 PowerPCCPU *first_ppc_cpu; 1237 uint32_t rtas_limit; 1238 hwaddr rtas_addr, fdt_addr; 1239 void *fdt; 1240 int rc; 1241 1242 /* Check for unknown sysbus devices */ 1243 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1244 1245 /* Allocate and/or reset the hash page table */ 1246 spapr_reallocate_hpt(spapr, 1247 spapr_hpt_shift_for_ramsize(machine->maxram_size), 1248 &error_fatal); 1249 1250 /* Update the RMA size if necessary */ 1251 if (spapr->vrma_adjust) { 1252 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 1253 spapr->htab_shift); 1254 } 1255 1256 qemu_devices_reset(); 1257 1258 /* 1259 * We place the device tree and RTAS just below either the top of the RMA, 1260 * or just below 2GB, whichever is lowere, so that it can be 1261 * processed with 32-bit real mode code if necessary 1262 */ 1263 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1264 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1265 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1266 1267 /* if this reset wasn't generated by CAS, we should reset our 1268 * negotiated options and start from scratch */ 1269 if (!spapr->cas_reboot) { 1270 spapr_ovec_cleanup(spapr->ov5_cas); 1271 spapr->ov5_cas = spapr_ovec_new(); 1272 } 1273 1274 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1275 1276 spapr_load_rtas(spapr, fdt, rtas_addr); 1277 1278 rc = fdt_pack(fdt); 1279 1280 /* Should only fail if we've built a corrupted tree */ 1281 assert(rc == 0); 1282 1283 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1284 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1285 fdt_totalsize(fdt), FDT_MAX_SIZE); 1286 exit(1); 1287 } 1288 1289 /* Load the fdt */ 1290 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1291 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1292 g_free(fdt); 1293 1294 /* Set up the entry state */ 1295 first_ppc_cpu = POWERPC_CPU(first_cpu); 1296 first_ppc_cpu->env.gpr[3] = fdt_addr; 1297 first_ppc_cpu->env.gpr[5] = 0; 1298 first_cpu->halted = 0; 1299 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1300 1301 spapr->cas_reboot = false; 1302 } 1303 1304 static void spapr_create_nvram(sPAPRMachineState *spapr) 1305 { 1306 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1307 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1308 1309 if (dinfo) { 1310 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1311 &error_fatal); 1312 } 1313 1314 qdev_init_nofail(dev); 1315 1316 spapr->nvram = (struct sPAPRNVRAM *)dev; 1317 } 1318 1319 static void spapr_rtc_create(sPAPRMachineState *spapr) 1320 { 1321 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC); 1322 1323 qdev_init_nofail(dev); 1324 spapr->rtc = dev; 1325 1326 object_property_add_alias(qdev_get_machine(), "rtc-time", 1327 OBJECT(spapr->rtc), "date", NULL); 1328 } 1329 1330 /* Returns whether we want to use VGA or not */ 1331 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1332 { 1333 switch (vga_interface_type) { 1334 case VGA_NONE: 1335 return false; 1336 case VGA_DEVICE: 1337 return true; 1338 case VGA_STD: 1339 case VGA_VIRTIO: 1340 return pci_vga_init(pci_bus) != NULL; 1341 default: 1342 error_setg(errp, 1343 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1344 return false; 1345 } 1346 } 1347 1348 static int spapr_post_load(void *opaque, int version_id) 1349 { 1350 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1351 int err = 0; 1352 1353 /* In earlier versions, there was no separate qdev for the PAPR 1354 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1355 * So when migrating from those versions, poke the incoming offset 1356 * value into the RTC device */ 1357 if (version_id < 3) { 1358 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset); 1359 } 1360 1361 return err; 1362 } 1363 1364 static bool version_before_3(void *opaque, int version_id) 1365 { 1366 return version_id < 3; 1367 } 1368 1369 static bool spapr_ov5_cas_needed(void *opaque) 1370 { 1371 sPAPRMachineState *spapr = opaque; 1372 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1373 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1374 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1375 bool cas_needed; 1376 1377 /* Prior to the introduction of sPAPROptionVector, we had two option 1378 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1379 * Both of these options encode machine topology into the device-tree 1380 * in such a way that the now-booted OS should still be able to interact 1381 * appropriately with QEMU regardless of what options were actually 1382 * negotiatied on the source side. 1383 * 1384 * As such, we can avoid migrating the CAS-negotiated options if these 1385 * are the only options available on the current machine/platform. 1386 * Since these are the only options available for pseries-2.7 and 1387 * earlier, this allows us to maintain old->new/new->old migration 1388 * compatibility. 1389 * 1390 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1391 * via default pseries-2.8 machines and explicit command-line parameters. 1392 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1393 * of the actual CAS-negotiated values to continue working properly. For 1394 * example, availability of memory unplug depends on knowing whether 1395 * OV5_HP_EVT was negotiated via CAS. 1396 * 1397 * Thus, for any cases where the set of available CAS-negotiatable 1398 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1399 * include the CAS-negotiated options in the migration stream. 1400 */ 1401 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1402 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1403 1404 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1405 * the mask itself since in the future it's possible "legacy" bits may be 1406 * removed via machine options, which could generate a false positive 1407 * that breaks migration. 1408 */ 1409 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1410 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1411 1412 spapr_ovec_cleanup(ov5_mask); 1413 spapr_ovec_cleanup(ov5_legacy); 1414 spapr_ovec_cleanup(ov5_removed); 1415 1416 return cas_needed; 1417 } 1418 1419 static const VMStateDescription vmstate_spapr_ov5_cas = { 1420 .name = "spapr_option_vector_ov5_cas", 1421 .version_id = 1, 1422 .minimum_version_id = 1, 1423 .needed = spapr_ov5_cas_needed, 1424 .fields = (VMStateField[]) { 1425 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1426 vmstate_spapr_ovec, sPAPROptionVector), 1427 VMSTATE_END_OF_LIST() 1428 }, 1429 }; 1430 1431 static const VMStateDescription vmstate_spapr = { 1432 .name = "spapr", 1433 .version_id = 3, 1434 .minimum_version_id = 1, 1435 .post_load = spapr_post_load, 1436 .fields = (VMStateField[]) { 1437 /* used to be @next_irq */ 1438 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1439 1440 /* RTC offset */ 1441 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1442 1443 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1444 VMSTATE_END_OF_LIST() 1445 }, 1446 .subsections = (const VMStateDescription*[]) { 1447 &vmstate_spapr_ov5_cas, 1448 NULL 1449 } 1450 }; 1451 1452 static int htab_save_setup(QEMUFile *f, void *opaque) 1453 { 1454 sPAPRMachineState *spapr = opaque; 1455 1456 /* "Iteration" header */ 1457 qemu_put_be32(f, spapr->htab_shift); 1458 1459 if (spapr->htab) { 1460 spapr->htab_save_index = 0; 1461 spapr->htab_first_pass = true; 1462 } else { 1463 assert(kvm_enabled()); 1464 } 1465 1466 1467 return 0; 1468 } 1469 1470 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1471 int64_t max_ns) 1472 { 1473 bool has_timeout = max_ns != -1; 1474 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1475 int index = spapr->htab_save_index; 1476 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1477 1478 assert(spapr->htab_first_pass); 1479 1480 do { 1481 int chunkstart; 1482 1483 /* Consume invalid HPTEs */ 1484 while ((index < htabslots) 1485 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1486 index++; 1487 CLEAN_HPTE(HPTE(spapr->htab, index)); 1488 } 1489 1490 /* Consume valid HPTEs */ 1491 chunkstart = index; 1492 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1493 && HPTE_VALID(HPTE(spapr->htab, index))) { 1494 index++; 1495 CLEAN_HPTE(HPTE(spapr->htab, index)); 1496 } 1497 1498 if (index > chunkstart) { 1499 int n_valid = index - chunkstart; 1500 1501 qemu_put_be32(f, chunkstart); 1502 qemu_put_be16(f, n_valid); 1503 qemu_put_be16(f, 0); 1504 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1505 HASH_PTE_SIZE_64 * n_valid); 1506 1507 if (has_timeout && 1508 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1509 break; 1510 } 1511 } 1512 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1513 1514 if (index >= htabslots) { 1515 assert(index == htabslots); 1516 index = 0; 1517 spapr->htab_first_pass = false; 1518 } 1519 spapr->htab_save_index = index; 1520 } 1521 1522 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1523 int64_t max_ns) 1524 { 1525 bool final = max_ns < 0; 1526 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1527 int examined = 0, sent = 0; 1528 int index = spapr->htab_save_index; 1529 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1530 1531 assert(!spapr->htab_first_pass); 1532 1533 do { 1534 int chunkstart, invalidstart; 1535 1536 /* Consume non-dirty HPTEs */ 1537 while ((index < htabslots) 1538 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1539 index++; 1540 examined++; 1541 } 1542 1543 chunkstart = index; 1544 /* Consume valid dirty HPTEs */ 1545 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1546 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1547 && HPTE_VALID(HPTE(spapr->htab, index))) { 1548 CLEAN_HPTE(HPTE(spapr->htab, index)); 1549 index++; 1550 examined++; 1551 } 1552 1553 invalidstart = index; 1554 /* Consume invalid dirty HPTEs */ 1555 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1556 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1557 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1558 CLEAN_HPTE(HPTE(spapr->htab, index)); 1559 index++; 1560 examined++; 1561 } 1562 1563 if (index > chunkstart) { 1564 int n_valid = invalidstart - chunkstart; 1565 int n_invalid = index - invalidstart; 1566 1567 qemu_put_be32(f, chunkstart); 1568 qemu_put_be16(f, n_valid); 1569 qemu_put_be16(f, n_invalid); 1570 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1571 HASH_PTE_SIZE_64 * n_valid); 1572 sent += index - chunkstart; 1573 1574 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1575 break; 1576 } 1577 } 1578 1579 if (examined >= htabslots) { 1580 break; 1581 } 1582 1583 if (index >= htabslots) { 1584 assert(index == htabslots); 1585 index = 0; 1586 } 1587 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1588 1589 if (index >= htabslots) { 1590 assert(index == htabslots); 1591 index = 0; 1592 } 1593 1594 spapr->htab_save_index = index; 1595 1596 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1597 } 1598 1599 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1600 #define MAX_KVM_BUF_SIZE 2048 1601 1602 static int htab_save_iterate(QEMUFile *f, void *opaque) 1603 { 1604 sPAPRMachineState *spapr = opaque; 1605 int fd; 1606 int rc = 0; 1607 1608 /* Iteration header */ 1609 qemu_put_be32(f, 0); 1610 1611 if (!spapr->htab) { 1612 assert(kvm_enabled()); 1613 1614 fd = get_htab_fd(spapr); 1615 if (fd < 0) { 1616 return fd; 1617 } 1618 1619 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1620 if (rc < 0) { 1621 return rc; 1622 } 1623 } else if (spapr->htab_first_pass) { 1624 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1625 } else { 1626 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1627 } 1628 1629 /* End marker */ 1630 qemu_put_be32(f, 0); 1631 qemu_put_be16(f, 0); 1632 qemu_put_be16(f, 0); 1633 1634 return rc; 1635 } 1636 1637 static int htab_save_complete(QEMUFile *f, void *opaque) 1638 { 1639 sPAPRMachineState *spapr = opaque; 1640 int fd; 1641 1642 /* Iteration header */ 1643 qemu_put_be32(f, 0); 1644 1645 if (!spapr->htab) { 1646 int rc; 1647 1648 assert(kvm_enabled()); 1649 1650 fd = get_htab_fd(spapr); 1651 if (fd < 0) { 1652 return fd; 1653 } 1654 1655 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 1656 if (rc < 0) { 1657 return rc; 1658 } 1659 } else { 1660 if (spapr->htab_first_pass) { 1661 htab_save_first_pass(f, spapr, -1); 1662 } 1663 htab_save_later_pass(f, spapr, -1); 1664 } 1665 1666 /* End marker */ 1667 qemu_put_be32(f, 0); 1668 qemu_put_be16(f, 0); 1669 qemu_put_be16(f, 0); 1670 1671 return 0; 1672 } 1673 1674 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1675 { 1676 sPAPRMachineState *spapr = opaque; 1677 uint32_t section_hdr; 1678 int fd = -1; 1679 1680 if (version_id < 1 || version_id > 1) { 1681 error_report("htab_load() bad version"); 1682 return -EINVAL; 1683 } 1684 1685 section_hdr = qemu_get_be32(f); 1686 1687 if (section_hdr) { 1688 Error *local_err = NULL; 1689 1690 /* First section gives the htab size */ 1691 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 1692 if (local_err) { 1693 error_report_err(local_err); 1694 return -EINVAL; 1695 } 1696 return 0; 1697 } 1698 1699 if (!spapr->htab) { 1700 assert(kvm_enabled()); 1701 1702 fd = kvmppc_get_htab_fd(true); 1703 if (fd < 0) { 1704 error_report("Unable to open fd to restore KVM hash table: %s", 1705 strerror(errno)); 1706 } 1707 } 1708 1709 while (true) { 1710 uint32_t index; 1711 uint16_t n_valid, n_invalid; 1712 1713 index = qemu_get_be32(f); 1714 n_valid = qemu_get_be16(f); 1715 n_invalid = qemu_get_be16(f); 1716 1717 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1718 /* End of Stream */ 1719 break; 1720 } 1721 1722 if ((index + n_valid + n_invalid) > 1723 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1724 /* Bad index in stream */ 1725 error_report( 1726 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 1727 index, n_valid, n_invalid, spapr->htab_shift); 1728 return -EINVAL; 1729 } 1730 1731 if (spapr->htab) { 1732 if (n_valid) { 1733 qemu_get_buffer(f, HPTE(spapr->htab, index), 1734 HASH_PTE_SIZE_64 * n_valid); 1735 } 1736 if (n_invalid) { 1737 memset(HPTE(spapr->htab, index + n_valid), 0, 1738 HASH_PTE_SIZE_64 * n_invalid); 1739 } 1740 } else { 1741 int rc; 1742 1743 assert(fd >= 0); 1744 1745 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1746 if (rc < 0) { 1747 return rc; 1748 } 1749 } 1750 } 1751 1752 if (!spapr->htab) { 1753 assert(fd >= 0); 1754 close(fd); 1755 } 1756 1757 return 0; 1758 } 1759 1760 static void htab_cleanup(void *opaque) 1761 { 1762 sPAPRMachineState *spapr = opaque; 1763 1764 close_htab_fd(spapr); 1765 } 1766 1767 static SaveVMHandlers savevm_htab_handlers = { 1768 .save_live_setup = htab_save_setup, 1769 .save_live_iterate = htab_save_iterate, 1770 .save_live_complete_precopy = htab_save_complete, 1771 .cleanup = htab_cleanup, 1772 .load_state = htab_load, 1773 }; 1774 1775 static void spapr_boot_set(void *opaque, const char *boot_device, 1776 Error **errp) 1777 { 1778 MachineState *machine = MACHINE(qdev_get_machine()); 1779 machine->boot_order = g_strdup(boot_device); 1780 } 1781 1782 /* 1783 * Reset routine for LMB DR devices. 1784 * 1785 * Unlike PCI DR devices, LMB DR devices explicitly register this reset 1786 * routine. Reset for PCI DR devices will be handled by PHB reset routine 1787 * when it walks all its children devices. LMB devices reset occurs 1788 * as part of spapr_ppc_reset(). 1789 */ 1790 static void spapr_drc_reset(void *opaque) 1791 { 1792 sPAPRDRConnector *drc = opaque; 1793 DeviceState *d = DEVICE(drc); 1794 1795 if (d) { 1796 device_reset(d); 1797 } 1798 } 1799 1800 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 1801 { 1802 MachineState *machine = MACHINE(spapr); 1803 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 1804 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 1805 int i; 1806 1807 for (i = 0; i < nr_lmbs; i++) { 1808 sPAPRDRConnector *drc; 1809 uint64_t addr; 1810 1811 addr = i * lmb_size + spapr->hotplug_memory.base; 1812 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB, 1813 addr/lmb_size); 1814 qemu_register_reset(spapr_drc_reset, drc); 1815 } 1816 } 1817 1818 /* 1819 * If RAM size, maxmem size and individual node mem sizes aren't aligned 1820 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 1821 * since we can't support such unaligned sizes with DRCONF_MEMORY. 1822 */ 1823 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 1824 { 1825 int i; 1826 1827 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1828 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 1829 " is not aligned to %llu MiB", 1830 machine->ram_size, 1831 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1832 return; 1833 } 1834 1835 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1836 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 1837 " is not aligned to %llu MiB", 1838 machine->ram_size, 1839 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1840 return; 1841 } 1842 1843 for (i = 0; i < nb_numa_nodes; i++) { 1844 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 1845 error_setg(errp, 1846 "Node %d memory size 0x%" PRIx64 1847 " is not aligned to %llu MiB", 1848 i, numa_info[i].node_mem, 1849 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1850 return; 1851 } 1852 } 1853 } 1854 1855 /* find cpu slot in machine->possible_cpus by core_id */ 1856 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 1857 { 1858 int index = id / smp_threads; 1859 1860 if (index >= ms->possible_cpus->len) { 1861 return NULL; 1862 } 1863 if (idx) { 1864 *idx = index; 1865 } 1866 return &ms->possible_cpus->cpus[index]; 1867 } 1868 1869 static void spapr_init_cpus(sPAPRMachineState *spapr) 1870 { 1871 MachineState *machine = MACHINE(spapr); 1872 MachineClass *mc = MACHINE_GET_CLASS(machine); 1873 char *type = spapr_get_cpu_core_type(machine->cpu_model); 1874 int smt = kvmppc_smt_threads(); 1875 const CPUArchIdList *possible_cpus; 1876 int boot_cores_nr = smp_cpus / smp_threads; 1877 int i; 1878 1879 if (!type) { 1880 error_report("Unable to find sPAPR CPU Core definition"); 1881 exit(1); 1882 } 1883 1884 possible_cpus = mc->possible_cpu_arch_ids(machine); 1885 if (mc->has_hotpluggable_cpus) { 1886 if (smp_cpus % smp_threads) { 1887 error_report("smp_cpus (%u) must be multiple of threads (%u)", 1888 smp_cpus, smp_threads); 1889 exit(1); 1890 } 1891 if (max_cpus % smp_threads) { 1892 error_report("max_cpus (%u) must be multiple of threads (%u)", 1893 max_cpus, smp_threads); 1894 exit(1); 1895 } 1896 } else { 1897 if (max_cpus != smp_cpus) { 1898 error_report("This machine version does not support CPU hotplug"); 1899 exit(1); 1900 } 1901 boot_cores_nr = possible_cpus->len; 1902 } 1903 1904 for (i = 0; i < possible_cpus->len; i++) { 1905 int core_id = i * smp_threads; 1906 1907 if (mc->has_hotpluggable_cpus) { 1908 sPAPRDRConnector *drc = 1909 spapr_dr_connector_new(OBJECT(spapr), 1910 SPAPR_DR_CONNECTOR_TYPE_CPU, 1911 (core_id / smp_threads) * smt); 1912 1913 qemu_register_reset(spapr_drc_reset, drc); 1914 } 1915 1916 if (i < boot_cores_nr) { 1917 Object *core = object_new(type); 1918 int nr_threads = smp_threads; 1919 1920 /* Handle the partially filled core for older machine types */ 1921 if ((i + 1) * smp_threads >= smp_cpus) { 1922 nr_threads = smp_cpus - i * smp_threads; 1923 } 1924 1925 object_property_set_int(core, nr_threads, "nr-threads", 1926 &error_fatal); 1927 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 1928 &error_fatal); 1929 object_property_set_bool(core, true, "realized", &error_fatal); 1930 } 1931 } 1932 g_free(type); 1933 } 1934 1935 /* pSeries LPAR / sPAPR hardware init */ 1936 static void ppc_spapr_init(MachineState *machine) 1937 { 1938 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1939 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1940 const char *kernel_filename = machine->kernel_filename; 1941 const char *initrd_filename = machine->initrd_filename; 1942 PCIHostState *phb; 1943 int i; 1944 MemoryRegion *sysmem = get_system_memory(); 1945 MemoryRegion *ram = g_new(MemoryRegion, 1); 1946 MemoryRegion *rma_region; 1947 void *rma = NULL; 1948 hwaddr rma_alloc_size; 1949 hwaddr node0_size = spapr_node0_size(); 1950 long load_limit, fw_size; 1951 char *filename; 1952 int smt = kvmppc_smt_threads(); 1953 1954 msi_nonbroken = true; 1955 1956 QLIST_INIT(&spapr->phbs); 1957 1958 /* Allocate RMA if necessary */ 1959 rma_alloc_size = kvmppc_alloc_rma(&rma); 1960 1961 if (rma_alloc_size == -1) { 1962 error_report("Unable to create RMA"); 1963 exit(1); 1964 } 1965 1966 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1967 spapr->rma_size = rma_alloc_size; 1968 } else { 1969 spapr->rma_size = node0_size; 1970 1971 /* With KVM, we don't actually know whether KVM supports an 1972 * unbounded RMA (PR KVM) or is limited by the hash table size 1973 * (HV KVM using VRMA), so we always assume the latter 1974 * 1975 * In that case, we also limit the initial allocations for RTAS 1976 * etc... to 256M since we have no way to know what the VRMA size 1977 * is going to be as it depends on the size of the hash table 1978 * isn't determined yet. 1979 */ 1980 if (kvm_enabled()) { 1981 spapr->vrma_adjust = 1; 1982 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1983 } 1984 1985 /* Actually we don't support unbounded RMA anymore since we 1986 * added proper emulation of HV mode. The max we can get is 1987 * 16G which also happens to be what we configure for PAPR 1988 * mode so make sure we don't do anything bigger than that 1989 */ 1990 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 1991 } 1992 1993 if (spapr->rma_size > node0_size) { 1994 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 1995 spapr->rma_size); 1996 exit(1); 1997 } 1998 1999 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2000 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2001 2002 /* Set up Interrupt Controller before we create the VCPUs */ 2003 spapr->xics = xics_system_init(machine, 2004 DIV_ROUND_UP(max_cpus * smt, smp_threads), 2005 XICS_IRQS_SPAPR, &error_fatal); 2006 2007 /* Set up containers for ibm,client-set-architecture negotiated options */ 2008 spapr->ov5 = spapr_ovec_new(); 2009 spapr->ov5_cas = spapr_ovec_new(); 2010 2011 if (smc->dr_lmb_enabled) { 2012 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2013 spapr_validate_node_memory(machine, &error_fatal); 2014 } 2015 2016 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2017 2018 /* advertise support for dedicated HP event source to guests */ 2019 if (spapr->use_hotplug_event_source) { 2020 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2021 } 2022 2023 /* init CPUs */ 2024 if (machine->cpu_model == NULL) { 2025 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu; 2026 } 2027 2028 ppc_cpu_parse_features(machine->cpu_model); 2029 2030 spapr_init_cpus(spapr); 2031 2032 if (kvm_enabled()) { 2033 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2034 kvmppc_enable_logical_ci_hcalls(); 2035 kvmppc_enable_set_mode_hcall(); 2036 2037 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2038 kvmppc_enable_clear_ref_mod_hcalls(); 2039 } 2040 2041 /* allocate RAM */ 2042 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2043 machine->ram_size); 2044 memory_region_add_subregion(sysmem, 0, ram); 2045 2046 if (rma_alloc_size && rma) { 2047 rma_region = g_new(MemoryRegion, 1); 2048 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 2049 rma_alloc_size, rma); 2050 vmstate_register_ram_global(rma_region); 2051 memory_region_add_subregion(sysmem, 0, rma_region); 2052 } 2053 2054 /* initialize hotplug memory address space */ 2055 if (machine->ram_size < machine->maxram_size) { 2056 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 2057 /* 2058 * Limit the number of hotpluggable memory slots to half the number 2059 * slots that KVM supports, leaving the other half for PCI and other 2060 * devices. However ensure that number of slots doesn't drop below 32. 2061 */ 2062 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2063 SPAPR_MAX_RAM_SLOTS; 2064 2065 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2066 max_memslots = SPAPR_MAX_RAM_SLOTS; 2067 } 2068 if (machine->ram_slots > max_memslots) { 2069 error_report("Specified number of memory slots %" 2070 PRIu64" exceeds max supported %d", 2071 machine->ram_slots, max_memslots); 2072 exit(1); 2073 } 2074 2075 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 2076 SPAPR_HOTPLUG_MEM_ALIGN); 2077 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 2078 "hotplug-memory", hotplug_mem_size); 2079 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 2080 &spapr->hotplug_memory.mr); 2081 } 2082 2083 if (smc->dr_lmb_enabled) { 2084 spapr_create_lmb_dr_connectors(spapr); 2085 } 2086 2087 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2088 if (!filename) { 2089 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2090 exit(1); 2091 } 2092 spapr->rtas_size = get_image_size(filename); 2093 if (spapr->rtas_size < 0) { 2094 error_report("Could not get size of LPAR rtas '%s'", filename); 2095 exit(1); 2096 } 2097 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2098 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2099 error_report("Could not load LPAR rtas '%s'", filename); 2100 exit(1); 2101 } 2102 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2103 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2104 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2105 exit(1); 2106 } 2107 g_free(filename); 2108 2109 /* Set up RTAS event infrastructure */ 2110 spapr_events_init(spapr); 2111 2112 /* Set up the RTC RTAS interfaces */ 2113 spapr_rtc_create(spapr); 2114 2115 /* Set up VIO bus */ 2116 spapr->vio_bus = spapr_vio_bus_init(); 2117 2118 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 2119 if (serial_hds[i]) { 2120 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 2121 } 2122 } 2123 2124 /* We always have at least the nvram device on VIO */ 2125 spapr_create_nvram(spapr); 2126 2127 /* Set up PCI */ 2128 spapr_pci_rtas_init(); 2129 2130 phb = spapr_create_phb(spapr, 0); 2131 2132 for (i = 0; i < nb_nics; i++) { 2133 NICInfo *nd = &nd_table[i]; 2134 2135 if (!nd->model) { 2136 nd->model = g_strdup("ibmveth"); 2137 } 2138 2139 if (strcmp(nd->model, "ibmveth") == 0) { 2140 spapr_vlan_create(spapr->vio_bus, nd); 2141 } else { 2142 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2143 } 2144 } 2145 2146 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2147 spapr_vscsi_create(spapr->vio_bus); 2148 } 2149 2150 /* Graphics */ 2151 if (spapr_vga_init(phb->bus, &error_fatal)) { 2152 spapr->has_graphics = true; 2153 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2154 } 2155 2156 if (machine->usb) { 2157 if (smc->use_ohci_by_default) { 2158 pci_create_simple(phb->bus, -1, "pci-ohci"); 2159 } else { 2160 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2161 } 2162 2163 if (spapr->has_graphics) { 2164 USBBus *usb_bus = usb_bus_find(-1); 2165 2166 usb_create_simple(usb_bus, "usb-kbd"); 2167 usb_create_simple(usb_bus, "usb-mouse"); 2168 } 2169 } 2170 2171 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 2172 error_report( 2173 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2174 MIN_RMA_SLOF); 2175 exit(1); 2176 } 2177 2178 if (kernel_filename) { 2179 uint64_t lowaddr = 0; 2180 2181 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2182 NULL, NULL, &lowaddr, NULL, 1, 2183 PPC_ELF_MACHINE, 0, 0); 2184 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2185 spapr->kernel_size = load_elf(kernel_filename, 2186 translate_kernel_address, NULL, NULL, 2187 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2188 0, 0); 2189 spapr->kernel_le = spapr->kernel_size > 0; 2190 } 2191 if (spapr->kernel_size < 0) { 2192 error_report("error loading %s: %s", kernel_filename, 2193 load_elf_strerror(spapr->kernel_size)); 2194 exit(1); 2195 } 2196 2197 /* load initrd */ 2198 if (initrd_filename) { 2199 /* Try to locate the initrd in the gap between the kernel 2200 * and the firmware. Add a bit of space just in case 2201 */ 2202 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2203 + 0x1ffff) & ~0xffff; 2204 spapr->initrd_size = load_image_targphys(initrd_filename, 2205 spapr->initrd_base, 2206 load_limit 2207 - spapr->initrd_base); 2208 if (spapr->initrd_size < 0) { 2209 error_report("could not load initial ram disk '%s'", 2210 initrd_filename); 2211 exit(1); 2212 } 2213 } 2214 } 2215 2216 if (bios_name == NULL) { 2217 bios_name = FW_FILE_NAME; 2218 } 2219 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2220 if (!filename) { 2221 error_report("Could not find LPAR firmware '%s'", bios_name); 2222 exit(1); 2223 } 2224 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2225 if (fw_size <= 0) { 2226 error_report("Could not load LPAR firmware '%s'", filename); 2227 exit(1); 2228 } 2229 g_free(filename); 2230 2231 /* FIXME: Should register things through the MachineState's qdev 2232 * interface, this is a legacy from the sPAPREnvironment structure 2233 * which predated MachineState but had a similar function */ 2234 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2235 register_savevm_live(NULL, "spapr/htab", -1, 1, 2236 &savevm_htab_handlers, spapr); 2237 2238 /* used by RTAS */ 2239 QTAILQ_INIT(&spapr->ccs_list); 2240 qemu_register_reset(spapr_ccs_reset_hook, spapr); 2241 2242 qemu_register_boot_set(spapr_boot_set, spapr); 2243 2244 /* to stop and start vmclock */ 2245 if (kvm_enabled()) { 2246 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2247 &spapr->tb); 2248 } 2249 } 2250 2251 static int spapr_kvm_type(const char *vm_type) 2252 { 2253 if (!vm_type) { 2254 return 0; 2255 } 2256 2257 if (!strcmp(vm_type, "HV")) { 2258 return 1; 2259 } 2260 2261 if (!strcmp(vm_type, "PR")) { 2262 return 2; 2263 } 2264 2265 error_report("Unknown kvm-type specified '%s'", vm_type); 2266 exit(1); 2267 } 2268 2269 /* 2270 * Implementation of an interface to adjust firmware path 2271 * for the bootindex property handling. 2272 */ 2273 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2274 DeviceState *dev) 2275 { 2276 #define CAST(type, obj, name) \ 2277 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2278 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2279 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2280 2281 if (d) { 2282 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2283 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2284 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2285 2286 if (spapr) { 2287 /* 2288 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2289 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2290 * in the top 16 bits of the 64-bit LUN 2291 */ 2292 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2293 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2294 (uint64_t)id << 48); 2295 } else if (virtio) { 2296 /* 2297 * We use SRP luns of the form 01000000 | (target << 8) | lun 2298 * in the top 32 bits of the 64-bit LUN 2299 * Note: the quote above is from SLOF and it is wrong, 2300 * the actual binding is: 2301 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2302 */ 2303 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2304 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2305 (uint64_t)id << 32); 2306 } else if (usb) { 2307 /* 2308 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2309 * in the top 32 bits of the 64-bit LUN 2310 */ 2311 unsigned usb_port = atoi(usb->port->path); 2312 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2313 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2314 (uint64_t)id << 32); 2315 } 2316 } 2317 2318 /* 2319 * SLOF probes the USB devices, and if it recognizes that the device is a 2320 * storage device, it changes its name to "storage" instead of "usb-host", 2321 * and additionally adds a child node for the SCSI LUN, so the correct 2322 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2323 */ 2324 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2325 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2326 if (usb_host_dev_is_scsi_storage(usbdev)) { 2327 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2328 } 2329 } 2330 2331 if (phb) { 2332 /* Replace "pci" with "pci@800000020000000" */ 2333 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2334 } 2335 2336 return NULL; 2337 } 2338 2339 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2340 { 2341 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2342 2343 return g_strdup(spapr->kvm_type); 2344 } 2345 2346 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2347 { 2348 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2349 2350 g_free(spapr->kvm_type); 2351 spapr->kvm_type = g_strdup(value); 2352 } 2353 2354 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2355 { 2356 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2357 2358 return spapr->use_hotplug_event_source; 2359 } 2360 2361 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2362 Error **errp) 2363 { 2364 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2365 2366 spapr->use_hotplug_event_source = value; 2367 } 2368 2369 static void spapr_machine_initfn(Object *obj) 2370 { 2371 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2372 2373 spapr->htab_fd = -1; 2374 spapr->use_hotplug_event_source = true; 2375 object_property_add_str(obj, "kvm-type", 2376 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2377 object_property_set_description(obj, "kvm-type", 2378 "Specifies the KVM virtualization mode (HV, PR)", 2379 NULL); 2380 object_property_add_bool(obj, "modern-hotplug-events", 2381 spapr_get_modern_hotplug_events, 2382 spapr_set_modern_hotplug_events, 2383 NULL); 2384 object_property_set_description(obj, "modern-hotplug-events", 2385 "Use dedicated hotplug event mechanism in" 2386 " place of standard EPOW events when possible" 2387 " (required for memory hot-unplug support)", 2388 NULL); 2389 } 2390 2391 static void spapr_machine_finalizefn(Object *obj) 2392 { 2393 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2394 2395 g_free(spapr->kvm_type); 2396 } 2397 2398 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 2399 { 2400 cpu_synchronize_state(cs); 2401 ppc_cpu_do_system_reset(cs); 2402 } 2403 2404 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2405 { 2406 CPUState *cs; 2407 2408 CPU_FOREACH(cs) { 2409 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 2410 } 2411 } 2412 2413 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2414 uint32_t node, bool dedicated_hp_event_source, 2415 Error **errp) 2416 { 2417 sPAPRDRConnector *drc; 2418 sPAPRDRConnectorClass *drck; 2419 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2420 int i, fdt_offset, fdt_size; 2421 void *fdt; 2422 uint64_t addr = addr_start; 2423 2424 for (i = 0; i < nr_lmbs; i++) { 2425 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2426 addr/SPAPR_MEMORY_BLOCK_SIZE); 2427 g_assert(drc); 2428 2429 fdt = create_device_tree(&fdt_size); 2430 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2431 SPAPR_MEMORY_BLOCK_SIZE); 2432 2433 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2434 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); 2435 addr += SPAPR_MEMORY_BLOCK_SIZE; 2436 if (!dev->hotplugged) { 2437 /* guests expect coldplugged LMBs to be pre-allocated */ 2438 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); 2439 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); 2440 } 2441 } 2442 /* send hotplug notification to the 2443 * guest only in case of hotplugged memory 2444 */ 2445 if (dev->hotplugged) { 2446 if (dedicated_hp_event_source) { 2447 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2448 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2449 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2450 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2451 nr_lmbs, 2452 drck->get_index(drc)); 2453 } else { 2454 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 2455 nr_lmbs); 2456 } 2457 } 2458 } 2459 2460 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2461 uint32_t node, Error **errp) 2462 { 2463 Error *local_err = NULL; 2464 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2465 PCDIMMDevice *dimm = PC_DIMM(dev); 2466 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2467 MemoryRegion *mr = ddc->get_memory_region(dimm); 2468 uint64_t align = memory_region_get_alignment(mr); 2469 uint64_t size = memory_region_size(mr); 2470 uint64_t addr; 2471 char *mem_dev; 2472 2473 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 2474 error_setg(&local_err, "Hotplugged memory size must be a multiple of " 2475 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); 2476 goto out; 2477 } 2478 2479 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); 2480 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { 2481 error_setg(&local_err, "Memory backend has bad page size. " 2482 "Use 'memory-backend-file' with correct mem-path."); 2483 goto out; 2484 } 2485 2486 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 2487 if (local_err) { 2488 goto out; 2489 } 2490 2491 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2492 if (local_err) { 2493 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2494 goto out; 2495 } 2496 2497 spapr_add_lmbs(dev, addr, size, node, 2498 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 2499 &error_abort); 2500 2501 out: 2502 error_propagate(errp, local_err); 2503 } 2504 2505 typedef struct sPAPRDIMMState { 2506 uint32_t nr_lmbs; 2507 } sPAPRDIMMState; 2508 2509 static void spapr_lmb_release(DeviceState *dev, void *opaque) 2510 { 2511 sPAPRDIMMState *ds = (sPAPRDIMMState *)opaque; 2512 HotplugHandler *hotplug_ctrl; 2513 2514 if (--ds->nr_lmbs) { 2515 return; 2516 } 2517 2518 g_free(ds); 2519 2520 /* 2521 * Now that all the LMBs have been removed by the guest, call the 2522 * pc-dimm unplug handler to cleanup up the pc-dimm device. 2523 */ 2524 hotplug_ctrl = qdev_get_hotplug_handler(dev); 2525 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2526 } 2527 2528 static void spapr_del_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2529 Error **errp) 2530 { 2531 sPAPRDRConnector *drc; 2532 sPAPRDRConnectorClass *drck; 2533 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 2534 int i; 2535 sPAPRDIMMState *ds = g_malloc0(sizeof(sPAPRDIMMState)); 2536 uint64_t addr = addr_start; 2537 2538 ds->nr_lmbs = nr_lmbs; 2539 for (i = 0; i < nr_lmbs; i++) { 2540 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2541 addr / SPAPR_MEMORY_BLOCK_SIZE); 2542 g_assert(drc); 2543 2544 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2545 drck->detach(drc, dev, spapr_lmb_release, ds, errp); 2546 addr += SPAPR_MEMORY_BLOCK_SIZE; 2547 } 2548 2549 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2550 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2551 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2552 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2553 nr_lmbs, 2554 drck->get_index(drc)); 2555 } 2556 2557 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2558 Error **errp) 2559 { 2560 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2561 PCDIMMDevice *dimm = PC_DIMM(dev); 2562 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2563 MemoryRegion *mr = ddc->get_memory_region(dimm); 2564 2565 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2566 object_unparent(OBJECT(dev)); 2567 } 2568 2569 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 2570 DeviceState *dev, Error **errp) 2571 { 2572 Error *local_err = NULL; 2573 PCDIMMDevice *dimm = PC_DIMM(dev); 2574 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2575 MemoryRegion *mr = ddc->get_memory_region(dimm); 2576 uint64_t size = memory_region_size(mr); 2577 uint64_t addr; 2578 2579 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2580 if (local_err) { 2581 goto out; 2582 } 2583 2584 spapr_del_lmbs(dev, addr, size, &error_abort); 2585 out: 2586 error_propagate(errp, local_err); 2587 } 2588 2589 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 2590 sPAPRMachineState *spapr) 2591 { 2592 PowerPCCPU *cpu = POWERPC_CPU(cs); 2593 DeviceClass *dc = DEVICE_GET_CLASS(cs); 2594 int id = ppc_get_vcpu_dt_id(cpu); 2595 void *fdt; 2596 int offset, fdt_size; 2597 char *nodename; 2598 2599 fdt = create_device_tree(&fdt_size); 2600 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 2601 offset = fdt_add_subnode(fdt, 0, nodename); 2602 2603 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 2604 g_free(nodename); 2605 2606 *fdt_offset = offset; 2607 return fdt; 2608 } 2609 2610 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2611 Error **errp) 2612 { 2613 MachineState *ms = MACHINE(qdev_get_machine()); 2614 CPUCore *cc = CPU_CORE(dev); 2615 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 2616 2617 core_slot->cpu = NULL; 2618 object_unparent(OBJECT(dev)); 2619 } 2620 2621 static void spapr_core_release(DeviceState *dev, void *opaque) 2622 { 2623 HotplugHandler *hotplug_ctrl; 2624 2625 hotplug_ctrl = qdev_get_hotplug_handler(dev); 2626 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2627 } 2628 2629 static 2630 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 2631 Error **errp) 2632 { 2633 int index; 2634 sPAPRDRConnector *drc; 2635 sPAPRDRConnectorClass *drck; 2636 Error *local_err = NULL; 2637 CPUCore *cc = CPU_CORE(dev); 2638 int smt = kvmppc_smt_threads(); 2639 2640 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 2641 error_setg(errp, "Unable to find CPU core with core-id: %d", 2642 cc->core_id); 2643 return; 2644 } 2645 if (index == 0) { 2646 error_setg(errp, "Boot CPU core may not be unplugged"); 2647 return; 2648 } 2649 2650 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt); 2651 g_assert(drc); 2652 2653 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2654 drck->detach(drc, dev, spapr_core_release, NULL, &local_err); 2655 if (local_err) { 2656 error_propagate(errp, local_err); 2657 return; 2658 } 2659 2660 spapr_hotplug_req_remove_by_index(drc); 2661 } 2662 2663 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2664 Error **errp) 2665 { 2666 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 2667 MachineClass *mc = MACHINE_GET_CLASS(spapr); 2668 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 2669 CPUCore *cc = CPU_CORE(dev); 2670 CPUState *cs = CPU(core->threads); 2671 sPAPRDRConnector *drc; 2672 Error *local_err = NULL; 2673 void *fdt = NULL; 2674 int fdt_offset = 0; 2675 int smt = kvmppc_smt_threads(); 2676 CPUArchId *core_slot; 2677 int index; 2678 2679 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 2680 if (!core_slot) { 2681 error_setg(errp, "Unable to find CPU core with core-id: %d", 2682 cc->core_id); 2683 return; 2684 } 2685 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt); 2686 2687 g_assert(drc || !mc->has_hotpluggable_cpus); 2688 2689 /* 2690 * Setup CPU DT entries only for hotplugged CPUs. For boot time or 2691 * coldplugged CPUs DT entries are setup in spapr_build_fdt(). 2692 */ 2693 if (dev->hotplugged) { 2694 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 2695 } 2696 2697 if (drc) { 2698 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2699 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err); 2700 if (local_err) { 2701 g_free(fdt); 2702 error_propagate(errp, local_err); 2703 return; 2704 } 2705 } 2706 2707 if (dev->hotplugged) { 2708 /* 2709 * Send hotplug notification interrupt to the guest only in case 2710 * of hotplugged CPUs. 2711 */ 2712 spapr_hotplug_req_add_by_index(drc); 2713 } else { 2714 /* 2715 * Set the right DRC states for cold plugged CPU. 2716 */ 2717 if (drc) { 2718 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2719 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); 2720 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); 2721 } 2722 } 2723 core_slot->cpu = OBJECT(dev); 2724 } 2725 2726 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2727 Error **errp) 2728 { 2729 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 2730 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 2731 Error *local_err = NULL; 2732 CPUCore *cc = CPU_CORE(dev); 2733 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model); 2734 const char *type = object_get_typename(OBJECT(dev)); 2735 CPUArchId *core_slot; 2736 int index; 2737 2738 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 2739 error_setg(&local_err, "CPU hotplug not supported for this machine"); 2740 goto out; 2741 } 2742 2743 if (strcmp(base_core_type, type)) { 2744 error_setg(&local_err, "CPU core type should be %s", base_core_type); 2745 goto out; 2746 } 2747 2748 if (cc->core_id % smp_threads) { 2749 error_setg(&local_err, "invalid core id %d", cc->core_id); 2750 goto out; 2751 } 2752 2753 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 2754 if (!core_slot) { 2755 error_setg(&local_err, "core id %d out of range", cc->core_id); 2756 goto out; 2757 } 2758 2759 if (core_slot->cpu) { 2760 error_setg(&local_err, "core %d already populated", cc->core_id); 2761 goto out; 2762 } 2763 2764 out: 2765 g_free(base_core_type); 2766 error_propagate(errp, local_err); 2767 } 2768 2769 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 2770 DeviceState *dev, Error **errp) 2771 { 2772 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 2773 2774 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2775 int node; 2776 2777 if (!smc->dr_lmb_enabled) { 2778 error_setg(errp, "Memory hotplug not supported for this machine"); 2779 return; 2780 } 2781 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 2782 if (*errp) { 2783 return; 2784 } 2785 if (node < 0 || node >= MAX_NODES) { 2786 error_setg(errp, "Invaild node %d", node); 2787 return; 2788 } 2789 2790 /* 2791 * Currently PowerPC kernel doesn't allow hot-adding memory to 2792 * memory-less node, but instead will silently add the memory 2793 * to the first node that has some memory. This causes two 2794 * unexpected behaviours for the user. 2795 * 2796 * - Memory gets hotplugged to a different node than what the user 2797 * specified. 2798 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 2799 * to memory-less node, a reboot will set things accordingly 2800 * and the previously hotplugged memory now ends in the right node. 2801 * This appears as if some memory moved from one node to another. 2802 * 2803 * So until kernel starts supporting memory hotplug to memory-less 2804 * nodes, just prevent such attempts upfront in QEMU. 2805 */ 2806 if (nb_numa_nodes && !numa_info[node].node_mem) { 2807 error_setg(errp, "Can't hotplug memory to memory-less node %d", 2808 node); 2809 return; 2810 } 2811 2812 spapr_memory_plug(hotplug_dev, dev, node, errp); 2813 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2814 spapr_core_plug(hotplug_dev, dev, errp); 2815 } 2816 } 2817 2818 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 2819 DeviceState *dev, Error **errp) 2820 { 2821 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 2822 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 2823 2824 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2825 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 2826 spapr_memory_unplug(hotplug_dev, dev, errp); 2827 } else { 2828 error_setg(errp, "Memory hot unplug not supported for this guest"); 2829 } 2830 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2831 if (!mc->has_hotpluggable_cpus) { 2832 error_setg(errp, "CPU hot unplug not supported on this machine"); 2833 return; 2834 } 2835 spapr_core_unplug(hotplug_dev, dev, errp); 2836 } 2837 } 2838 2839 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 2840 DeviceState *dev, Error **errp) 2841 { 2842 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 2843 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 2844 2845 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2846 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 2847 spapr_memory_unplug_request(hotplug_dev, dev, errp); 2848 } else { 2849 /* NOTE: this means there is a window after guest reset, prior to 2850 * CAS negotiation, where unplug requests will fail due to the 2851 * capability not being detected yet. This is a bit different than 2852 * the case with PCI unplug, where the events will be queued and 2853 * eventually handled by the guest after boot 2854 */ 2855 error_setg(errp, "Memory hot unplug not supported for this guest"); 2856 } 2857 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2858 if (!mc->has_hotpluggable_cpus) { 2859 error_setg(errp, "CPU hot unplug not supported on this machine"); 2860 return; 2861 } 2862 spapr_core_unplug_request(hotplug_dev, dev, errp); 2863 } 2864 } 2865 2866 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 2867 DeviceState *dev, Error **errp) 2868 { 2869 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2870 spapr_core_pre_plug(hotplug_dev, dev, errp); 2871 } 2872 } 2873 2874 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 2875 DeviceState *dev) 2876 { 2877 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2878 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2879 return HOTPLUG_HANDLER(machine); 2880 } 2881 return NULL; 2882 } 2883 2884 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index) 2885 { 2886 /* Allocate to NUMA nodes on a "socket" basis (not that concept of 2887 * socket means much for the paravirtualized PAPR platform) */ 2888 return cpu_index / smp_threads / smp_cores; 2889 } 2890 2891 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 2892 { 2893 int i; 2894 int spapr_max_cores = max_cpus / smp_threads; 2895 MachineClass *mc = MACHINE_GET_CLASS(machine); 2896 2897 if (!mc->has_hotpluggable_cpus) { 2898 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 2899 } 2900 if (machine->possible_cpus) { 2901 assert(machine->possible_cpus->len == spapr_max_cores); 2902 return machine->possible_cpus; 2903 } 2904 2905 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2906 sizeof(CPUArchId) * spapr_max_cores); 2907 machine->possible_cpus->len = spapr_max_cores; 2908 for (i = 0; i < machine->possible_cpus->len; i++) { 2909 int core_id = i * smp_threads; 2910 2911 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 2912 machine->possible_cpus->cpus[i].arch_id = core_id; 2913 machine->possible_cpus->cpus[i].props.has_core_id = true; 2914 machine->possible_cpus->cpus[i].props.core_id = core_id; 2915 /* TODO: add 'has_node/node' here to describe 2916 to which node core belongs */ 2917 } 2918 return machine->possible_cpus; 2919 } 2920 2921 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 2922 uint64_t *buid, hwaddr *pio, 2923 hwaddr *mmio32, hwaddr *mmio64, 2924 unsigned n_dma, uint32_t *liobns, Error **errp) 2925 { 2926 /* 2927 * New-style PHB window placement. 2928 * 2929 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 2930 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 2931 * windows. 2932 * 2933 * Some guest kernels can't work with MMIO windows above 1<<46 2934 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 2935 * 2936 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 2937 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 2938 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 2939 * 1TiB 64-bit MMIO windows for each PHB. 2940 */ 2941 const uint64_t base_buid = 0x800000020000000ULL; 2942 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 2943 SPAPR_PCI_MEM64_WIN_SIZE - 1) 2944 int i; 2945 2946 /* Sanity check natural alignments */ 2947 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 2948 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 2949 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 2950 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 2951 /* Sanity check bounds */ 2952 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 2953 SPAPR_PCI_MEM32_WIN_SIZE); 2954 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 2955 SPAPR_PCI_MEM64_WIN_SIZE); 2956 2957 if (index >= SPAPR_MAX_PHBS) { 2958 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 2959 SPAPR_MAX_PHBS - 1); 2960 return; 2961 } 2962 2963 *buid = base_buid + index; 2964 for (i = 0; i < n_dma; ++i) { 2965 liobns[i] = SPAPR_PCI_LIOBN(index, i); 2966 } 2967 2968 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 2969 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 2970 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 2971 } 2972 2973 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 2974 { 2975 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 2976 2977 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 2978 } 2979 2980 static void spapr_ics_resend(XICSFabric *dev) 2981 { 2982 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 2983 2984 ics_resend(spapr->ics); 2985 } 2986 2987 static ICPState *spapr_icp_get(XICSFabric *xi, int server) 2988 { 2989 sPAPRMachineState *spapr = SPAPR_MACHINE(xi); 2990 2991 return (server < spapr->xics->nr_servers) ? &spapr->xics->ss[server] : 2992 NULL; 2993 } 2994 2995 static void spapr_icp_resend(XICSFabric *xi) 2996 { 2997 sPAPRMachineState *spapr = SPAPR_MACHINE(xi); 2998 int i; 2999 3000 for (i = 0; i < spapr->xics->nr_servers; i++) { 3001 icp_resend(&spapr->xics->ss[i]); 3002 } 3003 } 3004 3005 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3006 { 3007 MachineClass *mc = MACHINE_CLASS(oc); 3008 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3009 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3010 NMIClass *nc = NMI_CLASS(oc); 3011 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3012 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3013 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3014 3015 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3016 3017 /* 3018 * We set up the default / latest behaviour here. The class_init 3019 * functions for the specific versioned machine types can override 3020 * these details for backwards compatibility 3021 */ 3022 mc->init = ppc_spapr_init; 3023 mc->reset = ppc_spapr_reset; 3024 mc->block_default_type = IF_SCSI; 3025 mc->max_cpus = 1024; 3026 mc->no_parallel = 1; 3027 mc->default_boot_order = ""; 3028 mc->default_ram_size = 512 * M_BYTE; 3029 mc->kvm_type = spapr_kvm_type; 3030 mc->has_dynamic_sysbus = true; 3031 mc->pci_allow_0_address = true; 3032 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3033 hc->pre_plug = spapr_machine_device_pre_plug; 3034 hc->plug = spapr_machine_device_plug; 3035 hc->unplug = spapr_machine_device_unplug; 3036 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id; 3037 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3038 hc->unplug_request = spapr_machine_device_unplug_request; 3039 3040 smc->dr_lmb_enabled = true; 3041 smc->tcg_default_cpu = "POWER8"; 3042 mc->has_hotpluggable_cpus = true; 3043 fwc->get_dev_path = spapr_get_fw_dev_path; 3044 nc->nmi_monitor_handler = spapr_nmi; 3045 smc->phb_placement = spapr_phb_placement; 3046 vhc->hypercall = emulate_spapr_hypercall; 3047 vhc->hpt_mask = spapr_hpt_mask; 3048 vhc->map_hptes = spapr_map_hptes; 3049 vhc->unmap_hptes = spapr_unmap_hptes; 3050 vhc->store_hpte = spapr_store_hpte; 3051 xic->ics_get = spapr_ics_get; 3052 xic->ics_resend = spapr_ics_resend; 3053 xic->icp_get = spapr_icp_get; 3054 xic->icp_resend = spapr_icp_resend; 3055 } 3056 3057 static const TypeInfo spapr_machine_info = { 3058 .name = TYPE_SPAPR_MACHINE, 3059 .parent = TYPE_MACHINE, 3060 .abstract = true, 3061 .instance_size = sizeof(sPAPRMachineState), 3062 .instance_init = spapr_machine_initfn, 3063 .instance_finalize = spapr_machine_finalizefn, 3064 .class_size = sizeof(sPAPRMachineClass), 3065 .class_init = spapr_machine_class_init, 3066 .interfaces = (InterfaceInfo[]) { 3067 { TYPE_FW_PATH_PROVIDER }, 3068 { TYPE_NMI }, 3069 { TYPE_HOTPLUG_HANDLER }, 3070 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 3071 { TYPE_XICS_FABRIC }, 3072 { } 3073 }, 3074 }; 3075 3076 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 3077 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 3078 void *data) \ 3079 { \ 3080 MachineClass *mc = MACHINE_CLASS(oc); \ 3081 spapr_machine_##suffix##_class_options(mc); \ 3082 if (latest) { \ 3083 mc->alias = "pseries"; \ 3084 mc->is_default = 1; \ 3085 } \ 3086 } \ 3087 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 3088 { \ 3089 MachineState *machine = MACHINE(obj); \ 3090 spapr_machine_##suffix##_instance_options(machine); \ 3091 } \ 3092 static const TypeInfo spapr_machine_##suffix##_info = { \ 3093 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 3094 .parent = TYPE_SPAPR_MACHINE, \ 3095 .class_init = spapr_machine_##suffix##_class_init, \ 3096 .instance_init = spapr_machine_##suffix##_instance_init, \ 3097 }; \ 3098 static void spapr_machine_register_##suffix(void) \ 3099 { \ 3100 type_register(&spapr_machine_##suffix##_info); \ 3101 } \ 3102 type_init(spapr_machine_register_##suffix) 3103 3104 /* 3105 * pseries-2.9 3106 */ 3107 static void spapr_machine_2_9_instance_options(MachineState *machine) 3108 { 3109 } 3110 3111 static void spapr_machine_2_9_class_options(MachineClass *mc) 3112 { 3113 /* Defaults for the latest behaviour inherited from the base class */ 3114 } 3115 3116 DEFINE_SPAPR_MACHINE(2_9, "2.9", true); 3117 3118 /* 3119 * pseries-2.8 3120 */ 3121 #define SPAPR_COMPAT_2_8 \ 3122 HW_COMPAT_2_8 3123 3124 static void spapr_machine_2_8_instance_options(MachineState *machine) 3125 { 3126 spapr_machine_2_9_instance_options(machine); 3127 } 3128 3129 static void spapr_machine_2_8_class_options(MachineClass *mc) 3130 { 3131 spapr_machine_2_9_class_options(mc); 3132 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 3133 } 3134 3135 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 3136 3137 /* 3138 * pseries-2.7 3139 */ 3140 #define SPAPR_COMPAT_2_7 \ 3141 HW_COMPAT_2_7 \ 3142 { \ 3143 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3144 .property = "mem_win_size", \ 3145 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 3146 }, \ 3147 { \ 3148 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3149 .property = "mem64_win_size", \ 3150 .value = "0", \ 3151 }, \ 3152 { \ 3153 .driver = TYPE_POWERPC_CPU, \ 3154 .property = "pre-2.8-migration", \ 3155 .value = "on", \ 3156 }, \ 3157 { \ 3158 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3159 .property = "pre-2.8-migration", \ 3160 .value = "on", \ 3161 }, 3162 3163 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 3164 uint64_t *buid, hwaddr *pio, 3165 hwaddr *mmio32, hwaddr *mmio64, 3166 unsigned n_dma, uint32_t *liobns, Error **errp) 3167 { 3168 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 3169 const uint64_t base_buid = 0x800000020000000ULL; 3170 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 3171 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 3172 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 3173 const uint32_t max_index = 255; 3174 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 3175 3176 uint64_t ram_top = MACHINE(spapr)->ram_size; 3177 hwaddr phb0_base, phb_base; 3178 int i; 3179 3180 /* Do we have hotpluggable memory? */ 3181 if (MACHINE(spapr)->maxram_size > ram_top) { 3182 /* Can't just use maxram_size, because there may be an 3183 * alignment gap between normal and hotpluggable memory 3184 * regions */ 3185 ram_top = spapr->hotplug_memory.base + 3186 memory_region_size(&spapr->hotplug_memory.mr); 3187 } 3188 3189 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 3190 3191 if (index > max_index) { 3192 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 3193 max_index); 3194 return; 3195 } 3196 3197 *buid = base_buid + index; 3198 for (i = 0; i < n_dma; ++i) { 3199 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3200 } 3201 3202 phb_base = phb0_base + index * phb_spacing; 3203 *pio = phb_base + pio_offset; 3204 *mmio32 = phb_base + mmio_offset; 3205 /* 3206 * We don't set the 64-bit MMIO window, relying on the PHB's 3207 * fallback behaviour of automatically splitting a large "32-bit" 3208 * window into contiguous 32-bit and 64-bit windows 3209 */ 3210 } 3211 3212 static void spapr_machine_2_7_instance_options(MachineState *machine) 3213 { 3214 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 3215 3216 spapr_machine_2_8_instance_options(machine); 3217 spapr->use_hotplug_event_source = false; 3218 } 3219 3220 static void spapr_machine_2_7_class_options(MachineClass *mc) 3221 { 3222 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3223 3224 spapr_machine_2_8_class_options(mc); 3225 smc->tcg_default_cpu = "POWER7"; 3226 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 3227 smc->phb_placement = phb_placement_2_7; 3228 } 3229 3230 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 3231 3232 /* 3233 * pseries-2.6 3234 */ 3235 #define SPAPR_COMPAT_2_6 \ 3236 HW_COMPAT_2_6 \ 3237 { \ 3238 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3239 .property = "ddw",\ 3240 .value = stringify(off),\ 3241 }, 3242 3243 static void spapr_machine_2_6_instance_options(MachineState *machine) 3244 { 3245 spapr_machine_2_7_instance_options(machine); 3246 } 3247 3248 static void spapr_machine_2_6_class_options(MachineClass *mc) 3249 { 3250 spapr_machine_2_7_class_options(mc); 3251 mc->has_hotpluggable_cpus = false; 3252 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 3253 } 3254 3255 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 3256 3257 /* 3258 * pseries-2.5 3259 */ 3260 #define SPAPR_COMPAT_2_5 \ 3261 HW_COMPAT_2_5 \ 3262 { \ 3263 .driver = "spapr-vlan", \ 3264 .property = "use-rx-buffer-pools", \ 3265 .value = "off", \ 3266 }, 3267 3268 static void spapr_machine_2_5_instance_options(MachineState *machine) 3269 { 3270 spapr_machine_2_6_instance_options(machine); 3271 } 3272 3273 static void spapr_machine_2_5_class_options(MachineClass *mc) 3274 { 3275 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3276 3277 spapr_machine_2_6_class_options(mc); 3278 smc->use_ohci_by_default = true; 3279 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 3280 } 3281 3282 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 3283 3284 /* 3285 * pseries-2.4 3286 */ 3287 #define SPAPR_COMPAT_2_4 \ 3288 HW_COMPAT_2_4 3289 3290 static void spapr_machine_2_4_instance_options(MachineState *machine) 3291 { 3292 spapr_machine_2_5_instance_options(machine); 3293 } 3294 3295 static void spapr_machine_2_4_class_options(MachineClass *mc) 3296 { 3297 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3298 3299 spapr_machine_2_5_class_options(mc); 3300 smc->dr_lmb_enabled = false; 3301 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 3302 } 3303 3304 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 3305 3306 /* 3307 * pseries-2.3 3308 */ 3309 #define SPAPR_COMPAT_2_3 \ 3310 HW_COMPAT_2_3 \ 3311 {\ 3312 .driver = "spapr-pci-host-bridge",\ 3313 .property = "dynamic-reconfiguration",\ 3314 .value = "off",\ 3315 }, 3316 3317 static void spapr_machine_2_3_instance_options(MachineState *machine) 3318 { 3319 spapr_machine_2_4_instance_options(machine); 3320 savevm_skip_section_footers(); 3321 global_state_set_optional(); 3322 savevm_skip_configuration(); 3323 } 3324 3325 static void spapr_machine_2_3_class_options(MachineClass *mc) 3326 { 3327 spapr_machine_2_4_class_options(mc); 3328 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 3329 } 3330 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 3331 3332 /* 3333 * pseries-2.2 3334 */ 3335 3336 #define SPAPR_COMPAT_2_2 \ 3337 HW_COMPAT_2_2 \ 3338 {\ 3339 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3340 .property = "mem_win_size",\ 3341 .value = "0x20000000",\ 3342 }, 3343 3344 static void spapr_machine_2_2_instance_options(MachineState *machine) 3345 { 3346 spapr_machine_2_3_instance_options(machine); 3347 machine->suppress_vmdesc = true; 3348 } 3349 3350 static void spapr_machine_2_2_class_options(MachineClass *mc) 3351 { 3352 spapr_machine_2_3_class_options(mc); 3353 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 3354 } 3355 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 3356 3357 /* 3358 * pseries-2.1 3359 */ 3360 #define SPAPR_COMPAT_2_1 \ 3361 HW_COMPAT_2_1 3362 3363 static void spapr_machine_2_1_instance_options(MachineState *machine) 3364 { 3365 spapr_machine_2_2_instance_options(machine); 3366 } 3367 3368 static void spapr_machine_2_1_class_options(MachineClass *mc) 3369 { 3370 spapr_machine_2_2_class_options(mc); 3371 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 3372 } 3373 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 3374 3375 static void spapr_machine_register_types(void) 3376 { 3377 type_register_static(&spapr_machine_info); 3378 } 3379 3380 type_init(spapr_machine_register_types) 3381