1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "sysemu/sysemu.h" 28 #include "sysemu/numa.h" 29 #include "hw/hw.h" 30 #include "hw/fw-path-provider.h" 31 #include "elf.h" 32 #include "net/net.h" 33 #include "sysemu/block-backend.h" 34 #include "sysemu/cpus.h" 35 #include "sysemu/kvm.h" 36 #include "kvm_ppc.h" 37 #include "migration/migration.h" 38 #include "mmu-hash64.h" 39 #include "qom/cpu.h" 40 41 #include "hw/boards.h" 42 #include "hw/ppc/ppc.h" 43 #include "hw/loader.h" 44 45 #include "hw/ppc/spapr.h" 46 #include "hw/ppc/spapr_vio.h" 47 #include "hw/pci-host/spapr.h" 48 #include "hw/ppc/xics.h" 49 #include "hw/pci/msi.h" 50 51 #include "hw/pci/pci.h" 52 #include "hw/scsi/scsi.h" 53 #include "hw/virtio/virtio-scsi.h" 54 55 #include "exec/address-spaces.h" 56 #include "hw/usb.h" 57 #include "qemu/config-file.h" 58 #include "qemu/error-report.h" 59 #include "trace.h" 60 #include "hw/nmi.h" 61 62 #include "hw/compat.h" 63 64 #include <libfdt.h> 65 66 /* SLOF memory layout: 67 * 68 * SLOF raw image loaded at 0, copies its romfs right below the flat 69 * device-tree, then position SLOF itself 31M below that 70 * 71 * So we set FW_OVERHEAD to 40MB which should account for all of that 72 * and more 73 * 74 * We load our kernel at 4M, leaving space for SLOF initial image 75 */ 76 #define FDT_MAX_SIZE 0x40000 77 #define RTAS_MAX_SIZE 0x10000 78 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 79 #define FW_MAX_SIZE 0x400000 80 #define FW_FILE_NAME "slof.bin" 81 #define FW_OVERHEAD 0x2800000 82 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 83 84 #define MIN_RMA_SLOF 128UL 85 86 #define TIMEBASE_FREQ 512000000ULL 87 88 #define MAX_CPUS 255 89 90 #define PHANDLE_XICP 0x00001111 91 92 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 93 94 static XICSState *try_create_xics(const char *type, int nr_servers, 95 int nr_irqs, Error **errp) 96 { 97 Error *err = NULL; 98 DeviceState *dev; 99 100 dev = qdev_create(NULL, type); 101 qdev_prop_set_uint32(dev, "nr_servers", nr_servers); 102 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); 103 object_property_set_bool(OBJECT(dev), true, "realized", &err); 104 if (err) { 105 error_propagate(errp, err); 106 object_unparent(OBJECT(dev)); 107 return NULL; 108 } 109 return XICS_COMMON(dev); 110 } 111 112 static XICSState *xics_system_init(MachineState *machine, 113 int nr_servers, int nr_irqs) 114 { 115 XICSState *icp = NULL; 116 117 if (kvm_enabled()) { 118 Error *err = NULL; 119 120 if (machine_kernel_irqchip_allowed(machine)) { 121 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs, &err); 122 } 123 if (machine_kernel_irqchip_required(machine) && !icp) { 124 error_report("kernel_irqchip requested but unavailable: %s", 125 error_get_pretty(err)); 126 } 127 } 128 129 if (!icp) { 130 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs, &error_abort); 131 } 132 133 return icp; 134 } 135 136 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 137 int smt_threads) 138 { 139 int i, ret = 0; 140 uint32_t servers_prop[smt_threads]; 141 uint32_t gservers_prop[smt_threads * 2]; 142 int index = ppc_get_vcpu_dt_id(cpu); 143 144 if (cpu->cpu_version) { 145 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version); 146 if (ret < 0) { 147 return ret; 148 } 149 } 150 151 /* Build interrupt servers and gservers properties */ 152 for (i = 0; i < smt_threads; i++) { 153 servers_prop[i] = cpu_to_be32(index + i); 154 /* Hack, direct the group queues back to cpu 0 */ 155 gservers_prop[i*2] = cpu_to_be32(index + i); 156 gservers_prop[i*2 + 1] = 0; 157 } 158 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 159 servers_prop, sizeof(servers_prop)); 160 if (ret < 0) { 161 return ret; 162 } 163 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 164 gservers_prop, sizeof(gservers_prop)); 165 166 return ret; 167 } 168 169 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs) 170 { 171 int ret = 0; 172 PowerPCCPU *cpu = POWERPC_CPU(cs); 173 int index = ppc_get_vcpu_dt_id(cpu); 174 uint32_t associativity[] = {cpu_to_be32(0x5), 175 cpu_to_be32(0x0), 176 cpu_to_be32(0x0), 177 cpu_to_be32(0x0), 178 cpu_to_be32(cs->numa_node), 179 cpu_to_be32(index)}; 180 181 /* Advertise NUMA via ibm,associativity */ 182 if (nb_numa_nodes > 1) { 183 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 184 sizeof(associativity)); 185 } 186 187 return ret; 188 } 189 190 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 191 { 192 int ret = 0, offset, cpus_offset; 193 CPUState *cs; 194 char cpu_model[32]; 195 int smt = kvmppc_smt_threads(); 196 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 197 198 CPU_FOREACH(cs) { 199 PowerPCCPU *cpu = POWERPC_CPU(cs); 200 DeviceClass *dc = DEVICE_GET_CLASS(cs); 201 int index = ppc_get_vcpu_dt_id(cpu); 202 203 if ((index % smt) != 0) { 204 continue; 205 } 206 207 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 208 209 cpus_offset = fdt_path_offset(fdt, "/cpus"); 210 if (cpus_offset < 0) { 211 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 212 "cpus"); 213 if (cpus_offset < 0) { 214 return cpus_offset; 215 } 216 } 217 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 218 if (offset < 0) { 219 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 220 if (offset < 0) { 221 return offset; 222 } 223 } 224 225 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 226 pft_size_prop, sizeof(pft_size_prop)); 227 if (ret < 0) { 228 return ret; 229 } 230 231 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs); 232 if (ret < 0) { 233 return ret; 234 } 235 236 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 237 ppc_get_compat_smt_threads(cpu)); 238 if (ret < 0) { 239 return ret; 240 } 241 } 242 return ret; 243 } 244 245 246 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, 247 size_t maxsize) 248 { 249 size_t maxcells = maxsize / sizeof(uint32_t); 250 int i, j, count; 251 uint32_t *p = prop; 252 253 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 254 struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; 255 256 if (!sps->page_shift) { 257 break; 258 } 259 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { 260 if (sps->enc[count].page_shift == 0) { 261 break; 262 } 263 } 264 if ((p - prop) >= (maxcells - 3 - count * 2)) { 265 break; 266 } 267 *(p++) = cpu_to_be32(sps->page_shift); 268 *(p++) = cpu_to_be32(sps->slb_enc); 269 *(p++) = cpu_to_be32(count); 270 for (j = 0; j < count; j++) { 271 *(p++) = cpu_to_be32(sps->enc[j].page_shift); 272 *(p++) = cpu_to_be32(sps->enc[j].pte_enc); 273 } 274 } 275 276 return (p - prop) * sizeof(uint32_t); 277 } 278 279 static hwaddr spapr_node0_size(void) 280 { 281 MachineState *machine = MACHINE(qdev_get_machine()); 282 283 if (nb_numa_nodes) { 284 int i; 285 for (i = 0; i < nb_numa_nodes; ++i) { 286 if (numa_info[i].node_mem) { 287 return MIN(pow2floor(numa_info[i].node_mem), 288 machine->ram_size); 289 } 290 } 291 } 292 return machine->ram_size; 293 } 294 295 #define _FDT(exp) \ 296 do { \ 297 int ret = (exp); \ 298 if (ret < 0) { \ 299 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ 300 #exp, fdt_strerror(ret)); \ 301 exit(1); \ 302 } \ 303 } while (0) 304 305 static void add_str(GString *s, const gchar *s1) 306 { 307 g_string_append_len(s, s1, strlen(s1) + 1); 308 } 309 310 static void *spapr_create_fdt_skel(hwaddr initrd_base, 311 hwaddr initrd_size, 312 hwaddr kernel_size, 313 bool little_endian, 314 const char *kernel_cmdline, 315 uint32_t epow_irq) 316 { 317 void *fdt; 318 uint32_t start_prop = cpu_to_be32(initrd_base); 319 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); 320 GString *hypertas = g_string_sized_new(256); 321 GString *qemu_hypertas = g_string_sized_new(256); 322 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; 323 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)}; 324 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; 325 char *buf; 326 327 add_str(hypertas, "hcall-pft"); 328 add_str(hypertas, "hcall-term"); 329 add_str(hypertas, "hcall-dabr"); 330 add_str(hypertas, "hcall-interrupt"); 331 add_str(hypertas, "hcall-tce"); 332 add_str(hypertas, "hcall-vio"); 333 add_str(hypertas, "hcall-splpar"); 334 add_str(hypertas, "hcall-bulk"); 335 add_str(hypertas, "hcall-set-mode"); 336 add_str(qemu_hypertas, "hcall-memop1"); 337 338 fdt = g_malloc0(FDT_MAX_SIZE); 339 _FDT((fdt_create(fdt, FDT_MAX_SIZE))); 340 341 if (kernel_size) { 342 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); 343 } 344 if (initrd_size) { 345 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); 346 } 347 _FDT((fdt_finish_reservemap(fdt))); 348 349 /* Root node */ 350 _FDT((fdt_begin_node(fdt, ""))); 351 _FDT((fdt_property_string(fdt, "device_type", "chrp"))); 352 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); 353 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); 354 355 /* 356 * Add info to guest to indentify which host is it being run on 357 * and what is the uuid of the guest 358 */ 359 if (kvmppc_get_host_model(&buf)) { 360 _FDT((fdt_property_string(fdt, "host-model", buf))); 361 g_free(buf); 362 } 363 if (kvmppc_get_host_serial(&buf)) { 364 _FDT((fdt_property_string(fdt, "host-serial", buf))); 365 g_free(buf); 366 } 367 368 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1], 369 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4], 370 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7], 371 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10], 372 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13], 373 qemu_uuid[14], qemu_uuid[15]); 374 375 _FDT((fdt_property_string(fdt, "vm,uuid", buf))); 376 g_free(buf); 377 378 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); 379 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); 380 381 /* /chosen */ 382 _FDT((fdt_begin_node(fdt, "chosen"))); 383 384 /* Set Form1_affinity */ 385 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); 386 387 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); 388 _FDT((fdt_property(fdt, "linux,initrd-start", 389 &start_prop, sizeof(start_prop)))); 390 _FDT((fdt_property(fdt, "linux,initrd-end", 391 &end_prop, sizeof(end_prop)))); 392 if (kernel_size) { 393 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 394 cpu_to_be64(kernel_size) }; 395 396 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); 397 if (little_endian) { 398 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); 399 } 400 } 401 if (boot_menu) { 402 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu))); 403 } 404 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); 405 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); 406 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); 407 408 _FDT((fdt_end_node(fdt))); 409 410 /* RTAS */ 411 _FDT((fdt_begin_node(fdt, "rtas"))); 412 413 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 414 add_str(hypertas, "hcall-multi-tce"); 415 } 416 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str, 417 hypertas->len))); 418 g_string_free(hypertas, TRUE); 419 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str, 420 qemu_hypertas->len))); 421 g_string_free(qemu_hypertas, TRUE); 422 423 _FDT((fdt_property(fdt, "ibm,associativity-reference-points", 424 refpoints, sizeof(refpoints)))); 425 426 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); 427 _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate", 428 RTAS_EVENT_SCAN_RATE))); 429 430 /* 431 * According to PAPR, rtas ibm,os-term does not guarantee a return 432 * back to the guest cpu. 433 * 434 * While an additional ibm,extended-os-term property indicates that 435 * rtas call return will always occur. Set this property. 436 */ 437 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0))); 438 439 _FDT((fdt_end_node(fdt))); 440 441 /* interrupt controller */ 442 _FDT((fdt_begin_node(fdt, "interrupt-controller"))); 443 444 _FDT((fdt_property_string(fdt, "device_type", 445 "PowerPC-External-Interrupt-Presentation"))); 446 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); 447 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 448 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", 449 interrupt_server_ranges_prop, 450 sizeof(interrupt_server_ranges_prop)))); 451 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); 452 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); 453 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); 454 455 _FDT((fdt_end_node(fdt))); 456 457 /* vdevice */ 458 _FDT((fdt_begin_node(fdt, "vdevice"))); 459 460 _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); 461 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); 462 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 463 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 464 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); 465 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 466 467 _FDT((fdt_end_node(fdt))); 468 469 /* event-sources */ 470 spapr_events_fdt_skel(fdt, epow_irq); 471 472 /* /hypervisor node */ 473 if (kvm_enabled()) { 474 uint8_t hypercall[16]; 475 476 /* indicate KVM hypercall interface */ 477 _FDT((fdt_begin_node(fdt, "hypervisor"))); 478 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm"))); 479 if (kvmppc_has_cap_fixup_hcalls()) { 480 /* 481 * Older KVM versions with older guest kernels were broken with the 482 * magic page, don't allow the guest to map it. 483 */ 484 kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 485 sizeof(hypercall)); 486 _FDT((fdt_property(fdt, "hcall-instructions", hypercall, 487 sizeof(hypercall)))); 488 } 489 _FDT((fdt_end_node(fdt))); 490 } 491 492 _FDT((fdt_end_node(fdt))); /* close root node */ 493 _FDT((fdt_finish(fdt))); 494 495 return fdt; 496 } 497 498 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 499 target_ulong addr, target_ulong size) 500 { 501 void *fdt, *fdt_skel; 502 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 503 504 size -= sizeof(hdr); 505 506 /* Create sceleton */ 507 fdt_skel = g_malloc0(size); 508 _FDT((fdt_create(fdt_skel, size))); 509 _FDT((fdt_begin_node(fdt_skel, ""))); 510 _FDT((fdt_end_node(fdt_skel))); 511 _FDT((fdt_finish(fdt_skel))); 512 fdt = g_malloc0(size); 513 _FDT((fdt_open_into(fdt_skel, fdt, size))); 514 g_free(fdt_skel); 515 516 /* Fix skeleton up */ 517 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 518 519 /* Pack resulting tree */ 520 _FDT((fdt_pack(fdt))); 521 522 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 523 trace_spapr_cas_failed(size); 524 return -1; 525 } 526 527 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 528 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 529 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 530 g_free(fdt); 531 532 return 0; 533 } 534 535 static void spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 536 hwaddr size) 537 { 538 uint32_t associativity[] = { 539 cpu_to_be32(0x4), /* length */ 540 cpu_to_be32(0x0), cpu_to_be32(0x0), 541 cpu_to_be32(0x0), cpu_to_be32(nodeid) 542 }; 543 char mem_name[32]; 544 uint64_t mem_reg_property[2]; 545 int off; 546 547 mem_reg_property[0] = cpu_to_be64(start); 548 mem_reg_property[1] = cpu_to_be64(size); 549 550 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 551 off = fdt_add_subnode(fdt, 0, mem_name); 552 _FDT(off); 553 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 554 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 555 sizeof(mem_reg_property)))); 556 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 557 sizeof(associativity)))); 558 } 559 560 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 561 { 562 MachineState *machine = MACHINE(spapr); 563 hwaddr mem_start, node_size; 564 int i, nb_nodes = nb_numa_nodes; 565 NodeInfo *nodes = numa_info; 566 NodeInfo ramnode; 567 568 /* No NUMA nodes, assume there is just one node with whole RAM */ 569 if (!nb_numa_nodes) { 570 nb_nodes = 1; 571 ramnode.node_mem = machine->ram_size; 572 nodes = &ramnode; 573 } 574 575 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 576 if (!nodes[i].node_mem) { 577 continue; 578 } 579 if (mem_start >= machine->ram_size) { 580 node_size = 0; 581 } else { 582 node_size = nodes[i].node_mem; 583 if (node_size > machine->ram_size - mem_start) { 584 node_size = machine->ram_size - mem_start; 585 } 586 } 587 if (!mem_start) { 588 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 589 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 590 mem_start += spapr->rma_size; 591 node_size -= spapr->rma_size; 592 } 593 for ( ; node_size; ) { 594 hwaddr sizetmp = pow2floor(node_size); 595 596 /* mem_start != 0 here */ 597 if (ctzl(mem_start) < ctzl(sizetmp)) { 598 sizetmp = 1ULL << ctzl(mem_start); 599 } 600 601 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 602 node_size -= sizetmp; 603 mem_start += sizetmp; 604 } 605 } 606 607 return 0; 608 } 609 610 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 611 sPAPRMachineState *spapr) 612 { 613 PowerPCCPU *cpu = POWERPC_CPU(cs); 614 CPUPPCState *env = &cpu->env; 615 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 616 int index = ppc_get_vcpu_dt_id(cpu); 617 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 618 0xffffffff, 0xffffffff}; 619 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; 620 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 621 uint32_t page_sizes_prop[64]; 622 size_t page_sizes_prop_size; 623 QemuOpts *opts = qemu_opts_find(qemu_find_opts("smp-opts"), NULL); 624 unsigned sockets = opts ? qemu_opt_get_number(opts, "sockets", 0) : 0; 625 uint32_t cpus_per_socket = sockets ? (smp_cpus / sockets) : 1; 626 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 627 628 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 629 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 630 631 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 632 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 633 env->dcache_line_size))); 634 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 635 env->dcache_line_size))); 636 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 637 env->icache_line_size))); 638 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 639 env->icache_line_size))); 640 641 if (pcc->l1_dcache_size) { 642 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 643 pcc->l1_dcache_size))); 644 } else { 645 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); 646 } 647 if (pcc->l1_icache_size) { 648 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 649 pcc->l1_icache_size))); 650 } else { 651 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); 652 } 653 654 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 655 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 656 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 657 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 658 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 659 660 if (env->spr_cb[SPR_PURR].oea_read) { 661 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 662 } 663 664 if (env->mmu_model & POWERPC_MMU_1TSEG) { 665 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 666 segs, sizeof(segs)))); 667 } 668 669 /* Advertise VMX/VSX (vector extensions) if available 670 * 0 / no property == no vector extensions 671 * 1 == VMX / Altivec available 672 * 2 == VSX available */ 673 if (env->insns_flags & PPC_ALTIVEC) { 674 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 675 676 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 677 } 678 679 /* Advertise DFP (Decimal Floating Point) if available 680 * 0 / no property == no DFP 681 * 1 == DFP available */ 682 if (env->insns_flags2 & PPC2_DFP) { 683 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 684 } 685 686 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, 687 sizeof(page_sizes_prop)); 688 if (page_sizes_prop_size) { 689 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 690 page_sizes_prop, page_sizes_prop_size))); 691 } 692 693 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 694 cs->cpu_index / cpus_per_socket))); 695 696 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 697 pft_size_prop, sizeof(pft_size_prop)))); 698 699 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs)); 700 701 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 702 ppc_get_compat_smt_threads(cpu))); 703 } 704 705 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 706 { 707 CPUState *cs; 708 int cpus_offset; 709 char *nodename; 710 int smt = kvmppc_smt_threads(); 711 712 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 713 _FDT(cpus_offset); 714 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 715 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 716 717 /* 718 * We walk the CPUs in reverse order to ensure that CPU DT nodes 719 * created by fdt_add_subnode() end up in the right order in FDT 720 * for the guest kernel the enumerate the CPUs correctly. 721 */ 722 CPU_FOREACH_REVERSE(cs) { 723 PowerPCCPU *cpu = POWERPC_CPU(cs); 724 int index = ppc_get_vcpu_dt_id(cpu); 725 DeviceClass *dc = DEVICE_GET_CLASS(cs); 726 int offset; 727 728 if ((index % smt) != 0) { 729 continue; 730 } 731 732 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 733 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 734 g_free(nodename); 735 _FDT(offset); 736 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 737 } 738 739 } 740 741 static void spapr_finalize_fdt(sPAPRMachineState *spapr, 742 hwaddr fdt_addr, 743 hwaddr rtas_addr, 744 hwaddr rtas_size) 745 { 746 MachineState *machine = MACHINE(qdev_get_machine()); 747 const char *boot_device = machine->boot_order; 748 int ret, i; 749 size_t cb = 0; 750 char *bootlist; 751 void *fdt; 752 sPAPRPHBState *phb; 753 754 fdt = g_malloc(FDT_MAX_SIZE); 755 756 /* open out the base tree into a temp buffer for the final tweaks */ 757 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); 758 759 ret = spapr_populate_memory(spapr, fdt); 760 if (ret < 0) { 761 fprintf(stderr, "couldn't setup memory nodes in fdt\n"); 762 exit(1); 763 } 764 765 ret = spapr_populate_vdevice(spapr->vio_bus, fdt); 766 if (ret < 0) { 767 fprintf(stderr, "couldn't setup vio devices in fdt\n"); 768 exit(1); 769 } 770 771 QLIST_FOREACH(phb, &spapr->phbs, list) { 772 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 773 } 774 775 if (ret < 0) { 776 fprintf(stderr, "couldn't setup PCI devices in fdt\n"); 777 exit(1); 778 } 779 780 /* RTAS */ 781 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); 782 if (ret < 0) { 783 fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); 784 } 785 786 /* cpus */ 787 spapr_populate_cpus_dt_node(fdt, spapr); 788 789 bootlist = get_boot_devices_list(&cb, true); 790 if (cb && bootlist) { 791 int offset = fdt_path_offset(fdt, "/chosen"); 792 if (offset < 0) { 793 exit(1); 794 } 795 for (i = 0; i < cb; i++) { 796 if (bootlist[i] == '\n') { 797 bootlist[i] = ' '; 798 } 799 800 } 801 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist); 802 } 803 804 if (boot_device && strlen(boot_device)) { 805 int offset = fdt_path_offset(fdt, "/chosen"); 806 807 if (offset < 0) { 808 exit(1); 809 } 810 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device); 811 } 812 813 if (!spapr->has_graphics) { 814 spapr_populate_chosen_stdout(fdt, spapr->vio_bus); 815 } 816 817 _FDT((fdt_pack(fdt))); 818 819 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 820 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 821 fdt_totalsize(fdt), FDT_MAX_SIZE); 822 exit(1); 823 } 824 825 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 826 827 g_free(bootlist); 828 g_free(fdt); 829 } 830 831 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 832 { 833 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 834 } 835 836 static void emulate_spapr_hypercall(PowerPCCPU *cpu) 837 { 838 CPUPPCState *env = &cpu->env; 839 840 if (msr_pr) { 841 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 842 env->gpr[3] = H_PRIVILEGE; 843 } else { 844 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 845 } 846 } 847 848 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 849 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 850 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 851 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 852 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 853 854 static void spapr_reset_htab(sPAPRMachineState *spapr) 855 { 856 long shift; 857 int index; 858 859 /* allocate hash page table. For now we always make this 16mb, 860 * later we should probably make it scale to the size of guest 861 * RAM */ 862 863 shift = kvmppc_reset_htab(spapr->htab_shift); 864 865 if (shift > 0) { 866 /* Kernel handles htab, we don't need to allocate one */ 867 spapr->htab_shift = shift; 868 kvmppc_kern_htab = true; 869 870 /* Tell readers to update their file descriptor */ 871 if (spapr->htab_fd >= 0) { 872 spapr->htab_fd_stale = true; 873 } 874 } else { 875 if (!spapr->htab) { 876 /* Allocate an htab if we don't yet have one */ 877 spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); 878 } 879 880 /* And clear it */ 881 memset(spapr->htab, 0, HTAB_SIZE(spapr)); 882 883 for (index = 0; index < HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; index++) { 884 DIRTY_HPTE(HPTE(spapr->htab, index)); 885 } 886 } 887 888 /* Update the RMA size if necessary */ 889 if (spapr->vrma_adjust) { 890 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 891 spapr->htab_shift); 892 } 893 } 894 895 static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 896 { 897 bool matched = false; 898 899 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 900 matched = true; 901 } 902 903 if (!matched) { 904 error_report("Device %s is not supported by this machine yet.", 905 qdev_fw_name(DEVICE(sbdev))); 906 exit(1); 907 } 908 909 return 0; 910 } 911 912 /* 913 * A guest reset will cause spapr->htab_fd to become stale if being used. 914 * Reopen the file descriptor to make sure the whole HTAB is properly read. 915 */ 916 static int spapr_check_htab_fd(sPAPRMachineState *spapr) 917 { 918 int rc = 0; 919 920 if (spapr->htab_fd_stale) { 921 close(spapr->htab_fd); 922 spapr->htab_fd = kvmppc_get_htab_fd(false); 923 if (spapr->htab_fd < 0) { 924 error_report("Unable to open fd for reading hash table from KVM: " 925 "%s", strerror(errno)); 926 rc = -1; 927 } 928 spapr->htab_fd_stale = false; 929 } 930 931 return rc; 932 } 933 934 static void ppc_spapr_reset(void) 935 { 936 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 937 PowerPCCPU *first_ppc_cpu; 938 uint32_t rtas_limit; 939 940 /* Check for unknown sysbus devices */ 941 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 942 943 /* Reset the hash table & recalc the RMA */ 944 spapr_reset_htab(spapr); 945 946 qemu_devices_reset(); 947 948 /* 949 * We place the device tree and RTAS just below either the top of the RMA, 950 * or just below 2GB, whichever is lowere, so that it can be 951 * processed with 32-bit real mode code if necessary 952 */ 953 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 954 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; 955 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; 956 957 /* Load the fdt */ 958 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, 959 spapr->rtas_size); 960 961 /* Copy RTAS over */ 962 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob, 963 spapr->rtas_size); 964 965 /* Set up the entry state */ 966 first_ppc_cpu = POWERPC_CPU(first_cpu); 967 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; 968 first_ppc_cpu->env.gpr[5] = 0; 969 first_cpu->halted = 0; 970 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 971 972 } 973 974 static void spapr_cpu_reset(void *opaque) 975 { 976 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 977 PowerPCCPU *cpu = opaque; 978 CPUState *cs = CPU(cpu); 979 CPUPPCState *env = &cpu->env; 980 981 cpu_reset(cs); 982 983 /* All CPUs start halted. CPU0 is unhalted from the machine level 984 * reset code and the rest are explicitly started up by the guest 985 * using an RTAS call */ 986 cs->halted = 1; 987 988 env->spr[SPR_HIOR] = 0; 989 990 env->external_htab = (uint8_t *)spapr->htab; 991 if (kvm_enabled() && !env->external_htab) { 992 /* 993 * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte* 994 * functions do the right thing. 995 */ 996 env->external_htab = (void *)1; 997 } 998 env->htab_base = -1; 999 /* 1000 * htab_mask is the mask used to normalize hash value to PTEG index. 1001 * htab_shift is log2 of hash table size. 1002 * We have 8 hpte per group, and each hpte is 16 bytes. 1003 * ie have 128 bytes per hpte entry. 1004 */ 1005 env->htab_mask = (1ULL << (spapr->htab_shift - 7)) - 1; 1006 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | 1007 (spapr->htab_shift - 18); 1008 } 1009 1010 static void spapr_create_nvram(sPAPRMachineState *spapr) 1011 { 1012 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1013 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1014 1015 if (dinfo) { 1016 qdev_prop_set_drive_nofail(dev, "drive", blk_by_legacy_dinfo(dinfo)); 1017 } 1018 1019 qdev_init_nofail(dev); 1020 1021 spapr->nvram = (struct sPAPRNVRAM *)dev; 1022 } 1023 1024 static void spapr_rtc_create(sPAPRMachineState *spapr) 1025 { 1026 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC); 1027 1028 qdev_init_nofail(dev); 1029 spapr->rtc = dev; 1030 1031 object_property_add_alias(qdev_get_machine(), "rtc-time", 1032 OBJECT(spapr->rtc), "date", NULL); 1033 } 1034 1035 /* Returns whether we want to use VGA or not */ 1036 static int spapr_vga_init(PCIBus *pci_bus) 1037 { 1038 switch (vga_interface_type) { 1039 case VGA_NONE: 1040 return false; 1041 case VGA_DEVICE: 1042 return true; 1043 case VGA_STD: 1044 return pci_vga_init(pci_bus) != NULL; 1045 default: 1046 fprintf(stderr, "This vga model is not supported," 1047 "currently it only supports -vga std\n"); 1048 exit(0); 1049 } 1050 } 1051 1052 static int spapr_post_load(void *opaque, int version_id) 1053 { 1054 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1055 int err = 0; 1056 1057 /* In earlier versions, there was no separate qdev for the PAPR 1058 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1059 * So when migrating from those versions, poke the incoming offset 1060 * value into the RTC device */ 1061 if (version_id < 3) { 1062 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset); 1063 } 1064 1065 return err; 1066 } 1067 1068 static bool version_before_3(void *opaque, int version_id) 1069 { 1070 return version_id < 3; 1071 } 1072 1073 static const VMStateDescription vmstate_spapr = { 1074 .name = "spapr", 1075 .version_id = 3, 1076 .minimum_version_id = 1, 1077 .post_load = spapr_post_load, 1078 .fields = (VMStateField[]) { 1079 /* used to be @next_irq */ 1080 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1081 1082 /* RTC offset */ 1083 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1084 1085 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1086 VMSTATE_END_OF_LIST() 1087 }, 1088 }; 1089 1090 static int htab_save_setup(QEMUFile *f, void *opaque) 1091 { 1092 sPAPRMachineState *spapr = opaque; 1093 1094 /* "Iteration" header */ 1095 qemu_put_be32(f, spapr->htab_shift); 1096 1097 if (spapr->htab) { 1098 spapr->htab_save_index = 0; 1099 spapr->htab_first_pass = true; 1100 } else { 1101 assert(kvm_enabled()); 1102 1103 spapr->htab_fd = kvmppc_get_htab_fd(false); 1104 spapr->htab_fd_stale = false; 1105 if (spapr->htab_fd < 0) { 1106 fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n", 1107 strerror(errno)); 1108 return -1; 1109 } 1110 } 1111 1112 1113 return 0; 1114 } 1115 1116 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1117 int64_t max_ns) 1118 { 1119 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1120 int index = spapr->htab_save_index; 1121 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1122 1123 assert(spapr->htab_first_pass); 1124 1125 do { 1126 int chunkstart; 1127 1128 /* Consume invalid HPTEs */ 1129 while ((index < htabslots) 1130 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1131 index++; 1132 CLEAN_HPTE(HPTE(spapr->htab, index)); 1133 } 1134 1135 /* Consume valid HPTEs */ 1136 chunkstart = index; 1137 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1138 && HPTE_VALID(HPTE(spapr->htab, index))) { 1139 index++; 1140 CLEAN_HPTE(HPTE(spapr->htab, index)); 1141 } 1142 1143 if (index > chunkstart) { 1144 int n_valid = index - chunkstart; 1145 1146 qemu_put_be32(f, chunkstart); 1147 qemu_put_be16(f, n_valid); 1148 qemu_put_be16(f, 0); 1149 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1150 HASH_PTE_SIZE_64 * n_valid); 1151 1152 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1153 break; 1154 } 1155 } 1156 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1157 1158 if (index >= htabslots) { 1159 assert(index == htabslots); 1160 index = 0; 1161 spapr->htab_first_pass = false; 1162 } 1163 spapr->htab_save_index = index; 1164 } 1165 1166 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1167 int64_t max_ns) 1168 { 1169 bool final = max_ns < 0; 1170 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1171 int examined = 0, sent = 0; 1172 int index = spapr->htab_save_index; 1173 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1174 1175 assert(!spapr->htab_first_pass); 1176 1177 do { 1178 int chunkstart, invalidstart; 1179 1180 /* Consume non-dirty HPTEs */ 1181 while ((index < htabslots) 1182 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1183 index++; 1184 examined++; 1185 } 1186 1187 chunkstart = index; 1188 /* Consume valid dirty HPTEs */ 1189 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1190 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1191 && HPTE_VALID(HPTE(spapr->htab, index))) { 1192 CLEAN_HPTE(HPTE(spapr->htab, index)); 1193 index++; 1194 examined++; 1195 } 1196 1197 invalidstart = index; 1198 /* Consume invalid dirty HPTEs */ 1199 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1200 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1201 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1202 CLEAN_HPTE(HPTE(spapr->htab, index)); 1203 index++; 1204 examined++; 1205 } 1206 1207 if (index > chunkstart) { 1208 int n_valid = invalidstart - chunkstart; 1209 int n_invalid = index - invalidstart; 1210 1211 qemu_put_be32(f, chunkstart); 1212 qemu_put_be16(f, n_valid); 1213 qemu_put_be16(f, n_invalid); 1214 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1215 HASH_PTE_SIZE_64 * n_valid); 1216 sent += index - chunkstart; 1217 1218 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1219 break; 1220 } 1221 } 1222 1223 if (examined >= htabslots) { 1224 break; 1225 } 1226 1227 if (index >= htabslots) { 1228 assert(index == htabslots); 1229 index = 0; 1230 } 1231 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1232 1233 if (index >= htabslots) { 1234 assert(index == htabslots); 1235 index = 0; 1236 } 1237 1238 spapr->htab_save_index = index; 1239 1240 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1241 } 1242 1243 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1244 #define MAX_KVM_BUF_SIZE 2048 1245 1246 static int htab_save_iterate(QEMUFile *f, void *opaque) 1247 { 1248 sPAPRMachineState *spapr = opaque; 1249 int rc = 0; 1250 1251 /* Iteration header */ 1252 qemu_put_be32(f, 0); 1253 1254 if (!spapr->htab) { 1255 assert(kvm_enabled()); 1256 1257 rc = spapr_check_htab_fd(spapr); 1258 if (rc < 0) { 1259 return rc; 1260 } 1261 1262 rc = kvmppc_save_htab(f, spapr->htab_fd, 1263 MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1264 if (rc < 0) { 1265 return rc; 1266 } 1267 } else if (spapr->htab_first_pass) { 1268 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1269 } else { 1270 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1271 } 1272 1273 /* End marker */ 1274 qemu_put_be32(f, 0); 1275 qemu_put_be16(f, 0); 1276 qemu_put_be16(f, 0); 1277 1278 return rc; 1279 } 1280 1281 static int htab_save_complete(QEMUFile *f, void *opaque) 1282 { 1283 sPAPRMachineState *spapr = opaque; 1284 1285 /* Iteration header */ 1286 qemu_put_be32(f, 0); 1287 1288 if (!spapr->htab) { 1289 int rc; 1290 1291 assert(kvm_enabled()); 1292 1293 rc = spapr_check_htab_fd(spapr); 1294 if (rc < 0) { 1295 return rc; 1296 } 1297 1298 rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1); 1299 if (rc < 0) { 1300 return rc; 1301 } 1302 close(spapr->htab_fd); 1303 spapr->htab_fd = -1; 1304 } else { 1305 htab_save_later_pass(f, spapr, -1); 1306 } 1307 1308 /* End marker */ 1309 qemu_put_be32(f, 0); 1310 qemu_put_be16(f, 0); 1311 qemu_put_be16(f, 0); 1312 1313 return 0; 1314 } 1315 1316 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1317 { 1318 sPAPRMachineState *spapr = opaque; 1319 uint32_t section_hdr; 1320 int fd = -1; 1321 1322 if (version_id < 1 || version_id > 1) { 1323 fprintf(stderr, "htab_load() bad version\n"); 1324 return -EINVAL; 1325 } 1326 1327 section_hdr = qemu_get_be32(f); 1328 1329 if (section_hdr) { 1330 /* First section, just the hash shift */ 1331 if (spapr->htab_shift != section_hdr) { 1332 return -EINVAL; 1333 } 1334 return 0; 1335 } 1336 1337 if (!spapr->htab) { 1338 assert(kvm_enabled()); 1339 1340 fd = kvmppc_get_htab_fd(true); 1341 if (fd < 0) { 1342 fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n", 1343 strerror(errno)); 1344 } 1345 } 1346 1347 while (true) { 1348 uint32_t index; 1349 uint16_t n_valid, n_invalid; 1350 1351 index = qemu_get_be32(f); 1352 n_valid = qemu_get_be16(f); 1353 n_invalid = qemu_get_be16(f); 1354 1355 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1356 /* End of Stream */ 1357 break; 1358 } 1359 1360 if ((index + n_valid + n_invalid) > 1361 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1362 /* Bad index in stream */ 1363 fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) " 1364 "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid, 1365 spapr->htab_shift); 1366 return -EINVAL; 1367 } 1368 1369 if (spapr->htab) { 1370 if (n_valid) { 1371 qemu_get_buffer(f, HPTE(spapr->htab, index), 1372 HASH_PTE_SIZE_64 * n_valid); 1373 } 1374 if (n_invalid) { 1375 memset(HPTE(spapr->htab, index + n_valid), 0, 1376 HASH_PTE_SIZE_64 * n_invalid); 1377 } 1378 } else { 1379 int rc; 1380 1381 assert(fd >= 0); 1382 1383 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1384 if (rc < 0) { 1385 return rc; 1386 } 1387 } 1388 } 1389 1390 if (!spapr->htab) { 1391 assert(fd >= 0); 1392 close(fd); 1393 } 1394 1395 return 0; 1396 } 1397 1398 static SaveVMHandlers savevm_htab_handlers = { 1399 .save_live_setup = htab_save_setup, 1400 .save_live_iterate = htab_save_iterate, 1401 .save_live_complete = htab_save_complete, 1402 .load_state = htab_load, 1403 }; 1404 1405 static void spapr_boot_set(void *opaque, const char *boot_device, 1406 Error **errp) 1407 { 1408 MachineState *machine = MACHINE(qdev_get_machine()); 1409 machine->boot_order = g_strdup(boot_device); 1410 } 1411 1412 static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu) 1413 { 1414 CPUPPCState *env = &cpu->env; 1415 1416 /* Set time-base frequency to 512 MHz */ 1417 cpu_ppc_tb_init(env, TIMEBASE_FREQ); 1418 1419 /* PAPR always has exception vectors in RAM not ROM. To ensure this, 1420 * MSR[IP] should never be set. 1421 */ 1422 env->msr_mask &= ~(1 << 6); 1423 1424 /* Tell KVM that we're in PAPR mode */ 1425 if (kvm_enabled()) { 1426 kvmppc_set_papr(cpu); 1427 } 1428 1429 if (cpu->max_compat) { 1430 if (ppc_set_compat(cpu, cpu->max_compat) < 0) { 1431 exit(1); 1432 } 1433 } 1434 1435 xics_cpu_setup(spapr->icp, cpu); 1436 1437 qemu_register_reset(spapr_cpu_reset, cpu); 1438 } 1439 1440 /* pSeries LPAR / sPAPR hardware init */ 1441 static void ppc_spapr_init(MachineState *machine) 1442 { 1443 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1444 const char *kernel_filename = machine->kernel_filename; 1445 const char *kernel_cmdline = machine->kernel_cmdline; 1446 const char *initrd_filename = machine->initrd_filename; 1447 PowerPCCPU *cpu; 1448 PCIHostState *phb; 1449 int i; 1450 MemoryRegion *sysmem = get_system_memory(); 1451 MemoryRegion *ram = g_new(MemoryRegion, 1); 1452 MemoryRegion *rma_region; 1453 void *rma = NULL; 1454 hwaddr rma_alloc_size; 1455 hwaddr node0_size = spapr_node0_size(); 1456 uint32_t initrd_base = 0; 1457 long kernel_size = 0, initrd_size = 0; 1458 long load_limit, fw_size; 1459 bool kernel_le = false; 1460 char *filename; 1461 1462 msi_supported = true; 1463 1464 QLIST_INIT(&spapr->phbs); 1465 1466 cpu_ppc_hypercall = emulate_spapr_hypercall; 1467 1468 /* Allocate RMA if necessary */ 1469 rma_alloc_size = kvmppc_alloc_rma(&rma); 1470 1471 if (rma_alloc_size == -1) { 1472 error_report("Unable to create RMA"); 1473 exit(1); 1474 } 1475 1476 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1477 spapr->rma_size = rma_alloc_size; 1478 } else { 1479 spapr->rma_size = node0_size; 1480 1481 /* With KVM, we don't actually know whether KVM supports an 1482 * unbounded RMA (PR KVM) or is limited by the hash table size 1483 * (HV KVM using VRMA), so we always assume the latter 1484 * 1485 * In that case, we also limit the initial allocations for RTAS 1486 * etc... to 256M since we have no way to know what the VRMA size 1487 * is going to be as it depends on the size of the hash table 1488 * isn't determined yet. 1489 */ 1490 if (kvm_enabled()) { 1491 spapr->vrma_adjust = 1; 1492 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1493 } 1494 } 1495 1496 if (spapr->rma_size > node0_size) { 1497 fprintf(stderr, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")\n", 1498 spapr->rma_size); 1499 exit(1); 1500 } 1501 1502 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 1503 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 1504 1505 /* We aim for a hash table of size 1/128 the size of RAM. The 1506 * normal rule of thumb is 1/64 the size of RAM, but that's much 1507 * more than needed for the Linux guests we support. */ 1508 spapr->htab_shift = 18; /* Minimum architected size */ 1509 while (spapr->htab_shift <= 46) { 1510 if ((1ULL << (spapr->htab_shift + 7)) >= machine->ram_size) { 1511 break; 1512 } 1513 spapr->htab_shift++; 1514 } 1515 1516 /* Set up Interrupt Controller before we create the VCPUs */ 1517 spapr->icp = xics_system_init(machine, 1518 DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(), 1519 smp_threads), 1520 XICS_IRQS); 1521 1522 /* init CPUs */ 1523 if (machine->cpu_model == NULL) { 1524 machine->cpu_model = kvm_enabled() ? "host" : "POWER7"; 1525 } 1526 for (i = 0; i < smp_cpus; i++) { 1527 cpu = cpu_ppc_init(machine->cpu_model); 1528 if (cpu == NULL) { 1529 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 1530 exit(1); 1531 } 1532 spapr_cpu_init(spapr, cpu); 1533 } 1534 1535 if (kvm_enabled()) { 1536 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 1537 kvmppc_enable_logical_ci_hcalls(); 1538 } 1539 1540 /* allocate RAM */ 1541 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 1542 machine->ram_size); 1543 memory_region_add_subregion(sysmem, 0, ram); 1544 1545 if (rma_alloc_size && rma) { 1546 rma_region = g_new(MemoryRegion, 1); 1547 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 1548 rma_alloc_size, rma); 1549 vmstate_register_ram_global(rma_region); 1550 memory_region_add_subregion(sysmem, 0, rma_region); 1551 } 1552 1553 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 1554 if (!filename) { 1555 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 1556 exit(1); 1557 } 1558 spapr->rtas_size = get_image_size(filename); 1559 spapr->rtas_blob = g_malloc(spapr->rtas_size); 1560 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 1561 error_report("Could not load LPAR rtas '%s'", filename); 1562 exit(1); 1563 } 1564 if (spapr->rtas_size > RTAS_MAX_SIZE) { 1565 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 1566 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 1567 exit(1); 1568 } 1569 g_free(filename); 1570 1571 /* Set up EPOW events infrastructure */ 1572 spapr_events_init(spapr); 1573 1574 /* Set up the RTC RTAS interfaces */ 1575 spapr_rtc_create(spapr); 1576 1577 /* Set up VIO bus */ 1578 spapr->vio_bus = spapr_vio_bus_init(); 1579 1580 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 1581 if (serial_hds[i]) { 1582 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 1583 } 1584 } 1585 1586 /* We always have at least the nvram device on VIO */ 1587 spapr_create_nvram(spapr); 1588 1589 /* Set up PCI */ 1590 spapr_pci_rtas_init(); 1591 1592 phb = spapr_create_phb(spapr, 0); 1593 1594 for (i = 0; i < nb_nics; i++) { 1595 NICInfo *nd = &nd_table[i]; 1596 1597 if (!nd->model) { 1598 nd->model = g_strdup("ibmveth"); 1599 } 1600 1601 if (strcmp(nd->model, "ibmveth") == 0) { 1602 spapr_vlan_create(spapr->vio_bus, nd); 1603 } else { 1604 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 1605 } 1606 } 1607 1608 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 1609 spapr_vscsi_create(spapr->vio_bus); 1610 } 1611 1612 /* Graphics */ 1613 if (spapr_vga_init(phb->bus)) { 1614 spapr->has_graphics = true; 1615 machine->usb |= defaults_enabled() && !machine->usb_disabled; 1616 } 1617 1618 if (machine->usb) { 1619 pci_create_simple(phb->bus, -1, "pci-ohci"); 1620 1621 if (spapr->has_graphics) { 1622 USBBus *usb_bus = usb_bus_find(-1); 1623 1624 usb_create_simple(usb_bus, "usb-kbd"); 1625 usb_create_simple(usb_bus, "usb-mouse"); 1626 } 1627 } 1628 1629 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 1630 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= " 1631 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF); 1632 exit(1); 1633 } 1634 1635 if (kernel_filename) { 1636 uint64_t lowaddr = 0; 1637 1638 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 1639 NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); 1640 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) { 1641 kernel_size = load_elf(kernel_filename, 1642 translate_kernel_address, NULL, 1643 NULL, &lowaddr, NULL, 0, ELF_MACHINE, 0); 1644 kernel_le = kernel_size > 0; 1645 } 1646 if (kernel_size < 0) { 1647 fprintf(stderr, "qemu: error loading %s: %s\n", 1648 kernel_filename, load_elf_strerror(kernel_size)); 1649 exit(1); 1650 } 1651 1652 /* load initrd */ 1653 if (initrd_filename) { 1654 /* Try to locate the initrd in the gap between the kernel 1655 * and the firmware. Add a bit of space just in case 1656 */ 1657 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; 1658 initrd_size = load_image_targphys(initrd_filename, initrd_base, 1659 load_limit - initrd_base); 1660 if (initrd_size < 0) { 1661 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 1662 initrd_filename); 1663 exit(1); 1664 } 1665 } else { 1666 initrd_base = 0; 1667 initrd_size = 0; 1668 } 1669 } 1670 1671 if (bios_name == NULL) { 1672 bios_name = FW_FILE_NAME; 1673 } 1674 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1675 if (!filename) { 1676 error_report("Could not find LPAR firmware '%s'", bios_name); 1677 exit(1); 1678 } 1679 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 1680 if (fw_size <= 0) { 1681 error_report("Could not load LPAR firmware '%s'", filename); 1682 exit(1); 1683 } 1684 g_free(filename); 1685 1686 /* FIXME: Should register things through the MachineState's qdev 1687 * interface, this is a legacy from the sPAPREnvironment structure 1688 * which predated MachineState but had a similar function */ 1689 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 1690 register_savevm_live(NULL, "spapr/htab", -1, 1, 1691 &savevm_htab_handlers, spapr); 1692 1693 /* Prepare the device tree */ 1694 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, 1695 kernel_size, kernel_le, 1696 kernel_cmdline, 1697 spapr->check_exception_irq); 1698 assert(spapr->fdt_skel != NULL); 1699 1700 /* used by RTAS */ 1701 QTAILQ_INIT(&spapr->ccs_list); 1702 qemu_register_reset(spapr_ccs_reset_hook, spapr); 1703 1704 qemu_register_boot_set(spapr_boot_set, spapr); 1705 } 1706 1707 static int spapr_kvm_type(const char *vm_type) 1708 { 1709 if (!vm_type) { 1710 return 0; 1711 } 1712 1713 if (!strcmp(vm_type, "HV")) { 1714 return 1; 1715 } 1716 1717 if (!strcmp(vm_type, "PR")) { 1718 return 2; 1719 } 1720 1721 error_report("Unknown kvm-type specified '%s'", vm_type); 1722 exit(1); 1723 } 1724 1725 /* 1726 * Implementation of an interface to adjust firmware path 1727 * for the bootindex property handling. 1728 */ 1729 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 1730 DeviceState *dev) 1731 { 1732 #define CAST(type, obj, name) \ 1733 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 1734 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 1735 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 1736 1737 if (d) { 1738 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 1739 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 1740 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 1741 1742 if (spapr) { 1743 /* 1744 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 1745 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 1746 * in the top 16 bits of the 64-bit LUN 1747 */ 1748 unsigned id = 0x8000 | (d->id << 8) | d->lun; 1749 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1750 (uint64_t)id << 48); 1751 } else if (virtio) { 1752 /* 1753 * We use SRP luns of the form 01000000 | (target << 8) | lun 1754 * in the top 32 bits of the 64-bit LUN 1755 * Note: the quote above is from SLOF and it is wrong, 1756 * the actual binding is: 1757 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 1758 */ 1759 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 1760 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1761 (uint64_t)id << 32); 1762 } else if (usb) { 1763 /* 1764 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 1765 * in the top 32 bits of the 64-bit LUN 1766 */ 1767 unsigned usb_port = atoi(usb->port->path); 1768 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 1769 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1770 (uint64_t)id << 32); 1771 } 1772 } 1773 1774 if (phb) { 1775 /* Replace "pci" with "pci@800000020000000" */ 1776 return g_strdup_printf("pci@%"PRIX64, phb->buid); 1777 } 1778 1779 return NULL; 1780 } 1781 1782 static char *spapr_get_kvm_type(Object *obj, Error **errp) 1783 { 1784 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 1785 1786 return g_strdup(spapr->kvm_type); 1787 } 1788 1789 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 1790 { 1791 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 1792 1793 g_free(spapr->kvm_type); 1794 spapr->kvm_type = g_strdup(value); 1795 } 1796 1797 static void spapr_machine_initfn(Object *obj) 1798 { 1799 object_property_add_str(obj, "kvm-type", 1800 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 1801 object_property_set_description(obj, "kvm-type", 1802 "Specifies the KVM virtualization mode (HV, PR)", 1803 NULL); 1804 } 1805 1806 static void ppc_cpu_do_nmi_on_cpu(void *arg) 1807 { 1808 CPUState *cs = arg; 1809 1810 cpu_synchronize_state(cs); 1811 ppc_cpu_do_system_reset(cs); 1812 } 1813 1814 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 1815 { 1816 CPUState *cs; 1817 1818 CPU_FOREACH(cs) { 1819 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs); 1820 } 1821 } 1822 1823 static void spapr_machine_class_init(ObjectClass *oc, void *data) 1824 { 1825 MachineClass *mc = MACHINE_CLASS(oc); 1826 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 1827 NMIClass *nc = NMI_CLASS(oc); 1828 1829 mc->init = ppc_spapr_init; 1830 mc->reset = ppc_spapr_reset; 1831 mc->block_default_type = IF_SCSI; 1832 mc->max_cpus = MAX_CPUS; 1833 mc->no_parallel = 1; 1834 mc->default_boot_order = ""; 1835 mc->default_ram_size = 512 * M_BYTE; 1836 mc->kvm_type = spapr_kvm_type; 1837 mc->has_dynamic_sysbus = true; 1838 mc->pci_allow_0_address = true; 1839 1840 fwc->get_dev_path = spapr_get_fw_dev_path; 1841 nc->nmi_monitor_handler = spapr_nmi; 1842 } 1843 1844 static const TypeInfo spapr_machine_info = { 1845 .name = TYPE_SPAPR_MACHINE, 1846 .parent = TYPE_MACHINE, 1847 .abstract = true, 1848 .instance_size = sizeof(sPAPRMachineState), 1849 .instance_init = spapr_machine_initfn, 1850 .class_size = sizeof(sPAPRMachineClass), 1851 .class_init = spapr_machine_class_init, 1852 .interfaces = (InterfaceInfo[]) { 1853 { TYPE_FW_PATH_PROVIDER }, 1854 { TYPE_NMI }, 1855 { } 1856 }, 1857 }; 1858 1859 #define SPAPR_COMPAT_2_3 \ 1860 HW_COMPAT_2_3 \ 1861 {\ 1862 .driver = "spapr-pci-host-bridge",\ 1863 .property = "dynamic-reconfiguration",\ 1864 .value = "off",\ 1865 }, 1866 1867 #define SPAPR_COMPAT_2_2 \ 1868 SPAPR_COMPAT_2_3 \ 1869 HW_COMPAT_2_2 \ 1870 {\ 1871 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 1872 .property = "mem_win_size",\ 1873 .value = "0x20000000",\ 1874 }, 1875 1876 #define SPAPR_COMPAT_2_1 \ 1877 SPAPR_COMPAT_2_2 \ 1878 HW_COMPAT_2_1 1879 1880 static void spapr_compat_2_3(Object *obj) 1881 { 1882 savevm_skip_section_footers(); 1883 global_state_set_optional(); 1884 } 1885 1886 static void spapr_compat_2_2(Object *obj) 1887 { 1888 spapr_compat_2_3(obj); 1889 } 1890 1891 static void spapr_compat_2_1(Object *obj) 1892 { 1893 spapr_compat_2_2(obj); 1894 } 1895 1896 static void spapr_machine_2_3_instance_init(Object *obj) 1897 { 1898 spapr_compat_2_3(obj); 1899 spapr_machine_initfn(obj); 1900 } 1901 1902 static void spapr_machine_2_2_instance_init(Object *obj) 1903 { 1904 spapr_compat_2_2(obj); 1905 spapr_machine_initfn(obj); 1906 } 1907 1908 static void spapr_machine_2_1_instance_init(Object *obj) 1909 { 1910 spapr_compat_2_1(obj); 1911 spapr_machine_initfn(obj); 1912 } 1913 1914 static void spapr_machine_2_1_class_init(ObjectClass *oc, void *data) 1915 { 1916 MachineClass *mc = MACHINE_CLASS(oc); 1917 static GlobalProperty compat_props[] = { 1918 SPAPR_COMPAT_2_1 1919 { /* end of list */ } 1920 }; 1921 1922 mc->name = "pseries-2.1"; 1923 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.1"; 1924 mc->compat_props = compat_props; 1925 } 1926 1927 static const TypeInfo spapr_machine_2_1_info = { 1928 .name = TYPE_SPAPR_MACHINE "2.1", 1929 .parent = TYPE_SPAPR_MACHINE, 1930 .class_init = spapr_machine_2_1_class_init, 1931 .instance_init = spapr_machine_2_1_instance_init, 1932 }; 1933 1934 static void spapr_machine_2_2_class_init(ObjectClass *oc, void *data) 1935 { 1936 static GlobalProperty compat_props[] = { 1937 SPAPR_COMPAT_2_2 1938 { /* end of list */ } 1939 }; 1940 MachineClass *mc = MACHINE_CLASS(oc); 1941 1942 mc->name = "pseries-2.2"; 1943 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.2"; 1944 mc->compat_props = compat_props; 1945 } 1946 1947 static const TypeInfo spapr_machine_2_2_info = { 1948 .name = TYPE_SPAPR_MACHINE "2.2", 1949 .parent = TYPE_SPAPR_MACHINE, 1950 .class_init = spapr_machine_2_2_class_init, 1951 .instance_init = spapr_machine_2_2_instance_init, 1952 }; 1953 1954 static void spapr_machine_2_3_class_init(ObjectClass *oc, void *data) 1955 { 1956 static GlobalProperty compat_props[] = { 1957 SPAPR_COMPAT_2_3 1958 { /* end of list */ } 1959 }; 1960 MachineClass *mc = MACHINE_CLASS(oc); 1961 1962 mc->name = "pseries-2.3"; 1963 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.3"; 1964 mc->compat_props = compat_props; 1965 } 1966 1967 static const TypeInfo spapr_machine_2_3_info = { 1968 .name = TYPE_SPAPR_MACHINE "2.3", 1969 .parent = TYPE_SPAPR_MACHINE, 1970 .class_init = spapr_machine_2_3_class_init, 1971 .instance_init = spapr_machine_2_3_instance_init, 1972 }; 1973 1974 static void spapr_machine_2_4_class_init(ObjectClass *oc, void *data) 1975 { 1976 MachineClass *mc = MACHINE_CLASS(oc); 1977 1978 mc->name = "pseries-2.4"; 1979 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.4"; 1980 mc->alias = "pseries"; 1981 mc->is_default = 1; 1982 } 1983 1984 static const TypeInfo spapr_machine_2_4_info = { 1985 .name = TYPE_SPAPR_MACHINE "2.4", 1986 .parent = TYPE_SPAPR_MACHINE, 1987 .class_init = spapr_machine_2_4_class_init, 1988 }; 1989 1990 static void spapr_machine_register_types(void) 1991 { 1992 type_register_static(&spapr_machine_info); 1993 type_register_static(&spapr_machine_2_1_info); 1994 type_register_static(&spapr_machine_2_2_info); 1995 type_register_static(&spapr_machine_2_3_info); 1996 type_register_static(&spapr_machine_2_4_info); 1997 } 1998 1999 type_init(spapr_machine_register_types) 2000