1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qapi/error.h" 30 #include "qapi/visitor.h" 31 #include "sysemu/sysemu.h" 32 #include "sysemu/hostmem.h" 33 #include "sysemu/numa.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/reset.h" 36 #include "sysemu/runstate.h" 37 #include "qemu/log.h" 38 #include "hw/fw-path-provider.h" 39 #include "elf.h" 40 #include "net/net.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/cpus.h" 43 #include "sysemu/hw_accel.h" 44 #include "kvm_ppc.h" 45 #include "migration/misc.h" 46 #include "migration/qemu-file-types.h" 47 #include "migration/global_state.h" 48 #include "migration/register.h" 49 #include "migration/blocker.h" 50 #include "mmu-hash64.h" 51 #include "mmu-book3s-v3.h" 52 #include "cpu-models.h" 53 #include "hw/core/cpu.h" 54 55 #include "hw/boards.h" 56 #include "hw/ppc/ppc.h" 57 #include "hw/loader.h" 58 59 #include "hw/ppc/fdt.h" 60 #include "hw/ppc/spapr.h" 61 #include "hw/ppc/spapr_vio.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/pci-host/spapr.h" 64 #include "hw/pci/msi.h" 65 66 #include "hw/pci/pci.h" 67 #include "hw/scsi/scsi.h" 68 #include "hw/virtio/virtio-scsi.h" 69 #include "hw/virtio/vhost-scsi-common.h" 70 71 #include "exec/address-spaces.h" 72 #include "exec/ram_addr.h" 73 #include "hw/usb.h" 74 #include "qemu/config-file.h" 75 #include "qemu/error-report.h" 76 #include "trace.h" 77 #include "hw/nmi.h" 78 #include "hw/intc/intc.h" 79 80 #include "hw/ppc/spapr_cpu_core.h" 81 #include "hw/mem/memory-device.h" 82 #include "hw/ppc/spapr_tpm_proxy.h" 83 #include "hw/ppc/spapr_nvdimm.h" 84 85 #include "monitor/monitor.h" 86 87 #include <libfdt.h> 88 89 /* SLOF memory layout: 90 * 91 * SLOF raw image loaded at 0, copies its romfs right below the flat 92 * device-tree, then position SLOF itself 31M below that 93 * 94 * So we set FW_OVERHEAD to 40MB which should account for all of that 95 * and more 96 * 97 * We load our kernel at 4M, leaving space for SLOF initial image 98 */ 99 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 100 #define FW_MAX_SIZE 0x400000 101 #define FW_FILE_NAME "slof.bin" 102 #define FW_OVERHEAD 0x2800000 103 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 104 105 #define MIN_RMA_SLOF (128 * MiB) 106 107 #define PHANDLE_INTC 0x00001111 108 109 /* These two functions implement the VCPU id numbering: one to compute them 110 * all and one to identify thread 0 of a VCORE. Any change to the first one 111 * is likely to have an impact on the second one, so let's keep them close. 112 */ 113 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 114 { 115 MachineState *ms = MACHINE(spapr); 116 unsigned int smp_threads = ms->smp.threads; 117 118 assert(spapr->vsmt); 119 return 120 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 121 } 122 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 123 PowerPCCPU *cpu) 124 { 125 assert(spapr->vsmt); 126 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 127 } 128 129 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 130 { 131 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 132 * and newer QEMUs don't even have them. In both cases, we don't want 133 * to send anything on the wire. 134 */ 135 return false; 136 } 137 138 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 139 .name = "icp/server", 140 .version_id = 1, 141 .minimum_version_id = 1, 142 .needed = pre_2_10_vmstate_dummy_icp_needed, 143 .fields = (VMStateField[]) { 144 VMSTATE_UNUSED(4), /* uint32_t xirr */ 145 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 146 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 147 VMSTATE_END_OF_LIST() 148 }, 149 }; 150 151 static void pre_2_10_vmstate_register_dummy_icp(int i) 152 { 153 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 154 (void *)(uintptr_t) i); 155 } 156 157 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 158 { 159 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 160 (void *)(uintptr_t) i); 161 } 162 163 int spapr_max_server_number(SpaprMachineState *spapr) 164 { 165 MachineState *ms = MACHINE(spapr); 166 167 assert(spapr->vsmt); 168 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 169 } 170 171 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 172 int smt_threads) 173 { 174 int i, ret = 0; 175 uint32_t servers_prop[smt_threads]; 176 uint32_t gservers_prop[smt_threads * 2]; 177 int index = spapr_get_vcpu_id(cpu); 178 179 if (cpu->compat_pvr) { 180 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 181 if (ret < 0) { 182 return ret; 183 } 184 } 185 186 /* Build interrupt servers and gservers properties */ 187 for (i = 0; i < smt_threads; i++) { 188 servers_prop[i] = cpu_to_be32(index + i); 189 /* Hack, direct the group queues back to cpu 0 */ 190 gservers_prop[i*2] = cpu_to_be32(index + i); 191 gservers_prop[i*2 + 1] = 0; 192 } 193 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 194 servers_prop, sizeof(servers_prop)); 195 if (ret < 0) { 196 return ret; 197 } 198 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 199 gservers_prop, sizeof(gservers_prop)); 200 201 return ret; 202 } 203 204 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 205 { 206 int index = spapr_get_vcpu_id(cpu); 207 uint32_t associativity[] = {cpu_to_be32(0x5), 208 cpu_to_be32(0x0), 209 cpu_to_be32(0x0), 210 cpu_to_be32(0x0), 211 cpu_to_be32(cpu->node_id), 212 cpu_to_be32(index)}; 213 214 /* Advertise NUMA via ibm,associativity */ 215 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 216 sizeof(associativity)); 217 } 218 219 static void spapr_dt_pa_features(SpaprMachineState *spapr, 220 PowerPCCPU *cpu, 221 void *fdt, int offset) 222 { 223 uint8_t pa_features_206[] = { 6, 0, 224 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 225 uint8_t pa_features_207[] = { 24, 0, 226 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 227 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 228 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 229 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 230 uint8_t pa_features_300[] = { 66, 0, 231 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 232 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 233 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 234 /* 6: DS207 */ 235 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 236 /* 16: Vector */ 237 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 238 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 239 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 240 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 241 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 242 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 243 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 244 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 245 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 246 /* 42: PM, 44: PC RA, 46: SC vec'd */ 247 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 248 /* 48: SIMD, 50: QP BFP, 52: String */ 249 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 250 /* 54: DecFP, 56: DecI, 58: SHA */ 251 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 252 /* 60: NM atomic, 62: RNG */ 253 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 254 }; 255 uint8_t *pa_features = NULL; 256 size_t pa_size; 257 258 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 259 pa_features = pa_features_206; 260 pa_size = sizeof(pa_features_206); 261 } 262 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 263 pa_features = pa_features_207; 264 pa_size = sizeof(pa_features_207); 265 } 266 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 267 pa_features = pa_features_300; 268 pa_size = sizeof(pa_features_300); 269 } 270 if (!pa_features) { 271 return; 272 } 273 274 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 275 /* 276 * Note: we keep CI large pages off by default because a 64K capable 277 * guest provisioned with large pages might otherwise try to map a qemu 278 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 279 * even if that qemu runs on a 4k host. 280 * We dd this bit back here if we are confident this is not an issue 281 */ 282 pa_features[3] |= 0x20; 283 } 284 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 285 pa_features[24] |= 0x80; /* Transactional memory support */ 286 } 287 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 288 /* Workaround for broken kernels that attempt (guest) radix 289 * mode when they can't handle it, if they see the radix bit set 290 * in pa-features. So hide it from them. */ 291 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 292 } 293 294 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 295 } 296 297 static hwaddr spapr_node0_size(MachineState *machine) 298 { 299 if (machine->numa_state->num_nodes) { 300 int i; 301 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 302 if (machine->numa_state->nodes[i].node_mem) { 303 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 304 machine->ram_size); 305 } 306 } 307 } 308 return machine->ram_size; 309 } 310 311 static void add_str(GString *s, const gchar *s1) 312 { 313 g_string_append_len(s, s1, strlen(s1) + 1); 314 } 315 316 static int spapr_dt_memory_node(void *fdt, int nodeid, hwaddr start, 317 hwaddr size) 318 { 319 uint32_t associativity[] = { 320 cpu_to_be32(0x4), /* length */ 321 cpu_to_be32(0x0), cpu_to_be32(0x0), 322 cpu_to_be32(0x0), cpu_to_be32(nodeid) 323 }; 324 char mem_name[32]; 325 uint64_t mem_reg_property[2]; 326 int off; 327 328 mem_reg_property[0] = cpu_to_be64(start); 329 mem_reg_property[1] = cpu_to_be64(size); 330 331 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 332 off = fdt_add_subnode(fdt, 0, mem_name); 333 _FDT(off); 334 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 335 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 336 sizeof(mem_reg_property)))); 337 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 338 sizeof(associativity)))); 339 return off; 340 } 341 342 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 343 { 344 MemoryDeviceInfoList *info; 345 346 for (info = list; info; info = info->next) { 347 MemoryDeviceInfo *value = info->value; 348 349 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 350 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 351 352 if (addr >= pcdimm_info->addr && 353 addr < (pcdimm_info->addr + pcdimm_info->size)) { 354 return pcdimm_info->node; 355 } 356 } 357 } 358 359 return -1; 360 } 361 362 struct sPAPRDrconfCellV2 { 363 uint32_t seq_lmbs; 364 uint64_t base_addr; 365 uint32_t drc_index; 366 uint32_t aa_index; 367 uint32_t flags; 368 } QEMU_PACKED; 369 370 typedef struct DrconfCellQueue { 371 struct sPAPRDrconfCellV2 cell; 372 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 373 } DrconfCellQueue; 374 375 static DrconfCellQueue * 376 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 377 uint32_t drc_index, uint32_t aa_index, 378 uint32_t flags) 379 { 380 DrconfCellQueue *elem; 381 382 elem = g_malloc0(sizeof(*elem)); 383 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 384 elem->cell.base_addr = cpu_to_be64(base_addr); 385 elem->cell.drc_index = cpu_to_be32(drc_index); 386 elem->cell.aa_index = cpu_to_be32(aa_index); 387 elem->cell.flags = cpu_to_be32(flags); 388 389 return elem; 390 } 391 392 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 393 int offset, MemoryDeviceInfoList *dimms) 394 { 395 MachineState *machine = MACHINE(spapr); 396 uint8_t *int_buf, *cur_index; 397 int ret; 398 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 399 uint64_t addr, cur_addr, size; 400 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 401 uint64_t mem_end = machine->device_memory->base + 402 memory_region_size(&machine->device_memory->mr); 403 uint32_t node, buf_len, nr_entries = 0; 404 SpaprDrc *drc; 405 DrconfCellQueue *elem, *next; 406 MemoryDeviceInfoList *info; 407 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 408 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 409 410 /* Entry to cover RAM and the gap area */ 411 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 412 SPAPR_LMB_FLAGS_RESERVED | 413 SPAPR_LMB_FLAGS_DRC_INVALID); 414 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 415 nr_entries++; 416 417 cur_addr = machine->device_memory->base; 418 for (info = dimms; info; info = info->next) { 419 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 420 421 addr = di->addr; 422 size = di->size; 423 node = di->node; 424 425 /* 426 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 427 * area is marked hotpluggable in the next iteration for the bigger 428 * chunk including the NVDIMM occupied area. 429 */ 430 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 431 continue; 432 433 /* Entry for hot-pluggable area */ 434 if (cur_addr < addr) { 435 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 436 g_assert(drc); 437 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 438 cur_addr, spapr_drc_index(drc), -1, 0); 439 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 440 nr_entries++; 441 } 442 443 /* Entry for DIMM */ 444 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 445 g_assert(drc); 446 elem = spapr_get_drconf_cell(size / lmb_size, addr, 447 spapr_drc_index(drc), node, 448 (SPAPR_LMB_FLAGS_ASSIGNED | 449 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 450 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 451 nr_entries++; 452 cur_addr = addr + size; 453 } 454 455 /* Entry for remaining hotpluggable area */ 456 if (cur_addr < mem_end) { 457 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 458 g_assert(drc); 459 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 460 cur_addr, spapr_drc_index(drc), -1, 0); 461 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 462 nr_entries++; 463 } 464 465 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 466 int_buf = cur_index = g_malloc0(buf_len); 467 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 468 cur_index += sizeof(nr_entries); 469 470 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 471 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 472 cur_index += sizeof(elem->cell); 473 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 474 g_free(elem); 475 } 476 477 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 478 g_free(int_buf); 479 if (ret < 0) { 480 return -1; 481 } 482 return 0; 483 } 484 485 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 486 int offset, MemoryDeviceInfoList *dimms) 487 { 488 MachineState *machine = MACHINE(spapr); 489 int i, ret; 490 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 491 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 492 uint32_t nr_lmbs = (machine->device_memory->base + 493 memory_region_size(&machine->device_memory->mr)) / 494 lmb_size; 495 uint32_t *int_buf, *cur_index, buf_len; 496 497 /* 498 * Allocate enough buffer size to fit in ibm,dynamic-memory 499 */ 500 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 501 cur_index = int_buf = g_malloc0(buf_len); 502 int_buf[0] = cpu_to_be32(nr_lmbs); 503 cur_index++; 504 for (i = 0; i < nr_lmbs; i++) { 505 uint64_t addr = i * lmb_size; 506 uint32_t *dynamic_memory = cur_index; 507 508 if (i >= device_lmb_start) { 509 SpaprDrc *drc; 510 511 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 512 g_assert(drc); 513 514 dynamic_memory[0] = cpu_to_be32(addr >> 32); 515 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 516 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 517 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 518 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 519 if (memory_region_present(get_system_memory(), addr)) { 520 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 521 } else { 522 dynamic_memory[5] = cpu_to_be32(0); 523 } 524 } else { 525 /* 526 * LMB information for RMA, boot time RAM and gap b/n RAM and 527 * device memory region -- all these are marked as reserved 528 * and as having no valid DRC. 529 */ 530 dynamic_memory[0] = cpu_to_be32(addr >> 32); 531 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 532 dynamic_memory[2] = cpu_to_be32(0); 533 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 534 dynamic_memory[4] = cpu_to_be32(-1); 535 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 536 SPAPR_LMB_FLAGS_DRC_INVALID); 537 } 538 539 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 540 } 541 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 542 g_free(int_buf); 543 if (ret < 0) { 544 return -1; 545 } 546 return 0; 547 } 548 549 /* 550 * Adds ibm,dynamic-reconfiguration-memory node. 551 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 552 * of this device tree node. 553 */ 554 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 555 void *fdt) 556 { 557 MachineState *machine = MACHINE(spapr); 558 int nb_numa_nodes = machine->numa_state->num_nodes; 559 int ret, i, offset; 560 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 561 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 562 uint32_t *int_buf, *cur_index, buf_len; 563 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 564 MemoryDeviceInfoList *dimms = NULL; 565 566 /* 567 * Don't create the node if there is no device memory 568 */ 569 if (machine->ram_size == machine->maxram_size) { 570 return 0; 571 } 572 573 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 574 575 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 576 sizeof(prop_lmb_size)); 577 if (ret < 0) { 578 return ret; 579 } 580 581 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 582 if (ret < 0) { 583 return ret; 584 } 585 586 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 587 if (ret < 0) { 588 return ret; 589 } 590 591 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 592 dimms = qmp_memory_device_list(); 593 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 594 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 595 } else { 596 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 597 } 598 qapi_free_MemoryDeviceInfoList(dimms); 599 600 if (ret < 0) { 601 return ret; 602 } 603 604 /* ibm,associativity-lookup-arrays */ 605 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 606 cur_index = int_buf = g_malloc0(buf_len); 607 int_buf[0] = cpu_to_be32(nr_nodes); 608 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 609 cur_index += 2; 610 for (i = 0; i < nr_nodes; i++) { 611 uint32_t associativity[] = { 612 cpu_to_be32(0x0), 613 cpu_to_be32(0x0), 614 cpu_to_be32(0x0), 615 cpu_to_be32(i) 616 }; 617 memcpy(cur_index, associativity, sizeof(associativity)); 618 cur_index += 4; 619 } 620 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 621 (cur_index - int_buf) * sizeof(uint32_t)); 622 g_free(int_buf); 623 624 return ret; 625 } 626 627 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 628 { 629 MachineState *machine = MACHINE(spapr); 630 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 631 hwaddr mem_start, node_size; 632 int i, nb_nodes = machine->numa_state->num_nodes; 633 NodeInfo *nodes = machine->numa_state->nodes; 634 635 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 636 if (!nodes[i].node_mem) { 637 continue; 638 } 639 if (mem_start >= machine->ram_size) { 640 node_size = 0; 641 } else { 642 node_size = nodes[i].node_mem; 643 if (node_size > machine->ram_size - mem_start) { 644 node_size = machine->ram_size - mem_start; 645 } 646 } 647 if (!mem_start) { 648 /* spapr_machine_init() checks for rma_size <= node0_size 649 * already */ 650 spapr_dt_memory_node(fdt, i, 0, spapr->rma_size); 651 mem_start += spapr->rma_size; 652 node_size -= spapr->rma_size; 653 } 654 for ( ; node_size; ) { 655 hwaddr sizetmp = pow2floor(node_size); 656 657 /* mem_start != 0 here */ 658 if (ctzl(mem_start) < ctzl(sizetmp)) { 659 sizetmp = 1ULL << ctzl(mem_start); 660 } 661 662 spapr_dt_memory_node(fdt, i, mem_start, sizetmp); 663 node_size -= sizetmp; 664 mem_start += sizetmp; 665 } 666 } 667 668 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 669 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 670 int ret; 671 672 g_assert(smc->dr_lmb_enabled); 673 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 674 if (ret) { 675 return ret; 676 } 677 } 678 679 return 0; 680 } 681 682 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 683 SpaprMachineState *spapr) 684 { 685 MachineState *ms = MACHINE(spapr); 686 PowerPCCPU *cpu = POWERPC_CPU(cs); 687 CPUPPCState *env = &cpu->env; 688 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 689 int index = spapr_get_vcpu_id(cpu); 690 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 691 0xffffffff, 0xffffffff}; 692 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 693 : SPAPR_TIMEBASE_FREQ; 694 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 695 uint32_t page_sizes_prop[64]; 696 size_t page_sizes_prop_size; 697 unsigned int smp_threads = ms->smp.threads; 698 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 699 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 700 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 701 SpaprDrc *drc; 702 int drc_index; 703 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 704 int i; 705 706 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 707 if (drc) { 708 drc_index = spapr_drc_index(drc); 709 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 710 } 711 712 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 713 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 714 715 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 716 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 717 env->dcache_line_size))); 718 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 719 env->dcache_line_size))); 720 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 721 env->icache_line_size))); 722 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 723 env->icache_line_size))); 724 725 if (pcc->l1_dcache_size) { 726 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 727 pcc->l1_dcache_size))); 728 } else { 729 warn_report("Unknown L1 dcache size for cpu"); 730 } 731 if (pcc->l1_icache_size) { 732 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 733 pcc->l1_icache_size))); 734 } else { 735 warn_report("Unknown L1 icache size for cpu"); 736 } 737 738 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 739 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 740 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 741 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 742 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 743 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 744 745 if (env->spr_cb[SPR_PURR].oea_read) { 746 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 747 } 748 if (env->spr_cb[SPR_SPURR].oea_read) { 749 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 750 } 751 752 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 753 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 754 segs, sizeof(segs)))); 755 } 756 757 /* Advertise VSX (vector extensions) if available 758 * 1 == VMX / Altivec available 759 * 2 == VSX available 760 * 761 * Only CPUs for which we create core types in spapr_cpu_core.c 762 * are possible, and all of those have VMX */ 763 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 764 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 765 } else { 766 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 767 } 768 769 /* Advertise DFP (Decimal Floating Point) if available 770 * 0 / no property == no DFP 771 * 1 == DFP available */ 772 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 773 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 774 } 775 776 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 777 sizeof(page_sizes_prop)); 778 if (page_sizes_prop_size) { 779 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 780 page_sizes_prop, page_sizes_prop_size))); 781 } 782 783 spapr_dt_pa_features(spapr, cpu, fdt, offset); 784 785 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 786 cs->cpu_index / vcpus_per_socket))); 787 788 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 789 pft_size_prop, sizeof(pft_size_prop)))); 790 791 if (ms->numa_state->num_nodes > 1) { 792 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 793 } 794 795 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 796 797 if (pcc->radix_page_info) { 798 for (i = 0; i < pcc->radix_page_info->count; i++) { 799 radix_AP_encodings[i] = 800 cpu_to_be32(pcc->radix_page_info->entries[i]); 801 } 802 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 803 radix_AP_encodings, 804 pcc->radix_page_info->count * 805 sizeof(radix_AP_encodings[0])))); 806 } 807 808 /* 809 * We set this property to let the guest know that it can use the large 810 * decrementer and its width in bits. 811 */ 812 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 813 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 814 pcc->lrg_decr_bits))); 815 } 816 817 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 818 { 819 CPUState **rev; 820 CPUState *cs; 821 int n_cpus; 822 int cpus_offset; 823 char *nodename; 824 int i; 825 826 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 827 _FDT(cpus_offset); 828 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 829 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 830 831 /* 832 * We walk the CPUs in reverse order to ensure that CPU DT nodes 833 * created by fdt_add_subnode() end up in the right order in FDT 834 * for the guest kernel the enumerate the CPUs correctly. 835 * 836 * The CPU list cannot be traversed in reverse order, so we need 837 * to do extra work. 838 */ 839 n_cpus = 0; 840 rev = NULL; 841 CPU_FOREACH(cs) { 842 rev = g_renew(CPUState *, rev, n_cpus + 1); 843 rev[n_cpus++] = cs; 844 } 845 846 for (i = n_cpus - 1; i >= 0; i--) { 847 CPUState *cs = rev[i]; 848 PowerPCCPU *cpu = POWERPC_CPU(cs); 849 int index = spapr_get_vcpu_id(cpu); 850 DeviceClass *dc = DEVICE_GET_CLASS(cs); 851 int offset; 852 853 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 854 continue; 855 } 856 857 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 858 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 859 g_free(nodename); 860 _FDT(offset); 861 spapr_dt_cpu(cs, fdt, offset, spapr); 862 } 863 864 g_free(rev); 865 } 866 867 static int spapr_dt_rng(void *fdt) 868 { 869 int node; 870 int ret; 871 872 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 873 if (node <= 0) { 874 return -1; 875 } 876 ret = fdt_setprop_string(fdt, node, "device_type", 877 "ibm,platform-facilities"); 878 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 879 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 880 881 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 882 if (node <= 0) { 883 return -1; 884 } 885 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 886 887 return ret ? -1 : 0; 888 } 889 890 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 891 { 892 MachineState *ms = MACHINE(spapr); 893 int rtas; 894 GString *hypertas = g_string_sized_new(256); 895 GString *qemu_hypertas = g_string_sized_new(256); 896 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 897 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 898 memory_region_size(&MACHINE(spapr)->device_memory->mr); 899 uint32_t lrdr_capacity[] = { 900 cpu_to_be32(max_device_addr >> 32), 901 cpu_to_be32(max_device_addr & 0xffffffff), 902 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 903 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 904 }; 905 uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0); 906 uint32_t maxdomains[] = { 907 cpu_to_be32(4), 908 maxdomain, 909 maxdomain, 910 maxdomain, 911 cpu_to_be32(spapr->gpu_numa_id), 912 }; 913 914 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 915 916 /* hypertas */ 917 add_str(hypertas, "hcall-pft"); 918 add_str(hypertas, "hcall-term"); 919 add_str(hypertas, "hcall-dabr"); 920 add_str(hypertas, "hcall-interrupt"); 921 add_str(hypertas, "hcall-tce"); 922 add_str(hypertas, "hcall-vio"); 923 add_str(hypertas, "hcall-splpar"); 924 add_str(hypertas, "hcall-join"); 925 add_str(hypertas, "hcall-bulk"); 926 add_str(hypertas, "hcall-set-mode"); 927 add_str(hypertas, "hcall-sprg0"); 928 add_str(hypertas, "hcall-copy"); 929 add_str(hypertas, "hcall-debug"); 930 add_str(hypertas, "hcall-vphn"); 931 add_str(qemu_hypertas, "hcall-memop1"); 932 933 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 934 add_str(hypertas, "hcall-multi-tce"); 935 } 936 937 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 938 add_str(hypertas, "hcall-hpt-resize"); 939 } 940 941 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 942 hypertas->str, hypertas->len)); 943 g_string_free(hypertas, TRUE); 944 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 945 qemu_hypertas->str, qemu_hypertas->len)); 946 g_string_free(qemu_hypertas, TRUE); 947 948 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 949 refpoints, sizeof(refpoints))); 950 951 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 952 maxdomains, sizeof(maxdomains))); 953 954 /* 955 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 956 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 957 * 958 * The system reset requirements are driven by existing Linux and PowerVM 959 * implementation which (contrary to PAPR) saves r3 in the error log 960 * structure like machine check, so Linux expects to find the saved r3 961 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 962 * does not look at the error value). 963 * 964 * System reset interrupts are not subject to interlock like machine 965 * check, so this memory area could be corrupted if the sreset is 966 * interrupted by a machine check (or vice versa) if it was shared. To 967 * prevent this, system reset uses per-CPU areas for the sreset save 968 * area. A system reset that interrupts a system reset handler could 969 * still overwrite this area, but Linux doesn't try to recover in that 970 * case anyway. 971 * 972 * The extra 8 bytes is required because Linux's FWNMI error log check 973 * is off-by-one. 974 */ 975 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_ERROR_LOG_MAX + 976 ms->smp.max_cpus * sizeof(uint64_t)*2 + sizeof(uint64_t))); 977 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 978 RTAS_ERROR_LOG_MAX)); 979 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 980 RTAS_EVENT_SCAN_RATE)); 981 982 g_assert(msi_nonbroken); 983 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 984 985 /* 986 * According to PAPR, rtas ibm,os-term does not guarantee a return 987 * back to the guest cpu. 988 * 989 * While an additional ibm,extended-os-term property indicates 990 * that rtas call return will always occur. Set this property. 991 */ 992 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 993 994 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 995 lrdr_capacity, sizeof(lrdr_capacity))); 996 997 spapr_dt_rtas_tokens(fdt, rtas); 998 } 999 1000 /* 1001 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 1002 * and the XIVE features that the guest may request and thus the valid 1003 * values for bytes 23..26 of option vector 5: 1004 */ 1005 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 1006 int chosen) 1007 { 1008 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1009 1010 char val[2 * 4] = { 1011 23, 0x00, /* XICS / XIVE mode */ 1012 24, 0x00, /* Hash/Radix, filled in below. */ 1013 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1014 26, 0x40, /* Radix options: GTSE == yes. */ 1015 }; 1016 1017 if (spapr->irq->xics && spapr->irq->xive) { 1018 val[1] = SPAPR_OV5_XIVE_BOTH; 1019 } else if (spapr->irq->xive) { 1020 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 1021 } else { 1022 assert(spapr->irq->xics); 1023 val[1] = SPAPR_OV5_XIVE_LEGACY; 1024 } 1025 1026 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1027 first_ppc_cpu->compat_pvr)) { 1028 /* 1029 * If we're in a pre POWER9 compat mode then the guest should 1030 * do hash and use the legacy interrupt mode 1031 */ 1032 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 1033 val[3] = 0x00; /* Hash */ 1034 } else if (kvm_enabled()) { 1035 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1036 val[3] = 0x80; /* OV5_MMU_BOTH */ 1037 } else if (kvmppc_has_cap_mmu_radix()) { 1038 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1039 } else { 1040 val[3] = 0x00; /* Hash */ 1041 } 1042 } else { 1043 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1044 val[3] = 0xC0; 1045 } 1046 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1047 val, sizeof(val))); 1048 } 1049 1050 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1051 { 1052 MachineState *machine = MACHINE(spapr); 1053 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1054 int chosen; 1055 1056 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1057 1058 if (reset) { 1059 const char *boot_device = machine->boot_order; 1060 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1061 size_t cb = 0; 1062 char *bootlist = get_boot_devices_list(&cb); 1063 1064 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1065 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1066 machine->kernel_cmdline)); 1067 } 1068 1069 if (spapr->initrd_size) { 1070 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1071 spapr->initrd_base)); 1072 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1073 spapr->initrd_base + spapr->initrd_size)); 1074 } 1075 1076 if (spapr->kernel_size) { 1077 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1078 cpu_to_be64(spapr->kernel_size) }; 1079 1080 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1081 &kprop, sizeof(kprop))); 1082 if (spapr->kernel_le) { 1083 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1084 } 1085 } 1086 if (boot_menu) { 1087 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1088 } 1089 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1090 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1091 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1092 1093 if (cb && bootlist) { 1094 int i; 1095 1096 for (i = 0; i < cb; i++) { 1097 if (bootlist[i] == '\n') { 1098 bootlist[i] = ' '; 1099 } 1100 } 1101 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1102 } 1103 1104 if (boot_device && strlen(boot_device)) { 1105 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1106 } 1107 1108 if (!spapr->has_graphics && stdout_path) { 1109 /* 1110 * "linux,stdout-path" and "stdout" properties are 1111 * deprecated by linux kernel. New platforms should only 1112 * use the "stdout-path" property. Set the new property 1113 * and continue using older property to remain compatible 1114 * with the existing firmware. 1115 */ 1116 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1117 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1118 } 1119 1120 /* 1121 * We can deal with BAR reallocation just fine, advertise it 1122 * to the guest 1123 */ 1124 if (smc->linux_pci_probe) { 1125 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1126 } 1127 1128 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1129 1130 g_free(stdout_path); 1131 g_free(bootlist); 1132 } 1133 1134 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1135 } 1136 1137 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1138 { 1139 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1140 * KVM to work under pHyp with some guest co-operation */ 1141 int hypervisor; 1142 uint8_t hypercall[16]; 1143 1144 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1145 /* indicate KVM hypercall interface */ 1146 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1147 if (kvmppc_has_cap_fixup_hcalls()) { 1148 /* 1149 * Older KVM versions with older guest kernels were broken 1150 * with the magic page, don't allow the guest to map it. 1151 */ 1152 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1153 sizeof(hypercall))) { 1154 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1155 hypercall, sizeof(hypercall))); 1156 } 1157 } 1158 } 1159 1160 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1161 { 1162 MachineState *machine = MACHINE(spapr); 1163 MachineClass *mc = MACHINE_GET_CLASS(machine); 1164 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1165 int ret; 1166 void *fdt; 1167 SpaprPhbState *phb; 1168 char *buf; 1169 1170 fdt = g_malloc0(space); 1171 _FDT((fdt_create_empty_tree(fdt, space))); 1172 1173 /* Root node */ 1174 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1175 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1176 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1177 1178 /* Guest UUID & Name*/ 1179 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1180 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1181 if (qemu_uuid_set) { 1182 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1183 } 1184 g_free(buf); 1185 1186 if (qemu_get_vm_name()) { 1187 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1188 qemu_get_vm_name())); 1189 } 1190 1191 /* Host Model & Serial Number */ 1192 if (spapr->host_model) { 1193 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1194 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1195 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1196 g_free(buf); 1197 } 1198 1199 if (spapr->host_serial) { 1200 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1201 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1202 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1203 g_free(buf); 1204 } 1205 1206 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1207 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1208 1209 /* /interrupt controller */ 1210 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1211 1212 ret = spapr_dt_memory(spapr, fdt); 1213 if (ret < 0) { 1214 error_report("couldn't setup memory nodes in fdt"); 1215 exit(1); 1216 } 1217 1218 /* /vdevice */ 1219 spapr_dt_vdevice(spapr->vio_bus, fdt); 1220 1221 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1222 ret = spapr_dt_rng(fdt); 1223 if (ret < 0) { 1224 error_report("could not set up rng device in the fdt"); 1225 exit(1); 1226 } 1227 } 1228 1229 QLIST_FOREACH(phb, &spapr->phbs, list) { 1230 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1231 if (ret < 0) { 1232 error_report("couldn't setup PCI devices in fdt"); 1233 exit(1); 1234 } 1235 } 1236 1237 spapr_dt_cpus(fdt, spapr); 1238 1239 if (smc->dr_lmb_enabled) { 1240 _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1241 } 1242 1243 if (mc->has_hotpluggable_cpus) { 1244 int offset = fdt_path_offset(fdt, "/cpus"); 1245 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1246 if (ret < 0) { 1247 error_report("Couldn't set up CPU DR device tree properties"); 1248 exit(1); 1249 } 1250 } 1251 1252 /* /event-sources */ 1253 spapr_dt_events(spapr, fdt); 1254 1255 /* /rtas */ 1256 spapr_dt_rtas(spapr, fdt); 1257 1258 /* /chosen */ 1259 spapr_dt_chosen(spapr, fdt, reset); 1260 1261 /* /hypervisor */ 1262 if (kvm_enabled()) { 1263 spapr_dt_hypervisor(spapr, fdt); 1264 } 1265 1266 /* Build memory reserve map */ 1267 if (reset) { 1268 if (spapr->kernel_size) { 1269 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1270 spapr->kernel_size))); 1271 } 1272 if (spapr->initrd_size) { 1273 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1274 spapr->initrd_size))); 1275 } 1276 } 1277 1278 if (smc->dr_phb_enabled) { 1279 ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB); 1280 if (ret < 0) { 1281 error_report("Couldn't set up PHB DR device tree properties"); 1282 exit(1); 1283 } 1284 } 1285 1286 /* NVDIMM devices */ 1287 if (mc->nvdimm_supported) { 1288 spapr_dt_persistent_memory(fdt); 1289 } 1290 1291 return fdt; 1292 } 1293 1294 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1295 { 1296 SpaprMachineState *spapr = opaque; 1297 1298 return (addr & 0x0fffffff) + spapr->kernel_addr; 1299 } 1300 1301 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1302 PowerPCCPU *cpu) 1303 { 1304 CPUPPCState *env = &cpu->env; 1305 1306 /* The TCG path should also be holding the BQL at this point */ 1307 g_assert(qemu_mutex_iothread_locked()); 1308 1309 if (msr_pr) { 1310 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1311 env->gpr[3] = H_PRIVILEGE; 1312 } else { 1313 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1314 } 1315 } 1316 1317 struct LPCRSyncState { 1318 target_ulong value; 1319 target_ulong mask; 1320 }; 1321 1322 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1323 { 1324 struct LPCRSyncState *s = arg.host_ptr; 1325 PowerPCCPU *cpu = POWERPC_CPU(cs); 1326 CPUPPCState *env = &cpu->env; 1327 target_ulong lpcr; 1328 1329 cpu_synchronize_state(cs); 1330 lpcr = env->spr[SPR_LPCR]; 1331 lpcr &= ~s->mask; 1332 lpcr |= s->value; 1333 ppc_store_lpcr(cpu, lpcr); 1334 } 1335 1336 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1337 { 1338 CPUState *cs; 1339 struct LPCRSyncState s = { 1340 .value = value, 1341 .mask = mask 1342 }; 1343 CPU_FOREACH(cs) { 1344 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1345 } 1346 } 1347 1348 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1349 { 1350 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1351 1352 /* Copy PATE1:GR into PATE0:HR */ 1353 entry->dw0 = spapr->patb_entry & PATE0_HR; 1354 entry->dw1 = spapr->patb_entry; 1355 } 1356 1357 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1358 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1359 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1360 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1361 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1362 1363 /* 1364 * Get the fd to access the kernel htab, re-opening it if necessary 1365 */ 1366 static int get_htab_fd(SpaprMachineState *spapr) 1367 { 1368 Error *local_err = NULL; 1369 1370 if (spapr->htab_fd >= 0) { 1371 return spapr->htab_fd; 1372 } 1373 1374 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1375 if (spapr->htab_fd < 0) { 1376 error_report_err(local_err); 1377 } 1378 1379 return spapr->htab_fd; 1380 } 1381 1382 void close_htab_fd(SpaprMachineState *spapr) 1383 { 1384 if (spapr->htab_fd >= 0) { 1385 close(spapr->htab_fd); 1386 } 1387 spapr->htab_fd = -1; 1388 } 1389 1390 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1391 { 1392 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1393 1394 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1395 } 1396 1397 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1398 { 1399 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1400 1401 assert(kvm_enabled()); 1402 1403 if (!spapr->htab) { 1404 return 0; 1405 } 1406 1407 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1408 } 1409 1410 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1411 hwaddr ptex, int n) 1412 { 1413 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1414 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1415 1416 if (!spapr->htab) { 1417 /* 1418 * HTAB is controlled by KVM. Fetch into temporary buffer 1419 */ 1420 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1421 kvmppc_read_hptes(hptes, ptex, n); 1422 return hptes; 1423 } 1424 1425 /* 1426 * HTAB is controlled by QEMU. Just point to the internally 1427 * accessible PTEG. 1428 */ 1429 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1430 } 1431 1432 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1433 const ppc_hash_pte64_t *hptes, 1434 hwaddr ptex, int n) 1435 { 1436 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1437 1438 if (!spapr->htab) { 1439 g_free((void *)hptes); 1440 } 1441 1442 /* Nothing to do for qemu managed HPT */ 1443 } 1444 1445 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1446 uint64_t pte0, uint64_t pte1) 1447 { 1448 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1449 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1450 1451 if (!spapr->htab) { 1452 kvmppc_write_hpte(ptex, pte0, pte1); 1453 } else { 1454 if (pte0 & HPTE64_V_VALID) { 1455 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1456 /* 1457 * When setting valid, we write PTE1 first. This ensures 1458 * proper synchronization with the reading code in 1459 * ppc_hash64_pteg_search() 1460 */ 1461 smp_wmb(); 1462 stq_p(spapr->htab + offset, pte0); 1463 } else { 1464 stq_p(spapr->htab + offset, pte0); 1465 /* 1466 * When clearing it we set PTE0 first. This ensures proper 1467 * synchronization with the reading code in 1468 * ppc_hash64_pteg_search() 1469 */ 1470 smp_wmb(); 1471 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1472 } 1473 } 1474 } 1475 1476 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1477 uint64_t pte1) 1478 { 1479 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1480 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1481 1482 if (!spapr->htab) { 1483 /* There should always be a hash table when this is called */ 1484 error_report("spapr_hpte_set_c called with no hash table !"); 1485 return; 1486 } 1487 1488 /* The HW performs a non-atomic byte update */ 1489 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1490 } 1491 1492 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1493 uint64_t pte1) 1494 { 1495 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1496 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1497 1498 if (!spapr->htab) { 1499 /* There should always be a hash table when this is called */ 1500 error_report("spapr_hpte_set_r called with no hash table !"); 1501 return; 1502 } 1503 1504 /* The HW performs a non-atomic byte update */ 1505 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1506 } 1507 1508 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1509 { 1510 int shift; 1511 1512 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1513 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1514 * that's much more than is needed for Linux guests */ 1515 shift = ctz64(pow2ceil(ramsize)) - 7; 1516 shift = MAX(shift, 18); /* Minimum architected size */ 1517 shift = MIN(shift, 46); /* Maximum architected size */ 1518 return shift; 1519 } 1520 1521 void spapr_free_hpt(SpaprMachineState *spapr) 1522 { 1523 g_free(spapr->htab); 1524 spapr->htab = NULL; 1525 spapr->htab_shift = 0; 1526 close_htab_fd(spapr); 1527 } 1528 1529 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 1530 Error **errp) 1531 { 1532 long rc; 1533 1534 /* Clean up any HPT info from a previous boot */ 1535 spapr_free_hpt(spapr); 1536 1537 rc = kvmppc_reset_htab(shift); 1538 if (rc < 0) { 1539 /* kernel-side HPT needed, but couldn't allocate one */ 1540 error_setg_errno(errp, errno, 1541 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1542 shift); 1543 /* This is almost certainly fatal, but if the caller really 1544 * wants to carry on with shift == 0, it's welcome to try */ 1545 } else if (rc > 0) { 1546 /* kernel-side HPT allocated */ 1547 if (rc != shift) { 1548 error_setg(errp, 1549 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1550 shift, rc); 1551 } 1552 1553 spapr->htab_shift = shift; 1554 spapr->htab = NULL; 1555 } else { 1556 /* kernel-side HPT not needed, allocate in userspace instead */ 1557 size_t size = 1ULL << shift; 1558 int i; 1559 1560 spapr->htab = qemu_memalign(size, size); 1561 if (!spapr->htab) { 1562 error_setg_errno(errp, errno, 1563 "Could not allocate HPT of order %d", shift); 1564 return; 1565 } 1566 1567 memset(spapr->htab, 0, size); 1568 spapr->htab_shift = shift; 1569 1570 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1571 DIRTY_HPTE(HPTE(spapr->htab, i)); 1572 } 1573 } 1574 /* We're setting up a hash table, so that means we're not radix */ 1575 spapr->patb_entry = 0; 1576 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1577 } 1578 1579 void spapr_setup_hpt(SpaprMachineState *spapr) 1580 { 1581 int hpt_shift; 1582 1583 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1584 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1585 } else { 1586 uint64_t current_ram_size; 1587 1588 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1589 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1590 } 1591 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1592 1593 if (kvm_enabled()) { 1594 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1595 1596 /* Check our RMA fits in the possible VRMA */ 1597 if (vrma_limit < spapr->rma_size) { 1598 error_report("Unable to create %" HWADDR_PRIu 1599 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1600 spapr->rma_size / MiB, vrma_limit / MiB); 1601 exit(EXIT_FAILURE); 1602 } 1603 } 1604 } 1605 1606 static int spapr_reset_drcs(Object *child, void *opaque) 1607 { 1608 SpaprDrc *drc = 1609 (SpaprDrc *) object_dynamic_cast(child, 1610 TYPE_SPAPR_DR_CONNECTOR); 1611 1612 if (drc) { 1613 spapr_drc_reset(drc); 1614 } 1615 1616 return 0; 1617 } 1618 1619 static void spapr_machine_reset(MachineState *machine) 1620 { 1621 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1622 PowerPCCPU *first_ppc_cpu; 1623 hwaddr fdt_addr; 1624 void *fdt; 1625 int rc; 1626 1627 kvmppc_svm_off(&error_fatal); 1628 spapr_caps_apply(spapr); 1629 1630 first_ppc_cpu = POWERPC_CPU(first_cpu); 1631 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1632 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1633 spapr->max_compat_pvr)) { 1634 /* 1635 * If using KVM with radix mode available, VCPUs can be started 1636 * without a HPT because KVM will start them in radix mode. 1637 * Set the GR bit in PATE so that we know there is no HPT. 1638 */ 1639 spapr->patb_entry = PATE1_GR; 1640 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1641 } else { 1642 spapr_setup_hpt(spapr); 1643 } 1644 1645 qemu_devices_reset(); 1646 1647 spapr_ovec_cleanup(spapr->ov5_cas); 1648 spapr->ov5_cas = spapr_ovec_new(); 1649 1650 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1651 1652 /* 1653 * This is fixing some of the default configuration of the XIVE 1654 * devices. To be called after the reset of the machine devices. 1655 */ 1656 spapr_irq_reset(spapr, &error_fatal); 1657 1658 /* 1659 * There is no CAS under qtest. Simulate one to please the code that 1660 * depends on spapr->ov5_cas. This is especially needed to test device 1661 * unplug, so we do that before resetting the DRCs. 1662 */ 1663 if (qtest_enabled()) { 1664 spapr_ovec_cleanup(spapr->ov5_cas); 1665 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1666 } 1667 1668 /* DRC reset may cause a device to be unplugged. This will cause troubles 1669 * if this device is used by another device (eg, a running vhost backend 1670 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1671 * situations, we reset DRCs after all devices have been reset. 1672 */ 1673 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1674 1675 spapr_clear_pending_events(spapr); 1676 1677 /* 1678 * We place the device tree and RTAS just below either the top of the RMA, 1679 * or just below 2GB, whichever is lower, so that it can be 1680 * processed with 32-bit real mode code if necessary 1681 */ 1682 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; 1683 1684 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1685 1686 rc = fdt_pack(fdt); 1687 1688 /* Should only fail if we've built a corrupted tree */ 1689 assert(rc == 0); 1690 1691 /* Load the fdt */ 1692 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1693 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1694 g_free(spapr->fdt_blob); 1695 spapr->fdt_size = fdt_totalsize(fdt); 1696 spapr->fdt_initial_size = spapr->fdt_size; 1697 spapr->fdt_blob = fdt; 1698 1699 /* Set up the entry state */ 1700 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0); 1701 first_ppc_cpu->env.gpr[5] = 0; 1702 1703 spapr->fwnmi_system_reset_addr = -1; 1704 spapr->fwnmi_machine_check_addr = -1; 1705 spapr->fwnmi_machine_check_interlock = -1; 1706 1707 /* Signal all vCPUs waiting on this condition */ 1708 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1709 1710 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1711 } 1712 1713 static void spapr_create_nvram(SpaprMachineState *spapr) 1714 { 1715 DeviceState *dev = qdev_new("spapr-nvram"); 1716 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1717 1718 if (dinfo) { 1719 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1720 &error_fatal); 1721 } 1722 1723 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1724 1725 spapr->nvram = (struct SpaprNvram *)dev; 1726 } 1727 1728 static void spapr_rtc_create(SpaprMachineState *spapr) 1729 { 1730 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1731 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1732 &error_fatal, NULL); 1733 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1734 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1735 "date"); 1736 } 1737 1738 /* Returns whether we want to use VGA or not */ 1739 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1740 { 1741 switch (vga_interface_type) { 1742 case VGA_NONE: 1743 return false; 1744 case VGA_DEVICE: 1745 return true; 1746 case VGA_STD: 1747 case VGA_VIRTIO: 1748 case VGA_CIRRUS: 1749 return pci_vga_init(pci_bus) != NULL; 1750 default: 1751 error_setg(errp, 1752 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1753 return false; 1754 } 1755 } 1756 1757 static int spapr_pre_load(void *opaque) 1758 { 1759 int rc; 1760 1761 rc = spapr_caps_pre_load(opaque); 1762 if (rc) { 1763 return rc; 1764 } 1765 1766 return 0; 1767 } 1768 1769 static int spapr_post_load(void *opaque, int version_id) 1770 { 1771 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1772 int err = 0; 1773 1774 err = spapr_caps_post_migration(spapr); 1775 if (err) { 1776 return err; 1777 } 1778 1779 /* 1780 * In earlier versions, there was no separate qdev for the PAPR 1781 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1782 * So when migrating from those versions, poke the incoming offset 1783 * value into the RTC device 1784 */ 1785 if (version_id < 3) { 1786 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1787 if (err) { 1788 return err; 1789 } 1790 } 1791 1792 if (kvm_enabled() && spapr->patb_entry) { 1793 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1794 bool radix = !!(spapr->patb_entry & PATE1_GR); 1795 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1796 1797 /* 1798 * Update LPCR:HR and UPRT as they may not be set properly in 1799 * the stream 1800 */ 1801 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1802 LPCR_HR | LPCR_UPRT); 1803 1804 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1805 if (err) { 1806 error_report("Process table config unsupported by the host"); 1807 return -EINVAL; 1808 } 1809 } 1810 1811 err = spapr_irq_post_load(spapr, version_id); 1812 if (err) { 1813 return err; 1814 } 1815 1816 return err; 1817 } 1818 1819 static int spapr_pre_save(void *opaque) 1820 { 1821 int rc; 1822 1823 rc = spapr_caps_pre_save(opaque); 1824 if (rc) { 1825 return rc; 1826 } 1827 1828 return 0; 1829 } 1830 1831 static bool version_before_3(void *opaque, int version_id) 1832 { 1833 return version_id < 3; 1834 } 1835 1836 static bool spapr_pending_events_needed(void *opaque) 1837 { 1838 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1839 return !QTAILQ_EMPTY(&spapr->pending_events); 1840 } 1841 1842 static const VMStateDescription vmstate_spapr_event_entry = { 1843 .name = "spapr_event_log_entry", 1844 .version_id = 1, 1845 .minimum_version_id = 1, 1846 .fields = (VMStateField[]) { 1847 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1848 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1849 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1850 NULL, extended_length), 1851 VMSTATE_END_OF_LIST() 1852 }, 1853 }; 1854 1855 static const VMStateDescription vmstate_spapr_pending_events = { 1856 .name = "spapr_pending_events", 1857 .version_id = 1, 1858 .minimum_version_id = 1, 1859 .needed = spapr_pending_events_needed, 1860 .fields = (VMStateField[]) { 1861 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1862 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1863 VMSTATE_END_OF_LIST() 1864 }, 1865 }; 1866 1867 static bool spapr_ov5_cas_needed(void *opaque) 1868 { 1869 SpaprMachineState *spapr = opaque; 1870 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1871 bool cas_needed; 1872 1873 /* Prior to the introduction of SpaprOptionVector, we had two option 1874 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1875 * Both of these options encode machine topology into the device-tree 1876 * in such a way that the now-booted OS should still be able to interact 1877 * appropriately with QEMU regardless of what options were actually 1878 * negotiatied on the source side. 1879 * 1880 * As such, we can avoid migrating the CAS-negotiated options if these 1881 * are the only options available on the current machine/platform. 1882 * Since these are the only options available for pseries-2.7 and 1883 * earlier, this allows us to maintain old->new/new->old migration 1884 * compatibility. 1885 * 1886 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1887 * via default pseries-2.8 machines and explicit command-line parameters. 1888 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1889 * of the actual CAS-negotiated values to continue working properly. For 1890 * example, availability of memory unplug depends on knowing whether 1891 * OV5_HP_EVT was negotiated via CAS. 1892 * 1893 * Thus, for any cases where the set of available CAS-negotiatable 1894 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1895 * include the CAS-negotiated options in the migration stream, unless 1896 * if they affect boot time behaviour only. 1897 */ 1898 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1899 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1900 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1901 1902 /* We need extra information if we have any bits outside the mask 1903 * defined above */ 1904 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1905 1906 spapr_ovec_cleanup(ov5_mask); 1907 1908 return cas_needed; 1909 } 1910 1911 static const VMStateDescription vmstate_spapr_ov5_cas = { 1912 .name = "spapr_option_vector_ov5_cas", 1913 .version_id = 1, 1914 .minimum_version_id = 1, 1915 .needed = spapr_ov5_cas_needed, 1916 .fields = (VMStateField[]) { 1917 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1918 vmstate_spapr_ovec, SpaprOptionVector), 1919 VMSTATE_END_OF_LIST() 1920 }, 1921 }; 1922 1923 static bool spapr_patb_entry_needed(void *opaque) 1924 { 1925 SpaprMachineState *spapr = opaque; 1926 1927 return !!spapr->patb_entry; 1928 } 1929 1930 static const VMStateDescription vmstate_spapr_patb_entry = { 1931 .name = "spapr_patb_entry", 1932 .version_id = 1, 1933 .minimum_version_id = 1, 1934 .needed = spapr_patb_entry_needed, 1935 .fields = (VMStateField[]) { 1936 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1937 VMSTATE_END_OF_LIST() 1938 }, 1939 }; 1940 1941 static bool spapr_irq_map_needed(void *opaque) 1942 { 1943 SpaprMachineState *spapr = opaque; 1944 1945 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1946 } 1947 1948 static const VMStateDescription vmstate_spapr_irq_map = { 1949 .name = "spapr_irq_map", 1950 .version_id = 1, 1951 .minimum_version_id = 1, 1952 .needed = spapr_irq_map_needed, 1953 .fields = (VMStateField[]) { 1954 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1955 VMSTATE_END_OF_LIST() 1956 }, 1957 }; 1958 1959 static bool spapr_dtb_needed(void *opaque) 1960 { 1961 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1962 1963 return smc->update_dt_enabled; 1964 } 1965 1966 static int spapr_dtb_pre_load(void *opaque) 1967 { 1968 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1969 1970 g_free(spapr->fdt_blob); 1971 spapr->fdt_blob = NULL; 1972 spapr->fdt_size = 0; 1973 1974 return 0; 1975 } 1976 1977 static const VMStateDescription vmstate_spapr_dtb = { 1978 .name = "spapr_dtb", 1979 .version_id = 1, 1980 .minimum_version_id = 1, 1981 .needed = spapr_dtb_needed, 1982 .pre_load = spapr_dtb_pre_load, 1983 .fields = (VMStateField[]) { 1984 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1985 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1986 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1987 fdt_size), 1988 VMSTATE_END_OF_LIST() 1989 }, 1990 }; 1991 1992 static bool spapr_fwnmi_needed(void *opaque) 1993 { 1994 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1995 1996 return spapr->fwnmi_machine_check_addr != -1; 1997 } 1998 1999 static int spapr_fwnmi_pre_save(void *opaque) 2000 { 2001 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2002 2003 /* 2004 * Check if machine check handling is in progress and print a 2005 * warning message. 2006 */ 2007 if (spapr->fwnmi_machine_check_interlock != -1) { 2008 warn_report("A machine check is being handled during migration. The" 2009 "handler may run and log hardware error on the destination"); 2010 } 2011 2012 return 0; 2013 } 2014 2015 static const VMStateDescription vmstate_spapr_fwnmi = { 2016 .name = "spapr_fwnmi", 2017 .version_id = 1, 2018 .minimum_version_id = 1, 2019 .needed = spapr_fwnmi_needed, 2020 .pre_save = spapr_fwnmi_pre_save, 2021 .fields = (VMStateField[]) { 2022 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 2023 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 2024 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 2025 VMSTATE_END_OF_LIST() 2026 }, 2027 }; 2028 2029 static const VMStateDescription vmstate_spapr = { 2030 .name = "spapr", 2031 .version_id = 3, 2032 .minimum_version_id = 1, 2033 .pre_load = spapr_pre_load, 2034 .post_load = spapr_post_load, 2035 .pre_save = spapr_pre_save, 2036 .fields = (VMStateField[]) { 2037 /* used to be @next_irq */ 2038 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2039 2040 /* RTC offset */ 2041 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2042 2043 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2044 VMSTATE_END_OF_LIST() 2045 }, 2046 .subsections = (const VMStateDescription*[]) { 2047 &vmstate_spapr_ov5_cas, 2048 &vmstate_spapr_patb_entry, 2049 &vmstate_spapr_pending_events, 2050 &vmstate_spapr_cap_htm, 2051 &vmstate_spapr_cap_vsx, 2052 &vmstate_spapr_cap_dfp, 2053 &vmstate_spapr_cap_cfpc, 2054 &vmstate_spapr_cap_sbbc, 2055 &vmstate_spapr_cap_ibs, 2056 &vmstate_spapr_cap_hpt_maxpagesize, 2057 &vmstate_spapr_irq_map, 2058 &vmstate_spapr_cap_nested_kvm_hv, 2059 &vmstate_spapr_dtb, 2060 &vmstate_spapr_cap_large_decr, 2061 &vmstate_spapr_cap_ccf_assist, 2062 &vmstate_spapr_cap_fwnmi, 2063 &vmstate_spapr_fwnmi, 2064 NULL 2065 } 2066 }; 2067 2068 static int htab_save_setup(QEMUFile *f, void *opaque) 2069 { 2070 SpaprMachineState *spapr = opaque; 2071 2072 /* "Iteration" header */ 2073 if (!spapr->htab_shift) { 2074 qemu_put_be32(f, -1); 2075 } else { 2076 qemu_put_be32(f, spapr->htab_shift); 2077 } 2078 2079 if (spapr->htab) { 2080 spapr->htab_save_index = 0; 2081 spapr->htab_first_pass = true; 2082 } else { 2083 if (spapr->htab_shift) { 2084 assert(kvm_enabled()); 2085 } 2086 } 2087 2088 2089 return 0; 2090 } 2091 2092 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2093 int chunkstart, int n_valid, int n_invalid) 2094 { 2095 qemu_put_be32(f, chunkstart); 2096 qemu_put_be16(f, n_valid); 2097 qemu_put_be16(f, n_invalid); 2098 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2099 HASH_PTE_SIZE_64 * n_valid); 2100 } 2101 2102 static void htab_save_end_marker(QEMUFile *f) 2103 { 2104 qemu_put_be32(f, 0); 2105 qemu_put_be16(f, 0); 2106 qemu_put_be16(f, 0); 2107 } 2108 2109 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2110 int64_t max_ns) 2111 { 2112 bool has_timeout = max_ns != -1; 2113 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2114 int index = spapr->htab_save_index; 2115 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2116 2117 assert(spapr->htab_first_pass); 2118 2119 do { 2120 int chunkstart; 2121 2122 /* Consume invalid HPTEs */ 2123 while ((index < htabslots) 2124 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2125 CLEAN_HPTE(HPTE(spapr->htab, index)); 2126 index++; 2127 } 2128 2129 /* Consume valid HPTEs */ 2130 chunkstart = index; 2131 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2132 && HPTE_VALID(HPTE(spapr->htab, index))) { 2133 CLEAN_HPTE(HPTE(spapr->htab, index)); 2134 index++; 2135 } 2136 2137 if (index > chunkstart) { 2138 int n_valid = index - chunkstart; 2139 2140 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2141 2142 if (has_timeout && 2143 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2144 break; 2145 } 2146 } 2147 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2148 2149 if (index >= htabslots) { 2150 assert(index == htabslots); 2151 index = 0; 2152 spapr->htab_first_pass = false; 2153 } 2154 spapr->htab_save_index = index; 2155 } 2156 2157 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2158 int64_t max_ns) 2159 { 2160 bool final = max_ns < 0; 2161 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2162 int examined = 0, sent = 0; 2163 int index = spapr->htab_save_index; 2164 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2165 2166 assert(!spapr->htab_first_pass); 2167 2168 do { 2169 int chunkstart, invalidstart; 2170 2171 /* Consume non-dirty HPTEs */ 2172 while ((index < htabslots) 2173 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2174 index++; 2175 examined++; 2176 } 2177 2178 chunkstart = index; 2179 /* Consume valid dirty HPTEs */ 2180 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2181 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2182 && HPTE_VALID(HPTE(spapr->htab, index))) { 2183 CLEAN_HPTE(HPTE(spapr->htab, index)); 2184 index++; 2185 examined++; 2186 } 2187 2188 invalidstart = index; 2189 /* Consume invalid dirty HPTEs */ 2190 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2191 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2192 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2193 CLEAN_HPTE(HPTE(spapr->htab, index)); 2194 index++; 2195 examined++; 2196 } 2197 2198 if (index > chunkstart) { 2199 int n_valid = invalidstart - chunkstart; 2200 int n_invalid = index - invalidstart; 2201 2202 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2203 sent += index - chunkstart; 2204 2205 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2206 break; 2207 } 2208 } 2209 2210 if (examined >= htabslots) { 2211 break; 2212 } 2213 2214 if (index >= htabslots) { 2215 assert(index == htabslots); 2216 index = 0; 2217 } 2218 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2219 2220 if (index >= htabslots) { 2221 assert(index == htabslots); 2222 index = 0; 2223 } 2224 2225 spapr->htab_save_index = index; 2226 2227 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2228 } 2229 2230 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2231 #define MAX_KVM_BUF_SIZE 2048 2232 2233 static int htab_save_iterate(QEMUFile *f, void *opaque) 2234 { 2235 SpaprMachineState *spapr = opaque; 2236 int fd; 2237 int rc = 0; 2238 2239 /* Iteration header */ 2240 if (!spapr->htab_shift) { 2241 qemu_put_be32(f, -1); 2242 return 1; 2243 } else { 2244 qemu_put_be32(f, 0); 2245 } 2246 2247 if (!spapr->htab) { 2248 assert(kvm_enabled()); 2249 2250 fd = get_htab_fd(spapr); 2251 if (fd < 0) { 2252 return fd; 2253 } 2254 2255 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2256 if (rc < 0) { 2257 return rc; 2258 } 2259 } else if (spapr->htab_first_pass) { 2260 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2261 } else { 2262 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2263 } 2264 2265 htab_save_end_marker(f); 2266 2267 return rc; 2268 } 2269 2270 static int htab_save_complete(QEMUFile *f, void *opaque) 2271 { 2272 SpaprMachineState *spapr = opaque; 2273 int fd; 2274 2275 /* Iteration header */ 2276 if (!spapr->htab_shift) { 2277 qemu_put_be32(f, -1); 2278 return 0; 2279 } else { 2280 qemu_put_be32(f, 0); 2281 } 2282 2283 if (!spapr->htab) { 2284 int rc; 2285 2286 assert(kvm_enabled()); 2287 2288 fd = get_htab_fd(spapr); 2289 if (fd < 0) { 2290 return fd; 2291 } 2292 2293 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2294 if (rc < 0) { 2295 return rc; 2296 } 2297 } else { 2298 if (spapr->htab_first_pass) { 2299 htab_save_first_pass(f, spapr, -1); 2300 } 2301 htab_save_later_pass(f, spapr, -1); 2302 } 2303 2304 /* End marker */ 2305 htab_save_end_marker(f); 2306 2307 return 0; 2308 } 2309 2310 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2311 { 2312 SpaprMachineState *spapr = opaque; 2313 uint32_t section_hdr; 2314 int fd = -1; 2315 Error *local_err = NULL; 2316 2317 if (version_id < 1 || version_id > 1) { 2318 error_report("htab_load() bad version"); 2319 return -EINVAL; 2320 } 2321 2322 section_hdr = qemu_get_be32(f); 2323 2324 if (section_hdr == -1) { 2325 spapr_free_hpt(spapr); 2326 return 0; 2327 } 2328 2329 if (section_hdr) { 2330 /* First section gives the htab size */ 2331 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2332 if (local_err) { 2333 error_report_err(local_err); 2334 return -EINVAL; 2335 } 2336 return 0; 2337 } 2338 2339 if (!spapr->htab) { 2340 assert(kvm_enabled()); 2341 2342 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2343 if (fd < 0) { 2344 error_report_err(local_err); 2345 return fd; 2346 } 2347 } 2348 2349 while (true) { 2350 uint32_t index; 2351 uint16_t n_valid, n_invalid; 2352 2353 index = qemu_get_be32(f); 2354 n_valid = qemu_get_be16(f); 2355 n_invalid = qemu_get_be16(f); 2356 2357 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2358 /* End of Stream */ 2359 break; 2360 } 2361 2362 if ((index + n_valid + n_invalid) > 2363 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2364 /* Bad index in stream */ 2365 error_report( 2366 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2367 index, n_valid, n_invalid, spapr->htab_shift); 2368 return -EINVAL; 2369 } 2370 2371 if (spapr->htab) { 2372 if (n_valid) { 2373 qemu_get_buffer(f, HPTE(spapr->htab, index), 2374 HASH_PTE_SIZE_64 * n_valid); 2375 } 2376 if (n_invalid) { 2377 memset(HPTE(spapr->htab, index + n_valid), 0, 2378 HASH_PTE_SIZE_64 * n_invalid); 2379 } 2380 } else { 2381 int rc; 2382 2383 assert(fd >= 0); 2384 2385 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2386 if (rc < 0) { 2387 return rc; 2388 } 2389 } 2390 } 2391 2392 if (!spapr->htab) { 2393 assert(fd >= 0); 2394 close(fd); 2395 } 2396 2397 return 0; 2398 } 2399 2400 static void htab_save_cleanup(void *opaque) 2401 { 2402 SpaprMachineState *spapr = opaque; 2403 2404 close_htab_fd(spapr); 2405 } 2406 2407 static SaveVMHandlers savevm_htab_handlers = { 2408 .save_setup = htab_save_setup, 2409 .save_live_iterate = htab_save_iterate, 2410 .save_live_complete_precopy = htab_save_complete, 2411 .save_cleanup = htab_save_cleanup, 2412 .load_state = htab_load, 2413 }; 2414 2415 static void spapr_boot_set(void *opaque, const char *boot_device, 2416 Error **errp) 2417 { 2418 MachineState *machine = MACHINE(opaque); 2419 machine->boot_order = g_strdup(boot_device); 2420 } 2421 2422 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2423 { 2424 MachineState *machine = MACHINE(spapr); 2425 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2426 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2427 int i; 2428 2429 for (i = 0; i < nr_lmbs; i++) { 2430 uint64_t addr; 2431 2432 addr = i * lmb_size + machine->device_memory->base; 2433 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2434 addr / lmb_size); 2435 } 2436 } 2437 2438 /* 2439 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2440 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2441 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2442 */ 2443 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2444 { 2445 int i; 2446 2447 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2448 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2449 " is not aligned to %" PRIu64 " MiB", 2450 machine->ram_size, 2451 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2452 return; 2453 } 2454 2455 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2456 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2457 " is not aligned to %" PRIu64 " MiB", 2458 machine->ram_size, 2459 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2460 return; 2461 } 2462 2463 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2464 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2465 error_setg(errp, 2466 "Node %d memory size 0x%" PRIx64 2467 " is not aligned to %" PRIu64 " MiB", 2468 i, machine->numa_state->nodes[i].node_mem, 2469 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2470 return; 2471 } 2472 } 2473 } 2474 2475 /* find cpu slot in machine->possible_cpus by core_id */ 2476 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2477 { 2478 int index = id / ms->smp.threads; 2479 2480 if (index >= ms->possible_cpus->len) { 2481 return NULL; 2482 } 2483 if (idx) { 2484 *idx = index; 2485 } 2486 return &ms->possible_cpus->cpus[index]; 2487 } 2488 2489 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2490 { 2491 MachineState *ms = MACHINE(spapr); 2492 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2493 Error *local_err = NULL; 2494 bool vsmt_user = !!spapr->vsmt; 2495 int kvm_smt = kvmppc_smt_threads(); 2496 int ret; 2497 unsigned int smp_threads = ms->smp.threads; 2498 2499 if (!kvm_enabled() && (smp_threads > 1)) { 2500 error_setg(errp, "TCG cannot support more than 1 thread/core " 2501 "on a pseries machine"); 2502 return; 2503 } 2504 if (!is_power_of_2(smp_threads)) { 2505 error_setg(errp, "Cannot support %d threads/core on a pseries " 2506 "machine because it must be a power of 2", smp_threads); 2507 return; 2508 } 2509 2510 /* Detemine the VSMT mode to use: */ 2511 if (vsmt_user) { 2512 if (spapr->vsmt < smp_threads) { 2513 error_setg(errp, "Cannot support VSMT mode %d" 2514 " because it must be >= threads/core (%d)", 2515 spapr->vsmt, smp_threads); 2516 return; 2517 } 2518 /* In this case, spapr->vsmt has been set by the command line */ 2519 } else if (!smc->smp_threads_vsmt) { 2520 /* 2521 * Default VSMT value is tricky, because we need it to be as 2522 * consistent as possible (for migration), but this requires 2523 * changing it for at least some existing cases. We pick 8 as 2524 * the value that we'd get with KVM on POWER8, the 2525 * overwhelmingly common case in production systems. 2526 */ 2527 spapr->vsmt = MAX(8, smp_threads); 2528 } else { 2529 spapr->vsmt = smp_threads; 2530 } 2531 2532 /* KVM: If necessary, set the SMT mode: */ 2533 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2534 ret = kvmppc_set_smt_threads(spapr->vsmt); 2535 if (ret) { 2536 /* Looks like KVM isn't able to change VSMT mode */ 2537 error_setg(&local_err, 2538 "Failed to set KVM's VSMT mode to %d (errno %d)", 2539 spapr->vsmt, ret); 2540 /* We can live with that if the default one is big enough 2541 * for the number of threads, and a submultiple of the one 2542 * we want. In this case we'll waste some vcpu ids, but 2543 * behaviour will be correct */ 2544 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2545 warn_report_err(local_err); 2546 } else { 2547 if (!vsmt_user) { 2548 error_append_hint(&local_err, 2549 "On PPC, a VM with %d threads/core" 2550 " on a host with %d threads/core" 2551 " requires the use of VSMT mode %d.\n", 2552 smp_threads, kvm_smt, spapr->vsmt); 2553 } 2554 kvmppc_error_append_smt_possible_hint(&local_err); 2555 error_propagate(errp, local_err); 2556 } 2557 } 2558 } 2559 /* else TCG: nothing to do currently */ 2560 } 2561 2562 static void spapr_init_cpus(SpaprMachineState *spapr) 2563 { 2564 MachineState *machine = MACHINE(spapr); 2565 MachineClass *mc = MACHINE_GET_CLASS(machine); 2566 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2567 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2568 const CPUArchIdList *possible_cpus; 2569 unsigned int smp_cpus = machine->smp.cpus; 2570 unsigned int smp_threads = machine->smp.threads; 2571 unsigned int max_cpus = machine->smp.max_cpus; 2572 int boot_cores_nr = smp_cpus / smp_threads; 2573 int i; 2574 2575 possible_cpus = mc->possible_cpu_arch_ids(machine); 2576 if (mc->has_hotpluggable_cpus) { 2577 if (smp_cpus % smp_threads) { 2578 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2579 smp_cpus, smp_threads); 2580 exit(1); 2581 } 2582 if (max_cpus % smp_threads) { 2583 error_report("max_cpus (%u) must be multiple of threads (%u)", 2584 max_cpus, smp_threads); 2585 exit(1); 2586 } 2587 } else { 2588 if (max_cpus != smp_cpus) { 2589 error_report("This machine version does not support CPU hotplug"); 2590 exit(1); 2591 } 2592 boot_cores_nr = possible_cpus->len; 2593 } 2594 2595 if (smc->pre_2_10_has_unused_icps) { 2596 int i; 2597 2598 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2599 /* Dummy entries get deregistered when real ICPState objects 2600 * are registered during CPU core hotplug. 2601 */ 2602 pre_2_10_vmstate_register_dummy_icp(i); 2603 } 2604 } 2605 2606 for (i = 0; i < possible_cpus->len; i++) { 2607 int core_id = i * smp_threads; 2608 2609 if (mc->has_hotpluggable_cpus) { 2610 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2611 spapr_vcpu_id(spapr, core_id)); 2612 } 2613 2614 if (i < boot_cores_nr) { 2615 Object *core = object_new(type); 2616 int nr_threads = smp_threads; 2617 2618 /* Handle the partially filled core for older machine types */ 2619 if ((i + 1) * smp_threads >= smp_cpus) { 2620 nr_threads = smp_cpus - i * smp_threads; 2621 } 2622 2623 object_property_set_int(core, "nr-threads", nr_threads, 2624 &error_fatal); 2625 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2626 &error_fatal); 2627 qdev_realize(DEVICE(core), NULL, &error_fatal); 2628 2629 object_unref(core); 2630 } 2631 } 2632 } 2633 2634 static PCIHostState *spapr_create_default_phb(void) 2635 { 2636 DeviceState *dev; 2637 2638 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2639 qdev_prop_set_uint32(dev, "index", 0); 2640 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2641 2642 return PCI_HOST_BRIDGE(dev); 2643 } 2644 2645 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2646 { 2647 MachineState *machine = MACHINE(spapr); 2648 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2649 hwaddr rma_size = machine->ram_size; 2650 hwaddr node0_size = spapr_node0_size(machine); 2651 2652 /* RMA has to fit in the first NUMA node */ 2653 rma_size = MIN(rma_size, node0_size); 2654 2655 /* 2656 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2657 * never exceed that 2658 */ 2659 rma_size = MIN(rma_size, 1 * TiB); 2660 2661 /* 2662 * Clamp the RMA size based on machine type. This is for 2663 * migration compatibility with older qemu versions, which limited 2664 * the RMA size for complicated and mostly bad reasons. 2665 */ 2666 if (smc->rma_limit) { 2667 rma_size = MIN(rma_size, smc->rma_limit); 2668 } 2669 2670 if (rma_size < MIN_RMA_SLOF) { 2671 error_setg(errp, 2672 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2673 "ldMiB guest RMA (Real Mode Area memory)", 2674 MIN_RMA_SLOF / MiB); 2675 return 0; 2676 } 2677 2678 return rma_size; 2679 } 2680 2681 /* pSeries LPAR / sPAPR hardware init */ 2682 static void spapr_machine_init(MachineState *machine) 2683 { 2684 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2685 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2686 MachineClass *mc = MACHINE_GET_CLASS(machine); 2687 const char *kernel_filename = machine->kernel_filename; 2688 const char *initrd_filename = machine->initrd_filename; 2689 PCIHostState *phb; 2690 int i; 2691 MemoryRegion *sysmem = get_system_memory(); 2692 long load_limit, fw_size; 2693 char *filename; 2694 Error *resize_hpt_err = NULL; 2695 2696 msi_nonbroken = true; 2697 2698 QLIST_INIT(&spapr->phbs); 2699 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2700 2701 /* Determine capabilities to run with */ 2702 spapr_caps_init(spapr); 2703 2704 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2705 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2706 /* 2707 * If the user explicitly requested a mode we should either 2708 * supply it, or fail completely (which we do below). But if 2709 * it's not set explicitly, we reset our mode to something 2710 * that works 2711 */ 2712 if (resize_hpt_err) { 2713 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2714 error_free(resize_hpt_err); 2715 resize_hpt_err = NULL; 2716 } else { 2717 spapr->resize_hpt = smc->resize_hpt_default; 2718 } 2719 } 2720 2721 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2722 2723 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2724 /* 2725 * User requested HPT resize, but this host can't supply it. Bail out 2726 */ 2727 error_report_err(resize_hpt_err); 2728 exit(1); 2729 } 2730 error_free(resize_hpt_err); 2731 2732 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2733 2734 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2735 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2736 2737 /* 2738 * VSMT must be set in order to be able to compute VCPU ids, ie to 2739 * call spapr_max_server_number() or spapr_vcpu_id(). 2740 */ 2741 spapr_set_vsmt_mode(spapr, &error_fatal); 2742 2743 /* Set up Interrupt Controller before we create the VCPUs */ 2744 spapr_irq_init(spapr, &error_fatal); 2745 2746 /* Set up containers for ibm,client-architecture-support negotiated options 2747 */ 2748 spapr->ov5 = spapr_ovec_new(); 2749 spapr->ov5_cas = spapr_ovec_new(); 2750 2751 if (smc->dr_lmb_enabled) { 2752 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2753 spapr_validate_node_memory(machine, &error_fatal); 2754 } 2755 2756 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2757 2758 /* advertise support for dedicated HP event source to guests */ 2759 if (spapr->use_hotplug_event_source) { 2760 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2761 } 2762 2763 /* advertise support for HPT resizing */ 2764 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2765 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2766 } 2767 2768 /* advertise support for ibm,dyamic-memory-v2 */ 2769 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2770 2771 /* advertise XIVE on POWER9 machines */ 2772 if (spapr->irq->xive) { 2773 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2774 } 2775 2776 /* init CPUs */ 2777 spapr_init_cpus(spapr); 2778 2779 /* 2780 * check we don't have a memory-less/cpu-less NUMA node 2781 * Firmware relies on the existing memory/cpu topology to provide the 2782 * NUMA topology to the kernel. 2783 * And the linux kernel needs to know the NUMA topology at start 2784 * to be able to hotplug CPUs later. 2785 */ 2786 if (machine->numa_state->num_nodes) { 2787 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2788 /* check for memory-less node */ 2789 if (machine->numa_state->nodes[i].node_mem == 0) { 2790 CPUState *cs; 2791 int found = 0; 2792 /* check for cpu-less node */ 2793 CPU_FOREACH(cs) { 2794 PowerPCCPU *cpu = POWERPC_CPU(cs); 2795 if (cpu->node_id == i) { 2796 found = 1; 2797 break; 2798 } 2799 } 2800 /* memory-less and cpu-less node */ 2801 if (!found) { 2802 error_report( 2803 "Memory-less/cpu-less nodes are not supported (node %d)", 2804 i); 2805 exit(1); 2806 } 2807 } 2808 } 2809 2810 } 2811 2812 /* 2813 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. 2814 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is 2815 * called from vPHB reset handler so we initialize the counter here. 2816 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM 2817 * must be equally distant from any other node. 2818 * The final value of spapr->gpu_numa_id is going to be written to 2819 * max-associativity-domains in spapr_build_fdt(). 2820 */ 2821 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes); 2822 2823 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2824 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2825 spapr->max_compat_pvr)) { 2826 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2827 /* KVM and TCG always allow GTSE with radix... */ 2828 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2829 } 2830 /* ... but not with hash (currently). */ 2831 2832 if (kvm_enabled()) { 2833 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2834 kvmppc_enable_logical_ci_hcalls(); 2835 kvmppc_enable_set_mode_hcall(); 2836 2837 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2838 kvmppc_enable_clear_ref_mod_hcalls(); 2839 2840 /* Enable H_PAGE_INIT */ 2841 kvmppc_enable_h_page_init(); 2842 } 2843 2844 /* map RAM */ 2845 memory_region_add_subregion(sysmem, 0, machine->ram); 2846 2847 /* always allocate the device memory information */ 2848 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2849 2850 /* initialize hotplug memory address space */ 2851 if (machine->ram_size < machine->maxram_size) { 2852 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2853 /* 2854 * Limit the number of hotpluggable memory slots to half the number 2855 * slots that KVM supports, leaving the other half for PCI and other 2856 * devices. However ensure that number of slots doesn't drop below 32. 2857 */ 2858 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2859 SPAPR_MAX_RAM_SLOTS; 2860 2861 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2862 max_memslots = SPAPR_MAX_RAM_SLOTS; 2863 } 2864 if (machine->ram_slots > max_memslots) { 2865 error_report("Specified number of memory slots %" 2866 PRIu64" exceeds max supported %d", 2867 machine->ram_slots, max_memslots); 2868 exit(1); 2869 } 2870 2871 machine->device_memory->base = ROUND_UP(machine->ram_size, 2872 SPAPR_DEVICE_MEM_ALIGN); 2873 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2874 "device-memory", device_mem_size); 2875 memory_region_add_subregion(sysmem, machine->device_memory->base, 2876 &machine->device_memory->mr); 2877 } 2878 2879 if (smc->dr_lmb_enabled) { 2880 spapr_create_lmb_dr_connectors(spapr); 2881 } 2882 2883 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { 2884 /* Create the error string for live migration blocker */ 2885 error_setg(&spapr->fwnmi_migration_blocker, 2886 "A machine check is being handled during migration. The handler" 2887 "may run and log hardware error on the destination"); 2888 } 2889 2890 if (mc->nvdimm_supported) { 2891 spapr_create_nvdimm_dr_connectors(spapr); 2892 } 2893 2894 /* Set up RTAS event infrastructure */ 2895 spapr_events_init(spapr); 2896 2897 /* Set up the RTC RTAS interfaces */ 2898 spapr_rtc_create(spapr); 2899 2900 /* Set up VIO bus */ 2901 spapr->vio_bus = spapr_vio_bus_init(); 2902 2903 for (i = 0; i < serial_max_hds(); i++) { 2904 if (serial_hd(i)) { 2905 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2906 } 2907 } 2908 2909 /* We always have at least the nvram device on VIO */ 2910 spapr_create_nvram(spapr); 2911 2912 /* 2913 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2914 * connectors (described in root DT node's "ibm,drc-types" property) 2915 * are pre-initialized here. additional child connectors (such as 2916 * connectors for a PHBs PCI slots) are added as needed during their 2917 * parent's realization. 2918 */ 2919 if (smc->dr_phb_enabled) { 2920 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2921 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2922 } 2923 } 2924 2925 /* Set up PCI */ 2926 spapr_pci_rtas_init(); 2927 2928 phb = spapr_create_default_phb(); 2929 2930 for (i = 0; i < nb_nics; i++) { 2931 NICInfo *nd = &nd_table[i]; 2932 2933 if (!nd->model) { 2934 nd->model = g_strdup("spapr-vlan"); 2935 } 2936 2937 if (g_str_equal(nd->model, "spapr-vlan") || 2938 g_str_equal(nd->model, "ibmveth")) { 2939 spapr_vlan_create(spapr->vio_bus, nd); 2940 } else { 2941 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2942 } 2943 } 2944 2945 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2946 spapr_vscsi_create(spapr->vio_bus); 2947 } 2948 2949 /* Graphics */ 2950 if (spapr_vga_init(phb->bus, &error_fatal)) { 2951 spapr->has_graphics = true; 2952 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2953 } 2954 2955 if (machine->usb) { 2956 if (smc->use_ohci_by_default) { 2957 pci_create_simple(phb->bus, -1, "pci-ohci"); 2958 } else { 2959 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2960 } 2961 2962 if (spapr->has_graphics) { 2963 USBBus *usb_bus = usb_bus_find(-1); 2964 2965 usb_create_simple(usb_bus, "usb-kbd"); 2966 usb_create_simple(usb_bus, "usb-mouse"); 2967 } 2968 } 2969 2970 if (kernel_filename) { 2971 uint64_t lowaddr = 0; 2972 2973 spapr->kernel_size = load_elf(kernel_filename, NULL, 2974 translate_kernel_address, spapr, 2975 NULL, &lowaddr, NULL, NULL, 1, 2976 PPC_ELF_MACHINE, 0, 0); 2977 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2978 spapr->kernel_size = load_elf(kernel_filename, NULL, 2979 translate_kernel_address, spapr, NULL, 2980 &lowaddr, NULL, NULL, 0, 2981 PPC_ELF_MACHINE, 2982 0, 0); 2983 spapr->kernel_le = spapr->kernel_size > 0; 2984 } 2985 if (spapr->kernel_size < 0) { 2986 error_report("error loading %s: %s", kernel_filename, 2987 load_elf_strerror(spapr->kernel_size)); 2988 exit(1); 2989 } 2990 2991 /* load initrd */ 2992 if (initrd_filename) { 2993 /* Try to locate the initrd in the gap between the kernel 2994 * and the firmware. Add a bit of space just in case 2995 */ 2996 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 2997 + 0x1ffff) & ~0xffff; 2998 spapr->initrd_size = load_image_targphys(initrd_filename, 2999 spapr->initrd_base, 3000 load_limit 3001 - spapr->initrd_base); 3002 if (spapr->initrd_size < 0) { 3003 error_report("could not load initial ram disk '%s'", 3004 initrd_filename); 3005 exit(1); 3006 } 3007 } 3008 } 3009 3010 if (bios_name == NULL) { 3011 bios_name = FW_FILE_NAME; 3012 } 3013 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 3014 if (!filename) { 3015 error_report("Could not find LPAR firmware '%s'", bios_name); 3016 exit(1); 3017 } 3018 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 3019 if (fw_size <= 0) { 3020 error_report("Could not load LPAR firmware '%s'", filename); 3021 exit(1); 3022 } 3023 g_free(filename); 3024 3025 /* FIXME: Should register things through the MachineState's qdev 3026 * interface, this is a legacy from the sPAPREnvironment structure 3027 * which predated MachineState but had a similar function */ 3028 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3029 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3030 &savevm_htab_handlers, spapr); 3031 3032 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 3033 3034 qemu_register_boot_set(spapr_boot_set, spapr); 3035 3036 /* 3037 * Nothing needs to be done to resume a suspended guest because 3038 * suspending does not change the machine state, so no need for 3039 * a ->wakeup method. 3040 */ 3041 qemu_register_wakeup_support(); 3042 3043 if (kvm_enabled()) { 3044 /* to stop and start vmclock */ 3045 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3046 &spapr->tb); 3047 3048 kvmppc_spapr_enable_inkernel_multitce(); 3049 } 3050 3051 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3052 } 3053 3054 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3055 { 3056 if (!vm_type) { 3057 return 0; 3058 } 3059 3060 if (!strcmp(vm_type, "HV")) { 3061 return 1; 3062 } 3063 3064 if (!strcmp(vm_type, "PR")) { 3065 return 2; 3066 } 3067 3068 error_report("Unknown kvm-type specified '%s'", vm_type); 3069 exit(1); 3070 } 3071 3072 /* 3073 * Implementation of an interface to adjust firmware path 3074 * for the bootindex property handling. 3075 */ 3076 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3077 DeviceState *dev) 3078 { 3079 #define CAST(type, obj, name) \ 3080 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3081 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3082 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3083 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3084 3085 if (d) { 3086 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3087 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3088 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3089 3090 if (spapr) { 3091 /* 3092 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3093 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3094 * 0x8000 | (target << 8) | (bus << 5) | lun 3095 * (see the "Logical unit addressing format" table in SAM5) 3096 */ 3097 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3098 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3099 (uint64_t)id << 48); 3100 } else if (virtio) { 3101 /* 3102 * We use SRP luns of the form 01000000 | (target << 8) | lun 3103 * in the top 32 bits of the 64-bit LUN 3104 * Note: the quote above is from SLOF and it is wrong, 3105 * the actual binding is: 3106 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3107 */ 3108 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3109 if (d->lun >= 256) { 3110 /* Use the LUN "flat space addressing method" */ 3111 id |= 0x4000; 3112 } 3113 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3114 (uint64_t)id << 32); 3115 } else if (usb) { 3116 /* 3117 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3118 * in the top 32 bits of the 64-bit LUN 3119 */ 3120 unsigned usb_port = atoi(usb->port->path); 3121 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3122 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3123 (uint64_t)id << 32); 3124 } 3125 } 3126 3127 /* 3128 * SLOF probes the USB devices, and if it recognizes that the device is a 3129 * storage device, it changes its name to "storage" instead of "usb-host", 3130 * and additionally adds a child node for the SCSI LUN, so the correct 3131 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3132 */ 3133 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3134 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3135 if (usb_host_dev_is_scsi_storage(usbdev)) { 3136 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3137 } 3138 } 3139 3140 if (phb) { 3141 /* Replace "pci" with "pci@800000020000000" */ 3142 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3143 } 3144 3145 if (vsc) { 3146 /* Same logic as virtio above */ 3147 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3148 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3149 } 3150 3151 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3152 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3153 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3154 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3155 } 3156 3157 return NULL; 3158 } 3159 3160 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3161 { 3162 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3163 3164 return g_strdup(spapr->kvm_type); 3165 } 3166 3167 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3168 { 3169 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3170 3171 g_free(spapr->kvm_type); 3172 spapr->kvm_type = g_strdup(value); 3173 } 3174 3175 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3176 { 3177 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3178 3179 return spapr->use_hotplug_event_source; 3180 } 3181 3182 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3183 Error **errp) 3184 { 3185 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3186 3187 spapr->use_hotplug_event_source = value; 3188 } 3189 3190 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3191 { 3192 return true; 3193 } 3194 3195 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3196 { 3197 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3198 3199 switch (spapr->resize_hpt) { 3200 case SPAPR_RESIZE_HPT_DEFAULT: 3201 return g_strdup("default"); 3202 case SPAPR_RESIZE_HPT_DISABLED: 3203 return g_strdup("disabled"); 3204 case SPAPR_RESIZE_HPT_ENABLED: 3205 return g_strdup("enabled"); 3206 case SPAPR_RESIZE_HPT_REQUIRED: 3207 return g_strdup("required"); 3208 } 3209 g_assert_not_reached(); 3210 } 3211 3212 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3213 { 3214 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3215 3216 if (strcmp(value, "default") == 0) { 3217 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3218 } else if (strcmp(value, "disabled") == 0) { 3219 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3220 } else if (strcmp(value, "enabled") == 0) { 3221 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3222 } else if (strcmp(value, "required") == 0) { 3223 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3224 } else { 3225 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3226 } 3227 } 3228 3229 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3230 { 3231 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3232 3233 if (spapr->irq == &spapr_irq_xics_legacy) { 3234 return g_strdup("legacy"); 3235 } else if (spapr->irq == &spapr_irq_xics) { 3236 return g_strdup("xics"); 3237 } else if (spapr->irq == &spapr_irq_xive) { 3238 return g_strdup("xive"); 3239 } else if (spapr->irq == &spapr_irq_dual) { 3240 return g_strdup("dual"); 3241 } 3242 g_assert_not_reached(); 3243 } 3244 3245 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3246 { 3247 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3248 3249 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3250 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3251 return; 3252 } 3253 3254 /* The legacy IRQ backend can not be set */ 3255 if (strcmp(value, "xics") == 0) { 3256 spapr->irq = &spapr_irq_xics; 3257 } else if (strcmp(value, "xive") == 0) { 3258 spapr->irq = &spapr_irq_xive; 3259 } else if (strcmp(value, "dual") == 0) { 3260 spapr->irq = &spapr_irq_dual; 3261 } else { 3262 error_setg(errp, "Bad value for \"ic-mode\" property"); 3263 } 3264 } 3265 3266 static char *spapr_get_host_model(Object *obj, Error **errp) 3267 { 3268 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3269 3270 return g_strdup(spapr->host_model); 3271 } 3272 3273 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3274 { 3275 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3276 3277 g_free(spapr->host_model); 3278 spapr->host_model = g_strdup(value); 3279 } 3280 3281 static char *spapr_get_host_serial(Object *obj, Error **errp) 3282 { 3283 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3284 3285 return g_strdup(spapr->host_serial); 3286 } 3287 3288 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3289 { 3290 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3291 3292 g_free(spapr->host_serial); 3293 spapr->host_serial = g_strdup(value); 3294 } 3295 3296 static void spapr_instance_init(Object *obj) 3297 { 3298 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3299 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3300 3301 spapr->htab_fd = -1; 3302 spapr->use_hotplug_event_source = true; 3303 object_property_add_str(obj, "kvm-type", 3304 spapr_get_kvm_type, spapr_set_kvm_type); 3305 object_property_set_description(obj, "kvm-type", 3306 "Specifies the KVM virtualization mode (HV, PR)"); 3307 object_property_add_bool(obj, "modern-hotplug-events", 3308 spapr_get_modern_hotplug_events, 3309 spapr_set_modern_hotplug_events); 3310 object_property_set_description(obj, "modern-hotplug-events", 3311 "Use dedicated hotplug event mechanism in" 3312 " place of standard EPOW events when possible" 3313 " (required for memory hot-unplug support)"); 3314 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3315 "Maximum permitted CPU compatibility mode"); 3316 3317 object_property_add_str(obj, "resize-hpt", 3318 spapr_get_resize_hpt, spapr_set_resize_hpt); 3319 object_property_set_description(obj, "resize-hpt", 3320 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3321 object_property_add_uint32_ptr(obj, "vsmt", 3322 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3323 object_property_set_description(obj, "vsmt", 3324 "Virtual SMT: KVM behaves as if this were" 3325 " the host's SMT mode"); 3326 3327 object_property_add_bool(obj, "vfio-no-msix-emulation", 3328 spapr_get_msix_emulation, NULL); 3329 3330 object_property_add_uint64_ptr(obj, "kernel-addr", 3331 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3332 object_property_set_description(obj, "kernel-addr", 3333 stringify(KERNEL_LOAD_ADDR) 3334 " for -kernel is the default"); 3335 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3336 /* The machine class defines the default interrupt controller mode */ 3337 spapr->irq = smc->irq; 3338 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3339 spapr_set_ic_mode); 3340 object_property_set_description(obj, "ic-mode", 3341 "Specifies the interrupt controller mode (xics, xive, dual)"); 3342 3343 object_property_add_str(obj, "host-model", 3344 spapr_get_host_model, spapr_set_host_model); 3345 object_property_set_description(obj, "host-model", 3346 "Host model to advertise in guest device tree"); 3347 object_property_add_str(obj, "host-serial", 3348 spapr_get_host_serial, spapr_set_host_serial); 3349 object_property_set_description(obj, "host-serial", 3350 "Host serial number to advertise in guest device tree"); 3351 } 3352 3353 static void spapr_machine_finalizefn(Object *obj) 3354 { 3355 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3356 3357 g_free(spapr->kvm_type); 3358 } 3359 3360 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3361 { 3362 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3363 PowerPCCPU *cpu = POWERPC_CPU(cs); 3364 CPUPPCState *env = &cpu->env; 3365 3366 cpu_synchronize_state(cs); 3367 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3368 if (spapr->fwnmi_system_reset_addr != -1) { 3369 uint64_t rtas_addr, addr; 3370 3371 /* get rtas addr from fdt */ 3372 rtas_addr = spapr_get_rtas_addr(); 3373 if (!rtas_addr) { 3374 qemu_system_guest_panicked(NULL); 3375 return; 3376 } 3377 3378 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3379 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3380 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3381 env->gpr[3] = addr; 3382 } 3383 ppc_cpu_do_system_reset(cs); 3384 if (spapr->fwnmi_system_reset_addr != -1) { 3385 env->nip = spapr->fwnmi_system_reset_addr; 3386 } 3387 } 3388 3389 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3390 { 3391 CPUState *cs; 3392 3393 CPU_FOREACH(cs) { 3394 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3395 } 3396 } 3397 3398 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3399 void *fdt, int *fdt_start_offset, Error **errp) 3400 { 3401 uint64_t addr; 3402 uint32_t node; 3403 3404 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3405 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3406 &error_abort); 3407 *fdt_start_offset = spapr_dt_memory_node(fdt, node, addr, 3408 SPAPR_MEMORY_BLOCK_SIZE); 3409 return 0; 3410 } 3411 3412 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3413 bool dedicated_hp_event_source, Error **errp) 3414 { 3415 SpaprDrc *drc; 3416 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3417 int i; 3418 uint64_t addr = addr_start; 3419 bool hotplugged = spapr_drc_hotplugged(dev); 3420 Error *local_err = NULL; 3421 3422 for (i = 0; i < nr_lmbs; i++) { 3423 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3424 addr / SPAPR_MEMORY_BLOCK_SIZE); 3425 g_assert(drc); 3426 3427 spapr_drc_attach(drc, dev, &local_err); 3428 if (local_err) { 3429 while (addr > addr_start) { 3430 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3431 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3432 addr / SPAPR_MEMORY_BLOCK_SIZE); 3433 spapr_drc_detach(drc); 3434 } 3435 error_propagate(errp, local_err); 3436 return; 3437 } 3438 if (!hotplugged) { 3439 spapr_drc_reset(drc); 3440 } 3441 addr += SPAPR_MEMORY_BLOCK_SIZE; 3442 } 3443 /* send hotplug notification to the 3444 * guest only in case of hotplugged memory 3445 */ 3446 if (hotplugged) { 3447 if (dedicated_hp_event_source) { 3448 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3449 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3450 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3451 nr_lmbs, 3452 spapr_drc_index(drc)); 3453 } else { 3454 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3455 nr_lmbs); 3456 } 3457 } 3458 } 3459 3460 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3461 Error **errp) 3462 { 3463 Error *local_err = NULL; 3464 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3465 PCDIMMDevice *dimm = PC_DIMM(dev); 3466 uint64_t size, addr, slot; 3467 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3468 3469 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3470 3471 pc_dimm_plug(dimm, MACHINE(ms), &local_err); 3472 if (local_err) { 3473 goto out; 3474 } 3475 3476 if (!is_nvdimm) { 3477 addr = object_property_get_uint(OBJECT(dimm), 3478 PC_DIMM_ADDR_PROP, &local_err); 3479 if (local_err) { 3480 goto out_unplug; 3481 } 3482 spapr_add_lmbs(dev, addr, size, 3483 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3484 &local_err); 3485 } else { 3486 slot = object_property_get_uint(OBJECT(dimm), 3487 PC_DIMM_SLOT_PROP, &local_err); 3488 if (local_err) { 3489 goto out_unplug; 3490 } 3491 spapr_add_nvdimm(dev, slot, &local_err); 3492 } 3493 3494 if (local_err) { 3495 goto out_unplug; 3496 } 3497 3498 return; 3499 3500 out_unplug: 3501 pc_dimm_unplug(dimm, MACHINE(ms)); 3502 out: 3503 error_propagate(errp, local_err); 3504 } 3505 3506 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3507 Error **errp) 3508 { 3509 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3510 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3511 const MachineClass *mc = MACHINE_CLASS(smc); 3512 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3513 PCDIMMDevice *dimm = PC_DIMM(dev); 3514 Error *local_err = NULL; 3515 uint64_t size; 3516 Object *memdev; 3517 hwaddr pagesize; 3518 3519 if (!smc->dr_lmb_enabled) { 3520 error_setg(errp, "Memory hotplug not supported for this machine"); 3521 return; 3522 } 3523 3524 if (is_nvdimm && !mc->nvdimm_supported) { 3525 error_setg(errp, "NVDIMM hotplug not supported for this machine"); 3526 return; 3527 } 3528 3529 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3530 if (local_err) { 3531 error_propagate(errp, local_err); 3532 return; 3533 } 3534 3535 if (!is_nvdimm && size % SPAPR_MEMORY_BLOCK_SIZE) { 3536 error_setg(errp, "Hotplugged memory size must be a multiple of " 3537 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3538 return; 3539 } else if (is_nvdimm) { 3540 spapr_nvdimm_validate_opts(NVDIMM(dev), size, &local_err); 3541 if (local_err) { 3542 error_propagate(errp, local_err); 3543 return; 3544 } 3545 } 3546 3547 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3548 &error_abort); 3549 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3550 spapr_check_pagesize(spapr, pagesize, &local_err); 3551 if (local_err) { 3552 error_propagate(errp, local_err); 3553 return; 3554 } 3555 3556 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3557 } 3558 3559 struct SpaprDimmState { 3560 PCDIMMDevice *dimm; 3561 uint32_t nr_lmbs; 3562 QTAILQ_ENTRY(SpaprDimmState) next; 3563 }; 3564 3565 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3566 PCDIMMDevice *dimm) 3567 { 3568 SpaprDimmState *dimm_state = NULL; 3569 3570 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3571 if (dimm_state->dimm == dimm) { 3572 break; 3573 } 3574 } 3575 return dimm_state; 3576 } 3577 3578 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3579 uint32_t nr_lmbs, 3580 PCDIMMDevice *dimm) 3581 { 3582 SpaprDimmState *ds = NULL; 3583 3584 /* 3585 * If this request is for a DIMM whose removal had failed earlier 3586 * (due to guest's refusal to remove the LMBs), we would have this 3587 * dimm already in the pending_dimm_unplugs list. In that 3588 * case don't add again. 3589 */ 3590 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3591 if (!ds) { 3592 ds = g_malloc0(sizeof(SpaprDimmState)); 3593 ds->nr_lmbs = nr_lmbs; 3594 ds->dimm = dimm; 3595 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3596 } 3597 return ds; 3598 } 3599 3600 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3601 SpaprDimmState *dimm_state) 3602 { 3603 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3604 g_free(dimm_state); 3605 } 3606 3607 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3608 PCDIMMDevice *dimm) 3609 { 3610 SpaprDrc *drc; 3611 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3612 &error_abort); 3613 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3614 uint32_t avail_lmbs = 0; 3615 uint64_t addr_start, addr; 3616 int i; 3617 3618 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3619 &error_abort); 3620 3621 addr = addr_start; 3622 for (i = 0; i < nr_lmbs; i++) { 3623 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3624 addr / SPAPR_MEMORY_BLOCK_SIZE); 3625 g_assert(drc); 3626 if (drc->dev) { 3627 avail_lmbs++; 3628 } 3629 addr += SPAPR_MEMORY_BLOCK_SIZE; 3630 } 3631 3632 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3633 } 3634 3635 /* Callback to be called during DRC release. */ 3636 void spapr_lmb_release(DeviceState *dev) 3637 { 3638 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3639 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3640 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3641 3642 /* This information will get lost if a migration occurs 3643 * during the unplug process. In this case recover it. */ 3644 if (ds == NULL) { 3645 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3646 g_assert(ds); 3647 /* The DRC being examined by the caller at least must be counted */ 3648 g_assert(ds->nr_lmbs); 3649 } 3650 3651 if (--ds->nr_lmbs) { 3652 return; 3653 } 3654 3655 /* 3656 * Now that all the LMBs have been removed by the guest, call the 3657 * unplug handler chain. This can never fail. 3658 */ 3659 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3660 object_unparent(OBJECT(dev)); 3661 } 3662 3663 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3664 { 3665 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3666 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3667 3668 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3669 qdev_unrealize(dev); 3670 spapr_pending_dimm_unplugs_remove(spapr, ds); 3671 } 3672 3673 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3674 DeviceState *dev, Error **errp) 3675 { 3676 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3677 Error *local_err = NULL; 3678 PCDIMMDevice *dimm = PC_DIMM(dev); 3679 uint32_t nr_lmbs; 3680 uint64_t size, addr_start, addr; 3681 int i; 3682 SpaprDrc *drc; 3683 3684 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3685 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3686 return; 3687 } 3688 3689 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3690 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3691 3692 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3693 &local_err); 3694 if (local_err) { 3695 error_propagate(errp, local_err); 3696 return; 3697 } 3698 3699 /* 3700 * An existing pending dimm state for this DIMM means that there is an 3701 * unplug operation in progress, waiting for the spapr_lmb_release 3702 * callback to complete the job (BQL can't cover that far). In this case, 3703 * bail out to avoid detaching DRCs that were already released. 3704 */ 3705 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3706 error_setg(errp, "Memory unplug already in progress for device %s", 3707 dev->id); 3708 return; 3709 } 3710 3711 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3712 3713 addr = addr_start; 3714 for (i = 0; i < nr_lmbs; i++) { 3715 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3716 addr / SPAPR_MEMORY_BLOCK_SIZE); 3717 g_assert(drc); 3718 3719 spapr_drc_detach(drc); 3720 addr += SPAPR_MEMORY_BLOCK_SIZE; 3721 } 3722 3723 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3724 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3725 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3726 nr_lmbs, spapr_drc_index(drc)); 3727 } 3728 3729 /* Callback to be called during DRC release. */ 3730 void spapr_core_release(DeviceState *dev) 3731 { 3732 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3733 3734 /* Call the unplug handler chain. This can never fail. */ 3735 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3736 object_unparent(OBJECT(dev)); 3737 } 3738 3739 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3740 { 3741 MachineState *ms = MACHINE(hotplug_dev); 3742 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3743 CPUCore *cc = CPU_CORE(dev); 3744 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3745 3746 if (smc->pre_2_10_has_unused_icps) { 3747 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3748 int i; 3749 3750 for (i = 0; i < cc->nr_threads; i++) { 3751 CPUState *cs = CPU(sc->threads[i]); 3752 3753 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3754 } 3755 } 3756 3757 assert(core_slot); 3758 core_slot->cpu = NULL; 3759 qdev_unrealize(dev); 3760 } 3761 3762 static 3763 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3764 Error **errp) 3765 { 3766 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3767 int index; 3768 SpaprDrc *drc; 3769 CPUCore *cc = CPU_CORE(dev); 3770 3771 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3772 error_setg(errp, "Unable to find CPU core with core-id: %d", 3773 cc->core_id); 3774 return; 3775 } 3776 if (index == 0) { 3777 error_setg(errp, "Boot CPU core may not be unplugged"); 3778 return; 3779 } 3780 3781 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3782 spapr_vcpu_id(spapr, cc->core_id)); 3783 g_assert(drc); 3784 3785 if (!spapr_drc_unplug_requested(drc)) { 3786 spapr_drc_detach(drc); 3787 spapr_hotplug_req_remove_by_index(drc); 3788 } 3789 } 3790 3791 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3792 void *fdt, int *fdt_start_offset, Error **errp) 3793 { 3794 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3795 CPUState *cs = CPU(core->threads[0]); 3796 PowerPCCPU *cpu = POWERPC_CPU(cs); 3797 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3798 int id = spapr_get_vcpu_id(cpu); 3799 char *nodename; 3800 int offset; 3801 3802 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3803 offset = fdt_add_subnode(fdt, 0, nodename); 3804 g_free(nodename); 3805 3806 spapr_dt_cpu(cs, fdt, offset, spapr); 3807 3808 *fdt_start_offset = offset; 3809 return 0; 3810 } 3811 3812 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3813 Error **errp) 3814 { 3815 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3816 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3817 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3818 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3819 CPUCore *cc = CPU_CORE(dev); 3820 CPUState *cs; 3821 SpaprDrc *drc; 3822 Error *local_err = NULL; 3823 CPUArchId *core_slot; 3824 int index; 3825 bool hotplugged = spapr_drc_hotplugged(dev); 3826 int i; 3827 3828 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3829 if (!core_slot) { 3830 error_setg(errp, "Unable to find CPU core with core-id: %d", 3831 cc->core_id); 3832 return; 3833 } 3834 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3835 spapr_vcpu_id(spapr, cc->core_id)); 3836 3837 g_assert(drc || !mc->has_hotpluggable_cpus); 3838 3839 if (drc) { 3840 spapr_drc_attach(drc, dev, &local_err); 3841 if (local_err) { 3842 error_propagate(errp, local_err); 3843 return; 3844 } 3845 3846 if (hotplugged) { 3847 /* 3848 * Send hotplug notification interrupt to the guest only 3849 * in case of hotplugged CPUs. 3850 */ 3851 spapr_hotplug_req_add_by_index(drc); 3852 } else { 3853 spapr_drc_reset(drc); 3854 } 3855 } 3856 3857 core_slot->cpu = OBJECT(dev); 3858 3859 if (smc->pre_2_10_has_unused_icps) { 3860 for (i = 0; i < cc->nr_threads; i++) { 3861 cs = CPU(core->threads[i]); 3862 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3863 } 3864 } 3865 3866 /* 3867 * Set compatibility mode to match the boot CPU, which was either set 3868 * by the machine reset code or by CAS. 3869 */ 3870 if (hotplugged) { 3871 for (i = 0; i < cc->nr_threads; i++) { 3872 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3873 &local_err); 3874 if (local_err) { 3875 error_propagate(errp, local_err); 3876 return; 3877 } 3878 } 3879 } 3880 } 3881 3882 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3883 Error **errp) 3884 { 3885 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3886 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3887 CPUCore *cc = CPU_CORE(dev); 3888 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3889 const char *type = object_get_typename(OBJECT(dev)); 3890 CPUArchId *core_slot; 3891 int index; 3892 unsigned int smp_threads = machine->smp.threads; 3893 3894 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3895 error_setg(errp, "CPU hotplug not supported for this machine"); 3896 return; 3897 } 3898 3899 if (strcmp(base_core_type, type)) { 3900 error_setg(errp, "CPU core type should be %s", base_core_type); 3901 return; 3902 } 3903 3904 if (cc->core_id % smp_threads) { 3905 error_setg(errp, "invalid core id %d", cc->core_id); 3906 return; 3907 } 3908 3909 /* 3910 * In general we should have homogeneous threads-per-core, but old 3911 * (pre hotplug support) machine types allow the last core to have 3912 * reduced threads as a compatibility hack for when we allowed 3913 * total vcpus not a multiple of threads-per-core. 3914 */ 3915 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3916 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 3917 smp_threads); 3918 return; 3919 } 3920 3921 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3922 if (!core_slot) { 3923 error_setg(errp, "core id %d out of range", cc->core_id); 3924 return; 3925 } 3926 3927 if (core_slot->cpu) { 3928 error_setg(errp, "core %d already populated", cc->core_id); 3929 return; 3930 } 3931 3932 numa_cpu_pre_plug(core_slot, dev, errp); 3933 } 3934 3935 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3936 void *fdt, int *fdt_start_offset, Error **errp) 3937 { 3938 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3939 int intc_phandle; 3940 3941 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3942 if (intc_phandle <= 0) { 3943 return -1; 3944 } 3945 3946 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3947 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3948 return -1; 3949 } 3950 3951 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3952 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3953 3954 return 0; 3955 } 3956 3957 static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3958 Error **errp) 3959 { 3960 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3961 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3962 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3963 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3964 3965 if (dev->hotplugged && !smc->dr_phb_enabled) { 3966 error_setg(errp, "PHB hotplug not supported for this machine"); 3967 return; 3968 } 3969 3970 if (sphb->index == (uint32_t)-1) { 3971 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3972 return; 3973 } 3974 3975 /* 3976 * This will check that sphb->index doesn't exceed the maximum number of 3977 * PHBs for the current machine type. 3978 */ 3979 smc->phb_placement(spapr, sphb->index, 3980 &sphb->buid, &sphb->io_win_addr, 3981 &sphb->mem_win_addr, &sphb->mem64_win_addr, 3982 windows_supported, sphb->dma_liobn, 3983 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 3984 errp); 3985 } 3986 3987 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3988 Error **errp) 3989 { 3990 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3991 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3992 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3993 SpaprDrc *drc; 3994 bool hotplugged = spapr_drc_hotplugged(dev); 3995 Error *local_err = NULL; 3996 3997 if (!smc->dr_phb_enabled) { 3998 return; 3999 } 4000 4001 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4002 /* hotplug hooks should check it's enabled before getting this far */ 4003 assert(drc); 4004 4005 spapr_drc_attach(drc, dev, &local_err); 4006 if (local_err) { 4007 error_propagate(errp, local_err); 4008 return; 4009 } 4010 4011 if (hotplugged) { 4012 spapr_hotplug_req_add_by_index(drc); 4013 } else { 4014 spapr_drc_reset(drc); 4015 } 4016 } 4017 4018 void spapr_phb_release(DeviceState *dev) 4019 { 4020 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4021 4022 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4023 object_unparent(OBJECT(dev)); 4024 } 4025 4026 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4027 { 4028 qdev_unrealize(dev); 4029 } 4030 4031 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4032 DeviceState *dev, Error **errp) 4033 { 4034 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4035 SpaprDrc *drc; 4036 4037 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4038 assert(drc); 4039 4040 if (!spapr_drc_unplug_requested(drc)) { 4041 spapr_drc_detach(drc); 4042 spapr_hotplug_req_remove_by_index(drc); 4043 } 4044 } 4045 4046 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4047 Error **errp) 4048 { 4049 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4050 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4051 4052 if (spapr->tpm_proxy != NULL) { 4053 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4054 return; 4055 } 4056 4057 spapr->tpm_proxy = tpm_proxy; 4058 } 4059 4060 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4061 { 4062 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4063 4064 qdev_unrealize(dev); 4065 object_unparent(OBJECT(dev)); 4066 spapr->tpm_proxy = NULL; 4067 } 4068 4069 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4070 DeviceState *dev, Error **errp) 4071 { 4072 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4073 spapr_memory_plug(hotplug_dev, dev, errp); 4074 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4075 spapr_core_plug(hotplug_dev, dev, errp); 4076 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4077 spapr_phb_plug(hotplug_dev, dev, errp); 4078 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4079 spapr_tpm_proxy_plug(hotplug_dev, dev, errp); 4080 } 4081 } 4082 4083 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4084 DeviceState *dev, Error **errp) 4085 { 4086 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4087 spapr_memory_unplug(hotplug_dev, dev); 4088 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4089 spapr_core_unplug(hotplug_dev, dev); 4090 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4091 spapr_phb_unplug(hotplug_dev, dev); 4092 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4093 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4094 } 4095 } 4096 4097 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4098 DeviceState *dev, Error **errp) 4099 { 4100 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4101 MachineClass *mc = MACHINE_GET_CLASS(sms); 4102 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4103 4104 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4105 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 4106 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4107 } else { 4108 /* NOTE: this means there is a window after guest reset, prior to 4109 * CAS negotiation, where unplug requests will fail due to the 4110 * capability not being detected yet. This is a bit different than 4111 * the case with PCI unplug, where the events will be queued and 4112 * eventually handled by the guest after boot 4113 */ 4114 error_setg(errp, "Memory hot unplug not supported for this guest"); 4115 } 4116 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4117 if (!mc->has_hotpluggable_cpus) { 4118 error_setg(errp, "CPU hot unplug not supported on this machine"); 4119 return; 4120 } 4121 spapr_core_unplug_request(hotplug_dev, dev, errp); 4122 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4123 if (!smc->dr_phb_enabled) { 4124 error_setg(errp, "PHB hot unplug not supported on this machine"); 4125 return; 4126 } 4127 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4128 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4129 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4130 } 4131 } 4132 4133 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4134 DeviceState *dev, Error **errp) 4135 { 4136 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4137 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4138 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4139 spapr_core_pre_plug(hotplug_dev, dev, errp); 4140 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4141 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4142 } 4143 } 4144 4145 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4146 DeviceState *dev) 4147 { 4148 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4149 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4150 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4151 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4152 return HOTPLUG_HANDLER(machine); 4153 } 4154 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4155 PCIDevice *pcidev = PCI_DEVICE(dev); 4156 PCIBus *root = pci_device_root_bus(pcidev); 4157 SpaprPhbState *phb = 4158 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4159 TYPE_SPAPR_PCI_HOST_BRIDGE); 4160 4161 if (phb) { 4162 return HOTPLUG_HANDLER(phb); 4163 } 4164 } 4165 return NULL; 4166 } 4167 4168 static CpuInstanceProperties 4169 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4170 { 4171 CPUArchId *core_slot; 4172 MachineClass *mc = MACHINE_GET_CLASS(machine); 4173 4174 /* make sure possible_cpu are intialized */ 4175 mc->possible_cpu_arch_ids(machine); 4176 /* get CPU core slot containing thread that matches cpu_index */ 4177 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4178 assert(core_slot); 4179 return core_slot->props; 4180 } 4181 4182 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4183 { 4184 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4185 } 4186 4187 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4188 { 4189 int i; 4190 unsigned int smp_threads = machine->smp.threads; 4191 unsigned int smp_cpus = machine->smp.cpus; 4192 const char *core_type; 4193 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4194 MachineClass *mc = MACHINE_GET_CLASS(machine); 4195 4196 if (!mc->has_hotpluggable_cpus) { 4197 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4198 } 4199 if (machine->possible_cpus) { 4200 assert(machine->possible_cpus->len == spapr_max_cores); 4201 return machine->possible_cpus; 4202 } 4203 4204 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4205 if (!core_type) { 4206 error_report("Unable to find sPAPR CPU Core definition"); 4207 exit(1); 4208 } 4209 4210 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4211 sizeof(CPUArchId) * spapr_max_cores); 4212 machine->possible_cpus->len = spapr_max_cores; 4213 for (i = 0; i < machine->possible_cpus->len; i++) { 4214 int core_id = i * smp_threads; 4215 4216 machine->possible_cpus->cpus[i].type = core_type; 4217 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4218 machine->possible_cpus->cpus[i].arch_id = core_id; 4219 machine->possible_cpus->cpus[i].props.has_core_id = true; 4220 machine->possible_cpus->cpus[i].props.core_id = core_id; 4221 } 4222 return machine->possible_cpus; 4223 } 4224 4225 static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4226 uint64_t *buid, hwaddr *pio, 4227 hwaddr *mmio32, hwaddr *mmio64, 4228 unsigned n_dma, uint32_t *liobns, 4229 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4230 { 4231 /* 4232 * New-style PHB window placement. 4233 * 4234 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4235 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4236 * windows. 4237 * 4238 * Some guest kernels can't work with MMIO windows above 1<<46 4239 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4240 * 4241 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4242 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4243 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4244 * 1TiB 64-bit MMIO windows for each PHB. 4245 */ 4246 const uint64_t base_buid = 0x800000020000000ULL; 4247 int i; 4248 4249 /* Sanity check natural alignments */ 4250 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4251 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4252 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4253 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4254 /* Sanity check bounds */ 4255 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4256 SPAPR_PCI_MEM32_WIN_SIZE); 4257 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4258 SPAPR_PCI_MEM64_WIN_SIZE); 4259 4260 if (index >= SPAPR_MAX_PHBS) { 4261 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4262 SPAPR_MAX_PHBS - 1); 4263 return; 4264 } 4265 4266 *buid = base_buid + index; 4267 for (i = 0; i < n_dma; ++i) { 4268 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4269 } 4270 4271 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4272 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4273 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4274 4275 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4276 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4277 } 4278 4279 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4280 { 4281 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4282 4283 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4284 } 4285 4286 static void spapr_ics_resend(XICSFabric *dev) 4287 { 4288 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4289 4290 ics_resend(spapr->ics); 4291 } 4292 4293 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4294 { 4295 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4296 4297 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4298 } 4299 4300 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4301 Monitor *mon) 4302 { 4303 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4304 4305 spapr_irq_print_info(spapr, mon); 4306 monitor_printf(mon, "irqchip: %s\n", 4307 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4308 } 4309 4310 /* 4311 * This is a XIVE only operation 4312 */ 4313 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4314 uint8_t nvt_blk, uint32_t nvt_idx, 4315 bool cam_ignore, uint8_t priority, 4316 uint32_t logic_serv, XiveTCTXMatch *match) 4317 { 4318 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4319 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4320 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4321 int count; 4322 4323 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4324 priority, logic_serv, match); 4325 if (count < 0) { 4326 return count; 4327 } 4328 4329 /* 4330 * When we implement the save and restore of the thread interrupt 4331 * contexts in the enter/exit CPU handlers of the machine and the 4332 * escalations in QEMU, we should be able to handle non dispatched 4333 * vCPUs. 4334 * 4335 * Until this is done, the sPAPR machine should find at least one 4336 * matching context always. 4337 */ 4338 if (count == 0) { 4339 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4340 nvt_blk, nvt_idx); 4341 } 4342 4343 return count; 4344 } 4345 4346 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4347 { 4348 return cpu->vcpu_id; 4349 } 4350 4351 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4352 { 4353 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4354 MachineState *ms = MACHINE(spapr); 4355 int vcpu_id; 4356 4357 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4358 4359 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4360 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4361 error_append_hint(errp, "Adjust the number of cpus to %d " 4362 "or try to raise the number of threads per core\n", 4363 vcpu_id * ms->smp.threads / spapr->vsmt); 4364 return; 4365 } 4366 4367 cpu->vcpu_id = vcpu_id; 4368 } 4369 4370 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4371 { 4372 CPUState *cs; 4373 4374 CPU_FOREACH(cs) { 4375 PowerPCCPU *cpu = POWERPC_CPU(cs); 4376 4377 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4378 return cpu; 4379 } 4380 } 4381 4382 return NULL; 4383 } 4384 4385 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4386 { 4387 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4388 4389 /* These are only called by TCG, KVM maintains dispatch state */ 4390 4391 spapr_cpu->prod = false; 4392 if (spapr_cpu->vpa_addr) { 4393 CPUState *cs = CPU(cpu); 4394 uint32_t dispatch; 4395 4396 dispatch = ldl_be_phys(cs->as, 4397 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4398 dispatch++; 4399 if ((dispatch & 1) != 0) { 4400 qemu_log_mask(LOG_GUEST_ERROR, 4401 "VPA: incorrect dispatch counter value for " 4402 "dispatched partition %u, correcting.\n", dispatch); 4403 dispatch++; 4404 } 4405 stl_be_phys(cs->as, 4406 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4407 } 4408 } 4409 4410 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4411 { 4412 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4413 4414 if (spapr_cpu->vpa_addr) { 4415 CPUState *cs = CPU(cpu); 4416 uint32_t dispatch; 4417 4418 dispatch = ldl_be_phys(cs->as, 4419 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4420 dispatch++; 4421 if ((dispatch & 1) != 1) { 4422 qemu_log_mask(LOG_GUEST_ERROR, 4423 "VPA: incorrect dispatch counter value for " 4424 "preempted partition %u, correcting.\n", dispatch); 4425 dispatch++; 4426 } 4427 stl_be_phys(cs->as, 4428 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4429 } 4430 } 4431 4432 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4433 { 4434 MachineClass *mc = MACHINE_CLASS(oc); 4435 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4436 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4437 NMIClass *nc = NMI_CLASS(oc); 4438 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4439 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4440 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4441 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4442 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4443 4444 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4445 mc->ignore_boot_device_suffixes = true; 4446 4447 /* 4448 * We set up the default / latest behaviour here. The class_init 4449 * functions for the specific versioned machine types can override 4450 * these details for backwards compatibility 4451 */ 4452 mc->init = spapr_machine_init; 4453 mc->reset = spapr_machine_reset; 4454 mc->block_default_type = IF_SCSI; 4455 mc->max_cpus = 1024; 4456 mc->no_parallel = 1; 4457 mc->default_boot_order = ""; 4458 mc->default_ram_size = 512 * MiB; 4459 mc->default_ram_id = "ppc_spapr.ram"; 4460 mc->default_display = "std"; 4461 mc->kvm_type = spapr_kvm_type; 4462 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4463 mc->pci_allow_0_address = true; 4464 assert(!mc->get_hotplug_handler); 4465 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4466 hc->pre_plug = spapr_machine_device_pre_plug; 4467 hc->plug = spapr_machine_device_plug; 4468 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4469 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4470 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4471 hc->unplug_request = spapr_machine_device_unplug_request; 4472 hc->unplug = spapr_machine_device_unplug; 4473 4474 smc->dr_lmb_enabled = true; 4475 smc->update_dt_enabled = true; 4476 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4477 mc->has_hotpluggable_cpus = true; 4478 mc->nvdimm_supported = true; 4479 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4480 fwc->get_dev_path = spapr_get_fw_dev_path; 4481 nc->nmi_monitor_handler = spapr_nmi; 4482 smc->phb_placement = spapr_phb_placement; 4483 vhc->hypercall = emulate_spapr_hypercall; 4484 vhc->hpt_mask = spapr_hpt_mask; 4485 vhc->map_hptes = spapr_map_hptes; 4486 vhc->unmap_hptes = spapr_unmap_hptes; 4487 vhc->hpte_set_c = spapr_hpte_set_c; 4488 vhc->hpte_set_r = spapr_hpte_set_r; 4489 vhc->get_pate = spapr_get_pate; 4490 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4491 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4492 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4493 xic->ics_get = spapr_ics_get; 4494 xic->ics_resend = spapr_ics_resend; 4495 xic->icp_get = spapr_icp_get; 4496 ispc->print_info = spapr_pic_print_info; 4497 /* Force NUMA node memory size to be a multiple of 4498 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4499 * in which LMBs are represented and hot-added 4500 */ 4501 mc->numa_mem_align_shift = 28; 4502 mc->auto_enable_numa = true; 4503 4504 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4505 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4506 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4507 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4508 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4509 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4510 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4511 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4512 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4513 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4514 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4515 spapr_caps_add_properties(smc); 4516 smc->irq = &spapr_irq_dual; 4517 smc->dr_phb_enabled = true; 4518 smc->linux_pci_probe = true; 4519 smc->smp_threads_vsmt = true; 4520 smc->nr_xirqs = SPAPR_NR_XIRQS; 4521 xfc->match_nvt = spapr_match_nvt; 4522 } 4523 4524 static const TypeInfo spapr_machine_info = { 4525 .name = TYPE_SPAPR_MACHINE, 4526 .parent = TYPE_MACHINE, 4527 .abstract = true, 4528 .instance_size = sizeof(SpaprMachineState), 4529 .instance_init = spapr_instance_init, 4530 .instance_finalize = spapr_machine_finalizefn, 4531 .class_size = sizeof(SpaprMachineClass), 4532 .class_init = spapr_machine_class_init, 4533 .interfaces = (InterfaceInfo[]) { 4534 { TYPE_FW_PATH_PROVIDER }, 4535 { TYPE_NMI }, 4536 { TYPE_HOTPLUG_HANDLER }, 4537 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4538 { TYPE_XICS_FABRIC }, 4539 { TYPE_INTERRUPT_STATS_PROVIDER }, 4540 { TYPE_XIVE_FABRIC }, 4541 { } 4542 }, 4543 }; 4544 4545 static void spapr_machine_latest_class_options(MachineClass *mc) 4546 { 4547 mc->alias = "pseries"; 4548 mc->is_default = true; 4549 } 4550 4551 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4552 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4553 void *data) \ 4554 { \ 4555 MachineClass *mc = MACHINE_CLASS(oc); \ 4556 spapr_machine_##suffix##_class_options(mc); \ 4557 if (latest) { \ 4558 spapr_machine_latest_class_options(mc); \ 4559 } \ 4560 } \ 4561 static const TypeInfo spapr_machine_##suffix##_info = { \ 4562 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4563 .parent = TYPE_SPAPR_MACHINE, \ 4564 .class_init = spapr_machine_##suffix##_class_init, \ 4565 }; \ 4566 static void spapr_machine_register_##suffix(void) \ 4567 { \ 4568 type_register(&spapr_machine_##suffix##_info); \ 4569 } \ 4570 type_init(spapr_machine_register_##suffix) 4571 4572 /* 4573 * pseries-5.1 4574 */ 4575 static void spapr_machine_5_1_class_options(MachineClass *mc) 4576 { 4577 /* Defaults for the latest behaviour inherited from the base class */ 4578 } 4579 4580 DEFINE_SPAPR_MACHINE(5_1, "5.1", true); 4581 4582 /* 4583 * pseries-5.0 4584 */ 4585 static void spapr_machine_5_0_class_options(MachineClass *mc) 4586 { 4587 spapr_machine_5_1_class_options(mc); 4588 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4589 mc->numa_mem_supported = true; 4590 } 4591 4592 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4593 4594 /* 4595 * pseries-4.2 4596 */ 4597 static void spapr_machine_4_2_class_options(MachineClass *mc) 4598 { 4599 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4600 4601 spapr_machine_5_0_class_options(mc); 4602 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4603 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4604 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4605 smc->rma_limit = 16 * GiB; 4606 mc->nvdimm_supported = false; 4607 } 4608 4609 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4610 4611 /* 4612 * pseries-4.1 4613 */ 4614 static void spapr_machine_4_1_class_options(MachineClass *mc) 4615 { 4616 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4617 static GlobalProperty compat[] = { 4618 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4619 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4620 }; 4621 4622 spapr_machine_4_2_class_options(mc); 4623 smc->linux_pci_probe = false; 4624 smc->smp_threads_vsmt = false; 4625 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4626 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4627 } 4628 4629 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4630 4631 /* 4632 * pseries-4.0 4633 */ 4634 static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4635 uint64_t *buid, hwaddr *pio, 4636 hwaddr *mmio32, hwaddr *mmio64, 4637 unsigned n_dma, uint32_t *liobns, 4638 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4639 { 4640 spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns, 4641 nv2gpa, nv2atsd, errp); 4642 *nv2gpa = 0; 4643 *nv2atsd = 0; 4644 } 4645 4646 static void spapr_machine_4_0_class_options(MachineClass *mc) 4647 { 4648 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4649 4650 spapr_machine_4_1_class_options(mc); 4651 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4652 smc->phb_placement = phb_placement_4_0; 4653 smc->irq = &spapr_irq_xics; 4654 smc->pre_4_1_migration = true; 4655 } 4656 4657 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4658 4659 /* 4660 * pseries-3.1 4661 */ 4662 static void spapr_machine_3_1_class_options(MachineClass *mc) 4663 { 4664 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4665 4666 spapr_machine_4_0_class_options(mc); 4667 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4668 4669 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4670 smc->update_dt_enabled = false; 4671 smc->dr_phb_enabled = false; 4672 smc->broken_host_serial_model = true; 4673 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4674 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4675 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4676 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4677 } 4678 4679 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4680 4681 /* 4682 * pseries-3.0 4683 */ 4684 4685 static void spapr_machine_3_0_class_options(MachineClass *mc) 4686 { 4687 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4688 4689 spapr_machine_3_1_class_options(mc); 4690 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4691 4692 smc->legacy_irq_allocation = true; 4693 smc->nr_xirqs = 0x400; 4694 smc->irq = &spapr_irq_xics_legacy; 4695 } 4696 4697 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4698 4699 /* 4700 * pseries-2.12 4701 */ 4702 static void spapr_machine_2_12_class_options(MachineClass *mc) 4703 { 4704 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4705 static GlobalProperty compat[] = { 4706 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4707 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4708 }; 4709 4710 spapr_machine_3_0_class_options(mc); 4711 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4712 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4713 4714 /* We depend on kvm_enabled() to choose a default value for the 4715 * hpt-max-page-size capability. Of course we can't do it here 4716 * because this is too early and the HW accelerator isn't initialzed 4717 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4718 */ 4719 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4720 } 4721 4722 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4723 4724 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4725 { 4726 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4727 4728 spapr_machine_2_12_class_options(mc); 4729 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4730 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4731 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4732 } 4733 4734 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4735 4736 /* 4737 * pseries-2.11 4738 */ 4739 4740 static void spapr_machine_2_11_class_options(MachineClass *mc) 4741 { 4742 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4743 4744 spapr_machine_2_12_class_options(mc); 4745 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4746 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4747 } 4748 4749 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4750 4751 /* 4752 * pseries-2.10 4753 */ 4754 4755 static void spapr_machine_2_10_class_options(MachineClass *mc) 4756 { 4757 spapr_machine_2_11_class_options(mc); 4758 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4759 } 4760 4761 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4762 4763 /* 4764 * pseries-2.9 4765 */ 4766 4767 static void spapr_machine_2_9_class_options(MachineClass *mc) 4768 { 4769 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4770 static GlobalProperty compat[] = { 4771 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4772 }; 4773 4774 spapr_machine_2_10_class_options(mc); 4775 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4776 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4777 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4778 smc->pre_2_10_has_unused_icps = true; 4779 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4780 } 4781 4782 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4783 4784 /* 4785 * pseries-2.8 4786 */ 4787 4788 static void spapr_machine_2_8_class_options(MachineClass *mc) 4789 { 4790 static GlobalProperty compat[] = { 4791 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4792 }; 4793 4794 spapr_machine_2_9_class_options(mc); 4795 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4796 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4797 mc->numa_mem_align_shift = 23; 4798 } 4799 4800 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4801 4802 /* 4803 * pseries-2.7 4804 */ 4805 4806 static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4807 uint64_t *buid, hwaddr *pio, 4808 hwaddr *mmio32, hwaddr *mmio64, 4809 unsigned n_dma, uint32_t *liobns, 4810 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4811 { 4812 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4813 const uint64_t base_buid = 0x800000020000000ULL; 4814 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4815 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4816 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4817 const uint32_t max_index = 255; 4818 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4819 4820 uint64_t ram_top = MACHINE(spapr)->ram_size; 4821 hwaddr phb0_base, phb_base; 4822 int i; 4823 4824 /* Do we have device memory? */ 4825 if (MACHINE(spapr)->maxram_size > ram_top) { 4826 /* Can't just use maxram_size, because there may be an 4827 * alignment gap between normal and device memory regions 4828 */ 4829 ram_top = MACHINE(spapr)->device_memory->base + 4830 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4831 } 4832 4833 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4834 4835 if (index > max_index) { 4836 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4837 max_index); 4838 return; 4839 } 4840 4841 *buid = base_buid + index; 4842 for (i = 0; i < n_dma; ++i) { 4843 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4844 } 4845 4846 phb_base = phb0_base + index * phb_spacing; 4847 *pio = phb_base + pio_offset; 4848 *mmio32 = phb_base + mmio_offset; 4849 /* 4850 * We don't set the 64-bit MMIO window, relying on the PHB's 4851 * fallback behaviour of automatically splitting a large "32-bit" 4852 * window into contiguous 32-bit and 64-bit windows 4853 */ 4854 4855 *nv2gpa = 0; 4856 *nv2atsd = 0; 4857 } 4858 4859 static void spapr_machine_2_7_class_options(MachineClass *mc) 4860 { 4861 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4862 static GlobalProperty compat[] = { 4863 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4864 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4865 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4866 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4867 }; 4868 4869 spapr_machine_2_8_class_options(mc); 4870 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4871 mc->default_machine_opts = "modern-hotplug-events=off"; 4872 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4873 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4874 smc->phb_placement = phb_placement_2_7; 4875 } 4876 4877 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4878 4879 /* 4880 * pseries-2.6 4881 */ 4882 4883 static void spapr_machine_2_6_class_options(MachineClass *mc) 4884 { 4885 static GlobalProperty compat[] = { 4886 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4887 }; 4888 4889 spapr_machine_2_7_class_options(mc); 4890 mc->has_hotpluggable_cpus = false; 4891 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4892 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4893 } 4894 4895 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4896 4897 /* 4898 * pseries-2.5 4899 */ 4900 4901 static void spapr_machine_2_5_class_options(MachineClass *mc) 4902 { 4903 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4904 static GlobalProperty compat[] = { 4905 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4906 }; 4907 4908 spapr_machine_2_6_class_options(mc); 4909 smc->use_ohci_by_default = true; 4910 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4911 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4912 } 4913 4914 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4915 4916 /* 4917 * pseries-2.4 4918 */ 4919 4920 static void spapr_machine_2_4_class_options(MachineClass *mc) 4921 { 4922 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4923 4924 spapr_machine_2_5_class_options(mc); 4925 smc->dr_lmb_enabled = false; 4926 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4927 } 4928 4929 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4930 4931 /* 4932 * pseries-2.3 4933 */ 4934 4935 static void spapr_machine_2_3_class_options(MachineClass *mc) 4936 { 4937 static GlobalProperty compat[] = { 4938 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4939 }; 4940 spapr_machine_2_4_class_options(mc); 4941 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4942 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4943 } 4944 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4945 4946 /* 4947 * pseries-2.2 4948 */ 4949 4950 static void spapr_machine_2_2_class_options(MachineClass *mc) 4951 { 4952 static GlobalProperty compat[] = { 4953 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4954 }; 4955 4956 spapr_machine_2_3_class_options(mc); 4957 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4958 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4959 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4960 } 4961 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4962 4963 /* 4964 * pseries-2.1 4965 */ 4966 4967 static void spapr_machine_2_1_class_options(MachineClass *mc) 4968 { 4969 spapr_machine_2_2_class_options(mc); 4970 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4971 } 4972 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4973 4974 static void spapr_machine_register_types(void) 4975 { 4976 type_register_static(&spapr_machine_info); 4977 } 4978 4979 type_init(spapr_machine_register_types) 4980