1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/numa.h" 31 #include "hw/hw.h" 32 #include "qemu/log.h" 33 #include "hw/fw-path-provider.h" 34 #include "elf.h" 35 #include "net/net.h" 36 #include "sysemu/device_tree.h" 37 #include "sysemu/block-backend.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/hw_accel.h" 40 #include "kvm_ppc.h" 41 #include "migration/migration.h" 42 #include "mmu-hash64.h" 43 #include "mmu-book3s-v3.h" 44 #include "qom/cpu.h" 45 46 #include "hw/boards.h" 47 #include "hw/ppc/ppc.h" 48 #include "hw/loader.h" 49 50 #include "hw/ppc/fdt.h" 51 #include "hw/ppc/spapr.h" 52 #include "hw/ppc/spapr_vio.h" 53 #include "hw/pci-host/spapr.h" 54 #include "hw/ppc/xics.h" 55 #include "hw/pci/msi.h" 56 57 #include "hw/pci/pci.h" 58 #include "hw/scsi/scsi.h" 59 #include "hw/virtio/virtio-scsi.h" 60 61 #include "exec/address-spaces.h" 62 #include "hw/usb.h" 63 #include "qemu/config-file.h" 64 #include "qemu/error-report.h" 65 #include "trace.h" 66 #include "hw/nmi.h" 67 #include "hw/intc/intc.h" 68 69 #include "hw/compat.h" 70 #include "qemu/cutils.h" 71 #include "hw/ppc/spapr_cpu_core.h" 72 #include "qmp-commands.h" 73 74 #include <libfdt.h> 75 76 /* SLOF memory layout: 77 * 78 * SLOF raw image loaded at 0, copies its romfs right below the flat 79 * device-tree, then position SLOF itself 31M below that 80 * 81 * So we set FW_OVERHEAD to 40MB which should account for all of that 82 * and more 83 * 84 * We load our kernel at 4M, leaving space for SLOF initial image 85 */ 86 #define FDT_MAX_SIZE 0x100000 87 #define RTAS_MAX_SIZE 0x10000 88 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 89 #define FW_MAX_SIZE 0x400000 90 #define FW_FILE_NAME "slof.bin" 91 #define FW_OVERHEAD 0x2800000 92 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 93 94 #define MIN_RMA_SLOF 128UL 95 96 #define PHANDLE_XICP 0x00001111 97 98 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 99 100 static int try_create_xics(sPAPRMachineState *spapr, const char *type_ics, 101 const char *type_icp, int nr_servers, 102 int nr_irqs, Error **errp) 103 { 104 XICSFabric *xi = XICS_FABRIC(spapr); 105 Error *err = NULL, *local_err = NULL; 106 ICSState *ics = NULL; 107 int i; 108 109 ics = ICS_SIMPLE(object_new(type_ics)); 110 object_property_add_child(OBJECT(spapr), "ics", OBJECT(ics), NULL); 111 object_property_set_int(OBJECT(ics), nr_irqs, "nr-irqs", &err); 112 object_property_add_const_link(OBJECT(ics), "xics", OBJECT(xi), NULL); 113 object_property_set_bool(OBJECT(ics), true, "realized", &local_err); 114 error_propagate(&err, local_err); 115 if (err) { 116 goto error; 117 } 118 119 spapr->icps = g_malloc0(nr_servers * sizeof(ICPState)); 120 spapr->nr_servers = nr_servers; 121 122 for (i = 0; i < nr_servers; i++) { 123 ICPState *icp = &spapr->icps[i]; 124 125 object_initialize(icp, sizeof(*icp), type_icp); 126 object_property_add_child(OBJECT(spapr), "icp[*]", OBJECT(icp), NULL); 127 object_property_add_const_link(OBJECT(icp), "xics", OBJECT(xi), NULL); 128 object_property_set_bool(OBJECT(icp), true, "realized", &err); 129 if (err) { 130 goto error; 131 } 132 object_unref(OBJECT(icp)); 133 } 134 135 spapr->ics = ics; 136 return 0; 137 138 error: 139 error_propagate(errp, err); 140 if (ics) { 141 object_unparent(OBJECT(ics)); 142 } 143 return -1; 144 } 145 146 static int xics_system_init(MachineState *machine, 147 int nr_servers, int nr_irqs, Error **errp) 148 { 149 int rc = -1; 150 151 if (kvm_enabled()) { 152 Error *err = NULL; 153 154 if (machine_kernel_irqchip_allowed(machine) && 155 !xics_kvm_init(SPAPR_MACHINE(machine), errp)) { 156 rc = try_create_xics(SPAPR_MACHINE(machine), TYPE_ICS_KVM, 157 TYPE_KVM_ICP, nr_servers, nr_irqs, &err); 158 } 159 if (machine_kernel_irqchip_required(machine) && rc < 0) { 160 error_reportf_err(err, 161 "kernel_irqchip requested but unavailable: "); 162 } else { 163 error_free(err); 164 } 165 } 166 167 if (rc < 0) { 168 xics_spapr_init(SPAPR_MACHINE(machine), errp); 169 rc = try_create_xics(SPAPR_MACHINE(machine), TYPE_ICS_SIMPLE, 170 TYPE_ICP, nr_servers, nr_irqs, errp); 171 } 172 173 return rc; 174 } 175 176 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 177 int smt_threads) 178 { 179 int i, ret = 0; 180 uint32_t servers_prop[smt_threads]; 181 uint32_t gservers_prop[smt_threads * 2]; 182 int index = ppc_get_vcpu_dt_id(cpu); 183 184 if (cpu->compat_pvr) { 185 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 186 if (ret < 0) { 187 return ret; 188 } 189 } 190 191 /* Build interrupt servers and gservers properties */ 192 for (i = 0; i < smt_threads; i++) { 193 servers_prop[i] = cpu_to_be32(index + i); 194 /* Hack, direct the group queues back to cpu 0 */ 195 gservers_prop[i*2] = cpu_to_be32(index + i); 196 gservers_prop[i*2 + 1] = 0; 197 } 198 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 199 servers_prop, sizeof(servers_prop)); 200 if (ret < 0) { 201 return ret; 202 } 203 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 204 gservers_prop, sizeof(gservers_prop)); 205 206 return ret; 207 } 208 209 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs) 210 { 211 int ret = 0; 212 PowerPCCPU *cpu = POWERPC_CPU(cs); 213 int index = ppc_get_vcpu_dt_id(cpu); 214 uint32_t associativity[] = {cpu_to_be32(0x5), 215 cpu_to_be32(0x0), 216 cpu_to_be32(0x0), 217 cpu_to_be32(0x0), 218 cpu_to_be32(cs->numa_node), 219 cpu_to_be32(index)}; 220 221 /* Advertise NUMA via ibm,associativity */ 222 if (nb_numa_nodes > 1) { 223 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 224 sizeof(associativity)); 225 } 226 227 return ret; 228 } 229 230 /* Populate the "ibm,pa-features" property */ 231 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset, 232 bool legacy_guest) 233 { 234 uint8_t pa_features_206[] = { 6, 0, 235 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 236 uint8_t pa_features_207[] = { 24, 0, 237 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 238 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 239 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 240 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 241 uint8_t pa_features_300[] = { 66, 0, 242 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 243 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 244 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 245 /* 6: DS207 */ 246 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 247 /* 16: Vector */ 248 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 249 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 250 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */ 251 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 252 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 253 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 254 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 255 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 256 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 257 /* 42: PM, 44: PC RA, 46: SC vec'd */ 258 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 259 /* 48: SIMD, 50: QP BFP, 52: String */ 260 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 261 /* 54: DecFP, 56: DecI, 58: SHA */ 262 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 263 /* 60: NM atomic, 62: RNG */ 264 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 265 }; 266 uint8_t *pa_features; 267 size_t pa_size; 268 269 switch (POWERPC_MMU_VER(env->mmu_model)) { 270 case POWERPC_MMU_VER_2_06: 271 pa_features = pa_features_206; 272 pa_size = sizeof(pa_features_206); 273 break; 274 case POWERPC_MMU_VER_2_07: 275 pa_features = pa_features_207; 276 pa_size = sizeof(pa_features_207); 277 break; 278 case POWERPC_MMU_VER_3_00: 279 pa_features = pa_features_300; 280 pa_size = sizeof(pa_features_300); 281 break; 282 default: 283 return; 284 } 285 286 if (env->ci_large_pages) { 287 /* 288 * Note: we keep CI large pages off by default because a 64K capable 289 * guest provisioned with large pages might otherwise try to map a qemu 290 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 291 * even if that qemu runs on a 4k host. 292 * We dd this bit back here if we are confident this is not an issue 293 */ 294 pa_features[3] |= 0x20; 295 } 296 if (kvmppc_has_cap_htm() && pa_size > 24) { 297 pa_features[24] |= 0x80; /* Transactional memory support */ 298 } 299 if (legacy_guest && pa_size > 40) { 300 /* Workaround for broken kernels that attempt (guest) radix 301 * mode when they can't handle it, if they see the radix bit set 302 * in pa-features. So hide it from them. */ 303 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 304 } 305 306 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 307 } 308 309 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 310 { 311 int ret = 0, offset, cpus_offset; 312 CPUState *cs; 313 char cpu_model[32]; 314 int smt = kvmppc_smt_threads(); 315 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 316 317 CPU_FOREACH(cs) { 318 PowerPCCPU *cpu = POWERPC_CPU(cs); 319 CPUPPCState *env = &cpu->env; 320 DeviceClass *dc = DEVICE_GET_CLASS(cs); 321 int index = ppc_get_vcpu_dt_id(cpu); 322 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 323 324 if ((index % smt) != 0) { 325 continue; 326 } 327 328 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 329 330 cpus_offset = fdt_path_offset(fdt, "/cpus"); 331 if (cpus_offset < 0) { 332 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 333 "cpus"); 334 if (cpus_offset < 0) { 335 return cpus_offset; 336 } 337 } 338 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 339 if (offset < 0) { 340 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 341 if (offset < 0) { 342 return offset; 343 } 344 } 345 346 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 347 pft_size_prop, sizeof(pft_size_prop)); 348 if (ret < 0) { 349 return ret; 350 } 351 352 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs); 353 if (ret < 0) { 354 return ret; 355 } 356 357 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 358 if (ret < 0) { 359 return ret; 360 } 361 362 spapr_populate_pa_features(env, fdt, offset, 363 spapr->cas_legacy_guest_workaround); 364 } 365 return ret; 366 } 367 368 static hwaddr spapr_node0_size(void) 369 { 370 MachineState *machine = MACHINE(qdev_get_machine()); 371 372 if (nb_numa_nodes) { 373 int i; 374 for (i = 0; i < nb_numa_nodes; ++i) { 375 if (numa_info[i].node_mem) { 376 return MIN(pow2floor(numa_info[i].node_mem), 377 machine->ram_size); 378 } 379 } 380 } 381 return machine->ram_size; 382 } 383 384 static void add_str(GString *s, const gchar *s1) 385 { 386 g_string_append_len(s, s1, strlen(s1) + 1); 387 } 388 389 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 390 hwaddr size) 391 { 392 uint32_t associativity[] = { 393 cpu_to_be32(0x4), /* length */ 394 cpu_to_be32(0x0), cpu_to_be32(0x0), 395 cpu_to_be32(0x0), cpu_to_be32(nodeid) 396 }; 397 char mem_name[32]; 398 uint64_t mem_reg_property[2]; 399 int off; 400 401 mem_reg_property[0] = cpu_to_be64(start); 402 mem_reg_property[1] = cpu_to_be64(size); 403 404 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 405 off = fdt_add_subnode(fdt, 0, mem_name); 406 _FDT(off); 407 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 408 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 409 sizeof(mem_reg_property)))); 410 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 411 sizeof(associativity)))); 412 return off; 413 } 414 415 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 416 { 417 MachineState *machine = MACHINE(spapr); 418 hwaddr mem_start, node_size; 419 int i, nb_nodes = nb_numa_nodes; 420 NodeInfo *nodes = numa_info; 421 NodeInfo ramnode; 422 423 /* No NUMA nodes, assume there is just one node with whole RAM */ 424 if (!nb_numa_nodes) { 425 nb_nodes = 1; 426 ramnode.node_mem = machine->ram_size; 427 nodes = &ramnode; 428 } 429 430 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 431 if (!nodes[i].node_mem) { 432 continue; 433 } 434 if (mem_start >= machine->ram_size) { 435 node_size = 0; 436 } else { 437 node_size = nodes[i].node_mem; 438 if (node_size > machine->ram_size - mem_start) { 439 node_size = machine->ram_size - mem_start; 440 } 441 } 442 if (!mem_start) { 443 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 444 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 445 mem_start += spapr->rma_size; 446 node_size -= spapr->rma_size; 447 } 448 for ( ; node_size; ) { 449 hwaddr sizetmp = pow2floor(node_size); 450 451 /* mem_start != 0 here */ 452 if (ctzl(mem_start) < ctzl(sizetmp)) { 453 sizetmp = 1ULL << ctzl(mem_start); 454 } 455 456 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 457 node_size -= sizetmp; 458 mem_start += sizetmp; 459 } 460 } 461 462 return 0; 463 } 464 465 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 466 sPAPRMachineState *spapr) 467 { 468 PowerPCCPU *cpu = POWERPC_CPU(cs); 469 CPUPPCState *env = &cpu->env; 470 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 471 int index = ppc_get_vcpu_dt_id(cpu); 472 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 473 0xffffffff, 0xffffffff}; 474 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 475 : SPAPR_TIMEBASE_FREQ; 476 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 477 uint32_t page_sizes_prop[64]; 478 size_t page_sizes_prop_size; 479 uint32_t vcpus_per_socket = smp_threads * smp_cores; 480 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 481 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 482 sPAPRDRConnector *drc; 483 sPAPRDRConnectorClass *drck; 484 int drc_index; 485 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 486 int i; 487 488 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index); 489 if (drc) { 490 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 491 drc_index = drck->get_index(drc); 492 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 493 } 494 495 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 496 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 497 498 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 499 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 500 env->dcache_line_size))); 501 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 502 env->dcache_line_size))); 503 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 504 env->icache_line_size))); 505 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 506 env->icache_line_size))); 507 508 if (pcc->l1_dcache_size) { 509 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 510 pcc->l1_dcache_size))); 511 } else { 512 error_report("Warning: Unknown L1 dcache size for cpu"); 513 } 514 if (pcc->l1_icache_size) { 515 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 516 pcc->l1_icache_size))); 517 } else { 518 error_report("Warning: Unknown L1 icache size for cpu"); 519 } 520 521 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 522 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 523 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 524 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 525 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 526 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 527 528 if (env->spr_cb[SPR_PURR].oea_read) { 529 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 530 } 531 532 if (env->mmu_model & POWERPC_MMU_1TSEG) { 533 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 534 segs, sizeof(segs)))); 535 } 536 537 /* Advertise VMX/VSX (vector extensions) if available 538 * 0 / no property == no vector extensions 539 * 1 == VMX / Altivec available 540 * 2 == VSX available */ 541 if (env->insns_flags & PPC_ALTIVEC) { 542 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 543 544 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 545 } 546 547 /* Advertise DFP (Decimal Floating Point) if available 548 * 0 / no property == no DFP 549 * 1 == DFP available */ 550 if (env->insns_flags2 & PPC2_DFP) { 551 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 552 } 553 554 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 555 sizeof(page_sizes_prop)); 556 if (page_sizes_prop_size) { 557 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 558 page_sizes_prop, page_sizes_prop_size))); 559 } 560 561 spapr_populate_pa_features(env, fdt, offset, false); 562 563 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 564 cs->cpu_index / vcpus_per_socket))); 565 566 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 567 pft_size_prop, sizeof(pft_size_prop)))); 568 569 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs)); 570 571 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 572 573 if (pcc->radix_page_info) { 574 for (i = 0; i < pcc->radix_page_info->count; i++) { 575 radix_AP_encodings[i] = 576 cpu_to_be32(pcc->radix_page_info->entries[i]); 577 } 578 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 579 radix_AP_encodings, 580 pcc->radix_page_info->count * 581 sizeof(radix_AP_encodings[0])))); 582 } 583 } 584 585 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 586 { 587 CPUState *cs; 588 int cpus_offset; 589 char *nodename; 590 int smt = kvmppc_smt_threads(); 591 592 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 593 _FDT(cpus_offset); 594 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 595 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 596 597 /* 598 * We walk the CPUs in reverse order to ensure that CPU DT nodes 599 * created by fdt_add_subnode() end up in the right order in FDT 600 * for the guest kernel the enumerate the CPUs correctly. 601 */ 602 CPU_FOREACH_REVERSE(cs) { 603 PowerPCCPU *cpu = POWERPC_CPU(cs); 604 int index = ppc_get_vcpu_dt_id(cpu); 605 DeviceClass *dc = DEVICE_GET_CLASS(cs); 606 int offset; 607 608 if ((index % smt) != 0) { 609 continue; 610 } 611 612 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 613 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 614 g_free(nodename); 615 _FDT(offset); 616 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 617 } 618 619 } 620 621 /* 622 * Adds ibm,dynamic-reconfiguration-memory node. 623 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 624 * of this device tree node. 625 */ 626 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 627 { 628 MachineState *machine = MACHINE(spapr); 629 int ret, i, offset; 630 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 631 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 632 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 633 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 634 memory_region_size(&spapr->hotplug_memory.mr)) / 635 lmb_size; 636 uint32_t *int_buf, *cur_index, buf_len; 637 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 638 639 /* 640 * Don't create the node if there is no hotpluggable memory 641 */ 642 if (machine->ram_size == machine->maxram_size) { 643 return 0; 644 } 645 646 /* 647 * Allocate enough buffer size to fit in ibm,dynamic-memory 648 * or ibm,associativity-lookup-arrays 649 */ 650 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 651 * sizeof(uint32_t); 652 cur_index = int_buf = g_malloc0(buf_len); 653 654 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 655 656 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 657 sizeof(prop_lmb_size)); 658 if (ret < 0) { 659 goto out; 660 } 661 662 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 663 if (ret < 0) { 664 goto out; 665 } 666 667 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 668 if (ret < 0) { 669 goto out; 670 } 671 672 /* ibm,dynamic-memory */ 673 int_buf[0] = cpu_to_be32(nr_lmbs); 674 cur_index++; 675 for (i = 0; i < nr_lmbs; i++) { 676 uint64_t addr = i * lmb_size; 677 uint32_t *dynamic_memory = cur_index; 678 679 if (i >= hotplug_lmb_start) { 680 sPAPRDRConnector *drc; 681 sPAPRDRConnectorClass *drck; 682 683 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i); 684 g_assert(drc); 685 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 686 687 dynamic_memory[0] = cpu_to_be32(addr >> 32); 688 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 689 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); 690 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 691 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); 692 if (memory_region_present(get_system_memory(), addr)) { 693 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 694 } else { 695 dynamic_memory[5] = cpu_to_be32(0); 696 } 697 } else { 698 /* 699 * LMB information for RMA, boot time RAM and gap b/n RAM and 700 * hotplug memory region -- all these are marked as reserved 701 * and as having no valid DRC. 702 */ 703 dynamic_memory[0] = cpu_to_be32(addr >> 32); 704 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 705 dynamic_memory[2] = cpu_to_be32(0); 706 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 707 dynamic_memory[4] = cpu_to_be32(-1); 708 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 709 SPAPR_LMB_FLAGS_DRC_INVALID); 710 } 711 712 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 713 } 714 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 715 if (ret < 0) { 716 goto out; 717 } 718 719 /* ibm,associativity-lookup-arrays */ 720 cur_index = int_buf; 721 int_buf[0] = cpu_to_be32(nr_nodes); 722 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 723 cur_index += 2; 724 for (i = 0; i < nr_nodes; i++) { 725 uint32_t associativity[] = { 726 cpu_to_be32(0x0), 727 cpu_to_be32(0x0), 728 cpu_to_be32(0x0), 729 cpu_to_be32(i) 730 }; 731 memcpy(cur_index, associativity, sizeof(associativity)); 732 cur_index += 4; 733 } 734 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 735 (cur_index - int_buf) * sizeof(uint32_t)); 736 out: 737 g_free(int_buf); 738 return ret; 739 } 740 741 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 742 sPAPROptionVector *ov5_updates) 743 { 744 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 745 int ret = 0, offset; 746 747 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 748 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 749 g_assert(smc->dr_lmb_enabled); 750 ret = spapr_populate_drconf_memory(spapr, fdt); 751 if (ret) { 752 goto out; 753 } 754 } 755 756 offset = fdt_path_offset(fdt, "/chosen"); 757 if (offset < 0) { 758 offset = fdt_add_subnode(fdt, 0, "chosen"); 759 if (offset < 0) { 760 return offset; 761 } 762 } 763 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 764 "ibm,architecture-vec-5"); 765 766 out: 767 return ret; 768 } 769 770 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 771 target_ulong addr, target_ulong size, 772 sPAPROptionVector *ov5_updates) 773 { 774 void *fdt, *fdt_skel; 775 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 776 777 size -= sizeof(hdr); 778 779 /* Create sceleton */ 780 fdt_skel = g_malloc0(size); 781 _FDT((fdt_create(fdt_skel, size))); 782 _FDT((fdt_begin_node(fdt_skel, ""))); 783 _FDT((fdt_end_node(fdt_skel))); 784 _FDT((fdt_finish(fdt_skel))); 785 fdt = g_malloc0(size); 786 _FDT((fdt_open_into(fdt_skel, fdt, size))); 787 g_free(fdt_skel); 788 789 /* Fixup cpu nodes */ 790 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 791 792 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 793 return -1; 794 } 795 796 /* Pack resulting tree */ 797 _FDT((fdt_pack(fdt))); 798 799 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 800 trace_spapr_cas_failed(size); 801 return -1; 802 } 803 804 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 805 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 806 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 807 g_free(fdt); 808 809 return 0; 810 } 811 812 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 813 { 814 int rtas; 815 GString *hypertas = g_string_sized_new(256); 816 GString *qemu_hypertas = g_string_sized_new(256); 817 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 818 uint64_t max_hotplug_addr = spapr->hotplug_memory.base + 819 memory_region_size(&spapr->hotplug_memory.mr); 820 uint32_t lrdr_capacity[] = { 821 cpu_to_be32(max_hotplug_addr >> 32), 822 cpu_to_be32(max_hotplug_addr & 0xffffffff), 823 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 824 cpu_to_be32(max_cpus / smp_threads), 825 }; 826 827 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 828 829 /* hypertas */ 830 add_str(hypertas, "hcall-pft"); 831 add_str(hypertas, "hcall-term"); 832 add_str(hypertas, "hcall-dabr"); 833 add_str(hypertas, "hcall-interrupt"); 834 add_str(hypertas, "hcall-tce"); 835 add_str(hypertas, "hcall-vio"); 836 add_str(hypertas, "hcall-splpar"); 837 add_str(hypertas, "hcall-bulk"); 838 add_str(hypertas, "hcall-set-mode"); 839 add_str(hypertas, "hcall-sprg0"); 840 add_str(hypertas, "hcall-copy"); 841 add_str(hypertas, "hcall-debug"); 842 add_str(qemu_hypertas, "hcall-memop1"); 843 844 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 845 add_str(hypertas, "hcall-multi-tce"); 846 } 847 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 848 hypertas->str, hypertas->len)); 849 g_string_free(hypertas, TRUE); 850 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 851 qemu_hypertas->str, qemu_hypertas->len)); 852 g_string_free(qemu_hypertas, TRUE); 853 854 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 855 refpoints, sizeof(refpoints))); 856 857 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 858 RTAS_ERROR_LOG_MAX)); 859 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 860 RTAS_EVENT_SCAN_RATE)); 861 862 if (msi_nonbroken) { 863 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 864 } 865 866 /* 867 * According to PAPR, rtas ibm,os-term does not guarantee a return 868 * back to the guest cpu. 869 * 870 * While an additional ibm,extended-os-term property indicates 871 * that rtas call return will always occur. Set this property. 872 */ 873 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 874 875 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 876 lrdr_capacity, sizeof(lrdr_capacity))); 877 878 spapr_dt_rtas_tokens(fdt, rtas); 879 } 880 881 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features 882 * that the guest may request and thus the valid values for bytes 24..26 of 883 * option vector 5: */ 884 static void spapr_dt_ov5_platform_support(void *fdt, int chosen) 885 { 886 char val[2 * 3] = { 887 24, 0x00, /* Hash/Radix, filled in below. */ 888 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 889 26, 0x40, /* Radix options: GTSE == yes. */ 890 }; 891 892 if (kvm_enabled()) { 893 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 894 val[1] = 0x80; /* OV5_MMU_BOTH */ 895 } else if (kvmppc_has_cap_mmu_radix()) { 896 val[1] = 0x40; /* OV5_MMU_RADIX_300 */ 897 } else { 898 val[1] = 0x00; /* Hash */ 899 } 900 } else { 901 /* TODO: TCG case, hash */ 902 val[1] = 0x00; 903 } 904 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 905 val, sizeof(val))); 906 } 907 908 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 909 { 910 MachineState *machine = MACHINE(spapr); 911 int chosen; 912 const char *boot_device = machine->boot_order; 913 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 914 size_t cb = 0; 915 char *bootlist = get_boot_devices_list(&cb, true); 916 917 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 918 919 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 920 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 921 spapr->initrd_base)); 922 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 923 spapr->initrd_base + spapr->initrd_size)); 924 925 if (spapr->kernel_size) { 926 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 927 cpu_to_be64(spapr->kernel_size) }; 928 929 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 930 &kprop, sizeof(kprop))); 931 if (spapr->kernel_le) { 932 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 933 } 934 } 935 if (boot_menu) { 936 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 937 } 938 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 939 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 940 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 941 942 if (cb && bootlist) { 943 int i; 944 945 for (i = 0; i < cb; i++) { 946 if (bootlist[i] == '\n') { 947 bootlist[i] = ' '; 948 } 949 } 950 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 951 } 952 953 if (boot_device && strlen(boot_device)) { 954 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 955 } 956 957 if (!spapr->has_graphics && stdout_path) { 958 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 959 } 960 961 spapr_dt_ov5_platform_support(fdt, chosen); 962 963 g_free(stdout_path); 964 g_free(bootlist); 965 } 966 967 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 968 { 969 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 970 * KVM to work under pHyp with some guest co-operation */ 971 int hypervisor; 972 uint8_t hypercall[16]; 973 974 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 975 /* indicate KVM hypercall interface */ 976 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 977 if (kvmppc_has_cap_fixup_hcalls()) { 978 /* 979 * Older KVM versions with older guest kernels were broken 980 * with the magic page, don't allow the guest to map it. 981 */ 982 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 983 sizeof(hypercall))) { 984 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 985 hypercall, sizeof(hypercall))); 986 } 987 } 988 } 989 990 static void *spapr_build_fdt(sPAPRMachineState *spapr, 991 hwaddr rtas_addr, 992 hwaddr rtas_size) 993 { 994 MachineState *machine = MACHINE(qdev_get_machine()); 995 MachineClass *mc = MACHINE_GET_CLASS(machine); 996 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 997 int ret; 998 void *fdt; 999 sPAPRPHBState *phb; 1000 char *buf; 1001 1002 fdt = g_malloc0(FDT_MAX_SIZE); 1003 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 1004 1005 /* Root node */ 1006 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1007 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1008 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1009 1010 /* 1011 * Add info to guest to indentify which host is it being run on 1012 * and what is the uuid of the guest 1013 */ 1014 if (kvmppc_get_host_model(&buf)) { 1015 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1016 g_free(buf); 1017 } 1018 if (kvmppc_get_host_serial(&buf)) { 1019 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1020 g_free(buf); 1021 } 1022 1023 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1024 1025 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1026 if (qemu_uuid_set) { 1027 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1028 } 1029 g_free(buf); 1030 1031 if (qemu_get_vm_name()) { 1032 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1033 qemu_get_vm_name())); 1034 } 1035 1036 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1037 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1038 1039 /* /interrupt controller */ 1040 spapr_dt_xics(spapr->nr_servers, fdt, PHANDLE_XICP); 1041 1042 ret = spapr_populate_memory(spapr, fdt); 1043 if (ret < 0) { 1044 error_report("couldn't setup memory nodes in fdt"); 1045 exit(1); 1046 } 1047 1048 /* /vdevice */ 1049 spapr_dt_vdevice(spapr->vio_bus, fdt); 1050 1051 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1052 ret = spapr_rng_populate_dt(fdt); 1053 if (ret < 0) { 1054 error_report("could not set up rng device in the fdt"); 1055 exit(1); 1056 } 1057 } 1058 1059 QLIST_FOREACH(phb, &spapr->phbs, list) { 1060 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 1061 if (ret < 0) { 1062 error_report("couldn't setup PCI devices in fdt"); 1063 exit(1); 1064 } 1065 } 1066 1067 /* cpus */ 1068 spapr_populate_cpus_dt_node(fdt, spapr); 1069 1070 if (smc->dr_lmb_enabled) { 1071 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1072 } 1073 1074 if (mc->has_hotpluggable_cpus) { 1075 int offset = fdt_path_offset(fdt, "/cpus"); 1076 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1077 SPAPR_DR_CONNECTOR_TYPE_CPU); 1078 if (ret < 0) { 1079 error_report("Couldn't set up CPU DR device tree properties"); 1080 exit(1); 1081 } 1082 } 1083 1084 /* /event-sources */ 1085 spapr_dt_events(spapr, fdt); 1086 1087 /* /rtas */ 1088 spapr_dt_rtas(spapr, fdt); 1089 1090 /* /chosen */ 1091 spapr_dt_chosen(spapr, fdt); 1092 1093 /* /hypervisor */ 1094 if (kvm_enabled()) { 1095 spapr_dt_hypervisor(spapr, fdt); 1096 } 1097 1098 /* Build memory reserve map */ 1099 if (spapr->kernel_size) { 1100 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1101 } 1102 if (spapr->initrd_size) { 1103 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1104 } 1105 1106 /* ibm,client-architecture-support updates */ 1107 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1108 if (ret < 0) { 1109 error_report("couldn't setup CAS properties fdt"); 1110 exit(1); 1111 } 1112 1113 return fdt; 1114 } 1115 1116 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1117 { 1118 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1119 } 1120 1121 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1122 PowerPCCPU *cpu) 1123 { 1124 CPUPPCState *env = &cpu->env; 1125 1126 /* The TCG path should also be holding the BQL at this point */ 1127 g_assert(qemu_mutex_iothread_locked()); 1128 1129 if (msr_pr) { 1130 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1131 env->gpr[3] = H_PRIVILEGE; 1132 } else { 1133 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1134 } 1135 } 1136 1137 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) 1138 { 1139 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1140 1141 return spapr->patb_entry; 1142 } 1143 1144 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1145 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1146 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1147 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1148 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1149 1150 /* 1151 * Get the fd to access the kernel htab, re-opening it if necessary 1152 */ 1153 static int get_htab_fd(sPAPRMachineState *spapr) 1154 { 1155 if (spapr->htab_fd >= 0) { 1156 return spapr->htab_fd; 1157 } 1158 1159 spapr->htab_fd = kvmppc_get_htab_fd(false); 1160 if (spapr->htab_fd < 0) { 1161 error_report("Unable to open fd for reading hash table from KVM: %s", 1162 strerror(errno)); 1163 } 1164 1165 return spapr->htab_fd; 1166 } 1167 1168 void close_htab_fd(sPAPRMachineState *spapr) 1169 { 1170 if (spapr->htab_fd >= 0) { 1171 close(spapr->htab_fd); 1172 } 1173 spapr->htab_fd = -1; 1174 } 1175 1176 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1177 { 1178 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1179 1180 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1181 } 1182 1183 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1184 hwaddr ptex, int n) 1185 { 1186 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1187 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1188 1189 if (!spapr->htab) { 1190 /* 1191 * HTAB is controlled by KVM. Fetch into temporary buffer 1192 */ 1193 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1194 kvmppc_read_hptes(hptes, ptex, n); 1195 return hptes; 1196 } 1197 1198 /* 1199 * HTAB is controlled by QEMU. Just point to the internally 1200 * accessible PTEG. 1201 */ 1202 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1203 } 1204 1205 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1206 const ppc_hash_pte64_t *hptes, 1207 hwaddr ptex, int n) 1208 { 1209 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1210 1211 if (!spapr->htab) { 1212 g_free((void *)hptes); 1213 } 1214 1215 /* Nothing to do for qemu managed HPT */ 1216 } 1217 1218 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1219 uint64_t pte0, uint64_t pte1) 1220 { 1221 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1222 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1223 1224 if (!spapr->htab) { 1225 kvmppc_write_hpte(ptex, pte0, pte1); 1226 } else { 1227 stq_p(spapr->htab + offset, pte0); 1228 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1229 } 1230 } 1231 1232 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1233 { 1234 int shift; 1235 1236 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1237 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1238 * that's much more than is needed for Linux guests */ 1239 shift = ctz64(pow2ceil(ramsize)) - 7; 1240 shift = MAX(shift, 18); /* Minimum architected size */ 1241 shift = MIN(shift, 46); /* Maximum architected size */ 1242 return shift; 1243 } 1244 1245 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1246 Error **errp) 1247 { 1248 long rc; 1249 1250 /* Clean up any HPT info from a previous boot */ 1251 g_free(spapr->htab); 1252 spapr->htab = NULL; 1253 spapr->htab_shift = 0; 1254 close_htab_fd(spapr); 1255 1256 rc = kvmppc_reset_htab(shift); 1257 if (rc < 0) { 1258 /* kernel-side HPT needed, but couldn't allocate one */ 1259 error_setg_errno(errp, errno, 1260 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1261 shift); 1262 /* This is almost certainly fatal, but if the caller really 1263 * wants to carry on with shift == 0, it's welcome to try */ 1264 } else if (rc > 0) { 1265 /* kernel-side HPT allocated */ 1266 if (rc != shift) { 1267 error_setg(errp, 1268 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1269 shift, rc); 1270 } 1271 1272 spapr->htab_shift = shift; 1273 spapr->htab = NULL; 1274 } else { 1275 /* kernel-side HPT not needed, allocate in userspace instead */ 1276 size_t size = 1ULL << shift; 1277 int i; 1278 1279 spapr->htab = qemu_memalign(size, size); 1280 if (!spapr->htab) { 1281 error_setg_errno(errp, errno, 1282 "Could not allocate HPT of order %d", shift); 1283 return; 1284 } 1285 1286 memset(spapr->htab, 0, size); 1287 spapr->htab_shift = shift; 1288 1289 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1290 DIRTY_HPTE(HPTE(spapr->htab, i)); 1291 } 1292 } 1293 } 1294 1295 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) 1296 { 1297 spapr_reallocate_hpt(spapr, 1298 spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size), 1299 &error_fatal); 1300 if (spapr->vrma_adjust) { 1301 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 1302 spapr->htab_shift); 1303 } 1304 /* We're setting up a hash table, so that means we're not radix */ 1305 spapr->patb_entry = 0; 1306 } 1307 1308 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1309 { 1310 bool matched = false; 1311 1312 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1313 matched = true; 1314 } 1315 1316 if (!matched) { 1317 error_report("Device %s is not supported by this machine yet.", 1318 qdev_fw_name(DEVICE(sbdev))); 1319 exit(1); 1320 } 1321 } 1322 1323 static void ppc_spapr_reset(void) 1324 { 1325 MachineState *machine = MACHINE(qdev_get_machine()); 1326 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1327 PowerPCCPU *first_ppc_cpu; 1328 uint32_t rtas_limit; 1329 hwaddr rtas_addr, fdt_addr; 1330 void *fdt; 1331 int rc; 1332 1333 /* Check for unknown sysbus devices */ 1334 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1335 1336 if (kvm_enabled() && kvmppc_has_cap_mmu_radix()) { 1337 /* If using KVM with radix mode available, VCPUs can be started 1338 * without a HPT because KVM will start them in radix mode. 1339 * Set the GR bit in PATB so that we know there is no HPT. */ 1340 spapr->patb_entry = PATBE1_GR; 1341 } else { 1342 spapr->patb_entry = 0; 1343 spapr_setup_hpt_and_vrma(spapr); 1344 } 1345 1346 qemu_devices_reset(); 1347 1348 /* 1349 * We place the device tree and RTAS just below either the top of the RMA, 1350 * or just below 2GB, whichever is lowere, so that it can be 1351 * processed with 32-bit real mode code if necessary 1352 */ 1353 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1354 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1355 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1356 1357 /* if this reset wasn't generated by CAS, we should reset our 1358 * negotiated options and start from scratch */ 1359 if (!spapr->cas_reboot) { 1360 spapr_ovec_cleanup(spapr->ov5_cas); 1361 spapr->ov5_cas = spapr_ovec_new(); 1362 } 1363 1364 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1365 1366 spapr_load_rtas(spapr, fdt, rtas_addr); 1367 1368 rc = fdt_pack(fdt); 1369 1370 /* Should only fail if we've built a corrupted tree */ 1371 assert(rc == 0); 1372 1373 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1374 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1375 fdt_totalsize(fdt), FDT_MAX_SIZE); 1376 exit(1); 1377 } 1378 1379 /* Load the fdt */ 1380 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1381 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1382 g_free(fdt); 1383 1384 /* Set up the entry state */ 1385 first_ppc_cpu = POWERPC_CPU(first_cpu); 1386 first_ppc_cpu->env.gpr[3] = fdt_addr; 1387 first_ppc_cpu->env.gpr[5] = 0; 1388 first_cpu->halted = 0; 1389 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1390 1391 spapr->cas_reboot = false; 1392 } 1393 1394 static void spapr_create_nvram(sPAPRMachineState *spapr) 1395 { 1396 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1397 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1398 1399 if (dinfo) { 1400 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1401 &error_fatal); 1402 } 1403 1404 qdev_init_nofail(dev); 1405 1406 spapr->nvram = (struct sPAPRNVRAM *)dev; 1407 } 1408 1409 static void spapr_rtc_create(sPAPRMachineState *spapr) 1410 { 1411 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); 1412 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), 1413 &error_fatal); 1414 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1415 &error_fatal); 1416 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1417 "date", &error_fatal); 1418 } 1419 1420 /* Returns whether we want to use VGA or not */ 1421 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1422 { 1423 switch (vga_interface_type) { 1424 case VGA_NONE: 1425 return false; 1426 case VGA_DEVICE: 1427 return true; 1428 case VGA_STD: 1429 case VGA_VIRTIO: 1430 return pci_vga_init(pci_bus) != NULL; 1431 default: 1432 error_setg(errp, 1433 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1434 return false; 1435 } 1436 } 1437 1438 static int spapr_post_load(void *opaque, int version_id) 1439 { 1440 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1441 int err = 0; 1442 1443 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { 1444 int i; 1445 for (i = 0; i < spapr->nr_servers; i++) { 1446 icp_resend(&spapr->icps[i]); 1447 } 1448 } 1449 1450 /* In earlier versions, there was no separate qdev for the PAPR 1451 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1452 * So when migrating from those versions, poke the incoming offset 1453 * value into the RTC device */ 1454 if (version_id < 3) { 1455 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1456 } 1457 1458 return err; 1459 } 1460 1461 static bool version_before_3(void *opaque, int version_id) 1462 { 1463 return version_id < 3; 1464 } 1465 1466 static bool spapr_ov5_cas_needed(void *opaque) 1467 { 1468 sPAPRMachineState *spapr = opaque; 1469 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1470 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1471 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1472 bool cas_needed; 1473 1474 /* Prior to the introduction of sPAPROptionVector, we had two option 1475 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1476 * Both of these options encode machine topology into the device-tree 1477 * in such a way that the now-booted OS should still be able to interact 1478 * appropriately with QEMU regardless of what options were actually 1479 * negotiatied on the source side. 1480 * 1481 * As such, we can avoid migrating the CAS-negotiated options if these 1482 * are the only options available on the current machine/platform. 1483 * Since these are the only options available for pseries-2.7 and 1484 * earlier, this allows us to maintain old->new/new->old migration 1485 * compatibility. 1486 * 1487 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1488 * via default pseries-2.8 machines and explicit command-line parameters. 1489 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1490 * of the actual CAS-negotiated values to continue working properly. For 1491 * example, availability of memory unplug depends on knowing whether 1492 * OV5_HP_EVT was negotiated via CAS. 1493 * 1494 * Thus, for any cases where the set of available CAS-negotiatable 1495 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1496 * include the CAS-negotiated options in the migration stream. 1497 */ 1498 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1499 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1500 1501 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1502 * the mask itself since in the future it's possible "legacy" bits may be 1503 * removed via machine options, which could generate a false positive 1504 * that breaks migration. 1505 */ 1506 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1507 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1508 1509 spapr_ovec_cleanup(ov5_mask); 1510 spapr_ovec_cleanup(ov5_legacy); 1511 spapr_ovec_cleanup(ov5_removed); 1512 1513 return cas_needed; 1514 } 1515 1516 static const VMStateDescription vmstate_spapr_ov5_cas = { 1517 .name = "spapr_option_vector_ov5_cas", 1518 .version_id = 1, 1519 .minimum_version_id = 1, 1520 .needed = spapr_ov5_cas_needed, 1521 .fields = (VMStateField[]) { 1522 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1523 vmstate_spapr_ovec, sPAPROptionVector), 1524 VMSTATE_END_OF_LIST() 1525 }, 1526 }; 1527 1528 static bool spapr_patb_entry_needed(void *opaque) 1529 { 1530 sPAPRMachineState *spapr = opaque; 1531 1532 return !!spapr->patb_entry; 1533 } 1534 1535 static const VMStateDescription vmstate_spapr_patb_entry = { 1536 .name = "spapr_patb_entry", 1537 .version_id = 1, 1538 .minimum_version_id = 1, 1539 .needed = spapr_patb_entry_needed, 1540 .fields = (VMStateField[]) { 1541 VMSTATE_UINT64(patb_entry, sPAPRMachineState), 1542 VMSTATE_END_OF_LIST() 1543 }, 1544 }; 1545 1546 static const VMStateDescription vmstate_spapr = { 1547 .name = "spapr", 1548 .version_id = 3, 1549 .minimum_version_id = 1, 1550 .post_load = spapr_post_load, 1551 .fields = (VMStateField[]) { 1552 /* used to be @next_irq */ 1553 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1554 1555 /* RTC offset */ 1556 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1557 1558 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1559 VMSTATE_END_OF_LIST() 1560 }, 1561 .subsections = (const VMStateDescription*[]) { 1562 &vmstate_spapr_ov5_cas, 1563 &vmstate_spapr_patb_entry, 1564 NULL 1565 } 1566 }; 1567 1568 static int htab_save_setup(QEMUFile *f, void *opaque) 1569 { 1570 sPAPRMachineState *spapr = opaque; 1571 1572 /* "Iteration" header */ 1573 qemu_put_be32(f, spapr->htab_shift); 1574 1575 if (spapr->htab) { 1576 spapr->htab_save_index = 0; 1577 spapr->htab_first_pass = true; 1578 } else { 1579 assert(kvm_enabled()); 1580 } 1581 1582 1583 return 0; 1584 } 1585 1586 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1587 int64_t max_ns) 1588 { 1589 bool has_timeout = max_ns != -1; 1590 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1591 int index = spapr->htab_save_index; 1592 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1593 1594 assert(spapr->htab_first_pass); 1595 1596 do { 1597 int chunkstart; 1598 1599 /* Consume invalid HPTEs */ 1600 while ((index < htabslots) 1601 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1602 CLEAN_HPTE(HPTE(spapr->htab, index)); 1603 index++; 1604 } 1605 1606 /* Consume valid HPTEs */ 1607 chunkstart = index; 1608 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1609 && HPTE_VALID(HPTE(spapr->htab, index))) { 1610 CLEAN_HPTE(HPTE(spapr->htab, index)); 1611 index++; 1612 } 1613 1614 if (index > chunkstart) { 1615 int n_valid = index - chunkstart; 1616 1617 qemu_put_be32(f, chunkstart); 1618 qemu_put_be16(f, n_valid); 1619 qemu_put_be16(f, 0); 1620 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1621 HASH_PTE_SIZE_64 * n_valid); 1622 1623 if (has_timeout && 1624 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1625 break; 1626 } 1627 } 1628 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1629 1630 if (index >= htabslots) { 1631 assert(index == htabslots); 1632 index = 0; 1633 spapr->htab_first_pass = false; 1634 } 1635 spapr->htab_save_index = index; 1636 } 1637 1638 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1639 int64_t max_ns) 1640 { 1641 bool final = max_ns < 0; 1642 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1643 int examined = 0, sent = 0; 1644 int index = spapr->htab_save_index; 1645 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1646 1647 assert(!spapr->htab_first_pass); 1648 1649 do { 1650 int chunkstart, invalidstart; 1651 1652 /* Consume non-dirty HPTEs */ 1653 while ((index < htabslots) 1654 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1655 index++; 1656 examined++; 1657 } 1658 1659 chunkstart = index; 1660 /* Consume valid dirty HPTEs */ 1661 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1662 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1663 && HPTE_VALID(HPTE(spapr->htab, index))) { 1664 CLEAN_HPTE(HPTE(spapr->htab, index)); 1665 index++; 1666 examined++; 1667 } 1668 1669 invalidstart = index; 1670 /* Consume invalid dirty HPTEs */ 1671 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1672 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1673 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1674 CLEAN_HPTE(HPTE(spapr->htab, index)); 1675 index++; 1676 examined++; 1677 } 1678 1679 if (index > chunkstart) { 1680 int n_valid = invalidstart - chunkstart; 1681 int n_invalid = index - invalidstart; 1682 1683 qemu_put_be32(f, chunkstart); 1684 qemu_put_be16(f, n_valid); 1685 qemu_put_be16(f, n_invalid); 1686 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1687 HASH_PTE_SIZE_64 * n_valid); 1688 sent += index - chunkstart; 1689 1690 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1691 break; 1692 } 1693 } 1694 1695 if (examined >= htabslots) { 1696 break; 1697 } 1698 1699 if (index >= htabslots) { 1700 assert(index == htabslots); 1701 index = 0; 1702 } 1703 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1704 1705 if (index >= htabslots) { 1706 assert(index == htabslots); 1707 index = 0; 1708 } 1709 1710 spapr->htab_save_index = index; 1711 1712 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1713 } 1714 1715 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1716 #define MAX_KVM_BUF_SIZE 2048 1717 1718 static int htab_save_iterate(QEMUFile *f, void *opaque) 1719 { 1720 sPAPRMachineState *spapr = opaque; 1721 int fd; 1722 int rc = 0; 1723 1724 /* Iteration header */ 1725 qemu_put_be32(f, 0); 1726 1727 if (!spapr->htab) { 1728 assert(kvm_enabled()); 1729 1730 fd = get_htab_fd(spapr); 1731 if (fd < 0) { 1732 return fd; 1733 } 1734 1735 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1736 if (rc < 0) { 1737 return rc; 1738 } 1739 } else if (spapr->htab_first_pass) { 1740 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1741 } else { 1742 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1743 } 1744 1745 /* End marker */ 1746 qemu_put_be32(f, 0); 1747 qemu_put_be16(f, 0); 1748 qemu_put_be16(f, 0); 1749 1750 return rc; 1751 } 1752 1753 static int htab_save_complete(QEMUFile *f, void *opaque) 1754 { 1755 sPAPRMachineState *spapr = opaque; 1756 int fd; 1757 1758 /* Iteration header */ 1759 qemu_put_be32(f, 0); 1760 1761 if (!spapr->htab) { 1762 int rc; 1763 1764 assert(kvm_enabled()); 1765 1766 fd = get_htab_fd(spapr); 1767 if (fd < 0) { 1768 return fd; 1769 } 1770 1771 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 1772 if (rc < 0) { 1773 return rc; 1774 } 1775 } else { 1776 if (spapr->htab_first_pass) { 1777 htab_save_first_pass(f, spapr, -1); 1778 } 1779 htab_save_later_pass(f, spapr, -1); 1780 } 1781 1782 /* End marker */ 1783 qemu_put_be32(f, 0); 1784 qemu_put_be16(f, 0); 1785 qemu_put_be16(f, 0); 1786 1787 return 0; 1788 } 1789 1790 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1791 { 1792 sPAPRMachineState *spapr = opaque; 1793 uint32_t section_hdr; 1794 int fd = -1; 1795 1796 if (version_id < 1 || version_id > 1) { 1797 error_report("htab_load() bad version"); 1798 return -EINVAL; 1799 } 1800 1801 section_hdr = qemu_get_be32(f); 1802 1803 if (section_hdr) { 1804 Error *local_err = NULL; 1805 1806 /* First section gives the htab size */ 1807 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 1808 if (local_err) { 1809 error_report_err(local_err); 1810 return -EINVAL; 1811 } 1812 return 0; 1813 } 1814 1815 if (!spapr->htab) { 1816 assert(kvm_enabled()); 1817 1818 fd = kvmppc_get_htab_fd(true); 1819 if (fd < 0) { 1820 error_report("Unable to open fd to restore KVM hash table: %s", 1821 strerror(errno)); 1822 } 1823 } 1824 1825 while (true) { 1826 uint32_t index; 1827 uint16_t n_valid, n_invalid; 1828 1829 index = qemu_get_be32(f); 1830 n_valid = qemu_get_be16(f); 1831 n_invalid = qemu_get_be16(f); 1832 1833 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1834 /* End of Stream */ 1835 break; 1836 } 1837 1838 if ((index + n_valid + n_invalid) > 1839 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1840 /* Bad index in stream */ 1841 error_report( 1842 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 1843 index, n_valid, n_invalid, spapr->htab_shift); 1844 return -EINVAL; 1845 } 1846 1847 if (spapr->htab) { 1848 if (n_valid) { 1849 qemu_get_buffer(f, HPTE(spapr->htab, index), 1850 HASH_PTE_SIZE_64 * n_valid); 1851 } 1852 if (n_invalid) { 1853 memset(HPTE(spapr->htab, index + n_valid), 0, 1854 HASH_PTE_SIZE_64 * n_invalid); 1855 } 1856 } else { 1857 int rc; 1858 1859 assert(fd >= 0); 1860 1861 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1862 if (rc < 0) { 1863 return rc; 1864 } 1865 } 1866 } 1867 1868 if (!spapr->htab) { 1869 assert(fd >= 0); 1870 close(fd); 1871 } 1872 1873 return 0; 1874 } 1875 1876 static void htab_cleanup(void *opaque) 1877 { 1878 sPAPRMachineState *spapr = opaque; 1879 1880 close_htab_fd(spapr); 1881 } 1882 1883 static SaveVMHandlers savevm_htab_handlers = { 1884 .save_live_setup = htab_save_setup, 1885 .save_live_iterate = htab_save_iterate, 1886 .save_live_complete_precopy = htab_save_complete, 1887 .cleanup = htab_cleanup, 1888 .load_state = htab_load, 1889 }; 1890 1891 static void spapr_boot_set(void *opaque, const char *boot_device, 1892 Error **errp) 1893 { 1894 MachineState *machine = MACHINE(qdev_get_machine()); 1895 machine->boot_order = g_strdup(boot_device); 1896 } 1897 1898 /* 1899 * Reset routine for LMB DR devices. 1900 * 1901 * Unlike PCI DR devices, LMB DR devices explicitly register this reset 1902 * routine. Reset for PCI DR devices will be handled by PHB reset routine 1903 * when it walks all its children devices. LMB devices reset occurs 1904 * as part of spapr_ppc_reset(). 1905 */ 1906 static void spapr_drc_reset(void *opaque) 1907 { 1908 sPAPRDRConnector *drc = opaque; 1909 DeviceState *d = DEVICE(drc); 1910 1911 if (d) { 1912 device_reset(d); 1913 } 1914 } 1915 1916 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 1917 { 1918 MachineState *machine = MACHINE(spapr); 1919 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 1920 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 1921 int i; 1922 1923 for (i = 0; i < nr_lmbs; i++) { 1924 sPAPRDRConnector *drc; 1925 uint64_t addr; 1926 1927 addr = i * lmb_size + spapr->hotplug_memory.base; 1928 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB, 1929 addr/lmb_size); 1930 qemu_register_reset(spapr_drc_reset, drc); 1931 } 1932 } 1933 1934 /* 1935 * If RAM size, maxmem size and individual node mem sizes aren't aligned 1936 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 1937 * since we can't support such unaligned sizes with DRCONF_MEMORY. 1938 */ 1939 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 1940 { 1941 int i; 1942 1943 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1944 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 1945 " is not aligned to %llu MiB", 1946 machine->ram_size, 1947 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1948 return; 1949 } 1950 1951 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1952 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 1953 " is not aligned to %llu MiB", 1954 machine->ram_size, 1955 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1956 return; 1957 } 1958 1959 for (i = 0; i < nb_numa_nodes; i++) { 1960 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 1961 error_setg(errp, 1962 "Node %d memory size 0x%" PRIx64 1963 " is not aligned to %llu MiB", 1964 i, numa_info[i].node_mem, 1965 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1966 return; 1967 } 1968 } 1969 } 1970 1971 /* find cpu slot in machine->possible_cpus by core_id */ 1972 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 1973 { 1974 int index = id / smp_threads; 1975 1976 if (index >= ms->possible_cpus->len) { 1977 return NULL; 1978 } 1979 if (idx) { 1980 *idx = index; 1981 } 1982 return &ms->possible_cpus->cpus[index]; 1983 } 1984 1985 static void spapr_init_cpus(sPAPRMachineState *spapr) 1986 { 1987 MachineState *machine = MACHINE(spapr); 1988 MachineClass *mc = MACHINE_GET_CLASS(machine); 1989 char *type = spapr_get_cpu_core_type(machine->cpu_model); 1990 int smt = kvmppc_smt_threads(); 1991 const CPUArchIdList *possible_cpus; 1992 int boot_cores_nr = smp_cpus / smp_threads; 1993 int i; 1994 1995 if (!type) { 1996 error_report("Unable to find sPAPR CPU Core definition"); 1997 exit(1); 1998 } 1999 2000 possible_cpus = mc->possible_cpu_arch_ids(machine); 2001 if (mc->has_hotpluggable_cpus) { 2002 if (smp_cpus % smp_threads) { 2003 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2004 smp_cpus, smp_threads); 2005 exit(1); 2006 } 2007 if (max_cpus % smp_threads) { 2008 error_report("max_cpus (%u) must be multiple of threads (%u)", 2009 max_cpus, smp_threads); 2010 exit(1); 2011 } 2012 } else { 2013 if (max_cpus != smp_cpus) { 2014 error_report("This machine version does not support CPU hotplug"); 2015 exit(1); 2016 } 2017 boot_cores_nr = possible_cpus->len; 2018 } 2019 2020 for (i = 0; i < possible_cpus->len; i++) { 2021 int core_id = i * smp_threads; 2022 2023 if (mc->has_hotpluggable_cpus) { 2024 sPAPRDRConnector *drc = 2025 spapr_dr_connector_new(OBJECT(spapr), 2026 SPAPR_DR_CONNECTOR_TYPE_CPU, 2027 (core_id / smp_threads) * smt); 2028 2029 qemu_register_reset(spapr_drc_reset, drc); 2030 } 2031 2032 if (i < boot_cores_nr) { 2033 Object *core = object_new(type); 2034 int nr_threads = smp_threads; 2035 2036 /* Handle the partially filled core for older machine types */ 2037 if ((i + 1) * smp_threads >= smp_cpus) { 2038 nr_threads = smp_cpus - i * smp_threads; 2039 } 2040 2041 object_property_set_int(core, nr_threads, "nr-threads", 2042 &error_fatal); 2043 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2044 &error_fatal); 2045 object_property_set_bool(core, true, "realized", &error_fatal); 2046 } 2047 } 2048 g_free(type); 2049 } 2050 2051 /* pSeries LPAR / sPAPR hardware init */ 2052 static void ppc_spapr_init(MachineState *machine) 2053 { 2054 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2055 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2056 const char *kernel_filename = machine->kernel_filename; 2057 const char *initrd_filename = machine->initrd_filename; 2058 PCIHostState *phb; 2059 int i; 2060 MemoryRegion *sysmem = get_system_memory(); 2061 MemoryRegion *ram = g_new(MemoryRegion, 1); 2062 MemoryRegion *rma_region; 2063 void *rma = NULL; 2064 hwaddr rma_alloc_size; 2065 hwaddr node0_size = spapr_node0_size(); 2066 long load_limit, fw_size; 2067 char *filename; 2068 int smt = kvmppc_smt_threads(); 2069 2070 msi_nonbroken = true; 2071 2072 QLIST_INIT(&spapr->phbs); 2073 2074 /* Allocate RMA if necessary */ 2075 rma_alloc_size = kvmppc_alloc_rma(&rma); 2076 2077 if (rma_alloc_size == -1) { 2078 error_report("Unable to create RMA"); 2079 exit(1); 2080 } 2081 2082 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 2083 spapr->rma_size = rma_alloc_size; 2084 } else { 2085 spapr->rma_size = node0_size; 2086 2087 /* With KVM, we don't actually know whether KVM supports an 2088 * unbounded RMA (PR KVM) or is limited by the hash table size 2089 * (HV KVM using VRMA), so we always assume the latter 2090 * 2091 * In that case, we also limit the initial allocations for RTAS 2092 * etc... to 256M since we have no way to know what the VRMA size 2093 * is going to be as it depends on the size of the hash table 2094 * isn't determined yet. 2095 */ 2096 if (kvm_enabled()) { 2097 spapr->vrma_adjust = 1; 2098 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2099 } 2100 2101 /* Actually we don't support unbounded RMA anymore since we 2102 * added proper emulation of HV mode. The max we can get is 2103 * 16G which also happens to be what we configure for PAPR 2104 * mode so make sure we don't do anything bigger than that 2105 */ 2106 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2107 } 2108 2109 if (spapr->rma_size > node0_size) { 2110 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2111 spapr->rma_size); 2112 exit(1); 2113 } 2114 2115 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2116 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2117 2118 /* Set up Interrupt Controller before we create the VCPUs */ 2119 xics_system_init(machine, DIV_ROUND_UP(max_cpus * smt, smp_threads), 2120 XICS_IRQS_SPAPR, &error_fatal); 2121 2122 /* Set up containers for ibm,client-set-architecture negotiated options */ 2123 spapr->ov5 = spapr_ovec_new(); 2124 spapr->ov5_cas = spapr_ovec_new(); 2125 2126 if (smc->dr_lmb_enabled) { 2127 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2128 spapr_validate_node_memory(machine, &error_fatal); 2129 } 2130 2131 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2132 if (kvmppc_has_cap_mmu_radix()) { 2133 /* KVM always allows GTSE with radix... */ 2134 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2135 } 2136 /* ... but not with hash (currently). */ 2137 2138 /* advertise support for dedicated HP event source to guests */ 2139 if (spapr->use_hotplug_event_source) { 2140 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2141 } 2142 2143 /* init CPUs */ 2144 if (machine->cpu_model == NULL) { 2145 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu; 2146 } 2147 2148 ppc_cpu_parse_features(machine->cpu_model); 2149 2150 spapr_init_cpus(spapr); 2151 2152 if (kvm_enabled()) { 2153 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2154 kvmppc_enable_logical_ci_hcalls(); 2155 kvmppc_enable_set_mode_hcall(); 2156 2157 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2158 kvmppc_enable_clear_ref_mod_hcalls(); 2159 } 2160 2161 /* allocate RAM */ 2162 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2163 machine->ram_size); 2164 memory_region_add_subregion(sysmem, 0, ram); 2165 2166 if (rma_alloc_size && rma) { 2167 rma_region = g_new(MemoryRegion, 1); 2168 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 2169 rma_alloc_size, rma); 2170 vmstate_register_ram_global(rma_region); 2171 memory_region_add_subregion(sysmem, 0, rma_region); 2172 } 2173 2174 /* initialize hotplug memory address space */ 2175 if (machine->ram_size < machine->maxram_size) { 2176 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 2177 /* 2178 * Limit the number of hotpluggable memory slots to half the number 2179 * slots that KVM supports, leaving the other half for PCI and other 2180 * devices. However ensure that number of slots doesn't drop below 32. 2181 */ 2182 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2183 SPAPR_MAX_RAM_SLOTS; 2184 2185 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2186 max_memslots = SPAPR_MAX_RAM_SLOTS; 2187 } 2188 if (machine->ram_slots > max_memslots) { 2189 error_report("Specified number of memory slots %" 2190 PRIu64" exceeds max supported %d", 2191 machine->ram_slots, max_memslots); 2192 exit(1); 2193 } 2194 2195 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 2196 SPAPR_HOTPLUG_MEM_ALIGN); 2197 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 2198 "hotplug-memory", hotplug_mem_size); 2199 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 2200 &spapr->hotplug_memory.mr); 2201 } 2202 2203 if (smc->dr_lmb_enabled) { 2204 spapr_create_lmb_dr_connectors(spapr); 2205 } 2206 2207 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2208 if (!filename) { 2209 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2210 exit(1); 2211 } 2212 spapr->rtas_size = get_image_size(filename); 2213 if (spapr->rtas_size < 0) { 2214 error_report("Could not get size of LPAR rtas '%s'", filename); 2215 exit(1); 2216 } 2217 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2218 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2219 error_report("Could not load LPAR rtas '%s'", filename); 2220 exit(1); 2221 } 2222 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2223 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2224 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2225 exit(1); 2226 } 2227 g_free(filename); 2228 2229 /* Set up RTAS event infrastructure */ 2230 spapr_events_init(spapr); 2231 2232 /* Set up the RTC RTAS interfaces */ 2233 spapr_rtc_create(spapr); 2234 2235 /* Set up VIO bus */ 2236 spapr->vio_bus = spapr_vio_bus_init(); 2237 2238 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 2239 if (serial_hds[i]) { 2240 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 2241 } 2242 } 2243 2244 /* We always have at least the nvram device on VIO */ 2245 spapr_create_nvram(spapr); 2246 2247 /* Set up PCI */ 2248 spapr_pci_rtas_init(); 2249 2250 phb = spapr_create_phb(spapr, 0); 2251 2252 for (i = 0; i < nb_nics; i++) { 2253 NICInfo *nd = &nd_table[i]; 2254 2255 if (!nd->model) { 2256 nd->model = g_strdup("ibmveth"); 2257 } 2258 2259 if (strcmp(nd->model, "ibmveth") == 0) { 2260 spapr_vlan_create(spapr->vio_bus, nd); 2261 } else { 2262 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2263 } 2264 } 2265 2266 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2267 spapr_vscsi_create(spapr->vio_bus); 2268 } 2269 2270 /* Graphics */ 2271 if (spapr_vga_init(phb->bus, &error_fatal)) { 2272 spapr->has_graphics = true; 2273 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2274 } 2275 2276 if (machine->usb) { 2277 if (smc->use_ohci_by_default) { 2278 pci_create_simple(phb->bus, -1, "pci-ohci"); 2279 } else { 2280 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2281 } 2282 2283 if (spapr->has_graphics) { 2284 USBBus *usb_bus = usb_bus_find(-1); 2285 2286 usb_create_simple(usb_bus, "usb-kbd"); 2287 usb_create_simple(usb_bus, "usb-mouse"); 2288 } 2289 } 2290 2291 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 2292 error_report( 2293 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2294 MIN_RMA_SLOF); 2295 exit(1); 2296 } 2297 2298 if (kernel_filename) { 2299 uint64_t lowaddr = 0; 2300 2301 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2302 NULL, NULL, &lowaddr, NULL, 1, 2303 PPC_ELF_MACHINE, 0, 0); 2304 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2305 spapr->kernel_size = load_elf(kernel_filename, 2306 translate_kernel_address, NULL, NULL, 2307 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2308 0, 0); 2309 spapr->kernel_le = spapr->kernel_size > 0; 2310 } 2311 if (spapr->kernel_size < 0) { 2312 error_report("error loading %s: %s", kernel_filename, 2313 load_elf_strerror(spapr->kernel_size)); 2314 exit(1); 2315 } 2316 2317 /* load initrd */ 2318 if (initrd_filename) { 2319 /* Try to locate the initrd in the gap between the kernel 2320 * and the firmware. Add a bit of space just in case 2321 */ 2322 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2323 + 0x1ffff) & ~0xffff; 2324 spapr->initrd_size = load_image_targphys(initrd_filename, 2325 spapr->initrd_base, 2326 load_limit 2327 - spapr->initrd_base); 2328 if (spapr->initrd_size < 0) { 2329 error_report("could not load initial ram disk '%s'", 2330 initrd_filename); 2331 exit(1); 2332 } 2333 } 2334 } 2335 2336 if (bios_name == NULL) { 2337 bios_name = FW_FILE_NAME; 2338 } 2339 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2340 if (!filename) { 2341 error_report("Could not find LPAR firmware '%s'", bios_name); 2342 exit(1); 2343 } 2344 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2345 if (fw_size <= 0) { 2346 error_report("Could not load LPAR firmware '%s'", filename); 2347 exit(1); 2348 } 2349 g_free(filename); 2350 2351 /* FIXME: Should register things through the MachineState's qdev 2352 * interface, this is a legacy from the sPAPREnvironment structure 2353 * which predated MachineState but had a similar function */ 2354 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2355 register_savevm_live(NULL, "spapr/htab", -1, 1, 2356 &savevm_htab_handlers, spapr); 2357 2358 /* used by RTAS */ 2359 QTAILQ_INIT(&spapr->ccs_list); 2360 qemu_register_reset(spapr_ccs_reset_hook, spapr); 2361 2362 qemu_register_boot_set(spapr_boot_set, spapr); 2363 2364 if (kvm_enabled()) { 2365 /* to stop and start vmclock */ 2366 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2367 &spapr->tb); 2368 2369 kvmppc_spapr_enable_inkernel_multitce(); 2370 } 2371 } 2372 2373 static int spapr_kvm_type(const char *vm_type) 2374 { 2375 if (!vm_type) { 2376 return 0; 2377 } 2378 2379 if (!strcmp(vm_type, "HV")) { 2380 return 1; 2381 } 2382 2383 if (!strcmp(vm_type, "PR")) { 2384 return 2; 2385 } 2386 2387 error_report("Unknown kvm-type specified '%s'", vm_type); 2388 exit(1); 2389 } 2390 2391 /* 2392 * Implementation of an interface to adjust firmware path 2393 * for the bootindex property handling. 2394 */ 2395 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2396 DeviceState *dev) 2397 { 2398 #define CAST(type, obj, name) \ 2399 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2400 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2401 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2402 2403 if (d) { 2404 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2405 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2406 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2407 2408 if (spapr) { 2409 /* 2410 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2411 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2412 * in the top 16 bits of the 64-bit LUN 2413 */ 2414 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2415 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2416 (uint64_t)id << 48); 2417 } else if (virtio) { 2418 /* 2419 * We use SRP luns of the form 01000000 | (target << 8) | lun 2420 * in the top 32 bits of the 64-bit LUN 2421 * Note: the quote above is from SLOF and it is wrong, 2422 * the actual binding is: 2423 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2424 */ 2425 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2426 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2427 (uint64_t)id << 32); 2428 } else if (usb) { 2429 /* 2430 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2431 * in the top 32 bits of the 64-bit LUN 2432 */ 2433 unsigned usb_port = atoi(usb->port->path); 2434 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2435 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2436 (uint64_t)id << 32); 2437 } 2438 } 2439 2440 /* 2441 * SLOF probes the USB devices, and if it recognizes that the device is a 2442 * storage device, it changes its name to "storage" instead of "usb-host", 2443 * and additionally adds a child node for the SCSI LUN, so the correct 2444 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2445 */ 2446 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2447 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2448 if (usb_host_dev_is_scsi_storage(usbdev)) { 2449 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2450 } 2451 } 2452 2453 if (phb) { 2454 /* Replace "pci" with "pci@800000020000000" */ 2455 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2456 } 2457 2458 return NULL; 2459 } 2460 2461 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2462 { 2463 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2464 2465 return g_strdup(spapr->kvm_type); 2466 } 2467 2468 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2469 { 2470 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2471 2472 g_free(spapr->kvm_type); 2473 spapr->kvm_type = g_strdup(value); 2474 } 2475 2476 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2477 { 2478 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2479 2480 return spapr->use_hotplug_event_source; 2481 } 2482 2483 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2484 Error **errp) 2485 { 2486 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2487 2488 spapr->use_hotplug_event_source = value; 2489 } 2490 2491 static void spapr_machine_initfn(Object *obj) 2492 { 2493 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2494 2495 spapr->htab_fd = -1; 2496 spapr->use_hotplug_event_source = true; 2497 object_property_add_str(obj, "kvm-type", 2498 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2499 object_property_set_description(obj, "kvm-type", 2500 "Specifies the KVM virtualization mode (HV, PR)", 2501 NULL); 2502 object_property_add_bool(obj, "modern-hotplug-events", 2503 spapr_get_modern_hotplug_events, 2504 spapr_set_modern_hotplug_events, 2505 NULL); 2506 object_property_set_description(obj, "modern-hotplug-events", 2507 "Use dedicated hotplug event mechanism in" 2508 " place of standard EPOW events when possible" 2509 " (required for memory hot-unplug support)", 2510 NULL); 2511 } 2512 2513 static void spapr_machine_finalizefn(Object *obj) 2514 { 2515 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2516 2517 g_free(spapr->kvm_type); 2518 } 2519 2520 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 2521 { 2522 cpu_synchronize_state(cs); 2523 ppc_cpu_do_system_reset(cs); 2524 } 2525 2526 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2527 { 2528 CPUState *cs; 2529 2530 CPU_FOREACH(cs) { 2531 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 2532 } 2533 } 2534 2535 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2536 uint32_t node, bool dedicated_hp_event_source, 2537 Error **errp) 2538 { 2539 sPAPRDRConnector *drc; 2540 sPAPRDRConnectorClass *drck; 2541 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2542 int i, fdt_offset, fdt_size; 2543 void *fdt; 2544 uint64_t addr = addr_start; 2545 2546 for (i = 0; i < nr_lmbs; i++) { 2547 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2548 addr/SPAPR_MEMORY_BLOCK_SIZE); 2549 g_assert(drc); 2550 2551 fdt = create_device_tree(&fdt_size); 2552 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2553 SPAPR_MEMORY_BLOCK_SIZE); 2554 2555 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2556 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); 2557 addr += SPAPR_MEMORY_BLOCK_SIZE; 2558 if (!dev->hotplugged) { 2559 /* guests expect coldplugged LMBs to be pre-allocated */ 2560 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); 2561 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); 2562 } 2563 } 2564 /* send hotplug notification to the 2565 * guest only in case of hotplugged memory 2566 */ 2567 if (dev->hotplugged) { 2568 if (dedicated_hp_event_source) { 2569 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2570 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2571 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2572 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2573 nr_lmbs, 2574 drck->get_index(drc)); 2575 } else { 2576 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 2577 nr_lmbs); 2578 } 2579 } 2580 } 2581 2582 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2583 uint32_t node, Error **errp) 2584 { 2585 Error *local_err = NULL; 2586 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2587 PCDIMMDevice *dimm = PC_DIMM(dev); 2588 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2589 MemoryRegion *mr = ddc->get_memory_region(dimm); 2590 uint64_t align = memory_region_get_alignment(mr); 2591 uint64_t size = memory_region_size(mr); 2592 uint64_t addr; 2593 char *mem_dev; 2594 2595 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 2596 error_setg(&local_err, "Hotplugged memory size must be a multiple of " 2597 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); 2598 goto out; 2599 } 2600 2601 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); 2602 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { 2603 error_setg(&local_err, "Memory backend has bad page size. " 2604 "Use 'memory-backend-file' with correct mem-path."); 2605 goto out; 2606 } 2607 2608 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 2609 if (local_err) { 2610 goto out; 2611 } 2612 2613 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2614 if (local_err) { 2615 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2616 goto out; 2617 } 2618 2619 spapr_add_lmbs(dev, addr, size, node, 2620 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 2621 &error_abort); 2622 2623 out: 2624 error_propagate(errp, local_err); 2625 } 2626 2627 typedef struct sPAPRDIMMState { 2628 uint32_t nr_lmbs; 2629 } sPAPRDIMMState; 2630 2631 static void spapr_lmb_release(DeviceState *dev, void *opaque) 2632 { 2633 sPAPRDIMMState *ds = (sPAPRDIMMState *)opaque; 2634 HotplugHandler *hotplug_ctrl; 2635 2636 if (--ds->nr_lmbs) { 2637 return; 2638 } 2639 2640 g_free(ds); 2641 2642 /* 2643 * Now that all the LMBs have been removed by the guest, call the 2644 * pc-dimm unplug handler to cleanup up the pc-dimm device. 2645 */ 2646 hotplug_ctrl = qdev_get_hotplug_handler(dev); 2647 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2648 } 2649 2650 static void spapr_del_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2651 Error **errp) 2652 { 2653 sPAPRDRConnector *drc; 2654 sPAPRDRConnectorClass *drck; 2655 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 2656 int i; 2657 sPAPRDIMMState *ds = g_malloc0(sizeof(sPAPRDIMMState)); 2658 uint64_t addr = addr_start; 2659 2660 ds->nr_lmbs = nr_lmbs; 2661 for (i = 0; i < nr_lmbs; i++) { 2662 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2663 addr / SPAPR_MEMORY_BLOCK_SIZE); 2664 g_assert(drc); 2665 2666 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2667 drck->detach(drc, dev, spapr_lmb_release, ds, errp); 2668 addr += SPAPR_MEMORY_BLOCK_SIZE; 2669 } 2670 2671 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2672 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2673 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2674 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2675 nr_lmbs, 2676 drck->get_index(drc)); 2677 } 2678 2679 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2680 Error **errp) 2681 { 2682 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2683 PCDIMMDevice *dimm = PC_DIMM(dev); 2684 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2685 MemoryRegion *mr = ddc->get_memory_region(dimm); 2686 2687 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2688 object_unparent(OBJECT(dev)); 2689 } 2690 2691 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 2692 DeviceState *dev, Error **errp) 2693 { 2694 Error *local_err = NULL; 2695 PCDIMMDevice *dimm = PC_DIMM(dev); 2696 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2697 MemoryRegion *mr = ddc->get_memory_region(dimm); 2698 uint64_t size = memory_region_size(mr); 2699 uint64_t addr; 2700 2701 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2702 if (local_err) { 2703 goto out; 2704 } 2705 2706 spapr_del_lmbs(dev, addr, size, &error_abort); 2707 out: 2708 error_propagate(errp, local_err); 2709 } 2710 2711 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 2712 sPAPRMachineState *spapr) 2713 { 2714 PowerPCCPU *cpu = POWERPC_CPU(cs); 2715 DeviceClass *dc = DEVICE_GET_CLASS(cs); 2716 int id = ppc_get_vcpu_dt_id(cpu); 2717 void *fdt; 2718 int offset, fdt_size; 2719 char *nodename; 2720 2721 fdt = create_device_tree(&fdt_size); 2722 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 2723 offset = fdt_add_subnode(fdt, 0, nodename); 2724 2725 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 2726 g_free(nodename); 2727 2728 *fdt_offset = offset; 2729 return fdt; 2730 } 2731 2732 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2733 Error **errp) 2734 { 2735 MachineState *ms = MACHINE(qdev_get_machine()); 2736 CPUCore *cc = CPU_CORE(dev); 2737 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 2738 2739 core_slot->cpu = NULL; 2740 object_unparent(OBJECT(dev)); 2741 } 2742 2743 static void spapr_core_release(DeviceState *dev, void *opaque) 2744 { 2745 HotplugHandler *hotplug_ctrl; 2746 2747 hotplug_ctrl = qdev_get_hotplug_handler(dev); 2748 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2749 } 2750 2751 static 2752 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 2753 Error **errp) 2754 { 2755 int index; 2756 sPAPRDRConnector *drc; 2757 sPAPRDRConnectorClass *drck; 2758 Error *local_err = NULL; 2759 CPUCore *cc = CPU_CORE(dev); 2760 int smt = kvmppc_smt_threads(); 2761 2762 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 2763 error_setg(errp, "Unable to find CPU core with core-id: %d", 2764 cc->core_id); 2765 return; 2766 } 2767 if (index == 0) { 2768 error_setg(errp, "Boot CPU core may not be unplugged"); 2769 return; 2770 } 2771 2772 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt); 2773 g_assert(drc); 2774 2775 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2776 drck->detach(drc, dev, spapr_core_release, NULL, &local_err); 2777 if (local_err) { 2778 error_propagate(errp, local_err); 2779 return; 2780 } 2781 2782 spapr_hotplug_req_remove_by_index(drc); 2783 } 2784 2785 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2786 Error **errp) 2787 { 2788 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 2789 MachineClass *mc = MACHINE_GET_CLASS(spapr); 2790 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 2791 CPUCore *cc = CPU_CORE(dev); 2792 CPUState *cs = CPU(core->threads); 2793 sPAPRDRConnector *drc; 2794 Error *local_err = NULL; 2795 void *fdt = NULL; 2796 int fdt_offset = 0; 2797 int smt = kvmppc_smt_threads(); 2798 CPUArchId *core_slot; 2799 int index; 2800 2801 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 2802 if (!core_slot) { 2803 error_setg(errp, "Unable to find CPU core with core-id: %d", 2804 cc->core_id); 2805 return; 2806 } 2807 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt); 2808 2809 g_assert(drc || !mc->has_hotpluggable_cpus); 2810 2811 /* 2812 * Setup CPU DT entries only for hotplugged CPUs. For boot time or 2813 * coldplugged CPUs DT entries are setup in spapr_build_fdt(). 2814 */ 2815 if (dev->hotplugged) { 2816 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 2817 } 2818 2819 if (drc) { 2820 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2821 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err); 2822 if (local_err) { 2823 g_free(fdt); 2824 error_propagate(errp, local_err); 2825 return; 2826 } 2827 } 2828 2829 if (dev->hotplugged) { 2830 /* 2831 * Send hotplug notification interrupt to the guest only in case 2832 * of hotplugged CPUs. 2833 */ 2834 spapr_hotplug_req_add_by_index(drc); 2835 } else { 2836 /* 2837 * Set the right DRC states for cold plugged CPU. 2838 */ 2839 if (drc) { 2840 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2841 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); 2842 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); 2843 } 2844 } 2845 core_slot->cpu = OBJECT(dev); 2846 } 2847 2848 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2849 Error **errp) 2850 { 2851 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 2852 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 2853 Error *local_err = NULL; 2854 CPUCore *cc = CPU_CORE(dev); 2855 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model); 2856 const char *type = object_get_typename(OBJECT(dev)); 2857 CPUArchId *core_slot; 2858 int index; 2859 2860 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 2861 error_setg(&local_err, "CPU hotplug not supported for this machine"); 2862 goto out; 2863 } 2864 2865 if (strcmp(base_core_type, type)) { 2866 error_setg(&local_err, "CPU core type should be %s", base_core_type); 2867 goto out; 2868 } 2869 2870 if (cc->core_id % smp_threads) { 2871 error_setg(&local_err, "invalid core id %d", cc->core_id); 2872 goto out; 2873 } 2874 2875 if (cc->nr_threads != smp_threads) { 2876 error_setg(errp, "invalid nr-threads %d, must be %d", 2877 cc->nr_threads, smp_threads); 2878 return; 2879 } 2880 2881 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 2882 if (!core_slot) { 2883 error_setg(&local_err, "core id %d out of range", cc->core_id); 2884 goto out; 2885 } 2886 2887 if (core_slot->cpu) { 2888 error_setg(&local_err, "core %d already populated", cc->core_id); 2889 goto out; 2890 } 2891 2892 out: 2893 g_free(base_core_type); 2894 error_propagate(errp, local_err); 2895 } 2896 2897 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 2898 DeviceState *dev, Error **errp) 2899 { 2900 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 2901 2902 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2903 int node; 2904 2905 if (!smc->dr_lmb_enabled) { 2906 error_setg(errp, "Memory hotplug not supported for this machine"); 2907 return; 2908 } 2909 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 2910 if (*errp) { 2911 return; 2912 } 2913 if (node < 0 || node >= MAX_NODES) { 2914 error_setg(errp, "Invaild node %d", node); 2915 return; 2916 } 2917 2918 /* 2919 * Currently PowerPC kernel doesn't allow hot-adding memory to 2920 * memory-less node, but instead will silently add the memory 2921 * to the first node that has some memory. This causes two 2922 * unexpected behaviours for the user. 2923 * 2924 * - Memory gets hotplugged to a different node than what the user 2925 * specified. 2926 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 2927 * to memory-less node, a reboot will set things accordingly 2928 * and the previously hotplugged memory now ends in the right node. 2929 * This appears as if some memory moved from one node to another. 2930 * 2931 * So until kernel starts supporting memory hotplug to memory-less 2932 * nodes, just prevent such attempts upfront in QEMU. 2933 */ 2934 if (nb_numa_nodes && !numa_info[node].node_mem) { 2935 error_setg(errp, "Can't hotplug memory to memory-less node %d", 2936 node); 2937 return; 2938 } 2939 2940 spapr_memory_plug(hotplug_dev, dev, node, errp); 2941 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2942 spapr_core_plug(hotplug_dev, dev, errp); 2943 } 2944 } 2945 2946 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 2947 DeviceState *dev, Error **errp) 2948 { 2949 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 2950 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 2951 2952 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2953 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 2954 spapr_memory_unplug(hotplug_dev, dev, errp); 2955 } else { 2956 error_setg(errp, "Memory hot unplug not supported for this guest"); 2957 } 2958 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2959 if (!mc->has_hotpluggable_cpus) { 2960 error_setg(errp, "CPU hot unplug not supported on this machine"); 2961 return; 2962 } 2963 spapr_core_unplug(hotplug_dev, dev, errp); 2964 } 2965 } 2966 2967 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 2968 DeviceState *dev, Error **errp) 2969 { 2970 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 2971 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 2972 2973 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2974 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 2975 spapr_memory_unplug_request(hotplug_dev, dev, errp); 2976 } else { 2977 /* NOTE: this means there is a window after guest reset, prior to 2978 * CAS negotiation, where unplug requests will fail due to the 2979 * capability not being detected yet. This is a bit different than 2980 * the case with PCI unplug, where the events will be queued and 2981 * eventually handled by the guest after boot 2982 */ 2983 error_setg(errp, "Memory hot unplug not supported for this guest"); 2984 } 2985 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2986 if (!mc->has_hotpluggable_cpus) { 2987 error_setg(errp, "CPU hot unplug not supported on this machine"); 2988 return; 2989 } 2990 spapr_core_unplug_request(hotplug_dev, dev, errp); 2991 } 2992 } 2993 2994 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 2995 DeviceState *dev, Error **errp) 2996 { 2997 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2998 spapr_core_pre_plug(hotplug_dev, dev, errp); 2999 } 3000 } 3001 3002 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 3003 DeviceState *dev) 3004 { 3005 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3006 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3007 return HOTPLUG_HANDLER(machine); 3008 } 3009 return NULL; 3010 } 3011 3012 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index) 3013 { 3014 /* Allocate to NUMA nodes on a "socket" basis (not that concept of 3015 * socket means much for the paravirtualized PAPR platform) */ 3016 return cpu_index / smp_threads / smp_cores; 3017 } 3018 3019 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 3020 { 3021 int i; 3022 int spapr_max_cores = max_cpus / smp_threads; 3023 MachineClass *mc = MACHINE_GET_CLASS(machine); 3024 3025 if (!mc->has_hotpluggable_cpus) { 3026 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 3027 } 3028 if (machine->possible_cpus) { 3029 assert(machine->possible_cpus->len == spapr_max_cores); 3030 return machine->possible_cpus; 3031 } 3032 3033 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 3034 sizeof(CPUArchId) * spapr_max_cores); 3035 machine->possible_cpus->len = spapr_max_cores; 3036 for (i = 0; i < machine->possible_cpus->len; i++) { 3037 int core_id = i * smp_threads; 3038 3039 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 3040 machine->possible_cpus->cpus[i].arch_id = core_id; 3041 machine->possible_cpus->cpus[i].props.has_core_id = true; 3042 machine->possible_cpus->cpus[i].props.core_id = core_id; 3043 /* TODO: add 'has_node/node' here to describe 3044 to which node core belongs */ 3045 } 3046 return machine->possible_cpus; 3047 } 3048 3049 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 3050 uint64_t *buid, hwaddr *pio, 3051 hwaddr *mmio32, hwaddr *mmio64, 3052 unsigned n_dma, uint32_t *liobns, Error **errp) 3053 { 3054 /* 3055 * New-style PHB window placement. 3056 * 3057 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 3058 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 3059 * windows. 3060 * 3061 * Some guest kernels can't work with MMIO windows above 1<<46 3062 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 3063 * 3064 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 3065 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 3066 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 3067 * 1TiB 64-bit MMIO windows for each PHB. 3068 */ 3069 const uint64_t base_buid = 0x800000020000000ULL; 3070 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 3071 SPAPR_PCI_MEM64_WIN_SIZE - 1) 3072 int i; 3073 3074 /* Sanity check natural alignments */ 3075 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3076 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3077 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 3078 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 3079 /* Sanity check bounds */ 3080 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 3081 SPAPR_PCI_MEM32_WIN_SIZE); 3082 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 3083 SPAPR_PCI_MEM64_WIN_SIZE); 3084 3085 if (index >= SPAPR_MAX_PHBS) { 3086 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 3087 SPAPR_MAX_PHBS - 1); 3088 return; 3089 } 3090 3091 *buid = base_buid + index; 3092 for (i = 0; i < n_dma; ++i) { 3093 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3094 } 3095 3096 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 3097 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 3098 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 3099 } 3100 3101 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 3102 { 3103 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3104 3105 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 3106 } 3107 3108 static void spapr_ics_resend(XICSFabric *dev) 3109 { 3110 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3111 3112 ics_resend(spapr->ics); 3113 } 3114 3115 static ICPState *spapr_icp_get(XICSFabric *xi, int server) 3116 { 3117 sPAPRMachineState *spapr = SPAPR_MACHINE(xi); 3118 3119 return (server < spapr->nr_servers) ? &spapr->icps[server] : NULL; 3120 } 3121 3122 static void spapr_pic_print_info(InterruptStatsProvider *obj, 3123 Monitor *mon) 3124 { 3125 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3126 int i; 3127 3128 for (i = 0; i < spapr->nr_servers; i++) { 3129 icp_pic_print_info(&spapr->icps[i], mon); 3130 } 3131 3132 ics_pic_print_info(spapr->ics, mon); 3133 } 3134 3135 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3136 { 3137 MachineClass *mc = MACHINE_CLASS(oc); 3138 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3139 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3140 NMIClass *nc = NMI_CLASS(oc); 3141 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3142 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3143 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3144 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 3145 3146 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3147 3148 /* 3149 * We set up the default / latest behaviour here. The class_init 3150 * functions for the specific versioned machine types can override 3151 * these details for backwards compatibility 3152 */ 3153 mc->init = ppc_spapr_init; 3154 mc->reset = ppc_spapr_reset; 3155 mc->block_default_type = IF_SCSI; 3156 mc->max_cpus = 1024; 3157 mc->no_parallel = 1; 3158 mc->default_boot_order = ""; 3159 mc->default_ram_size = 512 * M_BYTE; 3160 mc->kvm_type = spapr_kvm_type; 3161 mc->has_dynamic_sysbus = true; 3162 mc->pci_allow_0_address = true; 3163 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3164 hc->pre_plug = spapr_machine_device_pre_plug; 3165 hc->plug = spapr_machine_device_plug; 3166 hc->unplug = spapr_machine_device_unplug; 3167 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id; 3168 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3169 hc->unplug_request = spapr_machine_device_unplug_request; 3170 3171 smc->dr_lmb_enabled = true; 3172 smc->tcg_default_cpu = "POWER8"; 3173 mc->has_hotpluggable_cpus = true; 3174 fwc->get_dev_path = spapr_get_fw_dev_path; 3175 nc->nmi_monitor_handler = spapr_nmi; 3176 smc->phb_placement = spapr_phb_placement; 3177 vhc->hypercall = emulate_spapr_hypercall; 3178 vhc->hpt_mask = spapr_hpt_mask; 3179 vhc->map_hptes = spapr_map_hptes; 3180 vhc->unmap_hptes = spapr_unmap_hptes; 3181 vhc->store_hpte = spapr_store_hpte; 3182 vhc->get_patbe = spapr_get_patbe; 3183 xic->ics_get = spapr_ics_get; 3184 xic->ics_resend = spapr_ics_resend; 3185 xic->icp_get = spapr_icp_get; 3186 ispc->print_info = spapr_pic_print_info; 3187 /* Force NUMA node memory size to be a multiple of 3188 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 3189 * in which LMBs are represented and hot-added 3190 */ 3191 mc->numa_mem_align_shift = 28; 3192 } 3193 3194 static const TypeInfo spapr_machine_info = { 3195 .name = TYPE_SPAPR_MACHINE, 3196 .parent = TYPE_MACHINE, 3197 .abstract = true, 3198 .instance_size = sizeof(sPAPRMachineState), 3199 .instance_init = spapr_machine_initfn, 3200 .instance_finalize = spapr_machine_finalizefn, 3201 .class_size = sizeof(sPAPRMachineClass), 3202 .class_init = spapr_machine_class_init, 3203 .interfaces = (InterfaceInfo[]) { 3204 { TYPE_FW_PATH_PROVIDER }, 3205 { TYPE_NMI }, 3206 { TYPE_HOTPLUG_HANDLER }, 3207 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 3208 { TYPE_XICS_FABRIC }, 3209 { TYPE_INTERRUPT_STATS_PROVIDER }, 3210 { } 3211 }, 3212 }; 3213 3214 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 3215 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 3216 void *data) \ 3217 { \ 3218 MachineClass *mc = MACHINE_CLASS(oc); \ 3219 spapr_machine_##suffix##_class_options(mc); \ 3220 if (latest) { \ 3221 mc->alias = "pseries"; \ 3222 mc->is_default = 1; \ 3223 } \ 3224 } \ 3225 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 3226 { \ 3227 MachineState *machine = MACHINE(obj); \ 3228 spapr_machine_##suffix##_instance_options(machine); \ 3229 } \ 3230 static const TypeInfo spapr_machine_##suffix##_info = { \ 3231 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 3232 .parent = TYPE_SPAPR_MACHINE, \ 3233 .class_init = spapr_machine_##suffix##_class_init, \ 3234 .instance_init = spapr_machine_##suffix##_instance_init, \ 3235 }; \ 3236 static void spapr_machine_register_##suffix(void) \ 3237 { \ 3238 type_register(&spapr_machine_##suffix##_info); \ 3239 } \ 3240 type_init(spapr_machine_register_##suffix) 3241 3242 /* 3243 * pseries-2.10 3244 */ 3245 static void spapr_machine_2_10_instance_options(MachineState *machine) 3246 { 3247 } 3248 3249 static void spapr_machine_2_10_class_options(MachineClass *mc) 3250 { 3251 /* Defaults for the latest behaviour inherited from the base class */ 3252 } 3253 3254 DEFINE_SPAPR_MACHINE(2_10, "2.10", true); 3255 3256 /* 3257 * pseries-2.9 3258 */ 3259 #define SPAPR_COMPAT_2_9 \ 3260 HW_COMPAT_2_9 3261 3262 static void spapr_machine_2_9_instance_options(MachineState *machine) 3263 { 3264 spapr_machine_2_10_instance_options(machine); 3265 } 3266 3267 static void spapr_machine_2_9_class_options(MachineClass *mc) 3268 { 3269 spapr_machine_2_10_class_options(mc); 3270 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); 3271 } 3272 3273 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 3274 3275 /* 3276 * pseries-2.8 3277 */ 3278 #define SPAPR_COMPAT_2_8 \ 3279 HW_COMPAT_2_8 \ 3280 { \ 3281 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3282 .property = "pcie-extended-configuration-space", \ 3283 .value = "off", \ 3284 }, 3285 3286 static void spapr_machine_2_8_instance_options(MachineState *machine) 3287 { 3288 spapr_machine_2_9_instance_options(machine); 3289 } 3290 3291 static void spapr_machine_2_8_class_options(MachineClass *mc) 3292 { 3293 spapr_machine_2_9_class_options(mc); 3294 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 3295 mc->numa_mem_align_shift = 23; 3296 } 3297 3298 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 3299 3300 /* 3301 * pseries-2.7 3302 */ 3303 #define SPAPR_COMPAT_2_7 \ 3304 HW_COMPAT_2_7 \ 3305 { \ 3306 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3307 .property = "mem_win_size", \ 3308 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 3309 }, \ 3310 { \ 3311 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3312 .property = "mem64_win_size", \ 3313 .value = "0", \ 3314 }, \ 3315 { \ 3316 .driver = TYPE_POWERPC_CPU, \ 3317 .property = "pre-2.8-migration", \ 3318 .value = "on", \ 3319 }, \ 3320 { \ 3321 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3322 .property = "pre-2.8-migration", \ 3323 .value = "on", \ 3324 }, 3325 3326 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 3327 uint64_t *buid, hwaddr *pio, 3328 hwaddr *mmio32, hwaddr *mmio64, 3329 unsigned n_dma, uint32_t *liobns, Error **errp) 3330 { 3331 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 3332 const uint64_t base_buid = 0x800000020000000ULL; 3333 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 3334 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 3335 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 3336 const uint32_t max_index = 255; 3337 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 3338 3339 uint64_t ram_top = MACHINE(spapr)->ram_size; 3340 hwaddr phb0_base, phb_base; 3341 int i; 3342 3343 /* Do we have hotpluggable memory? */ 3344 if (MACHINE(spapr)->maxram_size > ram_top) { 3345 /* Can't just use maxram_size, because there may be an 3346 * alignment gap between normal and hotpluggable memory 3347 * regions */ 3348 ram_top = spapr->hotplug_memory.base + 3349 memory_region_size(&spapr->hotplug_memory.mr); 3350 } 3351 3352 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 3353 3354 if (index > max_index) { 3355 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 3356 max_index); 3357 return; 3358 } 3359 3360 *buid = base_buid + index; 3361 for (i = 0; i < n_dma; ++i) { 3362 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3363 } 3364 3365 phb_base = phb0_base + index * phb_spacing; 3366 *pio = phb_base + pio_offset; 3367 *mmio32 = phb_base + mmio_offset; 3368 /* 3369 * We don't set the 64-bit MMIO window, relying on the PHB's 3370 * fallback behaviour of automatically splitting a large "32-bit" 3371 * window into contiguous 32-bit and 64-bit windows 3372 */ 3373 } 3374 3375 static void spapr_machine_2_7_instance_options(MachineState *machine) 3376 { 3377 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 3378 3379 spapr_machine_2_8_instance_options(machine); 3380 spapr->use_hotplug_event_source = false; 3381 } 3382 3383 static void spapr_machine_2_7_class_options(MachineClass *mc) 3384 { 3385 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3386 3387 spapr_machine_2_8_class_options(mc); 3388 smc->tcg_default_cpu = "POWER7"; 3389 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 3390 smc->phb_placement = phb_placement_2_7; 3391 } 3392 3393 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 3394 3395 /* 3396 * pseries-2.6 3397 */ 3398 #define SPAPR_COMPAT_2_6 \ 3399 HW_COMPAT_2_6 \ 3400 { \ 3401 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3402 .property = "ddw",\ 3403 .value = stringify(off),\ 3404 }, 3405 3406 static void spapr_machine_2_6_instance_options(MachineState *machine) 3407 { 3408 spapr_machine_2_7_instance_options(machine); 3409 } 3410 3411 static void spapr_machine_2_6_class_options(MachineClass *mc) 3412 { 3413 spapr_machine_2_7_class_options(mc); 3414 mc->has_hotpluggable_cpus = false; 3415 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 3416 } 3417 3418 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 3419 3420 /* 3421 * pseries-2.5 3422 */ 3423 #define SPAPR_COMPAT_2_5 \ 3424 HW_COMPAT_2_5 \ 3425 { \ 3426 .driver = "spapr-vlan", \ 3427 .property = "use-rx-buffer-pools", \ 3428 .value = "off", \ 3429 }, 3430 3431 static void spapr_machine_2_5_instance_options(MachineState *machine) 3432 { 3433 spapr_machine_2_6_instance_options(machine); 3434 } 3435 3436 static void spapr_machine_2_5_class_options(MachineClass *mc) 3437 { 3438 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3439 3440 spapr_machine_2_6_class_options(mc); 3441 smc->use_ohci_by_default = true; 3442 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 3443 } 3444 3445 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 3446 3447 /* 3448 * pseries-2.4 3449 */ 3450 #define SPAPR_COMPAT_2_4 \ 3451 HW_COMPAT_2_4 3452 3453 static void spapr_machine_2_4_instance_options(MachineState *machine) 3454 { 3455 spapr_machine_2_5_instance_options(machine); 3456 } 3457 3458 static void spapr_machine_2_4_class_options(MachineClass *mc) 3459 { 3460 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3461 3462 spapr_machine_2_5_class_options(mc); 3463 smc->dr_lmb_enabled = false; 3464 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 3465 } 3466 3467 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 3468 3469 /* 3470 * pseries-2.3 3471 */ 3472 #define SPAPR_COMPAT_2_3 \ 3473 HW_COMPAT_2_3 \ 3474 {\ 3475 .driver = "spapr-pci-host-bridge",\ 3476 .property = "dynamic-reconfiguration",\ 3477 .value = "off",\ 3478 }, 3479 3480 static void spapr_machine_2_3_instance_options(MachineState *machine) 3481 { 3482 spapr_machine_2_4_instance_options(machine); 3483 savevm_skip_section_footers(); 3484 global_state_set_optional(); 3485 savevm_skip_configuration(); 3486 } 3487 3488 static void spapr_machine_2_3_class_options(MachineClass *mc) 3489 { 3490 spapr_machine_2_4_class_options(mc); 3491 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 3492 } 3493 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 3494 3495 /* 3496 * pseries-2.2 3497 */ 3498 3499 #define SPAPR_COMPAT_2_2 \ 3500 HW_COMPAT_2_2 \ 3501 {\ 3502 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3503 .property = "mem_win_size",\ 3504 .value = "0x20000000",\ 3505 }, 3506 3507 static void spapr_machine_2_2_instance_options(MachineState *machine) 3508 { 3509 spapr_machine_2_3_instance_options(machine); 3510 machine->suppress_vmdesc = true; 3511 } 3512 3513 static void spapr_machine_2_2_class_options(MachineClass *mc) 3514 { 3515 spapr_machine_2_3_class_options(mc); 3516 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 3517 } 3518 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 3519 3520 /* 3521 * pseries-2.1 3522 */ 3523 #define SPAPR_COMPAT_2_1 \ 3524 HW_COMPAT_2_1 3525 3526 static void spapr_machine_2_1_instance_options(MachineState *machine) 3527 { 3528 spapr_machine_2_2_instance_options(machine); 3529 } 3530 3531 static void spapr_machine_2_1_class_options(MachineClass *mc) 3532 { 3533 spapr_machine_2_2_class_options(mc); 3534 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 3535 } 3536 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 3537 3538 static void spapr_machine_register_types(void) 3539 { 3540 type_register_static(&spapr_machine_info); 3541 } 3542 3543 type_init(spapr_machine_register_types) 3544