1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/numa.h" 31 #include "hw/hw.h" 32 #include "qemu/log.h" 33 #include "hw/fw-path-provider.h" 34 #include "elf.h" 35 #include "net/net.h" 36 #include "sysemu/device_tree.h" 37 #include "sysemu/block-backend.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/hw_accel.h" 40 #include "kvm_ppc.h" 41 #include "migration/migration.h" 42 #include "mmu-hash64.h" 43 #include "mmu-book3s-v3.h" 44 #include "qom/cpu.h" 45 46 #include "hw/boards.h" 47 #include "hw/ppc/ppc.h" 48 #include "hw/loader.h" 49 50 #include "hw/ppc/fdt.h" 51 #include "hw/ppc/spapr.h" 52 #include "hw/ppc/spapr_vio.h" 53 #include "hw/pci-host/spapr.h" 54 #include "hw/ppc/xics.h" 55 #include "hw/pci/msi.h" 56 57 #include "hw/pci/pci.h" 58 #include "hw/scsi/scsi.h" 59 #include "hw/virtio/virtio-scsi.h" 60 #include "hw/virtio/vhost-scsi-common.h" 61 62 #include "exec/address-spaces.h" 63 #include "hw/usb.h" 64 #include "qemu/config-file.h" 65 #include "qemu/error-report.h" 66 #include "trace.h" 67 #include "hw/nmi.h" 68 #include "hw/intc/intc.h" 69 70 #include "hw/compat.h" 71 #include "qemu/cutils.h" 72 #include "hw/ppc/spapr_cpu_core.h" 73 #include "qmp-commands.h" 74 75 #include <libfdt.h> 76 77 /* SLOF memory layout: 78 * 79 * SLOF raw image loaded at 0, copies its romfs right below the flat 80 * device-tree, then position SLOF itself 31M below that 81 * 82 * So we set FW_OVERHEAD to 40MB which should account for all of that 83 * and more 84 * 85 * We load our kernel at 4M, leaving space for SLOF initial image 86 */ 87 #define FDT_MAX_SIZE 0x100000 88 #define RTAS_MAX_SIZE 0x10000 89 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 90 #define FW_MAX_SIZE 0x400000 91 #define FW_FILE_NAME "slof.bin" 92 #define FW_OVERHEAD 0x2800000 93 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 94 95 #define MIN_RMA_SLOF 128UL 96 97 #define PHANDLE_XICP 0x00001111 98 99 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 100 101 static ICSState *spapr_ics_create(sPAPRMachineState *spapr, 102 const char *type_ics, 103 int nr_irqs, Error **errp) 104 { 105 Error *local_err = NULL; 106 Object *obj; 107 108 obj = object_new(type_ics); 109 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); 110 object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr), 111 &error_abort); 112 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err); 113 if (local_err) { 114 goto error; 115 } 116 object_property_set_bool(obj, true, "realized", &local_err); 117 if (local_err) { 118 goto error; 119 } 120 121 return ICS_SIMPLE(obj); 122 123 error: 124 error_propagate(errp, local_err); 125 return NULL; 126 } 127 128 static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp) 129 { 130 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 131 132 if (kvm_enabled()) { 133 if (machine_kernel_irqchip_allowed(machine) && 134 !xics_kvm_init(spapr, errp)) { 135 spapr->icp_type = TYPE_KVM_ICP; 136 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp); 137 } 138 if (machine_kernel_irqchip_required(machine) && !spapr->ics) { 139 error_prepend(errp, "kernel_irqchip requested but unavailable: "); 140 return; 141 } 142 } 143 144 if (!spapr->ics) { 145 xics_spapr_init(spapr); 146 spapr->icp_type = TYPE_ICP; 147 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp); 148 if (!spapr->ics) { 149 return; 150 } 151 } 152 } 153 154 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 155 int smt_threads) 156 { 157 int i, ret = 0; 158 uint32_t servers_prop[smt_threads]; 159 uint32_t gservers_prop[smt_threads * 2]; 160 int index = ppc_get_vcpu_dt_id(cpu); 161 162 if (cpu->compat_pvr) { 163 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 164 if (ret < 0) { 165 return ret; 166 } 167 } 168 169 /* Build interrupt servers and gservers properties */ 170 for (i = 0; i < smt_threads; i++) { 171 servers_prop[i] = cpu_to_be32(index + i); 172 /* Hack, direct the group queues back to cpu 0 */ 173 gservers_prop[i*2] = cpu_to_be32(index + i); 174 gservers_prop[i*2 + 1] = 0; 175 } 176 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 177 servers_prop, sizeof(servers_prop)); 178 if (ret < 0) { 179 return ret; 180 } 181 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 182 gservers_prop, sizeof(gservers_prop)); 183 184 return ret; 185 } 186 187 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 188 { 189 int index = ppc_get_vcpu_dt_id(cpu); 190 uint32_t associativity[] = {cpu_to_be32(0x5), 191 cpu_to_be32(0x0), 192 cpu_to_be32(0x0), 193 cpu_to_be32(0x0), 194 cpu_to_be32(cpu->node_id), 195 cpu_to_be32(index)}; 196 197 /* Advertise NUMA via ibm,associativity */ 198 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 199 sizeof(associativity)); 200 } 201 202 /* Populate the "ibm,pa-features" property */ 203 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset, 204 bool legacy_guest) 205 { 206 uint8_t pa_features_206[] = { 6, 0, 207 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 208 uint8_t pa_features_207[] = { 24, 0, 209 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 210 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 211 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 212 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 213 uint8_t pa_features_300[] = { 66, 0, 214 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 215 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 216 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 217 /* 6: DS207 */ 218 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 219 /* 16: Vector */ 220 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 221 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 222 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 223 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 224 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 225 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 226 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 227 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 228 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 229 /* 42: PM, 44: PC RA, 46: SC vec'd */ 230 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 231 /* 48: SIMD, 50: QP BFP, 52: String */ 232 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 233 /* 54: DecFP, 56: DecI, 58: SHA */ 234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 235 /* 60: NM atomic, 62: RNG */ 236 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 237 }; 238 uint8_t *pa_features; 239 size_t pa_size; 240 241 switch (POWERPC_MMU_VER(env->mmu_model)) { 242 case POWERPC_MMU_VER_2_06: 243 pa_features = pa_features_206; 244 pa_size = sizeof(pa_features_206); 245 break; 246 case POWERPC_MMU_VER_2_07: 247 pa_features = pa_features_207; 248 pa_size = sizeof(pa_features_207); 249 break; 250 case POWERPC_MMU_VER_3_00: 251 pa_features = pa_features_300; 252 pa_size = sizeof(pa_features_300); 253 break; 254 default: 255 return; 256 } 257 258 if (env->ci_large_pages) { 259 /* 260 * Note: we keep CI large pages off by default because a 64K capable 261 * guest provisioned with large pages might otherwise try to map a qemu 262 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 263 * even if that qemu runs on a 4k host. 264 * We dd this bit back here if we are confident this is not an issue 265 */ 266 pa_features[3] |= 0x20; 267 } 268 if (kvmppc_has_cap_htm() && pa_size > 24) { 269 pa_features[24] |= 0x80; /* Transactional memory support */ 270 } 271 if (legacy_guest && pa_size > 40) { 272 /* Workaround for broken kernels that attempt (guest) radix 273 * mode when they can't handle it, if they see the radix bit set 274 * in pa-features. So hide it from them. */ 275 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 276 } 277 278 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 279 } 280 281 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 282 { 283 int ret = 0, offset, cpus_offset; 284 CPUState *cs; 285 char cpu_model[32]; 286 int smt = kvmppc_smt_threads(); 287 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 288 289 CPU_FOREACH(cs) { 290 PowerPCCPU *cpu = POWERPC_CPU(cs); 291 CPUPPCState *env = &cpu->env; 292 DeviceClass *dc = DEVICE_GET_CLASS(cs); 293 int index = ppc_get_vcpu_dt_id(cpu); 294 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 295 296 if ((index % smt) != 0) { 297 continue; 298 } 299 300 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 301 302 cpus_offset = fdt_path_offset(fdt, "/cpus"); 303 if (cpus_offset < 0) { 304 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 305 "cpus"); 306 if (cpus_offset < 0) { 307 return cpus_offset; 308 } 309 } 310 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 311 if (offset < 0) { 312 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 313 if (offset < 0) { 314 return offset; 315 } 316 } 317 318 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 319 pft_size_prop, sizeof(pft_size_prop)); 320 if (ret < 0) { 321 return ret; 322 } 323 324 if (nb_numa_nodes > 1) { 325 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); 326 if (ret < 0) { 327 return ret; 328 } 329 } 330 331 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 332 if (ret < 0) { 333 return ret; 334 } 335 336 spapr_populate_pa_features(env, fdt, offset, 337 spapr->cas_legacy_guest_workaround); 338 } 339 return ret; 340 } 341 342 static hwaddr spapr_node0_size(void) 343 { 344 MachineState *machine = MACHINE(qdev_get_machine()); 345 346 if (nb_numa_nodes) { 347 int i; 348 for (i = 0; i < nb_numa_nodes; ++i) { 349 if (numa_info[i].node_mem) { 350 return MIN(pow2floor(numa_info[i].node_mem), 351 machine->ram_size); 352 } 353 } 354 } 355 return machine->ram_size; 356 } 357 358 static void add_str(GString *s, const gchar *s1) 359 { 360 g_string_append_len(s, s1, strlen(s1) + 1); 361 } 362 363 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 364 hwaddr size) 365 { 366 uint32_t associativity[] = { 367 cpu_to_be32(0x4), /* length */ 368 cpu_to_be32(0x0), cpu_to_be32(0x0), 369 cpu_to_be32(0x0), cpu_to_be32(nodeid) 370 }; 371 char mem_name[32]; 372 uint64_t mem_reg_property[2]; 373 int off; 374 375 mem_reg_property[0] = cpu_to_be64(start); 376 mem_reg_property[1] = cpu_to_be64(size); 377 378 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 379 off = fdt_add_subnode(fdt, 0, mem_name); 380 _FDT(off); 381 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 382 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 383 sizeof(mem_reg_property)))); 384 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 385 sizeof(associativity)))); 386 return off; 387 } 388 389 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 390 { 391 MachineState *machine = MACHINE(spapr); 392 hwaddr mem_start, node_size; 393 int i, nb_nodes = nb_numa_nodes; 394 NodeInfo *nodes = numa_info; 395 NodeInfo ramnode; 396 397 /* No NUMA nodes, assume there is just one node with whole RAM */ 398 if (!nb_numa_nodes) { 399 nb_nodes = 1; 400 ramnode.node_mem = machine->ram_size; 401 nodes = &ramnode; 402 } 403 404 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 405 if (!nodes[i].node_mem) { 406 continue; 407 } 408 if (mem_start >= machine->ram_size) { 409 node_size = 0; 410 } else { 411 node_size = nodes[i].node_mem; 412 if (node_size > machine->ram_size - mem_start) { 413 node_size = machine->ram_size - mem_start; 414 } 415 } 416 if (!mem_start) { 417 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 418 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 419 mem_start += spapr->rma_size; 420 node_size -= spapr->rma_size; 421 } 422 for ( ; node_size; ) { 423 hwaddr sizetmp = pow2floor(node_size); 424 425 /* mem_start != 0 here */ 426 if (ctzl(mem_start) < ctzl(sizetmp)) { 427 sizetmp = 1ULL << ctzl(mem_start); 428 } 429 430 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 431 node_size -= sizetmp; 432 mem_start += sizetmp; 433 } 434 } 435 436 return 0; 437 } 438 439 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 440 sPAPRMachineState *spapr) 441 { 442 PowerPCCPU *cpu = POWERPC_CPU(cs); 443 CPUPPCState *env = &cpu->env; 444 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 445 int index = ppc_get_vcpu_dt_id(cpu); 446 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 447 0xffffffff, 0xffffffff}; 448 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 449 : SPAPR_TIMEBASE_FREQ; 450 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 451 uint32_t page_sizes_prop[64]; 452 size_t page_sizes_prop_size; 453 uint32_t vcpus_per_socket = smp_threads * smp_cores; 454 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 455 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 456 sPAPRDRConnector *drc; 457 int drc_index; 458 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 459 int i; 460 461 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 462 if (drc) { 463 drc_index = spapr_drc_index(drc); 464 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 465 } 466 467 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 468 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 469 470 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 471 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 472 env->dcache_line_size))); 473 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 474 env->dcache_line_size))); 475 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 476 env->icache_line_size))); 477 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 478 env->icache_line_size))); 479 480 if (pcc->l1_dcache_size) { 481 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 482 pcc->l1_dcache_size))); 483 } else { 484 error_report("Warning: Unknown L1 dcache size for cpu"); 485 } 486 if (pcc->l1_icache_size) { 487 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 488 pcc->l1_icache_size))); 489 } else { 490 error_report("Warning: Unknown L1 icache size for cpu"); 491 } 492 493 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 494 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 495 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 496 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 497 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 498 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 499 500 if (env->spr_cb[SPR_PURR].oea_read) { 501 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 502 } 503 504 if (env->mmu_model & POWERPC_MMU_1TSEG) { 505 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 506 segs, sizeof(segs)))); 507 } 508 509 /* Advertise VMX/VSX (vector extensions) if available 510 * 0 / no property == no vector extensions 511 * 1 == VMX / Altivec available 512 * 2 == VSX available */ 513 if (env->insns_flags & PPC_ALTIVEC) { 514 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 515 516 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 517 } 518 519 /* Advertise DFP (Decimal Floating Point) if available 520 * 0 / no property == no DFP 521 * 1 == DFP available */ 522 if (env->insns_flags2 & PPC2_DFP) { 523 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 524 } 525 526 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 527 sizeof(page_sizes_prop)); 528 if (page_sizes_prop_size) { 529 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 530 page_sizes_prop, page_sizes_prop_size))); 531 } 532 533 spapr_populate_pa_features(env, fdt, offset, false); 534 535 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 536 cs->cpu_index / vcpus_per_socket))); 537 538 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 539 pft_size_prop, sizeof(pft_size_prop)))); 540 541 if (nb_numa_nodes > 1) { 542 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 543 } 544 545 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 546 547 if (pcc->radix_page_info) { 548 for (i = 0; i < pcc->radix_page_info->count; i++) { 549 radix_AP_encodings[i] = 550 cpu_to_be32(pcc->radix_page_info->entries[i]); 551 } 552 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 553 radix_AP_encodings, 554 pcc->radix_page_info->count * 555 sizeof(radix_AP_encodings[0])))); 556 } 557 } 558 559 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 560 { 561 CPUState *cs; 562 int cpus_offset; 563 char *nodename; 564 int smt = kvmppc_smt_threads(); 565 566 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 567 _FDT(cpus_offset); 568 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 569 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 570 571 /* 572 * We walk the CPUs in reverse order to ensure that CPU DT nodes 573 * created by fdt_add_subnode() end up in the right order in FDT 574 * for the guest kernel the enumerate the CPUs correctly. 575 */ 576 CPU_FOREACH_REVERSE(cs) { 577 PowerPCCPU *cpu = POWERPC_CPU(cs); 578 int index = ppc_get_vcpu_dt_id(cpu); 579 DeviceClass *dc = DEVICE_GET_CLASS(cs); 580 int offset; 581 582 if ((index % smt) != 0) { 583 continue; 584 } 585 586 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 587 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 588 g_free(nodename); 589 _FDT(offset); 590 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 591 } 592 593 } 594 595 /* 596 * Adds ibm,dynamic-reconfiguration-memory node. 597 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 598 * of this device tree node. 599 */ 600 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 601 { 602 MachineState *machine = MACHINE(spapr); 603 int ret, i, offset; 604 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 605 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 606 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 607 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 608 memory_region_size(&spapr->hotplug_memory.mr)) / 609 lmb_size; 610 uint32_t *int_buf, *cur_index, buf_len; 611 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 612 613 /* 614 * Don't create the node if there is no hotpluggable memory 615 */ 616 if (machine->ram_size == machine->maxram_size) { 617 return 0; 618 } 619 620 /* 621 * Allocate enough buffer size to fit in ibm,dynamic-memory 622 * or ibm,associativity-lookup-arrays 623 */ 624 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 625 * sizeof(uint32_t); 626 cur_index = int_buf = g_malloc0(buf_len); 627 628 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 629 630 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 631 sizeof(prop_lmb_size)); 632 if (ret < 0) { 633 goto out; 634 } 635 636 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 637 if (ret < 0) { 638 goto out; 639 } 640 641 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 642 if (ret < 0) { 643 goto out; 644 } 645 646 /* ibm,dynamic-memory */ 647 int_buf[0] = cpu_to_be32(nr_lmbs); 648 cur_index++; 649 for (i = 0; i < nr_lmbs; i++) { 650 uint64_t addr = i * lmb_size; 651 uint32_t *dynamic_memory = cur_index; 652 653 if (i >= hotplug_lmb_start) { 654 sPAPRDRConnector *drc; 655 656 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 657 g_assert(drc); 658 659 dynamic_memory[0] = cpu_to_be32(addr >> 32); 660 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 661 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 662 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 663 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); 664 if (memory_region_present(get_system_memory(), addr)) { 665 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 666 } else { 667 dynamic_memory[5] = cpu_to_be32(0); 668 } 669 } else { 670 /* 671 * LMB information for RMA, boot time RAM and gap b/n RAM and 672 * hotplug memory region -- all these are marked as reserved 673 * and as having no valid DRC. 674 */ 675 dynamic_memory[0] = cpu_to_be32(addr >> 32); 676 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 677 dynamic_memory[2] = cpu_to_be32(0); 678 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 679 dynamic_memory[4] = cpu_to_be32(-1); 680 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 681 SPAPR_LMB_FLAGS_DRC_INVALID); 682 } 683 684 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 685 } 686 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 687 if (ret < 0) { 688 goto out; 689 } 690 691 /* ibm,associativity-lookup-arrays */ 692 cur_index = int_buf; 693 int_buf[0] = cpu_to_be32(nr_nodes); 694 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 695 cur_index += 2; 696 for (i = 0; i < nr_nodes; i++) { 697 uint32_t associativity[] = { 698 cpu_to_be32(0x0), 699 cpu_to_be32(0x0), 700 cpu_to_be32(0x0), 701 cpu_to_be32(i) 702 }; 703 memcpy(cur_index, associativity, sizeof(associativity)); 704 cur_index += 4; 705 } 706 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 707 (cur_index - int_buf) * sizeof(uint32_t)); 708 out: 709 g_free(int_buf); 710 return ret; 711 } 712 713 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 714 sPAPROptionVector *ov5_updates) 715 { 716 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 717 int ret = 0, offset; 718 719 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 720 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 721 g_assert(smc->dr_lmb_enabled); 722 ret = spapr_populate_drconf_memory(spapr, fdt); 723 if (ret) { 724 goto out; 725 } 726 } 727 728 offset = fdt_path_offset(fdt, "/chosen"); 729 if (offset < 0) { 730 offset = fdt_add_subnode(fdt, 0, "chosen"); 731 if (offset < 0) { 732 return offset; 733 } 734 } 735 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 736 "ibm,architecture-vec-5"); 737 738 out: 739 return ret; 740 } 741 742 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 743 target_ulong addr, target_ulong size, 744 sPAPROptionVector *ov5_updates) 745 { 746 void *fdt, *fdt_skel; 747 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 748 749 size -= sizeof(hdr); 750 751 /* Create sceleton */ 752 fdt_skel = g_malloc0(size); 753 _FDT((fdt_create(fdt_skel, size))); 754 _FDT((fdt_begin_node(fdt_skel, ""))); 755 _FDT((fdt_end_node(fdt_skel))); 756 _FDT((fdt_finish(fdt_skel))); 757 fdt = g_malloc0(size); 758 _FDT((fdt_open_into(fdt_skel, fdt, size))); 759 g_free(fdt_skel); 760 761 /* Fixup cpu nodes */ 762 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 763 764 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 765 return -1; 766 } 767 768 /* Pack resulting tree */ 769 _FDT((fdt_pack(fdt))); 770 771 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 772 trace_spapr_cas_failed(size); 773 return -1; 774 } 775 776 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 777 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 778 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 779 g_free(fdt); 780 781 return 0; 782 } 783 784 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 785 { 786 int rtas; 787 GString *hypertas = g_string_sized_new(256); 788 GString *qemu_hypertas = g_string_sized_new(256); 789 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 790 uint64_t max_hotplug_addr = spapr->hotplug_memory.base + 791 memory_region_size(&spapr->hotplug_memory.mr); 792 uint32_t lrdr_capacity[] = { 793 cpu_to_be32(max_hotplug_addr >> 32), 794 cpu_to_be32(max_hotplug_addr & 0xffffffff), 795 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 796 cpu_to_be32(max_cpus / smp_threads), 797 }; 798 799 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 800 801 /* hypertas */ 802 add_str(hypertas, "hcall-pft"); 803 add_str(hypertas, "hcall-term"); 804 add_str(hypertas, "hcall-dabr"); 805 add_str(hypertas, "hcall-interrupt"); 806 add_str(hypertas, "hcall-tce"); 807 add_str(hypertas, "hcall-vio"); 808 add_str(hypertas, "hcall-splpar"); 809 add_str(hypertas, "hcall-bulk"); 810 add_str(hypertas, "hcall-set-mode"); 811 add_str(hypertas, "hcall-sprg0"); 812 add_str(hypertas, "hcall-copy"); 813 add_str(hypertas, "hcall-debug"); 814 add_str(qemu_hypertas, "hcall-memop1"); 815 816 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 817 add_str(hypertas, "hcall-multi-tce"); 818 } 819 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 820 hypertas->str, hypertas->len)); 821 g_string_free(hypertas, TRUE); 822 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 823 qemu_hypertas->str, qemu_hypertas->len)); 824 g_string_free(qemu_hypertas, TRUE); 825 826 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 827 refpoints, sizeof(refpoints))); 828 829 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 830 RTAS_ERROR_LOG_MAX)); 831 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 832 RTAS_EVENT_SCAN_RATE)); 833 834 if (msi_nonbroken) { 835 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 836 } 837 838 /* 839 * According to PAPR, rtas ibm,os-term does not guarantee a return 840 * back to the guest cpu. 841 * 842 * While an additional ibm,extended-os-term property indicates 843 * that rtas call return will always occur. Set this property. 844 */ 845 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 846 847 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 848 lrdr_capacity, sizeof(lrdr_capacity))); 849 850 spapr_dt_rtas_tokens(fdt, rtas); 851 } 852 853 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features 854 * that the guest may request and thus the valid values for bytes 24..26 of 855 * option vector 5: */ 856 static void spapr_dt_ov5_platform_support(void *fdt, int chosen) 857 { 858 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 859 860 char val[2 * 3] = { 861 24, 0x00, /* Hash/Radix, filled in below. */ 862 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 863 26, 0x40, /* Radix options: GTSE == yes. */ 864 }; 865 866 if (kvm_enabled()) { 867 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 868 val[1] = 0x80; /* OV5_MMU_BOTH */ 869 } else if (kvmppc_has_cap_mmu_radix()) { 870 val[1] = 0x40; /* OV5_MMU_RADIX_300 */ 871 } else { 872 val[1] = 0x00; /* Hash */ 873 } 874 } else { 875 if (first_ppc_cpu->env.mmu_model & POWERPC_MMU_V3) { 876 /* V3 MMU supports both hash and radix (with dynamic switching) */ 877 val[1] = 0xC0; 878 } else { 879 /* Otherwise we can only do hash */ 880 val[1] = 0x00; 881 } 882 } 883 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 884 val, sizeof(val))); 885 } 886 887 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 888 { 889 MachineState *machine = MACHINE(spapr); 890 int chosen; 891 const char *boot_device = machine->boot_order; 892 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 893 size_t cb = 0; 894 char *bootlist = get_boot_devices_list(&cb, true); 895 896 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 897 898 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 899 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 900 spapr->initrd_base)); 901 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 902 spapr->initrd_base + spapr->initrd_size)); 903 904 if (spapr->kernel_size) { 905 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 906 cpu_to_be64(spapr->kernel_size) }; 907 908 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 909 &kprop, sizeof(kprop))); 910 if (spapr->kernel_le) { 911 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 912 } 913 } 914 if (boot_menu) { 915 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 916 } 917 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 918 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 919 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 920 921 if (cb && bootlist) { 922 int i; 923 924 for (i = 0; i < cb; i++) { 925 if (bootlist[i] == '\n') { 926 bootlist[i] = ' '; 927 } 928 } 929 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 930 } 931 932 if (boot_device && strlen(boot_device)) { 933 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 934 } 935 936 if (!spapr->has_graphics && stdout_path) { 937 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 938 } 939 940 spapr_dt_ov5_platform_support(fdt, chosen); 941 942 g_free(stdout_path); 943 g_free(bootlist); 944 } 945 946 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 947 { 948 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 949 * KVM to work under pHyp with some guest co-operation */ 950 int hypervisor; 951 uint8_t hypercall[16]; 952 953 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 954 /* indicate KVM hypercall interface */ 955 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 956 if (kvmppc_has_cap_fixup_hcalls()) { 957 /* 958 * Older KVM versions with older guest kernels were broken 959 * with the magic page, don't allow the guest to map it. 960 */ 961 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 962 sizeof(hypercall))) { 963 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 964 hypercall, sizeof(hypercall))); 965 } 966 } 967 } 968 969 static void *spapr_build_fdt(sPAPRMachineState *spapr, 970 hwaddr rtas_addr, 971 hwaddr rtas_size) 972 { 973 MachineState *machine = MACHINE(qdev_get_machine()); 974 MachineClass *mc = MACHINE_GET_CLASS(machine); 975 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 976 int ret; 977 void *fdt; 978 sPAPRPHBState *phb; 979 char *buf; 980 int smt = kvmppc_smt_threads(); 981 982 fdt = g_malloc0(FDT_MAX_SIZE); 983 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 984 985 /* Root node */ 986 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 987 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 988 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 989 990 /* 991 * Add info to guest to indentify which host is it being run on 992 * and what is the uuid of the guest 993 */ 994 if (kvmppc_get_host_model(&buf)) { 995 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 996 g_free(buf); 997 } 998 if (kvmppc_get_host_serial(&buf)) { 999 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1000 g_free(buf); 1001 } 1002 1003 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1004 1005 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1006 if (qemu_uuid_set) { 1007 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1008 } 1009 g_free(buf); 1010 1011 if (qemu_get_vm_name()) { 1012 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1013 qemu_get_vm_name())); 1014 } 1015 1016 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1017 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1018 1019 /* /interrupt controller */ 1020 spapr_dt_xics(DIV_ROUND_UP(max_cpus * smt, smp_threads), fdt, PHANDLE_XICP); 1021 1022 ret = spapr_populate_memory(spapr, fdt); 1023 if (ret < 0) { 1024 error_report("couldn't setup memory nodes in fdt"); 1025 exit(1); 1026 } 1027 1028 /* /vdevice */ 1029 spapr_dt_vdevice(spapr->vio_bus, fdt); 1030 1031 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1032 ret = spapr_rng_populate_dt(fdt); 1033 if (ret < 0) { 1034 error_report("could not set up rng device in the fdt"); 1035 exit(1); 1036 } 1037 } 1038 1039 QLIST_FOREACH(phb, &spapr->phbs, list) { 1040 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 1041 if (ret < 0) { 1042 error_report("couldn't setup PCI devices in fdt"); 1043 exit(1); 1044 } 1045 } 1046 1047 /* cpus */ 1048 spapr_populate_cpus_dt_node(fdt, spapr); 1049 1050 if (smc->dr_lmb_enabled) { 1051 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1052 } 1053 1054 if (mc->has_hotpluggable_cpus) { 1055 int offset = fdt_path_offset(fdt, "/cpus"); 1056 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1057 SPAPR_DR_CONNECTOR_TYPE_CPU); 1058 if (ret < 0) { 1059 error_report("Couldn't set up CPU DR device tree properties"); 1060 exit(1); 1061 } 1062 } 1063 1064 /* /event-sources */ 1065 spapr_dt_events(spapr, fdt); 1066 1067 /* /rtas */ 1068 spapr_dt_rtas(spapr, fdt); 1069 1070 /* /chosen */ 1071 spapr_dt_chosen(spapr, fdt); 1072 1073 /* /hypervisor */ 1074 if (kvm_enabled()) { 1075 spapr_dt_hypervisor(spapr, fdt); 1076 } 1077 1078 /* Build memory reserve map */ 1079 if (spapr->kernel_size) { 1080 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1081 } 1082 if (spapr->initrd_size) { 1083 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1084 } 1085 1086 /* ibm,client-architecture-support updates */ 1087 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1088 if (ret < 0) { 1089 error_report("couldn't setup CAS properties fdt"); 1090 exit(1); 1091 } 1092 1093 return fdt; 1094 } 1095 1096 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1097 { 1098 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1099 } 1100 1101 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1102 PowerPCCPU *cpu) 1103 { 1104 CPUPPCState *env = &cpu->env; 1105 1106 /* The TCG path should also be holding the BQL at this point */ 1107 g_assert(qemu_mutex_iothread_locked()); 1108 1109 if (msr_pr) { 1110 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1111 env->gpr[3] = H_PRIVILEGE; 1112 } else { 1113 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1114 } 1115 } 1116 1117 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) 1118 { 1119 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1120 1121 return spapr->patb_entry; 1122 } 1123 1124 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1125 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1126 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1127 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1128 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1129 1130 /* 1131 * Get the fd to access the kernel htab, re-opening it if necessary 1132 */ 1133 static int get_htab_fd(sPAPRMachineState *spapr) 1134 { 1135 if (spapr->htab_fd >= 0) { 1136 return spapr->htab_fd; 1137 } 1138 1139 spapr->htab_fd = kvmppc_get_htab_fd(false); 1140 if (spapr->htab_fd < 0) { 1141 error_report("Unable to open fd for reading hash table from KVM: %s", 1142 strerror(errno)); 1143 } 1144 1145 return spapr->htab_fd; 1146 } 1147 1148 void close_htab_fd(sPAPRMachineState *spapr) 1149 { 1150 if (spapr->htab_fd >= 0) { 1151 close(spapr->htab_fd); 1152 } 1153 spapr->htab_fd = -1; 1154 } 1155 1156 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1157 { 1158 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1159 1160 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1161 } 1162 1163 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1164 hwaddr ptex, int n) 1165 { 1166 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1167 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1168 1169 if (!spapr->htab) { 1170 /* 1171 * HTAB is controlled by KVM. Fetch into temporary buffer 1172 */ 1173 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1174 kvmppc_read_hptes(hptes, ptex, n); 1175 return hptes; 1176 } 1177 1178 /* 1179 * HTAB is controlled by QEMU. Just point to the internally 1180 * accessible PTEG. 1181 */ 1182 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1183 } 1184 1185 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1186 const ppc_hash_pte64_t *hptes, 1187 hwaddr ptex, int n) 1188 { 1189 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1190 1191 if (!spapr->htab) { 1192 g_free((void *)hptes); 1193 } 1194 1195 /* Nothing to do for qemu managed HPT */ 1196 } 1197 1198 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1199 uint64_t pte0, uint64_t pte1) 1200 { 1201 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1202 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1203 1204 if (!spapr->htab) { 1205 kvmppc_write_hpte(ptex, pte0, pte1); 1206 } else { 1207 stq_p(spapr->htab + offset, pte0); 1208 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1209 } 1210 } 1211 1212 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1213 { 1214 int shift; 1215 1216 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1217 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1218 * that's much more than is needed for Linux guests */ 1219 shift = ctz64(pow2ceil(ramsize)) - 7; 1220 shift = MAX(shift, 18); /* Minimum architected size */ 1221 shift = MIN(shift, 46); /* Maximum architected size */ 1222 return shift; 1223 } 1224 1225 void spapr_free_hpt(sPAPRMachineState *spapr) 1226 { 1227 g_free(spapr->htab); 1228 spapr->htab = NULL; 1229 spapr->htab_shift = 0; 1230 close_htab_fd(spapr); 1231 } 1232 1233 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1234 Error **errp) 1235 { 1236 long rc; 1237 1238 /* Clean up any HPT info from a previous boot */ 1239 spapr_free_hpt(spapr); 1240 1241 rc = kvmppc_reset_htab(shift); 1242 if (rc < 0) { 1243 /* kernel-side HPT needed, but couldn't allocate one */ 1244 error_setg_errno(errp, errno, 1245 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1246 shift); 1247 /* This is almost certainly fatal, but if the caller really 1248 * wants to carry on with shift == 0, it's welcome to try */ 1249 } else if (rc > 0) { 1250 /* kernel-side HPT allocated */ 1251 if (rc != shift) { 1252 error_setg(errp, 1253 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1254 shift, rc); 1255 } 1256 1257 spapr->htab_shift = shift; 1258 spapr->htab = NULL; 1259 } else { 1260 /* kernel-side HPT not needed, allocate in userspace instead */ 1261 size_t size = 1ULL << shift; 1262 int i; 1263 1264 spapr->htab = qemu_memalign(size, size); 1265 if (!spapr->htab) { 1266 error_setg_errno(errp, errno, 1267 "Could not allocate HPT of order %d", shift); 1268 return; 1269 } 1270 1271 memset(spapr->htab, 0, size); 1272 spapr->htab_shift = shift; 1273 1274 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1275 DIRTY_HPTE(HPTE(spapr->htab, i)); 1276 } 1277 } 1278 } 1279 1280 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) 1281 { 1282 spapr_reallocate_hpt(spapr, 1283 spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size), 1284 &error_fatal); 1285 if (spapr->vrma_adjust) { 1286 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 1287 spapr->htab_shift); 1288 } 1289 /* We're setting up a hash table, so that means we're not radix */ 1290 spapr->patb_entry = 0; 1291 } 1292 1293 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1294 { 1295 bool matched = false; 1296 1297 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1298 matched = true; 1299 } 1300 1301 if (!matched) { 1302 error_report("Device %s is not supported by this machine yet.", 1303 qdev_fw_name(DEVICE(sbdev))); 1304 exit(1); 1305 } 1306 } 1307 1308 static void ppc_spapr_reset(void) 1309 { 1310 MachineState *machine = MACHINE(qdev_get_machine()); 1311 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1312 PowerPCCPU *first_ppc_cpu; 1313 uint32_t rtas_limit; 1314 hwaddr rtas_addr, fdt_addr; 1315 void *fdt; 1316 int rc; 1317 1318 /* Check for unknown sysbus devices */ 1319 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1320 1321 if (kvm_enabled() && kvmppc_has_cap_mmu_radix()) { 1322 /* If using KVM with radix mode available, VCPUs can be started 1323 * without a HPT because KVM will start them in radix mode. 1324 * Set the GR bit in PATB so that we know there is no HPT. */ 1325 spapr->patb_entry = PATBE1_GR; 1326 } else { 1327 spapr->patb_entry = 0; 1328 spapr_setup_hpt_and_vrma(spapr); 1329 } 1330 1331 qemu_devices_reset(); 1332 1333 /* 1334 * We place the device tree and RTAS just below either the top of the RMA, 1335 * or just below 2GB, whichever is lowere, so that it can be 1336 * processed with 32-bit real mode code if necessary 1337 */ 1338 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1339 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1340 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1341 1342 /* if this reset wasn't generated by CAS, we should reset our 1343 * negotiated options and start from scratch */ 1344 if (!spapr->cas_reboot) { 1345 spapr_ovec_cleanup(spapr->ov5_cas); 1346 spapr->ov5_cas = spapr_ovec_new(); 1347 } 1348 1349 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1350 1351 spapr_load_rtas(spapr, fdt, rtas_addr); 1352 1353 rc = fdt_pack(fdt); 1354 1355 /* Should only fail if we've built a corrupted tree */ 1356 assert(rc == 0); 1357 1358 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1359 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1360 fdt_totalsize(fdt), FDT_MAX_SIZE); 1361 exit(1); 1362 } 1363 1364 /* Load the fdt */ 1365 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1366 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1367 g_free(fdt); 1368 1369 /* Set up the entry state */ 1370 first_ppc_cpu = POWERPC_CPU(first_cpu); 1371 first_ppc_cpu->env.gpr[3] = fdt_addr; 1372 first_ppc_cpu->env.gpr[5] = 0; 1373 first_cpu->halted = 0; 1374 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1375 1376 spapr->cas_reboot = false; 1377 } 1378 1379 static void spapr_create_nvram(sPAPRMachineState *spapr) 1380 { 1381 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1382 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1383 1384 if (dinfo) { 1385 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1386 &error_fatal); 1387 } 1388 1389 qdev_init_nofail(dev); 1390 1391 spapr->nvram = (struct sPAPRNVRAM *)dev; 1392 } 1393 1394 static void spapr_rtc_create(sPAPRMachineState *spapr) 1395 { 1396 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); 1397 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), 1398 &error_fatal); 1399 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1400 &error_fatal); 1401 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1402 "date", &error_fatal); 1403 } 1404 1405 /* Returns whether we want to use VGA or not */ 1406 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1407 { 1408 switch (vga_interface_type) { 1409 case VGA_NONE: 1410 return false; 1411 case VGA_DEVICE: 1412 return true; 1413 case VGA_STD: 1414 case VGA_VIRTIO: 1415 return pci_vga_init(pci_bus) != NULL; 1416 default: 1417 error_setg(errp, 1418 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1419 return false; 1420 } 1421 } 1422 1423 static int spapr_post_load(void *opaque, int version_id) 1424 { 1425 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1426 int err = 0; 1427 1428 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { 1429 CPUState *cs; 1430 CPU_FOREACH(cs) { 1431 PowerPCCPU *cpu = POWERPC_CPU(cs); 1432 icp_resend(ICP(cpu->intc)); 1433 } 1434 } 1435 1436 /* In earlier versions, there was no separate qdev for the PAPR 1437 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1438 * So when migrating from those versions, poke the incoming offset 1439 * value into the RTC device */ 1440 if (version_id < 3) { 1441 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1442 } 1443 1444 return err; 1445 } 1446 1447 static bool version_before_3(void *opaque, int version_id) 1448 { 1449 return version_id < 3; 1450 } 1451 1452 static bool spapr_ov5_cas_needed(void *opaque) 1453 { 1454 sPAPRMachineState *spapr = opaque; 1455 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1456 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1457 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1458 bool cas_needed; 1459 1460 /* Prior to the introduction of sPAPROptionVector, we had two option 1461 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1462 * Both of these options encode machine topology into the device-tree 1463 * in such a way that the now-booted OS should still be able to interact 1464 * appropriately with QEMU regardless of what options were actually 1465 * negotiatied on the source side. 1466 * 1467 * As such, we can avoid migrating the CAS-negotiated options if these 1468 * are the only options available on the current machine/platform. 1469 * Since these are the only options available for pseries-2.7 and 1470 * earlier, this allows us to maintain old->new/new->old migration 1471 * compatibility. 1472 * 1473 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1474 * via default pseries-2.8 machines and explicit command-line parameters. 1475 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1476 * of the actual CAS-negotiated values to continue working properly. For 1477 * example, availability of memory unplug depends on knowing whether 1478 * OV5_HP_EVT was negotiated via CAS. 1479 * 1480 * Thus, for any cases where the set of available CAS-negotiatable 1481 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1482 * include the CAS-negotiated options in the migration stream. 1483 */ 1484 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1485 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1486 1487 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1488 * the mask itself since in the future it's possible "legacy" bits may be 1489 * removed via machine options, which could generate a false positive 1490 * that breaks migration. 1491 */ 1492 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1493 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1494 1495 spapr_ovec_cleanup(ov5_mask); 1496 spapr_ovec_cleanup(ov5_legacy); 1497 spapr_ovec_cleanup(ov5_removed); 1498 1499 return cas_needed; 1500 } 1501 1502 static const VMStateDescription vmstate_spapr_ov5_cas = { 1503 .name = "spapr_option_vector_ov5_cas", 1504 .version_id = 1, 1505 .minimum_version_id = 1, 1506 .needed = spapr_ov5_cas_needed, 1507 .fields = (VMStateField[]) { 1508 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1509 vmstate_spapr_ovec, sPAPROptionVector), 1510 VMSTATE_END_OF_LIST() 1511 }, 1512 }; 1513 1514 static bool spapr_patb_entry_needed(void *opaque) 1515 { 1516 sPAPRMachineState *spapr = opaque; 1517 1518 return !!spapr->patb_entry; 1519 } 1520 1521 static const VMStateDescription vmstate_spapr_patb_entry = { 1522 .name = "spapr_patb_entry", 1523 .version_id = 1, 1524 .minimum_version_id = 1, 1525 .needed = spapr_patb_entry_needed, 1526 .fields = (VMStateField[]) { 1527 VMSTATE_UINT64(patb_entry, sPAPRMachineState), 1528 VMSTATE_END_OF_LIST() 1529 }, 1530 }; 1531 1532 static const VMStateDescription vmstate_spapr = { 1533 .name = "spapr", 1534 .version_id = 3, 1535 .minimum_version_id = 1, 1536 .post_load = spapr_post_load, 1537 .fields = (VMStateField[]) { 1538 /* used to be @next_irq */ 1539 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1540 1541 /* RTC offset */ 1542 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1543 1544 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1545 VMSTATE_END_OF_LIST() 1546 }, 1547 .subsections = (const VMStateDescription*[]) { 1548 &vmstate_spapr_ov5_cas, 1549 &vmstate_spapr_patb_entry, 1550 NULL 1551 } 1552 }; 1553 1554 static int htab_save_setup(QEMUFile *f, void *opaque) 1555 { 1556 sPAPRMachineState *spapr = opaque; 1557 1558 /* "Iteration" header */ 1559 qemu_put_be32(f, spapr->htab_shift); 1560 1561 if (spapr->htab) { 1562 spapr->htab_save_index = 0; 1563 spapr->htab_first_pass = true; 1564 } else { 1565 assert(kvm_enabled()); 1566 } 1567 1568 1569 return 0; 1570 } 1571 1572 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1573 int64_t max_ns) 1574 { 1575 bool has_timeout = max_ns != -1; 1576 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1577 int index = spapr->htab_save_index; 1578 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1579 1580 assert(spapr->htab_first_pass); 1581 1582 do { 1583 int chunkstart; 1584 1585 /* Consume invalid HPTEs */ 1586 while ((index < htabslots) 1587 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1588 CLEAN_HPTE(HPTE(spapr->htab, index)); 1589 index++; 1590 } 1591 1592 /* Consume valid HPTEs */ 1593 chunkstart = index; 1594 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1595 && HPTE_VALID(HPTE(spapr->htab, index))) { 1596 CLEAN_HPTE(HPTE(spapr->htab, index)); 1597 index++; 1598 } 1599 1600 if (index > chunkstart) { 1601 int n_valid = index - chunkstart; 1602 1603 qemu_put_be32(f, chunkstart); 1604 qemu_put_be16(f, n_valid); 1605 qemu_put_be16(f, 0); 1606 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1607 HASH_PTE_SIZE_64 * n_valid); 1608 1609 if (has_timeout && 1610 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1611 break; 1612 } 1613 } 1614 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1615 1616 if (index >= htabslots) { 1617 assert(index == htabslots); 1618 index = 0; 1619 spapr->htab_first_pass = false; 1620 } 1621 spapr->htab_save_index = index; 1622 } 1623 1624 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1625 int64_t max_ns) 1626 { 1627 bool final = max_ns < 0; 1628 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1629 int examined = 0, sent = 0; 1630 int index = spapr->htab_save_index; 1631 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1632 1633 assert(!spapr->htab_first_pass); 1634 1635 do { 1636 int chunkstart, invalidstart; 1637 1638 /* Consume non-dirty HPTEs */ 1639 while ((index < htabslots) 1640 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1641 index++; 1642 examined++; 1643 } 1644 1645 chunkstart = index; 1646 /* Consume valid dirty HPTEs */ 1647 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1648 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1649 && HPTE_VALID(HPTE(spapr->htab, index))) { 1650 CLEAN_HPTE(HPTE(spapr->htab, index)); 1651 index++; 1652 examined++; 1653 } 1654 1655 invalidstart = index; 1656 /* Consume invalid dirty HPTEs */ 1657 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1658 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1659 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1660 CLEAN_HPTE(HPTE(spapr->htab, index)); 1661 index++; 1662 examined++; 1663 } 1664 1665 if (index > chunkstart) { 1666 int n_valid = invalidstart - chunkstart; 1667 int n_invalid = index - invalidstart; 1668 1669 qemu_put_be32(f, chunkstart); 1670 qemu_put_be16(f, n_valid); 1671 qemu_put_be16(f, n_invalid); 1672 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1673 HASH_PTE_SIZE_64 * n_valid); 1674 sent += index - chunkstart; 1675 1676 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1677 break; 1678 } 1679 } 1680 1681 if (examined >= htabslots) { 1682 break; 1683 } 1684 1685 if (index >= htabslots) { 1686 assert(index == htabslots); 1687 index = 0; 1688 } 1689 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1690 1691 if (index >= htabslots) { 1692 assert(index == htabslots); 1693 index = 0; 1694 } 1695 1696 spapr->htab_save_index = index; 1697 1698 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1699 } 1700 1701 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1702 #define MAX_KVM_BUF_SIZE 2048 1703 1704 static int htab_save_iterate(QEMUFile *f, void *opaque) 1705 { 1706 sPAPRMachineState *spapr = opaque; 1707 int fd; 1708 int rc = 0; 1709 1710 /* Iteration header */ 1711 qemu_put_be32(f, 0); 1712 1713 if (!spapr->htab) { 1714 assert(kvm_enabled()); 1715 1716 fd = get_htab_fd(spapr); 1717 if (fd < 0) { 1718 return fd; 1719 } 1720 1721 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1722 if (rc < 0) { 1723 return rc; 1724 } 1725 } else if (spapr->htab_first_pass) { 1726 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1727 } else { 1728 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1729 } 1730 1731 /* End marker */ 1732 qemu_put_be32(f, 0); 1733 qemu_put_be16(f, 0); 1734 qemu_put_be16(f, 0); 1735 1736 return rc; 1737 } 1738 1739 static int htab_save_complete(QEMUFile *f, void *opaque) 1740 { 1741 sPAPRMachineState *spapr = opaque; 1742 int fd; 1743 1744 /* Iteration header */ 1745 qemu_put_be32(f, 0); 1746 1747 if (!spapr->htab) { 1748 int rc; 1749 1750 assert(kvm_enabled()); 1751 1752 fd = get_htab_fd(spapr); 1753 if (fd < 0) { 1754 return fd; 1755 } 1756 1757 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 1758 if (rc < 0) { 1759 return rc; 1760 } 1761 } else { 1762 if (spapr->htab_first_pass) { 1763 htab_save_first_pass(f, spapr, -1); 1764 } 1765 htab_save_later_pass(f, spapr, -1); 1766 } 1767 1768 /* End marker */ 1769 qemu_put_be32(f, 0); 1770 qemu_put_be16(f, 0); 1771 qemu_put_be16(f, 0); 1772 1773 return 0; 1774 } 1775 1776 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1777 { 1778 sPAPRMachineState *spapr = opaque; 1779 uint32_t section_hdr; 1780 int fd = -1; 1781 1782 if (version_id < 1 || version_id > 1) { 1783 error_report("htab_load() bad version"); 1784 return -EINVAL; 1785 } 1786 1787 section_hdr = qemu_get_be32(f); 1788 1789 if (section_hdr) { 1790 Error *local_err = NULL; 1791 1792 /* First section gives the htab size */ 1793 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 1794 if (local_err) { 1795 error_report_err(local_err); 1796 return -EINVAL; 1797 } 1798 return 0; 1799 } 1800 1801 if (!spapr->htab) { 1802 assert(kvm_enabled()); 1803 1804 fd = kvmppc_get_htab_fd(true); 1805 if (fd < 0) { 1806 error_report("Unable to open fd to restore KVM hash table: %s", 1807 strerror(errno)); 1808 } 1809 } 1810 1811 while (true) { 1812 uint32_t index; 1813 uint16_t n_valid, n_invalid; 1814 1815 index = qemu_get_be32(f); 1816 n_valid = qemu_get_be16(f); 1817 n_invalid = qemu_get_be16(f); 1818 1819 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1820 /* End of Stream */ 1821 break; 1822 } 1823 1824 if ((index + n_valid + n_invalid) > 1825 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1826 /* Bad index in stream */ 1827 error_report( 1828 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 1829 index, n_valid, n_invalid, spapr->htab_shift); 1830 return -EINVAL; 1831 } 1832 1833 if (spapr->htab) { 1834 if (n_valid) { 1835 qemu_get_buffer(f, HPTE(spapr->htab, index), 1836 HASH_PTE_SIZE_64 * n_valid); 1837 } 1838 if (n_invalid) { 1839 memset(HPTE(spapr->htab, index + n_valid), 0, 1840 HASH_PTE_SIZE_64 * n_invalid); 1841 } 1842 } else { 1843 int rc; 1844 1845 assert(fd >= 0); 1846 1847 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1848 if (rc < 0) { 1849 return rc; 1850 } 1851 } 1852 } 1853 1854 if (!spapr->htab) { 1855 assert(fd >= 0); 1856 close(fd); 1857 } 1858 1859 return 0; 1860 } 1861 1862 static void htab_cleanup(void *opaque) 1863 { 1864 sPAPRMachineState *spapr = opaque; 1865 1866 close_htab_fd(spapr); 1867 } 1868 1869 static SaveVMHandlers savevm_htab_handlers = { 1870 .save_live_setup = htab_save_setup, 1871 .save_live_iterate = htab_save_iterate, 1872 .save_live_complete_precopy = htab_save_complete, 1873 .cleanup = htab_cleanup, 1874 .load_state = htab_load, 1875 }; 1876 1877 static void spapr_boot_set(void *opaque, const char *boot_device, 1878 Error **errp) 1879 { 1880 MachineState *machine = MACHINE(qdev_get_machine()); 1881 machine->boot_order = g_strdup(boot_device); 1882 } 1883 1884 /* 1885 * Reset routine for LMB DR devices. 1886 * 1887 * Unlike PCI DR devices, LMB DR devices explicitly register this reset 1888 * routine. Reset for PCI DR devices will be handled by PHB reset routine 1889 * when it walks all its children devices. LMB devices reset occurs 1890 * as part of spapr_ppc_reset(). 1891 */ 1892 static void spapr_drc_reset(void *opaque) 1893 { 1894 sPAPRDRConnector *drc = opaque; 1895 DeviceState *d = DEVICE(drc); 1896 1897 if (d) { 1898 device_reset(d); 1899 } 1900 } 1901 1902 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 1903 { 1904 MachineState *machine = MACHINE(spapr); 1905 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 1906 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 1907 int i; 1908 1909 for (i = 0; i < nr_lmbs; i++) { 1910 sPAPRDRConnector *drc; 1911 uint64_t addr; 1912 1913 addr = i * lmb_size + spapr->hotplug_memory.base; 1914 drc = spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 1915 addr/lmb_size); 1916 qemu_register_reset(spapr_drc_reset, drc); 1917 } 1918 } 1919 1920 /* 1921 * If RAM size, maxmem size and individual node mem sizes aren't aligned 1922 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 1923 * since we can't support such unaligned sizes with DRCONF_MEMORY. 1924 */ 1925 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 1926 { 1927 int i; 1928 1929 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1930 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 1931 " is not aligned to %llu MiB", 1932 machine->ram_size, 1933 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1934 return; 1935 } 1936 1937 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1938 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 1939 " is not aligned to %llu MiB", 1940 machine->ram_size, 1941 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1942 return; 1943 } 1944 1945 for (i = 0; i < nb_numa_nodes; i++) { 1946 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 1947 error_setg(errp, 1948 "Node %d memory size 0x%" PRIx64 1949 " is not aligned to %llu MiB", 1950 i, numa_info[i].node_mem, 1951 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1952 return; 1953 } 1954 } 1955 } 1956 1957 /* find cpu slot in machine->possible_cpus by core_id */ 1958 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 1959 { 1960 int index = id / smp_threads; 1961 1962 if (index >= ms->possible_cpus->len) { 1963 return NULL; 1964 } 1965 if (idx) { 1966 *idx = index; 1967 } 1968 return &ms->possible_cpus->cpus[index]; 1969 } 1970 1971 static void spapr_init_cpus(sPAPRMachineState *spapr) 1972 { 1973 MachineState *machine = MACHINE(spapr); 1974 MachineClass *mc = MACHINE_GET_CLASS(machine); 1975 char *type = spapr_get_cpu_core_type(machine->cpu_model); 1976 int smt = kvmppc_smt_threads(); 1977 const CPUArchIdList *possible_cpus; 1978 int boot_cores_nr = smp_cpus / smp_threads; 1979 int i; 1980 1981 if (!type) { 1982 error_report("Unable to find sPAPR CPU Core definition"); 1983 exit(1); 1984 } 1985 1986 possible_cpus = mc->possible_cpu_arch_ids(machine); 1987 if (mc->has_hotpluggable_cpus) { 1988 if (smp_cpus % smp_threads) { 1989 error_report("smp_cpus (%u) must be multiple of threads (%u)", 1990 smp_cpus, smp_threads); 1991 exit(1); 1992 } 1993 if (max_cpus % smp_threads) { 1994 error_report("max_cpus (%u) must be multiple of threads (%u)", 1995 max_cpus, smp_threads); 1996 exit(1); 1997 } 1998 } else { 1999 if (max_cpus != smp_cpus) { 2000 error_report("This machine version does not support CPU hotplug"); 2001 exit(1); 2002 } 2003 boot_cores_nr = possible_cpus->len; 2004 } 2005 2006 for (i = 0; i < possible_cpus->len; i++) { 2007 int core_id = i * smp_threads; 2008 2009 if (mc->has_hotpluggable_cpus) { 2010 sPAPRDRConnector *drc = 2011 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2012 (core_id / smp_threads) * smt); 2013 2014 qemu_register_reset(spapr_drc_reset, drc); 2015 } 2016 2017 if (i < boot_cores_nr) { 2018 Object *core = object_new(type); 2019 int nr_threads = smp_threads; 2020 2021 /* Handle the partially filled core for older machine types */ 2022 if ((i + 1) * smp_threads >= smp_cpus) { 2023 nr_threads = smp_cpus - i * smp_threads; 2024 } 2025 2026 object_property_set_int(core, nr_threads, "nr-threads", 2027 &error_fatal); 2028 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2029 &error_fatal); 2030 object_property_set_bool(core, true, "realized", &error_fatal); 2031 } 2032 } 2033 g_free(type); 2034 } 2035 2036 /* pSeries LPAR / sPAPR hardware init */ 2037 static void ppc_spapr_init(MachineState *machine) 2038 { 2039 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2040 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2041 const char *kernel_filename = machine->kernel_filename; 2042 const char *initrd_filename = machine->initrd_filename; 2043 PCIHostState *phb; 2044 int i; 2045 MemoryRegion *sysmem = get_system_memory(); 2046 MemoryRegion *ram = g_new(MemoryRegion, 1); 2047 MemoryRegion *rma_region; 2048 void *rma = NULL; 2049 hwaddr rma_alloc_size; 2050 hwaddr node0_size = spapr_node0_size(); 2051 long load_limit, fw_size; 2052 char *filename; 2053 2054 msi_nonbroken = true; 2055 2056 QLIST_INIT(&spapr->phbs); 2057 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2058 2059 /* Allocate RMA if necessary */ 2060 rma_alloc_size = kvmppc_alloc_rma(&rma); 2061 2062 if (rma_alloc_size == -1) { 2063 error_report("Unable to create RMA"); 2064 exit(1); 2065 } 2066 2067 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 2068 spapr->rma_size = rma_alloc_size; 2069 } else { 2070 spapr->rma_size = node0_size; 2071 2072 /* With KVM, we don't actually know whether KVM supports an 2073 * unbounded RMA (PR KVM) or is limited by the hash table size 2074 * (HV KVM using VRMA), so we always assume the latter 2075 * 2076 * In that case, we also limit the initial allocations for RTAS 2077 * etc... to 256M since we have no way to know what the VRMA size 2078 * is going to be as it depends on the size of the hash table 2079 * isn't determined yet. 2080 */ 2081 if (kvm_enabled()) { 2082 spapr->vrma_adjust = 1; 2083 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2084 } 2085 2086 /* Actually we don't support unbounded RMA anymore since we 2087 * added proper emulation of HV mode. The max we can get is 2088 * 16G which also happens to be what we configure for PAPR 2089 * mode so make sure we don't do anything bigger than that 2090 */ 2091 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2092 } 2093 2094 if (spapr->rma_size > node0_size) { 2095 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2096 spapr->rma_size); 2097 exit(1); 2098 } 2099 2100 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2101 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2102 2103 /* Set up Interrupt Controller before we create the VCPUs */ 2104 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal); 2105 2106 /* Set up containers for ibm,client-set-architecture negotiated options */ 2107 spapr->ov5 = spapr_ovec_new(); 2108 spapr->ov5_cas = spapr_ovec_new(); 2109 2110 if (smc->dr_lmb_enabled) { 2111 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2112 spapr_validate_node_memory(machine, &error_fatal); 2113 } 2114 2115 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2116 if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) { 2117 /* KVM and TCG always allow GTSE with radix... */ 2118 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2119 } 2120 /* ... but not with hash (currently). */ 2121 2122 /* advertise support for dedicated HP event source to guests */ 2123 if (spapr->use_hotplug_event_source) { 2124 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2125 } 2126 2127 /* init CPUs */ 2128 if (machine->cpu_model == NULL) { 2129 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu; 2130 } 2131 2132 ppc_cpu_parse_features(machine->cpu_model); 2133 2134 spapr_init_cpus(spapr); 2135 2136 if (kvm_enabled()) { 2137 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2138 kvmppc_enable_logical_ci_hcalls(); 2139 kvmppc_enable_set_mode_hcall(); 2140 2141 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2142 kvmppc_enable_clear_ref_mod_hcalls(); 2143 } 2144 2145 /* allocate RAM */ 2146 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2147 machine->ram_size); 2148 memory_region_add_subregion(sysmem, 0, ram); 2149 2150 if (rma_alloc_size && rma) { 2151 rma_region = g_new(MemoryRegion, 1); 2152 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 2153 rma_alloc_size, rma); 2154 vmstate_register_ram_global(rma_region); 2155 memory_region_add_subregion(sysmem, 0, rma_region); 2156 } 2157 2158 /* initialize hotplug memory address space */ 2159 if (machine->ram_size < machine->maxram_size) { 2160 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 2161 /* 2162 * Limit the number of hotpluggable memory slots to half the number 2163 * slots that KVM supports, leaving the other half for PCI and other 2164 * devices. However ensure that number of slots doesn't drop below 32. 2165 */ 2166 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2167 SPAPR_MAX_RAM_SLOTS; 2168 2169 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2170 max_memslots = SPAPR_MAX_RAM_SLOTS; 2171 } 2172 if (machine->ram_slots > max_memslots) { 2173 error_report("Specified number of memory slots %" 2174 PRIu64" exceeds max supported %d", 2175 machine->ram_slots, max_memslots); 2176 exit(1); 2177 } 2178 2179 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 2180 SPAPR_HOTPLUG_MEM_ALIGN); 2181 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 2182 "hotplug-memory", hotplug_mem_size); 2183 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 2184 &spapr->hotplug_memory.mr); 2185 } 2186 2187 if (smc->dr_lmb_enabled) { 2188 spapr_create_lmb_dr_connectors(spapr); 2189 } 2190 2191 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2192 if (!filename) { 2193 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2194 exit(1); 2195 } 2196 spapr->rtas_size = get_image_size(filename); 2197 if (spapr->rtas_size < 0) { 2198 error_report("Could not get size of LPAR rtas '%s'", filename); 2199 exit(1); 2200 } 2201 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2202 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2203 error_report("Could not load LPAR rtas '%s'", filename); 2204 exit(1); 2205 } 2206 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2207 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2208 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2209 exit(1); 2210 } 2211 g_free(filename); 2212 2213 /* Set up RTAS event infrastructure */ 2214 spapr_events_init(spapr); 2215 2216 /* Set up the RTC RTAS interfaces */ 2217 spapr_rtc_create(spapr); 2218 2219 /* Set up VIO bus */ 2220 spapr->vio_bus = spapr_vio_bus_init(); 2221 2222 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 2223 if (serial_hds[i]) { 2224 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 2225 } 2226 } 2227 2228 /* We always have at least the nvram device on VIO */ 2229 spapr_create_nvram(spapr); 2230 2231 /* Set up PCI */ 2232 spapr_pci_rtas_init(); 2233 2234 phb = spapr_create_phb(spapr, 0); 2235 2236 for (i = 0; i < nb_nics; i++) { 2237 NICInfo *nd = &nd_table[i]; 2238 2239 if (!nd->model) { 2240 nd->model = g_strdup("ibmveth"); 2241 } 2242 2243 if (strcmp(nd->model, "ibmveth") == 0) { 2244 spapr_vlan_create(spapr->vio_bus, nd); 2245 } else { 2246 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2247 } 2248 } 2249 2250 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2251 spapr_vscsi_create(spapr->vio_bus); 2252 } 2253 2254 /* Graphics */ 2255 if (spapr_vga_init(phb->bus, &error_fatal)) { 2256 spapr->has_graphics = true; 2257 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2258 } 2259 2260 if (machine->usb) { 2261 if (smc->use_ohci_by_default) { 2262 pci_create_simple(phb->bus, -1, "pci-ohci"); 2263 } else { 2264 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2265 } 2266 2267 if (spapr->has_graphics) { 2268 USBBus *usb_bus = usb_bus_find(-1); 2269 2270 usb_create_simple(usb_bus, "usb-kbd"); 2271 usb_create_simple(usb_bus, "usb-mouse"); 2272 } 2273 } 2274 2275 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 2276 error_report( 2277 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2278 MIN_RMA_SLOF); 2279 exit(1); 2280 } 2281 2282 if (kernel_filename) { 2283 uint64_t lowaddr = 0; 2284 2285 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2286 NULL, NULL, &lowaddr, NULL, 1, 2287 PPC_ELF_MACHINE, 0, 0); 2288 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2289 spapr->kernel_size = load_elf(kernel_filename, 2290 translate_kernel_address, NULL, NULL, 2291 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2292 0, 0); 2293 spapr->kernel_le = spapr->kernel_size > 0; 2294 } 2295 if (spapr->kernel_size < 0) { 2296 error_report("error loading %s: %s", kernel_filename, 2297 load_elf_strerror(spapr->kernel_size)); 2298 exit(1); 2299 } 2300 2301 /* load initrd */ 2302 if (initrd_filename) { 2303 /* Try to locate the initrd in the gap between the kernel 2304 * and the firmware. Add a bit of space just in case 2305 */ 2306 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2307 + 0x1ffff) & ~0xffff; 2308 spapr->initrd_size = load_image_targphys(initrd_filename, 2309 spapr->initrd_base, 2310 load_limit 2311 - spapr->initrd_base); 2312 if (spapr->initrd_size < 0) { 2313 error_report("could not load initial ram disk '%s'", 2314 initrd_filename); 2315 exit(1); 2316 } 2317 } 2318 } 2319 2320 if (bios_name == NULL) { 2321 bios_name = FW_FILE_NAME; 2322 } 2323 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2324 if (!filename) { 2325 error_report("Could not find LPAR firmware '%s'", bios_name); 2326 exit(1); 2327 } 2328 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2329 if (fw_size <= 0) { 2330 error_report("Could not load LPAR firmware '%s'", filename); 2331 exit(1); 2332 } 2333 g_free(filename); 2334 2335 /* FIXME: Should register things through the MachineState's qdev 2336 * interface, this is a legacy from the sPAPREnvironment structure 2337 * which predated MachineState but had a similar function */ 2338 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2339 register_savevm_live(NULL, "spapr/htab", -1, 1, 2340 &savevm_htab_handlers, spapr); 2341 2342 qemu_register_boot_set(spapr_boot_set, spapr); 2343 2344 if (kvm_enabled()) { 2345 /* to stop and start vmclock */ 2346 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2347 &spapr->tb); 2348 2349 kvmppc_spapr_enable_inkernel_multitce(); 2350 } 2351 } 2352 2353 static int spapr_kvm_type(const char *vm_type) 2354 { 2355 if (!vm_type) { 2356 return 0; 2357 } 2358 2359 if (!strcmp(vm_type, "HV")) { 2360 return 1; 2361 } 2362 2363 if (!strcmp(vm_type, "PR")) { 2364 return 2; 2365 } 2366 2367 error_report("Unknown kvm-type specified '%s'", vm_type); 2368 exit(1); 2369 } 2370 2371 /* 2372 * Implementation of an interface to adjust firmware path 2373 * for the bootindex property handling. 2374 */ 2375 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2376 DeviceState *dev) 2377 { 2378 #define CAST(type, obj, name) \ 2379 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2380 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2381 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2382 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 2383 2384 if (d) { 2385 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2386 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2387 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2388 2389 if (spapr) { 2390 /* 2391 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2392 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2393 * in the top 16 bits of the 64-bit LUN 2394 */ 2395 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2396 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2397 (uint64_t)id << 48); 2398 } else if (virtio) { 2399 /* 2400 * We use SRP luns of the form 01000000 | (target << 8) | lun 2401 * in the top 32 bits of the 64-bit LUN 2402 * Note: the quote above is from SLOF and it is wrong, 2403 * the actual binding is: 2404 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2405 */ 2406 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2407 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2408 (uint64_t)id << 32); 2409 } else if (usb) { 2410 /* 2411 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2412 * in the top 32 bits of the 64-bit LUN 2413 */ 2414 unsigned usb_port = atoi(usb->port->path); 2415 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2416 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2417 (uint64_t)id << 32); 2418 } 2419 } 2420 2421 /* 2422 * SLOF probes the USB devices, and if it recognizes that the device is a 2423 * storage device, it changes its name to "storage" instead of "usb-host", 2424 * and additionally adds a child node for the SCSI LUN, so the correct 2425 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2426 */ 2427 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2428 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2429 if (usb_host_dev_is_scsi_storage(usbdev)) { 2430 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2431 } 2432 } 2433 2434 if (phb) { 2435 /* Replace "pci" with "pci@800000020000000" */ 2436 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2437 } 2438 2439 if (vsc) { 2440 /* Same logic as virtio above */ 2441 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 2442 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 2443 } 2444 2445 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 2446 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 2447 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 2448 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 2449 } 2450 2451 return NULL; 2452 } 2453 2454 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2455 { 2456 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2457 2458 return g_strdup(spapr->kvm_type); 2459 } 2460 2461 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2462 { 2463 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2464 2465 g_free(spapr->kvm_type); 2466 spapr->kvm_type = g_strdup(value); 2467 } 2468 2469 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2470 { 2471 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2472 2473 return spapr->use_hotplug_event_source; 2474 } 2475 2476 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2477 Error **errp) 2478 { 2479 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2480 2481 spapr->use_hotplug_event_source = value; 2482 } 2483 2484 static void spapr_machine_initfn(Object *obj) 2485 { 2486 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2487 2488 spapr->htab_fd = -1; 2489 spapr->use_hotplug_event_source = true; 2490 object_property_add_str(obj, "kvm-type", 2491 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2492 object_property_set_description(obj, "kvm-type", 2493 "Specifies the KVM virtualization mode (HV, PR)", 2494 NULL); 2495 object_property_add_bool(obj, "modern-hotplug-events", 2496 spapr_get_modern_hotplug_events, 2497 spapr_set_modern_hotplug_events, 2498 NULL); 2499 object_property_set_description(obj, "modern-hotplug-events", 2500 "Use dedicated hotplug event mechanism in" 2501 " place of standard EPOW events when possible" 2502 " (required for memory hot-unplug support)", 2503 NULL); 2504 } 2505 2506 static void spapr_machine_finalizefn(Object *obj) 2507 { 2508 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2509 2510 g_free(spapr->kvm_type); 2511 } 2512 2513 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 2514 { 2515 cpu_synchronize_state(cs); 2516 ppc_cpu_do_system_reset(cs); 2517 } 2518 2519 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2520 { 2521 CPUState *cs; 2522 2523 CPU_FOREACH(cs) { 2524 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 2525 } 2526 } 2527 2528 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2529 uint32_t node, bool dedicated_hp_event_source, 2530 Error **errp) 2531 { 2532 sPAPRDRConnector *drc; 2533 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2534 int i, fdt_offset, fdt_size; 2535 void *fdt; 2536 uint64_t addr = addr_start; 2537 2538 for (i = 0; i < nr_lmbs; i++) { 2539 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2540 addr / SPAPR_MEMORY_BLOCK_SIZE); 2541 g_assert(drc); 2542 2543 fdt = create_device_tree(&fdt_size); 2544 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2545 SPAPR_MEMORY_BLOCK_SIZE); 2546 2547 spapr_drc_attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); 2548 addr += SPAPR_MEMORY_BLOCK_SIZE; 2549 if (!dev->hotplugged) { 2550 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2551 /* guests expect coldplugged LMBs to be pre-allocated */ 2552 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); 2553 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); 2554 } 2555 } 2556 /* send hotplug notification to the 2557 * guest only in case of hotplugged memory 2558 */ 2559 if (dev->hotplugged) { 2560 if (dedicated_hp_event_source) { 2561 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2562 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2563 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2564 nr_lmbs, 2565 spapr_drc_index(drc)); 2566 } else { 2567 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 2568 nr_lmbs); 2569 } 2570 } 2571 } 2572 2573 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2574 uint32_t node, Error **errp) 2575 { 2576 Error *local_err = NULL; 2577 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2578 PCDIMMDevice *dimm = PC_DIMM(dev); 2579 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2580 MemoryRegion *mr = ddc->get_memory_region(dimm); 2581 uint64_t align = memory_region_get_alignment(mr); 2582 uint64_t size = memory_region_size(mr); 2583 uint64_t addr; 2584 2585 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 2586 if (local_err) { 2587 goto out; 2588 } 2589 2590 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2591 if (local_err) { 2592 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2593 goto out; 2594 } 2595 2596 spapr_add_lmbs(dev, addr, size, node, 2597 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 2598 &error_abort); 2599 2600 out: 2601 error_propagate(errp, local_err); 2602 } 2603 2604 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2605 Error **errp) 2606 { 2607 PCDIMMDevice *dimm = PC_DIMM(dev); 2608 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2609 MemoryRegion *mr = ddc->get_memory_region(dimm); 2610 uint64_t size = memory_region_size(mr); 2611 char *mem_dev; 2612 2613 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 2614 error_setg(errp, "Hotplugged memory size must be a multiple of " 2615 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2616 return; 2617 } 2618 2619 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); 2620 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { 2621 error_setg(errp, "Memory backend has bad page size. " 2622 "Use 'memory-backend-file' with correct mem-path."); 2623 goto out; 2624 } 2625 2626 out: 2627 g_free(mem_dev); 2628 } 2629 2630 struct sPAPRDIMMState { 2631 PCDIMMDevice *dimm; 2632 uint32_t nr_lmbs; 2633 QTAILQ_ENTRY(sPAPRDIMMState) next; 2634 }; 2635 2636 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, 2637 PCDIMMDevice *dimm) 2638 { 2639 sPAPRDIMMState *dimm_state = NULL; 2640 2641 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 2642 if (dimm_state->dimm == dimm) { 2643 break; 2644 } 2645 } 2646 return dimm_state; 2647 } 2648 2649 static void spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, 2650 sPAPRDIMMState *dimm_state) 2651 { 2652 g_assert(!spapr_pending_dimm_unplugs_find(spapr, dimm_state->dimm)); 2653 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, dimm_state, next); 2654 } 2655 2656 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, 2657 sPAPRDIMMState *dimm_state) 2658 { 2659 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 2660 g_free(dimm_state); 2661 } 2662 2663 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, 2664 PCDIMMDevice *dimm) 2665 { 2666 sPAPRDRConnector *drc; 2667 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2668 MemoryRegion *mr = ddc->get_memory_region(dimm); 2669 uint64_t size = memory_region_size(mr); 2670 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 2671 uint32_t avail_lmbs = 0; 2672 uint64_t addr_start, addr; 2673 int i; 2674 sPAPRDIMMState *ds; 2675 2676 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 2677 &error_abort); 2678 2679 addr = addr_start; 2680 for (i = 0; i < nr_lmbs; i++) { 2681 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2682 addr / SPAPR_MEMORY_BLOCK_SIZE); 2683 g_assert(drc); 2684 if (drc->dev) { 2685 avail_lmbs++; 2686 } 2687 addr += SPAPR_MEMORY_BLOCK_SIZE; 2688 } 2689 2690 ds = g_malloc0(sizeof(sPAPRDIMMState)); 2691 ds->nr_lmbs = avail_lmbs; 2692 ds->dimm = dimm; 2693 spapr_pending_dimm_unplugs_add(ms, ds); 2694 return ds; 2695 } 2696 2697 /* Callback to be called during DRC release. */ 2698 void spapr_lmb_release(DeviceState *dev) 2699 { 2700 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 2701 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 2702 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 2703 2704 /* This information will get lost if a migration occurs 2705 * during the unplug process. In this case recover it. */ 2706 if (ds == NULL) { 2707 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 2708 /* The DRC being examined by the caller at least must be counted */ 2709 g_assert(ds->nr_lmbs); 2710 } 2711 2712 if (--ds->nr_lmbs) { 2713 return; 2714 } 2715 2716 spapr_pending_dimm_unplugs_remove(spapr, ds); 2717 2718 /* 2719 * Now that all the LMBs have been removed by the guest, call the 2720 * pc-dimm unplug handler to cleanup up the pc-dimm device. 2721 */ 2722 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2723 } 2724 2725 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2726 Error **errp) 2727 { 2728 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2729 PCDIMMDevice *dimm = PC_DIMM(dev); 2730 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2731 MemoryRegion *mr = ddc->get_memory_region(dimm); 2732 2733 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2734 object_unparent(OBJECT(dev)); 2735 } 2736 2737 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 2738 DeviceState *dev, Error **errp) 2739 { 2740 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 2741 Error *local_err = NULL; 2742 PCDIMMDevice *dimm = PC_DIMM(dev); 2743 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2744 MemoryRegion *mr = ddc->get_memory_region(dimm); 2745 uint64_t size = memory_region_size(mr); 2746 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 2747 uint64_t addr_start, addr; 2748 int i; 2749 sPAPRDRConnector *drc; 2750 sPAPRDIMMState *ds; 2751 2752 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 2753 &local_err); 2754 if (local_err) { 2755 goto out; 2756 } 2757 2758 ds = g_malloc0(sizeof(sPAPRDIMMState)); 2759 ds->nr_lmbs = nr_lmbs; 2760 ds->dimm = dimm; 2761 spapr_pending_dimm_unplugs_add(spapr, ds); 2762 2763 addr = addr_start; 2764 for (i = 0; i < nr_lmbs; i++) { 2765 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2766 addr / SPAPR_MEMORY_BLOCK_SIZE); 2767 g_assert(drc); 2768 2769 spapr_drc_detach(drc, dev, errp); 2770 addr += SPAPR_MEMORY_BLOCK_SIZE; 2771 } 2772 2773 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2774 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2775 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2776 nr_lmbs, spapr_drc_index(drc)); 2777 out: 2778 error_propagate(errp, local_err); 2779 } 2780 2781 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 2782 sPAPRMachineState *spapr) 2783 { 2784 PowerPCCPU *cpu = POWERPC_CPU(cs); 2785 DeviceClass *dc = DEVICE_GET_CLASS(cs); 2786 int id = ppc_get_vcpu_dt_id(cpu); 2787 void *fdt; 2788 int offset, fdt_size; 2789 char *nodename; 2790 2791 fdt = create_device_tree(&fdt_size); 2792 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 2793 offset = fdt_add_subnode(fdt, 0, nodename); 2794 2795 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 2796 g_free(nodename); 2797 2798 *fdt_offset = offset; 2799 return fdt; 2800 } 2801 2802 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2803 Error **errp) 2804 { 2805 MachineState *ms = MACHINE(qdev_get_machine()); 2806 CPUCore *cc = CPU_CORE(dev); 2807 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 2808 2809 assert(core_slot); 2810 core_slot->cpu = NULL; 2811 object_unparent(OBJECT(dev)); 2812 } 2813 2814 /* Callback to be called during DRC release. */ 2815 void spapr_core_release(DeviceState *dev) 2816 { 2817 HotplugHandler *hotplug_ctrl; 2818 2819 hotplug_ctrl = qdev_get_hotplug_handler(dev); 2820 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2821 } 2822 2823 static 2824 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 2825 Error **errp) 2826 { 2827 int index; 2828 sPAPRDRConnector *drc; 2829 Error *local_err = NULL; 2830 CPUCore *cc = CPU_CORE(dev); 2831 int smt = kvmppc_smt_threads(); 2832 2833 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 2834 error_setg(errp, "Unable to find CPU core with core-id: %d", 2835 cc->core_id); 2836 return; 2837 } 2838 if (index == 0) { 2839 error_setg(errp, "Boot CPU core may not be unplugged"); 2840 return; 2841 } 2842 2843 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt); 2844 g_assert(drc); 2845 2846 spapr_drc_detach(drc, dev, &local_err); 2847 if (local_err) { 2848 error_propagate(errp, local_err); 2849 return; 2850 } 2851 2852 spapr_hotplug_req_remove_by_index(drc); 2853 } 2854 2855 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2856 Error **errp) 2857 { 2858 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 2859 MachineClass *mc = MACHINE_GET_CLASS(spapr); 2860 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 2861 CPUCore *cc = CPU_CORE(dev); 2862 CPUState *cs = CPU(core->threads); 2863 sPAPRDRConnector *drc; 2864 Error *local_err = NULL; 2865 void *fdt = NULL; 2866 int fdt_offset = 0; 2867 int smt = kvmppc_smt_threads(); 2868 CPUArchId *core_slot; 2869 int index; 2870 2871 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 2872 if (!core_slot) { 2873 error_setg(errp, "Unable to find CPU core with core-id: %d", 2874 cc->core_id); 2875 return; 2876 } 2877 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt); 2878 2879 g_assert(drc || !mc->has_hotpluggable_cpus); 2880 2881 /* 2882 * Setup CPU DT entries only for hotplugged CPUs. For boot time or 2883 * coldplugged CPUs DT entries are setup in spapr_build_fdt(). 2884 */ 2885 if (dev->hotplugged) { 2886 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 2887 } 2888 2889 if (drc) { 2890 spapr_drc_attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, 2891 &local_err); 2892 if (local_err) { 2893 g_free(fdt); 2894 error_propagate(errp, local_err); 2895 return; 2896 } 2897 } 2898 2899 if (dev->hotplugged) { 2900 /* 2901 * Send hotplug notification interrupt to the guest only in case 2902 * of hotplugged CPUs. 2903 */ 2904 spapr_hotplug_req_add_by_index(drc); 2905 } else { 2906 /* 2907 * Set the right DRC states for cold plugged CPU. 2908 */ 2909 if (drc) { 2910 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2911 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); 2912 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); 2913 } 2914 } 2915 core_slot->cpu = OBJECT(dev); 2916 } 2917 2918 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2919 Error **errp) 2920 { 2921 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 2922 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 2923 Error *local_err = NULL; 2924 CPUCore *cc = CPU_CORE(dev); 2925 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model); 2926 const char *type = object_get_typename(OBJECT(dev)); 2927 CPUArchId *core_slot; 2928 int index; 2929 2930 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 2931 error_setg(&local_err, "CPU hotplug not supported for this machine"); 2932 goto out; 2933 } 2934 2935 if (strcmp(base_core_type, type)) { 2936 error_setg(&local_err, "CPU core type should be %s", base_core_type); 2937 goto out; 2938 } 2939 2940 if (cc->core_id % smp_threads) { 2941 error_setg(&local_err, "invalid core id %d", cc->core_id); 2942 goto out; 2943 } 2944 2945 /* 2946 * In general we should have homogeneous threads-per-core, but old 2947 * (pre hotplug support) machine types allow the last core to have 2948 * reduced threads as a compatibility hack for when we allowed 2949 * total vcpus not a multiple of threads-per-core. 2950 */ 2951 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 2952 error_setg(errp, "invalid nr-threads %d, must be %d", 2953 cc->nr_threads, smp_threads); 2954 return; 2955 } 2956 2957 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 2958 if (!core_slot) { 2959 error_setg(&local_err, "core id %d out of range", cc->core_id); 2960 goto out; 2961 } 2962 2963 if (core_slot->cpu) { 2964 error_setg(&local_err, "core %d already populated", cc->core_id); 2965 goto out; 2966 } 2967 2968 numa_cpu_pre_plug(core_slot, dev, &local_err); 2969 2970 out: 2971 g_free(base_core_type); 2972 error_propagate(errp, local_err); 2973 } 2974 2975 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 2976 DeviceState *dev, Error **errp) 2977 { 2978 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 2979 2980 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2981 int node; 2982 2983 if (!smc->dr_lmb_enabled) { 2984 error_setg(errp, "Memory hotplug not supported for this machine"); 2985 return; 2986 } 2987 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 2988 if (*errp) { 2989 return; 2990 } 2991 if (node < 0 || node >= MAX_NODES) { 2992 error_setg(errp, "Invaild node %d", node); 2993 return; 2994 } 2995 2996 /* 2997 * Currently PowerPC kernel doesn't allow hot-adding memory to 2998 * memory-less node, but instead will silently add the memory 2999 * to the first node that has some memory. This causes two 3000 * unexpected behaviours for the user. 3001 * 3002 * - Memory gets hotplugged to a different node than what the user 3003 * specified. 3004 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 3005 * to memory-less node, a reboot will set things accordingly 3006 * and the previously hotplugged memory now ends in the right node. 3007 * This appears as if some memory moved from one node to another. 3008 * 3009 * So until kernel starts supporting memory hotplug to memory-less 3010 * nodes, just prevent such attempts upfront in QEMU. 3011 */ 3012 if (nb_numa_nodes && !numa_info[node].node_mem) { 3013 error_setg(errp, "Can't hotplug memory to memory-less node %d", 3014 node); 3015 return; 3016 } 3017 3018 spapr_memory_plug(hotplug_dev, dev, node, errp); 3019 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3020 spapr_core_plug(hotplug_dev, dev, errp); 3021 } 3022 } 3023 3024 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 3025 DeviceState *dev, Error **errp) 3026 { 3027 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 3028 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 3029 3030 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3031 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3032 spapr_memory_unplug(hotplug_dev, dev, errp); 3033 } else { 3034 error_setg(errp, "Memory hot unplug not supported for this guest"); 3035 } 3036 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3037 if (!mc->has_hotpluggable_cpus) { 3038 error_setg(errp, "CPU hot unplug not supported on this machine"); 3039 return; 3040 } 3041 spapr_core_unplug(hotplug_dev, dev, errp); 3042 } 3043 } 3044 3045 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 3046 DeviceState *dev, Error **errp) 3047 { 3048 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 3049 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 3050 3051 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3052 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3053 spapr_memory_unplug_request(hotplug_dev, dev, errp); 3054 } else { 3055 /* NOTE: this means there is a window after guest reset, prior to 3056 * CAS negotiation, where unplug requests will fail due to the 3057 * capability not being detected yet. This is a bit different than 3058 * the case with PCI unplug, where the events will be queued and 3059 * eventually handled by the guest after boot 3060 */ 3061 error_setg(errp, "Memory hot unplug not supported for this guest"); 3062 } 3063 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3064 if (!mc->has_hotpluggable_cpus) { 3065 error_setg(errp, "CPU hot unplug not supported on this machine"); 3066 return; 3067 } 3068 spapr_core_unplug_request(hotplug_dev, dev, errp); 3069 } 3070 } 3071 3072 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 3073 DeviceState *dev, Error **errp) 3074 { 3075 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3076 spapr_memory_pre_plug(hotplug_dev, dev, errp); 3077 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3078 spapr_core_pre_plug(hotplug_dev, dev, errp); 3079 } 3080 } 3081 3082 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 3083 DeviceState *dev) 3084 { 3085 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3086 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3087 return HOTPLUG_HANDLER(machine); 3088 } 3089 return NULL; 3090 } 3091 3092 static CpuInstanceProperties 3093 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 3094 { 3095 CPUArchId *core_slot; 3096 MachineClass *mc = MACHINE_GET_CLASS(machine); 3097 3098 /* make sure possible_cpu are intialized */ 3099 mc->possible_cpu_arch_ids(machine); 3100 /* get CPU core slot containing thread that matches cpu_index */ 3101 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 3102 assert(core_slot); 3103 return core_slot->props; 3104 } 3105 3106 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 3107 { 3108 int i; 3109 int spapr_max_cores = max_cpus / smp_threads; 3110 MachineClass *mc = MACHINE_GET_CLASS(machine); 3111 3112 if (!mc->has_hotpluggable_cpus) { 3113 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 3114 } 3115 if (machine->possible_cpus) { 3116 assert(machine->possible_cpus->len == spapr_max_cores); 3117 return machine->possible_cpus; 3118 } 3119 3120 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 3121 sizeof(CPUArchId) * spapr_max_cores); 3122 machine->possible_cpus->len = spapr_max_cores; 3123 for (i = 0; i < machine->possible_cpus->len; i++) { 3124 int core_id = i * smp_threads; 3125 3126 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 3127 machine->possible_cpus->cpus[i].arch_id = core_id; 3128 machine->possible_cpus->cpus[i].props.has_core_id = true; 3129 machine->possible_cpus->cpus[i].props.core_id = core_id; 3130 3131 /* default distribution of CPUs over NUMA nodes */ 3132 if (nb_numa_nodes) { 3133 /* preset values but do not enable them i.e. 'has_node_id = false', 3134 * numa init code will enable them later if manual mapping wasn't 3135 * present on CLI */ 3136 machine->possible_cpus->cpus[i].props.node_id = 3137 core_id / smp_threads / smp_cores % nb_numa_nodes; 3138 } 3139 } 3140 return machine->possible_cpus; 3141 } 3142 3143 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 3144 uint64_t *buid, hwaddr *pio, 3145 hwaddr *mmio32, hwaddr *mmio64, 3146 unsigned n_dma, uint32_t *liobns, Error **errp) 3147 { 3148 /* 3149 * New-style PHB window placement. 3150 * 3151 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 3152 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 3153 * windows. 3154 * 3155 * Some guest kernels can't work with MMIO windows above 1<<46 3156 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 3157 * 3158 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 3159 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 3160 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 3161 * 1TiB 64-bit MMIO windows for each PHB. 3162 */ 3163 const uint64_t base_buid = 0x800000020000000ULL; 3164 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 3165 SPAPR_PCI_MEM64_WIN_SIZE - 1) 3166 int i; 3167 3168 /* Sanity check natural alignments */ 3169 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3170 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3171 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 3172 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 3173 /* Sanity check bounds */ 3174 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 3175 SPAPR_PCI_MEM32_WIN_SIZE); 3176 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 3177 SPAPR_PCI_MEM64_WIN_SIZE); 3178 3179 if (index >= SPAPR_MAX_PHBS) { 3180 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 3181 SPAPR_MAX_PHBS - 1); 3182 return; 3183 } 3184 3185 *buid = base_buid + index; 3186 for (i = 0; i < n_dma; ++i) { 3187 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3188 } 3189 3190 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 3191 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 3192 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 3193 } 3194 3195 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 3196 { 3197 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3198 3199 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 3200 } 3201 3202 static void spapr_ics_resend(XICSFabric *dev) 3203 { 3204 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3205 3206 ics_resend(spapr->ics); 3207 } 3208 3209 static ICPState *spapr_icp_get(XICSFabric *xi, int cpu_dt_id) 3210 { 3211 PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id); 3212 3213 return cpu ? ICP(cpu->intc) : NULL; 3214 } 3215 3216 static void spapr_pic_print_info(InterruptStatsProvider *obj, 3217 Monitor *mon) 3218 { 3219 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3220 CPUState *cs; 3221 3222 CPU_FOREACH(cs) { 3223 PowerPCCPU *cpu = POWERPC_CPU(cs); 3224 3225 icp_pic_print_info(ICP(cpu->intc), mon); 3226 } 3227 3228 ics_pic_print_info(spapr->ics, mon); 3229 } 3230 3231 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3232 { 3233 MachineClass *mc = MACHINE_CLASS(oc); 3234 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3235 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3236 NMIClass *nc = NMI_CLASS(oc); 3237 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3238 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3239 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3240 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 3241 3242 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3243 3244 /* 3245 * We set up the default / latest behaviour here. The class_init 3246 * functions for the specific versioned machine types can override 3247 * these details for backwards compatibility 3248 */ 3249 mc->init = ppc_spapr_init; 3250 mc->reset = ppc_spapr_reset; 3251 mc->block_default_type = IF_SCSI; 3252 mc->max_cpus = 1024; 3253 mc->no_parallel = 1; 3254 mc->default_boot_order = ""; 3255 mc->default_ram_size = 512 * M_BYTE; 3256 mc->kvm_type = spapr_kvm_type; 3257 mc->has_dynamic_sysbus = true; 3258 mc->pci_allow_0_address = true; 3259 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3260 hc->pre_plug = spapr_machine_device_pre_plug; 3261 hc->plug = spapr_machine_device_plug; 3262 hc->unplug = spapr_machine_device_unplug; 3263 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 3264 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3265 hc->unplug_request = spapr_machine_device_unplug_request; 3266 3267 smc->dr_lmb_enabled = true; 3268 smc->tcg_default_cpu = "POWER8"; 3269 mc->has_hotpluggable_cpus = true; 3270 fwc->get_dev_path = spapr_get_fw_dev_path; 3271 nc->nmi_monitor_handler = spapr_nmi; 3272 smc->phb_placement = spapr_phb_placement; 3273 vhc->hypercall = emulate_spapr_hypercall; 3274 vhc->hpt_mask = spapr_hpt_mask; 3275 vhc->map_hptes = spapr_map_hptes; 3276 vhc->unmap_hptes = spapr_unmap_hptes; 3277 vhc->store_hpte = spapr_store_hpte; 3278 vhc->get_patbe = spapr_get_patbe; 3279 xic->ics_get = spapr_ics_get; 3280 xic->ics_resend = spapr_ics_resend; 3281 xic->icp_get = spapr_icp_get; 3282 ispc->print_info = spapr_pic_print_info; 3283 /* Force NUMA node memory size to be a multiple of 3284 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 3285 * in which LMBs are represented and hot-added 3286 */ 3287 mc->numa_mem_align_shift = 28; 3288 } 3289 3290 static const TypeInfo spapr_machine_info = { 3291 .name = TYPE_SPAPR_MACHINE, 3292 .parent = TYPE_MACHINE, 3293 .abstract = true, 3294 .instance_size = sizeof(sPAPRMachineState), 3295 .instance_init = spapr_machine_initfn, 3296 .instance_finalize = spapr_machine_finalizefn, 3297 .class_size = sizeof(sPAPRMachineClass), 3298 .class_init = spapr_machine_class_init, 3299 .interfaces = (InterfaceInfo[]) { 3300 { TYPE_FW_PATH_PROVIDER }, 3301 { TYPE_NMI }, 3302 { TYPE_HOTPLUG_HANDLER }, 3303 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 3304 { TYPE_XICS_FABRIC }, 3305 { TYPE_INTERRUPT_STATS_PROVIDER }, 3306 { } 3307 }, 3308 }; 3309 3310 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 3311 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 3312 void *data) \ 3313 { \ 3314 MachineClass *mc = MACHINE_CLASS(oc); \ 3315 spapr_machine_##suffix##_class_options(mc); \ 3316 if (latest) { \ 3317 mc->alias = "pseries"; \ 3318 mc->is_default = 1; \ 3319 } \ 3320 } \ 3321 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 3322 { \ 3323 MachineState *machine = MACHINE(obj); \ 3324 spapr_machine_##suffix##_instance_options(machine); \ 3325 } \ 3326 static const TypeInfo spapr_machine_##suffix##_info = { \ 3327 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 3328 .parent = TYPE_SPAPR_MACHINE, \ 3329 .class_init = spapr_machine_##suffix##_class_init, \ 3330 .instance_init = spapr_machine_##suffix##_instance_init, \ 3331 }; \ 3332 static void spapr_machine_register_##suffix(void) \ 3333 { \ 3334 type_register(&spapr_machine_##suffix##_info); \ 3335 } \ 3336 type_init(spapr_machine_register_##suffix) 3337 3338 /* 3339 * pseries-2.10 3340 */ 3341 static void spapr_machine_2_10_instance_options(MachineState *machine) 3342 { 3343 } 3344 3345 static void spapr_machine_2_10_class_options(MachineClass *mc) 3346 { 3347 /* Defaults for the latest behaviour inherited from the base class */ 3348 } 3349 3350 DEFINE_SPAPR_MACHINE(2_10, "2.10", true); 3351 3352 /* 3353 * pseries-2.9 3354 */ 3355 #define SPAPR_COMPAT_2_9 \ 3356 HW_COMPAT_2_9 3357 3358 static void spapr_machine_2_9_instance_options(MachineState *machine) 3359 { 3360 spapr_machine_2_10_instance_options(machine); 3361 } 3362 3363 static void spapr_machine_2_9_class_options(MachineClass *mc) 3364 { 3365 spapr_machine_2_10_class_options(mc); 3366 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); 3367 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 3368 } 3369 3370 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 3371 3372 /* 3373 * pseries-2.8 3374 */ 3375 #define SPAPR_COMPAT_2_8 \ 3376 HW_COMPAT_2_8 \ 3377 { \ 3378 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3379 .property = "pcie-extended-configuration-space", \ 3380 .value = "off", \ 3381 }, 3382 3383 static void spapr_machine_2_8_instance_options(MachineState *machine) 3384 { 3385 spapr_machine_2_9_instance_options(machine); 3386 } 3387 3388 static void spapr_machine_2_8_class_options(MachineClass *mc) 3389 { 3390 spapr_machine_2_9_class_options(mc); 3391 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 3392 mc->numa_mem_align_shift = 23; 3393 } 3394 3395 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 3396 3397 /* 3398 * pseries-2.7 3399 */ 3400 #define SPAPR_COMPAT_2_7 \ 3401 HW_COMPAT_2_7 \ 3402 { \ 3403 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3404 .property = "mem_win_size", \ 3405 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 3406 }, \ 3407 { \ 3408 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3409 .property = "mem64_win_size", \ 3410 .value = "0", \ 3411 }, \ 3412 { \ 3413 .driver = TYPE_POWERPC_CPU, \ 3414 .property = "pre-2.8-migration", \ 3415 .value = "on", \ 3416 }, \ 3417 { \ 3418 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3419 .property = "pre-2.8-migration", \ 3420 .value = "on", \ 3421 }, 3422 3423 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 3424 uint64_t *buid, hwaddr *pio, 3425 hwaddr *mmio32, hwaddr *mmio64, 3426 unsigned n_dma, uint32_t *liobns, Error **errp) 3427 { 3428 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 3429 const uint64_t base_buid = 0x800000020000000ULL; 3430 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 3431 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 3432 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 3433 const uint32_t max_index = 255; 3434 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 3435 3436 uint64_t ram_top = MACHINE(spapr)->ram_size; 3437 hwaddr phb0_base, phb_base; 3438 int i; 3439 3440 /* Do we have hotpluggable memory? */ 3441 if (MACHINE(spapr)->maxram_size > ram_top) { 3442 /* Can't just use maxram_size, because there may be an 3443 * alignment gap between normal and hotpluggable memory 3444 * regions */ 3445 ram_top = spapr->hotplug_memory.base + 3446 memory_region_size(&spapr->hotplug_memory.mr); 3447 } 3448 3449 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 3450 3451 if (index > max_index) { 3452 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 3453 max_index); 3454 return; 3455 } 3456 3457 *buid = base_buid + index; 3458 for (i = 0; i < n_dma; ++i) { 3459 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3460 } 3461 3462 phb_base = phb0_base + index * phb_spacing; 3463 *pio = phb_base + pio_offset; 3464 *mmio32 = phb_base + mmio_offset; 3465 /* 3466 * We don't set the 64-bit MMIO window, relying on the PHB's 3467 * fallback behaviour of automatically splitting a large "32-bit" 3468 * window into contiguous 32-bit and 64-bit windows 3469 */ 3470 } 3471 3472 static void spapr_machine_2_7_instance_options(MachineState *machine) 3473 { 3474 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 3475 3476 spapr_machine_2_8_instance_options(machine); 3477 spapr->use_hotplug_event_source = false; 3478 } 3479 3480 static void spapr_machine_2_7_class_options(MachineClass *mc) 3481 { 3482 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3483 3484 spapr_machine_2_8_class_options(mc); 3485 smc->tcg_default_cpu = "POWER7"; 3486 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 3487 smc->phb_placement = phb_placement_2_7; 3488 } 3489 3490 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 3491 3492 /* 3493 * pseries-2.6 3494 */ 3495 #define SPAPR_COMPAT_2_6 \ 3496 HW_COMPAT_2_6 \ 3497 { \ 3498 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3499 .property = "ddw",\ 3500 .value = stringify(off),\ 3501 }, 3502 3503 static void spapr_machine_2_6_instance_options(MachineState *machine) 3504 { 3505 spapr_machine_2_7_instance_options(machine); 3506 } 3507 3508 static void spapr_machine_2_6_class_options(MachineClass *mc) 3509 { 3510 spapr_machine_2_7_class_options(mc); 3511 mc->has_hotpluggable_cpus = false; 3512 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 3513 } 3514 3515 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 3516 3517 /* 3518 * pseries-2.5 3519 */ 3520 #define SPAPR_COMPAT_2_5 \ 3521 HW_COMPAT_2_5 \ 3522 { \ 3523 .driver = "spapr-vlan", \ 3524 .property = "use-rx-buffer-pools", \ 3525 .value = "off", \ 3526 }, 3527 3528 static void spapr_machine_2_5_instance_options(MachineState *machine) 3529 { 3530 spapr_machine_2_6_instance_options(machine); 3531 } 3532 3533 static void spapr_machine_2_5_class_options(MachineClass *mc) 3534 { 3535 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3536 3537 spapr_machine_2_6_class_options(mc); 3538 smc->use_ohci_by_default = true; 3539 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 3540 } 3541 3542 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 3543 3544 /* 3545 * pseries-2.4 3546 */ 3547 #define SPAPR_COMPAT_2_4 \ 3548 HW_COMPAT_2_4 3549 3550 static void spapr_machine_2_4_instance_options(MachineState *machine) 3551 { 3552 spapr_machine_2_5_instance_options(machine); 3553 } 3554 3555 static void spapr_machine_2_4_class_options(MachineClass *mc) 3556 { 3557 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3558 3559 spapr_machine_2_5_class_options(mc); 3560 smc->dr_lmb_enabled = false; 3561 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 3562 } 3563 3564 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 3565 3566 /* 3567 * pseries-2.3 3568 */ 3569 #define SPAPR_COMPAT_2_3 \ 3570 HW_COMPAT_2_3 \ 3571 {\ 3572 .driver = "spapr-pci-host-bridge",\ 3573 .property = "dynamic-reconfiguration",\ 3574 .value = "off",\ 3575 }, 3576 3577 static void spapr_machine_2_3_instance_options(MachineState *machine) 3578 { 3579 spapr_machine_2_4_instance_options(machine); 3580 savevm_skip_section_footers(); 3581 global_state_set_optional(); 3582 savevm_skip_configuration(); 3583 } 3584 3585 static void spapr_machine_2_3_class_options(MachineClass *mc) 3586 { 3587 spapr_machine_2_4_class_options(mc); 3588 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 3589 } 3590 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 3591 3592 /* 3593 * pseries-2.2 3594 */ 3595 3596 #define SPAPR_COMPAT_2_2 \ 3597 HW_COMPAT_2_2 \ 3598 {\ 3599 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3600 .property = "mem_win_size",\ 3601 .value = "0x20000000",\ 3602 }, 3603 3604 static void spapr_machine_2_2_instance_options(MachineState *machine) 3605 { 3606 spapr_machine_2_3_instance_options(machine); 3607 machine->suppress_vmdesc = true; 3608 } 3609 3610 static void spapr_machine_2_2_class_options(MachineClass *mc) 3611 { 3612 spapr_machine_2_3_class_options(mc); 3613 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 3614 } 3615 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 3616 3617 /* 3618 * pseries-2.1 3619 */ 3620 #define SPAPR_COMPAT_2_1 \ 3621 HW_COMPAT_2_1 3622 3623 static void spapr_machine_2_1_instance_options(MachineState *machine) 3624 { 3625 spapr_machine_2_2_instance_options(machine); 3626 } 3627 3628 static void spapr_machine_2_1_class_options(MachineClass *mc) 3629 { 3630 spapr_machine_2_2_class_options(mc); 3631 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 3632 } 3633 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 3634 3635 static void spapr_machine_register_types(void) 3636 { 3637 type_register_static(&spapr_machine_info); 3638 } 3639 3640 type_init(spapr_machine_register_types) 3641