1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qemu/datadir.h" 30 #include "qapi/error.h" 31 #include "qapi/qapi-events-machine.h" 32 #include "qapi/visitor.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/hostmem.h" 35 #include "sysemu/numa.h" 36 #include "sysemu/qtest.h" 37 #include "sysemu/reset.h" 38 #include "sysemu/runstate.h" 39 #include "qemu/log.h" 40 #include "hw/fw-path-provider.h" 41 #include "elf.h" 42 #include "net/net.h" 43 #include "sysemu/device_tree.h" 44 #include "sysemu/cpus.h" 45 #include "sysemu/hw_accel.h" 46 #include "kvm_ppc.h" 47 #include "migration/misc.h" 48 #include "migration/qemu-file-types.h" 49 #include "migration/global_state.h" 50 #include "migration/register.h" 51 #include "migration/blocker.h" 52 #include "mmu-hash64.h" 53 #include "mmu-book3s-v3.h" 54 #include "cpu-models.h" 55 #include "hw/core/cpu.h" 56 57 #include "hw/ppc/ppc.h" 58 #include "hw/loader.h" 59 60 #include "hw/ppc/fdt.h" 61 #include "hw/ppc/spapr.h" 62 #include "hw/ppc/spapr_vio.h" 63 #include "hw/qdev-properties.h" 64 #include "hw/pci-host/spapr.h" 65 #include "hw/pci/msi.h" 66 67 #include "hw/pci/pci.h" 68 #include "hw/scsi/scsi.h" 69 #include "hw/virtio/virtio-scsi.h" 70 #include "hw/virtio/vhost-scsi-common.h" 71 72 #include "exec/ram_addr.h" 73 #include "hw/usb.h" 74 #include "qemu/config-file.h" 75 #include "qemu/error-report.h" 76 #include "trace.h" 77 #include "hw/nmi.h" 78 #include "hw/intc/intc.h" 79 80 #include "hw/ppc/spapr_cpu_core.h" 81 #include "hw/mem/memory-device.h" 82 #include "hw/ppc/spapr_tpm_proxy.h" 83 #include "hw/ppc/spapr_nvdimm.h" 84 #include "hw/ppc/spapr_numa.h" 85 #include "hw/ppc/pef.h" 86 87 #include "monitor/monitor.h" 88 89 #include <libfdt.h> 90 91 /* SLOF memory layout: 92 * 93 * SLOF raw image loaded at 0, copies its romfs right below the flat 94 * device-tree, then position SLOF itself 31M below that 95 * 96 * So we set FW_OVERHEAD to 40MB which should account for all of that 97 * and more 98 * 99 * We load our kernel at 4M, leaving space for SLOF initial image 100 */ 101 #define FDT_MAX_ADDR 0x80000000 /* FDT must stay below that */ 102 #define FW_MAX_SIZE 0x400000 103 #define FW_FILE_NAME "slof.bin" 104 #define FW_OVERHEAD 0x2800000 105 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 106 107 #define MIN_RMA_SLOF (128 * MiB) 108 109 #define PHANDLE_INTC 0x00001111 110 111 /* These two functions implement the VCPU id numbering: one to compute them 112 * all and one to identify thread 0 of a VCORE. Any change to the first one 113 * is likely to have an impact on the second one, so let's keep them close. 114 */ 115 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 116 { 117 MachineState *ms = MACHINE(spapr); 118 unsigned int smp_threads = ms->smp.threads; 119 120 assert(spapr->vsmt); 121 return 122 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 123 } 124 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 125 PowerPCCPU *cpu) 126 { 127 assert(spapr->vsmt); 128 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 129 } 130 131 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 132 { 133 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 134 * and newer QEMUs don't even have them. In both cases, we don't want 135 * to send anything on the wire. 136 */ 137 return false; 138 } 139 140 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 141 .name = "icp/server", 142 .version_id = 1, 143 .minimum_version_id = 1, 144 .needed = pre_2_10_vmstate_dummy_icp_needed, 145 .fields = (VMStateField[]) { 146 VMSTATE_UNUSED(4), /* uint32_t xirr */ 147 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 148 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 149 VMSTATE_END_OF_LIST() 150 }, 151 }; 152 153 static void pre_2_10_vmstate_register_dummy_icp(int i) 154 { 155 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 156 (void *)(uintptr_t) i); 157 } 158 159 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 160 { 161 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 162 (void *)(uintptr_t) i); 163 } 164 165 int spapr_max_server_number(SpaprMachineState *spapr) 166 { 167 MachineState *ms = MACHINE(spapr); 168 169 assert(spapr->vsmt); 170 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 171 } 172 173 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 174 int smt_threads) 175 { 176 int i, ret = 0; 177 uint32_t servers_prop[smt_threads]; 178 uint32_t gservers_prop[smt_threads * 2]; 179 int index = spapr_get_vcpu_id(cpu); 180 181 if (cpu->compat_pvr) { 182 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 183 if (ret < 0) { 184 return ret; 185 } 186 } 187 188 /* Build interrupt servers and gservers properties */ 189 for (i = 0; i < smt_threads; i++) { 190 servers_prop[i] = cpu_to_be32(index + i); 191 /* Hack, direct the group queues back to cpu 0 */ 192 gservers_prop[i*2] = cpu_to_be32(index + i); 193 gservers_prop[i*2 + 1] = 0; 194 } 195 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 196 servers_prop, sizeof(servers_prop)); 197 if (ret < 0) { 198 return ret; 199 } 200 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 201 gservers_prop, sizeof(gservers_prop)); 202 203 return ret; 204 } 205 206 static void spapr_dt_pa_features(SpaprMachineState *spapr, 207 PowerPCCPU *cpu, 208 void *fdt, int offset) 209 { 210 uint8_t pa_features_206[] = { 6, 0, 211 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 212 uint8_t pa_features_207[] = { 24, 0, 213 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 214 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 215 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 216 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 217 uint8_t pa_features_300[] = { 66, 0, 218 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 219 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 220 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 221 /* 6: DS207 */ 222 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 223 /* 16: Vector */ 224 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 225 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 226 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 227 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 228 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 229 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 230 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 231 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 232 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 233 /* 42: PM, 44: PC RA, 46: SC vec'd */ 234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 235 /* 48: SIMD, 50: QP BFP, 52: String */ 236 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 237 /* 54: DecFP, 56: DecI, 58: SHA */ 238 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 239 /* 60: NM atomic, 62: RNG */ 240 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 241 }; 242 uint8_t *pa_features = NULL; 243 size_t pa_size; 244 245 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 246 pa_features = pa_features_206; 247 pa_size = sizeof(pa_features_206); 248 } 249 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 250 pa_features = pa_features_207; 251 pa_size = sizeof(pa_features_207); 252 } 253 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 254 pa_features = pa_features_300; 255 pa_size = sizeof(pa_features_300); 256 } 257 if (!pa_features) { 258 return; 259 } 260 261 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 262 /* 263 * Note: we keep CI large pages off by default because a 64K capable 264 * guest provisioned with large pages might otherwise try to map a qemu 265 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 266 * even if that qemu runs on a 4k host. 267 * We dd this bit back here if we are confident this is not an issue 268 */ 269 pa_features[3] |= 0x20; 270 } 271 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 272 pa_features[24] |= 0x80; /* Transactional memory support */ 273 } 274 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 275 /* Workaround for broken kernels that attempt (guest) radix 276 * mode when they can't handle it, if they see the radix bit set 277 * in pa-features. So hide it from them. */ 278 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 279 } 280 281 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 282 } 283 284 static hwaddr spapr_node0_size(MachineState *machine) 285 { 286 if (machine->numa_state->num_nodes) { 287 int i; 288 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 289 if (machine->numa_state->nodes[i].node_mem) { 290 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 291 machine->ram_size); 292 } 293 } 294 } 295 return machine->ram_size; 296 } 297 298 static void add_str(GString *s, const gchar *s1) 299 { 300 g_string_append_len(s, s1, strlen(s1) + 1); 301 } 302 303 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 304 hwaddr start, hwaddr size) 305 { 306 char mem_name[32]; 307 uint64_t mem_reg_property[2]; 308 int off; 309 310 mem_reg_property[0] = cpu_to_be64(start); 311 mem_reg_property[1] = cpu_to_be64(size); 312 313 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 314 off = fdt_add_subnode(fdt, 0, mem_name); 315 _FDT(off); 316 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 317 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 318 sizeof(mem_reg_property)))); 319 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 320 return off; 321 } 322 323 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 324 { 325 MemoryDeviceInfoList *info; 326 327 for (info = list; info; info = info->next) { 328 MemoryDeviceInfo *value = info->value; 329 330 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 331 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 332 333 if (addr >= pcdimm_info->addr && 334 addr < (pcdimm_info->addr + pcdimm_info->size)) { 335 return pcdimm_info->node; 336 } 337 } 338 } 339 340 return -1; 341 } 342 343 struct sPAPRDrconfCellV2 { 344 uint32_t seq_lmbs; 345 uint64_t base_addr; 346 uint32_t drc_index; 347 uint32_t aa_index; 348 uint32_t flags; 349 } QEMU_PACKED; 350 351 typedef struct DrconfCellQueue { 352 struct sPAPRDrconfCellV2 cell; 353 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 354 } DrconfCellQueue; 355 356 static DrconfCellQueue * 357 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 358 uint32_t drc_index, uint32_t aa_index, 359 uint32_t flags) 360 { 361 DrconfCellQueue *elem; 362 363 elem = g_malloc0(sizeof(*elem)); 364 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 365 elem->cell.base_addr = cpu_to_be64(base_addr); 366 elem->cell.drc_index = cpu_to_be32(drc_index); 367 elem->cell.aa_index = cpu_to_be32(aa_index); 368 elem->cell.flags = cpu_to_be32(flags); 369 370 return elem; 371 } 372 373 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 374 int offset, MemoryDeviceInfoList *dimms) 375 { 376 MachineState *machine = MACHINE(spapr); 377 uint8_t *int_buf, *cur_index; 378 int ret; 379 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 380 uint64_t addr, cur_addr, size; 381 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 382 uint64_t mem_end = machine->device_memory->base + 383 memory_region_size(&machine->device_memory->mr); 384 uint32_t node, buf_len, nr_entries = 0; 385 SpaprDrc *drc; 386 DrconfCellQueue *elem, *next; 387 MemoryDeviceInfoList *info; 388 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 389 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 390 391 /* Entry to cover RAM and the gap area */ 392 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 393 SPAPR_LMB_FLAGS_RESERVED | 394 SPAPR_LMB_FLAGS_DRC_INVALID); 395 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 396 nr_entries++; 397 398 cur_addr = machine->device_memory->base; 399 for (info = dimms; info; info = info->next) { 400 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 401 402 addr = di->addr; 403 size = di->size; 404 node = di->node; 405 406 /* 407 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 408 * area is marked hotpluggable in the next iteration for the bigger 409 * chunk including the NVDIMM occupied area. 410 */ 411 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 412 continue; 413 414 /* Entry for hot-pluggable area */ 415 if (cur_addr < addr) { 416 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 417 g_assert(drc); 418 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 419 cur_addr, spapr_drc_index(drc), -1, 0); 420 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 421 nr_entries++; 422 } 423 424 /* Entry for DIMM */ 425 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 426 g_assert(drc); 427 elem = spapr_get_drconf_cell(size / lmb_size, addr, 428 spapr_drc_index(drc), node, 429 (SPAPR_LMB_FLAGS_ASSIGNED | 430 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 431 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 432 nr_entries++; 433 cur_addr = addr + size; 434 } 435 436 /* Entry for remaining hotpluggable area */ 437 if (cur_addr < mem_end) { 438 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 439 g_assert(drc); 440 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 441 cur_addr, spapr_drc_index(drc), -1, 0); 442 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 443 nr_entries++; 444 } 445 446 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 447 int_buf = cur_index = g_malloc0(buf_len); 448 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 449 cur_index += sizeof(nr_entries); 450 451 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 452 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 453 cur_index += sizeof(elem->cell); 454 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 455 g_free(elem); 456 } 457 458 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 459 g_free(int_buf); 460 if (ret < 0) { 461 return -1; 462 } 463 return 0; 464 } 465 466 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 467 int offset, MemoryDeviceInfoList *dimms) 468 { 469 MachineState *machine = MACHINE(spapr); 470 int i, ret; 471 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 472 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 473 uint32_t nr_lmbs = (machine->device_memory->base + 474 memory_region_size(&machine->device_memory->mr)) / 475 lmb_size; 476 uint32_t *int_buf, *cur_index, buf_len; 477 478 /* 479 * Allocate enough buffer size to fit in ibm,dynamic-memory 480 */ 481 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 482 cur_index = int_buf = g_malloc0(buf_len); 483 int_buf[0] = cpu_to_be32(nr_lmbs); 484 cur_index++; 485 for (i = 0; i < nr_lmbs; i++) { 486 uint64_t addr = i * lmb_size; 487 uint32_t *dynamic_memory = cur_index; 488 489 if (i >= device_lmb_start) { 490 SpaprDrc *drc; 491 492 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 493 g_assert(drc); 494 495 dynamic_memory[0] = cpu_to_be32(addr >> 32); 496 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 497 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 498 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 499 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 500 if (memory_region_present(get_system_memory(), addr)) { 501 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 502 } else { 503 dynamic_memory[5] = cpu_to_be32(0); 504 } 505 } else { 506 /* 507 * LMB information for RMA, boot time RAM and gap b/n RAM and 508 * device memory region -- all these are marked as reserved 509 * and as having no valid DRC. 510 */ 511 dynamic_memory[0] = cpu_to_be32(addr >> 32); 512 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 513 dynamic_memory[2] = cpu_to_be32(0); 514 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 515 dynamic_memory[4] = cpu_to_be32(-1); 516 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 517 SPAPR_LMB_FLAGS_DRC_INVALID); 518 } 519 520 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 521 } 522 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 523 g_free(int_buf); 524 if (ret < 0) { 525 return -1; 526 } 527 return 0; 528 } 529 530 /* 531 * Adds ibm,dynamic-reconfiguration-memory node. 532 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 533 * of this device tree node. 534 */ 535 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 536 void *fdt) 537 { 538 MachineState *machine = MACHINE(spapr); 539 int ret, offset; 540 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 541 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 542 cpu_to_be32(lmb_size & 0xffffffff)}; 543 MemoryDeviceInfoList *dimms = NULL; 544 545 /* 546 * Don't create the node if there is no device memory 547 */ 548 if (machine->ram_size == machine->maxram_size) { 549 return 0; 550 } 551 552 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 553 554 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 555 sizeof(prop_lmb_size)); 556 if (ret < 0) { 557 return ret; 558 } 559 560 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 561 if (ret < 0) { 562 return ret; 563 } 564 565 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 566 if (ret < 0) { 567 return ret; 568 } 569 570 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 571 dimms = qmp_memory_device_list(); 572 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 573 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 574 } else { 575 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 576 } 577 qapi_free_MemoryDeviceInfoList(dimms); 578 579 if (ret < 0) { 580 return ret; 581 } 582 583 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 584 585 return ret; 586 } 587 588 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 589 { 590 MachineState *machine = MACHINE(spapr); 591 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 592 hwaddr mem_start, node_size; 593 int i, nb_nodes = machine->numa_state->num_nodes; 594 NodeInfo *nodes = machine->numa_state->nodes; 595 596 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 597 if (!nodes[i].node_mem) { 598 continue; 599 } 600 if (mem_start >= machine->ram_size) { 601 node_size = 0; 602 } else { 603 node_size = nodes[i].node_mem; 604 if (node_size > machine->ram_size - mem_start) { 605 node_size = machine->ram_size - mem_start; 606 } 607 } 608 if (!mem_start) { 609 /* spapr_machine_init() checks for rma_size <= node0_size 610 * already */ 611 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 612 mem_start += spapr->rma_size; 613 node_size -= spapr->rma_size; 614 } 615 for ( ; node_size; ) { 616 hwaddr sizetmp = pow2floor(node_size); 617 618 /* mem_start != 0 here */ 619 if (ctzl(mem_start) < ctzl(sizetmp)) { 620 sizetmp = 1ULL << ctzl(mem_start); 621 } 622 623 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 624 node_size -= sizetmp; 625 mem_start += sizetmp; 626 } 627 } 628 629 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 630 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 631 int ret; 632 633 g_assert(smc->dr_lmb_enabled); 634 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 635 if (ret) { 636 return ret; 637 } 638 } 639 640 return 0; 641 } 642 643 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 644 SpaprMachineState *spapr) 645 { 646 MachineState *ms = MACHINE(spapr); 647 PowerPCCPU *cpu = POWERPC_CPU(cs); 648 CPUPPCState *env = &cpu->env; 649 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 650 int index = spapr_get_vcpu_id(cpu); 651 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 652 0xffffffff, 0xffffffff}; 653 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 654 : SPAPR_TIMEBASE_FREQ; 655 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 656 uint32_t page_sizes_prop[64]; 657 size_t page_sizes_prop_size; 658 unsigned int smp_threads = ms->smp.threads; 659 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 660 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 661 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 662 SpaprDrc *drc; 663 int drc_index; 664 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 665 int i; 666 667 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 668 if (drc) { 669 drc_index = spapr_drc_index(drc); 670 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 671 } 672 673 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 674 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 675 676 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 677 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 678 env->dcache_line_size))); 679 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 680 env->dcache_line_size))); 681 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 682 env->icache_line_size))); 683 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 684 env->icache_line_size))); 685 686 if (pcc->l1_dcache_size) { 687 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 688 pcc->l1_dcache_size))); 689 } else { 690 warn_report("Unknown L1 dcache size for cpu"); 691 } 692 if (pcc->l1_icache_size) { 693 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 694 pcc->l1_icache_size))); 695 } else { 696 warn_report("Unknown L1 icache size for cpu"); 697 } 698 699 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 700 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 701 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 702 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 703 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 704 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 705 706 if (env->spr_cb[SPR_PURR].oea_read) { 707 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 708 } 709 if (env->spr_cb[SPR_SPURR].oea_read) { 710 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 711 } 712 713 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 714 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 715 segs, sizeof(segs)))); 716 } 717 718 /* Advertise VSX (vector extensions) if available 719 * 1 == VMX / Altivec available 720 * 2 == VSX available 721 * 722 * Only CPUs for which we create core types in spapr_cpu_core.c 723 * are possible, and all of those have VMX */ 724 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 725 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 726 } else { 727 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 728 } 729 730 /* Advertise DFP (Decimal Floating Point) if available 731 * 0 / no property == no DFP 732 * 1 == DFP available */ 733 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 734 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 735 } 736 737 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 738 sizeof(page_sizes_prop)); 739 if (page_sizes_prop_size) { 740 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 741 page_sizes_prop, page_sizes_prop_size))); 742 } 743 744 spapr_dt_pa_features(spapr, cpu, fdt, offset); 745 746 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 747 cs->cpu_index / vcpus_per_socket))); 748 749 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 750 pft_size_prop, sizeof(pft_size_prop)))); 751 752 if (ms->numa_state->num_nodes > 1) { 753 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 754 } 755 756 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 757 758 if (pcc->radix_page_info) { 759 for (i = 0; i < pcc->radix_page_info->count; i++) { 760 radix_AP_encodings[i] = 761 cpu_to_be32(pcc->radix_page_info->entries[i]); 762 } 763 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 764 radix_AP_encodings, 765 pcc->radix_page_info->count * 766 sizeof(radix_AP_encodings[0])))); 767 } 768 769 /* 770 * We set this property to let the guest know that it can use the large 771 * decrementer and its width in bits. 772 */ 773 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 774 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 775 pcc->lrg_decr_bits))); 776 } 777 778 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 779 { 780 CPUState **rev; 781 CPUState *cs; 782 int n_cpus; 783 int cpus_offset; 784 int i; 785 786 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 787 _FDT(cpus_offset); 788 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 789 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 790 791 /* 792 * We walk the CPUs in reverse order to ensure that CPU DT nodes 793 * created by fdt_add_subnode() end up in the right order in FDT 794 * for the guest kernel the enumerate the CPUs correctly. 795 * 796 * The CPU list cannot be traversed in reverse order, so we need 797 * to do extra work. 798 */ 799 n_cpus = 0; 800 rev = NULL; 801 CPU_FOREACH(cs) { 802 rev = g_renew(CPUState *, rev, n_cpus + 1); 803 rev[n_cpus++] = cs; 804 } 805 806 for (i = n_cpus - 1; i >= 0; i--) { 807 CPUState *cs = rev[i]; 808 PowerPCCPU *cpu = POWERPC_CPU(cs); 809 int index = spapr_get_vcpu_id(cpu); 810 DeviceClass *dc = DEVICE_GET_CLASS(cs); 811 g_autofree char *nodename = NULL; 812 int offset; 813 814 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 815 continue; 816 } 817 818 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 819 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 820 _FDT(offset); 821 spapr_dt_cpu(cs, fdt, offset, spapr); 822 } 823 824 g_free(rev); 825 } 826 827 static int spapr_dt_rng(void *fdt) 828 { 829 int node; 830 int ret; 831 832 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 833 if (node <= 0) { 834 return -1; 835 } 836 ret = fdt_setprop_string(fdt, node, "device_type", 837 "ibm,platform-facilities"); 838 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 839 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 840 841 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 842 if (node <= 0) { 843 return -1; 844 } 845 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 846 847 return ret ? -1 : 0; 848 } 849 850 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 851 { 852 MachineState *ms = MACHINE(spapr); 853 int rtas; 854 GString *hypertas = g_string_sized_new(256); 855 GString *qemu_hypertas = g_string_sized_new(256); 856 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 857 memory_region_size(&MACHINE(spapr)->device_memory->mr); 858 uint32_t lrdr_capacity[] = { 859 cpu_to_be32(max_device_addr >> 32), 860 cpu_to_be32(max_device_addr & 0xffffffff), 861 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 862 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 863 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 864 }; 865 866 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 867 868 /* hypertas */ 869 add_str(hypertas, "hcall-pft"); 870 add_str(hypertas, "hcall-term"); 871 add_str(hypertas, "hcall-dabr"); 872 add_str(hypertas, "hcall-interrupt"); 873 add_str(hypertas, "hcall-tce"); 874 add_str(hypertas, "hcall-vio"); 875 add_str(hypertas, "hcall-splpar"); 876 add_str(hypertas, "hcall-join"); 877 add_str(hypertas, "hcall-bulk"); 878 add_str(hypertas, "hcall-set-mode"); 879 add_str(hypertas, "hcall-sprg0"); 880 add_str(hypertas, "hcall-copy"); 881 add_str(hypertas, "hcall-debug"); 882 add_str(hypertas, "hcall-vphn"); 883 add_str(qemu_hypertas, "hcall-memop1"); 884 885 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 886 add_str(hypertas, "hcall-multi-tce"); 887 } 888 889 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 890 add_str(hypertas, "hcall-hpt-resize"); 891 } 892 893 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 894 hypertas->str, hypertas->len)); 895 g_string_free(hypertas, TRUE); 896 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 897 qemu_hypertas->str, qemu_hypertas->len)); 898 g_string_free(qemu_hypertas, TRUE); 899 900 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 901 902 /* 903 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 904 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 905 * 906 * The system reset requirements are driven by existing Linux and PowerVM 907 * implementation which (contrary to PAPR) saves r3 in the error log 908 * structure like machine check, so Linux expects to find the saved r3 909 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 910 * does not look at the error value). 911 * 912 * System reset interrupts are not subject to interlock like machine 913 * check, so this memory area could be corrupted if the sreset is 914 * interrupted by a machine check (or vice versa) if it was shared. To 915 * prevent this, system reset uses per-CPU areas for the sreset save 916 * area. A system reset that interrupts a system reset handler could 917 * still overwrite this area, but Linux doesn't try to recover in that 918 * case anyway. 919 * 920 * The extra 8 bytes is required because Linux's FWNMI error log check 921 * is off-by-one. 922 */ 923 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_ERROR_LOG_MAX + 924 ms->smp.max_cpus * sizeof(uint64_t)*2 + sizeof(uint64_t))); 925 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 926 RTAS_ERROR_LOG_MAX)); 927 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 928 RTAS_EVENT_SCAN_RATE)); 929 930 g_assert(msi_nonbroken); 931 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 932 933 /* 934 * According to PAPR, rtas ibm,os-term does not guarantee a return 935 * back to the guest cpu. 936 * 937 * While an additional ibm,extended-os-term property indicates 938 * that rtas call return will always occur. Set this property. 939 */ 940 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 941 942 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 943 lrdr_capacity, sizeof(lrdr_capacity))); 944 945 spapr_dt_rtas_tokens(fdt, rtas); 946 } 947 948 /* 949 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 950 * and the XIVE features that the guest may request and thus the valid 951 * values for bytes 23..26 of option vector 5: 952 */ 953 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 954 int chosen) 955 { 956 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 957 958 char val[2 * 4] = { 959 23, 0x00, /* XICS / XIVE mode */ 960 24, 0x00, /* Hash/Radix, filled in below. */ 961 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 962 26, 0x40, /* Radix options: GTSE == yes. */ 963 }; 964 965 if (spapr->irq->xics && spapr->irq->xive) { 966 val[1] = SPAPR_OV5_XIVE_BOTH; 967 } else if (spapr->irq->xive) { 968 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 969 } else { 970 assert(spapr->irq->xics); 971 val[1] = SPAPR_OV5_XIVE_LEGACY; 972 } 973 974 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 975 first_ppc_cpu->compat_pvr)) { 976 /* 977 * If we're in a pre POWER9 compat mode then the guest should 978 * do hash and use the legacy interrupt mode 979 */ 980 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 981 val[3] = 0x00; /* Hash */ 982 } else if (kvm_enabled()) { 983 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 984 val[3] = 0x80; /* OV5_MMU_BOTH */ 985 } else if (kvmppc_has_cap_mmu_radix()) { 986 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 987 } else { 988 val[3] = 0x00; /* Hash */ 989 } 990 } else { 991 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 992 val[3] = 0xC0; 993 } 994 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 995 val, sizeof(val))); 996 } 997 998 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 999 { 1000 MachineState *machine = MACHINE(spapr); 1001 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1002 int chosen; 1003 1004 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1005 1006 if (reset) { 1007 const char *boot_device = machine->boot_order; 1008 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1009 size_t cb = 0; 1010 char *bootlist = get_boot_devices_list(&cb); 1011 1012 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1013 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1014 machine->kernel_cmdline)); 1015 } 1016 1017 if (spapr->initrd_size) { 1018 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1019 spapr->initrd_base)); 1020 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1021 spapr->initrd_base + spapr->initrd_size)); 1022 } 1023 1024 if (spapr->kernel_size) { 1025 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1026 cpu_to_be64(spapr->kernel_size) }; 1027 1028 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1029 &kprop, sizeof(kprop))); 1030 if (spapr->kernel_le) { 1031 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1032 } 1033 } 1034 if (boot_menu) { 1035 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1036 } 1037 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1038 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1039 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1040 1041 if (cb && bootlist) { 1042 int i; 1043 1044 for (i = 0; i < cb; i++) { 1045 if (bootlist[i] == '\n') { 1046 bootlist[i] = ' '; 1047 } 1048 } 1049 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1050 } 1051 1052 if (boot_device && strlen(boot_device)) { 1053 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1054 } 1055 1056 if (!spapr->has_graphics && stdout_path) { 1057 /* 1058 * "linux,stdout-path" and "stdout" properties are 1059 * deprecated by linux kernel. New platforms should only 1060 * use the "stdout-path" property. Set the new property 1061 * and continue using older property to remain compatible 1062 * with the existing firmware. 1063 */ 1064 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1065 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1066 } 1067 1068 /* 1069 * We can deal with BAR reallocation just fine, advertise it 1070 * to the guest 1071 */ 1072 if (smc->linux_pci_probe) { 1073 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1074 } 1075 1076 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1077 1078 g_free(stdout_path); 1079 g_free(bootlist); 1080 } 1081 1082 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1083 } 1084 1085 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1086 { 1087 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1088 * KVM to work under pHyp with some guest co-operation */ 1089 int hypervisor; 1090 uint8_t hypercall[16]; 1091 1092 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1093 /* indicate KVM hypercall interface */ 1094 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1095 if (kvmppc_has_cap_fixup_hcalls()) { 1096 /* 1097 * Older KVM versions with older guest kernels were broken 1098 * with the magic page, don't allow the guest to map it. 1099 */ 1100 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1101 sizeof(hypercall))) { 1102 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1103 hypercall, sizeof(hypercall))); 1104 } 1105 } 1106 } 1107 1108 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1109 { 1110 MachineState *machine = MACHINE(spapr); 1111 MachineClass *mc = MACHINE_GET_CLASS(machine); 1112 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1113 uint32_t root_drc_type_mask = 0; 1114 int ret; 1115 void *fdt; 1116 SpaprPhbState *phb; 1117 char *buf; 1118 1119 fdt = g_malloc0(space); 1120 _FDT((fdt_create_empty_tree(fdt, space))); 1121 1122 /* Root node */ 1123 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1124 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1125 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1126 1127 /* Guest UUID & Name*/ 1128 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1129 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1130 if (qemu_uuid_set) { 1131 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1132 } 1133 g_free(buf); 1134 1135 if (qemu_get_vm_name()) { 1136 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1137 qemu_get_vm_name())); 1138 } 1139 1140 /* Host Model & Serial Number */ 1141 if (spapr->host_model) { 1142 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1143 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1144 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1145 g_free(buf); 1146 } 1147 1148 if (spapr->host_serial) { 1149 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1150 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1151 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1152 g_free(buf); 1153 } 1154 1155 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1156 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1157 1158 /* /interrupt controller */ 1159 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1160 1161 ret = spapr_dt_memory(spapr, fdt); 1162 if (ret < 0) { 1163 error_report("couldn't setup memory nodes in fdt"); 1164 exit(1); 1165 } 1166 1167 /* /vdevice */ 1168 spapr_dt_vdevice(spapr->vio_bus, fdt); 1169 1170 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1171 ret = spapr_dt_rng(fdt); 1172 if (ret < 0) { 1173 error_report("could not set up rng device in the fdt"); 1174 exit(1); 1175 } 1176 } 1177 1178 QLIST_FOREACH(phb, &spapr->phbs, list) { 1179 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1180 if (ret < 0) { 1181 error_report("couldn't setup PCI devices in fdt"); 1182 exit(1); 1183 } 1184 } 1185 1186 spapr_dt_cpus(fdt, spapr); 1187 1188 /* ibm,drc-indexes and friends */ 1189 if (smc->dr_lmb_enabled) { 1190 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; 1191 } 1192 if (smc->dr_phb_enabled) { 1193 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; 1194 } 1195 if (mc->nvdimm_supported) { 1196 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM; 1197 } 1198 if (root_drc_type_mask) { 1199 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask)); 1200 } 1201 1202 if (mc->has_hotpluggable_cpus) { 1203 int offset = fdt_path_offset(fdt, "/cpus"); 1204 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1205 if (ret < 0) { 1206 error_report("Couldn't set up CPU DR device tree properties"); 1207 exit(1); 1208 } 1209 } 1210 1211 /* /event-sources */ 1212 spapr_dt_events(spapr, fdt); 1213 1214 /* /rtas */ 1215 spapr_dt_rtas(spapr, fdt); 1216 1217 /* /chosen */ 1218 spapr_dt_chosen(spapr, fdt, reset); 1219 1220 /* /hypervisor */ 1221 if (kvm_enabled()) { 1222 spapr_dt_hypervisor(spapr, fdt); 1223 } 1224 1225 /* Build memory reserve map */ 1226 if (reset) { 1227 if (spapr->kernel_size) { 1228 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1229 spapr->kernel_size))); 1230 } 1231 if (spapr->initrd_size) { 1232 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1233 spapr->initrd_size))); 1234 } 1235 } 1236 1237 /* NVDIMM devices */ 1238 if (mc->nvdimm_supported) { 1239 spapr_dt_persistent_memory(spapr, fdt); 1240 } 1241 1242 return fdt; 1243 } 1244 1245 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1246 { 1247 SpaprMachineState *spapr = opaque; 1248 1249 return (addr & 0x0fffffff) + spapr->kernel_addr; 1250 } 1251 1252 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1253 PowerPCCPU *cpu) 1254 { 1255 CPUPPCState *env = &cpu->env; 1256 1257 /* The TCG path should also be holding the BQL at this point */ 1258 g_assert(qemu_mutex_iothread_locked()); 1259 1260 if (msr_pr) { 1261 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1262 env->gpr[3] = H_PRIVILEGE; 1263 } else { 1264 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1265 } 1266 } 1267 1268 struct LPCRSyncState { 1269 target_ulong value; 1270 target_ulong mask; 1271 }; 1272 1273 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1274 { 1275 struct LPCRSyncState *s = arg.host_ptr; 1276 PowerPCCPU *cpu = POWERPC_CPU(cs); 1277 CPUPPCState *env = &cpu->env; 1278 target_ulong lpcr; 1279 1280 cpu_synchronize_state(cs); 1281 lpcr = env->spr[SPR_LPCR]; 1282 lpcr &= ~s->mask; 1283 lpcr |= s->value; 1284 ppc_store_lpcr(cpu, lpcr); 1285 } 1286 1287 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1288 { 1289 CPUState *cs; 1290 struct LPCRSyncState s = { 1291 .value = value, 1292 .mask = mask 1293 }; 1294 CPU_FOREACH(cs) { 1295 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1296 } 1297 } 1298 1299 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1300 { 1301 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1302 1303 /* Copy PATE1:GR into PATE0:HR */ 1304 entry->dw0 = spapr->patb_entry & PATE0_HR; 1305 entry->dw1 = spapr->patb_entry; 1306 } 1307 1308 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1309 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1310 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1311 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1312 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1313 1314 /* 1315 * Get the fd to access the kernel htab, re-opening it if necessary 1316 */ 1317 static int get_htab_fd(SpaprMachineState *spapr) 1318 { 1319 Error *local_err = NULL; 1320 1321 if (spapr->htab_fd >= 0) { 1322 return spapr->htab_fd; 1323 } 1324 1325 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1326 if (spapr->htab_fd < 0) { 1327 error_report_err(local_err); 1328 } 1329 1330 return spapr->htab_fd; 1331 } 1332 1333 void close_htab_fd(SpaprMachineState *spapr) 1334 { 1335 if (spapr->htab_fd >= 0) { 1336 close(spapr->htab_fd); 1337 } 1338 spapr->htab_fd = -1; 1339 } 1340 1341 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1342 { 1343 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1344 1345 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1346 } 1347 1348 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1349 { 1350 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1351 1352 assert(kvm_enabled()); 1353 1354 if (!spapr->htab) { 1355 return 0; 1356 } 1357 1358 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1359 } 1360 1361 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1362 hwaddr ptex, int n) 1363 { 1364 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1365 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1366 1367 if (!spapr->htab) { 1368 /* 1369 * HTAB is controlled by KVM. Fetch into temporary buffer 1370 */ 1371 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1372 kvmppc_read_hptes(hptes, ptex, n); 1373 return hptes; 1374 } 1375 1376 /* 1377 * HTAB is controlled by QEMU. Just point to the internally 1378 * accessible PTEG. 1379 */ 1380 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1381 } 1382 1383 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1384 const ppc_hash_pte64_t *hptes, 1385 hwaddr ptex, int n) 1386 { 1387 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1388 1389 if (!spapr->htab) { 1390 g_free((void *)hptes); 1391 } 1392 1393 /* Nothing to do for qemu managed HPT */ 1394 } 1395 1396 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1397 uint64_t pte0, uint64_t pte1) 1398 { 1399 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1400 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1401 1402 if (!spapr->htab) { 1403 kvmppc_write_hpte(ptex, pte0, pte1); 1404 } else { 1405 if (pte0 & HPTE64_V_VALID) { 1406 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1407 /* 1408 * When setting valid, we write PTE1 first. This ensures 1409 * proper synchronization with the reading code in 1410 * ppc_hash64_pteg_search() 1411 */ 1412 smp_wmb(); 1413 stq_p(spapr->htab + offset, pte0); 1414 } else { 1415 stq_p(spapr->htab + offset, pte0); 1416 /* 1417 * When clearing it we set PTE0 first. This ensures proper 1418 * synchronization with the reading code in 1419 * ppc_hash64_pteg_search() 1420 */ 1421 smp_wmb(); 1422 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1423 } 1424 } 1425 } 1426 1427 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1428 uint64_t pte1) 1429 { 1430 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1431 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1432 1433 if (!spapr->htab) { 1434 /* There should always be a hash table when this is called */ 1435 error_report("spapr_hpte_set_c called with no hash table !"); 1436 return; 1437 } 1438 1439 /* The HW performs a non-atomic byte update */ 1440 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1441 } 1442 1443 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1444 uint64_t pte1) 1445 { 1446 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1447 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1448 1449 if (!spapr->htab) { 1450 /* There should always be a hash table when this is called */ 1451 error_report("spapr_hpte_set_r called with no hash table !"); 1452 return; 1453 } 1454 1455 /* The HW performs a non-atomic byte update */ 1456 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1457 } 1458 1459 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1460 { 1461 int shift; 1462 1463 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1464 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1465 * that's much more than is needed for Linux guests */ 1466 shift = ctz64(pow2ceil(ramsize)) - 7; 1467 shift = MAX(shift, 18); /* Minimum architected size */ 1468 shift = MIN(shift, 46); /* Maximum architected size */ 1469 return shift; 1470 } 1471 1472 void spapr_free_hpt(SpaprMachineState *spapr) 1473 { 1474 g_free(spapr->htab); 1475 spapr->htab = NULL; 1476 spapr->htab_shift = 0; 1477 close_htab_fd(spapr); 1478 } 1479 1480 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1481 { 1482 ERRP_GUARD(); 1483 long rc; 1484 1485 /* Clean up any HPT info from a previous boot */ 1486 spapr_free_hpt(spapr); 1487 1488 rc = kvmppc_reset_htab(shift); 1489 1490 if (rc == -EOPNOTSUPP) { 1491 error_setg(errp, "HPT not supported in nested guests"); 1492 return -EOPNOTSUPP; 1493 } 1494 1495 if (rc < 0) { 1496 /* kernel-side HPT needed, but couldn't allocate one */ 1497 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1498 shift); 1499 error_append_hint(errp, "Try smaller maxmem?\n"); 1500 return -errno; 1501 } else if (rc > 0) { 1502 /* kernel-side HPT allocated */ 1503 if (rc != shift) { 1504 error_setg(errp, 1505 "Requested order %d HPT, but kernel allocated order %ld", 1506 shift, rc); 1507 error_append_hint(errp, "Try smaller maxmem?\n"); 1508 return -ENOSPC; 1509 } 1510 1511 spapr->htab_shift = shift; 1512 spapr->htab = NULL; 1513 } else { 1514 /* kernel-side HPT not needed, allocate in userspace instead */ 1515 size_t size = 1ULL << shift; 1516 int i; 1517 1518 spapr->htab = qemu_memalign(size, size); 1519 memset(spapr->htab, 0, size); 1520 spapr->htab_shift = shift; 1521 1522 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1523 DIRTY_HPTE(HPTE(spapr->htab, i)); 1524 } 1525 } 1526 /* We're setting up a hash table, so that means we're not radix */ 1527 spapr->patb_entry = 0; 1528 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1529 return 0; 1530 } 1531 1532 void spapr_setup_hpt(SpaprMachineState *spapr) 1533 { 1534 int hpt_shift; 1535 1536 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1537 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1538 } else { 1539 uint64_t current_ram_size; 1540 1541 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1542 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1543 } 1544 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1545 1546 if (kvm_enabled()) { 1547 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1548 1549 /* Check our RMA fits in the possible VRMA */ 1550 if (vrma_limit < spapr->rma_size) { 1551 error_report("Unable to create %" HWADDR_PRIu 1552 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1553 spapr->rma_size / MiB, vrma_limit / MiB); 1554 exit(EXIT_FAILURE); 1555 } 1556 } 1557 } 1558 1559 static void spapr_machine_reset(MachineState *machine) 1560 { 1561 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1562 PowerPCCPU *first_ppc_cpu; 1563 hwaddr fdt_addr; 1564 void *fdt; 1565 int rc; 1566 1567 pef_kvm_reset(machine->cgs, &error_fatal); 1568 spapr_caps_apply(spapr); 1569 1570 first_ppc_cpu = POWERPC_CPU(first_cpu); 1571 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1572 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1573 spapr->max_compat_pvr)) { 1574 /* 1575 * If using KVM with radix mode available, VCPUs can be started 1576 * without a HPT because KVM will start them in radix mode. 1577 * Set the GR bit in PATE so that we know there is no HPT. 1578 */ 1579 spapr->patb_entry = PATE1_GR; 1580 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1581 } else { 1582 spapr_setup_hpt(spapr); 1583 } 1584 1585 qemu_devices_reset(); 1586 1587 spapr_ovec_cleanup(spapr->ov5_cas); 1588 spapr->ov5_cas = spapr_ovec_new(); 1589 1590 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1591 1592 /* 1593 * This is fixing some of the default configuration of the XIVE 1594 * devices. To be called after the reset of the machine devices. 1595 */ 1596 spapr_irq_reset(spapr, &error_fatal); 1597 1598 /* 1599 * There is no CAS under qtest. Simulate one to please the code that 1600 * depends on spapr->ov5_cas. This is especially needed to test device 1601 * unplug, so we do that before resetting the DRCs. 1602 */ 1603 if (qtest_enabled()) { 1604 spapr_ovec_cleanup(spapr->ov5_cas); 1605 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1606 } 1607 1608 /* DRC reset may cause a device to be unplugged. This will cause troubles 1609 * if this device is used by another device (eg, a running vhost backend 1610 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1611 * situations, we reset DRCs after all devices have been reset. 1612 */ 1613 spapr_drc_reset_all(spapr); 1614 1615 spapr_clear_pending_events(spapr); 1616 1617 /* 1618 * We place the device tree just below either the top of the RMA, 1619 * or just below 2GB, whichever is lower, so that it can be 1620 * processed with 32-bit real mode code if necessary 1621 */ 1622 fdt_addr = MIN(spapr->rma_size, FDT_MAX_ADDR) - FDT_MAX_SIZE; 1623 1624 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1625 1626 rc = fdt_pack(fdt); 1627 1628 /* Should only fail if we've built a corrupted tree */ 1629 assert(rc == 0); 1630 1631 /* Load the fdt */ 1632 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1633 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1634 g_free(spapr->fdt_blob); 1635 spapr->fdt_size = fdt_totalsize(fdt); 1636 spapr->fdt_initial_size = spapr->fdt_size; 1637 spapr->fdt_blob = fdt; 1638 1639 /* Set up the entry state */ 1640 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0); 1641 first_ppc_cpu->env.gpr[5] = 0; 1642 1643 spapr->fwnmi_system_reset_addr = -1; 1644 spapr->fwnmi_machine_check_addr = -1; 1645 spapr->fwnmi_machine_check_interlock = -1; 1646 1647 /* Signal all vCPUs waiting on this condition */ 1648 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1649 1650 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1651 } 1652 1653 static void spapr_create_nvram(SpaprMachineState *spapr) 1654 { 1655 DeviceState *dev = qdev_new("spapr-nvram"); 1656 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1657 1658 if (dinfo) { 1659 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1660 &error_fatal); 1661 } 1662 1663 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1664 1665 spapr->nvram = (struct SpaprNvram *)dev; 1666 } 1667 1668 static void spapr_rtc_create(SpaprMachineState *spapr) 1669 { 1670 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1671 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1672 &error_fatal, NULL); 1673 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1674 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1675 "date"); 1676 } 1677 1678 /* Returns whether we want to use VGA or not */ 1679 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1680 { 1681 switch (vga_interface_type) { 1682 case VGA_NONE: 1683 return false; 1684 case VGA_DEVICE: 1685 return true; 1686 case VGA_STD: 1687 case VGA_VIRTIO: 1688 case VGA_CIRRUS: 1689 return pci_vga_init(pci_bus) != NULL; 1690 default: 1691 error_setg(errp, 1692 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1693 return false; 1694 } 1695 } 1696 1697 static int spapr_pre_load(void *opaque) 1698 { 1699 int rc; 1700 1701 rc = spapr_caps_pre_load(opaque); 1702 if (rc) { 1703 return rc; 1704 } 1705 1706 return 0; 1707 } 1708 1709 static int spapr_post_load(void *opaque, int version_id) 1710 { 1711 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1712 int err = 0; 1713 1714 err = spapr_caps_post_migration(spapr); 1715 if (err) { 1716 return err; 1717 } 1718 1719 /* 1720 * In earlier versions, there was no separate qdev for the PAPR 1721 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1722 * So when migrating from those versions, poke the incoming offset 1723 * value into the RTC device 1724 */ 1725 if (version_id < 3) { 1726 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1727 if (err) { 1728 return err; 1729 } 1730 } 1731 1732 if (kvm_enabled() && spapr->patb_entry) { 1733 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1734 bool radix = !!(spapr->patb_entry & PATE1_GR); 1735 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1736 1737 /* 1738 * Update LPCR:HR and UPRT as they may not be set properly in 1739 * the stream 1740 */ 1741 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1742 LPCR_HR | LPCR_UPRT); 1743 1744 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1745 if (err) { 1746 error_report("Process table config unsupported by the host"); 1747 return -EINVAL; 1748 } 1749 } 1750 1751 err = spapr_irq_post_load(spapr, version_id); 1752 if (err) { 1753 return err; 1754 } 1755 1756 return err; 1757 } 1758 1759 static int spapr_pre_save(void *opaque) 1760 { 1761 int rc; 1762 1763 rc = spapr_caps_pre_save(opaque); 1764 if (rc) { 1765 return rc; 1766 } 1767 1768 return 0; 1769 } 1770 1771 static bool version_before_3(void *opaque, int version_id) 1772 { 1773 return version_id < 3; 1774 } 1775 1776 static bool spapr_pending_events_needed(void *opaque) 1777 { 1778 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1779 return !QTAILQ_EMPTY(&spapr->pending_events); 1780 } 1781 1782 static const VMStateDescription vmstate_spapr_event_entry = { 1783 .name = "spapr_event_log_entry", 1784 .version_id = 1, 1785 .minimum_version_id = 1, 1786 .fields = (VMStateField[]) { 1787 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1788 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1789 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1790 NULL, extended_length), 1791 VMSTATE_END_OF_LIST() 1792 }, 1793 }; 1794 1795 static const VMStateDescription vmstate_spapr_pending_events = { 1796 .name = "spapr_pending_events", 1797 .version_id = 1, 1798 .minimum_version_id = 1, 1799 .needed = spapr_pending_events_needed, 1800 .fields = (VMStateField[]) { 1801 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1802 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1803 VMSTATE_END_OF_LIST() 1804 }, 1805 }; 1806 1807 static bool spapr_ov5_cas_needed(void *opaque) 1808 { 1809 SpaprMachineState *spapr = opaque; 1810 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1811 bool cas_needed; 1812 1813 /* Prior to the introduction of SpaprOptionVector, we had two option 1814 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1815 * Both of these options encode machine topology into the device-tree 1816 * in such a way that the now-booted OS should still be able to interact 1817 * appropriately with QEMU regardless of what options were actually 1818 * negotiatied on the source side. 1819 * 1820 * As such, we can avoid migrating the CAS-negotiated options if these 1821 * are the only options available on the current machine/platform. 1822 * Since these are the only options available for pseries-2.7 and 1823 * earlier, this allows us to maintain old->new/new->old migration 1824 * compatibility. 1825 * 1826 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1827 * via default pseries-2.8 machines and explicit command-line parameters. 1828 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1829 * of the actual CAS-negotiated values to continue working properly. For 1830 * example, availability of memory unplug depends on knowing whether 1831 * OV5_HP_EVT was negotiated via CAS. 1832 * 1833 * Thus, for any cases where the set of available CAS-negotiatable 1834 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1835 * include the CAS-negotiated options in the migration stream, unless 1836 * if they affect boot time behaviour only. 1837 */ 1838 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1839 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1840 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1841 1842 /* We need extra information if we have any bits outside the mask 1843 * defined above */ 1844 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1845 1846 spapr_ovec_cleanup(ov5_mask); 1847 1848 return cas_needed; 1849 } 1850 1851 static const VMStateDescription vmstate_spapr_ov5_cas = { 1852 .name = "spapr_option_vector_ov5_cas", 1853 .version_id = 1, 1854 .minimum_version_id = 1, 1855 .needed = spapr_ov5_cas_needed, 1856 .fields = (VMStateField[]) { 1857 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1858 vmstate_spapr_ovec, SpaprOptionVector), 1859 VMSTATE_END_OF_LIST() 1860 }, 1861 }; 1862 1863 static bool spapr_patb_entry_needed(void *opaque) 1864 { 1865 SpaprMachineState *spapr = opaque; 1866 1867 return !!spapr->patb_entry; 1868 } 1869 1870 static const VMStateDescription vmstate_spapr_patb_entry = { 1871 .name = "spapr_patb_entry", 1872 .version_id = 1, 1873 .minimum_version_id = 1, 1874 .needed = spapr_patb_entry_needed, 1875 .fields = (VMStateField[]) { 1876 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1877 VMSTATE_END_OF_LIST() 1878 }, 1879 }; 1880 1881 static bool spapr_irq_map_needed(void *opaque) 1882 { 1883 SpaprMachineState *spapr = opaque; 1884 1885 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1886 } 1887 1888 static const VMStateDescription vmstate_spapr_irq_map = { 1889 .name = "spapr_irq_map", 1890 .version_id = 1, 1891 .minimum_version_id = 1, 1892 .needed = spapr_irq_map_needed, 1893 .fields = (VMStateField[]) { 1894 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1895 VMSTATE_END_OF_LIST() 1896 }, 1897 }; 1898 1899 static bool spapr_dtb_needed(void *opaque) 1900 { 1901 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1902 1903 return smc->update_dt_enabled; 1904 } 1905 1906 static int spapr_dtb_pre_load(void *opaque) 1907 { 1908 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1909 1910 g_free(spapr->fdt_blob); 1911 spapr->fdt_blob = NULL; 1912 spapr->fdt_size = 0; 1913 1914 return 0; 1915 } 1916 1917 static const VMStateDescription vmstate_spapr_dtb = { 1918 .name = "spapr_dtb", 1919 .version_id = 1, 1920 .minimum_version_id = 1, 1921 .needed = spapr_dtb_needed, 1922 .pre_load = spapr_dtb_pre_load, 1923 .fields = (VMStateField[]) { 1924 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1925 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1926 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1927 fdt_size), 1928 VMSTATE_END_OF_LIST() 1929 }, 1930 }; 1931 1932 static bool spapr_fwnmi_needed(void *opaque) 1933 { 1934 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1935 1936 return spapr->fwnmi_machine_check_addr != -1; 1937 } 1938 1939 static int spapr_fwnmi_pre_save(void *opaque) 1940 { 1941 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1942 1943 /* 1944 * Check if machine check handling is in progress and print a 1945 * warning message. 1946 */ 1947 if (spapr->fwnmi_machine_check_interlock != -1) { 1948 warn_report("A machine check is being handled during migration. The" 1949 "handler may run and log hardware error on the destination"); 1950 } 1951 1952 return 0; 1953 } 1954 1955 static const VMStateDescription vmstate_spapr_fwnmi = { 1956 .name = "spapr_fwnmi", 1957 .version_id = 1, 1958 .minimum_version_id = 1, 1959 .needed = spapr_fwnmi_needed, 1960 .pre_save = spapr_fwnmi_pre_save, 1961 .fields = (VMStateField[]) { 1962 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 1963 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 1964 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 1965 VMSTATE_END_OF_LIST() 1966 }, 1967 }; 1968 1969 static const VMStateDescription vmstate_spapr = { 1970 .name = "spapr", 1971 .version_id = 3, 1972 .minimum_version_id = 1, 1973 .pre_load = spapr_pre_load, 1974 .post_load = spapr_post_load, 1975 .pre_save = spapr_pre_save, 1976 .fields = (VMStateField[]) { 1977 /* used to be @next_irq */ 1978 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1979 1980 /* RTC offset */ 1981 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 1982 1983 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 1984 VMSTATE_END_OF_LIST() 1985 }, 1986 .subsections = (const VMStateDescription*[]) { 1987 &vmstate_spapr_ov5_cas, 1988 &vmstate_spapr_patb_entry, 1989 &vmstate_spapr_pending_events, 1990 &vmstate_spapr_cap_htm, 1991 &vmstate_spapr_cap_vsx, 1992 &vmstate_spapr_cap_dfp, 1993 &vmstate_spapr_cap_cfpc, 1994 &vmstate_spapr_cap_sbbc, 1995 &vmstate_spapr_cap_ibs, 1996 &vmstate_spapr_cap_hpt_maxpagesize, 1997 &vmstate_spapr_irq_map, 1998 &vmstate_spapr_cap_nested_kvm_hv, 1999 &vmstate_spapr_dtb, 2000 &vmstate_spapr_cap_large_decr, 2001 &vmstate_spapr_cap_ccf_assist, 2002 &vmstate_spapr_cap_fwnmi, 2003 &vmstate_spapr_fwnmi, 2004 NULL 2005 } 2006 }; 2007 2008 static int htab_save_setup(QEMUFile *f, void *opaque) 2009 { 2010 SpaprMachineState *spapr = opaque; 2011 2012 /* "Iteration" header */ 2013 if (!spapr->htab_shift) { 2014 qemu_put_be32(f, -1); 2015 } else { 2016 qemu_put_be32(f, spapr->htab_shift); 2017 } 2018 2019 if (spapr->htab) { 2020 spapr->htab_save_index = 0; 2021 spapr->htab_first_pass = true; 2022 } else { 2023 if (spapr->htab_shift) { 2024 assert(kvm_enabled()); 2025 } 2026 } 2027 2028 2029 return 0; 2030 } 2031 2032 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2033 int chunkstart, int n_valid, int n_invalid) 2034 { 2035 qemu_put_be32(f, chunkstart); 2036 qemu_put_be16(f, n_valid); 2037 qemu_put_be16(f, n_invalid); 2038 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2039 HASH_PTE_SIZE_64 * n_valid); 2040 } 2041 2042 static void htab_save_end_marker(QEMUFile *f) 2043 { 2044 qemu_put_be32(f, 0); 2045 qemu_put_be16(f, 0); 2046 qemu_put_be16(f, 0); 2047 } 2048 2049 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2050 int64_t max_ns) 2051 { 2052 bool has_timeout = max_ns != -1; 2053 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2054 int index = spapr->htab_save_index; 2055 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2056 2057 assert(spapr->htab_first_pass); 2058 2059 do { 2060 int chunkstart; 2061 2062 /* Consume invalid HPTEs */ 2063 while ((index < htabslots) 2064 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2065 CLEAN_HPTE(HPTE(spapr->htab, index)); 2066 index++; 2067 } 2068 2069 /* Consume valid HPTEs */ 2070 chunkstart = index; 2071 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2072 && HPTE_VALID(HPTE(spapr->htab, index))) { 2073 CLEAN_HPTE(HPTE(spapr->htab, index)); 2074 index++; 2075 } 2076 2077 if (index > chunkstart) { 2078 int n_valid = index - chunkstart; 2079 2080 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2081 2082 if (has_timeout && 2083 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2084 break; 2085 } 2086 } 2087 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2088 2089 if (index >= htabslots) { 2090 assert(index == htabslots); 2091 index = 0; 2092 spapr->htab_first_pass = false; 2093 } 2094 spapr->htab_save_index = index; 2095 } 2096 2097 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2098 int64_t max_ns) 2099 { 2100 bool final = max_ns < 0; 2101 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2102 int examined = 0, sent = 0; 2103 int index = spapr->htab_save_index; 2104 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2105 2106 assert(!spapr->htab_first_pass); 2107 2108 do { 2109 int chunkstart, invalidstart; 2110 2111 /* Consume non-dirty HPTEs */ 2112 while ((index < htabslots) 2113 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2114 index++; 2115 examined++; 2116 } 2117 2118 chunkstart = index; 2119 /* Consume valid dirty HPTEs */ 2120 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2121 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2122 && HPTE_VALID(HPTE(spapr->htab, index))) { 2123 CLEAN_HPTE(HPTE(spapr->htab, index)); 2124 index++; 2125 examined++; 2126 } 2127 2128 invalidstart = index; 2129 /* Consume invalid dirty HPTEs */ 2130 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2131 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2132 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2133 CLEAN_HPTE(HPTE(spapr->htab, index)); 2134 index++; 2135 examined++; 2136 } 2137 2138 if (index > chunkstart) { 2139 int n_valid = invalidstart - chunkstart; 2140 int n_invalid = index - invalidstart; 2141 2142 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2143 sent += index - chunkstart; 2144 2145 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2146 break; 2147 } 2148 } 2149 2150 if (examined >= htabslots) { 2151 break; 2152 } 2153 2154 if (index >= htabslots) { 2155 assert(index == htabslots); 2156 index = 0; 2157 } 2158 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2159 2160 if (index >= htabslots) { 2161 assert(index == htabslots); 2162 index = 0; 2163 } 2164 2165 spapr->htab_save_index = index; 2166 2167 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2168 } 2169 2170 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2171 #define MAX_KVM_BUF_SIZE 2048 2172 2173 static int htab_save_iterate(QEMUFile *f, void *opaque) 2174 { 2175 SpaprMachineState *spapr = opaque; 2176 int fd; 2177 int rc = 0; 2178 2179 /* Iteration header */ 2180 if (!spapr->htab_shift) { 2181 qemu_put_be32(f, -1); 2182 return 1; 2183 } else { 2184 qemu_put_be32(f, 0); 2185 } 2186 2187 if (!spapr->htab) { 2188 assert(kvm_enabled()); 2189 2190 fd = get_htab_fd(spapr); 2191 if (fd < 0) { 2192 return fd; 2193 } 2194 2195 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2196 if (rc < 0) { 2197 return rc; 2198 } 2199 } else if (spapr->htab_first_pass) { 2200 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2201 } else { 2202 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2203 } 2204 2205 htab_save_end_marker(f); 2206 2207 return rc; 2208 } 2209 2210 static int htab_save_complete(QEMUFile *f, void *opaque) 2211 { 2212 SpaprMachineState *spapr = opaque; 2213 int fd; 2214 2215 /* Iteration header */ 2216 if (!spapr->htab_shift) { 2217 qemu_put_be32(f, -1); 2218 return 0; 2219 } else { 2220 qemu_put_be32(f, 0); 2221 } 2222 2223 if (!spapr->htab) { 2224 int rc; 2225 2226 assert(kvm_enabled()); 2227 2228 fd = get_htab_fd(spapr); 2229 if (fd < 0) { 2230 return fd; 2231 } 2232 2233 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2234 if (rc < 0) { 2235 return rc; 2236 } 2237 } else { 2238 if (spapr->htab_first_pass) { 2239 htab_save_first_pass(f, spapr, -1); 2240 } 2241 htab_save_later_pass(f, spapr, -1); 2242 } 2243 2244 /* End marker */ 2245 htab_save_end_marker(f); 2246 2247 return 0; 2248 } 2249 2250 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2251 { 2252 SpaprMachineState *spapr = opaque; 2253 uint32_t section_hdr; 2254 int fd = -1; 2255 Error *local_err = NULL; 2256 2257 if (version_id < 1 || version_id > 1) { 2258 error_report("htab_load() bad version"); 2259 return -EINVAL; 2260 } 2261 2262 section_hdr = qemu_get_be32(f); 2263 2264 if (section_hdr == -1) { 2265 spapr_free_hpt(spapr); 2266 return 0; 2267 } 2268 2269 if (section_hdr) { 2270 int ret; 2271 2272 /* First section gives the htab size */ 2273 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2274 if (ret < 0) { 2275 error_report_err(local_err); 2276 return ret; 2277 } 2278 return 0; 2279 } 2280 2281 if (!spapr->htab) { 2282 assert(kvm_enabled()); 2283 2284 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2285 if (fd < 0) { 2286 error_report_err(local_err); 2287 return fd; 2288 } 2289 } 2290 2291 while (true) { 2292 uint32_t index; 2293 uint16_t n_valid, n_invalid; 2294 2295 index = qemu_get_be32(f); 2296 n_valid = qemu_get_be16(f); 2297 n_invalid = qemu_get_be16(f); 2298 2299 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2300 /* End of Stream */ 2301 break; 2302 } 2303 2304 if ((index + n_valid + n_invalid) > 2305 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2306 /* Bad index in stream */ 2307 error_report( 2308 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2309 index, n_valid, n_invalid, spapr->htab_shift); 2310 return -EINVAL; 2311 } 2312 2313 if (spapr->htab) { 2314 if (n_valid) { 2315 qemu_get_buffer(f, HPTE(spapr->htab, index), 2316 HASH_PTE_SIZE_64 * n_valid); 2317 } 2318 if (n_invalid) { 2319 memset(HPTE(spapr->htab, index + n_valid), 0, 2320 HASH_PTE_SIZE_64 * n_invalid); 2321 } 2322 } else { 2323 int rc; 2324 2325 assert(fd >= 0); 2326 2327 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2328 &local_err); 2329 if (rc < 0) { 2330 error_report_err(local_err); 2331 return rc; 2332 } 2333 } 2334 } 2335 2336 if (!spapr->htab) { 2337 assert(fd >= 0); 2338 close(fd); 2339 } 2340 2341 return 0; 2342 } 2343 2344 static void htab_save_cleanup(void *opaque) 2345 { 2346 SpaprMachineState *spapr = opaque; 2347 2348 close_htab_fd(spapr); 2349 } 2350 2351 static SaveVMHandlers savevm_htab_handlers = { 2352 .save_setup = htab_save_setup, 2353 .save_live_iterate = htab_save_iterate, 2354 .save_live_complete_precopy = htab_save_complete, 2355 .save_cleanup = htab_save_cleanup, 2356 .load_state = htab_load, 2357 }; 2358 2359 static void spapr_boot_set(void *opaque, const char *boot_device, 2360 Error **errp) 2361 { 2362 MachineState *machine = MACHINE(opaque); 2363 machine->boot_order = g_strdup(boot_device); 2364 } 2365 2366 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2367 { 2368 MachineState *machine = MACHINE(spapr); 2369 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2370 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2371 int i; 2372 2373 for (i = 0; i < nr_lmbs; i++) { 2374 uint64_t addr; 2375 2376 addr = i * lmb_size + machine->device_memory->base; 2377 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2378 addr / lmb_size); 2379 } 2380 } 2381 2382 /* 2383 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2384 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2385 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2386 */ 2387 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2388 { 2389 int i; 2390 2391 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2392 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2393 " is not aligned to %" PRIu64 " MiB", 2394 machine->ram_size, 2395 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2396 return; 2397 } 2398 2399 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2400 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2401 " is not aligned to %" PRIu64 " MiB", 2402 machine->ram_size, 2403 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2404 return; 2405 } 2406 2407 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2408 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2409 error_setg(errp, 2410 "Node %d memory size 0x%" PRIx64 2411 " is not aligned to %" PRIu64 " MiB", 2412 i, machine->numa_state->nodes[i].node_mem, 2413 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2414 return; 2415 } 2416 } 2417 } 2418 2419 /* find cpu slot in machine->possible_cpus by core_id */ 2420 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2421 { 2422 int index = id / ms->smp.threads; 2423 2424 if (index >= ms->possible_cpus->len) { 2425 return NULL; 2426 } 2427 if (idx) { 2428 *idx = index; 2429 } 2430 return &ms->possible_cpus->cpus[index]; 2431 } 2432 2433 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2434 { 2435 MachineState *ms = MACHINE(spapr); 2436 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2437 Error *local_err = NULL; 2438 bool vsmt_user = !!spapr->vsmt; 2439 int kvm_smt = kvmppc_smt_threads(); 2440 int ret; 2441 unsigned int smp_threads = ms->smp.threads; 2442 2443 if (!kvm_enabled() && (smp_threads > 1)) { 2444 error_setg(errp, "TCG cannot support more than 1 thread/core " 2445 "on a pseries machine"); 2446 return; 2447 } 2448 if (!is_power_of_2(smp_threads)) { 2449 error_setg(errp, "Cannot support %d threads/core on a pseries " 2450 "machine because it must be a power of 2", smp_threads); 2451 return; 2452 } 2453 2454 /* Detemine the VSMT mode to use: */ 2455 if (vsmt_user) { 2456 if (spapr->vsmt < smp_threads) { 2457 error_setg(errp, "Cannot support VSMT mode %d" 2458 " because it must be >= threads/core (%d)", 2459 spapr->vsmt, smp_threads); 2460 return; 2461 } 2462 /* In this case, spapr->vsmt has been set by the command line */ 2463 } else if (!smc->smp_threads_vsmt) { 2464 /* 2465 * Default VSMT value is tricky, because we need it to be as 2466 * consistent as possible (for migration), but this requires 2467 * changing it for at least some existing cases. We pick 8 as 2468 * the value that we'd get with KVM on POWER8, the 2469 * overwhelmingly common case in production systems. 2470 */ 2471 spapr->vsmt = MAX(8, smp_threads); 2472 } else { 2473 spapr->vsmt = smp_threads; 2474 } 2475 2476 /* KVM: If necessary, set the SMT mode: */ 2477 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2478 ret = kvmppc_set_smt_threads(spapr->vsmt); 2479 if (ret) { 2480 /* Looks like KVM isn't able to change VSMT mode */ 2481 error_setg(&local_err, 2482 "Failed to set KVM's VSMT mode to %d (errno %d)", 2483 spapr->vsmt, ret); 2484 /* We can live with that if the default one is big enough 2485 * for the number of threads, and a submultiple of the one 2486 * we want. In this case we'll waste some vcpu ids, but 2487 * behaviour will be correct */ 2488 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2489 warn_report_err(local_err); 2490 } else { 2491 if (!vsmt_user) { 2492 error_append_hint(&local_err, 2493 "On PPC, a VM with %d threads/core" 2494 " on a host with %d threads/core" 2495 " requires the use of VSMT mode %d.\n", 2496 smp_threads, kvm_smt, spapr->vsmt); 2497 } 2498 kvmppc_error_append_smt_possible_hint(&local_err); 2499 error_propagate(errp, local_err); 2500 } 2501 } 2502 } 2503 /* else TCG: nothing to do currently */ 2504 } 2505 2506 static void spapr_init_cpus(SpaprMachineState *spapr) 2507 { 2508 MachineState *machine = MACHINE(spapr); 2509 MachineClass *mc = MACHINE_GET_CLASS(machine); 2510 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2511 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2512 const CPUArchIdList *possible_cpus; 2513 unsigned int smp_cpus = machine->smp.cpus; 2514 unsigned int smp_threads = machine->smp.threads; 2515 unsigned int max_cpus = machine->smp.max_cpus; 2516 int boot_cores_nr = smp_cpus / smp_threads; 2517 int i; 2518 2519 possible_cpus = mc->possible_cpu_arch_ids(machine); 2520 if (mc->has_hotpluggable_cpus) { 2521 if (smp_cpus % smp_threads) { 2522 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2523 smp_cpus, smp_threads); 2524 exit(1); 2525 } 2526 if (max_cpus % smp_threads) { 2527 error_report("max_cpus (%u) must be multiple of threads (%u)", 2528 max_cpus, smp_threads); 2529 exit(1); 2530 } 2531 } else { 2532 if (max_cpus != smp_cpus) { 2533 error_report("This machine version does not support CPU hotplug"); 2534 exit(1); 2535 } 2536 boot_cores_nr = possible_cpus->len; 2537 } 2538 2539 if (smc->pre_2_10_has_unused_icps) { 2540 int i; 2541 2542 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2543 /* Dummy entries get deregistered when real ICPState objects 2544 * are registered during CPU core hotplug. 2545 */ 2546 pre_2_10_vmstate_register_dummy_icp(i); 2547 } 2548 } 2549 2550 for (i = 0; i < possible_cpus->len; i++) { 2551 int core_id = i * smp_threads; 2552 2553 if (mc->has_hotpluggable_cpus) { 2554 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2555 spapr_vcpu_id(spapr, core_id)); 2556 } 2557 2558 if (i < boot_cores_nr) { 2559 Object *core = object_new(type); 2560 int nr_threads = smp_threads; 2561 2562 /* Handle the partially filled core for older machine types */ 2563 if ((i + 1) * smp_threads >= smp_cpus) { 2564 nr_threads = smp_cpus - i * smp_threads; 2565 } 2566 2567 object_property_set_int(core, "nr-threads", nr_threads, 2568 &error_fatal); 2569 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2570 &error_fatal); 2571 qdev_realize(DEVICE(core), NULL, &error_fatal); 2572 2573 object_unref(core); 2574 } 2575 } 2576 } 2577 2578 static PCIHostState *spapr_create_default_phb(void) 2579 { 2580 DeviceState *dev; 2581 2582 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2583 qdev_prop_set_uint32(dev, "index", 0); 2584 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2585 2586 return PCI_HOST_BRIDGE(dev); 2587 } 2588 2589 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2590 { 2591 MachineState *machine = MACHINE(spapr); 2592 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2593 hwaddr rma_size = machine->ram_size; 2594 hwaddr node0_size = spapr_node0_size(machine); 2595 2596 /* RMA has to fit in the first NUMA node */ 2597 rma_size = MIN(rma_size, node0_size); 2598 2599 /* 2600 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2601 * never exceed that 2602 */ 2603 rma_size = MIN(rma_size, 1 * TiB); 2604 2605 /* 2606 * Clamp the RMA size based on machine type. This is for 2607 * migration compatibility with older qemu versions, which limited 2608 * the RMA size for complicated and mostly bad reasons. 2609 */ 2610 if (smc->rma_limit) { 2611 rma_size = MIN(rma_size, smc->rma_limit); 2612 } 2613 2614 if (rma_size < MIN_RMA_SLOF) { 2615 error_setg(errp, 2616 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2617 "ldMiB guest RMA (Real Mode Area memory)", 2618 MIN_RMA_SLOF / MiB); 2619 return 0; 2620 } 2621 2622 return rma_size; 2623 } 2624 2625 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2626 { 2627 MachineState *machine = MACHINE(spapr); 2628 int i; 2629 2630 for (i = 0; i < machine->ram_slots; i++) { 2631 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2632 } 2633 } 2634 2635 /* pSeries LPAR / sPAPR hardware init */ 2636 static void spapr_machine_init(MachineState *machine) 2637 { 2638 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2639 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2640 MachineClass *mc = MACHINE_GET_CLASS(machine); 2641 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 2642 const char *kernel_filename = machine->kernel_filename; 2643 const char *initrd_filename = machine->initrd_filename; 2644 PCIHostState *phb; 2645 int i; 2646 MemoryRegion *sysmem = get_system_memory(); 2647 long load_limit, fw_size; 2648 char *filename; 2649 Error *resize_hpt_err = NULL; 2650 2651 /* 2652 * if Secure VM (PEF) support is configured, then initialize it 2653 */ 2654 pef_kvm_init(machine->cgs, &error_fatal); 2655 2656 msi_nonbroken = true; 2657 2658 QLIST_INIT(&spapr->phbs); 2659 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2660 2661 /* Determine capabilities to run with */ 2662 spapr_caps_init(spapr); 2663 2664 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2665 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2666 /* 2667 * If the user explicitly requested a mode we should either 2668 * supply it, or fail completely (which we do below). But if 2669 * it's not set explicitly, we reset our mode to something 2670 * that works 2671 */ 2672 if (resize_hpt_err) { 2673 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2674 error_free(resize_hpt_err); 2675 resize_hpt_err = NULL; 2676 } else { 2677 spapr->resize_hpt = smc->resize_hpt_default; 2678 } 2679 } 2680 2681 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2682 2683 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2684 /* 2685 * User requested HPT resize, but this host can't supply it. Bail out 2686 */ 2687 error_report_err(resize_hpt_err); 2688 exit(1); 2689 } 2690 error_free(resize_hpt_err); 2691 2692 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2693 2694 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2695 load_limit = MIN(spapr->rma_size, FDT_MAX_ADDR) - FW_OVERHEAD; 2696 2697 /* 2698 * VSMT must be set in order to be able to compute VCPU ids, ie to 2699 * call spapr_max_server_number() or spapr_vcpu_id(). 2700 */ 2701 spapr_set_vsmt_mode(spapr, &error_fatal); 2702 2703 /* Set up Interrupt Controller before we create the VCPUs */ 2704 spapr_irq_init(spapr, &error_fatal); 2705 2706 /* Set up containers for ibm,client-architecture-support negotiated options 2707 */ 2708 spapr->ov5 = spapr_ovec_new(); 2709 spapr->ov5_cas = spapr_ovec_new(); 2710 2711 if (smc->dr_lmb_enabled) { 2712 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2713 spapr_validate_node_memory(machine, &error_fatal); 2714 } 2715 2716 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2717 2718 /* advertise support for dedicated HP event source to guests */ 2719 if (spapr->use_hotplug_event_source) { 2720 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2721 } 2722 2723 /* advertise support for HPT resizing */ 2724 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2725 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2726 } 2727 2728 /* advertise support for ibm,dyamic-memory-v2 */ 2729 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2730 2731 /* advertise XIVE on POWER9 machines */ 2732 if (spapr->irq->xive) { 2733 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2734 } 2735 2736 /* init CPUs */ 2737 spapr_init_cpus(spapr); 2738 2739 /* 2740 * check we don't have a memory-less/cpu-less NUMA node 2741 * Firmware relies on the existing memory/cpu topology to provide the 2742 * NUMA topology to the kernel. 2743 * And the linux kernel needs to know the NUMA topology at start 2744 * to be able to hotplug CPUs later. 2745 */ 2746 if (machine->numa_state->num_nodes) { 2747 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2748 /* check for memory-less node */ 2749 if (machine->numa_state->nodes[i].node_mem == 0) { 2750 CPUState *cs; 2751 int found = 0; 2752 /* check for cpu-less node */ 2753 CPU_FOREACH(cs) { 2754 PowerPCCPU *cpu = POWERPC_CPU(cs); 2755 if (cpu->node_id == i) { 2756 found = 1; 2757 break; 2758 } 2759 } 2760 /* memory-less and cpu-less node */ 2761 if (!found) { 2762 error_report( 2763 "Memory-less/cpu-less nodes are not supported (node %d)", 2764 i); 2765 exit(1); 2766 } 2767 } 2768 } 2769 2770 } 2771 2772 spapr->gpu_numa_id = spapr_numa_initial_nvgpu_numa_id(machine); 2773 2774 /* Init numa_assoc_array */ 2775 spapr_numa_associativity_init(spapr, machine); 2776 2777 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2778 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2779 spapr->max_compat_pvr)) { 2780 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2781 /* KVM and TCG always allow GTSE with radix... */ 2782 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2783 } 2784 /* ... but not with hash (currently). */ 2785 2786 if (kvm_enabled()) { 2787 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2788 kvmppc_enable_logical_ci_hcalls(); 2789 kvmppc_enable_set_mode_hcall(); 2790 2791 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2792 kvmppc_enable_clear_ref_mod_hcalls(); 2793 2794 /* Enable H_PAGE_INIT */ 2795 kvmppc_enable_h_page_init(); 2796 } 2797 2798 /* map RAM */ 2799 memory_region_add_subregion(sysmem, 0, machine->ram); 2800 2801 /* always allocate the device memory information */ 2802 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2803 2804 /* initialize hotplug memory address space */ 2805 if (machine->ram_size < machine->maxram_size) { 2806 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2807 /* 2808 * Limit the number of hotpluggable memory slots to half the number 2809 * slots that KVM supports, leaving the other half for PCI and other 2810 * devices. However ensure that number of slots doesn't drop below 32. 2811 */ 2812 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2813 SPAPR_MAX_RAM_SLOTS; 2814 2815 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2816 max_memslots = SPAPR_MAX_RAM_SLOTS; 2817 } 2818 if (machine->ram_slots > max_memslots) { 2819 error_report("Specified number of memory slots %" 2820 PRIu64" exceeds max supported %d", 2821 machine->ram_slots, max_memslots); 2822 exit(1); 2823 } 2824 2825 machine->device_memory->base = ROUND_UP(machine->ram_size, 2826 SPAPR_DEVICE_MEM_ALIGN); 2827 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2828 "device-memory", device_mem_size); 2829 memory_region_add_subregion(sysmem, machine->device_memory->base, 2830 &machine->device_memory->mr); 2831 } 2832 2833 if (smc->dr_lmb_enabled) { 2834 spapr_create_lmb_dr_connectors(spapr); 2835 } 2836 2837 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { 2838 /* Create the error string for live migration blocker */ 2839 error_setg(&spapr->fwnmi_migration_blocker, 2840 "A machine check is being handled during migration. The handler" 2841 "may run and log hardware error on the destination"); 2842 } 2843 2844 if (mc->nvdimm_supported) { 2845 spapr_create_nvdimm_dr_connectors(spapr); 2846 } 2847 2848 /* Set up RTAS event infrastructure */ 2849 spapr_events_init(spapr); 2850 2851 /* Set up the RTC RTAS interfaces */ 2852 spapr_rtc_create(spapr); 2853 2854 /* Set up VIO bus */ 2855 spapr->vio_bus = spapr_vio_bus_init(); 2856 2857 for (i = 0; serial_hd(i); i++) { 2858 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2859 } 2860 2861 /* We always have at least the nvram device on VIO */ 2862 spapr_create_nvram(spapr); 2863 2864 /* 2865 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2866 * connectors (described in root DT node's "ibm,drc-types" property) 2867 * are pre-initialized here. additional child connectors (such as 2868 * connectors for a PHBs PCI slots) are added as needed during their 2869 * parent's realization. 2870 */ 2871 if (smc->dr_phb_enabled) { 2872 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2873 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2874 } 2875 } 2876 2877 /* Set up PCI */ 2878 spapr_pci_rtas_init(); 2879 2880 phb = spapr_create_default_phb(); 2881 2882 for (i = 0; i < nb_nics; i++) { 2883 NICInfo *nd = &nd_table[i]; 2884 2885 if (!nd->model) { 2886 nd->model = g_strdup("spapr-vlan"); 2887 } 2888 2889 if (g_str_equal(nd->model, "spapr-vlan") || 2890 g_str_equal(nd->model, "ibmveth")) { 2891 spapr_vlan_create(spapr->vio_bus, nd); 2892 } else { 2893 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2894 } 2895 } 2896 2897 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2898 spapr_vscsi_create(spapr->vio_bus); 2899 } 2900 2901 /* Graphics */ 2902 if (spapr_vga_init(phb->bus, &error_fatal)) { 2903 spapr->has_graphics = true; 2904 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2905 } 2906 2907 if (machine->usb) { 2908 if (smc->use_ohci_by_default) { 2909 pci_create_simple(phb->bus, -1, "pci-ohci"); 2910 } else { 2911 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2912 } 2913 2914 if (spapr->has_graphics) { 2915 USBBus *usb_bus = usb_bus_find(-1); 2916 2917 usb_create_simple(usb_bus, "usb-kbd"); 2918 usb_create_simple(usb_bus, "usb-mouse"); 2919 } 2920 } 2921 2922 if (kernel_filename) { 2923 spapr->kernel_size = load_elf(kernel_filename, NULL, 2924 translate_kernel_address, spapr, 2925 NULL, NULL, NULL, NULL, 1, 2926 PPC_ELF_MACHINE, 0, 0); 2927 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2928 spapr->kernel_size = load_elf(kernel_filename, NULL, 2929 translate_kernel_address, spapr, 2930 NULL, NULL, NULL, NULL, 0, 2931 PPC_ELF_MACHINE, 0, 0); 2932 spapr->kernel_le = spapr->kernel_size > 0; 2933 } 2934 if (spapr->kernel_size < 0) { 2935 error_report("error loading %s: %s", kernel_filename, 2936 load_elf_strerror(spapr->kernel_size)); 2937 exit(1); 2938 } 2939 2940 /* load initrd */ 2941 if (initrd_filename) { 2942 /* Try to locate the initrd in the gap between the kernel 2943 * and the firmware. Add a bit of space just in case 2944 */ 2945 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 2946 + 0x1ffff) & ~0xffff; 2947 spapr->initrd_size = load_image_targphys(initrd_filename, 2948 spapr->initrd_base, 2949 load_limit 2950 - spapr->initrd_base); 2951 if (spapr->initrd_size < 0) { 2952 error_report("could not load initial ram disk '%s'", 2953 initrd_filename); 2954 exit(1); 2955 } 2956 } 2957 } 2958 2959 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2960 if (!filename) { 2961 error_report("Could not find LPAR firmware '%s'", bios_name); 2962 exit(1); 2963 } 2964 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2965 if (fw_size <= 0) { 2966 error_report("Could not load LPAR firmware '%s'", filename); 2967 exit(1); 2968 } 2969 g_free(filename); 2970 2971 /* FIXME: Should register things through the MachineState's qdev 2972 * interface, this is a legacy from the sPAPREnvironment structure 2973 * which predated MachineState but had a similar function */ 2974 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2975 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 2976 &savevm_htab_handlers, spapr); 2977 2978 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 2979 2980 qemu_register_boot_set(spapr_boot_set, spapr); 2981 2982 /* 2983 * Nothing needs to be done to resume a suspended guest because 2984 * suspending does not change the machine state, so no need for 2985 * a ->wakeup method. 2986 */ 2987 qemu_register_wakeup_support(); 2988 2989 if (kvm_enabled()) { 2990 /* to stop and start vmclock */ 2991 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2992 &spapr->tb); 2993 2994 kvmppc_spapr_enable_inkernel_multitce(); 2995 } 2996 2997 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 2998 } 2999 3000 #define DEFAULT_KVM_TYPE "auto" 3001 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3002 { 3003 /* 3004 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to 3005 * accomodate the 'HV' and 'PV' formats that exists in the 3006 * wild. The 'auto' mode is being introduced already as 3007 * lower-case, thus we don't need to bother checking for 3008 * "AUTO". 3009 */ 3010 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) { 3011 return 0; 3012 } 3013 3014 if (!g_ascii_strcasecmp(vm_type, "hv")) { 3015 return 1; 3016 } 3017 3018 if (!g_ascii_strcasecmp(vm_type, "pr")) { 3019 return 2; 3020 } 3021 3022 error_report("Unknown kvm-type specified '%s'", vm_type); 3023 exit(1); 3024 } 3025 3026 /* 3027 * Implementation of an interface to adjust firmware path 3028 * for the bootindex property handling. 3029 */ 3030 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3031 DeviceState *dev) 3032 { 3033 #define CAST(type, obj, name) \ 3034 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3035 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3036 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3037 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3038 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3039 3040 if (d) { 3041 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3042 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3043 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3044 3045 if (spapr) { 3046 /* 3047 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3048 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3049 * 0x8000 | (target << 8) | (bus << 5) | lun 3050 * (see the "Logical unit addressing format" table in SAM5) 3051 */ 3052 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3053 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3054 (uint64_t)id << 48); 3055 } else if (virtio) { 3056 /* 3057 * We use SRP luns of the form 01000000 | (target << 8) | lun 3058 * in the top 32 bits of the 64-bit LUN 3059 * Note: the quote above is from SLOF and it is wrong, 3060 * the actual binding is: 3061 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3062 */ 3063 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3064 if (d->lun >= 256) { 3065 /* Use the LUN "flat space addressing method" */ 3066 id |= 0x4000; 3067 } 3068 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3069 (uint64_t)id << 32); 3070 } else if (usb) { 3071 /* 3072 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3073 * in the top 32 bits of the 64-bit LUN 3074 */ 3075 unsigned usb_port = atoi(usb->port->path); 3076 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3077 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3078 (uint64_t)id << 32); 3079 } 3080 } 3081 3082 /* 3083 * SLOF probes the USB devices, and if it recognizes that the device is a 3084 * storage device, it changes its name to "storage" instead of "usb-host", 3085 * and additionally adds a child node for the SCSI LUN, so the correct 3086 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3087 */ 3088 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3089 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3090 if (usb_host_dev_is_scsi_storage(usbdev)) { 3091 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3092 } 3093 } 3094 3095 if (phb) { 3096 /* Replace "pci" with "pci@800000020000000" */ 3097 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3098 } 3099 3100 if (vsc) { 3101 /* Same logic as virtio above */ 3102 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3103 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3104 } 3105 3106 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3107 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3108 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3109 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3110 } 3111 3112 if (pcidev) { 3113 return spapr_pci_fw_dev_name(pcidev); 3114 } 3115 3116 return NULL; 3117 } 3118 3119 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3120 { 3121 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3122 3123 return g_strdup(spapr->kvm_type); 3124 } 3125 3126 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3127 { 3128 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3129 3130 g_free(spapr->kvm_type); 3131 spapr->kvm_type = g_strdup(value); 3132 } 3133 3134 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3135 { 3136 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3137 3138 return spapr->use_hotplug_event_source; 3139 } 3140 3141 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3142 Error **errp) 3143 { 3144 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3145 3146 spapr->use_hotplug_event_source = value; 3147 } 3148 3149 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3150 { 3151 return true; 3152 } 3153 3154 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3155 { 3156 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3157 3158 switch (spapr->resize_hpt) { 3159 case SPAPR_RESIZE_HPT_DEFAULT: 3160 return g_strdup("default"); 3161 case SPAPR_RESIZE_HPT_DISABLED: 3162 return g_strdup("disabled"); 3163 case SPAPR_RESIZE_HPT_ENABLED: 3164 return g_strdup("enabled"); 3165 case SPAPR_RESIZE_HPT_REQUIRED: 3166 return g_strdup("required"); 3167 } 3168 g_assert_not_reached(); 3169 } 3170 3171 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3172 { 3173 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3174 3175 if (strcmp(value, "default") == 0) { 3176 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3177 } else if (strcmp(value, "disabled") == 0) { 3178 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3179 } else if (strcmp(value, "enabled") == 0) { 3180 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3181 } else if (strcmp(value, "required") == 0) { 3182 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3183 } else { 3184 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3185 } 3186 } 3187 3188 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3189 { 3190 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3191 3192 if (spapr->irq == &spapr_irq_xics_legacy) { 3193 return g_strdup("legacy"); 3194 } else if (spapr->irq == &spapr_irq_xics) { 3195 return g_strdup("xics"); 3196 } else if (spapr->irq == &spapr_irq_xive) { 3197 return g_strdup("xive"); 3198 } else if (spapr->irq == &spapr_irq_dual) { 3199 return g_strdup("dual"); 3200 } 3201 g_assert_not_reached(); 3202 } 3203 3204 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3205 { 3206 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3207 3208 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3209 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3210 return; 3211 } 3212 3213 /* The legacy IRQ backend can not be set */ 3214 if (strcmp(value, "xics") == 0) { 3215 spapr->irq = &spapr_irq_xics; 3216 } else if (strcmp(value, "xive") == 0) { 3217 spapr->irq = &spapr_irq_xive; 3218 } else if (strcmp(value, "dual") == 0) { 3219 spapr->irq = &spapr_irq_dual; 3220 } else { 3221 error_setg(errp, "Bad value for \"ic-mode\" property"); 3222 } 3223 } 3224 3225 static char *spapr_get_host_model(Object *obj, Error **errp) 3226 { 3227 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3228 3229 return g_strdup(spapr->host_model); 3230 } 3231 3232 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3233 { 3234 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3235 3236 g_free(spapr->host_model); 3237 spapr->host_model = g_strdup(value); 3238 } 3239 3240 static char *spapr_get_host_serial(Object *obj, Error **errp) 3241 { 3242 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3243 3244 return g_strdup(spapr->host_serial); 3245 } 3246 3247 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3248 { 3249 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3250 3251 g_free(spapr->host_serial); 3252 spapr->host_serial = g_strdup(value); 3253 } 3254 3255 static void spapr_instance_init(Object *obj) 3256 { 3257 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3258 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3259 MachineState *ms = MACHINE(spapr); 3260 MachineClass *mc = MACHINE_GET_CLASS(ms); 3261 3262 /* 3263 * NVDIMM support went live in 5.1 without considering that, in 3264 * other archs, the user needs to enable NVDIMM support with the 3265 * 'nvdimm' machine option and the default behavior is NVDIMM 3266 * support disabled. It is too late to roll back to the standard 3267 * behavior without breaking 5.1 guests. 3268 */ 3269 if (mc->nvdimm_supported) { 3270 ms->nvdimms_state->is_enabled = true; 3271 } 3272 3273 spapr->htab_fd = -1; 3274 spapr->use_hotplug_event_source = true; 3275 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE); 3276 object_property_add_str(obj, "kvm-type", 3277 spapr_get_kvm_type, spapr_set_kvm_type); 3278 object_property_set_description(obj, "kvm-type", 3279 "Specifies the KVM virtualization mode (auto," 3280 " hv, pr). Defaults to 'auto'. This mode will use" 3281 " any available KVM module loaded in the host," 3282 " where kvm_hv takes precedence if both kvm_hv and" 3283 " kvm_pr are loaded."); 3284 object_property_add_bool(obj, "modern-hotplug-events", 3285 spapr_get_modern_hotplug_events, 3286 spapr_set_modern_hotplug_events); 3287 object_property_set_description(obj, "modern-hotplug-events", 3288 "Use dedicated hotplug event mechanism in" 3289 " place of standard EPOW events when possible" 3290 " (required for memory hot-unplug support)"); 3291 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3292 "Maximum permitted CPU compatibility mode"); 3293 3294 object_property_add_str(obj, "resize-hpt", 3295 spapr_get_resize_hpt, spapr_set_resize_hpt); 3296 object_property_set_description(obj, "resize-hpt", 3297 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3298 object_property_add_uint32_ptr(obj, "vsmt", 3299 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3300 object_property_set_description(obj, "vsmt", 3301 "Virtual SMT: KVM behaves as if this were" 3302 " the host's SMT mode"); 3303 3304 object_property_add_bool(obj, "vfio-no-msix-emulation", 3305 spapr_get_msix_emulation, NULL); 3306 3307 object_property_add_uint64_ptr(obj, "kernel-addr", 3308 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3309 object_property_set_description(obj, "kernel-addr", 3310 stringify(KERNEL_LOAD_ADDR) 3311 " for -kernel is the default"); 3312 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3313 /* The machine class defines the default interrupt controller mode */ 3314 spapr->irq = smc->irq; 3315 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3316 spapr_set_ic_mode); 3317 object_property_set_description(obj, "ic-mode", 3318 "Specifies the interrupt controller mode (xics, xive, dual)"); 3319 3320 object_property_add_str(obj, "host-model", 3321 spapr_get_host_model, spapr_set_host_model); 3322 object_property_set_description(obj, "host-model", 3323 "Host model to advertise in guest device tree"); 3324 object_property_add_str(obj, "host-serial", 3325 spapr_get_host_serial, spapr_set_host_serial); 3326 object_property_set_description(obj, "host-serial", 3327 "Host serial number to advertise in guest device tree"); 3328 } 3329 3330 static void spapr_machine_finalizefn(Object *obj) 3331 { 3332 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3333 3334 g_free(spapr->kvm_type); 3335 } 3336 3337 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3338 { 3339 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3340 PowerPCCPU *cpu = POWERPC_CPU(cs); 3341 CPUPPCState *env = &cpu->env; 3342 3343 cpu_synchronize_state(cs); 3344 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3345 if (spapr->fwnmi_system_reset_addr != -1) { 3346 uint64_t rtas_addr, addr; 3347 3348 /* get rtas addr from fdt */ 3349 rtas_addr = spapr_get_rtas_addr(); 3350 if (!rtas_addr) { 3351 qemu_system_guest_panicked(NULL); 3352 return; 3353 } 3354 3355 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3356 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3357 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3358 env->gpr[3] = addr; 3359 } 3360 ppc_cpu_do_system_reset(cs); 3361 if (spapr->fwnmi_system_reset_addr != -1) { 3362 env->nip = spapr->fwnmi_system_reset_addr; 3363 } 3364 } 3365 3366 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3367 { 3368 CPUState *cs; 3369 3370 CPU_FOREACH(cs) { 3371 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3372 } 3373 } 3374 3375 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3376 void *fdt, int *fdt_start_offset, Error **errp) 3377 { 3378 uint64_t addr; 3379 uint32_t node; 3380 3381 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3382 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3383 &error_abort); 3384 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3385 SPAPR_MEMORY_BLOCK_SIZE); 3386 return 0; 3387 } 3388 3389 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3390 bool dedicated_hp_event_source) 3391 { 3392 SpaprDrc *drc; 3393 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3394 int i; 3395 uint64_t addr = addr_start; 3396 bool hotplugged = spapr_drc_hotplugged(dev); 3397 3398 for (i = 0; i < nr_lmbs; i++) { 3399 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3400 addr / SPAPR_MEMORY_BLOCK_SIZE); 3401 g_assert(drc); 3402 3403 /* 3404 * memory_device_get_free_addr() provided a range of free addresses 3405 * that doesn't overlap with any existing mapping at pre-plug. The 3406 * corresponding LMB DRCs are thus assumed to be all attachable. 3407 */ 3408 spapr_drc_attach(drc, dev); 3409 if (!hotplugged) { 3410 spapr_drc_reset(drc); 3411 } 3412 addr += SPAPR_MEMORY_BLOCK_SIZE; 3413 } 3414 /* send hotplug notification to the 3415 * guest only in case of hotplugged memory 3416 */ 3417 if (hotplugged) { 3418 if (dedicated_hp_event_source) { 3419 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3420 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3421 g_assert(drc); 3422 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3423 nr_lmbs, 3424 spapr_drc_index(drc)); 3425 } else { 3426 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3427 nr_lmbs); 3428 } 3429 } 3430 } 3431 3432 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3433 { 3434 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3435 PCDIMMDevice *dimm = PC_DIMM(dev); 3436 uint64_t size, addr; 3437 int64_t slot; 3438 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3439 3440 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3441 3442 pc_dimm_plug(dimm, MACHINE(ms)); 3443 3444 if (!is_nvdimm) { 3445 addr = object_property_get_uint(OBJECT(dimm), 3446 PC_DIMM_ADDR_PROP, &error_abort); 3447 spapr_add_lmbs(dev, addr, size, 3448 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT)); 3449 } else { 3450 slot = object_property_get_int(OBJECT(dimm), 3451 PC_DIMM_SLOT_PROP, &error_abort); 3452 /* We should have valid slot number at this point */ 3453 g_assert(slot >= 0); 3454 spapr_add_nvdimm(dev, slot); 3455 } 3456 } 3457 3458 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3459 Error **errp) 3460 { 3461 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3462 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3463 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3464 PCDIMMDevice *dimm = PC_DIMM(dev); 3465 Error *local_err = NULL; 3466 uint64_t size; 3467 Object *memdev; 3468 hwaddr pagesize; 3469 3470 if (!smc->dr_lmb_enabled) { 3471 error_setg(errp, "Memory hotplug not supported for this machine"); 3472 return; 3473 } 3474 3475 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3476 if (local_err) { 3477 error_propagate(errp, local_err); 3478 return; 3479 } 3480 3481 if (is_nvdimm) { 3482 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3483 return; 3484 } 3485 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3486 error_setg(errp, "Hotplugged memory size must be a multiple of " 3487 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3488 return; 3489 } 3490 3491 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3492 &error_abort); 3493 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3494 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3495 return; 3496 } 3497 3498 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3499 } 3500 3501 struct SpaprDimmState { 3502 PCDIMMDevice *dimm; 3503 uint32_t nr_lmbs; 3504 QTAILQ_ENTRY(SpaprDimmState) next; 3505 }; 3506 3507 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3508 PCDIMMDevice *dimm) 3509 { 3510 SpaprDimmState *dimm_state = NULL; 3511 3512 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3513 if (dimm_state->dimm == dimm) { 3514 break; 3515 } 3516 } 3517 return dimm_state; 3518 } 3519 3520 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3521 uint32_t nr_lmbs, 3522 PCDIMMDevice *dimm) 3523 { 3524 SpaprDimmState *ds = NULL; 3525 3526 /* 3527 * If this request is for a DIMM whose removal had failed earlier 3528 * (due to guest's refusal to remove the LMBs), we would have this 3529 * dimm already in the pending_dimm_unplugs list. In that 3530 * case don't add again. 3531 */ 3532 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3533 if (!ds) { 3534 ds = g_malloc0(sizeof(SpaprDimmState)); 3535 ds->nr_lmbs = nr_lmbs; 3536 ds->dimm = dimm; 3537 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3538 } 3539 return ds; 3540 } 3541 3542 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3543 SpaprDimmState *dimm_state) 3544 { 3545 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3546 g_free(dimm_state); 3547 } 3548 3549 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3550 PCDIMMDevice *dimm) 3551 { 3552 SpaprDrc *drc; 3553 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3554 &error_abort); 3555 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3556 uint32_t avail_lmbs = 0; 3557 uint64_t addr_start, addr; 3558 int i; 3559 3560 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3561 &error_abort); 3562 3563 addr = addr_start; 3564 for (i = 0; i < nr_lmbs; i++) { 3565 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3566 addr / SPAPR_MEMORY_BLOCK_SIZE); 3567 g_assert(drc); 3568 if (drc->dev) { 3569 avail_lmbs++; 3570 } 3571 addr += SPAPR_MEMORY_BLOCK_SIZE; 3572 } 3573 3574 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3575 } 3576 3577 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev) 3578 { 3579 SpaprDimmState *ds; 3580 PCDIMMDevice *dimm; 3581 SpaprDrc *drc; 3582 uint32_t nr_lmbs; 3583 uint64_t size, addr_start, addr; 3584 g_autofree char *qapi_error = NULL; 3585 int i; 3586 3587 if (!dev) { 3588 return; 3589 } 3590 3591 dimm = PC_DIMM(dev); 3592 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3593 3594 /* 3595 * 'ds == NULL' would mean that the DIMM doesn't have a pending 3596 * unplug state, but one of its DRC is marked as unplug_requested. 3597 * This is bad and weird enough to g_assert() out. 3598 */ 3599 g_assert(ds); 3600 3601 spapr_pending_dimm_unplugs_remove(spapr, ds); 3602 3603 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3604 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3605 3606 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3607 &error_abort); 3608 3609 addr = addr_start; 3610 for (i = 0; i < nr_lmbs; i++) { 3611 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3612 addr / SPAPR_MEMORY_BLOCK_SIZE); 3613 g_assert(drc); 3614 3615 drc->unplug_requested = false; 3616 addr += SPAPR_MEMORY_BLOCK_SIZE; 3617 } 3618 3619 /* 3620 * Tell QAPI that something happened and the memory 3621 * hotunplug wasn't successful. 3622 */ 3623 qapi_error = g_strdup_printf("Memory hotunplug rejected by the guest " 3624 "for device %s", dev->id); 3625 qapi_event_send_mem_unplug_error(dev->id, qapi_error); 3626 } 3627 3628 /* Callback to be called during DRC release. */ 3629 void spapr_lmb_release(DeviceState *dev) 3630 { 3631 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3632 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3633 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3634 3635 /* This information will get lost if a migration occurs 3636 * during the unplug process. In this case recover it. */ 3637 if (ds == NULL) { 3638 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3639 g_assert(ds); 3640 /* The DRC being examined by the caller at least must be counted */ 3641 g_assert(ds->nr_lmbs); 3642 } 3643 3644 if (--ds->nr_lmbs) { 3645 return; 3646 } 3647 3648 /* 3649 * Now that all the LMBs have been removed by the guest, call the 3650 * unplug handler chain. This can never fail. 3651 */ 3652 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3653 object_unparent(OBJECT(dev)); 3654 } 3655 3656 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3657 { 3658 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3659 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3660 3661 /* We really shouldn't get this far without anything to unplug */ 3662 g_assert(ds); 3663 3664 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3665 qdev_unrealize(dev); 3666 spapr_pending_dimm_unplugs_remove(spapr, ds); 3667 } 3668 3669 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3670 DeviceState *dev, Error **errp) 3671 { 3672 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3673 PCDIMMDevice *dimm = PC_DIMM(dev); 3674 uint32_t nr_lmbs; 3675 uint64_t size, addr_start, addr; 3676 int i; 3677 SpaprDrc *drc; 3678 3679 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3680 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3681 return; 3682 } 3683 3684 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3685 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3686 3687 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3688 &error_abort); 3689 3690 /* 3691 * An existing pending dimm state for this DIMM means that there is an 3692 * unplug operation in progress, waiting for the spapr_lmb_release 3693 * callback to complete the job (BQL can't cover that far). In this case, 3694 * bail out to avoid detaching DRCs that were already released. 3695 */ 3696 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3697 error_setg(errp, "Memory unplug already in progress for device %s", 3698 dev->id); 3699 return; 3700 } 3701 3702 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3703 3704 addr = addr_start; 3705 for (i = 0; i < nr_lmbs; i++) { 3706 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3707 addr / SPAPR_MEMORY_BLOCK_SIZE); 3708 g_assert(drc); 3709 3710 spapr_drc_unplug_request(drc); 3711 addr += SPAPR_MEMORY_BLOCK_SIZE; 3712 } 3713 3714 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3715 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3716 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3717 nr_lmbs, spapr_drc_index(drc)); 3718 } 3719 3720 /* Callback to be called during DRC release. */ 3721 void spapr_core_release(DeviceState *dev) 3722 { 3723 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3724 3725 /* Call the unplug handler chain. This can never fail. */ 3726 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3727 object_unparent(OBJECT(dev)); 3728 } 3729 3730 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3731 { 3732 MachineState *ms = MACHINE(hotplug_dev); 3733 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3734 CPUCore *cc = CPU_CORE(dev); 3735 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3736 3737 if (smc->pre_2_10_has_unused_icps) { 3738 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3739 int i; 3740 3741 for (i = 0; i < cc->nr_threads; i++) { 3742 CPUState *cs = CPU(sc->threads[i]); 3743 3744 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3745 } 3746 } 3747 3748 assert(core_slot); 3749 core_slot->cpu = NULL; 3750 qdev_unrealize(dev); 3751 } 3752 3753 static 3754 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3755 Error **errp) 3756 { 3757 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3758 int index; 3759 SpaprDrc *drc; 3760 CPUCore *cc = CPU_CORE(dev); 3761 3762 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3763 error_setg(errp, "Unable to find CPU core with core-id: %d", 3764 cc->core_id); 3765 return; 3766 } 3767 if (index == 0) { 3768 error_setg(errp, "Boot CPU core may not be unplugged"); 3769 return; 3770 } 3771 3772 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3773 spapr_vcpu_id(spapr, cc->core_id)); 3774 g_assert(drc); 3775 3776 if (!spapr_drc_unplug_requested(drc)) { 3777 spapr_drc_unplug_request(drc); 3778 } 3779 3780 /* 3781 * spapr_hotplug_req_remove_by_index is left unguarded, out of the 3782 * "!spapr_drc_unplug_requested" check, to allow for multiple IRQ 3783 * pulses removing the same CPU. Otherwise, in an failed hotunplug 3784 * attempt (e.g. the kernel will refuse to remove the last online 3785 * CPU), we will never attempt it again because unplug_requested 3786 * will still be 'true' in that case. 3787 */ 3788 spapr_hotplug_req_remove_by_index(drc); 3789 } 3790 3791 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3792 void *fdt, int *fdt_start_offset, Error **errp) 3793 { 3794 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3795 CPUState *cs = CPU(core->threads[0]); 3796 PowerPCCPU *cpu = POWERPC_CPU(cs); 3797 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3798 int id = spapr_get_vcpu_id(cpu); 3799 g_autofree char *nodename = NULL; 3800 int offset; 3801 3802 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3803 offset = fdt_add_subnode(fdt, 0, nodename); 3804 3805 spapr_dt_cpu(cs, fdt, offset, spapr); 3806 3807 /* 3808 * spapr_dt_cpu() does not fill the 'name' property in the 3809 * CPU node. The function is called during boot process, before 3810 * and after CAS, and overwriting the 'name' property written 3811 * by SLOF is not allowed. 3812 * 3813 * Write it manually after spapr_dt_cpu(). This makes the hotplug 3814 * CPUs more compatible with the coldplugged ones, which have 3815 * the 'name' property. Linux Kernel also relies on this 3816 * property to identify CPU nodes. 3817 */ 3818 _FDT((fdt_setprop_string(fdt, offset, "name", nodename))); 3819 3820 *fdt_start_offset = offset; 3821 return 0; 3822 } 3823 3824 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3825 { 3826 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3827 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3828 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3829 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3830 CPUCore *cc = CPU_CORE(dev); 3831 CPUState *cs; 3832 SpaprDrc *drc; 3833 CPUArchId *core_slot; 3834 int index; 3835 bool hotplugged = spapr_drc_hotplugged(dev); 3836 int i; 3837 3838 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3839 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */ 3840 3841 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3842 spapr_vcpu_id(spapr, cc->core_id)); 3843 3844 g_assert(drc || !mc->has_hotpluggable_cpus); 3845 3846 if (drc) { 3847 /* 3848 * spapr_core_pre_plug() already buys us this is a brand new 3849 * core being plugged into a free slot. Nothing should already 3850 * be attached to the corresponding DRC. 3851 */ 3852 spapr_drc_attach(drc, dev); 3853 3854 if (hotplugged) { 3855 /* 3856 * Send hotplug notification interrupt to the guest only 3857 * in case of hotplugged CPUs. 3858 */ 3859 spapr_hotplug_req_add_by_index(drc); 3860 } else { 3861 spapr_drc_reset(drc); 3862 } 3863 } 3864 3865 core_slot->cpu = OBJECT(dev); 3866 3867 /* 3868 * Set compatibility mode to match the boot CPU, which was either set 3869 * by the machine reset code or by CAS. This really shouldn't fail at 3870 * this point. 3871 */ 3872 if (hotplugged) { 3873 for (i = 0; i < cc->nr_threads; i++) { 3874 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3875 &error_abort); 3876 } 3877 } 3878 3879 if (smc->pre_2_10_has_unused_icps) { 3880 for (i = 0; i < cc->nr_threads; i++) { 3881 cs = CPU(core->threads[i]); 3882 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3883 } 3884 } 3885 } 3886 3887 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3888 Error **errp) 3889 { 3890 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3891 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3892 CPUCore *cc = CPU_CORE(dev); 3893 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3894 const char *type = object_get_typename(OBJECT(dev)); 3895 CPUArchId *core_slot; 3896 int index; 3897 unsigned int smp_threads = machine->smp.threads; 3898 3899 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3900 error_setg(errp, "CPU hotplug not supported for this machine"); 3901 return; 3902 } 3903 3904 if (strcmp(base_core_type, type)) { 3905 error_setg(errp, "CPU core type should be %s", base_core_type); 3906 return; 3907 } 3908 3909 if (cc->core_id % smp_threads) { 3910 error_setg(errp, "invalid core id %d", cc->core_id); 3911 return; 3912 } 3913 3914 /* 3915 * In general we should have homogeneous threads-per-core, but old 3916 * (pre hotplug support) machine types allow the last core to have 3917 * reduced threads as a compatibility hack for when we allowed 3918 * total vcpus not a multiple of threads-per-core. 3919 */ 3920 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3921 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 3922 smp_threads); 3923 return; 3924 } 3925 3926 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3927 if (!core_slot) { 3928 error_setg(errp, "core id %d out of range", cc->core_id); 3929 return; 3930 } 3931 3932 if (core_slot->cpu) { 3933 error_setg(errp, "core %d already populated", cc->core_id); 3934 return; 3935 } 3936 3937 numa_cpu_pre_plug(core_slot, dev, errp); 3938 } 3939 3940 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3941 void *fdt, int *fdt_start_offset, Error **errp) 3942 { 3943 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3944 int intc_phandle; 3945 3946 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3947 if (intc_phandle <= 0) { 3948 return -1; 3949 } 3950 3951 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3952 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3953 return -1; 3954 } 3955 3956 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3957 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3958 3959 return 0; 3960 } 3961 3962 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3963 Error **errp) 3964 { 3965 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3966 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3967 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3968 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3969 SpaprDrc *drc; 3970 3971 if (dev->hotplugged && !smc->dr_phb_enabled) { 3972 error_setg(errp, "PHB hotplug not supported for this machine"); 3973 return false; 3974 } 3975 3976 if (sphb->index == (uint32_t)-1) { 3977 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3978 return false; 3979 } 3980 3981 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3982 if (drc && drc->dev) { 3983 error_setg(errp, "PHB %d already attached", sphb->index); 3984 return false; 3985 } 3986 3987 /* 3988 * This will check that sphb->index doesn't exceed the maximum number of 3989 * PHBs for the current machine type. 3990 */ 3991 return 3992 smc->phb_placement(spapr, sphb->index, 3993 &sphb->buid, &sphb->io_win_addr, 3994 &sphb->mem_win_addr, &sphb->mem64_win_addr, 3995 windows_supported, sphb->dma_liobn, 3996 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 3997 errp); 3998 } 3999 4000 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4001 { 4002 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4003 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4004 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4005 SpaprDrc *drc; 4006 bool hotplugged = spapr_drc_hotplugged(dev); 4007 4008 if (!smc->dr_phb_enabled) { 4009 return; 4010 } 4011 4012 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4013 /* hotplug hooks should check it's enabled before getting this far */ 4014 assert(drc); 4015 4016 /* spapr_phb_pre_plug() already checked the DRC is attachable */ 4017 spapr_drc_attach(drc, dev); 4018 4019 if (hotplugged) { 4020 spapr_hotplug_req_add_by_index(drc); 4021 } else { 4022 spapr_drc_reset(drc); 4023 } 4024 } 4025 4026 void spapr_phb_release(DeviceState *dev) 4027 { 4028 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4029 4030 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4031 object_unparent(OBJECT(dev)); 4032 } 4033 4034 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4035 { 4036 qdev_unrealize(dev); 4037 } 4038 4039 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4040 DeviceState *dev, Error **errp) 4041 { 4042 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4043 SpaprDrc *drc; 4044 4045 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4046 assert(drc); 4047 4048 if (!spapr_drc_unplug_requested(drc)) { 4049 spapr_drc_unplug_request(drc); 4050 spapr_hotplug_req_remove_by_index(drc); 4051 } else { 4052 error_setg(errp, 4053 "PCI Host Bridge unplug already in progress for device %s", 4054 dev->id); 4055 } 4056 } 4057 4058 static 4059 bool spapr_tpm_proxy_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4060 Error **errp) 4061 { 4062 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4063 4064 if (spapr->tpm_proxy != NULL) { 4065 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4066 return false; 4067 } 4068 4069 return true; 4070 } 4071 4072 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4073 { 4074 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4075 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4076 4077 /* Already checked in spapr_tpm_proxy_pre_plug() */ 4078 g_assert(spapr->tpm_proxy == NULL); 4079 4080 spapr->tpm_proxy = tpm_proxy; 4081 } 4082 4083 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4084 { 4085 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4086 4087 qdev_unrealize(dev); 4088 object_unparent(OBJECT(dev)); 4089 spapr->tpm_proxy = NULL; 4090 } 4091 4092 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4093 DeviceState *dev, Error **errp) 4094 { 4095 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4096 spapr_memory_plug(hotplug_dev, dev); 4097 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4098 spapr_core_plug(hotplug_dev, dev); 4099 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4100 spapr_phb_plug(hotplug_dev, dev); 4101 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4102 spapr_tpm_proxy_plug(hotplug_dev, dev); 4103 } 4104 } 4105 4106 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4107 DeviceState *dev, Error **errp) 4108 { 4109 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4110 spapr_memory_unplug(hotplug_dev, dev); 4111 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4112 spapr_core_unplug(hotplug_dev, dev); 4113 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4114 spapr_phb_unplug(hotplug_dev, dev); 4115 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4116 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4117 } 4118 } 4119 4120 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr) 4121 { 4122 return spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT) || 4123 /* 4124 * CAS will process all pending unplug requests. 4125 * 4126 * HACK: a guest could theoretically have cleared all bits in OV5, 4127 * but none of the guests we care for do. 4128 */ 4129 spapr_ovec_empty(spapr->ov5_cas); 4130 } 4131 4132 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4133 DeviceState *dev, Error **errp) 4134 { 4135 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4136 MachineClass *mc = MACHINE_GET_CLASS(sms); 4137 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4138 4139 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4140 if (spapr_memory_hot_unplug_supported(sms)) { 4141 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4142 } else { 4143 error_setg(errp, "Memory hot unplug not supported for this guest"); 4144 } 4145 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4146 if (!mc->has_hotpluggable_cpus) { 4147 error_setg(errp, "CPU hot unplug not supported on this machine"); 4148 return; 4149 } 4150 spapr_core_unplug_request(hotplug_dev, dev, errp); 4151 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4152 if (!smc->dr_phb_enabled) { 4153 error_setg(errp, "PHB hot unplug not supported on this machine"); 4154 return; 4155 } 4156 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4157 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4158 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4159 } 4160 } 4161 4162 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4163 DeviceState *dev, Error **errp) 4164 { 4165 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4166 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4167 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4168 spapr_core_pre_plug(hotplug_dev, dev, errp); 4169 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4170 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4171 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4172 spapr_tpm_proxy_pre_plug(hotplug_dev, dev, errp); 4173 } 4174 } 4175 4176 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4177 DeviceState *dev) 4178 { 4179 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4180 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4181 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4182 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4183 return HOTPLUG_HANDLER(machine); 4184 } 4185 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4186 PCIDevice *pcidev = PCI_DEVICE(dev); 4187 PCIBus *root = pci_device_root_bus(pcidev); 4188 SpaprPhbState *phb = 4189 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4190 TYPE_SPAPR_PCI_HOST_BRIDGE); 4191 4192 if (phb) { 4193 return HOTPLUG_HANDLER(phb); 4194 } 4195 } 4196 return NULL; 4197 } 4198 4199 static CpuInstanceProperties 4200 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4201 { 4202 CPUArchId *core_slot; 4203 MachineClass *mc = MACHINE_GET_CLASS(machine); 4204 4205 /* make sure possible_cpu are intialized */ 4206 mc->possible_cpu_arch_ids(machine); 4207 /* get CPU core slot containing thread that matches cpu_index */ 4208 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4209 assert(core_slot); 4210 return core_slot->props; 4211 } 4212 4213 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4214 { 4215 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4216 } 4217 4218 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4219 { 4220 int i; 4221 unsigned int smp_threads = machine->smp.threads; 4222 unsigned int smp_cpus = machine->smp.cpus; 4223 const char *core_type; 4224 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4225 MachineClass *mc = MACHINE_GET_CLASS(machine); 4226 4227 if (!mc->has_hotpluggable_cpus) { 4228 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4229 } 4230 if (machine->possible_cpus) { 4231 assert(machine->possible_cpus->len == spapr_max_cores); 4232 return machine->possible_cpus; 4233 } 4234 4235 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4236 if (!core_type) { 4237 error_report("Unable to find sPAPR CPU Core definition"); 4238 exit(1); 4239 } 4240 4241 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4242 sizeof(CPUArchId) * spapr_max_cores); 4243 machine->possible_cpus->len = spapr_max_cores; 4244 for (i = 0; i < machine->possible_cpus->len; i++) { 4245 int core_id = i * smp_threads; 4246 4247 machine->possible_cpus->cpus[i].type = core_type; 4248 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4249 machine->possible_cpus->cpus[i].arch_id = core_id; 4250 machine->possible_cpus->cpus[i].props.has_core_id = true; 4251 machine->possible_cpus->cpus[i].props.core_id = core_id; 4252 } 4253 return machine->possible_cpus; 4254 } 4255 4256 static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4257 uint64_t *buid, hwaddr *pio, 4258 hwaddr *mmio32, hwaddr *mmio64, 4259 unsigned n_dma, uint32_t *liobns, 4260 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4261 { 4262 /* 4263 * New-style PHB window placement. 4264 * 4265 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4266 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4267 * windows. 4268 * 4269 * Some guest kernels can't work with MMIO windows above 1<<46 4270 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4271 * 4272 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4273 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4274 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4275 * 1TiB 64-bit MMIO windows for each PHB. 4276 */ 4277 const uint64_t base_buid = 0x800000020000000ULL; 4278 int i; 4279 4280 /* Sanity check natural alignments */ 4281 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4282 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4283 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4284 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4285 /* Sanity check bounds */ 4286 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4287 SPAPR_PCI_MEM32_WIN_SIZE); 4288 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4289 SPAPR_PCI_MEM64_WIN_SIZE); 4290 4291 if (index >= SPAPR_MAX_PHBS) { 4292 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4293 SPAPR_MAX_PHBS - 1); 4294 return false; 4295 } 4296 4297 *buid = base_buid + index; 4298 for (i = 0; i < n_dma; ++i) { 4299 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4300 } 4301 4302 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4303 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4304 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4305 4306 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4307 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4308 return true; 4309 } 4310 4311 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4312 { 4313 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4314 4315 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4316 } 4317 4318 static void spapr_ics_resend(XICSFabric *dev) 4319 { 4320 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4321 4322 ics_resend(spapr->ics); 4323 } 4324 4325 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4326 { 4327 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4328 4329 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4330 } 4331 4332 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4333 Monitor *mon) 4334 { 4335 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4336 4337 spapr_irq_print_info(spapr, mon); 4338 monitor_printf(mon, "irqchip: %s\n", 4339 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4340 } 4341 4342 /* 4343 * This is a XIVE only operation 4344 */ 4345 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4346 uint8_t nvt_blk, uint32_t nvt_idx, 4347 bool cam_ignore, uint8_t priority, 4348 uint32_t logic_serv, XiveTCTXMatch *match) 4349 { 4350 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4351 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4352 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4353 int count; 4354 4355 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4356 priority, logic_serv, match); 4357 if (count < 0) { 4358 return count; 4359 } 4360 4361 /* 4362 * When we implement the save and restore of the thread interrupt 4363 * contexts in the enter/exit CPU handlers of the machine and the 4364 * escalations in QEMU, we should be able to handle non dispatched 4365 * vCPUs. 4366 * 4367 * Until this is done, the sPAPR machine should find at least one 4368 * matching context always. 4369 */ 4370 if (count == 0) { 4371 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4372 nvt_blk, nvt_idx); 4373 } 4374 4375 return count; 4376 } 4377 4378 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4379 { 4380 return cpu->vcpu_id; 4381 } 4382 4383 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4384 { 4385 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4386 MachineState *ms = MACHINE(spapr); 4387 int vcpu_id; 4388 4389 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4390 4391 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4392 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4393 error_append_hint(errp, "Adjust the number of cpus to %d " 4394 "or try to raise the number of threads per core\n", 4395 vcpu_id * ms->smp.threads / spapr->vsmt); 4396 return false; 4397 } 4398 4399 cpu->vcpu_id = vcpu_id; 4400 return true; 4401 } 4402 4403 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4404 { 4405 CPUState *cs; 4406 4407 CPU_FOREACH(cs) { 4408 PowerPCCPU *cpu = POWERPC_CPU(cs); 4409 4410 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4411 return cpu; 4412 } 4413 } 4414 4415 return NULL; 4416 } 4417 4418 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4419 { 4420 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4421 4422 /* These are only called by TCG, KVM maintains dispatch state */ 4423 4424 spapr_cpu->prod = false; 4425 if (spapr_cpu->vpa_addr) { 4426 CPUState *cs = CPU(cpu); 4427 uint32_t dispatch; 4428 4429 dispatch = ldl_be_phys(cs->as, 4430 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4431 dispatch++; 4432 if ((dispatch & 1) != 0) { 4433 qemu_log_mask(LOG_GUEST_ERROR, 4434 "VPA: incorrect dispatch counter value for " 4435 "dispatched partition %u, correcting.\n", dispatch); 4436 dispatch++; 4437 } 4438 stl_be_phys(cs->as, 4439 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4440 } 4441 } 4442 4443 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4444 { 4445 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4446 4447 if (spapr_cpu->vpa_addr) { 4448 CPUState *cs = CPU(cpu); 4449 uint32_t dispatch; 4450 4451 dispatch = ldl_be_phys(cs->as, 4452 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4453 dispatch++; 4454 if ((dispatch & 1) != 1) { 4455 qemu_log_mask(LOG_GUEST_ERROR, 4456 "VPA: incorrect dispatch counter value for " 4457 "preempted partition %u, correcting.\n", dispatch); 4458 dispatch++; 4459 } 4460 stl_be_phys(cs->as, 4461 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4462 } 4463 } 4464 4465 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4466 { 4467 MachineClass *mc = MACHINE_CLASS(oc); 4468 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4469 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4470 NMIClass *nc = NMI_CLASS(oc); 4471 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4472 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4473 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4474 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4475 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4476 4477 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4478 mc->ignore_boot_device_suffixes = true; 4479 4480 /* 4481 * We set up the default / latest behaviour here. The class_init 4482 * functions for the specific versioned machine types can override 4483 * these details for backwards compatibility 4484 */ 4485 mc->init = spapr_machine_init; 4486 mc->reset = spapr_machine_reset; 4487 mc->block_default_type = IF_SCSI; 4488 4489 /* 4490 * Setting max_cpus to INT32_MAX. Both KVM and TCG max_cpus values 4491 * should be limited by the host capability instead of hardcoded. 4492 * max_cpus for KVM guests will be checked in kvm_init(), and TCG 4493 * guests are welcome to have as many CPUs as the host are capable 4494 * of emulate. 4495 */ 4496 mc->max_cpus = INT32_MAX; 4497 4498 mc->no_parallel = 1; 4499 mc->default_boot_order = ""; 4500 mc->default_ram_size = 512 * MiB; 4501 mc->default_ram_id = "ppc_spapr.ram"; 4502 mc->default_display = "std"; 4503 mc->kvm_type = spapr_kvm_type; 4504 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4505 mc->pci_allow_0_address = true; 4506 assert(!mc->get_hotplug_handler); 4507 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4508 hc->pre_plug = spapr_machine_device_pre_plug; 4509 hc->plug = spapr_machine_device_plug; 4510 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4511 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4512 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4513 hc->unplug_request = spapr_machine_device_unplug_request; 4514 hc->unplug = spapr_machine_device_unplug; 4515 4516 smc->dr_lmb_enabled = true; 4517 smc->update_dt_enabled = true; 4518 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4519 mc->has_hotpluggable_cpus = true; 4520 mc->nvdimm_supported = true; 4521 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4522 fwc->get_dev_path = spapr_get_fw_dev_path; 4523 nc->nmi_monitor_handler = spapr_nmi; 4524 smc->phb_placement = spapr_phb_placement; 4525 vhc->hypercall = emulate_spapr_hypercall; 4526 vhc->hpt_mask = spapr_hpt_mask; 4527 vhc->map_hptes = spapr_map_hptes; 4528 vhc->unmap_hptes = spapr_unmap_hptes; 4529 vhc->hpte_set_c = spapr_hpte_set_c; 4530 vhc->hpte_set_r = spapr_hpte_set_r; 4531 vhc->get_pate = spapr_get_pate; 4532 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4533 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4534 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4535 xic->ics_get = spapr_ics_get; 4536 xic->ics_resend = spapr_ics_resend; 4537 xic->icp_get = spapr_icp_get; 4538 ispc->print_info = spapr_pic_print_info; 4539 /* Force NUMA node memory size to be a multiple of 4540 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4541 * in which LMBs are represented and hot-added 4542 */ 4543 mc->numa_mem_align_shift = 28; 4544 mc->auto_enable_numa = true; 4545 4546 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4547 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4548 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4549 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4550 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4551 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4552 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4553 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4554 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4555 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4556 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4557 spapr_caps_add_properties(smc); 4558 smc->irq = &spapr_irq_dual; 4559 smc->dr_phb_enabled = true; 4560 smc->linux_pci_probe = true; 4561 smc->smp_threads_vsmt = true; 4562 smc->nr_xirqs = SPAPR_NR_XIRQS; 4563 xfc->match_nvt = spapr_match_nvt; 4564 } 4565 4566 static const TypeInfo spapr_machine_info = { 4567 .name = TYPE_SPAPR_MACHINE, 4568 .parent = TYPE_MACHINE, 4569 .abstract = true, 4570 .instance_size = sizeof(SpaprMachineState), 4571 .instance_init = spapr_instance_init, 4572 .instance_finalize = spapr_machine_finalizefn, 4573 .class_size = sizeof(SpaprMachineClass), 4574 .class_init = spapr_machine_class_init, 4575 .interfaces = (InterfaceInfo[]) { 4576 { TYPE_FW_PATH_PROVIDER }, 4577 { TYPE_NMI }, 4578 { TYPE_HOTPLUG_HANDLER }, 4579 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4580 { TYPE_XICS_FABRIC }, 4581 { TYPE_INTERRUPT_STATS_PROVIDER }, 4582 { TYPE_XIVE_FABRIC }, 4583 { } 4584 }, 4585 }; 4586 4587 static void spapr_machine_latest_class_options(MachineClass *mc) 4588 { 4589 mc->alias = "pseries"; 4590 mc->is_default = true; 4591 } 4592 4593 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4594 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4595 void *data) \ 4596 { \ 4597 MachineClass *mc = MACHINE_CLASS(oc); \ 4598 spapr_machine_##suffix##_class_options(mc); \ 4599 if (latest) { \ 4600 spapr_machine_latest_class_options(mc); \ 4601 } \ 4602 } \ 4603 static const TypeInfo spapr_machine_##suffix##_info = { \ 4604 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4605 .parent = TYPE_SPAPR_MACHINE, \ 4606 .class_init = spapr_machine_##suffix##_class_init, \ 4607 }; \ 4608 static void spapr_machine_register_##suffix(void) \ 4609 { \ 4610 type_register(&spapr_machine_##suffix##_info); \ 4611 } \ 4612 type_init(spapr_machine_register_##suffix) 4613 4614 /* 4615 * pseries-6.1 4616 */ 4617 static void spapr_machine_6_1_class_options(MachineClass *mc) 4618 { 4619 /* Defaults for the latest behaviour inherited from the base class */ 4620 } 4621 4622 DEFINE_SPAPR_MACHINE(6_1, "6.1", true); 4623 4624 /* 4625 * pseries-6.0 4626 */ 4627 static void spapr_machine_6_0_class_options(MachineClass *mc) 4628 { 4629 spapr_machine_6_1_class_options(mc); 4630 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 4631 } 4632 4633 DEFINE_SPAPR_MACHINE(6_0, "6.0", false); 4634 4635 /* 4636 * pseries-5.2 4637 */ 4638 static void spapr_machine_5_2_class_options(MachineClass *mc) 4639 { 4640 spapr_machine_6_0_class_options(mc); 4641 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 4642 } 4643 4644 DEFINE_SPAPR_MACHINE(5_2, "5.2", false); 4645 4646 /* 4647 * pseries-5.1 4648 */ 4649 static void spapr_machine_5_1_class_options(MachineClass *mc) 4650 { 4651 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4652 4653 spapr_machine_5_2_class_options(mc); 4654 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4655 smc->pre_5_2_numa_associativity = true; 4656 } 4657 4658 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4659 4660 /* 4661 * pseries-5.0 4662 */ 4663 static void spapr_machine_5_0_class_options(MachineClass *mc) 4664 { 4665 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4666 static GlobalProperty compat[] = { 4667 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4668 }; 4669 4670 spapr_machine_5_1_class_options(mc); 4671 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4672 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4673 mc->numa_mem_supported = true; 4674 smc->pre_5_1_assoc_refpoints = true; 4675 } 4676 4677 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4678 4679 /* 4680 * pseries-4.2 4681 */ 4682 static void spapr_machine_4_2_class_options(MachineClass *mc) 4683 { 4684 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4685 4686 spapr_machine_5_0_class_options(mc); 4687 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4688 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4689 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4690 smc->rma_limit = 16 * GiB; 4691 mc->nvdimm_supported = false; 4692 } 4693 4694 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4695 4696 /* 4697 * pseries-4.1 4698 */ 4699 static void spapr_machine_4_1_class_options(MachineClass *mc) 4700 { 4701 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4702 static GlobalProperty compat[] = { 4703 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4704 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4705 }; 4706 4707 spapr_machine_4_2_class_options(mc); 4708 smc->linux_pci_probe = false; 4709 smc->smp_threads_vsmt = false; 4710 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4711 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4712 } 4713 4714 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4715 4716 /* 4717 * pseries-4.0 4718 */ 4719 static bool phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4720 uint64_t *buid, hwaddr *pio, 4721 hwaddr *mmio32, hwaddr *mmio64, 4722 unsigned n_dma, uint32_t *liobns, 4723 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4724 { 4725 if (!spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, 4726 liobns, nv2gpa, nv2atsd, errp)) { 4727 return false; 4728 } 4729 4730 *nv2gpa = 0; 4731 *nv2atsd = 0; 4732 return true; 4733 } 4734 static void spapr_machine_4_0_class_options(MachineClass *mc) 4735 { 4736 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4737 4738 spapr_machine_4_1_class_options(mc); 4739 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4740 smc->phb_placement = phb_placement_4_0; 4741 smc->irq = &spapr_irq_xics; 4742 smc->pre_4_1_migration = true; 4743 } 4744 4745 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4746 4747 /* 4748 * pseries-3.1 4749 */ 4750 static void spapr_machine_3_1_class_options(MachineClass *mc) 4751 { 4752 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4753 4754 spapr_machine_4_0_class_options(mc); 4755 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4756 4757 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4758 smc->update_dt_enabled = false; 4759 smc->dr_phb_enabled = false; 4760 smc->broken_host_serial_model = true; 4761 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4762 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4763 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4764 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4765 } 4766 4767 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4768 4769 /* 4770 * pseries-3.0 4771 */ 4772 4773 static void spapr_machine_3_0_class_options(MachineClass *mc) 4774 { 4775 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4776 4777 spapr_machine_3_1_class_options(mc); 4778 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4779 4780 smc->legacy_irq_allocation = true; 4781 smc->nr_xirqs = 0x400; 4782 smc->irq = &spapr_irq_xics_legacy; 4783 } 4784 4785 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4786 4787 /* 4788 * pseries-2.12 4789 */ 4790 static void spapr_machine_2_12_class_options(MachineClass *mc) 4791 { 4792 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4793 static GlobalProperty compat[] = { 4794 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4795 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4796 }; 4797 4798 spapr_machine_3_0_class_options(mc); 4799 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4800 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4801 4802 /* We depend on kvm_enabled() to choose a default value for the 4803 * hpt-max-page-size capability. Of course we can't do it here 4804 * because this is too early and the HW accelerator isn't initialzed 4805 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4806 */ 4807 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4808 } 4809 4810 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4811 4812 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4813 { 4814 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4815 4816 spapr_machine_2_12_class_options(mc); 4817 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4818 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4819 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4820 } 4821 4822 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4823 4824 /* 4825 * pseries-2.11 4826 */ 4827 4828 static void spapr_machine_2_11_class_options(MachineClass *mc) 4829 { 4830 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4831 4832 spapr_machine_2_12_class_options(mc); 4833 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4834 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4835 } 4836 4837 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4838 4839 /* 4840 * pseries-2.10 4841 */ 4842 4843 static void spapr_machine_2_10_class_options(MachineClass *mc) 4844 { 4845 spapr_machine_2_11_class_options(mc); 4846 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4847 } 4848 4849 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4850 4851 /* 4852 * pseries-2.9 4853 */ 4854 4855 static void spapr_machine_2_9_class_options(MachineClass *mc) 4856 { 4857 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4858 static GlobalProperty compat[] = { 4859 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4860 }; 4861 4862 spapr_machine_2_10_class_options(mc); 4863 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4864 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4865 smc->pre_2_10_has_unused_icps = true; 4866 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4867 } 4868 4869 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4870 4871 /* 4872 * pseries-2.8 4873 */ 4874 4875 static void spapr_machine_2_8_class_options(MachineClass *mc) 4876 { 4877 static GlobalProperty compat[] = { 4878 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4879 }; 4880 4881 spapr_machine_2_9_class_options(mc); 4882 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4883 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4884 mc->numa_mem_align_shift = 23; 4885 } 4886 4887 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4888 4889 /* 4890 * pseries-2.7 4891 */ 4892 4893 static bool phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4894 uint64_t *buid, hwaddr *pio, 4895 hwaddr *mmio32, hwaddr *mmio64, 4896 unsigned n_dma, uint32_t *liobns, 4897 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4898 { 4899 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4900 const uint64_t base_buid = 0x800000020000000ULL; 4901 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4902 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4903 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4904 const uint32_t max_index = 255; 4905 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4906 4907 uint64_t ram_top = MACHINE(spapr)->ram_size; 4908 hwaddr phb0_base, phb_base; 4909 int i; 4910 4911 /* Do we have device memory? */ 4912 if (MACHINE(spapr)->maxram_size > ram_top) { 4913 /* Can't just use maxram_size, because there may be an 4914 * alignment gap between normal and device memory regions 4915 */ 4916 ram_top = MACHINE(spapr)->device_memory->base + 4917 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4918 } 4919 4920 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4921 4922 if (index > max_index) { 4923 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4924 max_index); 4925 return false; 4926 } 4927 4928 *buid = base_buid + index; 4929 for (i = 0; i < n_dma; ++i) { 4930 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4931 } 4932 4933 phb_base = phb0_base + index * phb_spacing; 4934 *pio = phb_base + pio_offset; 4935 *mmio32 = phb_base + mmio_offset; 4936 /* 4937 * We don't set the 64-bit MMIO window, relying on the PHB's 4938 * fallback behaviour of automatically splitting a large "32-bit" 4939 * window into contiguous 32-bit and 64-bit windows 4940 */ 4941 4942 *nv2gpa = 0; 4943 *nv2atsd = 0; 4944 return true; 4945 } 4946 4947 static void spapr_machine_2_7_class_options(MachineClass *mc) 4948 { 4949 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4950 static GlobalProperty compat[] = { 4951 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4952 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4953 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4954 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4955 }; 4956 4957 spapr_machine_2_8_class_options(mc); 4958 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4959 mc->default_machine_opts = "modern-hotplug-events=off"; 4960 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4961 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4962 smc->phb_placement = phb_placement_2_7; 4963 } 4964 4965 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4966 4967 /* 4968 * pseries-2.6 4969 */ 4970 4971 static void spapr_machine_2_6_class_options(MachineClass *mc) 4972 { 4973 static GlobalProperty compat[] = { 4974 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4975 }; 4976 4977 spapr_machine_2_7_class_options(mc); 4978 mc->has_hotpluggable_cpus = false; 4979 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4980 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4981 } 4982 4983 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4984 4985 /* 4986 * pseries-2.5 4987 */ 4988 4989 static void spapr_machine_2_5_class_options(MachineClass *mc) 4990 { 4991 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4992 static GlobalProperty compat[] = { 4993 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4994 }; 4995 4996 spapr_machine_2_6_class_options(mc); 4997 smc->use_ohci_by_default = true; 4998 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4999 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5000 } 5001 5002 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 5003 5004 /* 5005 * pseries-2.4 5006 */ 5007 5008 static void spapr_machine_2_4_class_options(MachineClass *mc) 5009 { 5010 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5011 5012 spapr_machine_2_5_class_options(mc); 5013 smc->dr_lmb_enabled = false; 5014 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 5015 } 5016 5017 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 5018 5019 /* 5020 * pseries-2.3 5021 */ 5022 5023 static void spapr_machine_2_3_class_options(MachineClass *mc) 5024 { 5025 static GlobalProperty compat[] = { 5026 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 5027 }; 5028 spapr_machine_2_4_class_options(mc); 5029 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 5030 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5031 } 5032 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 5033 5034 /* 5035 * pseries-2.2 5036 */ 5037 5038 static void spapr_machine_2_2_class_options(MachineClass *mc) 5039 { 5040 static GlobalProperty compat[] = { 5041 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 5042 }; 5043 5044 spapr_machine_2_3_class_options(mc); 5045 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 5046 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5047 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 5048 } 5049 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 5050 5051 /* 5052 * pseries-2.1 5053 */ 5054 5055 static void spapr_machine_2_1_class_options(MachineClass *mc) 5056 { 5057 spapr_machine_2_2_class_options(mc); 5058 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 5059 } 5060 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 5061 5062 static void spapr_machine_register_types(void) 5063 { 5064 type_register_static(&spapr_machine_info); 5065 } 5066 5067 type_init(spapr_machine_register_types) 5068