1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/numa.h" 31 #include "hw/hw.h" 32 #include "qemu/log.h" 33 #include "hw/fw-path-provider.h" 34 #include "elf.h" 35 #include "net/net.h" 36 #include "sysemu/device_tree.h" 37 #include "sysemu/block-backend.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/hw_accel.h" 40 #include "kvm_ppc.h" 41 #include "migration/migration.h" 42 #include "mmu-hash64.h" 43 #include "qom/cpu.h" 44 45 #include "hw/boards.h" 46 #include "hw/ppc/ppc.h" 47 #include "hw/loader.h" 48 49 #include "hw/ppc/fdt.h" 50 #include "hw/ppc/spapr.h" 51 #include "hw/ppc/spapr_vio.h" 52 #include "hw/pci-host/spapr.h" 53 #include "hw/ppc/xics.h" 54 #include "hw/pci/msi.h" 55 56 #include "hw/pci/pci.h" 57 #include "hw/scsi/scsi.h" 58 #include "hw/virtio/virtio-scsi.h" 59 60 #include "exec/address-spaces.h" 61 #include "hw/usb.h" 62 #include "qemu/config-file.h" 63 #include "qemu/error-report.h" 64 #include "trace.h" 65 #include "hw/nmi.h" 66 67 #include "hw/compat.h" 68 #include "qemu/cutils.h" 69 #include "hw/ppc/spapr_cpu_core.h" 70 #include "qmp-commands.h" 71 72 #include <libfdt.h> 73 74 /* SLOF memory layout: 75 * 76 * SLOF raw image loaded at 0, copies its romfs right below the flat 77 * device-tree, then position SLOF itself 31M below that 78 * 79 * So we set FW_OVERHEAD to 40MB which should account for all of that 80 * and more 81 * 82 * We load our kernel at 4M, leaving space for SLOF initial image 83 */ 84 #define FDT_MAX_SIZE 0x100000 85 #define RTAS_MAX_SIZE 0x10000 86 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 87 #define FW_MAX_SIZE 0x400000 88 #define FW_FILE_NAME "slof.bin" 89 #define FW_OVERHEAD 0x2800000 90 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 91 92 #define MIN_RMA_SLOF 128UL 93 94 #define PHANDLE_XICP 0x00001111 95 96 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 97 98 static int try_create_xics(sPAPRMachineState *spapr, const char *type_ics, 99 const char *type_icp, int nr_servers, 100 int nr_irqs, Error **errp) 101 { 102 XICSFabric *xi = XICS_FABRIC(spapr); 103 Error *err = NULL, *local_err = NULL; 104 ICSState *ics = NULL; 105 int i; 106 107 ics = ICS_SIMPLE(object_new(type_ics)); 108 qdev_set_parent_bus(DEVICE(ics), sysbus_get_default()); 109 object_property_add_child(OBJECT(spapr), "ics", OBJECT(ics), NULL); 110 object_property_set_int(OBJECT(ics), nr_irqs, "nr-irqs", &err); 111 object_property_add_const_link(OBJECT(ics), "xics", OBJECT(xi), NULL); 112 object_property_set_bool(OBJECT(ics), true, "realized", &local_err); 113 error_propagate(&err, local_err); 114 if (err) { 115 goto error; 116 } 117 118 spapr->icps = g_malloc0(nr_servers * sizeof(ICPState)); 119 spapr->nr_servers = nr_servers; 120 121 for (i = 0; i < nr_servers; i++) { 122 ICPState *icp = &spapr->icps[i]; 123 124 object_initialize(icp, sizeof(*icp), type_icp); 125 qdev_set_parent_bus(DEVICE(icp), sysbus_get_default()); 126 object_property_add_child(OBJECT(spapr), "icp[*]", OBJECT(icp), NULL); 127 object_property_add_const_link(OBJECT(icp), "xics", OBJECT(xi), NULL); 128 object_property_set_bool(OBJECT(icp), true, "realized", &err); 129 if (err) { 130 goto error; 131 } 132 object_unref(OBJECT(icp)); 133 } 134 135 spapr->ics = ics; 136 return 0; 137 138 error: 139 error_propagate(errp, err); 140 if (ics) { 141 object_unparent(OBJECT(ics)); 142 } 143 return -1; 144 } 145 146 static int xics_system_init(MachineState *machine, 147 int nr_servers, int nr_irqs, Error **errp) 148 { 149 int rc = -1; 150 151 if (kvm_enabled()) { 152 Error *err = NULL; 153 154 if (machine_kernel_irqchip_allowed(machine) && 155 !xics_kvm_init(SPAPR_MACHINE(machine), errp)) { 156 rc = try_create_xics(SPAPR_MACHINE(machine), TYPE_ICS_KVM, 157 TYPE_KVM_ICP, nr_servers, nr_irqs, &err); 158 } 159 if (machine_kernel_irqchip_required(machine) && rc < 0) { 160 error_reportf_err(err, 161 "kernel_irqchip requested but unavailable: "); 162 } else { 163 error_free(err); 164 } 165 } 166 167 if (rc < 0) { 168 xics_spapr_init(SPAPR_MACHINE(machine), errp); 169 rc = try_create_xics(SPAPR_MACHINE(machine), TYPE_ICS_SIMPLE, 170 TYPE_ICP, nr_servers, nr_irqs, errp); 171 } 172 173 return rc; 174 } 175 176 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 177 int smt_threads) 178 { 179 int i, ret = 0; 180 uint32_t servers_prop[smt_threads]; 181 uint32_t gservers_prop[smt_threads * 2]; 182 int index = ppc_get_vcpu_dt_id(cpu); 183 184 if (cpu->compat_pvr) { 185 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 186 if (ret < 0) { 187 return ret; 188 } 189 } 190 191 /* Build interrupt servers and gservers properties */ 192 for (i = 0; i < smt_threads; i++) { 193 servers_prop[i] = cpu_to_be32(index + i); 194 /* Hack, direct the group queues back to cpu 0 */ 195 gservers_prop[i*2] = cpu_to_be32(index + i); 196 gservers_prop[i*2 + 1] = 0; 197 } 198 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 199 servers_prop, sizeof(servers_prop)); 200 if (ret < 0) { 201 return ret; 202 } 203 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 204 gservers_prop, sizeof(gservers_prop)); 205 206 return ret; 207 } 208 209 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs) 210 { 211 int ret = 0; 212 PowerPCCPU *cpu = POWERPC_CPU(cs); 213 int index = ppc_get_vcpu_dt_id(cpu); 214 uint32_t associativity[] = {cpu_to_be32(0x5), 215 cpu_to_be32(0x0), 216 cpu_to_be32(0x0), 217 cpu_to_be32(0x0), 218 cpu_to_be32(cs->numa_node), 219 cpu_to_be32(index)}; 220 221 /* Advertise NUMA via ibm,associativity */ 222 if (nb_numa_nodes > 1) { 223 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 224 sizeof(associativity)); 225 } 226 227 return ret; 228 } 229 230 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 231 { 232 int ret = 0, offset, cpus_offset; 233 CPUState *cs; 234 char cpu_model[32]; 235 int smt = kvmppc_smt_threads(); 236 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 237 238 CPU_FOREACH(cs) { 239 PowerPCCPU *cpu = POWERPC_CPU(cs); 240 DeviceClass *dc = DEVICE_GET_CLASS(cs); 241 int index = ppc_get_vcpu_dt_id(cpu); 242 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 243 244 if ((index % smt) != 0) { 245 continue; 246 } 247 248 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 249 250 cpus_offset = fdt_path_offset(fdt, "/cpus"); 251 if (cpus_offset < 0) { 252 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 253 "cpus"); 254 if (cpus_offset < 0) { 255 return cpus_offset; 256 } 257 } 258 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 259 if (offset < 0) { 260 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 261 if (offset < 0) { 262 return offset; 263 } 264 } 265 266 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 267 pft_size_prop, sizeof(pft_size_prop)); 268 if (ret < 0) { 269 return ret; 270 } 271 272 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs); 273 if (ret < 0) { 274 return ret; 275 } 276 277 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 278 if (ret < 0) { 279 return ret; 280 } 281 } 282 return ret; 283 } 284 285 static hwaddr spapr_node0_size(void) 286 { 287 MachineState *machine = MACHINE(qdev_get_machine()); 288 289 if (nb_numa_nodes) { 290 int i; 291 for (i = 0; i < nb_numa_nodes; ++i) { 292 if (numa_info[i].node_mem) { 293 return MIN(pow2floor(numa_info[i].node_mem), 294 machine->ram_size); 295 } 296 } 297 } 298 return machine->ram_size; 299 } 300 301 static void add_str(GString *s, const gchar *s1) 302 { 303 g_string_append_len(s, s1, strlen(s1) + 1); 304 } 305 306 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 307 hwaddr size) 308 { 309 uint32_t associativity[] = { 310 cpu_to_be32(0x4), /* length */ 311 cpu_to_be32(0x0), cpu_to_be32(0x0), 312 cpu_to_be32(0x0), cpu_to_be32(nodeid) 313 }; 314 char mem_name[32]; 315 uint64_t mem_reg_property[2]; 316 int off; 317 318 mem_reg_property[0] = cpu_to_be64(start); 319 mem_reg_property[1] = cpu_to_be64(size); 320 321 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 322 off = fdt_add_subnode(fdt, 0, mem_name); 323 _FDT(off); 324 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 325 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 326 sizeof(mem_reg_property)))); 327 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 328 sizeof(associativity)))); 329 return off; 330 } 331 332 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 333 { 334 MachineState *machine = MACHINE(spapr); 335 hwaddr mem_start, node_size; 336 int i, nb_nodes = nb_numa_nodes; 337 NodeInfo *nodes = numa_info; 338 NodeInfo ramnode; 339 340 /* No NUMA nodes, assume there is just one node with whole RAM */ 341 if (!nb_numa_nodes) { 342 nb_nodes = 1; 343 ramnode.node_mem = machine->ram_size; 344 nodes = &ramnode; 345 } 346 347 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 348 if (!nodes[i].node_mem) { 349 continue; 350 } 351 if (mem_start >= machine->ram_size) { 352 node_size = 0; 353 } else { 354 node_size = nodes[i].node_mem; 355 if (node_size > machine->ram_size - mem_start) { 356 node_size = machine->ram_size - mem_start; 357 } 358 } 359 if (!mem_start) { 360 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 361 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 362 mem_start += spapr->rma_size; 363 node_size -= spapr->rma_size; 364 } 365 for ( ; node_size; ) { 366 hwaddr sizetmp = pow2floor(node_size); 367 368 /* mem_start != 0 here */ 369 if (ctzl(mem_start) < ctzl(sizetmp)) { 370 sizetmp = 1ULL << ctzl(mem_start); 371 } 372 373 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 374 node_size -= sizetmp; 375 mem_start += sizetmp; 376 } 377 } 378 379 return 0; 380 } 381 382 /* Populate the "ibm,pa-features" property */ 383 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset) 384 { 385 uint8_t pa_features_206[] = { 6, 0, 386 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 387 uint8_t pa_features_207[] = { 24, 0, 388 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 389 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 390 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 391 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 392 uint8_t *pa_features; 393 size_t pa_size; 394 395 switch (env->mmu_model) { 396 case POWERPC_MMU_2_06: 397 case POWERPC_MMU_2_06a: 398 pa_features = pa_features_206; 399 pa_size = sizeof(pa_features_206); 400 break; 401 case POWERPC_MMU_2_07: 402 case POWERPC_MMU_2_07a: 403 pa_features = pa_features_207; 404 pa_size = sizeof(pa_features_207); 405 break; 406 default: 407 return; 408 } 409 410 if (env->ci_large_pages) { 411 /* 412 * Note: we keep CI large pages off by default because a 64K capable 413 * guest provisioned with large pages might otherwise try to map a qemu 414 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 415 * even if that qemu runs on a 4k host. 416 * We dd this bit back here if we are confident this is not an issue 417 */ 418 pa_features[3] |= 0x20; 419 } 420 if (kvmppc_has_cap_htm() && pa_size > 24) { 421 pa_features[24] |= 0x80; /* Transactional memory support */ 422 } 423 424 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 425 } 426 427 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 428 sPAPRMachineState *spapr) 429 { 430 PowerPCCPU *cpu = POWERPC_CPU(cs); 431 CPUPPCState *env = &cpu->env; 432 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 433 int index = ppc_get_vcpu_dt_id(cpu); 434 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 435 0xffffffff, 0xffffffff}; 436 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 437 : SPAPR_TIMEBASE_FREQ; 438 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 439 uint32_t page_sizes_prop[64]; 440 size_t page_sizes_prop_size; 441 uint32_t vcpus_per_socket = smp_threads * smp_cores; 442 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 443 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 444 sPAPRDRConnector *drc; 445 sPAPRDRConnectorClass *drck; 446 int drc_index; 447 448 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index); 449 if (drc) { 450 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 451 drc_index = drck->get_index(drc); 452 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 453 } 454 455 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 456 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 457 458 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 459 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 460 env->dcache_line_size))); 461 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 462 env->dcache_line_size))); 463 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 464 env->icache_line_size))); 465 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 466 env->icache_line_size))); 467 468 if (pcc->l1_dcache_size) { 469 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 470 pcc->l1_dcache_size))); 471 } else { 472 error_report("Warning: Unknown L1 dcache size for cpu"); 473 } 474 if (pcc->l1_icache_size) { 475 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 476 pcc->l1_icache_size))); 477 } else { 478 error_report("Warning: Unknown L1 icache size for cpu"); 479 } 480 481 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 482 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 483 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 484 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 485 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 486 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 487 488 if (env->spr_cb[SPR_PURR].oea_read) { 489 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 490 } 491 492 if (env->mmu_model & POWERPC_MMU_1TSEG) { 493 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 494 segs, sizeof(segs)))); 495 } 496 497 /* Advertise VMX/VSX (vector extensions) if available 498 * 0 / no property == no vector extensions 499 * 1 == VMX / Altivec available 500 * 2 == VSX available */ 501 if (env->insns_flags & PPC_ALTIVEC) { 502 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 503 504 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 505 } 506 507 /* Advertise DFP (Decimal Floating Point) if available 508 * 0 / no property == no DFP 509 * 1 == DFP available */ 510 if (env->insns_flags2 & PPC2_DFP) { 511 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 512 } 513 514 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 515 sizeof(page_sizes_prop)); 516 if (page_sizes_prop_size) { 517 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 518 page_sizes_prop, page_sizes_prop_size))); 519 } 520 521 spapr_populate_pa_features(env, fdt, offset); 522 523 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 524 cs->cpu_index / vcpus_per_socket))); 525 526 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 527 pft_size_prop, sizeof(pft_size_prop)))); 528 529 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs)); 530 531 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 532 } 533 534 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 535 { 536 CPUState *cs; 537 int cpus_offset; 538 char *nodename; 539 int smt = kvmppc_smt_threads(); 540 541 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 542 _FDT(cpus_offset); 543 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 544 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 545 546 /* 547 * We walk the CPUs in reverse order to ensure that CPU DT nodes 548 * created by fdt_add_subnode() end up in the right order in FDT 549 * for the guest kernel the enumerate the CPUs correctly. 550 */ 551 CPU_FOREACH_REVERSE(cs) { 552 PowerPCCPU *cpu = POWERPC_CPU(cs); 553 int index = ppc_get_vcpu_dt_id(cpu); 554 DeviceClass *dc = DEVICE_GET_CLASS(cs); 555 int offset; 556 557 if ((index % smt) != 0) { 558 continue; 559 } 560 561 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 562 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 563 g_free(nodename); 564 _FDT(offset); 565 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 566 } 567 568 } 569 570 /* 571 * Adds ibm,dynamic-reconfiguration-memory node. 572 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 573 * of this device tree node. 574 */ 575 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 576 { 577 MachineState *machine = MACHINE(spapr); 578 int ret, i, offset; 579 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 580 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 581 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 582 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 583 memory_region_size(&spapr->hotplug_memory.mr)) / 584 lmb_size; 585 uint32_t *int_buf, *cur_index, buf_len; 586 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 587 588 /* 589 * Don't create the node if there is no hotpluggable memory 590 */ 591 if (machine->ram_size == machine->maxram_size) { 592 return 0; 593 } 594 595 /* 596 * Allocate enough buffer size to fit in ibm,dynamic-memory 597 * or ibm,associativity-lookup-arrays 598 */ 599 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 600 * sizeof(uint32_t); 601 cur_index = int_buf = g_malloc0(buf_len); 602 603 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 604 605 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 606 sizeof(prop_lmb_size)); 607 if (ret < 0) { 608 goto out; 609 } 610 611 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 612 if (ret < 0) { 613 goto out; 614 } 615 616 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 617 if (ret < 0) { 618 goto out; 619 } 620 621 /* ibm,dynamic-memory */ 622 int_buf[0] = cpu_to_be32(nr_lmbs); 623 cur_index++; 624 for (i = 0; i < nr_lmbs; i++) { 625 uint64_t addr = i * lmb_size; 626 uint32_t *dynamic_memory = cur_index; 627 628 if (i >= hotplug_lmb_start) { 629 sPAPRDRConnector *drc; 630 sPAPRDRConnectorClass *drck; 631 632 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i); 633 g_assert(drc); 634 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 635 636 dynamic_memory[0] = cpu_to_be32(addr >> 32); 637 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 638 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); 639 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 640 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); 641 if (memory_region_present(get_system_memory(), addr)) { 642 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 643 } else { 644 dynamic_memory[5] = cpu_to_be32(0); 645 } 646 } else { 647 /* 648 * LMB information for RMA, boot time RAM and gap b/n RAM and 649 * hotplug memory region -- all these are marked as reserved 650 * and as having no valid DRC. 651 */ 652 dynamic_memory[0] = cpu_to_be32(addr >> 32); 653 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 654 dynamic_memory[2] = cpu_to_be32(0); 655 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 656 dynamic_memory[4] = cpu_to_be32(-1); 657 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 658 SPAPR_LMB_FLAGS_DRC_INVALID); 659 } 660 661 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 662 } 663 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 664 if (ret < 0) { 665 goto out; 666 } 667 668 /* ibm,associativity-lookup-arrays */ 669 cur_index = int_buf; 670 int_buf[0] = cpu_to_be32(nr_nodes); 671 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 672 cur_index += 2; 673 for (i = 0; i < nr_nodes; i++) { 674 uint32_t associativity[] = { 675 cpu_to_be32(0x0), 676 cpu_to_be32(0x0), 677 cpu_to_be32(0x0), 678 cpu_to_be32(i) 679 }; 680 memcpy(cur_index, associativity, sizeof(associativity)); 681 cur_index += 4; 682 } 683 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 684 (cur_index - int_buf) * sizeof(uint32_t)); 685 out: 686 g_free(int_buf); 687 return ret; 688 } 689 690 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 691 sPAPROptionVector *ov5_updates) 692 { 693 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 694 int ret = 0, offset; 695 696 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 697 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 698 g_assert(smc->dr_lmb_enabled); 699 ret = spapr_populate_drconf_memory(spapr, fdt); 700 if (ret) { 701 goto out; 702 } 703 } 704 705 offset = fdt_path_offset(fdt, "/chosen"); 706 if (offset < 0) { 707 offset = fdt_add_subnode(fdt, 0, "chosen"); 708 if (offset < 0) { 709 return offset; 710 } 711 } 712 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 713 "ibm,architecture-vec-5"); 714 715 out: 716 return ret; 717 } 718 719 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 720 target_ulong addr, target_ulong size, 721 sPAPROptionVector *ov5_updates) 722 { 723 void *fdt, *fdt_skel; 724 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 725 726 size -= sizeof(hdr); 727 728 /* Create sceleton */ 729 fdt_skel = g_malloc0(size); 730 _FDT((fdt_create(fdt_skel, size))); 731 _FDT((fdt_begin_node(fdt_skel, ""))); 732 _FDT((fdt_end_node(fdt_skel))); 733 _FDT((fdt_finish(fdt_skel))); 734 fdt = g_malloc0(size); 735 _FDT((fdt_open_into(fdt_skel, fdt, size))); 736 g_free(fdt_skel); 737 738 /* Fixup cpu nodes */ 739 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 740 741 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 742 return -1; 743 } 744 745 /* Pack resulting tree */ 746 _FDT((fdt_pack(fdt))); 747 748 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 749 trace_spapr_cas_failed(size); 750 return -1; 751 } 752 753 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 754 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 755 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 756 g_free(fdt); 757 758 return 0; 759 } 760 761 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 762 { 763 int rtas; 764 GString *hypertas = g_string_sized_new(256); 765 GString *qemu_hypertas = g_string_sized_new(256); 766 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 767 uint64_t max_hotplug_addr = spapr->hotplug_memory.base + 768 memory_region_size(&spapr->hotplug_memory.mr); 769 uint32_t lrdr_capacity[] = { 770 cpu_to_be32(max_hotplug_addr >> 32), 771 cpu_to_be32(max_hotplug_addr & 0xffffffff), 772 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 773 cpu_to_be32(max_cpus / smp_threads), 774 }; 775 776 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 777 778 /* hypertas */ 779 add_str(hypertas, "hcall-pft"); 780 add_str(hypertas, "hcall-term"); 781 add_str(hypertas, "hcall-dabr"); 782 add_str(hypertas, "hcall-interrupt"); 783 add_str(hypertas, "hcall-tce"); 784 add_str(hypertas, "hcall-vio"); 785 add_str(hypertas, "hcall-splpar"); 786 add_str(hypertas, "hcall-bulk"); 787 add_str(hypertas, "hcall-set-mode"); 788 add_str(hypertas, "hcall-sprg0"); 789 add_str(hypertas, "hcall-copy"); 790 add_str(hypertas, "hcall-debug"); 791 add_str(qemu_hypertas, "hcall-memop1"); 792 793 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 794 add_str(hypertas, "hcall-multi-tce"); 795 } 796 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 797 hypertas->str, hypertas->len)); 798 g_string_free(hypertas, TRUE); 799 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 800 qemu_hypertas->str, qemu_hypertas->len)); 801 g_string_free(qemu_hypertas, TRUE); 802 803 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 804 refpoints, sizeof(refpoints))); 805 806 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 807 RTAS_ERROR_LOG_MAX)); 808 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 809 RTAS_EVENT_SCAN_RATE)); 810 811 if (msi_nonbroken) { 812 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 813 } 814 815 /* 816 * According to PAPR, rtas ibm,os-term does not guarantee a return 817 * back to the guest cpu. 818 * 819 * While an additional ibm,extended-os-term property indicates 820 * that rtas call return will always occur. Set this property. 821 */ 822 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 823 824 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 825 lrdr_capacity, sizeof(lrdr_capacity))); 826 827 spapr_dt_rtas_tokens(fdt, rtas); 828 } 829 830 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 831 { 832 MachineState *machine = MACHINE(spapr); 833 int chosen; 834 const char *boot_device = machine->boot_order; 835 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 836 size_t cb = 0; 837 char *bootlist = get_boot_devices_list(&cb, true); 838 839 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 840 841 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 842 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 843 spapr->initrd_base)); 844 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 845 spapr->initrd_base + spapr->initrd_size)); 846 847 if (spapr->kernel_size) { 848 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 849 cpu_to_be64(spapr->kernel_size) }; 850 851 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 852 &kprop, sizeof(kprop))); 853 if (spapr->kernel_le) { 854 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 855 } 856 } 857 if (boot_menu) { 858 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 859 } 860 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 861 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 862 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 863 864 if (cb && bootlist) { 865 int i; 866 867 for (i = 0; i < cb; i++) { 868 if (bootlist[i] == '\n') { 869 bootlist[i] = ' '; 870 } 871 } 872 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 873 } 874 875 if (boot_device && strlen(boot_device)) { 876 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 877 } 878 879 if (!spapr->has_graphics && stdout_path) { 880 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 881 } 882 883 g_free(stdout_path); 884 g_free(bootlist); 885 } 886 887 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 888 { 889 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 890 * KVM to work under pHyp with some guest co-operation */ 891 int hypervisor; 892 uint8_t hypercall[16]; 893 894 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 895 /* indicate KVM hypercall interface */ 896 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 897 if (kvmppc_has_cap_fixup_hcalls()) { 898 /* 899 * Older KVM versions with older guest kernels were broken 900 * with the magic page, don't allow the guest to map it. 901 */ 902 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 903 sizeof(hypercall))) { 904 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 905 hypercall, sizeof(hypercall))); 906 } 907 } 908 } 909 910 static void *spapr_build_fdt(sPAPRMachineState *spapr, 911 hwaddr rtas_addr, 912 hwaddr rtas_size) 913 { 914 MachineState *machine = MACHINE(qdev_get_machine()); 915 MachineClass *mc = MACHINE_GET_CLASS(machine); 916 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 917 int ret; 918 void *fdt; 919 sPAPRPHBState *phb; 920 char *buf; 921 922 fdt = g_malloc0(FDT_MAX_SIZE); 923 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 924 925 /* Root node */ 926 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 927 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 928 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 929 930 /* 931 * Add info to guest to indentify which host is it being run on 932 * and what is the uuid of the guest 933 */ 934 if (kvmppc_get_host_model(&buf)) { 935 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 936 g_free(buf); 937 } 938 if (kvmppc_get_host_serial(&buf)) { 939 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 940 g_free(buf); 941 } 942 943 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 944 945 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 946 if (qemu_uuid_set) { 947 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 948 } 949 g_free(buf); 950 951 if (qemu_get_vm_name()) { 952 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 953 qemu_get_vm_name())); 954 } 955 956 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 957 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 958 959 /* /interrupt controller */ 960 spapr_dt_xics(spapr->nr_servers, fdt, PHANDLE_XICP); 961 962 ret = spapr_populate_memory(spapr, fdt); 963 if (ret < 0) { 964 error_report("couldn't setup memory nodes in fdt"); 965 exit(1); 966 } 967 968 /* /vdevice */ 969 spapr_dt_vdevice(spapr->vio_bus, fdt); 970 971 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 972 ret = spapr_rng_populate_dt(fdt); 973 if (ret < 0) { 974 error_report("could not set up rng device in the fdt"); 975 exit(1); 976 } 977 } 978 979 QLIST_FOREACH(phb, &spapr->phbs, list) { 980 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 981 if (ret < 0) { 982 error_report("couldn't setup PCI devices in fdt"); 983 exit(1); 984 } 985 } 986 987 /* cpus */ 988 spapr_populate_cpus_dt_node(fdt, spapr); 989 990 if (smc->dr_lmb_enabled) { 991 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 992 } 993 994 if (mc->has_hotpluggable_cpus) { 995 int offset = fdt_path_offset(fdt, "/cpus"); 996 ret = spapr_drc_populate_dt(fdt, offset, NULL, 997 SPAPR_DR_CONNECTOR_TYPE_CPU); 998 if (ret < 0) { 999 error_report("Couldn't set up CPU DR device tree properties"); 1000 exit(1); 1001 } 1002 } 1003 1004 /* /event-sources */ 1005 spapr_dt_events(spapr, fdt); 1006 1007 /* /rtas */ 1008 spapr_dt_rtas(spapr, fdt); 1009 1010 /* /chosen */ 1011 spapr_dt_chosen(spapr, fdt); 1012 1013 /* /hypervisor */ 1014 if (kvm_enabled()) { 1015 spapr_dt_hypervisor(spapr, fdt); 1016 } 1017 1018 /* Build memory reserve map */ 1019 if (spapr->kernel_size) { 1020 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1021 } 1022 if (spapr->initrd_size) { 1023 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1024 } 1025 1026 /* ibm,client-architecture-support updates */ 1027 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1028 if (ret < 0) { 1029 error_report("couldn't setup CAS properties fdt"); 1030 exit(1); 1031 } 1032 1033 return fdt; 1034 } 1035 1036 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1037 { 1038 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1039 } 1040 1041 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1042 PowerPCCPU *cpu) 1043 { 1044 CPUPPCState *env = &cpu->env; 1045 1046 /* The TCG path should also be holding the BQL at this point */ 1047 g_assert(qemu_mutex_iothread_locked()); 1048 1049 if (msr_pr) { 1050 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1051 env->gpr[3] = H_PRIVILEGE; 1052 } else { 1053 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1054 } 1055 } 1056 1057 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1058 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1059 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1060 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1061 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1062 1063 /* 1064 * Get the fd to access the kernel htab, re-opening it if necessary 1065 */ 1066 static int get_htab_fd(sPAPRMachineState *spapr) 1067 { 1068 if (spapr->htab_fd >= 0) { 1069 return spapr->htab_fd; 1070 } 1071 1072 spapr->htab_fd = kvmppc_get_htab_fd(false); 1073 if (spapr->htab_fd < 0) { 1074 error_report("Unable to open fd for reading hash table from KVM: %s", 1075 strerror(errno)); 1076 } 1077 1078 return spapr->htab_fd; 1079 } 1080 1081 static void close_htab_fd(sPAPRMachineState *spapr) 1082 { 1083 if (spapr->htab_fd >= 0) { 1084 close(spapr->htab_fd); 1085 } 1086 spapr->htab_fd = -1; 1087 } 1088 1089 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1090 { 1091 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1092 1093 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1094 } 1095 1096 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1097 hwaddr ptex, int n) 1098 { 1099 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1100 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1101 1102 if (!spapr->htab) { 1103 /* 1104 * HTAB is controlled by KVM. Fetch into temporary buffer 1105 */ 1106 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1107 kvmppc_read_hptes(hptes, ptex, n); 1108 return hptes; 1109 } 1110 1111 /* 1112 * HTAB is controlled by QEMU. Just point to the internally 1113 * accessible PTEG. 1114 */ 1115 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1116 } 1117 1118 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1119 const ppc_hash_pte64_t *hptes, 1120 hwaddr ptex, int n) 1121 { 1122 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1123 1124 if (!spapr->htab) { 1125 g_free((void *)hptes); 1126 } 1127 1128 /* Nothing to do for qemu managed HPT */ 1129 } 1130 1131 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1132 uint64_t pte0, uint64_t pte1) 1133 { 1134 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1135 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1136 1137 if (!spapr->htab) { 1138 kvmppc_write_hpte(ptex, pte0, pte1); 1139 } else { 1140 stq_p(spapr->htab + offset, pte0); 1141 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1142 } 1143 } 1144 1145 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1146 { 1147 int shift; 1148 1149 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1150 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1151 * that's much more than is needed for Linux guests */ 1152 shift = ctz64(pow2ceil(ramsize)) - 7; 1153 shift = MAX(shift, 18); /* Minimum architected size */ 1154 shift = MIN(shift, 46); /* Maximum architected size */ 1155 return shift; 1156 } 1157 1158 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1159 Error **errp) 1160 { 1161 long rc; 1162 1163 /* Clean up any HPT info from a previous boot */ 1164 g_free(spapr->htab); 1165 spapr->htab = NULL; 1166 spapr->htab_shift = 0; 1167 close_htab_fd(spapr); 1168 1169 rc = kvmppc_reset_htab(shift); 1170 if (rc < 0) { 1171 /* kernel-side HPT needed, but couldn't allocate one */ 1172 error_setg_errno(errp, errno, 1173 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1174 shift); 1175 /* This is almost certainly fatal, but if the caller really 1176 * wants to carry on with shift == 0, it's welcome to try */ 1177 } else if (rc > 0) { 1178 /* kernel-side HPT allocated */ 1179 if (rc != shift) { 1180 error_setg(errp, 1181 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1182 shift, rc); 1183 } 1184 1185 spapr->htab_shift = shift; 1186 spapr->htab = NULL; 1187 } else { 1188 /* kernel-side HPT not needed, allocate in userspace instead */ 1189 size_t size = 1ULL << shift; 1190 int i; 1191 1192 spapr->htab = qemu_memalign(size, size); 1193 if (!spapr->htab) { 1194 error_setg_errno(errp, errno, 1195 "Could not allocate HPT of order %d", shift); 1196 return; 1197 } 1198 1199 memset(spapr->htab, 0, size); 1200 spapr->htab_shift = shift; 1201 1202 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1203 DIRTY_HPTE(HPTE(spapr->htab, i)); 1204 } 1205 } 1206 } 1207 1208 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1209 { 1210 bool matched = false; 1211 1212 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1213 matched = true; 1214 } 1215 1216 if (!matched) { 1217 error_report("Device %s is not supported by this machine yet.", 1218 qdev_fw_name(DEVICE(sbdev))); 1219 exit(1); 1220 } 1221 } 1222 1223 static void ppc_spapr_reset(void) 1224 { 1225 MachineState *machine = MACHINE(qdev_get_machine()); 1226 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1227 PowerPCCPU *first_ppc_cpu; 1228 uint32_t rtas_limit; 1229 hwaddr rtas_addr, fdt_addr; 1230 void *fdt; 1231 int rc; 1232 1233 /* Check for unknown sysbus devices */ 1234 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1235 1236 /* Allocate and/or reset the hash page table */ 1237 spapr_reallocate_hpt(spapr, 1238 spapr_hpt_shift_for_ramsize(machine->maxram_size), 1239 &error_fatal); 1240 1241 /* Update the RMA size if necessary */ 1242 if (spapr->vrma_adjust) { 1243 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 1244 spapr->htab_shift); 1245 } 1246 1247 qemu_devices_reset(); 1248 1249 /* 1250 * We place the device tree and RTAS just below either the top of the RMA, 1251 * or just below 2GB, whichever is lowere, so that it can be 1252 * processed with 32-bit real mode code if necessary 1253 */ 1254 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1255 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1256 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1257 1258 /* if this reset wasn't generated by CAS, we should reset our 1259 * negotiated options and start from scratch */ 1260 if (!spapr->cas_reboot) { 1261 spapr_ovec_cleanup(spapr->ov5_cas); 1262 spapr->ov5_cas = spapr_ovec_new(); 1263 } 1264 1265 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1266 1267 spapr_load_rtas(spapr, fdt, rtas_addr); 1268 1269 rc = fdt_pack(fdt); 1270 1271 /* Should only fail if we've built a corrupted tree */ 1272 assert(rc == 0); 1273 1274 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1275 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1276 fdt_totalsize(fdt), FDT_MAX_SIZE); 1277 exit(1); 1278 } 1279 1280 /* Load the fdt */ 1281 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1282 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1283 g_free(fdt); 1284 1285 /* Set up the entry state */ 1286 first_ppc_cpu = POWERPC_CPU(first_cpu); 1287 first_ppc_cpu->env.gpr[3] = fdt_addr; 1288 first_ppc_cpu->env.gpr[5] = 0; 1289 first_cpu->halted = 0; 1290 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1291 1292 spapr->cas_reboot = false; 1293 } 1294 1295 static void spapr_create_nvram(sPAPRMachineState *spapr) 1296 { 1297 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1298 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1299 1300 if (dinfo) { 1301 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1302 &error_fatal); 1303 } 1304 1305 qdev_init_nofail(dev); 1306 1307 spapr->nvram = (struct sPAPRNVRAM *)dev; 1308 } 1309 1310 static void spapr_rtc_create(sPAPRMachineState *spapr) 1311 { 1312 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC); 1313 1314 qdev_init_nofail(dev); 1315 spapr->rtc = dev; 1316 1317 object_property_add_alias(qdev_get_machine(), "rtc-time", 1318 OBJECT(spapr->rtc), "date", NULL); 1319 } 1320 1321 /* Returns whether we want to use VGA or not */ 1322 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1323 { 1324 switch (vga_interface_type) { 1325 case VGA_NONE: 1326 return false; 1327 case VGA_DEVICE: 1328 return true; 1329 case VGA_STD: 1330 case VGA_VIRTIO: 1331 return pci_vga_init(pci_bus) != NULL; 1332 default: 1333 error_setg(errp, 1334 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1335 return false; 1336 } 1337 } 1338 1339 static int spapr_post_load(void *opaque, int version_id) 1340 { 1341 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1342 int err = 0; 1343 1344 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { 1345 int i; 1346 for (i = 0; i < spapr->nr_servers; i++) { 1347 icp_resend(&spapr->icps[i]); 1348 } 1349 } 1350 1351 /* In earlier versions, there was no separate qdev for the PAPR 1352 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1353 * So when migrating from those versions, poke the incoming offset 1354 * value into the RTC device */ 1355 if (version_id < 3) { 1356 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset); 1357 } 1358 1359 return err; 1360 } 1361 1362 static bool version_before_3(void *opaque, int version_id) 1363 { 1364 return version_id < 3; 1365 } 1366 1367 static bool spapr_ov5_cas_needed(void *opaque) 1368 { 1369 sPAPRMachineState *spapr = opaque; 1370 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1371 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1372 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1373 bool cas_needed; 1374 1375 /* Prior to the introduction of sPAPROptionVector, we had two option 1376 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1377 * Both of these options encode machine topology into the device-tree 1378 * in such a way that the now-booted OS should still be able to interact 1379 * appropriately with QEMU regardless of what options were actually 1380 * negotiatied on the source side. 1381 * 1382 * As such, we can avoid migrating the CAS-negotiated options if these 1383 * are the only options available on the current machine/platform. 1384 * Since these are the only options available for pseries-2.7 and 1385 * earlier, this allows us to maintain old->new/new->old migration 1386 * compatibility. 1387 * 1388 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1389 * via default pseries-2.8 machines and explicit command-line parameters. 1390 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1391 * of the actual CAS-negotiated values to continue working properly. For 1392 * example, availability of memory unplug depends on knowing whether 1393 * OV5_HP_EVT was negotiated via CAS. 1394 * 1395 * Thus, for any cases where the set of available CAS-negotiatable 1396 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1397 * include the CAS-negotiated options in the migration stream. 1398 */ 1399 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1400 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1401 1402 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1403 * the mask itself since in the future it's possible "legacy" bits may be 1404 * removed via machine options, which could generate a false positive 1405 * that breaks migration. 1406 */ 1407 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1408 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1409 1410 spapr_ovec_cleanup(ov5_mask); 1411 spapr_ovec_cleanup(ov5_legacy); 1412 spapr_ovec_cleanup(ov5_removed); 1413 1414 return cas_needed; 1415 } 1416 1417 static const VMStateDescription vmstate_spapr_ov5_cas = { 1418 .name = "spapr_option_vector_ov5_cas", 1419 .version_id = 1, 1420 .minimum_version_id = 1, 1421 .needed = spapr_ov5_cas_needed, 1422 .fields = (VMStateField[]) { 1423 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1424 vmstate_spapr_ovec, sPAPROptionVector), 1425 VMSTATE_END_OF_LIST() 1426 }, 1427 }; 1428 1429 static const VMStateDescription vmstate_spapr = { 1430 .name = "spapr", 1431 .version_id = 3, 1432 .minimum_version_id = 1, 1433 .post_load = spapr_post_load, 1434 .fields = (VMStateField[]) { 1435 /* used to be @next_irq */ 1436 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1437 1438 /* RTC offset */ 1439 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1440 1441 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1442 VMSTATE_END_OF_LIST() 1443 }, 1444 .subsections = (const VMStateDescription*[]) { 1445 &vmstate_spapr_ov5_cas, 1446 NULL 1447 } 1448 }; 1449 1450 static int htab_save_setup(QEMUFile *f, void *opaque) 1451 { 1452 sPAPRMachineState *spapr = opaque; 1453 1454 /* "Iteration" header */ 1455 qemu_put_be32(f, spapr->htab_shift); 1456 1457 if (spapr->htab) { 1458 spapr->htab_save_index = 0; 1459 spapr->htab_first_pass = true; 1460 } else { 1461 assert(kvm_enabled()); 1462 } 1463 1464 1465 return 0; 1466 } 1467 1468 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1469 int64_t max_ns) 1470 { 1471 bool has_timeout = max_ns != -1; 1472 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1473 int index = spapr->htab_save_index; 1474 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1475 1476 assert(spapr->htab_first_pass); 1477 1478 do { 1479 int chunkstart; 1480 1481 /* Consume invalid HPTEs */ 1482 while ((index < htabslots) 1483 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1484 index++; 1485 CLEAN_HPTE(HPTE(spapr->htab, index)); 1486 } 1487 1488 /* Consume valid HPTEs */ 1489 chunkstart = index; 1490 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1491 && HPTE_VALID(HPTE(spapr->htab, index))) { 1492 index++; 1493 CLEAN_HPTE(HPTE(spapr->htab, index)); 1494 } 1495 1496 if (index > chunkstart) { 1497 int n_valid = index - chunkstart; 1498 1499 qemu_put_be32(f, chunkstart); 1500 qemu_put_be16(f, n_valid); 1501 qemu_put_be16(f, 0); 1502 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1503 HASH_PTE_SIZE_64 * n_valid); 1504 1505 if (has_timeout && 1506 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1507 break; 1508 } 1509 } 1510 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1511 1512 if (index >= htabslots) { 1513 assert(index == htabslots); 1514 index = 0; 1515 spapr->htab_first_pass = false; 1516 } 1517 spapr->htab_save_index = index; 1518 } 1519 1520 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1521 int64_t max_ns) 1522 { 1523 bool final = max_ns < 0; 1524 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1525 int examined = 0, sent = 0; 1526 int index = spapr->htab_save_index; 1527 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1528 1529 assert(!spapr->htab_first_pass); 1530 1531 do { 1532 int chunkstart, invalidstart; 1533 1534 /* Consume non-dirty HPTEs */ 1535 while ((index < htabslots) 1536 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1537 index++; 1538 examined++; 1539 } 1540 1541 chunkstart = index; 1542 /* Consume valid dirty HPTEs */ 1543 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1544 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1545 && HPTE_VALID(HPTE(spapr->htab, index))) { 1546 CLEAN_HPTE(HPTE(spapr->htab, index)); 1547 index++; 1548 examined++; 1549 } 1550 1551 invalidstart = index; 1552 /* Consume invalid dirty HPTEs */ 1553 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1554 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1555 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1556 CLEAN_HPTE(HPTE(spapr->htab, index)); 1557 index++; 1558 examined++; 1559 } 1560 1561 if (index > chunkstart) { 1562 int n_valid = invalidstart - chunkstart; 1563 int n_invalid = index - invalidstart; 1564 1565 qemu_put_be32(f, chunkstart); 1566 qemu_put_be16(f, n_valid); 1567 qemu_put_be16(f, n_invalid); 1568 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1569 HASH_PTE_SIZE_64 * n_valid); 1570 sent += index - chunkstart; 1571 1572 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1573 break; 1574 } 1575 } 1576 1577 if (examined >= htabslots) { 1578 break; 1579 } 1580 1581 if (index >= htabslots) { 1582 assert(index == htabslots); 1583 index = 0; 1584 } 1585 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1586 1587 if (index >= htabslots) { 1588 assert(index == htabslots); 1589 index = 0; 1590 } 1591 1592 spapr->htab_save_index = index; 1593 1594 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1595 } 1596 1597 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1598 #define MAX_KVM_BUF_SIZE 2048 1599 1600 static int htab_save_iterate(QEMUFile *f, void *opaque) 1601 { 1602 sPAPRMachineState *spapr = opaque; 1603 int fd; 1604 int rc = 0; 1605 1606 /* Iteration header */ 1607 qemu_put_be32(f, 0); 1608 1609 if (!spapr->htab) { 1610 assert(kvm_enabled()); 1611 1612 fd = get_htab_fd(spapr); 1613 if (fd < 0) { 1614 return fd; 1615 } 1616 1617 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1618 if (rc < 0) { 1619 return rc; 1620 } 1621 } else if (spapr->htab_first_pass) { 1622 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1623 } else { 1624 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1625 } 1626 1627 /* End marker */ 1628 qemu_put_be32(f, 0); 1629 qemu_put_be16(f, 0); 1630 qemu_put_be16(f, 0); 1631 1632 return rc; 1633 } 1634 1635 static int htab_save_complete(QEMUFile *f, void *opaque) 1636 { 1637 sPAPRMachineState *spapr = opaque; 1638 int fd; 1639 1640 /* Iteration header */ 1641 qemu_put_be32(f, 0); 1642 1643 if (!spapr->htab) { 1644 int rc; 1645 1646 assert(kvm_enabled()); 1647 1648 fd = get_htab_fd(spapr); 1649 if (fd < 0) { 1650 return fd; 1651 } 1652 1653 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 1654 if (rc < 0) { 1655 return rc; 1656 } 1657 } else { 1658 if (spapr->htab_first_pass) { 1659 htab_save_first_pass(f, spapr, -1); 1660 } 1661 htab_save_later_pass(f, spapr, -1); 1662 } 1663 1664 /* End marker */ 1665 qemu_put_be32(f, 0); 1666 qemu_put_be16(f, 0); 1667 qemu_put_be16(f, 0); 1668 1669 return 0; 1670 } 1671 1672 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1673 { 1674 sPAPRMachineState *spapr = opaque; 1675 uint32_t section_hdr; 1676 int fd = -1; 1677 1678 if (version_id < 1 || version_id > 1) { 1679 error_report("htab_load() bad version"); 1680 return -EINVAL; 1681 } 1682 1683 section_hdr = qemu_get_be32(f); 1684 1685 if (section_hdr) { 1686 Error *local_err = NULL; 1687 1688 /* First section gives the htab size */ 1689 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 1690 if (local_err) { 1691 error_report_err(local_err); 1692 return -EINVAL; 1693 } 1694 return 0; 1695 } 1696 1697 if (!spapr->htab) { 1698 assert(kvm_enabled()); 1699 1700 fd = kvmppc_get_htab_fd(true); 1701 if (fd < 0) { 1702 error_report("Unable to open fd to restore KVM hash table: %s", 1703 strerror(errno)); 1704 } 1705 } 1706 1707 while (true) { 1708 uint32_t index; 1709 uint16_t n_valid, n_invalid; 1710 1711 index = qemu_get_be32(f); 1712 n_valid = qemu_get_be16(f); 1713 n_invalid = qemu_get_be16(f); 1714 1715 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1716 /* End of Stream */ 1717 break; 1718 } 1719 1720 if ((index + n_valid + n_invalid) > 1721 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1722 /* Bad index in stream */ 1723 error_report( 1724 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 1725 index, n_valid, n_invalid, spapr->htab_shift); 1726 return -EINVAL; 1727 } 1728 1729 if (spapr->htab) { 1730 if (n_valid) { 1731 qemu_get_buffer(f, HPTE(spapr->htab, index), 1732 HASH_PTE_SIZE_64 * n_valid); 1733 } 1734 if (n_invalid) { 1735 memset(HPTE(spapr->htab, index + n_valid), 0, 1736 HASH_PTE_SIZE_64 * n_invalid); 1737 } 1738 } else { 1739 int rc; 1740 1741 assert(fd >= 0); 1742 1743 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1744 if (rc < 0) { 1745 return rc; 1746 } 1747 } 1748 } 1749 1750 if (!spapr->htab) { 1751 assert(fd >= 0); 1752 close(fd); 1753 } 1754 1755 return 0; 1756 } 1757 1758 static void htab_cleanup(void *opaque) 1759 { 1760 sPAPRMachineState *spapr = opaque; 1761 1762 close_htab_fd(spapr); 1763 } 1764 1765 static SaveVMHandlers savevm_htab_handlers = { 1766 .save_live_setup = htab_save_setup, 1767 .save_live_iterate = htab_save_iterate, 1768 .save_live_complete_precopy = htab_save_complete, 1769 .cleanup = htab_cleanup, 1770 .load_state = htab_load, 1771 }; 1772 1773 static void spapr_boot_set(void *opaque, const char *boot_device, 1774 Error **errp) 1775 { 1776 MachineState *machine = MACHINE(qdev_get_machine()); 1777 machine->boot_order = g_strdup(boot_device); 1778 } 1779 1780 /* 1781 * Reset routine for LMB DR devices. 1782 * 1783 * Unlike PCI DR devices, LMB DR devices explicitly register this reset 1784 * routine. Reset for PCI DR devices will be handled by PHB reset routine 1785 * when it walks all its children devices. LMB devices reset occurs 1786 * as part of spapr_ppc_reset(). 1787 */ 1788 static void spapr_drc_reset(void *opaque) 1789 { 1790 sPAPRDRConnector *drc = opaque; 1791 DeviceState *d = DEVICE(drc); 1792 1793 if (d) { 1794 device_reset(d); 1795 } 1796 } 1797 1798 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 1799 { 1800 MachineState *machine = MACHINE(spapr); 1801 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 1802 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 1803 int i; 1804 1805 for (i = 0; i < nr_lmbs; i++) { 1806 sPAPRDRConnector *drc; 1807 uint64_t addr; 1808 1809 addr = i * lmb_size + spapr->hotplug_memory.base; 1810 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB, 1811 addr/lmb_size); 1812 qemu_register_reset(spapr_drc_reset, drc); 1813 } 1814 } 1815 1816 /* 1817 * If RAM size, maxmem size and individual node mem sizes aren't aligned 1818 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 1819 * since we can't support such unaligned sizes with DRCONF_MEMORY. 1820 */ 1821 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 1822 { 1823 int i; 1824 1825 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1826 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 1827 " is not aligned to %llu MiB", 1828 machine->ram_size, 1829 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1830 return; 1831 } 1832 1833 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1834 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 1835 " is not aligned to %llu MiB", 1836 machine->ram_size, 1837 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1838 return; 1839 } 1840 1841 for (i = 0; i < nb_numa_nodes; i++) { 1842 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 1843 error_setg(errp, 1844 "Node %d memory size 0x%" PRIx64 1845 " is not aligned to %llu MiB", 1846 i, numa_info[i].node_mem, 1847 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1848 return; 1849 } 1850 } 1851 } 1852 1853 /* find cpu slot in machine->possible_cpus by core_id */ 1854 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 1855 { 1856 int index = id / smp_threads; 1857 1858 if (index >= ms->possible_cpus->len) { 1859 return NULL; 1860 } 1861 if (idx) { 1862 *idx = index; 1863 } 1864 return &ms->possible_cpus->cpus[index]; 1865 } 1866 1867 static void spapr_init_cpus(sPAPRMachineState *spapr) 1868 { 1869 MachineState *machine = MACHINE(spapr); 1870 MachineClass *mc = MACHINE_GET_CLASS(machine); 1871 char *type = spapr_get_cpu_core_type(machine->cpu_model); 1872 int smt = kvmppc_smt_threads(); 1873 const CPUArchIdList *possible_cpus; 1874 int boot_cores_nr = smp_cpus / smp_threads; 1875 int i; 1876 1877 if (!type) { 1878 error_report("Unable to find sPAPR CPU Core definition"); 1879 exit(1); 1880 } 1881 1882 possible_cpus = mc->possible_cpu_arch_ids(machine); 1883 if (mc->has_hotpluggable_cpus) { 1884 if (smp_cpus % smp_threads) { 1885 error_report("smp_cpus (%u) must be multiple of threads (%u)", 1886 smp_cpus, smp_threads); 1887 exit(1); 1888 } 1889 if (max_cpus % smp_threads) { 1890 error_report("max_cpus (%u) must be multiple of threads (%u)", 1891 max_cpus, smp_threads); 1892 exit(1); 1893 } 1894 } else { 1895 if (max_cpus != smp_cpus) { 1896 error_report("This machine version does not support CPU hotplug"); 1897 exit(1); 1898 } 1899 boot_cores_nr = possible_cpus->len; 1900 } 1901 1902 for (i = 0; i < possible_cpus->len; i++) { 1903 int core_id = i * smp_threads; 1904 1905 if (mc->has_hotpluggable_cpus) { 1906 sPAPRDRConnector *drc = 1907 spapr_dr_connector_new(OBJECT(spapr), 1908 SPAPR_DR_CONNECTOR_TYPE_CPU, 1909 (core_id / smp_threads) * smt); 1910 1911 qemu_register_reset(spapr_drc_reset, drc); 1912 } 1913 1914 if (i < boot_cores_nr) { 1915 Object *core = object_new(type); 1916 int nr_threads = smp_threads; 1917 1918 /* Handle the partially filled core for older machine types */ 1919 if ((i + 1) * smp_threads >= smp_cpus) { 1920 nr_threads = smp_cpus - i * smp_threads; 1921 } 1922 1923 object_property_set_int(core, nr_threads, "nr-threads", 1924 &error_fatal); 1925 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 1926 &error_fatal); 1927 object_property_set_bool(core, true, "realized", &error_fatal); 1928 } 1929 } 1930 g_free(type); 1931 } 1932 1933 /* pSeries LPAR / sPAPR hardware init */ 1934 static void ppc_spapr_init(MachineState *machine) 1935 { 1936 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1937 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1938 const char *kernel_filename = machine->kernel_filename; 1939 const char *initrd_filename = machine->initrd_filename; 1940 PCIHostState *phb; 1941 int i; 1942 MemoryRegion *sysmem = get_system_memory(); 1943 MemoryRegion *ram = g_new(MemoryRegion, 1); 1944 MemoryRegion *rma_region; 1945 void *rma = NULL; 1946 hwaddr rma_alloc_size; 1947 hwaddr node0_size = spapr_node0_size(); 1948 long load_limit, fw_size; 1949 char *filename; 1950 int smt = kvmppc_smt_threads(); 1951 1952 msi_nonbroken = true; 1953 1954 QLIST_INIT(&spapr->phbs); 1955 1956 /* Allocate RMA if necessary */ 1957 rma_alloc_size = kvmppc_alloc_rma(&rma); 1958 1959 if (rma_alloc_size == -1) { 1960 error_report("Unable to create RMA"); 1961 exit(1); 1962 } 1963 1964 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1965 spapr->rma_size = rma_alloc_size; 1966 } else { 1967 spapr->rma_size = node0_size; 1968 1969 /* With KVM, we don't actually know whether KVM supports an 1970 * unbounded RMA (PR KVM) or is limited by the hash table size 1971 * (HV KVM using VRMA), so we always assume the latter 1972 * 1973 * In that case, we also limit the initial allocations for RTAS 1974 * etc... to 256M since we have no way to know what the VRMA size 1975 * is going to be as it depends on the size of the hash table 1976 * isn't determined yet. 1977 */ 1978 if (kvm_enabled()) { 1979 spapr->vrma_adjust = 1; 1980 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1981 } 1982 1983 /* Actually we don't support unbounded RMA anymore since we 1984 * added proper emulation of HV mode. The max we can get is 1985 * 16G which also happens to be what we configure for PAPR 1986 * mode so make sure we don't do anything bigger than that 1987 */ 1988 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 1989 } 1990 1991 if (spapr->rma_size > node0_size) { 1992 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 1993 spapr->rma_size); 1994 exit(1); 1995 } 1996 1997 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 1998 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 1999 2000 /* Set up Interrupt Controller before we create the VCPUs */ 2001 xics_system_init(machine, DIV_ROUND_UP(max_cpus * smt, smp_threads), 2002 XICS_IRQS_SPAPR, &error_fatal); 2003 2004 /* Set up containers for ibm,client-set-architecture negotiated options */ 2005 spapr->ov5 = spapr_ovec_new(); 2006 spapr->ov5_cas = spapr_ovec_new(); 2007 2008 if (smc->dr_lmb_enabled) { 2009 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2010 spapr_validate_node_memory(machine, &error_fatal); 2011 } 2012 2013 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2014 2015 /* advertise support for dedicated HP event source to guests */ 2016 if (spapr->use_hotplug_event_source) { 2017 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2018 } 2019 2020 /* init CPUs */ 2021 if (machine->cpu_model == NULL) { 2022 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu; 2023 } 2024 2025 ppc_cpu_parse_features(machine->cpu_model); 2026 2027 spapr_init_cpus(spapr); 2028 2029 if (kvm_enabled()) { 2030 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2031 kvmppc_enable_logical_ci_hcalls(); 2032 kvmppc_enable_set_mode_hcall(); 2033 2034 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2035 kvmppc_enable_clear_ref_mod_hcalls(); 2036 } 2037 2038 /* allocate RAM */ 2039 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2040 machine->ram_size); 2041 memory_region_add_subregion(sysmem, 0, ram); 2042 2043 if (rma_alloc_size && rma) { 2044 rma_region = g_new(MemoryRegion, 1); 2045 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 2046 rma_alloc_size, rma); 2047 vmstate_register_ram_global(rma_region); 2048 memory_region_add_subregion(sysmem, 0, rma_region); 2049 } 2050 2051 /* initialize hotplug memory address space */ 2052 if (machine->ram_size < machine->maxram_size) { 2053 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 2054 /* 2055 * Limit the number of hotpluggable memory slots to half the number 2056 * slots that KVM supports, leaving the other half for PCI and other 2057 * devices. However ensure that number of slots doesn't drop below 32. 2058 */ 2059 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2060 SPAPR_MAX_RAM_SLOTS; 2061 2062 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2063 max_memslots = SPAPR_MAX_RAM_SLOTS; 2064 } 2065 if (machine->ram_slots > max_memslots) { 2066 error_report("Specified number of memory slots %" 2067 PRIu64" exceeds max supported %d", 2068 machine->ram_slots, max_memslots); 2069 exit(1); 2070 } 2071 2072 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 2073 SPAPR_HOTPLUG_MEM_ALIGN); 2074 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 2075 "hotplug-memory", hotplug_mem_size); 2076 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 2077 &spapr->hotplug_memory.mr); 2078 } 2079 2080 if (smc->dr_lmb_enabled) { 2081 spapr_create_lmb_dr_connectors(spapr); 2082 } 2083 2084 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2085 if (!filename) { 2086 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2087 exit(1); 2088 } 2089 spapr->rtas_size = get_image_size(filename); 2090 if (spapr->rtas_size < 0) { 2091 error_report("Could not get size of LPAR rtas '%s'", filename); 2092 exit(1); 2093 } 2094 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2095 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2096 error_report("Could not load LPAR rtas '%s'", filename); 2097 exit(1); 2098 } 2099 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2100 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2101 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2102 exit(1); 2103 } 2104 g_free(filename); 2105 2106 /* Set up RTAS event infrastructure */ 2107 spapr_events_init(spapr); 2108 2109 /* Set up the RTC RTAS interfaces */ 2110 spapr_rtc_create(spapr); 2111 2112 /* Set up VIO bus */ 2113 spapr->vio_bus = spapr_vio_bus_init(); 2114 2115 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 2116 if (serial_hds[i]) { 2117 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 2118 } 2119 } 2120 2121 /* We always have at least the nvram device on VIO */ 2122 spapr_create_nvram(spapr); 2123 2124 /* Set up PCI */ 2125 spapr_pci_rtas_init(); 2126 2127 phb = spapr_create_phb(spapr, 0); 2128 2129 for (i = 0; i < nb_nics; i++) { 2130 NICInfo *nd = &nd_table[i]; 2131 2132 if (!nd->model) { 2133 nd->model = g_strdup("ibmveth"); 2134 } 2135 2136 if (strcmp(nd->model, "ibmveth") == 0) { 2137 spapr_vlan_create(spapr->vio_bus, nd); 2138 } else { 2139 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2140 } 2141 } 2142 2143 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2144 spapr_vscsi_create(spapr->vio_bus); 2145 } 2146 2147 /* Graphics */ 2148 if (spapr_vga_init(phb->bus, &error_fatal)) { 2149 spapr->has_graphics = true; 2150 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2151 } 2152 2153 if (machine->usb) { 2154 if (smc->use_ohci_by_default) { 2155 pci_create_simple(phb->bus, -1, "pci-ohci"); 2156 } else { 2157 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2158 } 2159 2160 if (spapr->has_graphics) { 2161 USBBus *usb_bus = usb_bus_find(-1); 2162 2163 usb_create_simple(usb_bus, "usb-kbd"); 2164 usb_create_simple(usb_bus, "usb-mouse"); 2165 } 2166 } 2167 2168 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 2169 error_report( 2170 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2171 MIN_RMA_SLOF); 2172 exit(1); 2173 } 2174 2175 if (kernel_filename) { 2176 uint64_t lowaddr = 0; 2177 2178 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2179 NULL, NULL, &lowaddr, NULL, 1, 2180 PPC_ELF_MACHINE, 0, 0); 2181 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2182 spapr->kernel_size = load_elf(kernel_filename, 2183 translate_kernel_address, NULL, NULL, 2184 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2185 0, 0); 2186 spapr->kernel_le = spapr->kernel_size > 0; 2187 } 2188 if (spapr->kernel_size < 0) { 2189 error_report("error loading %s: %s", kernel_filename, 2190 load_elf_strerror(spapr->kernel_size)); 2191 exit(1); 2192 } 2193 2194 /* load initrd */ 2195 if (initrd_filename) { 2196 /* Try to locate the initrd in the gap between the kernel 2197 * and the firmware. Add a bit of space just in case 2198 */ 2199 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2200 + 0x1ffff) & ~0xffff; 2201 spapr->initrd_size = load_image_targphys(initrd_filename, 2202 spapr->initrd_base, 2203 load_limit 2204 - spapr->initrd_base); 2205 if (spapr->initrd_size < 0) { 2206 error_report("could not load initial ram disk '%s'", 2207 initrd_filename); 2208 exit(1); 2209 } 2210 } 2211 } 2212 2213 if (bios_name == NULL) { 2214 bios_name = FW_FILE_NAME; 2215 } 2216 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2217 if (!filename) { 2218 error_report("Could not find LPAR firmware '%s'", bios_name); 2219 exit(1); 2220 } 2221 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2222 if (fw_size <= 0) { 2223 error_report("Could not load LPAR firmware '%s'", filename); 2224 exit(1); 2225 } 2226 g_free(filename); 2227 2228 /* FIXME: Should register things through the MachineState's qdev 2229 * interface, this is a legacy from the sPAPREnvironment structure 2230 * which predated MachineState but had a similar function */ 2231 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2232 register_savevm_live(NULL, "spapr/htab", -1, 1, 2233 &savevm_htab_handlers, spapr); 2234 2235 /* used by RTAS */ 2236 QTAILQ_INIT(&spapr->ccs_list); 2237 qemu_register_reset(spapr_ccs_reset_hook, spapr); 2238 2239 qemu_register_boot_set(spapr_boot_set, spapr); 2240 2241 /* to stop and start vmclock */ 2242 if (kvm_enabled()) { 2243 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2244 &spapr->tb); 2245 } 2246 } 2247 2248 static int spapr_kvm_type(const char *vm_type) 2249 { 2250 if (!vm_type) { 2251 return 0; 2252 } 2253 2254 if (!strcmp(vm_type, "HV")) { 2255 return 1; 2256 } 2257 2258 if (!strcmp(vm_type, "PR")) { 2259 return 2; 2260 } 2261 2262 error_report("Unknown kvm-type specified '%s'", vm_type); 2263 exit(1); 2264 } 2265 2266 /* 2267 * Implementation of an interface to adjust firmware path 2268 * for the bootindex property handling. 2269 */ 2270 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2271 DeviceState *dev) 2272 { 2273 #define CAST(type, obj, name) \ 2274 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2275 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2276 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2277 2278 if (d) { 2279 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2280 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2281 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2282 2283 if (spapr) { 2284 /* 2285 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2286 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2287 * in the top 16 bits of the 64-bit LUN 2288 */ 2289 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2290 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2291 (uint64_t)id << 48); 2292 } else if (virtio) { 2293 /* 2294 * We use SRP luns of the form 01000000 | (target << 8) | lun 2295 * in the top 32 bits of the 64-bit LUN 2296 * Note: the quote above is from SLOF and it is wrong, 2297 * the actual binding is: 2298 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2299 */ 2300 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2301 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2302 (uint64_t)id << 32); 2303 } else if (usb) { 2304 /* 2305 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2306 * in the top 32 bits of the 64-bit LUN 2307 */ 2308 unsigned usb_port = atoi(usb->port->path); 2309 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2310 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2311 (uint64_t)id << 32); 2312 } 2313 } 2314 2315 /* 2316 * SLOF probes the USB devices, and if it recognizes that the device is a 2317 * storage device, it changes its name to "storage" instead of "usb-host", 2318 * and additionally adds a child node for the SCSI LUN, so the correct 2319 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2320 */ 2321 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2322 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2323 if (usb_host_dev_is_scsi_storage(usbdev)) { 2324 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2325 } 2326 } 2327 2328 if (phb) { 2329 /* Replace "pci" with "pci@800000020000000" */ 2330 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2331 } 2332 2333 return NULL; 2334 } 2335 2336 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2337 { 2338 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2339 2340 return g_strdup(spapr->kvm_type); 2341 } 2342 2343 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2344 { 2345 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2346 2347 g_free(spapr->kvm_type); 2348 spapr->kvm_type = g_strdup(value); 2349 } 2350 2351 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2352 { 2353 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2354 2355 return spapr->use_hotplug_event_source; 2356 } 2357 2358 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2359 Error **errp) 2360 { 2361 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2362 2363 spapr->use_hotplug_event_source = value; 2364 } 2365 2366 static void spapr_machine_initfn(Object *obj) 2367 { 2368 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2369 2370 spapr->htab_fd = -1; 2371 spapr->use_hotplug_event_source = true; 2372 object_property_add_str(obj, "kvm-type", 2373 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2374 object_property_set_description(obj, "kvm-type", 2375 "Specifies the KVM virtualization mode (HV, PR)", 2376 NULL); 2377 object_property_add_bool(obj, "modern-hotplug-events", 2378 spapr_get_modern_hotplug_events, 2379 spapr_set_modern_hotplug_events, 2380 NULL); 2381 object_property_set_description(obj, "modern-hotplug-events", 2382 "Use dedicated hotplug event mechanism in" 2383 " place of standard EPOW events when possible" 2384 " (required for memory hot-unplug support)", 2385 NULL); 2386 } 2387 2388 static void spapr_machine_finalizefn(Object *obj) 2389 { 2390 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2391 2392 g_free(spapr->kvm_type); 2393 } 2394 2395 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 2396 { 2397 cpu_synchronize_state(cs); 2398 ppc_cpu_do_system_reset(cs); 2399 } 2400 2401 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2402 { 2403 CPUState *cs; 2404 2405 CPU_FOREACH(cs) { 2406 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 2407 } 2408 } 2409 2410 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2411 uint32_t node, bool dedicated_hp_event_source, 2412 Error **errp) 2413 { 2414 sPAPRDRConnector *drc; 2415 sPAPRDRConnectorClass *drck; 2416 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2417 int i, fdt_offset, fdt_size; 2418 void *fdt; 2419 uint64_t addr = addr_start; 2420 2421 for (i = 0; i < nr_lmbs; i++) { 2422 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2423 addr/SPAPR_MEMORY_BLOCK_SIZE); 2424 g_assert(drc); 2425 2426 fdt = create_device_tree(&fdt_size); 2427 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2428 SPAPR_MEMORY_BLOCK_SIZE); 2429 2430 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2431 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); 2432 addr += SPAPR_MEMORY_BLOCK_SIZE; 2433 if (!dev->hotplugged) { 2434 /* guests expect coldplugged LMBs to be pre-allocated */ 2435 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); 2436 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); 2437 } 2438 } 2439 /* send hotplug notification to the 2440 * guest only in case of hotplugged memory 2441 */ 2442 if (dev->hotplugged) { 2443 if (dedicated_hp_event_source) { 2444 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2445 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2446 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2447 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2448 nr_lmbs, 2449 drck->get_index(drc)); 2450 } else { 2451 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 2452 nr_lmbs); 2453 } 2454 } 2455 } 2456 2457 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2458 uint32_t node, Error **errp) 2459 { 2460 Error *local_err = NULL; 2461 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2462 PCDIMMDevice *dimm = PC_DIMM(dev); 2463 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2464 MemoryRegion *mr = ddc->get_memory_region(dimm); 2465 uint64_t align = memory_region_get_alignment(mr); 2466 uint64_t size = memory_region_size(mr); 2467 uint64_t addr; 2468 char *mem_dev; 2469 2470 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 2471 error_setg(&local_err, "Hotplugged memory size must be a multiple of " 2472 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); 2473 goto out; 2474 } 2475 2476 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); 2477 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { 2478 error_setg(&local_err, "Memory backend has bad page size. " 2479 "Use 'memory-backend-file' with correct mem-path."); 2480 goto out; 2481 } 2482 2483 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 2484 if (local_err) { 2485 goto out; 2486 } 2487 2488 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2489 if (local_err) { 2490 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2491 goto out; 2492 } 2493 2494 spapr_add_lmbs(dev, addr, size, node, 2495 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 2496 &error_abort); 2497 2498 out: 2499 error_propagate(errp, local_err); 2500 } 2501 2502 typedef struct sPAPRDIMMState { 2503 uint32_t nr_lmbs; 2504 } sPAPRDIMMState; 2505 2506 static void spapr_lmb_release(DeviceState *dev, void *opaque) 2507 { 2508 sPAPRDIMMState *ds = (sPAPRDIMMState *)opaque; 2509 HotplugHandler *hotplug_ctrl; 2510 2511 if (--ds->nr_lmbs) { 2512 return; 2513 } 2514 2515 g_free(ds); 2516 2517 /* 2518 * Now that all the LMBs have been removed by the guest, call the 2519 * pc-dimm unplug handler to cleanup up the pc-dimm device. 2520 */ 2521 hotplug_ctrl = qdev_get_hotplug_handler(dev); 2522 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2523 } 2524 2525 static void spapr_del_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2526 Error **errp) 2527 { 2528 sPAPRDRConnector *drc; 2529 sPAPRDRConnectorClass *drck; 2530 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 2531 int i; 2532 sPAPRDIMMState *ds = g_malloc0(sizeof(sPAPRDIMMState)); 2533 uint64_t addr = addr_start; 2534 2535 ds->nr_lmbs = nr_lmbs; 2536 for (i = 0; i < nr_lmbs; i++) { 2537 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2538 addr / SPAPR_MEMORY_BLOCK_SIZE); 2539 g_assert(drc); 2540 2541 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2542 drck->detach(drc, dev, spapr_lmb_release, ds, errp); 2543 addr += SPAPR_MEMORY_BLOCK_SIZE; 2544 } 2545 2546 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2547 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2548 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2549 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2550 nr_lmbs, 2551 drck->get_index(drc)); 2552 } 2553 2554 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2555 Error **errp) 2556 { 2557 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2558 PCDIMMDevice *dimm = PC_DIMM(dev); 2559 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2560 MemoryRegion *mr = ddc->get_memory_region(dimm); 2561 2562 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2563 object_unparent(OBJECT(dev)); 2564 } 2565 2566 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 2567 DeviceState *dev, Error **errp) 2568 { 2569 Error *local_err = NULL; 2570 PCDIMMDevice *dimm = PC_DIMM(dev); 2571 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2572 MemoryRegion *mr = ddc->get_memory_region(dimm); 2573 uint64_t size = memory_region_size(mr); 2574 uint64_t addr; 2575 2576 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2577 if (local_err) { 2578 goto out; 2579 } 2580 2581 spapr_del_lmbs(dev, addr, size, &error_abort); 2582 out: 2583 error_propagate(errp, local_err); 2584 } 2585 2586 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 2587 sPAPRMachineState *spapr) 2588 { 2589 PowerPCCPU *cpu = POWERPC_CPU(cs); 2590 DeviceClass *dc = DEVICE_GET_CLASS(cs); 2591 int id = ppc_get_vcpu_dt_id(cpu); 2592 void *fdt; 2593 int offset, fdt_size; 2594 char *nodename; 2595 2596 fdt = create_device_tree(&fdt_size); 2597 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 2598 offset = fdt_add_subnode(fdt, 0, nodename); 2599 2600 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 2601 g_free(nodename); 2602 2603 *fdt_offset = offset; 2604 return fdt; 2605 } 2606 2607 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2608 Error **errp) 2609 { 2610 MachineState *ms = MACHINE(qdev_get_machine()); 2611 CPUCore *cc = CPU_CORE(dev); 2612 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 2613 2614 core_slot->cpu = NULL; 2615 object_unparent(OBJECT(dev)); 2616 } 2617 2618 static void spapr_core_release(DeviceState *dev, void *opaque) 2619 { 2620 HotplugHandler *hotplug_ctrl; 2621 2622 hotplug_ctrl = qdev_get_hotplug_handler(dev); 2623 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2624 } 2625 2626 static 2627 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 2628 Error **errp) 2629 { 2630 int index; 2631 sPAPRDRConnector *drc; 2632 sPAPRDRConnectorClass *drck; 2633 Error *local_err = NULL; 2634 CPUCore *cc = CPU_CORE(dev); 2635 int smt = kvmppc_smt_threads(); 2636 2637 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 2638 error_setg(errp, "Unable to find CPU core with core-id: %d", 2639 cc->core_id); 2640 return; 2641 } 2642 if (index == 0) { 2643 error_setg(errp, "Boot CPU core may not be unplugged"); 2644 return; 2645 } 2646 2647 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt); 2648 g_assert(drc); 2649 2650 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2651 drck->detach(drc, dev, spapr_core_release, NULL, &local_err); 2652 if (local_err) { 2653 error_propagate(errp, local_err); 2654 return; 2655 } 2656 2657 spapr_hotplug_req_remove_by_index(drc); 2658 } 2659 2660 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2661 Error **errp) 2662 { 2663 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 2664 MachineClass *mc = MACHINE_GET_CLASS(spapr); 2665 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 2666 CPUCore *cc = CPU_CORE(dev); 2667 CPUState *cs = CPU(core->threads); 2668 sPAPRDRConnector *drc; 2669 Error *local_err = NULL; 2670 void *fdt = NULL; 2671 int fdt_offset = 0; 2672 int smt = kvmppc_smt_threads(); 2673 CPUArchId *core_slot; 2674 int index; 2675 2676 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 2677 if (!core_slot) { 2678 error_setg(errp, "Unable to find CPU core with core-id: %d", 2679 cc->core_id); 2680 return; 2681 } 2682 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt); 2683 2684 g_assert(drc || !mc->has_hotpluggable_cpus); 2685 2686 /* 2687 * Setup CPU DT entries only for hotplugged CPUs. For boot time or 2688 * coldplugged CPUs DT entries are setup in spapr_build_fdt(). 2689 */ 2690 if (dev->hotplugged) { 2691 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 2692 } 2693 2694 if (drc) { 2695 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2696 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err); 2697 if (local_err) { 2698 g_free(fdt); 2699 error_propagate(errp, local_err); 2700 return; 2701 } 2702 } 2703 2704 if (dev->hotplugged) { 2705 /* 2706 * Send hotplug notification interrupt to the guest only in case 2707 * of hotplugged CPUs. 2708 */ 2709 spapr_hotplug_req_add_by_index(drc); 2710 } else { 2711 /* 2712 * Set the right DRC states for cold plugged CPU. 2713 */ 2714 if (drc) { 2715 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2716 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); 2717 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); 2718 } 2719 } 2720 core_slot->cpu = OBJECT(dev); 2721 } 2722 2723 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2724 Error **errp) 2725 { 2726 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 2727 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 2728 Error *local_err = NULL; 2729 CPUCore *cc = CPU_CORE(dev); 2730 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model); 2731 const char *type = object_get_typename(OBJECT(dev)); 2732 CPUArchId *core_slot; 2733 int index; 2734 2735 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 2736 error_setg(&local_err, "CPU hotplug not supported for this machine"); 2737 goto out; 2738 } 2739 2740 if (strcmp(base_core_type, type)) { 2741 error_setg(&local_err, "CPU core type should be %s", base_core_type); 2742 goto out; 2743 } 2744 2745 if (cc->core_id % smp_threads) { 2746 error_setg(&local_err, "invalid core id %d", cc->core_id); 2747 goto out; 2748 } 2749 2750 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 2751 if (!core_slot) { 2752 error_setg(&local_err, "core id %d out of range", cc->core_id); 2753 goto out; 2754 } 2755 2756 if (core_slot->cpu) { 2757 error_setg(&local_err, "core %d already populated", cc->core_id); 2758 goto out; 2759 } 2760 2761 out: 2762 g_free(base_core_type); 2763 error_propagate(errp, local_err); 2764 } 2765 2766 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 2767 DeviceState *dev, Error **errp) 2768 { 2769 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 2770 2771 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2772 int node; 2773 2774 if (!smc->dr_lmb_enabled) { 2775 error_setg(errp, "Memory hotplug not supported for this machine"); 2776 return; 2777 } 2778 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 2779 if (*errp) { 2780 return; 2781 } 2782 if (node < 0 || node >= MAX_NODES) { 2783 error_setg(errp, "Invaild node %d", node); 2784 return; 2785 } 2786 2787 /* 2788 * Currently PowerPC kernel doesn't allow hot-adding memory to 2789 * memory-less node, but instead will silently add the memory 2790 * to the first node that has some memory. This causes two 2791 * unexpected behaviours for the user. 2792 * 2793 * - Memory gets hotplugged to a different node than what the user 2794 * specified. 2795 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 2796 * to memory-less node, a reboot will set things accordingly 2797 * and the previously hotplugged memory now ends in the right node. 2798 * This appears as if some memory moved from one node to another. 2799 * 2800 * So until kernel starts supporting memory hotplug to memory-less 2801 * nodes, just prevent such attempts upfront in QEMU. 2802 */ 2803 if (nb_numa_nodes && !numa_info[node].node_mem) { 2804 error_setg(errp, "Can't hotplug memory to memory-less node %d", 2805 node); 2806 return; 2807 } 2808 2809 spapr_memory_plug(hotplug_dev, dev, node, errp); 2810 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2811 spapr_core_plug(hotplug_dev, dev, errp); 2812 } 2813 } 2814 2815 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 2816 DeviceState *dev, Error **errp) 2817 { 2818 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 2819 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 2820 2821 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2822 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 2823 spapr_memory_unplug(hotplug_dev, dev, errp); 2824 } else { 2825 error_setg(errp, "Memory hot unplug not supported for this guest"); 2826 } 2827 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2828 if (!mc->has_hotpluggable_cpus) { 2829 error_setg(errp, "CPU hot unplug not supported on this machine"); 2830 return; 2831 } 2832 spapr_core_unplug(hotplug_dev, dev, errp); 2833 } 2834 } 2835 2836 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 2837 DeviceState *dev, Error **errp) 2838 { 2839 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 2840 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 2841 2842 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2843 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 2844 spapr_memory_unplug_request(hotplug_dev, dev, errp); 2845 } else { 2846 /* NOTE: this means there is a window after guest reset, prior to 2847 * CAS negotiation, where unplug requests will fail due to the 2848 * capability not being detected yet. This is a bit different than 2849 * the case with PCI unplug, where the events will be queued and 2850 * eventually handled by the guest after boot 2851 */ 2852 error_setg(errp, "Memory hot unplug not supported for this guest"); 2853 } 2854 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2855 if (!mc->has_hotpluggable_cpus) { 2856 error_setg(errp, "CPU hot unplug not supported on this machine"); 2857 return; 2858 } 2859 spapr_core_unplug_request(hotplug_dev, dev, errp); 2860 } 2861 } 2862 2863 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 2864 DeviceState *dev, Error **errp) 2865 { 2866 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2867 spapr_core_pre_plug(hotplug_dev, dev, errp); 2868 } 2869 } 2870 2871 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 2872 DeviceState *dev) 2873 { 2874 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2875 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2876 return HOTPLUG_HANDLER(machine); 2877 } 2878 return NULL; 2879 } 2880 2881 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index) 2882 { 2883 /* Allocate to NUMA nodes on a "socket" basis (not that concept of 2884 * socket means much for the paravirtualized PAPR platform) */ 2885 return cpu_index / smp_threads / smp_cores; 2886 } 2887 2888 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 2889 { 2890 int i; 2891 int spapr_max_cores = max_cpus / smp_threads; 2892 MachineClass *mc = MACHINE_GET_CLASS(machine); 2893 2894 if (!mc->has_hotpluggable_cpus) { 2895 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 2896 } 2897 if (machine->possible_cpus) { 2898 assert(machine->possible_cpus->len == spapr_max_cores); 2899 return machine->possible_cpus; 2900 } 2901 2902 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2903 sizeof(CPUArchId) * spapr_max_cores); 2904 machine->possible_cpus->len = spapr_max_cores; 2905 for (i = 0; i < machine->possible_cpus->len; i++) { 2906 int core_id = i * smp_threads; 2907 2908 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 2909 machine->possible_cpus->cpus[i].arch_id = core_id; 2910 machine->possible_cpus->cpus[i].props.has_core_id = true; 2911 machine->possible_cpus->cpus[i].props.core_id = core_id; 2912 /* TODO: add 'has_node/node' here to describe 2913 to which node core belongs */ 2914 } 2915 return machine->possible_cpus; 2916 } 2917 2918 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 2919 uint64_t *buid, hwaddr *pio, 2920 hwaddr *mmio32, hwaddr *mmio64, 2921 unsigned n_dma, uint32_t *liobns, Error **errp) 2922 { 2923 /* 2924 * New-style PHB window placement. 2925 * 2926 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 2927 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 2928 * windows. 2929 * 2930 * Some guest kernels can't work with MMIO windows above 1<<46 2931 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 2932 * 2933 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 2934 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 2935 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 2936 * 1TiB 64-bit MMIO windows for each PHB. 2937 */ 2938 const uint64_t base_buid = 0x800000020000000ULL; 2939 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 2940 SPAPR_PCI_MEM64_WIN_SIZE - 1) 2941 int i; 2942 2943 /* Sanity check natural alignments */ 2944 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 2945 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 2946 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 2947 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 2948 /* Sanity check bounds */ 2949 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 2950 SPAPR_PCI_MEM32_WIN_SIZE); 2951 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 2952 SPAPR_PCI_MEM64_WIN_SIZE); 2953 2954 if (index >= SPAPR_MAX_PHBS) { 2955 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 2956 SPAPR_MAX_PHBS - 1); 2957 return; 2958 } 2959 2960 *buid = base_buid + index; 2961 for (i = 0; i < n_dma; ++i) { 2962 liobns[i] = SPAPR_PCI_LIOBN(index, i); 2963 } 2964 2965 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 2966 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 2967 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 2968 } 2969 2970 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 2971 { 2972 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 2973 2974 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 2975 } 2976 2977 static void spapr_ics_resend(XICSFabric *dev) 2978 { 2979 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 2980 2981 ics_resend(spapr->ics); 2982 } 2983 2984 static ICPState *spapr_icp_get(XICSFabric *xi, int server) 2985 { 2986 sPAPRMachineState *spapr = SPAPR_MACHINE(xi); 2987 2988 return (server < spapr->nr_servers) ? &spapr->icps[server] : NULL; 2989 } 2990 2991 static void spapr_machine_class_init(ObjectClass *oc, void *data) 2992 { 2993 MachineClass *mc = MACHINE_CLASS(oc); 2994 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 2995 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 2996 NMIClass *nc = NMI_CLASS(oc); 2997 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2998 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 2999 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3000 3001 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3002 3003 /* 3004 * We set up the default / latest behaviour here. The class_init 3005 * functions for the specific versioned machine types can override 3006 * these details for backwards compatibility 3007 */ 3008 mc->init = ppc_spapr_init; 3009 mc->reset = ppc_spapr_reset; 3010 mc->block_default_type = IF_SCSI; 3011 mc->max_cpus = 1024; 3012 mc->no_parallel = 1; 3013 mc->default_boot_order = ""; 3014 mc->default_ram_size = 512 * M_BYTE; 3015 mc->kvm_type = spapr_kvm_type; 3016 mc->has_dynamic_sysbus = true; 3017 mc->pci_allow_0_address = true; 3018 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3019 hc->pre_plug = spapr_machine_device_pre_plug; 3020 hc->plug = spapr_machine_device_plug; 3021 hc->unplug = spapr_machine_device_unplug; 3022 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id; 3023 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3024 hc->unplug_request = spapr_machine_device_unplug_request; 3025 3026 smc->dr_lmb_enabled = true; 3027 smc->tcg_default_cpu = "POWER8"; 3028 mc->has_hotpluggable_cpus = true; 3029 fwc->get_dev_path = spapr_get_fw_dev_path; 3030 nc->nmi_monitor_handler = spapr_nmi; 3031 smc->phb_placement = spapr_phb_placement; 3032 vhc->hypercall = emulate_spapr_hypercall; 3033 vhc->hpt_mask = spapr_hpt_mask; 3034 vhc->map_hptes = spapr_map_hptes; 3035 vhc->unmap_hptes = spapr_unmap_hptes; 3036 vhc->store_hpte = spapr_store_hpte; 3037 xic->ics_get = spapr_ics_get; 3038 xic->ics_resend = spapr_ics_resend; 3039 xic->icp_get = spapr_icp_get; 3040 } 3041 3042 static const TypeInfo spapr_machine_info = { 3043 .name = TYPE_SPAPR_MACHINE, 3044 .parent = TYPE_MACHINE, 3045 .abstract = true, 3046 .instance_size = sizeof(sPAPRMachineState), 3047 .instance_init = spapr_machine_initfn, 3048 .instance_finalize = spapr_machine_finalizefn, 3049 .class_size = sizeof(sPAPRMachineClass), 3050 .class_init = spapr_machine_class_init, 3051 .interfaces = (InterfaceInfo[]) { 3052 { TYPE_FW_PATH_PROVIDER }, 3053 { TYPE_NMI }, 3054 { TYPE_HOTPLUG_HANDLER }, 3055 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 3056 { TYPE_XICS_FABRIC }, 3057 { } 3058 }, 3059 }; 3060 3061 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 3062 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 3063 void *data) \ 3064 { \ 3065 MachineClass *mc = MACHINE_CLASS(oc); \ 3066 spapr_machine_##suffix##_class_options(mc); \ 3067 if (latest) { \ 3068 mc->alias = "pseries"; \ 3069 mc->is_default = 1; \ 3070 } \ 3071 } \ 3072 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 3073 { \ 3074 MachineState *machine = MACHINE(obj); \ 3075 spapr_machine_##suffix##_instance_options(machine); \ 3076 } \ 3077 static const TypeInfo spapr_machine_##suffix##_info = { \ 3078 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 3079 .parent = TYPE_SPAPR_MACHINE, \ 3080 .class_init = spapr_machine_##suffix##_class_init, \ 3081 .instance_init = spapr_machine_##suffix##_instance_init, \ 3082 }; \ 3083 static void spapr_machine_register_##suffix(void) \ 3084 { \ 3085 type_register(&spapr_machine_##suffix##_info); \ 3086 } \ 3087 type_init(spapr_machine_register_##suffix) 3088 3089 /* 3090 * pseries-2.9 3091 */ 3092 static void spapr_machine_2_9_instance_options(MachineState *machine) 3093 { 3094 } 3095 3096 static void spapr_machine_2_9_class_options(MachineClass *mc) 3097 { 3098 /* Defaults for the latest behaviour inherited from the base class */ 3099 } 3100 3101 DEFINE_SPAPR_MACHINE(2_9, "2.9", true); 3102 3103 /* 3104 * pseries-2.8 3105 */ 3106 #define SPAPR_COMPAT_2_8 \ 3107 HW_COMPAT_2_8 3108 3109 static void spapr_machine_2_8_instance_options(MachineState *machine) 3110 { 3111 spapr_machine_2_9_instance_options(machine); 3112 } 3113 3114 static void spapr_machine_2_8_class_options(MachineClass *mc) 3115 { 3116 spapr_machine_2_9_class_options(mc); 3117 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 3118 } 3119 3120 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 3121 3122 /* 3123 * pseries-2.7 3124 */ 3125 #define SPAPR_COMPAT_2_7 \ 3126 HW_COMPAT_2_7 \ 3127 { \ 3128 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3129 .property = "mem_win_size", \ 3130 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 3131 }, \ 3132 { \ 3133 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3134 .property = "mem64_win_size", \ 3135 .value = "0", \ 3136 }, \ 3137 { \ 3138 .driver = TYPE_POWERPC_CPU, \ 3139 .property = "pre-2.8-migration", \ 3140 .value = "on", \ 3141 }, \ 3142 { \ 3143 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3144 .property = "pre-2.8-migration", \ 3145 .value = "on", \ 3146 }, 3147 3148 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 3149 uint64_t *buid, hwaddr *pio, 3150 hwaddr *mmio32, hwaddr *mmio64, 3151 unsigned n_dma, uint32_t *liobns, Error **errp) 3152 { 3153 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 3154 const uint64_t base_buid = 0x800000020000000ULL; 3155 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 3156 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 3157 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 3158 const uint32_t max_index = 255; 3159 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 3160 3161 uint64_t ram_top = MACHINE(spapr)->ram_size; 3162 hwaddr phb0_base, phb_base; 3163 int i; 3164 3165 /* Do we have hotpluggable memory? */ 3166 if (MACHINE(spapr)->maxram_size > ram_top) { 3167 /* Can't just use maxram_size, because there may be an 3168 * alignment gap between normal and hotpluggable memory 3169 * regions */ 3170 ram_top = spapr->hotplug_memory.base + 3171 memory_region_size(&spapr->hotplug_memory.mr); 3172 } 3173 3174 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 3175 3176 if (index > max_index) { 3177 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 3178 max_index); 3179 return; 3180 } 3181 3182 *buid = base_buid + index; 3183 for (i = 0; i < n_dma; ++i) { 3184 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3185 } 3186 3187 phb_base = phb0_base + index * phb_spacing; 3188 *pio = phb_base + pio_offset; 3189 *mmio32 = phb_base + mmio_offset; 3190 /* 3191 * We don't set the 64-bit MMIO window, relying on the PHB's 3192 * fallback behaviour of automatically splitting a large "32-bit" 3193 * window into contiguous 32-bit and 64-bit windows 3194 */ 3195 } 3196 3197 static void spapr_machine_2_7_instance_options(MachineState *machine) 3198 { 3199 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 3200 3201 spapr_machine_2_8_instance_options(machine); 3202 spapr->use_hotplug_event_source = false; 3203 } 3204 3205 static void spapr_machine_2_7_class_options(MachineClass *mc) 3206 { 3207 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3208 3209 spapr_machine_2_8_class_options(mc); 3210 smc->tcg_default_cpu = "POWER7"; 3211 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 3212 smc->phb_placement = phb_placement_2_7; 3213 } 3214 3215 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 3216 3217 /* 3218 * pseries-2.6 3219 */ 3220 #define SPAPR_COMPAT_2_6 \ 3221 HW_COMPAT_2_6 \ 3222 { \ 3223 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3224 .property = "ddw",\ 3225 .value = stringify(off),\ 3226 }, 3227 3228 static void spapr_machine_2_6_instance_options(MachineState *machine) 3229 { 3230 spapr_machine_2_7_instance_options(machine); 3231 } 3232 3233 static void spapr_machine_2_6_class_options(MachineClass *mc) 3234 { 3235 spapr_machine_2_7_class_options(mc); 3236 mc->has_hotpluggable_cpus = false; 3237 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 3238 } 3239 3240 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 3241 3242 /* 3243 * pseries-2.5 3244 */ 3245 #define SPAPR_COMPAT_2_5 \ 3246 HW_COMPAT_2_5 \ 3247 { \ 3248 .driver = "spapr-vlan", \ 3249 .property = "use-rx-buffer-pools", \ 3250 .value = "off", \ 3251 }, 3252 3253 static void spapr_machine_2_5_instance_options(MachineState *machine) 3254 { 3255 spapr_machine_2_6_instance_options(machine); 3256 } 3257 3258 static void spapr_machine_2_5_class_options(MachineClass *mc) 3259 { 3260 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3261 3262 spapr_machine_2_6_class_options(mc); 3263 smc->use_ohci_by_default = true; 3264 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 3265 } 3266 3267 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 3268 3269 /* 3270 * pseries-2.4 3271 */ 3272 #define SPAPR_COMPAT_2_4 \ 3273 HW_COMPAT_2_4 3274 3275 static void spapr_machine_2_4_instance_options(MachineState *machine) 3276 { 3277 spapr_machine_2_5_instance_options(machine); 3278 } 3279 3280 static void spapr_machine_2_4_class_options(MachineClass *mc) 3281 { 3282 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3283 3284 spapr_machine_2_5_class_options(mc); 3285 smc->dr_lmb_enabled = false; 3286 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 3287 } 3288 3289 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 3290 3291 /* 3292 * pseries-2.3 3293 */ 3294 #define SPAPR_COMPAT_2_3 \ 3295 HW_COMPAT_2_3 \ 3296 {\ 3297 .driver = "spapr-pci-host-bridge",\ 3298 .property = "dynamic-reconfiguration",\ 3299 .value = "off",\ 3300 }, 3301 3302 static void spapr_machine_2_3_instance_options(MachineState *machine) 3303 { 3304 spapr_machine_2_4_instance_options(machine); 3305 savevm_skip_section_footers(); 3306 global_state_set_optional(); 3307 savevm_skip_configuration(); 3308 } 3309 3310 static void spapr_machine_2_3_class_options(MachineClass *mc) 3311 { 3312 spapr_machine_2_4_class_options(mc); 3313 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 3314 } 3315 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 3316 3317 /* 3318 * pseries-2.2 3319 */ 3320 3321 #define SPAPR_COMPAT_2_2 \ 3322 HW_COMPAT_2_2 \ 3323 {\ 3324 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3325 .property = "mem_win_size",\ 3326 .value = "0x20000000",\ 3327 }, 3328 3329 static void spapr_machine_2_2_instance_options(MachineState *machine) 3330 { 3331 spapr_machine_2_3_instance_options(machine); 3332 machine->suppress_vmdesc = true; 3333 } 3334 3335 static void spapr_machine_2_2_class_options(MachineClass *mc) 3336 { 3337 spapr_machine_2_3_class_options(mc); 3338 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 3339 } 3340 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 3341 3342 /* 3343 * pseries-2.1 3344 */ 3345 #define SPAPR_COMPAT_2_1 \ 3346 HW_COMPAT_2_1 3347 3348 static void spapr_machine_2_1_instance_options(MachineState *machine) 3349 { 3350 spapr_machine_2_2_instance_options(machine); 3351 } 3352 3353 static void spapr_machine_2_1_class_options(MachineClass *mc) 3354 { 3355 spapr_machine_2_2_class_options(mc); 3356 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 3357 } 3358 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 3359 3360 static void spapr_machine_register_types(void) 3361 { 3362 type_register_static(&spapr_machine_info); 3363 } 3364 3365 type_init(spapr_machine_register_types) 3366