1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/numa.h" 32 #include "hw/hw.h" 33 #include "qemu/log.h" 34 #include "hw/fw-path-provider.h" 35 #include "elf.h" 36 #include "net/net.h" 37 #include "sysemu/device_tree.h" 38 #include "sysemu/block-backend.h" 39 #include "sysemu/cpus.h" 40 #include "sysemu/hw_accel.h" 41 #include "kvm_ppc.h" 42 #include "migration/misc.h" 43 #include "migration/global_state.h" 44 #include "migration/register.h" 45 #include "mmu-hash64.h" 46 #include "mmu-book3s-v3.h" 47 #include "cpu-models.h" 48 #include "qom/cpu.h" 49 50 #include "hw/boards.h" 51 #include "hw/ppc/ppc.h" 52 #include "hw/loader.h" 53 54 #include "hw/ppc/fdt.h" 55 #include "hw/ppc/spapr.h" 56 #include "hw/ppc/spapr_vio.h" 57 #include "hw/pci-host/spapr.h" 58 #include "hw/ppc/xics.h" 59 #include "hw/pci/msi.h" 60 61 #include "hw/pci/pci.h" 62 #include "hw/scsi/scsi.h" 63 #include "hw/virtio/virtio-scsi.h" 64 #include "hw/virtio/vhost-scsi-common.h" 65 66 #include "exec/address-spaces.h" 67 #include "hw/usb.h" 68 #include "qemu/config-file.h" 69 #include "qemu/error-report.h" 70 #include "trace.h" 71 #include "hw/nmi.h" 72 #include "hw/intc/intc.h" 73 74 #include "hw/compat.h" 75 #include "qemu/cutils.h" 76 #include "hw/ppc/spapr_cpu_core.h" 77 78 #include <libfdt.h> 79 80 /* SLOF memory layout: 81 * 82 * SLOF raw image loaded at 0, copies its romfs right below the flat 83 * device-tree, then position SLOF itself 31M below that 84 * 85 * So we set FW_OVERHEAD to 40MB which should account for all of that 86 * and more 87 * 88 * We load our kernel at 4M, leaving space for SLOF initial image 89 */ 90 #define FDT_MAX_SIZE 0x100000 91 #define RTAS_MAX_SIZE 0x10000 92 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 93 #define FW_MAX_SIZE 0x400000 94 #define FW_FILE_NAME "slof.bin" 95 #define FW_OVERHEAD 0x2800000 96 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 97 98 #define MIN_RMA_SLOF 128UL 99 100 #define PHANDLE_XICP 0x00001111 101 102 /* These two functions implement the VCPU id numbering: one to compute them 103 * all and one to identify thread 0 of a VCORE. Any change to the first one 104 * is likely to have an impact on the second one, so let's keep them close. 105 */ 106 static int spapr_vcpu_id(sPAPRMachineState *spapr, int cpu_index) 107 { 108 assert(spapr->vsmt); 109 return 110 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 111 } 112 static bool spapr_is_thread0_in_vcore(sPAPRMachineState *spapr, 113 PowerPCCPU *cpu) 114 { 115 assert(spapr->vsmt); 116 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 117 } 118 119 static ICSState *spapr_ics_create(sPAPRMachineState *spapr, 120 const char *type_ics, 121 int nr_irqs, Error **errp) 122 { 123 Error *local_err = NULL; 124 Object *obj; 125 126 obj = object_new(type_ics); 127 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); 128 object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr), 129 &error_abort); 130 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err); 131 if (local_err) { 132 goto error; 133 } 134 object_property_set_bool(obj, true, "realized", &local_err); 135 if (local_err) { 136 goto error; 137 } 138 139 return ICS_SIMPLE(obj); 140 141 error: 142 error_propagate(errp, local_err); 143 return NULL; 144 } 145 146 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 147 { 148 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 149 * and newer QEMUs don't even have them. In both cases, we don't want 150 * to send anything on the wire. 151 */ 152 return false; 153 } 154 155 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 156 .name = "icp/server", 157 .version_id = 1, 158 .minimum_version_id = 1, 159 .needed = pre_2_10_vmstate_dummy_icp_needed, 160 .fields = (VMStateField[]) { 161 VMSTATE_UNUSED(4), /* uint32_t xirr */ 162 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 163 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 164 VMSTATE_END_OF_LIST() 165 }, 166 }; 167 168 static void pre_2_10_vmstate_register_dummy_icp(int i) 169 { 170 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 171 (void *)(uintptr_t) i); 172 } 173 174 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 175 { 176 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 177 (void *)(uintptr_t) i); 178 } 179 180 static int xics_max_server_number(sPAPRMachineState *spapr) 181 { 182 assert(spapr->vsmt); 183 return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads); 184 } 185 186 static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp) 187 { 188 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 189 190 if (kvm_enabled()) { 191 if (machine_kernel_irqchip_allowed(machine) && 192 !xics_kvm_init(spapr, errp)) { 193 spapr->icp_type = TYPE_KVM_ICP; 194 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp); 195 } 196 if (machine_kernel_irqchip_required(machine) && !spapr->ics) { 197 error_prepend(errp, "kernel_irqchip requested but unavailable: "); 198 return; 199 } 200 } 201 202 if (!spapr->ics) { 203 xics_spapr_init(spapr); 204 spapr->icp_type = TYPE_ICP; 205 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp); 206 if (!spapr->ics) { 207 return; 208 } 209 } 210 } 211 212 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 213 int smt_threads) 214 { 215 int i, ret = 0; 216 uint32_t servers_prop[smt_threads]; 217 uint32_t gservers_prop[smt_threads * 2]; 218 int index = spapr_get_vcpu_id(cpu); 219 220 if (cpu->compat_pvr) { 221 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 222 if (ret < 0) { 223 return ret; 224 } 225 } 226 227 /* Build interrupt servers and gservers properties */ 228 for (i = 0; i < smt_threads; i++) { 229 servers_prop[i] = cpu_to_be32(index + i); 230 /* Hack, direct the group queues back to cpu 0 */ 231 gservers_prop[i*2] = cpu_to_be32(index + i); 232 gservers_prop[i*2 + 1] = 0; 233 } 234 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 235 servers_prop, sizeof(servers_prop)); 236 if (ret < 0) { 237 return ret; 238 } 239 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 240 gservers_prop, sizeof(gservers_prop)); 241 242 return ret; 243 } 244 245 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 246 { 247 int index = spapr_get_vcpu_id(cpu); 248 uint32_t associativity[] = {cpu_to_be32(0x5), 249 cpu_to_be32(0x0), 250 cpu_to_be32(0x0), 251 cpu_to_be32(0x0), 252 cpu_to_be32(cpu->node_id), 253 cpu_to_be32(index)}; 254 255 /* Advertise NUMA via ibm,associativity */ 256 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 257 sizeof(associativity)); 258 } 259 260 /* Populate the "ibm,pa-features" property */ 261 static void spapr_populate_pa_features(sPAPRMachineState *spapr, 262 PowerPCCPU *cpu, 263 void *fdt, int offset, 264 bool legacy_guest) 265 { 266 uint8_t pa_features_206[] = { 6, 0, 267 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 268 uint8_t pa_features_207[] = { 24, 0, 269 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 270 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 271 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 272 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 273 uint8_t pa_features_300[] = { 66, 0, 274 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 275 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 276 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 277 /* 6: DS207 */ 278 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 279 /* 16: Vector */ 280 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 281 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 282 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 283 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 284 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 285 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 286 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 287 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 288 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 289 /* 42: PM, 44: PC RA, 46: SC vec'd */ 290 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 291 /* 48: SIMD, 50: QP BFP, 52: String */ 292 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 293 /* 54: DecFP, 56: DecI, 58: SHA */ 294 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 295 /* 60: NM atomic, 62: RNG */ 296 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 297 }; 298 uint8_t *pa_features = NULL; 299 size_t pa_size; 300 301 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 302 pa_features = pa_features_206; 303 pa_size = sizeof(pa_features_206); 304 } 305 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 306 pa_features = pa_features_207; 307 pa_size = sizeof(pa_features_207); 308 } 309 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 310 pa_features = pa_features_300; 311 pa_size = sizeof(pa_features_300); 312 } 313 if (!pa_features) { 314 return; 315 } 316 317 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 318 /* 319 * Note: we keep CI large pages off by default because a 64K capable 320 * guest provisioned with large pages might otherwise try to map a qemu 321 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 322 * even if that qemu runs on a 4k host. 323 * We dd this bit back here if we are confident this is not an issue 324 */ 325 pa_features[3] |= 0x20; 326 } 327 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 328 pa_features[24] |= 0x80; /* Transactional memory support */ 329 } 330 if (legacy_guest && pa_size > 40) { 331 /* Workaround for broken kernels that attempt (guest) radix 332 * mode when they can't handle it, if they see the radix bit set 333 * in pa-features. So hide it from them. */ 334 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 335 } 336 337 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 338 } 339 340 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 341 { 342 int ret = 0, offset, cpus_offset; 343 CPUState *cs; 344 char cpu_model[32]; 345 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 346 347 CPU_FOREACH(cs) { 348 PowerPCCPU *cpu = POWERPC_CPU(cs); 349 DeviceClass *dc = DEVICE_GET_CLASS(cs); 350 int index = spapr_get_vcpu_id(cpu); 351 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 352 353 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 354 continue; 355 } 356 357 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 358 359 cpus_offset = fdt_path_offset(fdt, "/cpus"); 360 if (cpus_offset < 0) { 361 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 362 if (cpus_offset < 0) { 363 return cpus_offset; 364 } 365 } 366 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 367 if (offset < 0) { 368 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 369 if (offset < 0) { 370 return offset; 371 } 372 } 373 374 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 375 pft_size_prop, sizeof(pft_size_prop)); 376 if (ret < 0) { 377 return ret; 378 } 379 380 if (nb_numa_nodes > 1) { 381 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); 382 if (ret < 0) { 383 return ret; 384 } 385 } 386 387 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 388 if (ret < 0) { 389 return ret; 390 } 391 392 spapr_populate_pa_features(spapr, cpu, fdt, offset, 393 spapr->cas_legacy_guest_workaround); 394 } 395 return ret; 396 } 397 398 static hwaddr spapr_node0_size(MachineState *machine) 399 { 400 if (nb_numa_nodes) { 401 int i; 402 for (i = 0; i < nb_numa_nodes; ++i) { 403 if (numa_info[i].node_mem) { 404 return MIN(pow2floor(numa_info[i].node_mem), 405 machine->ram_size); 406 } 407 } 408 } 409 return machine->ram_size; 410 } 411 412 static void add_str(GString *s, const gchar *s1) 413 { 414 g_string_append_len(s, s1, strlen(s1) + 1); 415 } 416 417 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 418 hwaddr size) 419 { 420 uint32_t associativity[] = { 421 cpu_to_be32(0x4), /* length */ 422 cpu_to_be32(0x0), cpu_to_be32(0x0), 423 cpu_to_be32(0x0), cpu_to_be32(nodeid) 424 }; 425 char mem_name[32]; 426 uint64_t mem_reg_property[2]; 427 int off; 428 429 mem_reg_property[0] = cpu_to_be64(start); 430 mem_reg_property[1] = cpu_to_be64(size); 431 432 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 433 off = fdt_add_subnode(fdt, 0, mem_name); 434 _FDT(off); 435 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 436 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 437 sizeof(mem_reg_property)))); 438 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 439 sizeof(associativity)))); 440 return off; 441 } 442 443 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 444 { 445 MachineState *machine = MACHINE(spapr); 446 hwaddr mem_start, node_size; 447 int i, nb_nodes = nb_numa_nodes; 448 NodeInfo *nodes = numa_info; 449 NodeInfo ramnode; 450 451 /* No NUMA nodes, assume there is just one node with whole RAM */ 452 if (!nb_numa_nodes) { 453 nb_nodes = 1; 454 ramnode.node_mem = machine->ram_size; 455 nodes = &ramnode; 456 } 457 458 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 459 if (!nodes[i].node_mem) { 460 continue; 461 } 462 if (mem_start >= machine->ram_size) { 463 node_size = 0; 464 } else { 465 node_size = nodes[i].node_mem; 466 if (node_size > machine->ram_size - mem_start) { 467 node_size = machine->ram_size - mem_start; 468 } 469 } 470 if (!mem_start) { 471 /* spapr_machine_init() checks for rma_size <= node0_size 472 * already */ 473 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 474 mem_start += spapr->rma_size; 475 node_size -= spapr->rma_size; 476 } 477 for ( ; node_size; ) { 478 hwaddr sizetmp = pow2floor(node_size); 479 480 /* mem_start != 0 here */ 481 if (ctzl(mem_start) < ctzl(sizetmp)) { 482 sizetmp = 1ULL << ctzl(mem_start); 483 } 484 485 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 486 node_size -= sizetmp; 487 mem_start += sizetmp; 488 } 489 } 490 491 return 0; 492 } 493 494 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 495 sPAPRMachineState *spapr) 496 { 497 PowerPCCPU *cpu = POWERPC_CPU(cs); 498 CPUPPCState *env = &cpu->env; 499 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 500 int index = spapr_get_vcpu_id(cpu); 501 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 502 0xffffffff, 0xffffffff}; 503 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 504 : SPAPR_TIMEBASE_FREQ; 505 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 506 uint32_t page_sizes_prop[64]; 507 size_t page_sizes_prop_size; 508 uint32_t vcpus_per_socket = smp_threads * smp_cores; 509 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 510 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 511 sPAPRDRConnector *drc; 512 int drc_index; 513 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 514 int i; 515 516 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 517 if (drc) { 518 drc_index = spapr_drc_index(drc); 519 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 520 } 521 522 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 523 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 524 525 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 526 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 527 env->dcache_line_size))); 528 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 529 env->dcache_line_size))); 530 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 531 env->icache_line_size))); 532 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 533 env->icache_line_size))); 534 535 if (pcc->l1_dcache_size) { 536 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 537 pcc->l1_dcache_size))); 538 } else { 539 warn_report("Unknown L1 dcache size for cpu"); 540 } 541 if (pcc->l1_icache_size) { 542 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 543 pcc->l1_icache_size))); 544 } else { 545 warn_report("Unknown L1 icache size for cpu"); 546 } 547 548 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 549 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 550 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 551 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 552 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 553 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 554 555 if (env->spr_cb[SPR_PURR].oea_read) { 556 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 557 } 558 559 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 560 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 561 segs, sizeof(segs)))); 562 } 563 564 /* Advertise VSX (vector extensions) if available 565 * 1 == VMX / Altivec available 566 * 2 == VSX available 567 * 568 * Only CPUs for which we create core types in spapr_cpu_core.c 569 * are possible, and all of those have VMX */ 570 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 571 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 572 } else { 573 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 574 } 575 576 /* Advertise DFP (Decimal Floating Point) if available 577 * 0 / no property == no DFP 578 * 1 == DFP available */ 579 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 580 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 581 } 582 583 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 584 sizeof(page_sizes_prop)); 585 if (page_sizes_prop_size) { 586 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 587 page_sizes_prop, page_sizes_prop_size))); 588 } 589 590 spapr_populate_pa_features(spapr, cpu, fdt, offset, false); 591 592 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 593 cs->cpu_index / vcpus_per_socket))); 594 595 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 596 pft_size_prop, sizeof(pft_size_prop)))); 597 598 if (nb_numa_nodes > 1) { 599 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 600 } 601 602 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 603 604 if (pcc->radix_page_info) { 605 for (i = 0; i < pcc->radix_page_info->count; i++) { 606 radix_AP_encodings[i] = 607 cpu_to_be32(pcc->radix_page_info->entries[i]); 608 } 609 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 610 radix_AP_encodings, 611 pcc->radix_page_info->count * 612 sizeof(radix_AP_encodings[0])))); 613 } 614 } 615 616 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 617 { 618 CPUState *cs; 619 int cpus_offset; 620 char *nodename; 621 622 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 623 _FDT(cpus_offset); 624 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 625 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 626 627 /* 628 * We walk the CPUs in reverse order to ensure that CPU DT nodes 629 * created by fdt_add_subnode() end up in the right order in FDT 630 * for the guest kernel the enumerate the CPUs correctly. 631 */ 632 CPU_FOREACH_REVERSE(cs) { 633 PowerPCCPU *cpu = POWERPC_CPU(cs); 634 int index = spapr_get_vcpu_id(cpu); 635 DeviceClass *dc = DEVICE_GET_CLASS(cs); 636 int offset; 637 638 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 639 continue; 640 } 641 642 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 643 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 644 g_free(nodename); 645 _FDT(offset); 646 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 647 } 648 649 } 650 651 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 652 { 653 MemoryDeviceInfoList *info; 654 655 for (info = list; info; info = info->next) { 656 MemoryDeviceInfo *value = info->value; 657 658 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 659 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 660 661 if (pcdimm_info->addr >= addr && 662 addr < (pcdimm_info->addr + pcdimm_info->size)) { 663 return pcdimm_info->node; 664 } 665 } 666 } 667 668 return -1; 669 } 670 671 struct sPAPRDrconfCellV2 { 672 uint32_t seq_lmbs; 673 uint64_t base_addr; 674 uint32_t drc_index; 675 uint32_t aa_index; 676 uint32_t flags; 677 } QEMU_PACKED; 678 679 typedef struct DrconfCellQueue { 680 struct sPAPRDrconfCellV2 cell; 681 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 682 } DrconfCellQueue; 683 684 static DrconfCellQueue * 685 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 686 uint32_t drc_index, uint32_t aa_index, 687 uint32_t flags) 688 { 689 DrconfCellQueue *elem; 690 691 elem = g_malloc0(sizeof(*elem)); 692 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 693 elem->cell.base_addr = cpu_to_be64(base_addr); 694 elem->cell.drc_index = cpu_to_be32(drc_index); 695 elem->cell.aa_index = cpu_to_be32(aa_index); 696 elem->cell.flags = cpu_to_be32(flags); 697 698 return elem; 699 } 700 701 /* ibm,dynamic-memory-v2 */ 702 static int spapr_populate_drmem_v2(sPAPRMachineState *spapr, void *fdt, 703 int offset, MemoryDeviceInfoList *dimms) 704 { 705 uint8_t *int_buf, *cur_index, buf_len; 706 int ret; 707 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 708 uint64_t addr, cur_addr, size; 709 uint32_t nr_boot_lmbs = (spapr->hotplug_memory.base / lmb_size); 710 uint64_t mem_end = spapr->hotplug_memory.base + 711 memory_region_size(&spapr->hotplug_memory.mr); 712 uint32_t node, nr_entries = 0; 713 sPAPRDRConnector *drc; 714 DrconfCellQueue *elem, *next; 715 MemoryDeviceInfoList *info; 716 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 717 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 718 719 /* Entry to cover RAM and the gap area */ 720 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 721 SPAPR_LMB_FLAGS_RESERVED | 722 SPAPR_LMB_FLAGS_DRC_INVALID); 723 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 724 nr_entries++; 725 726 cur_addr = spapr->hotplug_memory.base; 727 for (info = dimms; info; info = info->next) { 728 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 729 730 addr = di->addr; 731 size = di->size; 732 node = di->node; 733 734 /* Entry for hot-pluggable area */ 735 if (cur_addr < addr) { 736 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 737 g_assert(drc); 738 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 739 cur_addr, spapr_drc_index(drc), -1, 0); 740 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 741 nr_entries++; 742 } 743 744 /* Entry for DIMM */ 745 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 746 g_assert(drc); 747 elem = spapr_get_drconf_cell(size / lmb_size, addr, 748 spapr_drc_index(drc), node, 749 SPAPR_LMB_FLAGS_ASSIGNED); 750 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 751 nr_entries++; 752 cur_addr = addr + size; 753 } 754 755 /* Entry for remaining hotpluggable area */ 756 if (cur_addr < mem_end) { 757 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 758 g_assert(drc); 759 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 760 cur_addr, spapr_drc_index(drc), -1, 0); 761 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 762 nr_entries++; 763 } 764 765 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 766 int_buf = cur_index = g_malloc0(buf_len); 767 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 768 cur_index += sizeof(nr_entries); 769 770 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 771 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 772 cur_index += sizeof(elem->cell); 773 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 774 g_free(elem); 775 } 776 777 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 778 g_free(int_buf); 779 if (ret < 0) { 780 return -1; 781 } 782 return 0; 783 } 784 785 /* ibm,dynamic-memory */ 786 static int spapr_populate_drmem_v1(sPAPRMachineState *spapr, void *fdt, 787 int offset, MemoryDeviceInfoList *dimms) 788 { 789 int i, ret; 790 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 791 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 792 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 793 memory_region_size(&spapr->hotplug_memory.mr)) / 794 lmb_size; 795 uint32_t *int_buf, *cur_index, buf_len; 796 797 /* 798 * Allocate enough buffer size to fit in ibm,dynamic-memory 799 */ 800 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 801 cur_index = int_buf = g_malloc0(buf_len); 802 int_buf[0] = cpu_to_be32(nr_lmbs); 803 cur_index++; 804 for (i = 0; i < nr_lmbs; i++) { 805 uint64_t addr = i * lmb_size; 806 uint32_t *dynamic_memory = cur_index; 807 808 if (i >= hotplug_lmb_start) { 809 sPAPRDRConnector *drc; 810 811 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 812 g_assert(drc); 813 814 dynamic_memory[0] = cpu_to_be32(addr >> 32); 815 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 816 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 817 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 818 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 819 if (memory_region_present(get_system_memory(), addr)) { 820 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 821 } else { 822 dynamic_memory[5] = cpu_to_be32(0); 823 } 824 } else { 825 /* 826 * LMB information for RMA, boot time RAM and gap b/n RAM and 827 * hotplug memory region -- all these are marked as reserved 828 * and as having no valid DRC. 829 */ 830 dynamic_memory[0] = cpu_to_be32(addr >> 32); 831 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 832 dynamic_memory[2] = cpu_to_be32(0); 833 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 834 dynamic_memory[4] = cpu_to_be32(-1); 835 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 836 SPAPR_LMB_FLAGS_DRC_INVALID); 837 } 838 839 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 840 } 841 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 842 g_free(int_buf); 843 if (ret < 0) { 844 return -1; 845 } 846 return 0; 847 } 848 849 /* 850 * Adds ibm,dynamic-reconfiguration-memory node. 851 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 852 * of this device tree node. 853 */ 854 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 855 { 856 MachineState *machine = MACHINE(spapr); 857 int ret, i, offset; 858 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 859 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 860 uint32_t *int_buf, *cur_index, buf_len; 861 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 862 MemoryDeviceInfoList *dimms = NULL; 863 864 /* 865 * Don't create the node if there is no hotpluggable memory 866 */ 867 if (machine->ram_size == machine->maxram_size) { 868 return 0; 869 } 870 871 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 872 873 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 874 sizeof(prop_lmb_size)); 875 if (ret < 0) { 876 return ret; 877 } 878 879 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 880 if (ret < 0) { 881 return ret; 882 } 883 884 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 885 if (ret < 0) { 886 return ret; 887 } 888 889 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 890 dimms = qmp_pc_dimm_device_list(); 891 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 892 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); 893 } else { 894 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); 895 } 896 qapi_free_MemoryDeviceInfoList(dimms); 897 898 if (ret < 0) { 899 return ret; 900 } 901 902 /* ibm,associativity-lookup-arrays */ 903 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 904 cur_index = int_buf = g_malloc0(buf_len); 905 906 cur_index = int_buf; 907 int_buf[0] = cpu_to_be32(nr_nodes); 908 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 909 cur_index += 2; 910 for (i = 0; i < nr_nodes; i++) { 911 uint32_t associativity[] = { 912 cpu_to_be32(0x0), 913 cpu_to_be32(0x0), 914 cpu_to_be32(0x0), 915 cpu_to_be32(i) 916 }; 917 memcpy(cur_index, associativity, sizeof(associativity)); 918 cur_index += 4; 919 } 920 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 921 (cur_index - int_buf) * sizeof(uint32_t)); 922 g_free(int_buf); 923 924 return ret; 925 } 926 927 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 928 sPAPROptionVector *ov5_updates) 929 { 930 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 931 int ret = 0, offset; 932 933 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 934 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 935 g_assert(smc->dr_lmb_enabled); 936 ret = spapr_populate_drconf_memory(spapr, fdt); 937 if (ret) { 938 goto out; 939 } 940 } 941 942 offset = fdt_path_offset(fdt, "/chosen"); 943 if (offset < 0) { 944 offset = fdt_add_subnode(fdt, 0, "chosen"); 945 if (offset < 0) { 946 return offset; 947 } 948 } 949 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 950 "ibm,architecture-vec-5"); 951 952 out: 953 return ret; 954 } 955 956 static bool spapr_hotplugged_dev_before_cas(void) 957 { 958 Object *drc_container, *obj; 959 ObjectProperty *prop; 960 ObjectPropertyIterator iter; 961 962 drc_container = container_get(object_get_root(), "/dr-connector"); 963 object_property_iter_init(&iter, drc_container); 964 while ((prop = object_property_iter_next(&iter))) { 965 if (!strstart(prop->type, "link<", NULL)) { 966 continue; 967 } 968 obj = object_property_get_link(drc_container, prop->name, NULL); 969 if (spapr_drc_needed(obj)) { 970 return true; 971 } 972 } 973 return false; 974 } 975 976 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 977 target_ulong addr, target_ulong size, 978 sPAPROptionVector *ov5_updates) 979 { 980 void *fdt, *fdt_skel; 981 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 982 983 if (spapr_hotplugged_dev_before_cas()) { 984 return 1; 985 } 986 987 if (size < sizeof(hdr) || size > FW_MAX_SIZE) { 988 error_report("SLOF provided an unexpected CAS buffer size " 989 TARGET_FMT_lu " (min: %zu, max: %u)", 990 size, sizeof(hdr), FW_MAX_SIZE); 991 exit(EXIT_FAILURE); 992 } 993 994 size -= sizeof(hdr); 995 996 /* Create skeleton */ 997 fdt_skel = g_malloc0(size); 998 _FDT((fdt_create(fdt_skel, size))); 999 _FDT((fdt_finish_reservemap(fdt_skel))); 1000 _FDT((fdt_begin_node(fdt_skel, ""))); 1001 _FDT((fdt_end_node(fdt_skel))); 1002 _FDT((fdt_finish(fdt_skel))); 1003 fdt = g_malloc0(size); 1004 _FDT((fdt_open_into(fdt_skel, fdt, size))); 1005 g_free(fdt_skel); 1006 1007 /* Fixup cpu nodes */ 1008 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 1009 1010 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 1011 return -1; 1012 } 1013 1014 /* Pack resulting tree */ 1015 _FDT((fdt_pack(fdt))); 1016 1017 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 1018 trace_spapr_cas_failed(size); 1019 return -1; 1020 } 1021 1022 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 1023 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 1024 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 1025 g_free(fdt); 1026 1027 return 0; 1028 } 1029 1030 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 1031 { 1032 int rtas; 1033 GString *hypertas = g_string_sized_new(256); 1034 GString *qemu_hypertas = g_string_sized_new(256); 1035 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 1036 uint64_t max_hotplug_addr = spapr->hotplug_memory.base + 1037 memory_region_size(&spapr->hotplug_memory.mr); 1038 uint32_t lrdr_capacity[] = { 1039 cpu_to_be32(max_hotplug_addr >> 32), 1040 cpu_to_be32(max_hotplug_addr & 0xffffffff), 1041 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 1042 cpu_to_be32(max_cpus / smp_threads), 1043 }; 1044 uint32_t maxdomains[] = { 1045 cpu_to_be32(4), 1046 cpu_to_be32(0), 1047 cpu_to_be32(0), 1048 cpu_to_be32(0), 1049 cpu_to_be32(nb_numa_nodes ? nb_numa_nodes - 1 : 0), 1050 }; 1051 1052 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 1053 1054 /* hypertas */ 1055 add_str(hypertas, "hcall-pft"); 1056 add_str(hypertas, "hcall-term"); 1057 add_str(hypertas, "hcall-dabr"); 1058 add_str(hypertas, "hcall-interrupt"); 1059 add_str(hypertas, "hcall-tce"); 1060 add_str(hypertas, "hcall-vio"); 1061 add_str(hypertas, "hcall-splpar"); 1062 add_str(hypertas, "hcall-bulk"); 1063 add_str(hypertas, "hcall-set-mode"); 1064 add_str(hypertas, "hcall-sprg0"); 1065 add_str(hypertas, "hcall-copy"); 1066 add_str(hypertas, "hcall-debug"); 1067 add_str(qemu_hypertas, "hcall-memop1"); 1068 1069 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 1070 add_str(hypertas, "hcall-multi-tce"); 1071 } 1072 1073 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 1074 add_str(hypertas, "hcall-hpt-resize"); 1075 } 1076 1077 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 1078 hypertas->str, hypertas->len)); 1079 g_string_free(hypertas, TRUE); 1080 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 1081 qemu_hypertas->str, qemu_hypertas->len)); 1082 g_string_free(qemu_hypertas, TRUE); 1083 1084 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 1085 refpoints, sizeof(refpoints))); 1086 1087 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 1088 maxdomains, sizeof(maxdomains))); 1089 1090 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 1091 RTAS_ERROR_LOG_MAX)); 1092 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 1093 RTAS_EVENT_SCAN_RATE)); 1094 1095 g_assert(msi_nonbroken); 1096 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 1097 1098 /* 1099 * According to PAPR, rtas ibm,os-term does not guarantee a return 1100 * back to the guest cpu. 1101 * 1102 * While an additional ibm,extended-os-term property indicates 1103 * that rtas call return will always occur. Set this property. 1104 */ 1105 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 1106 1107 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 1108 lrdr_capacity, sizeof(lrdr_capacity))); 1109 1110 spapr_dt_rtas_tokens(fdt, rtas); 1111 } 1112 1113 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features 1114 * that the guest may request and thus the valid values for bytes 24..26 of 1115 * option vector 5: */ 1116 static void spapr_dt_ov5_platform_support(void *fdt, int chosen) 1117 { 1118 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1119 1120 char val[2 * 4] = { 1121 23, 0x00, /* Xive mode, filled in below. */ 1122 24, 0x00, /* Hash/Radix, filled in below. */ 1123 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1124 26, 0x40, /* Radix options: GTSE == yes. */ 1125 }; 1126 1127 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1128 first_ppc_cpu->compat_pvr)) { 1129 /* If we're in a pre POWER9 compat mode then the guest should do hash */ 1130 val[3] = 0x00; /* Hash */ 1131 } else if (kvm_enabled()) { 1132 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1133 val[3] = 0x80; /* OV5_MMU_BOTH */ 1134 } else if (kvmppc_has_cap_mmu_radix()) { 1135 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1136 } else { 1137 val[3] = 0x00; /* Hash */ 1138 } 1139 } else { 1140 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1141 val[3] = 0xC0; 1142 } 1143 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1144 val, sizeof(val))); 1145 } 1146 1147 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 1148 { 1149 MachineState *machine = MACHINE(spapr); 1150 int chosen; 1151 const char *boot_device = machine->boot_order; 1152 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1153 size_t cb = 0; 1154 char *bootlist = get_boot_devices_list(&cb, true); 1155 1156 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1157 1158 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 1159 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1160 spapr->initrd_base)); 1161 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1162 spapr->initrd_base + spapr->initrd_size)); 1163 1164 if (spapr->kernel_size) { 1165 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 1166 cpu_to_be64(spapr->kernel_size) }; 1167 1168 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1169 &kprop, sizeof(kprop))); 1170 if (spapr->kernel_le) { 1171 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1172 } 1173 } 1174 if (boot_menu) { 1175 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1176 } 1177 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1178 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1179 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1180 1181 if (cb && bootlist) { 1182 int i; 1183 1184 for (i = 0; i < cb; i++) { 1185 if (bootlist[i] == '\n') { 1186 bootlist[i] = ' '; 1187 } 1188 } 1189 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1190 } 1191 1192 if (boot_device && strlen(boot_device)) { 1193 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1194 } 1195 1196 if (!spapr->has_graphics && stdout_path) { 1197 /* 1198 * "linux,stdout-path" and "stdout" properties are deprecated by linux 1199 * kernel. New platforms should only use the "stdout-path" property. Set 1200 * the new property and continue using older property to remain 1201 * compatible with the existing firmware. 1202 */ 1203 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1204 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1205 } 1206 1207 spapr_dt_ov5_platform_support(fdt, chosen); 1208 1209 g_free(stdout_path); 1210 g_free(bootlist); 1211 } 1212 1213 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 1214 { 1215 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1216 * KVM to work under pHyp with some guest co-operation */ 1217 int hypervisor; 1218 uint8_t hypercall[16]; 1219 1220 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1221 /* indicate KVM hypercall interface */ 1222 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1223 if (kvmppc_has_cap_fixup_hcalls()) { 1224 /* 1225 * Older KVM versions with older guest kernels were broken 1226 * with the magic page, don't allow the guest to map it. 1227 */ 1228 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1229 sizeof(hypercall))) { 1230 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1231 hypercall, sizeof(hypercall))); 1232 } 1233 } 1234 } 1235 1236 static void *spapr_build_fdt(sPAPRMachineState *spapr, 1237 hwaddr rtas_addr, 1238 hwaddr rtas_size) 1239 { 1240 MachineState *machine = MACHINE(spapr); 1241 MachineClass *mc = MACHINE_GET_CLASS(machine); 1242 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1243 int ret; 1244 void *fdt; 1245 sPAPRPHBState *phb; 1246 char *buf; 1247 1248 fdt = g_malloc0(FDT_MAX_SIZE); 1249 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 1250 1251 /* Root node */ 1252 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1253 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1254 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1255 1256 /* 1257 * Add info to guest to indentify which host is it being run on 1258 * and what is the uuid of the guest 1259 */ 1260 if (kvmppc_get_host_model(&buf)) { 1261 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1262 g_free(buf); 1263 } 1264 if (kvmppc_get_host_serial(&buf)) { 1265 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1266 g_free(buf); 1267 } 1268 1269 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1270 1271 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1272 if (qemu_uuid_set) { 1273 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1274 } 1275 g_free(buf); 1276 1277 if (qemu_get_vm_name()) { 1278 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1279 qemu_get_vm_name())); 1280 } 1281 1282 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1283 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1284 1285 /* /interrupt controller */ 1286 spapr_dt_xics(xics_max_server_number(spapr), fdt, PHANDLE_XICP); 1287 1288 ret = spapr_populate_memory(spapr, fdt); 1289 if (ret < 0) { 1290 error_report("couldn't setup memory nodes in fdt"); 1291 exit(1); 1292 } 1293 1294 /* /vdevice */ 1295 spapr_dt_vdevice(spapr->vio_bus, fdt); 1296 1297 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1298 ret = spapr_rng_populate_dt(fdt); 1299 if (ret < 0) { 1300 error_report("could not set up rng device in the fdt"); 1301 exit(1); 1302 } 1303 } 1304 1305 QLIST_FOREACH(phb, &spapr->phbs, list) { 1306 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 1307 if (ret < 0) { 1308 error_report("couldn't setup PCI devices in fdt"); 1309 exit(1); 1310 } 1311 } 1312 1313 /* cpus */ 1314 spapr_populate_cpus_dt_node(fdt, spapr); 1315 1316 if (smc->dr_lmb_enabled) { 1317 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1318 } 1319 1320 if (mc->has_hotpluggable_cpus) { 1321 int offset = fdt_path_offset(fdt, "/cpus"); 1322 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1323 SPAPR_DR_CONNECTOR_TYPE_CPU); 1324 if (ret < 0) { 1325 error_report("Couldn't set up CPU DR device tree properties"); 1326 exit(1); 1327 } 1328 } 1329 1330 /* /event-sources */ 1331 spapr_dt_events(spapr, fdt); 1332 1333 /* /rtas */ 1334 spapr_dt_rtas(spapr, fdt); 1335 1336 /* /chosen */ 1337 spapr_dt_chosen(spapr, fdt); 1338 1339 /* /hypervisor */ 1340 if (kvm_enabled()) { 1341 spapr_dt_hypervisor(spapr, fdt); 1342 } 1343 1344 /* Build memory reserve map */ 1345 if (spapr->kernel_size) { 1346 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1347 } 1348 if (spapr->initrd_size) { 1349 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1350 } 1351 1352 /* ibm,client-architecture-support updates */ 1353 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1354 if (ret < 0) { 1355 error_report("couldn't setup CAS properties fdt"); 1356 exit(1); 1357 } 1358 1359 return fdt; 1360 } 1361 1362 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1363 { 1364 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1365 } 1366 1367 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1368 PowerPCCPU *cpu) 1369 { 1370 CPUPPCState *env = &cpu->env; 1371 1372 /* The TCG path should also be holding the BQL at this point */ 1373 g_assert(qemu_mutex_iothread_locked()); 1374 1375 if (msr_pr) { 1376 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1377 env->gpr[3] = H_PRIVILEGE; 1378 } else { 1379 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1380 } 1381 } 1382 1383 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) 1384 { 1385 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1386 1387 return spapr->patb_entry; 1388 } 1389 1390 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1391 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1392 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1393 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1394 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1395 1396 /* 1397 * Get the fd to access the kernel htab, re-opening it if necessary 1398 */ 1399 static int get_htab_fd(sPAPRMachineState *spapr) 1400 { 1401 Error *local_err = NULL; 1402 1403 if (spapr->htab_fd >= 0) { 1404 return spapr->htab_fd; 1405 } 1406 1407 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1408 if (spapr->htab_fd < 0) { 1409 error_report_err(local_err); 1410 } 1411 1412 return spapr->htab_fd; 1413 } 1414 1415 void close_htab_fd(sPAPRMachineState *spapr) 1416 { 1417 if (spapr->htab_fd >= 0) { 1418 close(spapr->htab_fd); 1419 } 1420 spapr->htab_fd = -1; 1421 } 1422 1423 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1424 { 1425 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1426 1427 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1428 } 1429 1430 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1431 { 1432 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1433 1434 assert(kvm_enabled()); 1435 1436 if (!spapr->htab) { 1437 return 0; 1438 } 1439 1440 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1441 } 1442 1443 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1444 hwaddr ptex, int n) 1445 { 1446 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1447 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1448 1449 if (!spapr->htab) { 1450 /* 1451 * HTAB is controlled by KVM. Fetch into temporary buffer 1452 */ 1453 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1454 kvmppc_read_hptes(hptes, ptex, n); 1455 return hptes; 1456 } 1457 1458 /* 1459 * HTAB is controlled by QEMU. Just point to the internally 1460 * accessible PTEG. 1461 */ 1462 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1463 } 1464 1465 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1466 const ppc_hash_pte64_t *hptes, 1467 hwaddr ptex, int n) 1468 { 1469 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1470 1471 if (!spapr->htab) { 1472 g_free((void *)hptes); 1473 } 1474 1475 /* Nothing to do for qemu managed HPT */ 1476 } 1477 1478 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1479 uint64_t pte0, uint64_t pte1) 1480 { 1481 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1482 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1483 1484 if (!spapr->htab) { 1485 kvmppc_write_hpte(ptex, pte0, pte1); 1486 } else { 1487 stq_p(spapr->htab + offset, pte0); 1488 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1489 } 1490 } 1491 1492 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1493 { 1494 int shift; 1495 1496 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1497 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1498 * that's much more than is needed for Linux guests */ 1499 shift = ctz64(pow2ceil(ramsize)) - 7; 1500 shift = MAX(shift, 18); /* Minimum architected size */ 1501 shift = MIN(shift, 46); /* Maximum architected size */ 1502 return shift; 1503 } 1504 1505 void spapr_free_hpt(sPAPRMachineState *spapr) 1506 { 1507 g_free(spapr->htab); 1508 spapr->htab = NULL; 1509 spapr->htab_shift = 0; 1510 close_htab_fd(spapr); 1511 } 1512 1513 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1514 Error **errp) 1515 { 1516 long rc; 1517 1518 /* Clean up any HPT info from a previous boot */ 1519 spapr_free_hpt(spapr); 1520 1521 rc = kvmppc_reset_htab(shift); 1522 if (rc < 0) { 1523 /* kernel-side HPT needed, but couldn't allocate one */ 1524 error_setg_errno(errp, errno, 1525 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1526 shift); 1527 /* This is almost certainly fatal, but if the caller really 1528 * wants to carry on with shift == 0, it's welcome to try */ 1529 } else if (rc > 0) { 1530 /* kernel-side HPT allocated */ 1531 if (rc != shift) { 1532 error_setg(errp, 1533 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1534 shift, rc); 1535 } 1536 1537 spapr->htab_shift = shift; 1538 spapr->htab = NULL; 1539 } else { 1540 /* kernel-side HPT not needed, allocate in userspace instead */ 1541 size_t size = 1ULL << shift; 1542 int i; 1543 1544 spapr->htab = qemu_memalign(size, size); 1545 if (!spapr->htab) { 1546 error_setg_errno(errp, errno, 1547 "Could not allocate HPT of order %d", shift); 1548 return; 1549 } 1550 1551 memset(spapr->htab, 0, size); 1552 spapr->htab_shift = shift; 1553 1554 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1555 DIRTY_HPTE(HPTE(spapr->htab, i)); 1556 } 1557 } 1558 /* We're setting up a hash table, so that means we're not radix */ 1559 spapr->patb_entry = 0; 1560 } 1561 1562 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) 1563 { 1564 int hpt_shift; 1565 1566 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1567 || (spapr->cas_reboot 1568 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1569 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1570 } else { 1571 uint64_t current_ram_size; 1572 1573 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1574 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1575 } 1576 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1577 1578 if (spapr->vrma_adjust) { 1579 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), 1580 spapr->htab_shift); 1581 } 1582 } 1583 1584 static int spapr_reset_drcs(Object *child, void *opaque) 1585 { 1586 sPAPRDRConnector *drc = 1587 (sPAPRDRConnector *) object_dynamic_cast(child, 1588 TYPE_SPAPR_DR_CONNECTOR); 1589 1590 if (drc) { 1591 spapr_drc_reset(drc); 1592 } 1593 1594 return 0; 1595 } 1596 1597 static void spapr_machine_reset(void) 1598 { 1599 MachineState *machine = MACHINE(qdev_get_machine()); 1600 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1601 PowerPCCPU *first_ppc_cpu; 1602 uint32_t rtas_limit; 1603 hwaddr rtas_addr, fdt_addr; 1604 void *fdt; 1605 int rc; 1606 1607 spapr_caps_reset(spapr); 1608 1609 first_ppc_cpu = POWERPC_CPU(first_cpu); 1610 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1611 ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1612 spapr->max_compat_pvr)) { 1613 /* If using KVM with radix mode available, VCPUs can be started 1614 * without a HPT because KVM will start them in radix mode. 1615 * Set the GR bit in PATB so that we know there is no HPT. */ 1616 spapr->patb_entry = PATBE1_GR; 1617 } else { 1618 spapr_setup_hpt_and_vrma(spapr); 1619 } 1620 1621 /* if this reset wasn't generated by CAS, we should reset our 1622 * negotiated options and start from scratch */ 1623 if (!spapr->cas_reboot) { 1624 spapr_ovec_cleanup(spapr->ov5_cas); 1625 spapr->ov5_cas = spapr_ovec_new(); 1626 1627 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal); 1628 } 1629 1630 qemu_devices_reset(); 1631 1632 /* DRC reset may cause a device to be unplugged. This will cause troubles 1633 * if this device is used by another device (eg, a running vhost backend 1634 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1635 * situations, we reset DRCs after all devices have been reset. 1636 */ 1637 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1638 1639 spapr_clear_pending_events(spapr); 1640 1641 /* 1642 * We place the device tree and RTAS just below either the top of the RMA, 1643 * or just below 2GB, whichever is lowere, so that it can be 1644 * processed with 32-bit real mode code if necessary 1645 */ 1646 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1647 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1648 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1649 1650 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1651 1652 spapr_load_rtas(spapr, fdt, rtas_addr); 1653 1654 rc = fdt_pack(fdt); 1655 1656 /* Should only fail if we've built a corrupted tree */ 1657 assert(rc == 0); 1658 1659 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1660 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1661 fdt_totalsize(fdt), FDT_MAX_SIZE); 1662 exit(1); 1663 } 1664 1665 /* Load the fdt */ 1666 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1667 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1668 g_free(fdt); 1669 1670 /* Set up the entry state */ 1671 first_ppc_cpu->env.gpr[3] = fdt_addr; 1672 first_ppc_cpu->env.gpr[5] = 0; 1673 first_cpu->halted = 0; 1674 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1675 1676 spapr->cas_reboot = false; 1677 } 1678 1679 static void spapr_create_nvram(sPAPRMachineState *spapr) 1680 { 1681 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1682 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1683 1684 if (dinfo) { 1685 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1686 &error_fatal); 1687 } 1688 1689 qdev_init_nofail(dev); 1690 1691 spapr->nvram = (struct sPAPRNVRAM *)dev; 1692 } 1693 1694 static void spapr_rtc_create(sPAPRMachineState *spapr) 1695 { 1696 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); 1697 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), 1698 &error_fatal); 1699 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1700 &error_fatal); 1701 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1702 "date", &error_fatal); 1703 } 1704 1705 /* Returns whether we want to use VGA or not */ 1706 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1707 { 1708 switch (vga_interface_type) { 1709 case VGA_NONE: 1710 return false; 1711 case VGA_DEVICE: 1712 return true; 1713 case VGA_STD: 1714 case VGA_VIRTIO: 1715 return pci_vga_init(pci_bus) != NULL; 1716 default: 1717 error_setg(errp, 1718 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1719 return false; 1720 } 1721 } 1722 1723 static int spapr_pre_load(void *opaque) 1724 { 1725 int rc; 1726 1727 rc = spapr_caps_pre_load(opaque); 1728 if (rc) { 1729 return rc; 1730 } 1731 1732 return 0; 1733 } 1734 1735 static int spapr_post_load(void *opaque, int version_id) 1736 { 1737 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1738 int err = 0; 1739 1740 err = spapr_caps_post_migration(spapr); 1741 if (err) { 1742 return err; 1743 } 1744 1745 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { 1746 CPUState *cs; 1747 CPU_FOREACH(cs) { 1748 PowerPCCPU *cpu = POWERPC_CPU(cs); 1749 icp_resend(ICP(cpu->intc)); 1750 } 1751 } 1752 1753 /* In earlier versions, there was no separate qdev for the PAPR 1754 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1755 * So when migrating from those versions, poke the incoming offset 1756 * value into the RTC device */ 1757 if (version_id < 3) { 1758 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1759 } 1760 1761 if (kvm_enabled() && spapr->patb_entry) { 1762 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1763 bool radix = !!(spapr->patb_entry & PATBE1_GR); 1764 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1765 1766 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1767 if (err) { 1768 error_report("Process table config unsupported by the host"); 1769 return -EINVAL; 1770 } 1771 } 1772 1773 return err; 1774 } 1775 1776 static int spapr_pre_save(void *opaque) 1777 { 1778 int rc; 1779 1780 rc = spapr_caps_pre_save(opaque); 1781 if (rc) { 1782 return rc; 1783 } 1784 1785 return 0; 1786 } 1787 1788 static bool version_before_3(void *opaque, int version_id) 1789 { 1790 return version_id < 3; 1791 } 1792 1793 static bool spapr_pending_events_needed(void *opaque) 1794 { 1795 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1796 return !QTAILQ_EMPTY(&spapr->pending_events); 1797 } 1798 1799 static const VMStateDescription vmstate_spapr_event_entry = { 1800 .name = "spapr_event_log_entry", 1801 .version_id = 1, 1802 .minimum_version_id = 1, 1803 .fields = (VMStateField[]) { 1804 VMSTATE_UINT32(summary, sPAPREventLogEntry), 1805 VMSTATE_UINT32(extended_length, sPAPREventLogEntry), 1806 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0, 1807 NULL, extended_length), 1808 VMSTATE_END_OF_LIST() 1809 }, 1810 }; 1811 1812 static const VMStateDescription vmstate_spapr_pending_events = { 1813 .name = "spapr_pending_events", 1814 .version_id = 1, 1815 .minimum_version_id = 1, 1816 .needed = spapr_pending_events_needed, 1817 .fields = (VMStateField[]) { 1818 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1, 1819 vmstate_spapr_event_entry, sPAPREventLogEntry, next), 1820 VMSTATE_END_OF_LIST() 1821 }, 1822 }; 1823 1824 static bool spapr_ov5_cas_needed(void *opaque) 1825 { 1826 sPAPRMachineState *spapr = opaque; 1827 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1828 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1829 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1830 bool cas_needed; 1831 1832 /* Prior to the introduction of sPAPROptionVector, we had two option 1833 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1834 * Both of these options encode machine topology into the device-tree 1835 * in such a way that the now-booted OS should still be able to interact 1836 * appropriately with QEMU regardless of what options were actually 1837 * negotiatied on the source side. 1838 * 1839 * As such, we can avoid migrating the CAS-negotiated options if these 1840 * are the only options available on the current machine/platform. 1841 * Since these are the only options available for pseries-2.7 and 1842 * earlier, this allows us to maintain old->new/new->old migration 1843 * compatibility. 1844 * 1845 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1846 * via default pseries-2.8 machines and explicit command-line parameters. 1847 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1848 * of the actual CAS-negotiated values to continue working properly. For 1849 * example, availability of memory unplug depends on knowing whether 1850 * OV5_HP_EVT was negotiated via CAS. 1851 * 1852 * Thus, for any cases where the set of available CAS-negotiatable 1853 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1854 * include the CAS-negotiated options in the migration stream. 1855 */ 1856 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1857 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1858 1859 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1860 * the mask itself since in the future it's possible "legacy" bits may be 1861 * removed via machine options, which could generate a false positive 1862 * that breaks migration. 1863 */ 1864 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1865 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1866 1867 spapr_ovec_cleanup(ov5_mask); 1868 spapr_ovec_cleanup(ov5_legacy); 1869 spapr_ovec_cleanup(ov5_removed); 1870 1871 return cas_needed; 1872 } 1873 1874 static const VMStateDescription vmstate_spapr_ov5_cas = { 1875 .name = "spapr_option_vector_ov5_cas", 1876 .version_id = 1, 1877 .minimum_version_id = 1, 1878 .needed = spapr_ov5_cas_needed, 1879 .fields = (VMStateField[]) { 1880 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1881 vmstate_spapr_ovec, sPAPROptionVector), 1882 VMSTATE_END_OF_LIST() 1883 }, 1884 }; 1885 1886 static bool spapr_patb_entry_needed(void *opaque) 1887 { 1888 sPAPRMachineState *spapr = opaque; 1889 1890 return !!spapr->patb_entry; 1891 } 1892 1893 static const VMStateDescription vmstate_spapr_patb_entry = { 1894 .name = "spapr_patb_entry", 1895 .version_id = 1, 1896 .minimum_version_id = 1, 1897 .needed = spapr_patb_entry_needed, 1898 .fields = (VMStateField[]) { 1899 VMSTATE_UINT64(patb_entry, sPAPRMachineState), 1900 VMSTATE_END_OF_LIST() 1901 }, 1902 }; 1903 1904 static const VMStateDescription vmstate_spapr = { 1905 .name = "spapr", 1906 .version_id = 3, 1907 .minimum_version_id = 1, 1908 .pre_load = spapr_pre_load, 1909 .post_load = spapr_post_load, 1910 .pre_save = spapr_pre_save, 1911 .fields = (VMStateField[]) { 1912 /* used to be @next_irq */ 1913 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1914 1915 /* RTC offset */ 1916 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1917 1918 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1919 VMSTATE_END_OF_LIST() 1920 }, 1921 .subsections = (const VMStateDescription*[]) { 1922 &vmstate_spapr_ov5_cas, 1923 &vmstate_spapr_patb_entry, 1924 &vmstate_spapr_pending_events, 1925 &vmstate_spapr_cap_htm, 1926 &vmstate_spapr_cap_vsx, 1927 &vmstate_spapr_cap_dfp, 1928 &vmstate_spapr_cap_cfpc, 1929 &vmstate_spapr_cap_sbbc, 1930 &vmstate_spapr_cap_ibs, 1931 NULL 1932 } 1933 }; 1934 1935 static int htab_save_setup(QEMUFile *f, void *opaque) 1936 { 1937 sPAPRMachineState *spapr = opaque; 1938 1939 /* "Iteration" header */ 1940 if (!spapr->htab_shift) { 1941 qemu_put_be32(f, -1); 1942 } else { 1943 qemu_put_be32(f, spapr->htab_shift); 1944 } 1945 1946 if (spapr->htab) { 1947 spapr->htab_save_index = 0; 1948 spapr->htab_first_pass = true; 1949 } else { 1950 if (spapr->htab_shift) { 1951 assert(kvm_enabled()); 1952 } 1953 } 1954 1955 1956 return 0; 1957 } 1958 1959 static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr, 1960 int chunkstart, int n_valid, int n_invalid) 1961 { 1962 qemu_put_be32(f, chunkstart); 1963 qemu_put_be16(f, n_valid); 1964 qemu_put_be16(f, n_invalid); 1965 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1966 HASH_PTE_SIZE_64 * n_valid); 1967 } 1968 1969 static void htab_save_end_marker(QEMUFile *f) 1970 { 1971 qemu_put_be32(f, 0); 1972 qemu_put_be16(f, 0); 1973 qemu_put_be16(f, 0); 1974 } 1975 1976 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1977 int64_t max_ns) 1978 { 1979 bool has_timeout = max_ns != -1; 1980 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1981 int index = spapr->htab_save_index; 1982 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1983 1984 assert(spapr->htab_first_pass); 1985 1986 do { 1987 int chunkstart; 1988 1989 /* Consume invalid HPTEs */ 1990 while ((index < htabslots) 1991 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1992 CLEAN_HPTE(HPTE(spapr->htab, index)); 1993 index++; 1994 } 1995 1996 /* Consume valid HPTEs */ 1997 chunkstart = index; 1998 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1999 && HPTE_VALID(HPTE(spapr->htab, index))) { 2000 CLEAN_HPTE(HPTE(spapr->htab, index)); 2001 index++; 2002 } 2003 2004 if (index > chunkstart) { 2005 int n_valid = index - chunkstart; 2006 2007 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2008 2009 if (has_timeout && 2010 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2011 break; 2012 } 2013 } 2014 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2015 2016 if (index >= htabslots) { 2017 assert(index == htabslots); 2018 index = 0; 2019 spapr->htab_first_pass = false; 2020 } 2021 spapr->htab_save_index = index; 2022 } 2023 2024 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 2025 int64_t max_ns) 2026 { 2027 bool final = max_ns < 0; 2028 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2029 int examined = 0, sent = 0; 2030 int index = spapr->htab_save_index; 2031 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2032 2033 assert(!spapr->htab_first_pass); 2034 2035 do { 2036 int chunkstart, invalidstart; 2037 2038 /* Consume non-dirty HPTEs */ 2039 while ((index < htabslots) 2040 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2041 index++; 2042 examined++; 2043 } 2044 2045 chunkstart = index; 2046 /* Consume valid dirty HPTEs */ 2047 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2048 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2049 && HPTE_VALID(HPTE(spapr->htab, index))) { 2050 CLEAN_HPTE(HPTE(spapr->htab, index)); 2051 index++; 2052 examined++; 2053 } 2054 2055 invalidstart = index; 2056 /* Consume invalid dirty HPTEs */ 2057 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2058 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2059 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2060 CLEAN_HPTE(HPTE(spapr->htab, index)); 2061 index++; 2062 examined++; 2063 } 2064 2065 if (index > chunkstart) { 2066 int n_valid = invalidstart - chunkstart; 2067 int n_invalid = index - invalidstart; 2068 2069 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2070 sent += index - chunkstart; 2071 2072 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2073 break; 2074 } 2075 } 2076 2077 if (examined >= htabslots) { 2078 break; 2079 } 2080 2081 if (index >= htabslots) { 2082 assert(index == htabslots); 2083 index = 0; 2084 } 2085 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2086 2087 if (index >= htabslots) { 2088 assert(index == htabslots); 2089 index = 0; 2090 } 2091 2092 spapr->htab_save_index = index; 2093 2094 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2095 } 2096 2097 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2098 #define MAX_KVM_BUF_SIZE 2048 2099 2100 static int htab_save_iterate(QEMUFile *f, void *opaque) 2101 { 2102 sPAPRMachineState *spapr = opaque; 2103 int fd; 2104 int rc = 0; 2105 2106 /* Iteration header */ 2107 if (!spapr->htab_shift) { 2108 qemu_put_be32(f, -1); 2109 return 1; 2110 } else { 2111 qemu_put_be32(f, 0); 2112 } 2113 2114 if (!spapr->htab) { 2115 assert(kvm_enabled()); 2116 2117 fd = get_htab_fd(spapr); 2118 if (fd < 0) { 2119 return fd; 2120 } 2121 2122 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2123 if (rc < 0) { 2124 return rc; 2125 } 2126 } else if (spapr->htab_first_pass) { 2127 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2128 } else { 2129 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2130 } 2131 2132 htab_save_end_marker(f); 2133 2134 return rc; 2135 } 2136 2137 static int htab_save_complete(QEMUFile *f, void *opaque) 2138 { 2139 sPAPRMachineState *spapr = opaque; 2140 int fd; 2141 2142 /* Iteration header */ 2143 if (!spapr->htab_shift) { 2144 qemu_put_be32(f, -1); 2145 return 0; 2146 } else { 2147 qemu_put_be32(f, 0); 2148 } 2149 2150 if (!spapr->htab) { 2151 int rc; 2152 2153 assert(kvm_enabled()); 2154 2155 fd = get_htab_fd(spapr); 2156 if (fd < 0) { 2157 return fd; 2158 } 2159 2160 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2161 if (rc < 0) { 2162 return rc; 2163 } 2164 } else { 2165 if (spapr->htab_first_pass) { 2166 htab_save_first_pass(f, spapr, -1); 2167 } 2168 htab_save_later_pass(f, spapr, -1); 2169 } 2170 2171 /* End marker */ 2172 htab_save_end_marker(f); 2173 2174 return 0; 2175 } 2176 2177 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2178 { 2179 sPAPRMachineState *spapr = opaque; 2180 uint32_t section_hdr; 2181 int fd = -1; 2182 Error *local_err = NULL; 2183 2184 if (version_id < 1 || version_id > 1) { 2185 error_report("htab_load() bad version"); 2186 return -EINVAL; 2187 } 2188 2189 section_hdr = qemu_get_be32(f); 2190 2191 if (section_hdr == -1) { 2192 spapr_free_hpt(spapr); 2193 return 0; 2194 } 2195 2196 if (section_hdr) { 2197 /* First section gives the htab size */ 2198 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2199 if (local_err) { 2200 error_report_err(local_err); 2201 return -EINVAL; 2202 } 2203 return 0; 2204 } 2205 2206 if (!spapr->htab) { 2207 assert(kvm_enabled()); 2208 2209 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2210 if (fd < 0) { 2211 error_report_err(local_err); 2212 return fd; 2213 } 2214 } 2215 2216 while (true) { 2217 uint32_t index; 2218 uint16_t n_valid, n_invalid; 2219 2220 index = qemu_get_be32(f); 2221 n_valid = qemu_get_be16(f); 2222 n_invalid = qemu_get_be16(f); 2223 2224 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2225 /* End of Stream */ 2226 break; 2227 } 2228 2229 if ((index + n_valid + n_invalid) > 2230 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2231 /* Bad index in stream */ 2232 error_report( 2233 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2234 index, n_valid, n_invalid, spapr->htab_shift); 2235 return -EINVAL; 2236 } 2237 2238 if (spapr->htab) { 2239 if (n_valid) { 2240 qemu_get_buffer(f, HPTE(spapr->htab, index), 2241 HASH_PTE_SIZE_64 * n_valid); 2242 } 2243 if (n_invalid) { 2244 memset(HPTE(spapr->htab, index + n_valid), 0, 2245 HASH_PTE_SIZE_64 * n_invalid); 2246 } 2247 } else { 2248 int rc; 2249 2250 assert(fd >= 0); 2251 2252 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2253 if (rc < 0) { 2254 return rc; 2255 } 2256 } 2257 } 2258 2259 if (!spapr->htab) { 2260 assert(fd >= 0); 2261 close(fd); 2262 } 2263 2264 return 0; 2265 } 2266 2267 static void htab_save_cleanup(void *opaque) 2268 { 2269 sPAPRMachineState *spapr = opaque; 2270 2271 close_htab_fd(spapr); 2272 } 2273 2274 static SaveVMHandlers savevm_htab_handlers = { 2275 .save_setup = htab_save_setup, 2276 .save_live_iterate = htab_save_iterate, 2277 .save_live_complete_precopy = htab_save_complete, 2278 .save_cleanup = htab_save_cleanup, 2279 .load_state = htab_load, 2280 }; 2281 2282 static void spapr_boot_set(void *opaque, const char *boot_device, 2283 Error **errp) 2284 { 2285 MachineState *machine = MACHINE(opaque); 2286 machine->boot_order = g_strdup(boot_device); 2287 } 2288 2289 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 2290 { 2291 MachineState *machine = MACHINE(spapr); 2292 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2293 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2294 int i; 2295 2296 for (i = 0; i < nr_lmbs; i++) { 2297 uint64_t addr; 2298 2299 addr = i * lmb_size + spapr->hotplug_memory.base; 2300 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2301 addr / lmb_size); 2302 } 2303 } 2304 2305 /* 2306 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2307 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2308 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2309 */ 2310 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2311 { 2312 int i; 2313 2314 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2315 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2316 " is not aligned to %llu MiB", 2317 machine->ram_size, 2318 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2319 return; 2320 } 2321 2322 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2323 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2324 " is not aligned to %llu MiB", 2325 machine->ram_size, 2326 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2327 return; 2328 } 2329 2330 for (i = 0; i < nb_numa_nodes; i++) { 2331 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2332 error_setg(errp, 2333 "Node %d memory size 0x%" PRIx64 2334 " is not aligned to %llu MiB", 2335 i, numa_info[i].node_mem, 2336 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2337 return; 2338 } 2339 } 2340 } 2341 2342 /* find cpu slot in machine->possible_cpus by core_id */ 2343 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2344 { 2345 int index = id / smp_threads; 2346 2347 if (index >= ms->possible_cpus->len) { 2348 return NULL; 2349 } 2350 if (idx) { 2351 *idx = index; 2352 } 2353 return &ms->possible_cpus->cpus[index]; 2354 } 2355 2356 static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp) 2357 { 2358 Error *local_err = NULL; 2359 bool vsmt_user = !!spapr->vsmt; 2360 int kvm_smt = kvmppc_smt_threads(); 2361 int ret; 2362 2363 if (!kvm_enabled() && (smp_threads > 1)) { 2364 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2365 "on a pseries machine"); 2366 goto out; 2367 } 2368 if (!is_power_of_2(smp_threads)) { 2369 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2370 "machine because it must be a power of 2", smp_threads); 2371 goto out; 2372 } 2373 2374 /* Detemine the VSMT mode to use: */ 2375 if (vsmt_user) { 2376 if (spapr->vsmt < smp_threads) { 2377 error_setg(&local_err, "Cannot support VSMT mode %d" 2378 " because it must be >= threads/core (%d)", 2379 spapr->vsmt, smp_threads); 2380 goto out; 2381 } 2382 /* In this case, spapr->vsmt has been set by the command line */ 2383 } else { 2384 /* 2385 * Default VSMT value is tricky, because we need it to be as 2386 * consistent as possible (for migration), but this requires 2387 * changing it for at least some existing cases. We pick 8 as 2388 * the value that we'd get with KVM on POWER8, the 2389 * overwhelmingly common case in production systems. 2390 */ 2391 spapr->vsmt = MAX(8, smp_threads); 2392 } 2393 2394 /* KVM: If necessary, set the SMT mode: */ 2395 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2396 ret = kvmppc_set_smt_threads(spapr->vsmt); 2397 if (ret) { 2398 /* Looks like KVM isn't able to change VSMT mode */ 2399 error_setg(&local_err, 2400 "Failed to set KVM's VSMT mode to %d (errno %d)", 2401 spapr->vsmt, ret); 2402 /* We can live with that if the default one is big enough 2403 * for the number of threads, and a submultiple of the one 2404 * we want. In this case we'll waste some vcpu ids, but 2405 * behaviour will be correct */ 2406 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2407 warn_report_err(local_err); 2408 local_err = NULL; 2409 goto out; 2410 } else { 2411 if (!vsmt_user) { 2412 error_append_hint(&local_err, 2413 "On PPC, a VM with %d threads/core" 2414 " on a host with %d threads/core" 2415 " requires the use of VSMT mode %d.\n", 2416 smp_threads, kvm_smt, spapr->vsmt); 2417 } 2418 kvmppc_hint_smt_possible(&local_err); 2419 goto out; 2420 } 2421 } 2422 } 2423 /* else TCG: nothing to do currently */ 2424 out: 2425 error_propagate(errp, local_err); 2426 } 2427 2428 static void spapr_init_cpus(sPAPRMachineState *spapr) 2429 { 2430 MachineState *machine = MACHINE(spapr); 2431 MachineClass *mc = MACHINE_GET_CLASS(machine); 2432 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2433 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2434 const CPUArchIdList *possible_cpus; 2435 int boot_cores_nr = smp_cpus / smp_threads; 2436 int i; 2437 2438 possible_cpus = mc->possible_cpu_arch_ids(machine); 2439 if (mc->has_hotpluggable_cpus) { 2440 if (smp_cpus % smp_threads) { 2441 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2442 smp_cpus, smp_threads); 2443 exit(1); 2444 } 2445 if (max_cpus % smp_threads) { 2446 error_report("max_cpus (%u) must be multiple of threads (%u)", 2447 max_cpus, smp_threads); 2448 exit(1); 2449 } 2450 } else { 2451 if (max_cpus != smp_cpus) { 2452 error_report("This machine version does not support CPU hotplug"); 2453 exit(1); 2454 } 2455 boot_cores_nr = possible_cpus->len; 2456 } 2457 2458 /* VSMT must be set in order to be able to compute VCPU ids, ie to 2459 * call xics_max_server_number() or spapr_vcpu_id(). 2460 */ 2461 spapr_set_vsmt_mode(spapr, &error_fatal); 2462 2463 if (smc->pre_2_10_has_unused_icps) { 2464 int i; 2465 2466 for (i = 0; i < xics_max_server_number(spapr); i++) { 2467 /* Dummy entries get deregistered when real ICPState objects 2468 * are registered during CPU core hotplug. 2469 */ 2470 pre_2_10_vmstate_register_dummy_icp(i); 2471 } 2472 } 2473 2474 for (i = 0; i < possible_cpus->len; i++) { 2475 int core_id = i * smp_threads; 2476 2477 if (mc->has_hotpluggable_cpus) { 2478 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2479 spapr_vcpu_id(spapr, core_id)); 2480 } 2481 2482 if (i < boot_cores_nr) { 2483 Object *core = object_new(type); 2484 int nr_threads = smp_threads; 2485 2486 /* Handle the partially filled core for older machine types */ 2487 if ((i + 1) * smp_threads >= smp_cpus) { 2488 nr_threads = smp_cpus - i * smp_threads; 2489 } 2490 2491 object_property_set_int(core, nr_threads, "nr-threads", 2492 &error_fatal); 2493 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2494 &error_fatal); 2495 object_property_set_bool(core, true, "realized", &error_fatal); 2496 } 2497 } 2498 } 2499 2500 /* pSeries LPAR / sPAPR hardware init */ 2501 static void spapr_machine_init(MachineState *machine) 2502 { 2503 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2504 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2505 const char *kernel_filename = machine->kernel_filename; 2506 const char *initrd_filename = machine->initrd_filename; 2507 PCIHostState *phb; 2508 int i; 2509 MemoryRegion *sysmem = get_system_memory(); 2510 MemoryRegion *ram = g_new(MemoryRegion, 1); 2511 MemoryRegion *rma_region; 2512 void *rma = NULL; 2513 hwaddr rma_alloc_size; 2514 hwaddr node0_size = spapr_node0_size(machine); 2515 long load_limit, fw_size; 2516 char *filename; 2517 Error *resize_hpt_err = NULL; 2518 2519 msi_nonbroken = true; 2520 2521 QLIST_INIT(&spapr->phbs); 2522 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2523 2524 /* Check HPT resizing availability */ 2525 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2526 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2527 /* 2528 * If the user explicitly requested a mode we should either 2529 * supply it, or fail completely (which we do below). But if 2530 * it's not set explicitly, we reset our mode to something 2531 * that works 2532 */ 2533 if (resize_hpt_err) { 2534 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2535 error_free(resize_hpt_err); 2536 resize_hpt_err = NULL; 2537 } else { 2538 spapr->resize_hpt = smc->resize_hpt_default; 2539 } 2540 } 2541 2542 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2543 2544 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2545 /* 2546 * User requested HPT resize, but this host can't supply it. Bail out 2547 */ 2548 error_report_err(resize_hpt_err); 2549 exit(1); 2550 } 2551 2552 /* Allocate RMA if necessary */ 2553 rma_alloc_size = kvmppc_alloc_rma(&rma); 2554 2555 if (rma_alloc_size == -1) { 2556 error_report("Unable to create RMA"); 2557 exit(1); 2558 } 2559 2560 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 2561 spapr->rma_size = rma_alloc_size; 2562 } else { 2563 spapr->rma_size = node0_size; 2564 2565 /* With KVM, we don't actually know whether KVM supports an 2566 * unbounded RMA (PR KVM) or is limited by the hash table size 2567 * (HV KVM using VRMA), so we always assume the latter 2568 * 2569 * In that case, we also limit the initial allocations for RTAS 2570 * etc... to 256M since we have no way to know what the VRMA size 2571 * is going to be as it depends on the size of the hash table 2572 * isn't determined yet. 2573 */ 2574 if (kvm_enabled()) { 2575 spapr->vrma_adjust = 1; 2576 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2577 } 2578 2579 /* Actually we don't support unbounded RMA anymore since we 2580 * added proper emulation of HV mode. The max we can get is 2581 * 16G which also happens to be what we configure for PAPR 2582 * mode so make sure we don't do anything bigger than that 2583 */ 2584 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2585 } 2586 2587 if (spapr->rma_size > node0_size) { 2588 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2589 spapr->rma_size); 2590 exit(1); 2591 } 2592 2593 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2594 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2595 2596 /* Set up Interrupt Controller before we create the VCPUs */ 2597 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal); 2598 2599 /* Set up containers for ibm,client-architecture-support negotiated options 2600 */ 2601 spapr->ov5 = spapr_ovec_new(); 2602 spapr->ov5_cas = spapr_ovec_new(); 2603 2604 if (smc->dr_lmb_enabled) { 2605 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2606 spapr_validate_node_memory(machine, &error_fatal); 2607 } 2608 2609 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2610 if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) { 2611 /* KVM and TCG always allow GTSE with radix... */ 2612 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2613 } 2614 /* ... but not with hash (currently). */ 2615 2616 /* advertise support for dedicated HP event source to guests */ 2617 if (spapr->use_hotplug_event_source) { 2618 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2619 } 2620 2621 /* advertise support for HPT resizing */ 2622 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2623 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2624 } 2625 2626 /* advertise support for ibm,dyamic-memory-v2 */ 2627 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2628 2629 /* init CPUs */ 2630 spapr_init_cpus(spapr); 2631 2632 if (kvm_enabled()) { 2633 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2634 kvmppc_enable_logical_ci_hcalls(); 2635 kvmppc_enable_set_mode_hcall(); 2636 2637 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2638 kvmppc_enable_clear_ref_mod_hcalls(); 2639 } 2640 2641 /* allocate RAM */ 2642 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2643 machine->ram_size); 2644 memory_region_add_subregion(sysmem, 0, ram); 2645 2646 if (rma_alloc_size && rma) { 2647 rma_region = g_new(MemoryRegion, 1); 2648 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 2649 rma_alloc_size, rma); 2650 vmstate_register_ram_global(rma_region); 2651 memory_region_add_subregion(sysmem, 0, rma_region); 2652 } 2653 2654 /* initialize hotplug memory address space */ 2655 if (machine->ram_size < machine->maxram_size) { 2656 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 2657 /* 2658 * Limit the number of hotpluggable memory slots to half the number 2659 * slots that KVM supports, leaving the other half for PCI and other 2660 * devices. However ensure that number of slots doesn't drop below 32. 2661 */ 2662 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2663 SPAPR_MAX_RAM_SLOTS; 2664 2665 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2666 max_memslots = SPAPR_MAX_RAM_SLOTS; 2667 } 2668 if (machine->ram_slots > max_memslots) { 2669 error_report("Specified number of memory slots %" 2670 PRIu64" exceeds max supported %d", 2671 machine->ram_slots, max_memslots); 2672 exit(1); 2673 } 2674 2675 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 2676 SPAPR_HOTPLUG_MEM_ALIGN); 2677 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 2678 "hotplug-memory", hotplug_mem_size); 2679 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 2680 &spapr->hotplug_memory.mr); 2681 } 2682 2683 if (smc->dr_lmb_enabled) { 2684 spapr_create_lmb_dr_connectors(spapr); 2685 } 2686 2687 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2688 if (!filename) { 2689 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2690 exit(1); 2691 } 2692 spapr->rtas_size = get_image_size(filename); 2693 if (spapr->rtas_size < 0) { 2694 error_report("Could not get size of LPAR rtas '%s'", filename); 2695 exit(1); 2696 } 2697 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2698 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2699 error_report("Could not load LPAR rtas '%s'", filename); 2700 exit(1); 2701 } 2702 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2703 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2704 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2705 exit(1); 2706 } 2707 g_free(filename); 2708 2709 /* Set up RTAS event infrastructure */ 2710 spapr_events_init(spapr); 2711 2712 /* Set up the RTC RTAS interfaces */ 2713 spapr_rtc_create(spapr); 2714 2715 /* Set up VIO bus */ 2716 spapr->vio_bus = spapr_vio_bus_init(); 2717 2718 for (i = 0; i < serial_max_hds(); i++) { 2719 if (serial_hd(i)) { 2720 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2721 } 2722 } 2723 2724 /* We always have at least the nvram device on VIO */ 2725 spapr_create_nvram(spapr); 2726 2727 /* Set up PCI */ 2728 spapr_pci_rtas_init(); 2729 2730 phb = spapr_create_phb(spapr, 0); 2731 2732 for (i = 0; i < nb_nics; i++) { 2733 NICInfo *nd = &nd_table[i]; 2734 2735 if (!nd->model) { 2736 nd->model = g_strdup("spapr-vlan"); 2737 } 2738 2739 if (g_str_equal(nd->model, "spapr-vlan") || 2740 g_str_equal(nd->model, "ibmveth")) { 2741 spapr_vlan_create(spapr->vio_bus, nd); 2742 } else { 2743 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2744 } 2745 } 2746 2747 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2748 spapr_vscsi_create(spapr->vio_bus); 2749 } 2750 2751 /* Graphics */ 2752 if (spapr_vga_init(phb->bus, &error_fatal)) { 2753 spapr->has_graphics = true; 2754 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2755 } 2756 2757 if (machine->usb) { 2758 if (smc->use_ohci_by_default) { 2759 pci_create_simple(phb->bus, -1, "pci-ohci"); 2760 } else { 2761 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2762 } 2763 2764 if (spapr->has_graphics) { 2765 USBBus *usb_bus = usb_bus_find(-1); 2766 2767 usb_create_simple(usb_bus, "usb-kbd"); 2768 usb_create_simple(usb_bus, "usb-mouse"); 2769 } 2770 } 2771 2772 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 2773 error_report( 2774 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2775 MIN_RMA_SLOF); 2776 exit(1); 2777 } 2778 2779 if (kernel_filename) { 2780 uint64_t lowaddr = 0; 2781 2782 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2783 NULL, NULL, &lowaddr, NULL, 1, 2784 PPC_ELF_MACHINE, 0, 0); 2785 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2786 spapr->kernel_size = load_elf(kernel_filename, 2787 translate_kernel_address, NULL, NULL, 2788 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2789 0, 0); 2790 spapr->kernel_le = spapr->kernel_size > 0; 2791 } 2792 if (spapr->kernel_size < 0) { 2793 error_report("error loading %s: %s", kernel_filename, 2794 load_elf_strerror(spapr->kernel_size)); 2795 exit(1); 2796 } 2797 2798 /* load initrd */ 2799 if (initrd_filename) { 2800 /* Try to locate the initrd in the gap between the kernel 2801 * and the firmware. Add a bit of space just in case 2802 */ 2803 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2804 + 0x1ffff) & ~0xffff; 2805 spapr->initrd_size = load_image_targphys(initrd_filename, 2806 spapr->initrd_base, 2807 load_limit 2808 - spapr->initrd_base); 2809 if (spapr->initrd_size < 0) { 2810 error_report("could not load initial ram disk '%s'", 2811 initrd_filename); 2812 exit(1); 2813 } 2814 } 2815 } 2816 2817 if (bios_name == NULL) { 2818 bios_name = FW_FILE_NAME; 2819 } 2820 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2821 if (!filename) { 2822 error_report("Could not find LPAR firmware '%s'", bios_name); 2823 exit(1); 2824 } 2825 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2826 if (fw_size <= 0) { 2827 error_report("Could not load LPAR firmware '%s'", filename); 2828 exit(1); 2829 } 2830 g_free(filename); 2831 2832 /* FIXME: Should register things through the MachineState's qdev 2833 * interface, this is a legacy from the sPAPREnvironment structure 2834 * which predated MachineState but had a similar function */ 2835 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2836 register_savevm_live(NULL, "spapr/htab", -1, 1, 2837 &savevm_htab_handlers, spapr); 2838 2839 qemu_register_boot_set(spapr_boot_set, spapr); 2840 2841 if (kvm_enabled()) { 2842 /* to stop and start vmclock */ 2843 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2844 &spapr->tb); 2845 2846 kvmppc_spapr_enable_inkernel_multitce(); 2847 } 2848 } 2849 2850 static int spapr_kvm_type(const char *vm_type) 2851 { 2852 if (!vm_type) { 2853 return 0; 2854 } 2855 2856 if (!strcmp(vm_type, "HV")) { 2857 return 1; 2858 } 2859 2860 if (!strcmp(vm_type, "PR")) { 2861 return 2; 2862 } 2863 2864 error_report("Unknown kvm-type specified '%s'", vm_type); 2865 exit(1); 2866 } 2867 2868 /* 2869 * Implementation of an interface to adjust firmware path 2870 * for the bootindex property handling. 2871 */ 2872 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2873 DeviceState *dev) 2874 { 2875 #define CAST(type, obj, name) \ 2876 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2877 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2878 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2879 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 2880 2881 if (d) { 2882 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2883 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2884 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2885 2886 if (spapr) { 2887 /* 2888 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2889 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2890 * in the top 16 bits of the 64-bit LUN 2891 */ 2892 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2893 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2894 (uint64_t)id << 48); 2895 } else if (virtio) { 2896 /* 2897 * We use SRP luns of the form 01000000 | (target << 8) | lun 2898 * in the top 32 bits of the 64-bit LUN 2899 * Note: the quote above is from SLOF and it is wrong, 2900 * the actual binding is: 2901 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2902 */ 2903 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2904 if (d->lun >= 256) { 2905 /* Use the LUN "flat space addressing method" */ 2906 id |= 0x4000; 2907 } 2908 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2909 (uint64_t)id << 32); 2910 } else if (usb) { 2911 /* 2912 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2913 * in the top 32 bits of the 64-bit LUN 2914 */ 2915 unsigned usb_port = atoi(usb->port->path); 2916 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2917 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2918 (uint64_t)id << 32); 2919 } 2920 } 2921 2922 /* 2923 * SLOF probes the USB devices, and if it recognizes that the device is a 2924 * storage device, it changes its name to "storage" instead of "usb-host", 2925 * and additionally adds a child node for the SCSI LUN, so the correct 2926 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2927 */ 2928 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2929 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2930 if (usb_host_dev_is_scsi_storage(usbdev)) { 2931 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2932 } 2933 } 2934 2935 if (phb) { 2936 /* Replace "pci" with "pci@800000020000000" */ 2937 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2938 } 2939 2940 if (vsc) { 2941 /* Same logic as virtio above */ 2942 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 2943 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 2944 } 2945 2946 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 2947 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 2948 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 2949 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 2950 } 2951 2952 return NULL; 2953 } 2954 2955 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2956 { 2957 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2958 2959 return g_strdup(spapr->kvm_type); 2960 } 2961 2962 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2963 { 2964 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2965 2966 g_free(spapr->kvm_type); 2967 spapr->kvm_type = g_strdup(value); 2968 } 2969 2970 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2971 { 2972 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2973 2974 return spapr->use_hotplug_event_source; 2975 } 2976 2977 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2978 Error **errp) 2979 { 2980 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2981 2982 spapr->use_hotplug_event_source = value; 2983 } 2984 2985 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 2986 { 2987 return true; 2988 } 2989 2990 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 2991 { 2992 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2993 2994 switch (spapr->resize_hpt) { 2995 case SPAPR_RESIZE_HPT_DEFAULT: 2996 return g_strdup("default"); 2997 case SPAPR_RESIZE_HPT_DISABLED: 2998 return g_strdup("disabled"); 2999 case SPAPR_RESIZE_HPT_ENABLED: 3000 return g_strdup("enabled"); 3001 case SPAPR_RESIZE_HPT_REQUIRED: 3002 return g_strdup("required"); 3003 } 3004 g_assert_not_reached(); 3005 } 3006 3007 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3008 { 3009 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3010 3011 if (strcmp(value, "default") == 0) { 3012 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3013 } else if (strcmp(value, "disabled") == 0) { 3014 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3015 } else if (strcmp(value, "enabled") == 0) { 3016 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3017 } else if (strcmp(value, "required") == 0) { 3018 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3019 } else { 3020 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3021 } 3022 } 3023 3024 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 3025 void *opaque, Error **errp) 3026 { 3027 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3028 } 3029 3030 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 3031 void *opaque, Error **errp) 3032 { 3033 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3034 } 3035 3036 static void spapr_instance_init(Object *obj) 3037 { 3038 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3039 3040 spapr->htab_fd = -1; 3041 spapr->use_hotplug_event_source = true; 3042 object_property_add_str(obj, "kvm-type", 3043 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 3044 object_property_set_description(obj, "kvm-type", 3045 "Specifies the KVM virtualization mode (HV, PR)", 3046 NULL); 3047 object_property_add_bool(obj, "modern-hotplug-events", 3048 spapr_get_modern_hotplug_events, 3049 spapr_set_modern_hotplug_events, 3050 NULL); 3051 object_property_set_description(obj, "modern-hotplug-events", 3052 "Use dedicated hotplug event mechanism in" 3053 " place of standard EPOW events when possible" 3054 " (required for memory hot-unplug support)", 3055 NULL); 3056 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3057 "Maximum permitted CPU compatibility mode", 3058 &error_fatal); 3059 3060 object_property_add_str(obj, "resize-hpt", 3061 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 3062 object_property_set_description(obj, "resize-hpt", 3063 "Resizing of the Hash Page Table (enabled, disabled, required)", 3064 NULL); 3065 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 3066 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 3067 object_property_set_description(obj, "vsmt", 3068 "Virtual SMT: KVM behaves as if this were" 3069 " the host's SMT mode", &error_abort); 3070 object_property_add_bool(obj, "vfio-no-msix-emulation", 3071 spapr_get_msix_emulation, NULL, NULL); 3072 } 3073 3074 static void spapr_machine_finalizefn(Object *obj) 3075 { 3076 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3077 3078 g_free(spapr->kvm_type); 3079 } 3080 3081 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3082 { 3083 cpu_synchronize_state(cs); 3084 ppc_cpu_do_system_reset(cs); 3085 } 3086 3087 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3088 { 3089 CPUState *cs; 3090 3091 CPU_FOREACH(cs) { 3092 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3093 } 3094 } 3095 3096 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3097 uint32_t node, bool dedicated_hp_event_source, 3098 Error **errp) 3099 { 3100 sPAPRDRConnector *drc; 3101 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3102 int i, fdt_offset, fdt_size; 3103 void *fdt; 3104 uint64_t addr = addr_start; 3105 bool hotplugged = spapr_drc_hotplugged(dev); 3106 Error *local_err = NULL; 3107 3108 for (i = 0; i < nr_lmbs; i++) { 3109 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3110 addr / SPAPR_MEMORY_BLOCK_SIZE); 3111 g_assert(drc); 3112 3113 fdt = create_device_tree(&fdt_size); 3114 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 3115 SPAPR_MEMORY_BLOCK_SIZE); 3116 3117 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 3118 if (local_err) { 3119 while (addr > addr_start) { 3120 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3121 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3122 addr / SPAPR_MEMORY_BLOCK_SIZE); 3123 spapr_drc_detach(drc); 3124 } 3125 g_free(fdt); 3126 error_propagate(errp, local_err); 3127 return; 3128 } 3129 if (!hotplugged) { 3130 spapr_drc_reset(drc); 3131 } 3132 addr += SPAPR_MEMORY_BLOCK_SIZE; 3133 } 3134 /* send hotplug notification to the 3135 * guest only in case of hotplugged memory 3136 */ 3137 if (hotplugged) { 3138 if (dedicated_hp_event_source) { 3139 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3140 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3141 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3142 nr_lmbs, 3143 spapr_drc_index(drc)); 3144 } else { 3145 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3146 nr_lmbs); 3147 } 3148 } 3149 } 3150 3151 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3152 uint32_t node, Error **errp) 3153 { 3154 Error *local_err = NULL; 3155 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3156 PCDIMMDevice *dimm = PC_DIMM(dev); 3157 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3158 MemoryRegion *mr; 3159 uint64_t align, size, addr; 3160 3161 mr = ddc->get_memory_region(dimm, &local_err); 3162 if (local_err) { 3163 goto out; 3164 } 3165 align = memory_region_get_alignment(mr); 3166 size = memory_region_size(mr); 3167 3168 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 3169 if (local_err) { 3170 goto out; 3171 } 3172 3173 addr = object_property_get_uint(OBJECT(dimm), 3174 PC_DIMM_ADDR_PROP, &local_err); 3175 if (local_err) { 3176 goto out_unplug; 3177 } 3178 3179 spapr_add_lmbs(dev, addr, size, node, 3180 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3181 &local_err); 3182 if (local_err) { 3183 goto out_unplug; 3184 } 3185 3186 return; 3187 3188 out_unplug: 3189 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 3190 out: 3191 error_propagate(errp, local_err); 3192 } 3193 3194 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3195 Error **errp) 3196 { 3197 PCDIMMDevice *dimm = PC_DIMM(dev); 3198 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3199 MemoryRegion *mr; 3200 uint64_t size; 3201 char *mem_dev; 3202 3203 mr = ddc->get_memory_region(dimm, errp); 3204 if (!mr) { 3205 return; 3206 } 3207 size = memory_region_size(mr); 3208 3209 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3210 error_setg(errp, "Hotplugged memory size must be a multiple of " 3211 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 3212 return; 3213 } 3214 3215 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); 3216 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { 3217 error_setg(errp, "Memory backend has bad page size. " 3218 "Use 'memory-backend-file' with correct mem-path."); 3219 goto out; 3220 } 3221 3222 out: 3223 g_free(mem_dev); 3224 } 3225 3226 struct sPAPRDIMMState { 3227 PCDIMMDevice *dimm; 3228 uint32_t nr_lmbs; 3229 QTAILQ_ENTRY(sPAPRDIMMState) next; 3230 }; 3231 3232 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, 3233 PCDIMMDevice *dimm) 3234 { 3235 sPAPRDIMMState *dimm_state = NULL; 3236 3237 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3238 if (dimm_state->dimm == dimm) { 3239 break; 3240 } 3241 } 3242 return dimm_state; 3243 } 3244 3245 static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, 3246 uint32_t nr_lmbs, 3247 PCDIMMDevice *dimm) 3248 { 3249 sPAPRDIMMState *ds = NULL; 3250 3251 /* 3252 * If this request is for a DIMM whose removal had failed earlier 3253 * (due to guest's refusal to remove the LMBs), we would have this 3254 * dimm already in the pending_dimm_unplugs list. In that 3255 * case don't add again. 3256 */ 3257 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3258 if (!ds) { 3259 ds = g_malloc0(sizeof(sPAPRDIMMState)); 3260 ds->nr_lmbs = nr_lmbs; 3261 ds->dimm = dimm; 3262 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3263 } 3264 return ds; 3265 } 3266 3267 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, 3268 sPAPRDIMMState *dimm_state) 3269 { 3270 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3271 g_free(dimm_state); 3272 } 3273 3274 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, 3275 PCDIMMDevice *dimm) 3276 { 3277 sPAPRDRConnector *drc; 3278 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3279 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); 3280 uint64_t size = memory_region_size(mr); 3281 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3282 uint32_t avail_lmbs = 0; 3283 uint64_t addr_start, addr; 3284 int i; 3285 3286 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3287 &error_abort); 3288 3289 addr = addr_start; 3290 for (i = 0; i < nr_lmbs; i++) { 3291 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3292 addr / SPAPR_MEMORY_BLOCK_SIZE); 3293 g_assert(drc); 3294 if (drc->dev) { 3295 avail_lmbs++; 3296 } 3297 addr += SPAPR_MEMORY_BLOCK_SIZE; 3298 } 3299 3300 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3301 } 3302 3303 /* Callback to be called during DRC release. */ 3304 void spapr_lmb_release(DeviceState *dev) 3305 { 3306 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_hotplug_handler(dev)); 3307 PCDIMMDevice *dimm = PC_DIMM(dev); 3308 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3309 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); 3310 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3311 3312 /* This information will get lost if a migration occurs 3313 * during the unplug process. In this case recover it. */ 3314 if (ds == NULL) { 3315 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3316 g_assert(ds); 3317 /* The DRC being examined by the caller at least must be counted */ 3318 g_assert(ds->nr_lmbs); 3319 } 3320 3321 if (--ds->nr_lmbs) { 3322 return; 3323 } 3324 3325 /* 3326 * Now that all the LMBs have been removed by the guest, call the 3327 * pc-dimm unplug handler to cleanup up the pc-dimm device. 3328 */ 3329 pc_dimm_memory_unplug(dev, &spapr->hotplug_memory, mr); 3330 object_unparent(OBJECT(dev)); 3331 spapr_pending_dimm_unplugs_remove(spapr, ds); 3332 } 3333 3334 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3335 DeviceState *dev, Error **errp) 3336 { 3337 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3338 Error *local_err = NULL; 3339 PCDIMMDevice *dimm = PC_DIMM(dev); 3340 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3341 MemoryRegion *mr; 3342 uint32_t nr_lmbs; 3343 uint64_t size, addr_start, addr; 3344 int i; 3345 sPAPRDRConnector *drc; 3346 3347 mr = ddc->get_memory_region(dimm, &local_err); 3348 if (local_err) { 3349 goto out; 3350 } 3351 size = memory_region_size(mr); 3352 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3353 3354 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3355 &local_err); 3356 if (local_err) { 3357 goto out; 3358 } 3359 3360 /* 3361 * An existing pending dimm state for this DIMM means that there is an 3362 * unplug operation in progress, waiting for the spapr_lmb_release 3363 * callback to complete the job (BQL can't cover that far). In this case, 3364 * bail out to avoid detaching DRCs that were already released. 3365 */ 3366 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3367 error_setg(&local_err, 3368 "Memory unplug already in progress for device %s", 3369 dev->id); 3370 goto out; 3371 } 3372 3373 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3374 3375 addr = addr_start; 3376 for (i = 0; i < nr_lmbs; i++) { 3377 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3378 addr / SPAPR_MEMORY_BLOCK_SIZE); 3379 g_assert(drc); 3380 3381 spapr_drc_detach(drc); 3382 addr += SPAPR_MEMORY_BLOCK_SIZE; 3383 } 3384 3385 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3386 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3387 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3388 nr_lmbs, spapr_drc_index(drc)); 3389 out: 3390 error_propagate(errp, local_err); 3391 } 3392 3393 static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 3394 sPAPRMachineState *spapr) 3395 { 3396 PowerPCCPU *cpu = POWERPC_CPU(cs); 3397 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3398 int id = spapr_get_vcpu_id(cpu); 3399 void *fdt; 3400 int offset, fdt_size; 3401 char *nodename; 3402 3403 fdt = create_device_tree(&fdt_size); 3404 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3405 offset = fdt_add_subnode(fdt, 0, nodename); 3406 3407 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3408 g_free(nodename); 3409 3410 *fdt_offset = offset; 3411 return fdt; 3412 } 3413 3414 /* Callback to be called during DRC release. */ 3415 void spapr_core_release(DeviceState *dev) 3416 { 3417 MachineState *ms = MACHINE(qdev_get_hotplug_handler(dev)); 3418 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3419 CPUCore *cc = CPU_CORE(dev); 3420 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3421 3422 if (smc->pre_2_10_has_unused_icps) { 3423 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3424 int i; 3425 3426 for (i = 0; i < cc->nr_threads; i++) { 3427 CPUState *cs = CPU(sc->threads[i]); 3428 3429 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3430 } 3431 } 3432 3433 assert(core_slot); 3434 core_slot->cpu = NULL; 3435 object_unparent(OBJECT(dev)); 3436 } 3437 3438 static 3439 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3440 Error **errp) 3441 { 3442 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3443 int index; 3444 sPAPRDRConnector *drc; 3445 CPUCore *cc = CPU_CORE(dev); 3446 3447 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3448 error_setg(errp, "Unable to find CPU core with core-id: %d", 3449 cc->core_id); 3450 return; 3451 } 3452 if (index == 0) { 3453 error_setg(errp, "Boot CPU core may not be unplugged"); 3454 return; 3455 } 3456 3457 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3458 spapr_vcpu_id(spapr, cc->core_id)); 3459 g_assert(drc); 3460 3461 spapr_drc_detach(drc); 3462 3463 spapr_hotplug_req_remove_by_index(drc); 3464 } 3465 3466 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3467 Error **errp) 3468 { 3469 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3470 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3471 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3472 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3473 CPUCore *cc = CPU_CORE(dev); 3474 CPUState *cs = CPU(core->threads[0]); 3475 sPAPRDRConnector *drc; 3476 Error *local_err = NULL; 3477 CPUArchId *core_slot; 3478 int index; 3479 bool hotplugged = spapr_drc_hotplugged(dev); 3480 3481 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3482 if (!core_slot) { 3483 error_setg(errp, "Unable to find CPU core with core-id: %d", 3484 cc->core_id); 3485 return; 3486 } 3487 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3488 spapr_vcpu_id(spapr, cc->core_id)); 3489 3490 g_assert(drc || !mc->has_hotpluggable_cpus); 3491 3492 if (drc) { 3493 void *fdt; 3494 int fdt_offset; 3495 3496 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 3497 3498 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 3499 if (local_err) { 3500 g_free(fdt); 3501 error_propagate(errp, local_err); 3502 return; 3503 } 3504 3505 if (hotplugged) { 3506 /* 3507 * Send hotplug notification interrupt to the guest only 3508 * in case of hotplugged CPUs. 3509 */ 3510 spapr_hotplug_req_add_by_index(drc); 3511 } else { 3512 spapr_drc_reset(drc); 3513 } 3514 } 3515 3516 core_slot->cpu = OBJECT(dev); 3517 3518 if (smc->pre_2_10_has_unused_icps) { 3519 int i; 3520 3521 for (i = 0; i < cc->nr_threads; i++) { 3522 cs = CPU(core->threads[i]); 3523 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3524 } 3525 } 3526 } 3527 3528 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3529 Error **errp) 3530 { 3531 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3532 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3533 Error *local_err = NULL; 3534 CPUCore *cc = CPU_CORE(dev); 3535 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3536 const char *type = object_get_typename(OBJECT(dev)); 3537 CPUArchId *core_slot; 3538 int index; 3539 3540 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3541 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3542 goto out; 3543 } 3544 3545 if (strcmp(base_core_type, type)) { 3546 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3547 goto out; 3548 } 3549 3550 if (cc->core_id % smp_threads) { 3551 error_setg(&local_err, "invalid core id %d", cc->core_id); 3552 goto out; 3553 } 3554 3555 /* 3556 * In general we should have homogeneous threads-per-core, but old 3557 * (pre hotplug support) machine types allow the last core to have 3558 * reduced threads as a compatibility hack for when we allowed 3559 * total vcpus not a multiple of threads-per-core. 3560 */ 3561 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3562 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3563 cc->nr_threads, smp_threads); 3564 goto out; 3565 } 3566 3567 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3568 if (!core_slot) { 3569 error_setg(&local_err, "core id %d out of range", cc->core_id); 3570 goto out; 3571 } 3572 3573 if (core_slot->cpu) { 3574 error_setg(&local_err, "core %d already populated", cc->core_id); 3575 goto out; 3576 } 3577 3578 numa_cpu_pre_plug(core_slot, dev, &local_err); 3579 3580 out: 3581 error_propagate(errp, local_err); 3582 } 3583 3584 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 3585 DeviceState *dev, Error **errp) 3586 { 3587 MachineState *ms = MACHINE(hotplug_dev); 3588 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3589 3590 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3591 int node; 3592 3593 if (!smc->dr_lmb_enabled) { 3594 error_setg(errp, "Memory hotplug not supported for this machine"); 3595 return; 3596 } 3597 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 3598 if (*errp) { 3599 return; 3600 } 3601 if (node < 0 || node >= MAX_NODES) { 3602 error_setg(errp, "Invaild node %d", node); 3603 return; 3604 } 3605 3606 spapr_memory_plug(hotplug_dev, dev, node, errp); 3607 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3608 spapr_core_plug(hotplug_dev, dev, errp); 3609 } 3610 } 3611 3612 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 3613 DeviceState *dev, Error **errp) 3614 { 3615 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3616 MachineClass *mc = MACHINE_GET_CLASS(sms); 3617 3618 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3619 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3620 spapr_memory_unplug_request(hotplug_dev, dev, errp); 3621 } else { 3622 /* NOTE: this means there is a window after guest reset, prior to 3623 * CAS negotiation, where unplug requests will fail due to the 3624 * capability not being detected yet. This is a bit different than 3625 * the case with PCI unplug, where the events will be queued and 3626 * eventually handled by the guest after boot 3627 */ 3628 error_setg(errp, "Memory hot unplug not supported for this guest"); 3629 } 3630 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3631 if (!mc->has_hotpluggable_cpus) { 3632 error_setg(errp, "CPU hot unplug not supported on this machine"); 3633 return; 3634 } 3635 spapr_core_unplug_request(hotplug_dev, dev, errp); 3636 } 3637 } 3638 3639 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 3640 DeviceState *dev, Error **errp) 3641 { 3642 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3643 spapr_memory_pre_plug(hotplug_dev, dev, errp); 3644 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3645 spapr_core_pre_plug(hotplug_dev, dev, errp); 3646 } 3647 } 3648 3649 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 3650 DeviceState *dev) 3651 { 3652 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3653 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3654 return HOTPLUG_HANDLER(machine); 3655 } 3656 return NULL; 3657 } 3658 3659 static CpuInstanceProperties 3660 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 3661 { 3662 CPUArchId *core_slot; 3663 MachineClass *mc = MACHINE_GET_CLASS(machine); 3664 3665 /* make sure possible_cpu are intialized */ 3666 mc->possible_cpu_arch_ids(machine); 3667 /* get CPU core slot containing thread that matches cpu_index */ 3668 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 3669 assert(core_slot); 3670 return core_slot->props; 3671 } 3672 3673 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 3674 { 3675 return idx / smp_cores % nb_numa_nodes; 3676 } 3677 3678 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 3679 { 3680 int i; 3681 const char *core_type; 3682 int spapr_max_cores = max_cpus / smp_threads; 3683 MachineClass *mc = MACHINE_GET_CLASS(machine); 3684 3685 if (!mc->has_hotpluggable_cpus) { 3686 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 3687 } 3688 if (machine->possible_cpus) { 3689 assert(machine->possible_cpus->len == spapr_max_cores); 3690 return machine->possible_cpus; 3691 } 3692 3693 core_type = spapr_get_cpu_core_type(machine->cpu_type); 3694 if (!core_type) { 3695 error_report("Unable to find sPAPR CPU Core definition"); 3696 exit(1); 3697 } 3698 3699 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 3700 sizeof(CPUArchId) * spapr_max_cores); 3701 machine->possible_cpus->len = spapr_max_cores; 3702 for (i = 0; i < machine->possible_cpus->len; i++) { 3703 int core_id = i * smp_threads; 3704 3705 machine->possible_cpus->cpus[i].type = core_type; 3706 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 3707 machine->possible_cpus->cpus[i].arch_id = core_id; 3708 machine->possible_cpus->cpus[i].props.has_core_id = true; 3709 machine->possible_cpus->cpus[i].props.core_id = core_id; 3710 } 3711 return machine->possible_cpus; 3712 } 3713 3714 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 3715 uint64_t *buid, hwaddr *pio, 3716 hwaddr *mmio32, hwaddr *mmio64, 3717 unsigned n_dma, uint32_t *liobns, Error **errp) 3718 { 3719 /* 3720 * New-style PHB window placement. 3721 * 3722 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 3723 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 3724 * windows. 3725 * 3726 * Some guest kernels can't work with MMIO windows above 1<<46 3727 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 3728 * 3729 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 3730 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 3731 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 3732 * 1TiB 64-bit MMIO windows for each PHB. 3733 */ 3734 const uint64_t base_buid = 0x800000020000000ULL; 3735 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 3736 SPAPR_PCI_MEM64_WIN_SIZE - 1) 3737 int i; 3738 3739 /* Sanity check natural alignments */ 3740 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3741 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3742 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 3743 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 3744 /* Sanity check bounds */ 3745 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 3746 SPAPR_PCI_MEM32_WIN_SIZE); 3747 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 3748 SPAPR_PCI_MEM64_WIN_SIZE); 3749 3750 if (index >= SPAPR_MAX_PHBS) { 3751 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 3752 SPAPR_MAX_PHBS - 1); 3753 return; 3754 } 3755 3756 *buid = base_buid + index; 3757 for (i = 0; i < n_dma; ++i) { 3758 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3759 } 3760 3761 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 3762 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 3763 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 3764 } 3765 3766 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 3767 { 3768 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3769 3770 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 3771 } 3772 3773 static void spapr_ics_resend(XICSFabric *dev) 3774 { 3775 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3776 3777 ics_resend(spapr->ics); 3778 } 3779 3780 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 3781 { 3782 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 3783 3784 return cpu ? ICP(cpu->intc) : NULL; 3785 } 3786 3787 #define ICS_IRQ_FREE(ics, srcno) \ 3788 (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK))) 3789 3790 static int ics_find_free_block(ICSState *ics, int num, int alignnum) 3791 { 3792 int first, i; 3793 3794 for (first = 0; first < ics->nr_irqs; first += alignnum) { 3795 if (num > (ics->nr_irqs - first)) { 3796 return -1; 3797 } 3798 for (i = first; i < first + num; ++i) { 3799 if (!ICS_IRQ_FREE(ics, i)) { 3800 break; 3801 } 3802 } 3803 if (i == (first + num)) { 3804 return first; 3805 } 3806 } 3807 3808 return -1; 3809 } 3810 3811 /* 3812 * Allocate the IRQ number and set the IRQ type, LSI or MSI 3813 */ 3814 static void spapr_irq_set_lsi(sPAPRMachineState *spapr, int irq, bool lsi) 3815 { 3816 ics_set_irq_type(spapr->ics, irq - spapr->ics->offset, lsi); 3817 } 3818 3819 int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi, 3820 Error **errp) 3821 { 3822 ICSState *ics = spapr->ics; 3823 int irq; 3824 3825 assert(ics); 3826 3827 if (irq_hint) { 3828 if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) { 3829 error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint); 3830 return -1; 3831 } 3832 irq = irq_hint; 3833 } else { 3834 irq = ics_find_free_block(ics, 1, 1); 3835 if (irq < 0) { 3836 error_setg(errp, "can't allocate IRQ: no IRQ left"); 3837 return -1; 3838 } 3839 irq += ics->offset; 3840 } 3841 3842 spapr_irq_set_lsi(spapr, irq, lsi); 3843 trace_spapr_irq_alloc(irq); 3844 3845 return irq; 3846 } 3847 3848 /* 3849 * Allocate block of consecutive IRQs, and return the number of the first IRQ in 3850 * the block. If align==true, aligns the first IRQ number to num. 3851 */ 3852 int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi, 3853 bool align, Error **errp) 3854 { 3855 ICSState *ics = spapr->ics; 3856 int i, first = -1; 3857 3858 assert(ics); 3859 3860 /* 3861 * MSIMesage::data is used for storing VIRQ so 3862 * it has to be aligned to num to support multiple 3863 * MSI vectors. MSI-X is not affected by this. 3864 * The hint is used for the first IRQ, the rest should 3865 * be allocated continuously. 3866 */ 3867 if (align) { 3868 assert((num == 1) || (num == 2) || (num == 4) || 3869 (num == 8) || (num == 16) || (num == 32)); 3870 first = ics_find_free_block(ics, num, num); 3871 } else { 3872 first = ics_find_free_block(ics, num, 1); 3873 } 3874 if (first < 0) { 3875 error_setg(errp, "can't find a free %d-IRQ block", num); 3876 return -1; 3877 } 3878 3879 first += ics->offset; 3880 for (i = first; i < first + num; ++i) { 3881 spapr_irq_set_lsi(spapr, i, lsi); 3882 } 3883 3884 trace_spapr_irq_alloc_block(first, num, lsi, align); 3885 3886 return first; 3887 } 3888 3889 void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num) 3890 { 3891 ICSState *ics = spapr->ics; 3892 int srcno = irq - ics->offset; 3893 int i; 3894 3895 if (ics_valid_irq(ics, irq)) { 3896 trace_spapr_irq_free(0, irq, num); 3897 for (i = srcno; i < srcno + num; ++i) { 3898 if (ICS_IRQ_FREE(ics, i)) { 3899 trace_spapr_irq_free_warn(0, i + ics->offset); 3900 } 3901 memset(&ics->irqs[i], 0, sizeof(ICSIRQState)); 3902 } 3903 } 3904 } 3905 3906 qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq) 3907 { 3908 ICSState *ics = spapr->ics; 3909 3910 if (ics_valid_irq(ics, irq)) { 3911 return ics->qirqs[irq - ics->offset]; 3912 } 3913 3914 return NULL; 3915 } 3916 3917 static void spapr_pic_print_info(InterruptStatsProvider *obj, 3918 Monitor *mon) 3919 { 3920 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3921 CPUState *cs; 3922 3923 CPU_FOREACH(cs) { 3924 PowerPCCPU *cpu = POWERPC_CPU(cs); 3925 3926 icp_pic_print_info(ICP(cpu->intc), mon); 3927 } 3928 3929 ics_pic_print_info(spapr->ics, mon); 3930 } 3931 3932 int spapr_get_vcpu_id(PowerPCCPU *cpu) 3933 { 3934 return cpu->vcpu_id; 3935 } 3936 3937 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 3938 { 3939 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3940 int vcpu_id; 3941 3942 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 3943 3944 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 3945 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 3946 error_append_hint(errp, "Adjust the number of cpus to %d " 3947 "or try to raise the number of threads per core\n", 3948 vcpu_id * smp_threads / spapr->vsmt); 3949 return; 3950 } 3951 3952 cpu->vcpu_id = vcpu_id; 3953 } 3954 3955 PowerPCCPU *spapr_find_cpu(int vcpu_id) 3956 { 3957 CPUState *cs; 3958 3959 CPU_FOREACH(cs) { 3960 PowerPCCPU *cpu = POWERPC_CPU(cs); 3961 3962 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 3963 return cpu; 3964 } 3965 } 3966 3967 return NULL; 3968 } 3969 3970 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3971 { 3972 MachineClass *mc = MACHINE_CLASS(oc); 3973 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3974 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3975 NMIClass *nc = NMI_CLASS(oc); 3976 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3977 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3978 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3979 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 3980 3981 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3982 3983 /* 3984 * We set up the default / latest behaviour here. The class_init 3985 * functions for the specific versioned machine types can override 3986 * these details for backwards compatibility 3987 */ 3988 mc->init = spapr_machine_init; 3989 mc->reset = spapr_machine_reset; 3990 mc->block_default_type = IF_SCSI; 3991 mc->max_cpus = 1024; 3992 mc->no_parallel = 1; 3993 mc->default_boot_order = ""; 3994 mc->default_ram_size = 512 * M_BYTE; 3995 mc->kvm_type = spapr_kvm_type; 3996 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 3997 mc->pci_allow_0_address = true; 3998 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3999 hc->pre_plug = spapr_machine_device_pre_plug; 4000 hc->plug = spapr_machine_device_plug; 4001 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4002 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4003 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4004 hc->unplug_request = spapr_machine_device_unplug_request; 4005 4006 smc->dr_lmb_enabled = true; 4007 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4008 mc->has_hotpluggable_cpus = true; 4009 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4010 fwc->get_dev_path = spapr_get_fw_dev_path; 4011 nc->nmi_monitor_handler = spapr_nmi; 4012 smc->phb_placement = spapr_phb_placement; 4013 vhc->hypercall = emulate_spapr_hypercall; 4014 vhc->hpt_mask = spapr_hpt_mask; 4015 vhc->map_hptes = spapr_map_hptes; 4016 vhc->unmap_hptes = spapr_unmap_hptes; 4017 vhc->store_hpte = spapr_store_hpte; 4018 vhc->get_patbe = spapr_get_patbe; 4019 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4020 xic->ics_get = spapr_ics_get; 4021 xic->ics_resend = spapr_ics_resend; 4022 xic->icp_get = spapr_icp_get; 4023 ispc->print_info = spapr_pic_print_info; 4024 /* Force NUMA node memory size to be a multiple of 4025 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4026 * in which LMBs are represented and hot-added 4027 */ 4028 mc->numa_mem_align_shift = 28; 4029 4030 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4031 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4032 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4033 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4034 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4035 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4036 spapr_caps_add_properties(smc, &error_abort); 4037 } 4038 4039 static const TypeInfo spapr_machine_info = { 4040 .name = TYPE_SPAPR_MACHINE, 4041 .parent = TYPE_MACHINE, 4042 .abstract = true, 4043 .instance_size = sizeof(sPAPRMachineState), 4044 .instance_init = spapr_instance_init, 4045 .instance_finalize = spapr_machine_finalizefn, 4046 .class_size = sizeof(sPAPRMachineClass), 4047 .class_init = spapr_machine_class_init, 4048 .interfaces = (InterfaceInfo[]) { 4049 { TYPE_FW_PATH_PROVIDER }, 4050 { TYPE_NMI }, 4051 { TYPE_HOTPLUG_HANDLER }, 4052 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4053 { TYPE_XICS_FABRIC }, 4054 { TYPE_INTERRUPT_STATS_PROVIDER }, 4055 { } 4056 }, 4057 }; 4058 4059 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4060 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4061 void *data) \ 4062 { \ 4063 MachineClass *mc = MACHINE_CLASS(oc); \ 4064 spapr_machine_##suffix##_class_options(mc); \ 4065 if (latest) { \ 4066 mc->alias = "pseries"; \ 4067 mc->is_default = 1; \ 4068 } \ 4069 } \ 4070 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 4071 { \ 4072 MachineState *machine = MACHINE(obj); \ 4073 spapr_machine_##suffix##_instance_options(machine); \ 4074 } \ 4075 static const TypeInfo spapr_machine_##suffix##_info = { \ 4076 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4077 .parent = TYPE_SPAPR_MACHINE, \ 4078 .class_init = spapr_machine_##suffix##_class_init, \ 4079 .instance_init = spapr_machine_##suffix##_instance_init, \ 4080 }; \ 4081 static void spapr_machine_register_##suffix(void) \ 4082 { \ 4083 type_register(&spapr_machine_##suffix##_info); \ 4084 } \ 4085 type_init(spapr_machine_register_##suffix) 4086 4087 /* 4088 * pseries-2.13 4089 */ 4090 static void spapr_machine_2_13_instance_options(MachineState *machine) 4091 { 4092 } 4093 4094 static void spapr_machine_2_13_class_options(MachineClass *mc) 4095 { 4096 /* Defaults for the latest behaviour inherited from the base class */ 4097 } 4098 4099 DEFINE_SPAPR_MACHINE(2_13, "2.13", true); 4100 4101 /* 4102 * pseries-2.12 4103 */ 4104 #define SPAPR_COMPAT_2_12 \ 4105 HW_COMPAT_2_12 \ 4106 { \ 4107 .driver = TYPE_POWERPC_CPU, \ 4108 .property = "pre-2.13-migration", \ 4109 .value = "on", \ 4110 }, 4111 4112 static void spapr_machine_2_12_instance_options(MachineState *machine) 4113 { 4114 spapr_machine_2_13_instance_options(machine); 4115 } 4116 4117 static void spapr_machine_2_12_class_options(MachineClass *mc) 4118 { 4119 spapr_machine_2_13_class_options(mc); 4120 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_12); 4121 } 4122 4123 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4124 4125 static void spapr_machine_2_12_sxxm_instance_options(MachineState *machine) 4126 { 4127 spapr_machine_2_12_instance_options(machine); 4128 } 4129 4130 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4131 { 4132 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4133 4134 spapr_machine_2_12_class_options(mc); 4135 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4136 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4137 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4138 } 4139 4140 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4141 4142 /* 4143 * pseries-2.11 4144 */ 4145 #define SPAPR_COMPAT_2_11 \ 4146 HW_COMPAT_2_11 4147 4148 static void spapr_machine_2_11_instance_options(MachineState *machine) 4149 { 4150 spapr_machine_2_12_instance_options(machine); 4151 } 4152 4153 static void spapr_machine_2_11_class_options(MachineClass *mc) 4154 { 4155 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4156 4157 spapr_machine_2_12_class_options(mc); 4158 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4159 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11); 4160 } 4161 4162 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4163 4164 /* 4165 * pseries-2.10 4166 */ 4167 #define SPAPR_COMPAT_2_10 \ 4168 HW_COMPAT_2_10 4169 4170 static void spapr_machine_2_10_instance_options(MachineState *machine) 4171 { 4172 spapr_machine_2_11_instance_options(machine); 4173 } 4174 4175 static void spapr_machine_2_10_class_options(MachineClass *mc) 4176 { 4177 spapr_machine_2_11_class_options(mc); 4178 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10); 4179 } 4180 4181 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4182 4183 /* 4184 * pseries-2.9 4185 */ 4186 #define SPAPR_COMPAT_2_9 \ 4187 HW_COMPAT_2_9 \ 4188 { \ 4189 .driver = TYPE_POWERPC_CPU, \ 4190 .property = "pre-2.10-migration", \ 4191 .value = "on", \ 4192 }, \ 4193 4194 static void spapr_machine_2_9_instance_options(MachineState *machine) 4195 { 4196 spapr_machine_2_10_instance_options(machine); 4197 } 4198 4199 static void spapr_machine_2_9_class_options(MachineClass *mc) 4200 { 4201 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4202 4203 spapr_machine_2_10_class_options(mc); 4204 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); 4205 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4206 smc->pre_2_10_has_unused_icps = true; 4207 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4208 } 4209 4210 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4211 4212 /* 4213 * pseries-2.8 4214 */ 4215 #define SPAPR_COMPAT_2_8 \ 4216 HW_COMPAT_2_8 \ 4217 { \ 4218 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4219 .property = "pcie-extended-configuration-space", \ 4220 .value = "off", \ 4221 }, 4222 4223 static void spapr_machine_2_8_instance_options(MachineState *machine) 4224 { 4225 spapr_machine_2_9_instance_options(machine); 4226 } 4227 4228 static void spapr_machine_2_8_class_options(MachineClass *mc) 4229 { 4230 spapr_machine_2_9_class_options(mc); 4231 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 4232 mc->numa_mem_align_shift = 23; 4233 } 4234 4235 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4236 4237 /* 4238 * pseries-2.7 4239 */ 4240 #define SPAPR_COMPAT_2_7 \ 4241 HW_COMPAT_2_7 \ 4242 { \ 4243 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4244 .property = "mem_win_size", \ 4245 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 4246 }, \ 4247 { \ 4248 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4249 .property = "mem64_win_size", \ 4250 .value = "0", \ 4251 }, \ 4252 { \ 4253 .driver = TYPE_POWERPC_CPU, \ 4254 .property = "pre-2.8-migration", \ 4255 .value = "on", \ 4256 }, \ 4257 { \ 4258 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4259 .property = "pre-2.8-migration", \ 4260 .value = "on", \ 4261 }, 4262 4263 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 4264 uint64_t *buid, hwaddr *pio, 4265 hwaddr *mmio32, hwaddr *mmio64, 4266 unsigned n_dma, uint32_t *liobns, Error **errp) 4267 { 4268 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4269 const uint64_t base_buid = 0x800000020000000ULL; 4270 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4271 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4272 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4273 const uint32_t max_index = 255; 4274 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4275 4276 uint64_t ram_top = MACHINE(spapr)->ram_size; 4277 hwaddr phb0_base, phb_base; 4278 int i; 4279 4280 /* Do we have hotpluggable memory? */ 4281 if (MACHINE(spapr)->maxram_size > ram_top) { 4282 /* Can't just use maxram_size, because there may be an 4283 * alignment gap between normal and hotpluggable memory 4284 * regions */ 4285 ram_top = spapr->hotplug_memory.base + 4286 memory_region_size(&spapr->hotplug_memory.mr); 4287 } 4288 4289 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4290 4291 if (index > max_index) { 4292 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4293 max_index); 4294 return; 4295 } 4296 4297 *buid = base_buid + index; 4298 for (i = 0; i < n_dma; ++i) { 4299 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4300 } 4301 4302 phb_base = phb0_base + index * phb_spacing; 4303 *pio = phb_base + pio_offset; 4304 *mmio32 = phb_base + mmio_offset; 4305 /* 4306 * We don't set the 64-bit MMIO window, relying on the PHB's 4307 * fallback behaviour of automatically splitting a large "32-bit" 4308 * window into contiguous 32-bit and 64-bit windows 4309 */ 4310 } 4311 4312 static void spapr_machine_2_7_instance_options(MachineState *machine) 4313 { 4314 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 4315 4316 spapr_machine_2_8_instance_options(machine); 4317 spapr->use_hotplug_event_source = false; 4318 } 4319 4320 static void spapr_machine_2_7_class_options(MachineClass *mc) 4321 { 4322 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4323 4324 spapr_machine_2_8_class_options(mc); 4325 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4326 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 4327 smc->phb_placement = phb_placement_2_7; 4328 } 4329 4330 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4331 4332 /* 4333 * pseries-2.6 4334 */ 4335 #define SPAPR_COMPAT_2_6 \ 4336 HW_COMPAT_2_6 \ 4337 { \ 4338 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 4339 .property = "ddw",\ 4340 .value = stringify(off),\ 4341 }, 4342 4343 static void spapr_machine_2_6_instance_options(MachineState *machine) 4344 { 4345 spapr_machine_2_7_instance_options(machine); 4346 } 4347 4348 static void spapr_machine_2_6_class_options(MachineClass *mc) 4349 { 4350 spapr_machine_2_7_class_options(mc); 4351 mc->has_hotpluggable_cpus = false; 4352 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 4353 } 4354 4355 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4356 4357 /* 4358 * pseries-2.5 4359 */ 4360 #define SPAPR_COMPAT_2_5 \ 4361 HW_COMPAT_2_5 \ 4362 { \ 4363 .driver = "spapr-vlan", \ 4364 .property = "use-rx-buffer-pools", \ 4365 .value = "off", \ 4366 }, 4367 4368 static void spapr_machine_2_5_instance_options(MachineState *machine) 4369 { 4370 spapr_machine_2_6_instance_options(machine); 4371 } 4372 4373 static void spapr_machine_2_5_class_options(MachineClass *mc) 4374 { 4375 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4376 4377 spapr_machine_2_6_class_options(mc); 4378 smc->use_ohci_by_default = true; 4379 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 4380 } 4381 4382 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4383 4384 /* 4385 * pseries-2.4 4386 */ 4387 #define SPAPR_COMPAT_2_4 \ 4388 HW_COMPAT_2_4 4389 4390 static void spapr_machine_2_4_instance_options(MachineState *machine) 4391 { 4392 spapr_machine_2_5_instance_options(machine); 4393 } 4394 4395 static void spapr_machine_2_4_class_options(MachineClass *mc) 4396 { 4397 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4398 4399 spapr_machine_2_5_class_options(mc); 4400 smc->dr_lmb_enabled = false; 4401 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 4402 } 4403 4404 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4405 4406 /* 4407 * pseries-2.3 4408 */ 4409 #define SPAPR_COMPAT_2_3 \ 4410 HW_COMPAT_2_3 \ 4411 {\ 4412 .driver = "spapr-pci-host-bridge",\ 4413 .property = "dynamic-reconfiguration",\ 4414 .value = "off",\ 4415 }, 4416 4417 static void spapr_machine_2_3_instance_options(MachineState *machine) 4418 { 4419 spapr_machine_2_4_instance_options(machine); 4420 } 4421 4422 static void spapr_machine_2_3_class_options(MachineClass *mc) 4423 { 4424 spapr_machine_2_4_class_options(mc); 4425 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 4426 } 4427 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4428 4429 /* 4430 * pseries-2.2 4431 */ 4432 4433 #define SPAPR_COMPAT_2_2 \ 4434 HW_COMPAT_2_2 \ 4435 {\ 4436 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 4437 .property = "mem_win_size",\ 4438 .value = "0x20000000",\ 4439 }, 4440 4441 static void spapr_machine_2_2_instance_options(MachineState *machine) 4442 { 4443 spapr_machine_2_3_instance_options(machine); 4444 machine->suppress_vmdesc = true; 4445 } 4446 4447 static void spapr_machine_2_2_class_options(MachineClass *mc) 4448 { 4449 spapr_machine_2_3_class_options(mc); 4450 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 4451 } 4452 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4453 4454 /* 4455 * pseries-2.1 4456 */ 4457 #define SPAPR_COMPAT_2_1 \ 4458 HW_COMPAT_2_1 4459 4460 static void spapr_machine_2_1_instance_options(MachineState *machine) 4461 { 4462 spapr_machine_2_2_instance_options(machine); 4463 } 4464 4465 static void spapr_machine_2_1_class_options(MachineClass *mc) 4466 { 4467 spapr_machine_2_2_class_options(mc); 4468 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 4469 } 4470 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4471 4472 static void spapr_machine_register_types(void) 4473 { 4474 type_register_static(&spapr_machine_info); 4475 } 4476 4477 type_init(spapr_machine_register_types) 4478