1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qemu/datadir.h" 30 #include "qapi/error.h" 31 #include "qapi/qapi-events-machine.h" 32 #include "qapi/visitor.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/hostmem.h" 35 #include "sysemu/numa.h" 36 #include "sysemu/qtest.h" 37 #include "sysemu/reset.h" 38 #include "sysemu/runstate.h" 39 #include "qemu/log.h" 40 #include "hw/fw-path-provider.h" 41 #include "elf.h" 42 #include "net/net.h" 43 #include "sysemu/device_tree.h" 44 #include "sysemu/cpus.h" 45 #include "sysemu/hw_accel.h" 46 #include "kvm_ppc.h" 47 #include "migration/misc.h" 48 #include "migration/qemu-file-types.h" 49 #include "migration/global_state.h" 50 #include "migration/register.h" 51 #include "migration/blocker.h" 52 #include "mmu-hash64.h" 53 #include "mmu-book3s-v3.h" 54 #include "cpu-models.h" 55 #include "hw/core/cpu.h" 56 57 #include "hw/ppc/ppc.h" 58 #include "hw/loader.h" 59 60 #include "hw/ppc/fdt.h" 61 #include "hw/ppc/spapr.h" 62 #include "hw/ppc/spapr_vio.h" 63 #include "hw/qdev-properties.h" 64 #include "hw/pci-host/spapr.h" 65 #include "hw/pci/msi.h" 66 67 #include "hw/pci/pci.h" 68 #include "hw/scsi/scsi.h" 69 #include "hw/virtio/virtio-scsi.h" 70 #include "hw/virtio/vhost-scsi-common.h" 71 72 #include "exec/ram_addr.h" 73 #include "hw/usb.h" 74 #include "qemu/config-file.h" 75 #include "qemu/error-report.h" 76 #include "trace.h" 77 #include "hw/nmi.h" 78 #include "hw/intc/intc.h" 79 80 #include "hw/ppc/spapr_cpu_core.h" 81 #include "hw/mem/memory-device.h" 82 #include "hw/ppc/spapr_tpm_proxy.h" 83 #include "hw/ppc/spapr_nvdimm.h" 84 #include "hw/ppc/spapr_numa.h" 85 #include "hw/ppc/pef.h" 86 87 #include "monitor/monitor.h" 88 89 #include <libfdt.h> 90 91 /* SLOF memory layout: 92 * 93 * SLOF raw image loaded at 0, copies its romfs right below the flat 94 * device-tree, then position SLOF itself 31M below that 95 * 96 * So we set FW_OVERHEAD to 40MB which should account for all of that 97 * and more 98 * 99 * We load our kernel at 4M, leaving space for SLOF initial image 100 */ 101 #define FDT_MAX_ADDR 0x80000000 /* FDT must stay below that */ 102 #define FW_MAX_SIZE 0x400000 103 #define FW_FILE_NAME "slof.bin" 104 #define FW_OVERHEAD 0x2800000 105 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 106 107 #define MIN_RMA_SLOF (128 * MiB) 108 109 #define PHANDLE_INTC 0x00001111 110 111 /* These two functions implement the VCPU id numbering: one to compute them 112 * all and one to identify thread 0 of a VCORE. Any change to the first one 113 * is likely to have an impact on the second one, so let's keep them close. 114 */ 115 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 116 { 117 MachineState *ms = MACHINE(spapr); 118 unsigned int smp_threads = ms->smp.threads; 119 120 assert(spapr->vsmt); 121 return 122 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 123 } 124 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 125 PowerPCCPU *cpu) 126 { 127 assert(spapr->vsmt); 128 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 129 } 130 131 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 132 { 133 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 134 * and newer QEMUs don't even have them. In both cases, we don't want 135 * to send anything on the wire. 136 */ 137 return false; 138 } 139 140 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 141 .name = "icp/server", 142 .version_id = 1, 143 .minimum_version_id = 1, 144 .needed = pre_2_10_vmstate_dummy_icp_needed, 145 .fields = (VMStateField[]) { 146 VMSTATE_UNUSED(4), /* uint32_t xirr */ 147 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 148 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 149 VMSTATE_END_OF_LIST() 150 }, 151 }; 152 153 static void pre_2_10_vmstate_register_dummy_icp(int i) 154 { 155 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 156 (void *)(uintptr_t) i); 157 } 158 159 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 160 { 161 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 162 (void *)(uintptr_t) i); 163 } 164 165 int spapr_max_server_number(SpaprMachineState *spapr) 166 { 167 MachineState *ms = MACHINE(spapr); 168 169 assert(spapr->vsmt); 170 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 171 } 172 173 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 174 int smt_threads) 175 { 176 int i, ret = 0; 177 uint32_t servers_prop[smt_threads]; 178 uint32_t gservers_prop[smt_threads * 2]; 179 int index = spapr_get_vcpu_id(cpu); 180 181 if (cpu->compat_pvr) { 182 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 183 if (ret < 0) { 184 return ret; 185 } 186 } 187 188 /* Build interrupt servers and gservers properties */ 189 for (i = 0; i < smt_threads; i++) { 190 servers_prop[i] = cpu_to_be32(index + i); 191 /* Hack, direct the group queues back to cpu 0 */ 192 gservers_prop[i*2] = cpu_to_be32(index + i); 193 gservers_prop[i*2 + 1] = 0; 194 } 195 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 196 servers_prop, sizeof(servers_prop)); 197 if (ret < 0) { 198 return ret; 199 } 200 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 201 gservers_prop, sizeof(gservers_prop)); 202 203 return ret; 204 } 205 206 static void spapr_dt_pa_features(SpaprMachineState *spapr, 207 PowerPCCPU *cpu, 208 void *fdt, int offset) 209 { 210 uint8_t pa_features_206[] = { 6, 0, 211 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 212 uint8_t pa_features_207[] = { 24, 0, 213 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 214 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 215 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 216 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 217 uint8_t pa_features_300[] = { 66, 0, 218 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 219 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 220 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 221 /* 6: DS207 */ 222 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 223 /* 16: Vector */ 224 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 225 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 226 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 227 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 228 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 229 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 230 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 231 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 232 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 233 /* 42: PM, 44: PC RA, 46: SC vec'd */ 234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 235 /* 48: SIMD, 50: QP BFP, 52: String */ 236 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 237 /* 54: DecFP, 56: DecI, 58: SHA */ 238 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 239 /* 60: NM atomic, 62: RNG */ 240 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 241 }; 242 uint8_t *pa_features = NULL; 243 size_t pa_size; 244 245 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 246 pa_features = pa_features_206; 247 pa_size = sizeof(pa_features_206); 248 } 249 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 250 pa_features = pa_features_207; 251 pa_size = sizeof(pa_features_207); 252 } 253 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 254 pa_features = pa_features_300; 255 pa_size = sizeof(pa_features_300); 256 } 257 if (!pa_features) { 258 return; 259 } 260 261 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 262 /* 263 * Note: we keep CI large pages off by default because a 64K capable 264 * guest provisioned with large pages might otherwise try to map a qemu 265 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 266 * even if that qemu runs on a 4k host. 267 * We dd this bit back here if we are confident this is not an issue 268 */ 269 pa_features[3] |= 0x20; 270 } 271 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 272 pa_features[24] |= 0x80; /* Transactional memory support */ 273 } 274 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 275 /* Workaround for broken kernels that attempt (guest) radix 276 * mode when they can't handle it, if they see the radix bit set 277 * in pa-features. So hide it from them. */ 278 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 279 } 280 281 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 282 } 283 284 static hwaddr spapr_node0_size(MachineState *machine) 285 { 286 if (machine->numa_state->num_nodes) { 287 int i; 288 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 289 if (machine->numa_state->nodes[i].node_mem) { 290 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 291 machine->ram_size); 292 } 293 } 294 } 295 return machine->ram_size; 296 } 297 298 static void add_str(GString *s, const gchar *s1) 299 { 300 g_string_append_len(s, s1, strlen(s1) + 1); 301 } 302 303 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 304 hwaddr start, hwaddr size) 305 { 306 char mem_name[32]; 307 uint64_t mem_reg_property[2]; 308 int off; 309 310 mem_reg_property[0] = cpu_to_be64(start); 311 mem_reg_property[1] = cpu_to_be64(size); 312 313 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 314 off = fdt_add_subnode(fdt, 0, mem_name); 315 _FDT(off); 316 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 317 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 318 sizeof(mem_reg_property)))); 319 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 320 return off; 321 } 322 323 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 324 { 325 MemoryDeviceInfoList *info; 326 327 for (info = list; info; info = info->next) { 328 MemoryDeviceInfo *value = info->value; 329 330 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 331 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 332 333 if (addr >= pcdimm_info->addr && 334 addr < (pcdimm_info->addr + pcdimm_info->size)) { 335 return pcdimm_info->node; 336 } 337 } 338 } 339 340 return -1; 341 } 342 343 struct sPAPRDrconfCellV2 { 344 uint32_t seq_lmbs; 345 uint64_t base_addr; 346 uint32_t drc_index; 347 uint32_t aa_index; 348 uint32_t flags; 349 } QEMU_PACKED; 350 351 typedef struct DrconfCellQueue { 352 struct sPAPRDrconfCellV2 cell; 353 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 354 } DrconfCellQueue; 355 356 static DrconfCellQueue * 357 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 358 uint32_t drc_index, uint32_t aa_index, 359 uint32_t flags) 360 { 361 DrconfCellQueue *elem; 362 363 elem = g_malloc0(sizeof(*elem)); 364 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 365 elem->cell.base_addr = cpu_to_be64(base_addr); 366 elem->cell.drc_index = cpu_to_be32(drc_index); 367 elem->cell.aa_index = cpu_to_be32(aa_index); 368 elem->cell.flags = cpu_to_be32(flags); 369 370 return elem; 371 } 372 373 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 374 int offset, MemoryDeviceInfoList *dimms) 375 { 376 MachineState *machine = MACHINE(spapr); 377 uint8_t *int_buf, *cur_index; 378 int ret; 379 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 380 uint64_t addr, cur_addr, size; 381 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 382 uint64_t mem_end = machine->device_memory->base + 383 memory_region_size(&machine->device_memory->mr); 384 uint32_t node, buf_len, nr_entries = 0; 385 SpaprDrc *drc; 386 DrconfCellQueue *elem, *next; 387 MemoryDeviceInfoList *info; 388 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 389 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 390 391 /* Entry to cover RAM and the gap area */ 392 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 393 SPAPR_LMB_FLAGS_RESERVED | 394 SPAPR_LMB_FLAGS_DRC_INVALID); 395 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 396 nr_entries++; 397 398 cur_addr = machine->device_memory->base; 399 for (info = dimms; info; info = info->next) { 400 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 401 402 addr = di->addr; 403 size = di->size; 404 node = di->node; 405 406 /* 407 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 408 * area is marked hotpluggable in the next iteration for the bigger 409 * chunk including the NVDIMM occupied area. 410 */ 411 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 412 continue; 413 414 /* Entry for hot-pluggable area */ 415 if (cur_addr < addr) { 416 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 417 g_assert(drc); 418 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 419 cur_addr, spapr_drc_index(drc), -1, 0); 420 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 421 nr_entries++; 422 } 423 424 /* Entry for DIMM */ 425 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 426 g_assert(drc); 427 elem = spapr_get_drconf_cell(size / lmb_size, addr, 428 spapr_drc_index(drc), node, 429 (SPAPR_LMB_FLAGS_ASSIGNED | 430 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 431 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 432 nr_entries++; 433 cur_addr = addr + size; 434 } 435 436 /* Entry for remaining hotpluggable area */ 437 if (cur_addr < mem_end) { 438 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 439 g_assert(drc); 440 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 441 cur_addr, spapr_drc_index(drc), -1, 0); 442 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 443 nr_entries++; 444 } 445 446 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 447 int_buf = cur_index = g_malloc0(buf_len); 448 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 449 cur_index += sizeof(nr_entries); 450 451 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 452 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 453 cur_index += sizeof(elem->cell); 454 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 455 g_free(elem); 456 } 457 458 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 459 g_free(int_buf); 460 if (ret < 0) { 461 return -1; 462 } 463 return 0; 464 } 465 466 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 467 int offset, MemoryDeviceInfoList *dimms) 468 { 469 MachineState *machine = MACHINE(spapr); 470 int i, ret; 471 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 472 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 473 uint32_t nr_lmbs = (machine->device_memory->base + 474 memory_region_size(&machine->device_memory->mr)) / 475 lmb_size; 476 uint32_t *int_buf, *cur_index, buf_len; 477 478 /* 479 * Allocate enough buffer size to fit in ibm,dynamic-memory 480 */ 481 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 482 cur_index = int_buf = g_malloc0(buf_len); 483 int_buf[0] = cpu_to_be32(nr_lmbs); 484 cur_index++; 485 for (i = 0; i < nr_lmbs; i++) { 486 uint64_t addr = i * lmb_size; 487 uint32_t *dynamic_memory = cur_index; 488 489 if (i >= device_lmb_start) { 490 SpaprDrc *drc; 491 492 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 493 g_assert(drc); 494 495 dynamic_memory[0] = cpu_to_be32(addr >> 32); 496 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 497 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 498 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 499 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 500 if (memory_region_present(get_system_memory(), addr)) { 501 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 502 } else { 503 dynamic_memory[5] = cpu_to_be32(0); 504 } 505 } else { 506 /* 507 * LMB information for RMA, boot time RAM and gap b/n RAM and 508 * device memory region -- all these are marked as reserved 509 * and as having no valid DRC. 510 */ 511 dynamic_memory[0] = cpu_to_be32(addr >> 32); 512 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 513 dynamic_memory[2] = cpu_to_be32(0); 514 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 515 dynamic_memory[4] = cpu_to_be32(-1); 516 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 517 SPAPR_LMB_FLAGS_DRC_INVALID); 518 } 519 520 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 521 } 522 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 523 g_free(int_buf); 524 if (ret < 0) { 525 return -1; 526 } 527 return 0; 528 } 529 530 /* 531 * Adds ibm,dynamic-reconfiguration-memory node. 532 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 533 * of this device tree node. 534 */ 535 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 536 void *fdt) 537 { 538 MachineState *machine = MACHINE(spapr); 539 int ret, offset; 540 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 541 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 542 cpu_to_be32(lmb_size & 0xffffffff)}; 543 MemoryDeviceInfoList *dimms = NULL; 544 545 /* 546 * Don't create the node if there is no device memory 547 */ 548 if (machine->ram_size == machine->maxram_size) { 549 return 0; 550 } 551 552 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 553 554 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 555 sizeof(prop_lmb_size)); 556 if (ret < 0) { 557 return ret; 558 } 559 560 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 561 if (ret < 0) { 562 return ret; 563 } 564 565 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 566 if (ret < 0) { 567 return ret; 568 } 569 570 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 571 dimms = qmp_memory_device_list(); 572 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 573 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 574 } else { 575 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 576 } 577 qapi_free_MemoryDeviceInfoList(dimms); 578 579 if (ret < 0) { 580 return ret; 581 } 582 583 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 584 585 return ret; 586 } 587 588 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 589 { 590 MachineState *machine = MACHINE(spapr); 591 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 592 hwaddr mem_start, node_size; 593 int i, nb_nodes = machine->numa_state->num_nodes; 594 NodeInfo *nodes = machine->numa_state->nodes; 595 596 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 597 if (!nodes[i].node_mem) { 598 continue; 599 } 600 if (mem_start >= machine->ram_size) { 601 node_size = 0; 602 } else { 603 node_size = nodes[i].node_mem; 604 if (node_size > machine->ram_size - mem_start) { 605 node_size = machine->ram_size - mem_start; 606 } 607 } 608 if (!mem_start) { 609 /* spapr_machine_init() checks for rma_size <= node0_size 610 * already */ 611 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 612 mem_start += spapr->rma_size; 613 node_size -= spapr->rma_size; 614 } 615 for ( ; node_size; ) { 616 hwaddr sizetmp = pow2floor(node_size); 617 618 /* mem_start != 0 here */ 619 if (ctzl(mem_start) < ctzl(sizetmp)) { 620 sizetmp = 1ULL << ctzl(mem_start); 621 } 622 623 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 624 node_size -= sizetmp; 625 mem_start += sizetmp; 626 } 627 } 628 629 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 630 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 631 int ret; 632 633 g_assert(smc->dr_lmb_enabled); 634 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 635 if (ret) { 636 return ret; 637 } 638 } 639 640 return 0; 641 } 642 643 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 644 SpaprMachineState *spapr) 645 { 646 MachineState *ms = MACHINE(spapr); 647 PowerPCCPU *cpu = POWERPC_CPU(cs); 648 CPUPPCState *env = &cpu->env; 649 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 650 int index = spapr_get_vcpu_id(cpu); 651 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 652 0xffffffff, 0xffffffff}; 653 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 654 : SPAPR_TIMEBASE_FREQ; 655 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 656 uint32_t page_sizes_prop[64]; 657 size_t page_sizes_prop_size; 658 unsigned int smp_threads = ms->smp.threads; 659 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 660 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 661 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 662 SpaprDrc *drc; 663 int drc_index; 664 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 665 int i; 666 667 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 668 if (drc) { 669 drc_index = spapr_drc_index(drc); 670 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 671 } 672 673 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 674 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 675 676 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 677 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 678 env->dcache_line_size))); 679 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 680 env->dcache_line_size))); 681 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 682 env->icache_line_size))); 683 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 684 env->icache_line_size))); 685 686 if (pcc->l1_dcache_size) { 687 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 688 pcc->l1_dcache_size))); 689 } else { 690 warn_report("Unknown L1 dcache size for cpu"); 691 } 692 if (pcc->l1_icache_size) { 693 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 694 pcc->l1_icache_size))); 695 } else { 696 warn_report("Unknown L1 icache size for cpu"); 697 } 698 699 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 700 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 701 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 702 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 703 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 704 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 705 706 if (ppc_has_spr(cpu, SPR_PURR)) { 707 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 708 } 709 if (ppc_has_spr(cpu, SPR_PURR)) { 710 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 711 } 712 713 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 714 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 715 segs, sizeof(segs)))); 716 } 717 718 /* Advertise VSX (vector extensions) if available 719 * 1 == VMX / Altivec available 720 * 2 == VSX available 721 * 722 * Only CPUs for which we create core types in spapr_cpu_core.c 723 * are possible, and all of those have VMX */ 724 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 725 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 726 } else { 727 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 728 } 729 730 /* Advertise DFP (Decimal Floating Point) if available 731 * 0 / no property == no DFP 732 * 1 == DFP available */ 733 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 734 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 735 } 736 737 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 738 sizeof(page_sizes_prop)); 739 if (page_sizes_prop_size) { 740 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 741 page_sizes_prop, page_sizes_prop_size))); 742 } 743 744 spapr_dt_pa_features(spapr, cpu, fdt, offset); 745 746 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 747 cs->cpu_index / vcpus_per_socket))); 748 749 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 750 pft_size_prop, sizeof(pft_size_prop)))); 751 752 if (ms->numa_state->num_nodes > 1) { 753 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 754 } 755 756 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 757 758 if (pcc->radix_page_info) { 759 for (i = 0; i < pcc->radix_page_info->count; i++) { 760 radix_AP_encodings[i] = 761 cpu_to_be32(pcc->radix_page_info->entries[i]); 762 } 763 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 764 radix_AP_encodings, 765 pcc->radix_page_info->count * 766 sizeof(radix_AP_encodings[0])))); 767 } 768 769 /* 770 * We set this property to let the guest know that it can use the large 771 * decrementer and its width in bits. 772 */ 773 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 774 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 775 pcc->lrg_decr_bits))); 776 } 777 778 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 779 { 780 CPUState **rev; 781 CPUState *cs; 782 int n_cpus; 783 int cpus_offset; 784 int i; 785 786 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 787 _FDT(cpus_offset); 788 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 789 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 790 791 /* 792 * We walk the CPUs in reverse order to ensure that CPU DT nodes 793 * created by fdt_add_subnode() end up in the right order in FDT 794 * for the guest kernel the enumerate the CPUs correctly. 795 * 796 * The CPU list cannot be traversed in reverse order, so we need 797 * to do extra work. 798 */ 799 n_cpus = 0; 800 rev = NULL; 801 CPU_FOREACH(cs) { 802 rev = g_renew(CPUState *, rev, n_cpus + 1); 803 rev[n_cpus++] = cs; 804 } 805 806 for (i = n_cpus - 1; i >= 0; i--) { 807 CPUState *cs = rev[i]; 808 PowerPCCPU *cpu = POWERPC_CPU(cs); 809 int index = spapr_get_vcpu_id(cpu); 810 DeviceClass *dc = DEVICE_GET_CLASS(cs); 811 g_autofree char *nodename = NULL; 812 int offset; 813 814 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 815 continue; 816 } 817 818 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 819 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 820 _FDT(offset); 821 spapr_dt_cpu(cs, fdt, offset, spapr); 822 } 823 824 g_free(rev); 825 } 826 827 static int spapr_dt_rng(void *fdt) 828 { 829 int node; 830 int ret; 831 832 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 833 if (node <= 0) { 834 return -1; 835 } 836 ret = fdt_setprop_string(fdt, node, "device_type", 837 "ibm,platform-facilities"); 838 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 839 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 840 841 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 842 if (node <= 0) { 843 return -1; 844 } 845 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 846 847 return ret ? -1 : 0; 848 } 849 850 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 851 { 852 MachineState *ms = MACHINE(spapr); 853 int rtas; 854 GString *hypertas = g_string_sized_new(256); 855 GString *qemu_hypertas = g_string_sized_new(256); 856 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 857 memory_region_size(&MACHINE(spapr)->device_memory->mr); 858 uint32_t lrdr_capacity[] = { 859 cpu_to_be32(max_device_addr >> 32), 860 cpu_to_be32(max_device_addr & 0xffffffff), 861 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 862 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 863 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 864 }; 865 866 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 867 868 /* hypertas */ 869 add_str(hypertas, "hcall-pft"); 870 add_str(hypertas, "hcall-term"); 871 add_str(hypertas, "hcall-dabr"); 872 add_str(hypertas, "hcall-interrupt"); 873 add_str(hypertas, "hcall-tce"); 874 add_str(hypertas, "hcall-vio"); 875 add_str(hypertas, "hcall-splpar"); 876 add_str(hypertas, "hcall-join"); 877 add_str(hypertas, "hcall-bulk"); 878 add_str(hypertas, "hcall-set-mode"); 879 add_str(hypertas, "hcall-sprg0"); 880 add_str(hypertas, "hcall-copy"); 881 add_str(hypertas, "hcall-debug"); 882 add_str(hypertas, "hcall-vphn"); 883 add_str(qemu_hypertas, "hcall-memop1"); 884 885 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 886 add_str(hypertas, "hcall-multi-tce"); 887 } 888 889 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 890 add_str(hypertas, "hcall-hpt-resize"); 891 } 892 893 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 894 hypertas->str, hypertas->len)); 895 g_string_free(hypertas, TRUE); 896 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 897 qemu_hypertas->str, qemu_hypertas->len)); 898 g_string_free(qemu_hypertas, TRUE); 899 900 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 901 902 /* 903 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 904 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 905 * 906 * The system reset requirements are driven by existing Linux and PowerVM 907 * implementation which (contrary to PAPR) saves r3 in the error log 908 * structure like machine check, so Linux expects to find the saved r3 909 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 910 * does not look at the error value). 911 * 912 * System reset interrupts are not subject to interlock like machine 913 * check, so this memory area could be corrupted if the sreset is 914 * interrupted by a machine check (or vice versa) if it was shared. To 915 * prevent this, system reset uses per-CPU areas for the sreset save 916 * area. A system reset that interrupts a system reset handler could 917 * still overwrite this area, but Linux doesn't try to recover in that 918 * case anyway. 919 * 920 * The extra 8 bytes is required because Linux's FWNMI error log check 921 * is off-by-one. 922 * 923 * RTAS_MIN_SIZE is required for the RTAS blob itself. 924 */ 925 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_MIN_SIZE + 926 RTAS_ERROR_LOG_MAX + 927 ms->smp.max_cpus * sizeof(uint64_t) * 2 + 928 sizeof(uint64_t))); 929 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 930 RTAS_ERROR_LOG_MAX)); 931 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 932 RTAS_EVENT_SCAN_RATE)); 933 934 g_assert(msi_nonbroken); 935 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 936 937 /* 938 * According to PAPR, rtas ibm,os-term does not guarantee a return 939 * back to the guest cpu. 940 * 941 * While an additional ibm,extended-os-term property indicates 942 * that rtas call return will always occur. Set this property. 943 */ 944 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 945 946 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 947 lrdr_capacity, sizeof(lrdr_capacity))); 948 949 spapr_dt_rtas_tokens(fdt, rtas); 950 } 951 952 /* 953 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 954 * and the XIVE features that the guest may request and thus the valid 955 * values for bytes 23..26 of option vector 5: 956 */ 957 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 958 int chosen) 959 { 960 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 961 962 char val[2 * 4] = { 963 23, 0x00, /* XICS / XIVE mode */ 964 24, 0x00, /* Hash/Radix, filled in below. */ 965 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 966 26, 0x40, /* Radix options: GTSE == yes. */ 967 }; 968 969 if (spapr->irq->xics && spapr->irq->xive) { 970 val[1] = SPAPR_OV5_XIVE_BOTH; 971 } else if (spapr->irq->xive) { 972 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 973 } else { 974 assert(spapr->irq->xics); 975 val[1] = SPAPR_OV5_XIVE_LEGACY; 976 } 977 978 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 979 first_ppc_cpu->compat_pvr)) { 980 /* 981 * If we're in a pre POWER9 compat mode then the guest should 982 * do hash and use the legacy interrupt mode 983 */ 984 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 985 val[3] = 0x00; /* Hash */ 986 spapr_check_mmu_mode(false); 987 } else if (kvm_enabled()) { 988 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 989 val[3] = 0x80; /* OV5_MMU_BOTH */ 990 } else if (kvmppc_has_cap_mmu_radix()) { 991 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 992 } else { 993 val[3] = 0x00; /* Hash */ 994 } 995 } else { 996 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 997 val[3] = 0xC0; 998 } 999 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1000 val, sizeof(val))); 1001 } 1002 1003 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1004 { 1005 MachineState *machine = MACHINE(spapr); 1006 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1007 int chosen; 1008 1009 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1010 1011 if (reset) { 1012 const char *boot_device = spapr->boot_device; 1013 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1014 size_t cb = 0; 1015 char *bootlist = get_boot_devices_list(&cb); 1016 1017 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1018 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1019 machine->kernel_cmdline)); 1020 } 1021 1022 if (spapr->initrd_size) { 1023 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1024 spapr->initrd_base)); 1025 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1026 spapr->initrd_base + spapr->initrd_size)); 1027 } 1028 1029 if (spapr->kernel_size) { 1030 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1031 cpu_to_be64(spapr->kernel_size) }; 1032 1033 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1034 &kprop, sizeof(kprop))); 1035 if (spapr->kernel_le) { 1036 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1037 } 1038 } 1039 if (boot_menu) { 1040 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1041 } 1042 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1043 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1044 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1045 1046 if (cb && bootlist) { 1047 int i; 1048 1049 for (i = 0; i < cb; i++) { 1050 if (bootlist[i] == '\n') { 1051 bootlist[i] = ' '; 1052 } 1053 } 1054 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1055 } 1056 1057 if (boot_device && strlen(boot_device)) { 1058 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1059 } 1060 1061 if (!spapr->has_graphics && stdout_path) { 1062 /* 1063 * "linux,stdout-path" and "stdout" properties are 1064 * deprecated by linux kernel. New platforms should only 1065 * use the "stdout-path" property. Set the new property 1066 * and continue using older property to remain compatible 1067 * with the existing firmware. 1068 */ 1069 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1070 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1071 } 1072 1073 /* 1074 * We can deal with BAR reallocation just fine, advertise it 1075 * to the guest 1076 */ 1077 if (smc->linux_pci_probe) { 1078 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1079 } 1080 1081 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1082 1083 g_free(stdout_path); 1084 g_free(bootlist); 1085 } 1086 1087 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1088 } 1089 1090 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1091 { 1092 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1093 * KVM to work under pHyp with some guest co-operation */ 1094 int hypervisor; 1095 uint8_t hypercall[16]; 1096 1097 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1098 /* indicate KVM hypercall interface */ 1099 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1100 if (kvmppc_has_cap_fixup_hcalls()) { 1101 /* 1102 * Older KVM versions with older guest kernels were broken 1103 * with the magic page, don't allow the guest to map it. 1104 */ 1105 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1106 sizeof(hypercall))) { 1107 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1108 hypercall, sizeof(hypercall))); 1109 } 1110 } 1111 } 1112 1113 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1114 { 1115 MachineState *machine = MACHINE(spapr); 1116 MachineClass *mc = MACHINE_GET_CLASS(machine); 1117 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1118 uint32_t root_drc_type_mask = 0; 1119 int ret; 1120 void *fdt; 1121 SpaprPhbState *phb; 1122 char *buf; 1123 1124 fdt = g_malloc0(space); 1125 _FDT((fdt_create_empty_tree(fdt, space))); 1126 1127 /* Root node */ 1128 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1129 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1130 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1131 1132 /* Guest UUID & Name*/ 1133 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1134 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1135 if (qemu_uuid_set) { 1136 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1137 } 1138 g_free(buf); 1139 1140 if (qemu_get_vm_name()) { 1141 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1142 qemu_get_vm_name())); 1143 } 1144 1145 /* Host Model & Serial Number */ 1146 if (spapr->host_model) { 1147 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1148 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1149 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1150 g_free(buf); 1151 } 1152 1153 if (spapr->host_serial) { 1154 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1155 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1156 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1157 g_free(buf); 1158 } 1159 1160 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1161 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1162 1163 /* /interrupt controller */ 1164 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1165 1166 ret = spapr_dt_memory(spapr, fdt); 1167 if (ret < 0) { 1168 error_report("couldn't setup memory nodes in fdt"); 1169 exit(1); 1170 } 1171 1172 /* /vdevice */ 1173 spapr_dt_vdevice(spapr->vio_bus, fdt); 1174 1175 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1176 ret = spapr_dt_rng(fdt); 1177 if (ret < 0) { 1178 error_report("could not set up rng device in the fdt"); 1179 exit(1); 1180 } 1181 } 1182 1183 QLIST_FOREACH(phb, &spapr->phbs, list) { 1184 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1185 if (ret < 0) { 1186 error_report("couldn't setup PCI devices in fdt"); 1187 exit(1); 1188 } 1189 } 1190 1191 spapr_dt_cpus(fdt, spapr); 1192 1193 /* ibm,drc-indexes and friends */ 1194 if (smc->dr_lmb_enabled) { 1195 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; 1196 } 1197 if (smc->dr_phb_enabled) { 1198 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; 1199 } 1200 if (mc->nvdimm_supported) { 1201 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM; 1202 } 1203 if (root_drc_type_mask) { 1204 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask)); 1205 } 1206 1207 if (mc->has_hotpluggable_cpus) { 1208 int offset = fdt_path_offset(fdt, "/cpus"); 1209 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1210 if (ret < 0) { 1211 error_report("Couldn't set up CPU DR device tree properties"); 1212 exit(1); 1213 } 1214 } 1215 1216 /* /event-sources */ 1217 spapr_dt_events(spapr, fdt); 1218 1219 /* /rtas */ 1220 spapr_dt_rtas(spapr, fdt); 1221 1222 /* /chosen */ 1223 spapr_dt_chosen(spapr, fdt, reset); 1224 1225 /* /hypervisor */ 1226 if (kvm_enabled()) { 1227 spapr_dt_hypervisor(spapr, fdt); 1228 } 1229 1230 /* Build memory reserve map */ 1231 if (reset) { 1232 if (spapr->kernel_size) { 1233 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1234 spapr->kernel_size))); 1235 } 1236 if (spapr->initrd_size) { 1237 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1238 spapr->initrd_size))); 1239 } 1240 } 1241 1242 /* NVDIMM devices */ 1243 if (mc->nvdimm_supported) { 1244 spapr_dt_persistent_memory(spapr, fdt); 1245 } 1246 1247 return fdt; 1248 } 1249 1250 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1251 { 1252 SpaprMachineState *spapr = opaque; 1253 1254 return (addr & 0x0fffffff) + spapr->kernel_addr; 1255 } 1256 1257 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1258 PowerPCCPU *cpu) 1259 { 1260 CPUPPCState *env = &cpu->env; 1261 1262 /* The TCG path should also be holding the BQL at this point */ 1263 g_assert(qemu_mutex_iothread_locked()); 1264 1265 if (msr_pr) { 1266 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1267 env->gpr[3] = H_PRIVILEGE; 1268 } else { 1269 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1270 } 1271 } 1272 1273 struct LPCRSyncState { 1274 target_ulong value; 1275 target_ulong mask; 1276 }; 1277 1278 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1279 { 1280 struct LPCRSyncState *s = arg.host_ptr; 1281 PowerPCCPU *cpu = POWERPC_CPU(cs); 1282 CPUPPCState *env = &cpu->env; 1283 target_ulong lpcr; 1284 1285 cpu_synchronize_state(cs); 1286 lpcr = env->spr[SPR_LPCR]; 1287 lpcr &= ~s->mask; 1288 lpcr |= s->value; 1289 ppc_store_lpcr(cpu, lpcr); 1290 } 1291 1292 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1293 { 1294 CPUState *cs; 1295 struct LPCRSyncState s = { 1296 .value = value, 1297 .mask = mask 1298 }; 1299 CPU_FOREACH(cs) { 1300 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1301 } 1302 } 1303 1304 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1305 { 1306 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1307 1308 /* Copy PATE1:GR into PATE0:HR */ 1309 entry->dw0 = spapr->patb_entry & PATE0_HR; 1310 entry->dw1 = spapr->patb_entry; 1311 } 1312 1313 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1314 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1315 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1316 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1317 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1318 1319 /* 1320 * Get the fd to access the kernel htab, re-opening it if necessary 1321 */ 1322 static int get_htab_fd(SpaprMachineState *spapr) 1323 { 1324 Error *local_err = NULL; 1325 1326 if (spapr->htab_fd >= 0) { 1327 return spapr->htab_fd; 1328 } 1329 1330 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1331 if (spapr->htab_fd < 0) { 1332 error_report_err(local_err); 1333 } 1334 1335 return spapr->htab_fd; 1336 } 1337 1338 void close_htab_fd(SpaprMachineState *spapr) 1339 { 1340 if (spapr->htab_fd >= 0) { 1341 close(spapr->htab_fd); 1342 } 1343 spapr->htab_fd = -1; 1344 } 1345 1346 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1347 { 1348 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1349 1350 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1351 } 1352 1353 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1354 { 1355 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1356 1357 assert(kvm_enabled()); 1358 1359 if (!spapr->htab) { 1360 return 0; 1361 } 1362 1363 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1364 } 1365 1366 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1367 hwaddr ptex, int n) 1368 { 1369 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1370 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1371 1372 if (!spapr->htab) { 1373 /* 1374 * HTAB is controlled by KVM. Fetch into temporary buffer 1375 */ 1376 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1377 kvmppc_read_hptes(hptes, ptex, n); 1378 return hptes; 1379 } 1380 1381 /* 1382 * HTAB is controlled by QEMU. Just point to the internally 1383 * accessible PTEG. 1384 */ 1385 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1386 } 1387 1388 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1389 const ppc_hash_pte64_t *hptes, 1390 hwaddr ptex, int n) 1391 { 1392 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1393 1394 if (!spapr->htab) { 1395 g_free((void *)hptes); 1396 } 1397 1398 /* Nothing to do for qemu managed HPT */ 1399 } 1400 1401 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1402 uint64_t pte0, uint64_t pte1) 1403 { 1404 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1405 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1406 1407 if (!spapr->htab) { 1408 kvmppc_write_hpte(ptex, pte0, pte1); 1409 } else { 1410 if (pte0 & HPTE64_V_VALID) { 1411 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1412 /* 1413 * When setting valid, we write PTE1 first. This ensures 1414 * proper synchronization with the reading code in 1415 * ppc_hash64_pteg_search() 1416 */ 1417 smp_wmb(); 1418 stq_p(spapr->htab + offset, pte0); 1419 } else { 1420 stq_p(spapr->htab + offset, pte0); 1421 /* 1422 * When clearing it we set PTE0 first. This ensures proper 1423 * synchronization with the reading code in 1424 * ppc_hash64_pteg_search() 1425 */ 1426 smp_wmb(); 1427 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1428 } 1429 } 1430 } 1431 1432 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1433 uint64_t pte1) 1434 { 1435 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; 1436 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1437 1438 if (!spapr->htab) { 1439 /* There should always be a hash table when this is called */ 1440 error_report("spapr_hpte_set_c called with no hash table !"); 1441 return; 1442 } 1443 1444 /* The HW performs a non-atomic byte update */ 1445 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1446 } 1447 1448 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1449 uint64_t pte1) 1450 { 1451 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; 1452 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1453 1454 if (!spapr->htab) { 1455 /* There should always be a hash table when this is called */ 1456 error_report("spapr_hpte_set_r called with no hash table !"); 1457 return; 1458 } 1459 1460 /* The HW performs a non-atomic byte update */ 1461 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1462 } 1463 1464 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1465 { 1466 int shift; 1467 1468 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1469 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1470 * that's much more than is needed for Linux guests */ 1471 shift = ctz64(pow2ceil(ramsize)) - 7; 1472 shift = MAX(shift, 18); /* Minimum architected size */ 1473 shift = MIN(shift, 46); /* Maximum architected size */ 1474 return shift; 1475 } 1476 1477 void spapr_free_hpt(SpaprMachineState *spapr) 1478 { 1479 g_free(spapr->htab); 1480 spapr->htab = NULL; 1481 spapr->htab_shift = 0; 1482 close_htab_fd(spapr); 1483 } 1484 1485 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1486 { 1487 ERRP_GUARD(); 1488 long rc; 1489 1490 /* Clean up any HPT info from a previous boot */ 1491 spapr_free_hpt(spapr); 1492 1493 rc = kvmppc_reset_htab(shift); 1494 1495 if (rc == -EOPNOTSUPP) { 1496 error_setg(errp, "HPT not supported in nested guests"); 1497 return -EOPNOTSUPP; 1498 } 1499 1500 if (rc < 0) { 1501 /* kernel-side HPT needed, but couldn't allocate one */ 1502 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1503 shift); 1504 error_append_hint(errp, "Try smaller maxmem?\n"); 1505 return -errno; 1506 } else if (rc > 0) { 1507 /* kernel-side HPT allocated */ 1508 if (rc != shift) { 1509 error_setg(errp, 1510 "Requested order %d HPT, but kernel allocated order %ld", 1511 shift, rc); 1512 error_append_hint(errp, "Try smaller maxmem?\n"); 1513 return -ENOSPC; 1514 } 1515 1516 spapr->htab_shift = shift; 1517 spapr->htab = NULL; 1518 } else { 1519 /* kernel-side HPT not needed, allocate in userspace instead */ 1520 size_t size = 1ULL << shift; 1521 int i; 1522 1523 spapr->htab = qemu_memalign(size, size); 1524 memset(spapr->htab, 0, size); 1525 spapr->htab_shift = shift; 1526 1527 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1528 DIRTY_HPTE(HPTE(spapr->htab, i)); 1529 } 1530 } 1531 /* We're setting up a hash table, so that means we're not radix */ 1532 spapr->patb_entry = 0; 1533 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1534 return 0; 1535 } 1536 1537 void spapr_setup_hpt(SpaprMachineState *spapr) 1538 { 1539 int hpt_shift; 1540 1541 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1542 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1543 } else { 1544 uint64_t current_ram_size; 1545 1546 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1547 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1548 } 1549 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1550 1551 if (kvm_enabled()) { 1552 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1553 1554 /* Check our RMA fits in the possible VRMA */ 1555 if (vrma_limit < spapr->rma_size) { 1556 error_report("Unable to create %" HWADDR_PRIu 1557 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1558 spapr->rma_size / MiB, vrma_limit / MiB); 1559 exit(EXIT_FAILURE); 1560 } 1561 } 1562 } 1563 1564 void spapr_check_mmu_mode(bool guest_radix) 1565 { 1566 if (guest_radix) { 1567 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 1568 error_report("Guest requested unavailable MMU mode (radix)."); 1569 exit(EXIT_FAILURE); 1570 } 1571 } else { 1572 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 1573 && !kvmppc_has_cap_mmu_hash_v3()) { 1574 error_report("Guest requested unavailable MMU mode (hash)."); 1575 exit(EXIT_FAILURE); 1576 } 1577 } 1578 } 1579 1580 static void spapr_machine_reset(MachineState *machine) 1581 { 1582 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1583 PowerPCCPU *first_ppc_cpu; 1584 hwaddr fdt_addr; 1585 void *fdt; 1586 int rc; 1587 1588 pef_kvm_reset(machine->cgs, &error_fatal); 1589 spapr_caps_apply(spapr); 1590 1591 first_ppc_cpu = POWERPC_CPU(first_cpu); 1592 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1593 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1594 spapr->max_compat_pvr)) { 1595 /* 1596 * If using KVM with radix mode available, VCPUs can be started 1597 * without a HPT because KVM will start them in radix mode. 1598 * Set the GR bit in PATE so that we know there is no HPT. 1599 */ 1600 spapr->patb_entry = PATE1_GR; 1601 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1602 } else { 1603 spapr_setup_hpt(spapr); 1604 } 1605 1606 qemu_devices_reset(); 1607 1608 spapr_ovec_cleanup(spapr->ov5_cas); 1609 spapr->ov5_cas = spapr_ovec_new(); 1610 1611 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1612 1613 /* 1614 * This is fixing some of the default configuration of the XIVE 1615 * devices. To be called after the reset of the machine devices. 1616 */ 1617 spapr_irq_reset(spapr, &error_fatal); 1618 1619 /* 1620 * There is no CAS under qtest. Simulate one to please the code that 1621 * depends on spapr->ov5_cas. This is especially needed to test device 1622 * unplug, so we do that before resetting the DRCs. 1623 */ 1624 if (qtest_enabled()) { 1625 spapr_ovec_cleanup(spapr->ov5_cas); 1626 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1627 } 1628 1629 /* DRC reset may cause a device to be unplugged. This will cause troubles 1630 * if this device is used by another device (eg, a running vhost backend 1631 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1632 * situations, we reset DRCs after all devices have been reset. 1633 */ 1634 spapr_drc_reset_all(spapr); 1635 1636 spapr_clear_pending_events(spapr); 1637 1638 /* 1639 * We place the device tree just below either the top of the RMA, 1640 * or just below 2GB, whichever is lower, so that it can be 1641 * processed with 32-bit real mode code if necessary 1642 */ 1643 fdt_addr = MIN(spapr->rma_size, FDT_MAX_ADDR) - FDT_MAX_SIZE; 1644 1645 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1646 1647 rc = fdt_pack(fdt); 1648 1649 /* Should only fail if we've built a corrupted tree */ 1650 assert(rc == 0); 1651 1652 /* Load the fdt */ 1653 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1654 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1655 g_free(spapr->fdt_blob); 1656 spapr->fdt_size = fdt_totalsize(fdt); 1657 spapr->fdt_initial_size = spapr->fdt_size; 1658 spapr->fdt_blob = fdt; 1659 1660 /* Set up the entry state */ 1661 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0); 1662 first_ppc_cpu->env.gpr[5] = 0; 1663 1664 spapr->fwnmi_system_reset_addr = -1; 1665 spapr->fwnmi_machine_check_addr = -1; 1666 spapr->fwnmi_machine_check_interlock = -1; 1667 1668 /* Signal all vCPUs waiting on this condition */ 1669 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1670 1671 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1672 } 1673 1674 static void spapr_create_nvram(SpaprMachineState *spapr) 1675 { 1676 DeviceState *dev = qdev_new("spapr-nvram"); 1677 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1678 1679 if (dinfo) { 1680 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1681 &error_fatal); 1682 } 1683 1684 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1685 1686 spapr->nvram = (struct SpaprNvram *)dev; 1687 } 1688 1689 static void spapr_rtc_create(SpaprMachineState *spapr) 1690 { 1691 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1692 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1693 &error_fatal, NULL); 1694 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1695 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1696 "date"); 1697 } 1698 1699 /* Returns whether we want to use VGA or not */ 1700 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1701 { 1702 switch (vga_interface_type) { 1703 case VGA_NONE: 1704 return false; 1705 case VGA_DEVICE: 1706 return true; 1707 case VGA_STD: 1708 case VGA_VIRTIO: 1709 case VGA_CIRRUS: 1710 return pci_vga_init(pci_bus) != NULL; 1711 default: 1712 error_setg(errp, 1713 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1714 return false; 1715 } 1716 } 1717 1718 static int spapr_pre_load(void *opaque) 1719 { 1720 int rc; 1721 1722 rc = spapr_caps_pre_load(opaque); 1723 if (rc) { 1724 return rc; 1725 } 1726 1727 return 0; 1728 } 1729 1730 static int spapr_post_load(void *opaque, int version_id) 1731 { 1732 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1733 int err = 0; 1734 1735 err = spapr_caps_post_migration(spapr); 1736 if (err) { 1737 return err; 1738 } 1739 1740 /* 1741 * In earlier versions, there was no separate qdev for the PAPR 1742 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1743 * So when migrating from those versions, poke the incoming offset 1744 * value into the RTC device 1745 */ 1746 if (version_id < 3) { 1747 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1748 if (err) { 1749 return err; 1750 } 1751 } 1752 1753 if (kvm_enabled() && spapr->patb_entry) { 1754 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1755 bool radix = !!(spapr->patb_entry & PATE1_GR); 1756 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1757 1758 /* 1759 * Update LPCR:HR and UPRT as they may not be set properly in 1760 * the stream 1761 */ 1762 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1763 LPCR_HR | LPCR_UPRT); 1764 1765 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1766 if (err) { 1767 error_report("Process table config unsupported by the host"); 1768 return -EINVAL; 1769 } 1770 } 1771 1772 err = spapr_irq_post_load(spapr, version_id); 1773 if (err) { 1774 return err; 1775 } 1776 1777 return err; 1778 } 1779 1780 static int spapr_pre_save(void *opaque) 1781 { 1782 int rc; 1783 1784 rc = spapr_caps_pre_save(opaque); 1785 if (rc) { 1786 return rc; 1787 } 1788 1789 return 0; 1790 } 1791 1792 static bool version_before_3(void *opaque, int version_id) 1793 { 1794 return version_id < 3; 1795 } 1796 1797 static bool spapr_pending_events_needed(void *opaque) 1798 { 1799 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1800 return !QTAILQ_EMPTY(&spapr->pending_events); 1801 } 1802 1803 static const VMStateDescription vmstate_spapr_event_entry = { 1804 .name = "spapr_event_log_entry", 1805 .version_id = 1, 1806 .minimum_version_id = 1, 1807 .fields = (VMStateField[]) { 1808 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1809 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1810 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1811 NULL, extended_length), 1812 VMSTATE_END_OF_LIST() 1813 }, 1814 }; 1815 1816 static const VMStateDescription vmstate_spapr_pending_events = { 1817 .name = "spapr_pending_events", 1818 .version_id = 1, 1819 .minimum_version_id = 1, 1820 .needed = spapr_pending_events_needed, 1821 .fields = (VMStateField[]) { 1822 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1823 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1824 VMSTATE_END_OF_LIST() 1825 }, 1826 }; 1827 1828 static bool spapr_ov5_cas_needed(void *opaque) 1829 { 1830 SpaprMachineState *spapr = opaque; 1831 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1832 bool cas_needed; 1833 1834 /* Prior to the introduction of SpaprOptionVector, we had two option 1835 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1836 * Both of these options encode machine topology into the device-tree 1837 * in such a way that the now-booted OS should still be able to interact 1838 * appropriately with QEMU regardless of what options were actually 1839 * negotiatied on the source side. 1840 * 1841 * As such, we can avoid migrating the CAS-negotiated options if these 1842 * are the only options available on the current machine/platform. 1843 * Since these are the only options available for pseries-2.7 and 1844 * earlier, this allows us to maintain old->new/new->old migration 1845 * compatibility. 1846 * 1847 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1848 * via default pseries-2.8 machines and explicit command-line parameters. 1849 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1850 * of the actual CAS-negotiated values to continue working properly. For 1851 * example, availability of memory unplug depends on knowing whether 1852 * OV5_HP_EVT was negotiated via CAS. 1853 * 1854 * Thus, for any cases where the set of available CAS-negotiatable 1855 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1856 * include the CAS-negotiated options in the migration stream, unless 1857 * if they affect boot time behaviour only. 1858 */ 1859 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1860 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1861 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1862 1863 /* We need extra information if we have any bits outside the mask 1864 * defined above */ 1865 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1866 1867 spapr_ovec_cleanup(ov5_mask); 1868 1869 return cas_needed; 1870 } 1871 1872 static const VMStateDescription vmstate_spapr_ov5_cas = { 1873 .name = "spapr_option_vector_ov5_cas", 1874 .version_id = 1, 1875 .minimum_version_id = 1, 1876 .needed = spapr_ov5_cas_needed, 1877 .fields = (VMStateField[]) { 1878 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1879 vmstate_spapr_ovec, SpaprOptionVector), 1880 VMSTATE_END_OF_LIST() 1881 }, 1882 }; 1883 1884 static bool spapr_patb_entry_needed(void *opaque) 1885 { 1886 SpaprMachineState *spapr = opaque; 1887 1888 return !!spapr->patb_entry; 1889 } 1890 1891 static const VMStateDescription vmstate_spapr_patb_entry = { 1892 .name = "spapr_patb_entry", 1893 .version_id = 1, 1894 .minimum_version_id = 1, 1895 .needed = spapr_patb_entry_needed, 1896 .fields = (VMStateField[]) { 1897 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1898 VMSTATE_END_OF_LIST() 1899 }, 1900 }; 1901 1902 static bool spapr_irq_map_needed(void *opaque) 1903 { 1904 SpaprMachineState *spapr = opaque; 1905 1906 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1907 } 1908 1909 static const VMStateDescription vmstate_spapr_irq_map = { 1910 .name = "spapr_irq_map", 1911 .version_id = 1, 1912 .minimum_version_id = 1, 1913 .needed = spapr_irq_map_needed, 1914 .fields = (VMStateField[]) { 1915 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1916 VMSTATE_END_OF_LIST() 1917 }, 1918 }; 1919 1920 static bool spapr_dtb_needed(void *opaque) 1921 { 1922 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1923 1924 return smc->update_dt_enabled; 1925 } 1926 1927 static int spapr_dtb_pre_load(void *opaque) 1928 { 1929 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1930 1931 g_free(spapr->fdt_blob); 1932 spapr->fdt_blob = NULL; 1933 spapr->fdt_size = 0; 1934 1935 return 0; 1936 } 1937 1938 static const VMStateDescription vmstate_spapr_dtb = { 1939 .name = "spapr_dtb", 1940 .version_id = 1, 1941 .minimum_version_id = 1, 1942 .needed = spapr_dtb_needed, 1943 .pre_load = spapr_dtb_pre_load, 1944 .fields = (VMStateField[]) { 1945 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1946 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1947 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1948 fdt_size), 1949 VMSTATE_END_OF_LIST() 1950 }, 1951 }; 1952 1953 static bool spapr_fwnmi_needed(void *opaque) 1954 { 1955 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1956 1957 return spapr->fwnmi_machine_check_addr != -1; 1958 } 1959 1960 static int spapr_fwnmi_pre_save(void *opaque) 1961 { 1962 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1963 1964 /* 1965 * Check if machine check handling is in progress and print a 1966 * warning message. 1967 */ 1968 if (spapr->fwnmi_machine_check_interlock != -1) { 1969 warn_report("A machine check is being handled during migration. The" 1970 "handler may run and log hardware error on the destination"); 1971 } 1972 1973 return 0; 1974 } 1975 1976 static const VMStateDescription vmstate_spapr_fwnmi = { 1977 .name = "spapr_fwnmi", 1978 .version_id = 1, 1979 .minimum_version_id = 1, 1980 .needed = spapr_fwnmi_needed, 1981 .pre_save = spapr_fwnmi_pre_save, 1982 .fields = (VMStateField[]) { 1983 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 1984 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 1985 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 1986 VMSTATE_END_OF_LIST() 1987 }, 1988 }; 1989 1990 static const VMStateDescription vmstate_spapr = { 1991 .name = "spapr", 1992 .version_id = 3, 1993 .minimum_version_id = 1, 1994 .pre_load = spapr_pre_load, 1995 .post_load = spapr_post_load, 1996 .pre_save = spapr_pre_save, 1997 .fields = (VMStateField[]) { 1998 /* used to be @next_irq */ 1999 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2000 2001 /* RTC offset */ 2002 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2003 2004 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2005 VMSTATE_END_OF_LIST() 2006 }, 2007 .subsections = (const VMStateDescription*[]) { 2008 &vmstate_spapr_ov5_cas, 2009 &vmstate_spapr_patb_entry, 2010 &vmstate_spapr_pending_events, 2011 &vmstate_spapr_cap_htm, 2012 &vmstate_spapr_cap_vsx, 2013 &vmstate_spapr_cap_dfp, 2014 &vmstate_spapr_cap_cfpc, 2015 &vmstate_spapr_cap_sbbc, 2016 &vmstate_spapr_cap_ibs, 2017 &vmstate_spapr_cap_hpt_maxpagesize, 2018 &vmstate_spapr_irq_map, 2019 &vmstate_spapr_cap_nested_kvm_hv, 2020 &vmstate_spapr_dtb, 2021 &vmstate_spapr_cap_large_decr, 2022 &vmstate_spapr_cap_ccf_assist, 2023 &vmstate_spapr_cap_fwnmi, 2024 &vmstate_spapr_fwnmi, 2025 NULL 2026 } 2027 }; 2028 2029 static int htab_save_setup(QEMUFile *f, void *opaque) 2030 { 2031 SpaprMachineState *spapr = opaque; 2032 2033 /* "Iteration" header */ 2034 if (!spapr->htab_shift) { 2035 qemu_put_be32(f, -1); 2036 } else { 2037 qemu_put_be32(f, spapr->htab_shift); 2038 } 2039 2040 if (spapr->htab) { 2041 spapr->htab_save_index = 0; 2042 spapr->htab_first_pass = true; 2043 } else { 2044 if (spapr->htab_shift) { 2045 assert(kvm_enabled()); 2046 } 2047 } 2048 2049 2050 return 0; 2051 } 2052 2053 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2054 int chunkstart, int n_valid, int n_invalid) 2055 { 2056 qemu_put_be32(f, chunkstart); 2057 qemu_put_be16(f, n_valid); 2058 qemu_put_be16(f, n_invalid); 2059 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2060 HASH_PTE_SIZE_64 * n_valid); 2061 } 2062 2063 static void htab_save_end_marker(QEMUFile *f) 2064 { 2065 qemu_put_be32(f, 0); 2066 qemu_put_be16(f, 0); 2067 qemu_put_be16(f, 0); 2068 } 2069 2070 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2071 int64_t max_ns) 2072 { 2073 bool has_timeout = max_ns != -1; 2074 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2075 int index = spapr->htab_save_index; 2076 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2077 2078 assert(spapr->htab_first_pass); 2079 2080 do { 2081 int chunkstart; 2082 2083 /* Consume invalid HPTEs */ 2084 while ((index < htabslots) 2085 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2086 CLEAN_HPTE(HPTE(spapr->htab, index)); 2087 index++; 2088 } 2089 2090 /* Consume valid HPTEs */ 2091 chunkstart = index; 2092 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2093 && HPTE_VALID(HPTE(spapr->htab, index))) { 2094 CLEAN_HPTE(HPTE(spapr->htab, index)); 2095 index++; 2096 } 2097 2098 if (index > chunkstart) { 2099 int n_valid = index - chunkstart; 2100 2101 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2102 2103 if (has_timeout && 2104 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2105 break; 2106 } 2107 } 2108 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2109 2110 if (index >= htabslots) { 2111 assert(index == htabslots); 2112 index = 0; 2113 spapr->htab_first_pass = false; 2114 } 2115 spapr->htab_save_index = index; 2116 } 2117 2118 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2119 int64_t max_ns) 2120 { 2121 bool final = max_ns < 0; 2122 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2123 int examined = 0, sent = 0; 2124 int index = spapr->htab_save_index; 2125 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2126 2127 assert(!spapr->htab_first_pass); 2128 2129 do { 2130 int chunkstart, invalidstart; 2131 2132 /* Consume non-dirty HPTEs */ 2133 while ((index < htabslots) 2134 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2135 index++; 2136 examined++; 2137 } 2138 2139 chunkstart = index; 2140 /* Consume valid dirty HPTEs */ 2141 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2142 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2143 && HPTE_VALID(HPTE(spapr->htab, index))) { 2144 CLEAN_HPTE(HPTE(spapr->htab, index)); 2145 index++; 2146 examined++; 2147 } 2148 2149 invalidstart = index; 2150 /* Consume invalid dirty HPTEs */ 2151 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2152 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2153 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2154 CLEAN_HPTE(HPTE(spapr->htab, index)); 2155 index++; 2156 examined++; 2157 } 2158 2159 if (index > chunkstart) { 2160 int n_valid = invalidstart - chunkstart; 2161 int n_invalid = index - invalidstart; 2162 2163 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2164 sent += index - chunkstart; 2165 2166 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2167 break; 2168 } 2169 } 2170 2171 if (examined >= htabslots) { 2172 break; 2173 } 2174 2175 if (index >= htabslots) { 2176 assert(index == htabslots); 2177 index = 0; 2178 } 2179 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2180 2181 if (index >= htabslots) { 2182 assert(index == htabslots); 2183 index = 0; 2184 } 2185 2186 spapr->htab_save_index = index; 2187 2188 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2189 } 2190 2191 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2192 #define MAX_KVM_BUF_SIZE 2048 2193 2194 static int htab_save_iterate(QEMUFile *f, void *opaque) 2195 { 2196 SpaprMachineState *spapr = opaque; 2197 int fd; 2198 int rc = 0; 2199 2200 /* Iteration header */ 2201 if (!spapr->htab_shift) { 2202 qemu_put_be32(f, -1); 2203 return 1; 2204 } else { 2205 qemu_put_be32(f, 0); 2206 } 2207 2208 if (!spapr->htab) { 2209 assert(kvm_enabled()); 2210 2211 fd = get_htab_fd(spapr); 2212 if (fd < 0) { 2213 return fd; 2214 } 2215 2216 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2217 if (rc < 0) { 2218 return rc; 2219 } 2220 } else if (spapr->htab_first_pass) { 2221 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2222 } else { 2223 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2224 } 2225 2226 htab_save_end_marker(f); 2227 2228 return rc; 2229 } 2230 2231 static int htab_save_complete(QEMUFile *f, void *opaque) 2232 { 2233 SpaprMachineState *spapr = opaque; 2234 int fd; 2235 2236 /* Iteration header */ 2237 if (!spapr->htab_shift) { 2238 qemu_put_be32(f, -1); 2239 return 0; 2240 } else { 2241 qemu_put_be32(f, 0); 2242 } 2243 2244 if (!spapr->htab) { 2245 int rc; 2246 2247 assert(kvm_enabled()); 2248 2249 fd = get_htab_fd(spapr); 2250 if (fd < 0) { 2251 return fd; 2252 } 2253 2254 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2255 if (rc < 0) { 2256 return rc; 2257 } 2258 } else { 2259 if (spapr->htab_first_pass) { 2260 htab_save_first_pass(f, spapr, -1); 2261 } 2262 htab_save_later_pass(f, spapr, -1); 2263 } 2264 2265 /* End marker */ 2266 htab_save_end_marker(f); 2267 2268 return 0; 2269 } 2270 2271 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2272 { 2273 SpaprMachineState *spapr = opaque; 2274 uint32_t section_hdr; 2275 int fd = -1; 2276 Error *local_err = NULL; 2277 2278 if (version_id < 1 || version_id > 1) { 2279 error_report("htab_load() bad version"); 2280 return -EINVAL; 2281 } 2282 2283 section_hdr = qemu_get_be32(f); 2284 2285 if (section_hdr == -1) { 2286 spapr_free_hpt(spapr); 2287 return 0; 2288 } 2289 2290 if (section_hdr) { 2291 int ret; 2292 2293 /* First section gives the htab size */ 2294 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2295 if (ret < 0) { 2296 error_report_err(local_err); 2297 return ret; 2298 } 2299 return 0; 2300 } 2301 2302 if (!spapr->htab) { 2303 assert(kvm_enabled()); 2304 2305 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2306 if (fd < 0) { 2307 error_report_err(local_err); 2308 return fd; 2309 } 2310 } 2311 2312 while (true) { 2313 uint32_t index; 2314 uint16_t n_valid, n_invalid; 2315 2316 index = qemu_get_be32(f); 2317 n_valid = qemu_get_be16(f); 2318 n_invalid = qemu_get_be16(f); 2319 2320 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2321 /* End of Stream */ 2322 break; 2323 } 2324 2325 if ((index + n_valid + n_invalid) > 2326 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2327 /* Bad index in stream */ 2328 error_report( 2329 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2330 index, n_valid, n_invalid, spapr->htab_shift); 2331 return -EINVAL; 2332 } 2333 2334 if (spapr->htab) { 2335 if (n_valid) { 2336 qemu_get_buffer(f, HPTE(spapr->htab, index), 2337 HASH_PTE_SIZE_64 * n_valid); 2338 } 2339 if (n_invalid) { 2340 memset(HPTE(spapr->htab, index + n_valid), 0, 2341 HASH_PTE_SIZE_64 * n_invalid); 2342 } 2343 } else { 2344 int rc; 2345 2346 assert(fd >= 0); 2347 2348 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2349 &local_err); 2350 if (rc < 0) { 2351 error_report_err(local_err); 2352 return rc; 2353 } 2354 } 2355 } 2356 2357 if (!spapr->htab) { 2358 assert(fd >= 0); 2359 close(fd); 2360 } 2361 2362 return 0; 2363 } 2364 2365 static void htab_save_cleanup(void *opaque) 2366 { 2367 SpaprMachineState *spapr = opaque; 2368 2369 close_htab_fd(spapr); 2370 } 2371 2372 static SaveVMHandlers savevm_htab_handlers = { 2373 .save_setup = htab_save_setup, 2374 .save_live_iterate = htab_save_iterate, 2375 .save_live_complete_precopy = htab_save_complete, 2376 .save_cleanup = htab_save_cleanup, 2377 .load_state = htab_load, 2378 }; 2379 2380 static void spapr_boot_set(void *opaque, const char *boot_device, 2381 Error **errp) 2382 { 2383 SpaprMachineState *spapr = SPAPR_MACHINE(opaque); 2384 2385 g_free(spapr->boot_device); 2386 spapr->boot_device = g_strdup(boot_device); 2387 } 2388 2389 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2390 { 2391 MachineState *machine = MACHINE(spapr); 2392 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2393 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2394 int i; 2395 2396 for (i = 0; i < nr_lmbs; i++) { 2397 uint64_t addr; 2398 2399 addr = i * lmb_size + machine->device_memory->base; 2400 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2401 addr / lmb_size); 2402 } 2403 } 2404 2405 /* 2406 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2407 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2408 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2409 */ 2410 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2411 { 2412 int i; 2413 2414 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2415 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2416 " is not aligned to %" PRIu64 " MiB", 2417 machine->ram_size, 2418 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2419 return; 2420 } 2421 2422 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2423 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2424 " is not aligned to %" PRIu64 " MiB", 2425 machine->ram_size, 2426 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2427 return; 2428 } 2429 2430 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2431 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2432 error_setg(errp, 2433 "Node %d memory size 0x%" PRIx64 2434 " is not aligned to %" PRIu64 " MiB", 2435 i, machine->numa_state->nodes[i].node_mem, 2436 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2437 return; 2438 } 2439 } 2440 } 2441 2442 /* find cpu slot in machine->possible_cpus by core_id */ 2443 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2444 { 2445 int index = id / ms->smp.threads; 2446 2447 if (index >= ms->possible_cpus->len) { 2448 return NULL; 2449 } 2450 if (idx) { 2451 *idx = index; 2452 } 2453 return &ms->possible_cpus->cpus[index]; 2454 } 2455 2456 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2457 { 2458 MachineState *ms = MACHINE(spapr); 2459 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2460 Error *local_err = NULL; 2461 bool vsmt_user = !!spapr->vsmt; 2462 int kvm_smt = kvmppc_smt_threads(); 2463 int ret; 2464 unsigned int smp_threads = ms->smp.threads; 2465 2466 if (!kvm_enabled() && (smp_threads > 1)) { 2467 error_setg(errp, "TCG cannot support more than 1 thread/core " 2468 "on a pseries machine"); 2469 return; 2470 } 2471 if (!is_power_of_2(smp_threads)) { 2472 error_setg(errp, "Cannot support %d threads/core on a pseries " 2473 "machine because it must be a power of 2", smp_threads); 2474 return; 2475 } 2476 2477 /* Detemine the VSMT mode to use: */ 2478 if (vsmt_user) { 2479 if (spapr->vsmt < smp_threads) { 2480 error_setg(errp, "Cannot support VSMT mode %d" 2481 " because it must be >= threads/core (%d)", 2482 spapr->vsmt, smp_threads); 2483 return; 2484 } 2485 /* In this case, spapr->vsmt has been set by the command line */ 2486 } else if (!smc->smp_threads_vsmt) { 2487 /* 2488 * Default VSMT value is tricky, because we need it to be as 2489 * consistent as possible (for migration), but this requires 2490 * changing it for at least some existing cases. We pick 8 as 2491 * the value that we'd get with KVM on POWER8, the 2492 * overwhelmingly common case in production systems. 2493 */ 2494 spapr->vsmt = MAX(8, smp_threads); 2495 } else { 2496 spapr->vsmt = smp_threads; 2497 } 2498 2499 /* KVM: If necessary, set the SMT mode: */ 2500 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2501 ret = kvmppc_set_smt_threads(spapr->vsmt); 2502 if (ret) { 2503 /* Looks like KVM isn't able to change VSMT mode */ 2504 error_setg(&local_err, 2505 "Failed to set KVM's VSMT mode to %d (errno %d)", 2506 spapr->vsmt, ret); 2507 /* We can live with that if the default one is big enough 2508 * for the number of threads, and a submultiple of the one 2509 * we want. In this case we'll waste some vcpu ids, but 2510 * behaviour will be correct */ 2511 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2512 warn_report_err(local_err); 2513 } else { 2514 if (!vsmt_user) { 2515 error_append_hint(&local_err, 2516 "On PPC, a VM with %d threads/core" 2517 " on a host with %d threads/core" 2518 " requires the use of VSMT mode %d.\n", 2519 smp_threads, kvm_smt, spapr->vsmt); 2520 } 2521 kvmppc_error_append_smt_possible_hint(&local_err); 2522 error_propagate(errp, local_err); 2523 } 2524 } 2525 } 2526 /* else TCG: nothing to do currently */ 2527 } 2528 2529 static void spapr_init_cpus(SpaprMachineState *spapr) 2530 { 2531 MachineState *machine = MACHINE(spapr); 2532 MachineClass *mc = MACHINE_GET_CLASS(machine); 2533 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2534 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2535 const CPUArchIdList *possible_cpus; 2536 unsigned int smp_cpus = machine->smp.cpus; 2537 unsigned int smp_threads = machine->smp.threads; 2538 unsigned int max_cpus = machine->smp.max_cpus; 2539 int boot_cores_nr = smp_cpus / smp_threads; 2540 int i; 2541 2542 possible_cpus = mc->possible_cpu_arch_ids(machine); 2543 if (mc->has_hotpluggable_cpus) { 2544 if (smp_cpus % smp_threads) { 2545 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2546 smp_cpus, smp_threads); 2547 exit(1); 2548 } 2549 if (max_cpus % smp_threads) { 2550 error_report("max_cpus (%u) must be multiple of threads (%u)", 2551 max_cpus, smp_threads); 2552 exit(1); 2553 } 2554 } else { 2555 if (max_cpus != smp_cpus) { 2556 error_report("This machine version does not support CPU hotplug"); 2557 exit(1); 2558 } 2559 boot_cores_nr = possible_cpus->len; 2560 } 2561 2562 if (smc->pre_2_10_has_unused_icps) { 2563 int i; 2564 2565 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2566 /* Dummy entries get deregistered when real ICPState objects 2567 * are registered during CPU core hotplug. 2568 */ 2569 pre_2_10_vmstate_register_dummy_icp(i); 2570 } 2571 } 2572 2573 for (i = 0; i < possible_cpus->len; i++) { 2574 int core_id = i * smp_threads; 2575 2576 if (mc->has_hotpluggable_cpus) { 2577 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2578 spapr_vcpu_id(spapr, core_id)); 2579 } 2580 2581 if (i < boot_cores_nr) { 2582 Object *core = object_new(type); 2583 int nr_threads = smp_threads; 2584 2585 /* Handle the partially filled core for older machine types */ 2586 if ((i + 1) * smp_threads >= smp_cpus) { 2587 nr_threads = smp_cpus - i * smp_threads; 2588 } 2589 2590 object_property_set_int(core, "nr-threads", nr_threads, 2591 &error_fatal); 2592 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2593 &error_fatal); 2594 qdev_realize(DEVICE(core), NULL, &error_fatal); 2595 2596 object_unref(core); 2597 } 2598 } 2599 } 2600 2601 static PCIHostState *spapr_create_default_phb(void) 2602 { 2603 DeviceState *dev; 2604 2605 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2606 qdev_prop_set_uint32(dev, "index", 0); 2607 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2608 2609 return PCI_HOST_BRIDGE(dev); 2610 } 2611 2612 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2613 { 2614 MachineState *machine = MACHINE(spapr); 2615 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2616 hwaddr rma_size = machine->ram_size; 2617 hwaddr node0_size = spapr_node0_size(machine); 2618 2619 /* RMA has to fit in the first NUMA node */ 2620 rma_size = MIN(rma_size, node0_size); 2621 2622 /* 2623 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2624 * never exceed that 2625 */ 2626 rma_size = MIN(rma_size, 1 * TiB); 2627 2628 /* 2629 * Clamp the RMA size based on machine type. This is for 2630 * migration compatibility with older qemu versions, which limited 2631 * the RMA size for complicated and mostly bad reasons. 2632 */ 2633 if (smc->rma_limit) { 2634 rma_size = MIN(rma_size, smc->rma_limit); 2635 } 2636 2637 if (rma_size < MIN_RMA_SLOF) { 2638 error_setg(errp, 2639 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2640 "ldMiB guest RMA (Real Mode Area memory)", 2641 MIN_RMA_SLOF / MiB); 2642 return 0; 2643 } 2644 2645 return rma_size; 2646 } 2647 2648 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2649 { 2650 MachineState *machine = MACHINE(spapr); 2651 int i; 2652 2653 for (i = 0; i < machine->ram_slots; i++) { 2654 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2655 } 2656 } 2657 2658 /* pSeries LPAR / sPAPR hardware init */ 2659 static void spapr_machine_init(MachineState *machine) 2660 { 2661 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2662 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2663 MachineClass *mc = MACHINE_GET_CLASS(machine); 2664 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 2665 const char *kernel_filename = machine->kernel_filename; 2666 const char *initrd_filename = machine->initrd_filename; 2667 PCIHostState *phb; 2668 int i; 2669 MemoryRegion *sysmem = get_system_memory(); 2670 long load_limit, fw_size; 2671 char *filename; 2672 Error *resize_hpt_err = NULL; 2673 2674 /* 2675 * if Secure VM (PEF) support is configured, then initialize it 2676 */ 2677 pef_kvm_init(machine->cgs, &error_fatal); 2678 2679 msi_nonbroken = true; 2680 2681 QLIST_INIT(&spapr->phbs); 2682 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2683 2684 /* Determine capabilities to run with */ 2685 spapr_caps_init(spapr); 2686 2687 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2688 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2689 /* 2690 * If the user explicitly requested a mode we should either 2691 * supply it, or fail completely (which we do below). But if 2692 * it's not set explicitly, we reset our mode to something 2693 * that works 2694 */ 2695 if (resize_hpt_err) { 2696 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2697 error_free(resize_hpt_err); 2698 resize_hpt_err = NULL; 2699 } else { 2700 spapr->resize_hpt = smc->resize_hpt_default; 2701 } 2702 } 2703 2704 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2705 2706 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2707 /* 2708 * User requested HPT resize, but this host can't supply it. Bail out 2709 */ 2710 error_report_err(resize_hpt_err); 2711 exit(1); 2712 } 2713 error_free(resize_hpt_err); 2714 2715 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2716 2717 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2718 load_limit = MIN(spapr->rma_size, FDT_MAX_ADDR) - FW_OVERHEAD; 2719 2720 /* 2721 * VSMT must be set in order to be able to compute VCPU ids, ie to 2722 * call spapr_max_server_number() or spapr_vcpu_id(). 2723 */ 2724 spapr_set_vsmt_mode(spapr, &error_fatal); 2725 2726 /* Set up Interrupt Controller before we create the VCPUs */ 2727 spapr_irq_init(spapr, &error_fatal); 2728 2729 /* Set up containers for ibm,client-architecture-support negotiated options 2730 */ 2731 spapr->ov5 = spapr_ovec_new(); 2732 spapr->ov5_cas = spapr_ovec_new(); 2733 2734 if (smc->dr_lmb_enabled) { 2735 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2736 spapr_validate_node_memory(machine, &error_fatal); 2737 } 2738 2739 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2740 2741 /* advertise support for dedicated HP event source to guests */ 2742 if (spapr->use_hotplug_event_source) { 2743 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2744 } 2745 2746 /* advertise support for HPT resizing */ 2747 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2748 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2749 } 2750 2751 /* advertise support for ibm,dyamic-memory-v2 */ 2752 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2753 2754 /* advertise XIVE on POWER9 machines */ 2755 if (spapr->irq->xive) { 2756 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2757 } 2758 2759 /* init CPUs */ 2760 spapr_init_cpus(spapr); 2761 2762 /* 2763 * check we don't have a memory-less/cpu-less NUMA node 2764 * Firmware relies on the existing memory/cpu topology to provide the 2765 * NUMA topology to the kernel. 2766 * And the linux kernel needs to know the NUMA topology at start 2767 * to be able to hotplug CPUs later. 2768 */ 2769 if (machine->numa_state->num_nodes) { 2770 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 2771 /* check for memory-less node */ 2772 if (machine->numa_state->nodes[i].node_mem == 0) { 2773 CPUState *cs; 2774 int found = 0; 2775 /* check for cpu-less node */ 2776 CPU_FOREACH(cs) { 2777 PowerPCCPU *cpu = POWERPC_CPU(cs); 2778 if (cpu->node_id == i) { 2779 found = 1; 2780 break; 2781 } 2782 } 2783 /* memory-less and cpu-less node */ 2784 if (!found) { 2785 error_report( 2786 "Memory-less/cpu-less nodes are not supported (node %d)", 2787 i); 2788 exit(1); 2789 } 2790 } 2791 } 2792 2793 } 2794 2795 spapr->gpu_numa_id = spapr_numa_initial_nvgpu_numa_id(machine); 2796 2797 /* Init numa_assoc_array */ 2798 spapr_numa_associativity_init(spapr, machine); 2799 2800 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2801 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2802 spapr->max_compat_pvr)) { 2803 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2804 /* KVM and TCG always allow GTSE with radix... */ 2805 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2806 } 2807 /* ... but not with hash (currently). */ 2808 2809 if (kvm_enabled()) { 2810 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2811 kvmppc_enable_logical_ci_hcalls(); 2812 kvmppc_enable_set_mode_hcall(); 2813 2814 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2815 kvmppc_enable_clear_ref_mod_hcalls(); 2816 2817 /* Enable H_PAGE_INIT */ 2818 kvmppc_enable_h_page_init(); 2819 } 2820 2821 /* map RAM */ 2822 memory_region_add_subregion(sysmem, 0, machine->ram); 2823 2824 /* always allocate the device memory information */ 2825 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2826 2827 /* initialize hotplug memory address space */ 2828 if (machine->ram_size < machine->maxram_size) { 2829 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2830 /* 2831 * Limit the number of hotpluggable memory slots to half the number 2832 * slots that KVM supports, leaving the other half for PCI and other 2833 * devices. However ensure that number of slots doesn't drop below 32. 2834 */ 2835 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2836 SPAPR_MAX_RAM_SLOTS; 2837 2838 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2839 max_memslots = SPAPR_MAX_RAM_SLOTS; 2840 } 2841 if (machine->ram_slots > max_memslots) { 2842 error_report("Specified number of memory slots %" 2843 PRIu64" exceeds max supported %d", 2844 machine->ram_slots, max_memslots); 2845 exit(1); 2846 } 2847 2848 machine->device_memory->base = ROUND_UP(machine->ram_size, 2849 SPAPR_DEVICE_MEM_ALIGN); 2850 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2851 "device-memory", device_mem_size); 2852 memory_region_add_subregion(sysmem, machine->device_memory->base, 2853 &machine->device_memory->mr); 2854 } 2855 2856 if (smc->dr_lmb_enabled) { 2857 spapr_create_lmb_dr_connectors(spapr); 2858 } 2859 2860 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { 2861 /* Create the error string for live migration blocker */ 2862 error_setg(&spapr->fwnmi_migration_blocker, 2863 "A machine check is being handled during migration. The handler" 2864 "may run and log hardware error on the destination"); 2865 } 2866 2867 if (mc->nvdimm_supported) { 2868 spapr_create_nvdimm_dr_connectors(spapr); 2869 } 2870 2871 /* Set up RTAS event infrastructure */ 2872 spapr_events_init(spapr); 2873 2874 /* Set up the RTC RTAS interfaces */ 2875 spapr_rtc_create(spapr); 2876 2877 /* Set up VIO bus */ 2878 spapr->vio_bus = spapr_vio_bus_init(); 2879 2880 for (i = 0; serial_hd(i); i++) { 2881 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2882 } 2883 2884 /* We always have at least the nvram device on VIO */ 2885 spapr_create_nvram(spapr); 2886 2887 /* 2888 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2889 * connectors (described in root DT node's "ibm,drc-types" property) 2890 * are pre-initialized here. additional child connectors (such as 2891 * connectors for a PHBs PCI slots) are added as needed during their 2892 * parent's realization. 2893 */ 2894 if (smc->dr_phb_enabled) { 2895 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2896 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2897 } 2898 } 2899 2900 /* Set up PCI */ 2901 spapr_pci_rtas_init(); 2902 2903 phb = spapr_create_default_phb(); 2904 2905 for (i = 0; i < nb_nics; i++) { 2906 NICInfo *nd = &nd_table[i]; 2907 2908 if (!nd->model) { 2909 nd->model = g_strdup("spapr-vlan"); 2910 } 2911 2912 if (g_str_equal(nd->model, "spapr-vlan") || 2913 g_str_equal(nd->model, "ibmveth")) { 2914 spapr_vlan_create(spapr->vio_bus, nd); 2915 } else { 2916 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2917 } 2918 } 2919 2920 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2921 spapr_vscsi_create(spapr->vio_bus); 2922 } 2923 2924 /* Graphics */ 2925 if (spapr_vga_init(phb->bus, &error_fatal)) { 2926 spapr->has_graphics = true; 2927 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2928 } 2929 2930 if (machine->usb) { 2931 if (smc->use_ohci_by_default) { 2932 pci_create_simple(phb->bus, -1, "pci-ohci"); 2933 } else { 2934 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2935 } 2936 2937 if (spapr->has_graphics) { 2938 USBBus *usb_bus = usb_bus_find(-1); 2939 2940 usb_create_simple(usb_bus, "usb-kbd"); 2941 usb_create_simple(usb_bus, "usb-mouse"); 2942 } 2943 } 2944 2945 if (kernel_filename) { 2946 spapr->kernel_size = load_elf(kernel_filename, NULL, 2947 translate_kernel_address, spapr, 2948 NULL, NULL, NULL, NULL, 1, 2949 PPC_ELF_MACHINE, 0, 0); 2950 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2951 spapr->kernel_size = load_elf(kernel_filename, NULL, 2952 translate_kernel_address, spapr, 2953 NULL, NULL, NULL, NULL, 0, 2954 PPC_ELF_MACHINE, 0, 0); 2955 spapr->kernel_le = spapr->kernel_size > 0; 2956 } 2957 if (spapr->kernel_size < 0) { 2958 error_report("error loading %s: %s", kernel_filename, 2959 load_elf_strerror(spapr->kernel_size)); 2960 exit(1); 2961 } 2962 2963 /* load initrd */ 2964 if (initrd_filename) { 2965 /* Try to locate the initrd in the gap between the kernel 2966 * and the firmware. Add a bit of space just in case 2967 */ 2968 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 2969 + 0x1ffff) & ~0xffff; 2970 spapr->initrd_size = load_image_targphys(initrd_filename, 2971 spapr->initrd_base, 2972 load_limit 2973 - spapr->initrd_base); 2974 if (spapr->initrd_size < 0) { 2975 error_report("could not load initial ram disk '%s'", 2976 initrd_filename); 2977 exit(1); 2978 } 2979 } 2980 } 2981 2982 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2983 if (!filename) { 2984 error_report("Could not find LPAR firmware '%s'", bios_name); 2985 exit(1); 2986 } 2987 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2988 if (fw_size <= 0) { 2989 error_report("Could not load LPAR firmware '%s'", filename); 2990 exit(1); 2991 } 2992 g_free(filename); 2993 2994 /* FIXME: Should register things through the MachineState's qdev 2995 * interface, this is a legacy from the sPAPREnvironment structure 2996 * which predated MachineState but had a similar function */ 2997 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2998 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 2999 &savevm_htab_handlers, spapr); 3000 3001 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 3002 3003 qemu_register_boot_set(spapr_boot_set, spapr); 3004 3005 /* 3006 * Nothing needs to be done to resume a suspended guest because 3007 * suspending does not change the machine state, so no need for 3008 * a ->wakeup method. 3009 */ 3010 qemu_register_wakeup_support(); 3011 3012 if (kvm_enabled()) { 3013 /* to stop and start vmclock */ 3014 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3015 &spapr->tb); 3016 3017 kvmppc_spapr_enable_inkernel_multitce(); 3018 } 3019 3020 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3021 } 3022 3023 #define DEFAULT_KVM_TYPE "auto" 3024 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3025 { 3026 /* 3027 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to 3028 * accomodate the 'HV' and 'PV' formats that exists in the 3029 * wild. The 'auto' mode is being introduced already as 3030 * lower-case, thus we don't need to bother checking for 3031 * "AUTO". 3032 */ 3033 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) { 3034 return 0; 3035 } 3036 3037 if (!g_ascii_strcasecmp(vm_type, "hv")) { 3038 return 1; 3039 } 3040 3041 if (!g_ascii_strcasecmp(vm_type, "pr")) { 3042 return 2; 3043 } 3044 3045 error_report("Unknown kvm-type specified '%s'", vm_type); 3046 exit(1); 3047 } 3048 3049 /* 3050 * Implementation of an interface to adjust firmware path 3051 * for the bootindex property handling. 3052 */ 3053 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3054 DeviceState *dev) 3055 { 3056 #define CAST(type, obj, name) \ 3057 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3058 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3059 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3060 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3061 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3062 3063 if (d) { 3064 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3065 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3066 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3067 3068 if (spapr) { 3069 /* 3070 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3071 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3072 * 0x8000 | (target << 8) | (bus << 5) | lun 3073 * (see the "Logical unit addressing format" table in SAM5) 3074 */ 3075 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3076 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3077 (uint64_t)id << 48); 3078 } else if (virtio) { 3079 /* 3080 * We use SRP luns of the form 01000000 | (target << 8) | lun 3081 * in the top 32 bits of the 64-bit LUN 3082 * Note: the quote above is from SLOF and it is wrong, 3083 * the actual binding is: 3084 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3085 */ 3086 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3087 if (d->lun >= 256) { 3088 /* Use the LUN "flat space addressing method" */ 3089 id |= 0x4000; 3090 } 3091 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3092 (uint64_t)id << 32); 3093 } else if (usb) { 3094 /* 3095 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3096 * in the top 32 bits of the 64-bit LUN 3097 */ 3098 unsigned usb_port = atoi(usb->port->path); 3099 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3100 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3101 (uint64_t)id << 32); 3102 } 3103 } 3104 3105 /* 3106 * SLOF probes the USB devices, and if it recognizes that the device is a 3107 * storage device, it changes its name to "storage" instead of "usb-host", 3108 * and additionally adds a child node for the SCSI LUN, so the correct 3109 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3110 */ 3111 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3112 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3113 if (usb_host_dev_is_scsi_storage(usbdev)) { 3114 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3115 } 3116 } 3117 3118 if (phb) { 3119 /* Replace "pci" with "pci@800000020000000" */ 3120 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3121 } 3122 3123 if (vsc) { 3124 /* Same logic as virtio above */ 3125 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3126 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3127 } 3128 3129 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3130 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3131 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3132 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3133 } 3134 3135 if (pcidev) { 3136 return spapr_pci_fw_dev_name(pcidev); 3137 } 3138 3139 return NULL; 3140 } 3141 3142 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3143 { 3144 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3145 3146 return g_strdup(spapr->kvm_type); 3147 } 3148 3149 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3150 { 3151 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3152 3153 g_free(spapr->kvm_type); 3154 spapr->kvm_type = g_strdup(value); 3155 } 3156 3157 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3158 { 3159 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3160 3161 return spapr->use_hotplug_event_source; 3162 } 3163 3164 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3165 Error **errp) 3166 { 3167 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3168 3169 spapr->use_hotplug_event_source = value; 3170 } 3171 3172 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3173 { 3174 return true; 3175 } 3176 3177 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3178 { 3179 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3180 3181 switch (spapr->resize_hpt) { 3182 case SPAPR_RESIZE_HPT_DEFAULT: 3183 return g_strdup("default"); 3184 case SPAPR_RESIZE_HPT_DISABLED: 3185 return g_strdup("disabled"); 3186 case SPAPR_RESIZE_HPT_ENABLED: 3187 return g_strdup("enabled"); 3188 case SPAPR_RESIZE_HPT_REQUIRED: 3189 return g_strdup("required"); 3190 } 3191 g_assert_not_reached(); 3192 } 3193 3194 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3195 { 3196 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3197 3198 if (strcmp(value, "default") == 0) { 3199 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3200 } else if (strcmp(value, "disabled") == 0) { 3201 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3202 } else if (strcmp(value, "enabled") == 0) { 3203 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3204 } else if (strcmp(value, "required") == 0) { 3205 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3206 } else { 3207 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3208 } 3209 } 3210 3211 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3212 { 3213 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3214 3215 if (spapr->irq == &spapr_irq_xics_legacy) { 3216 return g_strdup("legacy"); 3217 } else if (spapr->irq == &spapr_irq_xics) { 3218 return g_strdup("xics"); 3219 } else if (spapr->irq == &spapr_irq_xive) { 3220 return g_strdup("xive"); 3221 } else if (spapr->irq == &spapr_irq_dual) { 3222 return g_strdup("dual"); 3223 } 3224 g_assert_not_reached(); 3225 } 3226 3227 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3228 { 3229 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3230 3231 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3232 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3233 return; 3234 } 3235 3236 /* The legacy IRQ backend can not be set */ 3237 if (strcmp(value, "xics") == 0) { 3238 spapr->irq = &spapr_irq_xics; 3239 } else if (strcmp(value, "xive") == 0) { 3240 spapr->irq = &spapr_irq_xive; 3241 } else if (strcmp(value, "dual") == 0) { 3242 spapr->irq = &spapr_irq_dual; 3243 } else { 3244 error_setg(errp, "Bad value for \"ic-mode\" property"); 3245 } 3246 } 3247 3248 static char *spapr_get_host_model(Object *obj, Error **errp) 3249 { 3250 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3251 3252 return g_strdup(spapr->host_model); 3253 } 3254 3255 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3256 { 3257 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3258 3259 g_free(spapr->host_model); 3260 spapr->host_model = g_strdup(value); 3261 } 3262 3263 static char *spapr_get_host_serial(Object *obj, Error **errp) 3264 { 3265 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3266 3267 return g_strdup(spapr->host_serial); 3268 } 3269 3270 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3271 { 3272 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3273 3274 g_free(spapr->host_serial); 3275 spapr->host_serial = g_strdup(value); 3276 } 3277 3278 static void spapr_instance_init(Object *obj) 3279 { 3280 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3281 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3282 MachineState *ms = MACHINE(spapr); 3283 MachineClass *mc = MACHINE_GET_CLASS(ms); 3284 3285 /* 3286 * NVDIMM support went live in 5.1 without considering that, in 3287 * other archs, the user needs to enable NVDIMM support with the 3288 * 'nvdimm' machine option and the default behavior is NVDIMM 3289 * support disabled. It is too late to roll back to the standard 3290 * behavior without breaking 5.1 guests. 3291 */ 3292 if (mc->nvdimm_supported) { 3293 ms->nvdimms_state->is_enabled = true; 3294 } 3295 3296 spapr->htab_fd = -1; 3297 spapr->use_hotplug_event_source = true; 3298 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE); 3299 object_property_add_str(obj, "kvm-type", 3300 spapr_get_kvm_type, spapr_set_kvm_type); 3301 object_property_set_description(obj, "kvm-type", 3302 "Specifies the KVM virtualization mode (auto," 3303 " hv, pr). Defaults to 'auto'. This mode will use" 3304 " any available KVM module loaded in the host," 3305 " where kvm_hv takes precedence if both kvm_hv and" 3306 " kvm_pr are loaded."); 3307 object_property_add_bool(obj, "modern-hotplug-events", 3308 spapr_get_modern_hotplug_events, 3309 spapr_set_modern_hotplug_events); 3310 object_property_set_description(obj, "modern-hotplug-events", 3311 "Use dedicated hotplug event mechanism in" 3312 " place of standard EPOW events when possible" 3313 " (required for memory hot-unplug support)"); 3314 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3315 "Maximum permitted CPU compatibility mode"); 3316 3317 object_property_add_str(obj, "resize-hpt", 3318 spapr_get_resize_hpt, spapr_set_resize_hpt); 3319 object_property_set_description(obj, "resize-hpt", 3320 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3321 object_property_add_uint32_ptr(obj, "vsmt", 3322 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3323 object_property_set_description(obj, "vsmt", 3324 "Virtual SMT: KVM behaves as if this were" 3325 " the host's SMT mode"); 3326 3327 object_property_add_bool(obj, "vfio-no-msix-emulation", 3328 spapr_get_msix_emulation, NULL); 3329 3330 object_property_add_uint64_ptr(obj, "kernel-addr", 3331 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3332 object_property_set_description(obj, "kernel-addr", 3333 stringify(KERNEL_LOAD_ADDR) 3334 " for -kernel is the default"); 3335 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3336 /* The machine class defines the default interrupt controller mode */ 3337 spapr->irq = smc->irq; 3338 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3339 spapr_set_ic_mode); 3340 object_property_set_description(obj, "ic-mode", 3341 "Specifies the interrupt controller mode (xics, xive, dual)"); 3342 3343 object_property_add_str(obj, "host-model", 3344 spapr_get_host_model, spapr_set_host_model); 3345 object_property_set_description(obj, "host-model", 3346 "Host model to advertise in guest device tree"); 3347 object_property_add_str(obj, "host-serial", 3348 spapr_get_host_serial, spapr_set_host_serial); 3349 object_property_set_description(obj, "host-serial", 3350 "Host serial number to advertise in guest device tree"); 3351 } 3352 3353 static void spapr_machine_finalizefn(Object *obj) 3354 { 3355 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3356 3357 g_free(spapr->kvm_type); 3358 } 3359 3360 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3361 { 3362 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3363 PowerPCCPU *cpu = POWERPC_CPU(cs); 3364 CPUPPCState *env = &cpu->env; 3365 3366 cpu_synchronize_state(cs); 3367 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3368 if (spapr->fwnmi_system_reset_addr != -1) { 3369 uint64_t rtas_addr, addr; 3370 3371 /* get rtas addr from fdt */ 3372 rtas_addr = spapr_get_rtas_addr(); 3373 if (!rtas_addr) { 3374 qemu_system_guest_panicked(NULL); 3375 return; 3376 } 3377 3378 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3379 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3380 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3381 env->gpr[3] = addr; 3382 } 3383 ppc_cpu_do_system_reset(cs); 3384 if (spapr->fwnmi_system_reset_addr != -1) { 3385 env->nip = spapr->fwnmi_system_reset_addr; 3386 } 3387 } 3388 3389 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3390 { 3391 CPUState *cs; 3392 3393 CPU_FOREACH(cs) { 3394 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3395 } 3396 } 3397 3398 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3399 void *fdt, int *fdt_start_offset, Error **errp) 3400 { 3401 uint64_t addr; 3402 uint32_t node; 3403 3404 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3405 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3406 &error_abort); 3407 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3408 SPAPR_MEMORY_BLOCK_SIZE); 3409 return 0; 3410 } 3411 3412 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3413 bool dedicated_hp_event_source) 3414 { 3415 SpaprDrc *drc; 3416 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3417 int i; 3418 uint64_t addr = addr_start; 3419 bool hotplugged = spapr_drc_hotplugged(dev); 3420 3421 for (i = 0; i < nr_lmbs; i++) { 3422 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3423 addr / SPAPR_MEMORY_BLOCK_SIZE); 3424 g_assert(drc); 3425 3426 /* 3427 * memory_device_get_free_addr() provided a range of free addresses 3428 * that doesn't overlap with any existing mapping at pre-plug. The 3429 * corresponding LMB DRCs are thus assumed to be all attachable. 3430 */ 3431 spapr_drc_attach(drc, dev); 3432 if (!hotplugged) { 3433 spapr_drc_reset(drc); 3434 } 3435 addr += SPAPR_MEMORY_BLOCK_SIZE; 3436 } 3437 /* send hotplug notification to the 3438 * guest only in case of hotplugged memory 3439 */ 3440 if (hotplugged) { 3441 if (dedicated_hp_event_source) { 3442 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3443 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3444 g_assert(drc); 3445 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3446 nr_lmbs, 3447 spapr_drc_index(drc)); 3448 } else { 3449 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3450 nr_lmbs); 3451 } 3452 } 3453 } 3454 3455 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3456 { 3457 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3458 PCDIMMDevice *dimm = PC_DIMM(dev); 3459 uint64_t size, addr; 3460 int64_t slot; 3461 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3462 3463 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3464 3465 pc_dimm_plug(dimm, MACHINE(ms)); 3466 3467 if (!is_nvdimm) { 3468 addr = object_property_get_uint(OBJECT(dimm), 3469 PC_DIMM_ADDR_PROP, &error_abort); 3470 spapr_add_lmbs(dev, addr, size, 3471 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT)); 3472 } else { 3473 slot = object_property_get_int(OBJECT(dimm), 3474 PC_DIMM_SLOT_PROP, &error_abort); 3475 /* We should have valid slot number at this point */ 3476 g_assert(slot >= 0); 3477 spapr_add_nvdimm(dev, slot); 3478 } 3479 } 3480 3481 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3482 Error **errp) 3483 { 3484 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3485 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3486 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3487 PCDIMMDevice *dimm = PC_DIMM(dev); 3488 Error *local_err = NULL; 3489 uint64_t size; 3490 Object *memdev; 3491 hwaddr pagesize; 3492 3493 if (!smc->dr_lmb_enabled) { 3494 error_setg(errp, "Memory hotplug not supported for this machine"); 3495 return; 3496 } 3497 3498 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3499 if (local_err) { 3500 error_propagate(errp, local_err); 3501 return; 3502 } 3503 3504 if (is_nvdimm) { 3505 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3506 return; 3507 } 3508 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3509 error_setg(errp, "Hotplugged memory size must be a multiple of " 3510 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3511 return; 3512 } 3513 3514 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3515 &error_abort); 3516 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3517 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3518 return; 3519 } 3520 3521 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3522 } 3523 3524 struct SpaprDimmState { 3525 PCDIMMDevice *dimm; 3526 uint32_t nr_lmbs; 3527 QTAILQ_ENTRY(SpaprDimmState) next; 3528 }; 3529 3530 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3531 PCDIMMDevice *dimm) 3532 { 3533 SpaprDimmState *dimm_state = NULL; 3534 3535 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3536 if (dimm_state->dimm == dimm) { 3537 break; 3538 } 3539 } 3540 return dimm_state; 3541 } 3542 3543 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3544 uint32_t nr_lmbs, 3545 PCDIMMDevice *dimm) 3546 { 3547 SpaprDimmState *ds = NULL; 3548 3549 /* 3550 * If this request is for a DIMM whose removal had failed earlier 3551 * (due to guest's refusal to remove the LMBs), we would have this 3552 * dimm already in the pending_dimm_unplugs list. In that 3553 * case don't add again. 3554 */ 3555 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3556 if (!ds) { 3557 ds = g_malloc0(sizeof(SpaprDimmState)); 3558 ds->nr_lmbs = nr_lmbs; 3559 ds->dimm = dimm; 3560 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3561 } 3562 return ds; 3563 } 3564 3565 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3566 SpaprDimmState *dimm_state) 3567 { 3568 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3569 g_free(dimm_state); 3570 } 3571 3572 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3573 PCDIMMDevice *dimm) 3574 { 3575 SpaprDrc *drc; 3576 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3577 &error_abort); 3578 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3579 uint32_t avail_lmbs = 0; 3580 uint64_t addr_start, addr; 3581 int i; 3582 3583 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3584 &error_abort); 3585 3586 addr = addr_start; 3587 for (i = 0; i < nr_lmbs; i++) { 3588 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3589 addr / SPAPR_MEMORY_BLOCK_SIZE); 3590 g_assert(drc); 3591 if (drc->dev) { 3592 avail_lmbs++; 3593 } 3594 addr += SPAPR_MEMORY_BLOCK_SIZE; 3595 } 3596 3597 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3598 } 3599 3600 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev) 3601 { 3602 SpaprDimmState *ds; 3603 PCDIMMDevice *dimm; 3604 SpaprDrc *drc; 3605 uint32_t nr_lmbs; 3606 uint64_t size, addr_start, addr; 3607 g_autofree char *qapi_error = NULL; 3608 int i; 3609 3610 if (!dev) { 3611 return; 3612 } 3613 3614 dimm = PC_DIMM(dev); 3615 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3616 3617 /* 3618 * 'ds == NULL' would mean that the DIMM doesn't have a pending 3619 * unplug state, but one of its DRC is marked as unplug_requested. 3620 * This is bad and weird enough to g_assert() out. 3621 */ 3622 g_assert(ds); 3623 3624 spapr_pending_dimm_unplugs_remove(spapr, ds); 3625 3626 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3627 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3628 3629 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3630 &error_abort); 3631 3632 addr = addr_start; 3633 for (i = 0; i < nr_lmbs; i++) { 3634 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3635 addr / SPAPR_MEMORY_BLOCK_SIZE); 3636 g_assert(drc); 3637 3638 drc->unplug_requested = false; 3639 addr += SPAPR_MEMORY_BLOCK_SIZE; 3640 } 3641 3642 /* 3643 * Tell QAPI that something happened and the memory 3644 * hotunplug wasn't successful. 3645 */ 3646 qapi_error = g_strdup_printf("Memory hotunplug rejected by the guest " 3647 "for device %s", dev->id); 3648 qapi_event_send_mem_unplug_error(dev->id, qapi_error); 3649 } 3650 3651 /* Callback to be called during DRC release. */ 3652 void spapr_lmb_release(DeviceState *dev) 3653 { 3654 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3655 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3656 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3657 3658 /* This information will get lost if a migration occurs 3659 * during the unplug process. In this case recover it. */ 3660 if (ds == NULL) { 3661 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3662 g_assert(ds); 3663 /* The DRC being examined by the caller at least must be counted */ 3664 g_assert(ds->nr_lmbs); 3665 } 3666 3667 if (--ds->nr_lmbs) { 3668 return; 3669 } 3670 3671 /* 3672 * Now that all the LMBs have been removed by the guest, call the 3673 * unplug handler chain. This can never fail. 3674 */ 3675 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3676 object_unparent(OBJECT(dev)); 3677 } 3678 3679 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3680 { 3681 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3682 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3683 3684 /* We really shouldn't get this far without anything to unplug */ 3685 g_assert(ds); 3686 3687 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3688 qdev_unrealize(dev); 3689 spapr_pending_dimm_unplugs_remove(spapr, ds); 3690 } 3691 3692 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3693 DeviceState *dev, Error **errp) 3694 { 3695 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3696 PCDIMMDevice *dimm = PC_DIMM(dev); 3697 uint32_t nr_lmbs; 3698 uint64_t size, addr_start, addr; 3699 int i; 3700 SpaprDrc *drc; 3701 3702 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3703 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3704 return; 3705 } 3706 3707 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3708 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3709 3710 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3711 &error_abort); 3712 3713 /* 3714 * An existing pending dimm state for this DIMM means that there is an 3715 * unplug operation in progress, waiting for the spapr_lmb_release 3716 * callback to complete the job (BQL can't cover that far). In this case, 3717 * bail out to avoid detaching DRCs that were already released. 3718 */ 3719 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3720 error_setg(errp, "Memory unplug already in progress for device %s", 3721 dev->id); 3722 return; 3723 } 3724 3725 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3726 3727 addr = addr_start; 3728 for (i = 0; i < nr_lmbs; i++) { 3729 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3730 addr / SPAPR_MEMORY_BLOCK_SIZE); 3731 g_assert(drc); 3732 3733 spapr_drc_unplug_request(drc); 3734 addr += SPAPR_MEMORY_BLOCK_SIZE; 3735 } 3736 3737 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3738 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3739 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3740 nr_lmbs, spapr_drc_index(drc)); 3741 } 3742 3743 /* Callback to be called during DRC release. */ 3744 void spapr_core_release(DeviceState *dev) 3745 { 3746 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3747 3748 /* Call the unplug handler chain. This can never fail. */ 3749 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3750 object_unparent(OBJECT(dev)); 3751 } 3752 3753 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3754 { 3755 MachineState *ms = MACHINE(hotplug_dev); 3756 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3757 CPUCore *cc = CPU_CORE(dev); 3758 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3759 3760 if (smc->pre_2_10_has_unused_icps) { 3761 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3762 int i; 3763 3764 for (i = 0; i < cc->nr_threads; i++) { 3765 CPUState *cs = CPU(sc->threads[i]); 3766 3767 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3768 } 3769 } 3770 3771 assert(core_slot); 3772 core_slot->cpu = NULL; 3773 qdev_unrealize(dev); 3774 } 3775 3776 static 3777 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3778 Error **errp) 3779 { 3780 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3781 int index; 3782 SpaprDrc *drc; 3783 CPUCore *cc = CPU_CORE(dev); 3784 3785 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3786 error_setg(errp, "Unable to find CPU core with core-id: %d", 3787 cc->core_id); 3788 return; 3789 } 3790 if (index == 0) { 3791 error_setg(errp, "Boot CPU core may not be unplugged"); 3792 return; 3793 } 3794 3795 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3796 spapr_vcpu_id(spapr, cc->core_id)); 3797 g_assert(drc); 3798 3799 if (!spapr_drc_unplug_requested(drc)) { 3800 spapr_drc_unplug_request(drc); 3801 } 3802 3803 /* 3804 * spapr_hotplug_req_remove_by_index is left unguarded, out of the 3805 * "!spapr_drc_unplug_requested" check, to allow for multiple IRQ 3806 * pulses removing the same CPU. Otherwise, in an failed hotunplug 3807 * attempt (e.g. the kernel will refuse to remove the last online 3808 * CPU), we will never attempt it again because unplug_requested 3809 * will still be 'true' in that case. 3810 */ 3811 spapr_hotplug_req_remove_by_index(drc); 3812 } 3813 3814 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3815 void *fdt, int *fdt_start_offset, Error **errp) 3816 { 3817 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3818 CPUState *cs = CPU(core->threads[0]); 3819 PowerPCCPU *cpu = POWERPC_CPU(cs); 3820 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3821 int id = spapr_get_vcpu_id(cpu); 3822 g_autofree char *nodename = NULL; 3823 int offset; 3824 3825 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3826 offset = fdt_add_subnode(fdt, 0, nodename); 3827 3828 spapr_dt_cpu(cs, fdt, offset, spapr); 3829 3830 /* 3831 * spapr_dt_cpu() does not fill the 'name' property in the 3832 * CPU node. The function is called during boot process, before 3833 * and after CAS, and overwriting the 'name' property written 3834 * by SLOF is not allowed. 3835 * 3836 * Write it manually after spapr_dt_cpu(). This makes the hotplug 3837 * CPUs more compatible with the coldplugged ones, which have 3838 * the 'name' property. Linux Kernel also relies on this 3839 * property to identify CPU nodes. 3840 */ 3841 _FDT((fdt_setprop_string(fdt, offset, "name", nodename))); 3842 3843 *fdt_start_offset = offset; 3844 return 0; 3845 } 3846 3847 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3848 { 3849 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3850 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3851 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3852 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3853 CPUCore *cc = CPU_CORE(dev); 3854 CPUState *cs; 3855 SpaprDrc *drc; 3856 CPUArchId *core_slot; 3857 int index; 3858 bool hotplugged = spapr_drc_hotplugged(dev); 3859 int i; 3860 3861 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3862 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */ 3863 3864 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3865 spapr_vcpu_id(spapr, cc->core_id)); 3866 3867 g_assert(drc || !mc->has_hotpluggable_cpus); 3868 3869 if (drc) { 3870 /* 3871 * spapr_core_pre_plug() already buys us this is a brand new 3872 * core being plugged into a free slot. Nothing should already 3873 * be attached to the corresponding DRC. 3874 */ 3875 spapr_drc_attach(drc, dev); 3876 3877 if (hotplugged) { 3878 /* 3879 * Send hotplug notification interrupt to the guest only 3880 * in case of hotplugged CPUs. 3881 */ 3882 spapr_hotplug_req_add_by_index(drc); 3883 } else { 3884 spapr_drc_reset(drc); 3885 } 3886 } 3887 3888 core_slot->cpu = OBJECT(dev); 3889 3890 /* 3891 * Set compatibility mode to match the boot CPU, which was either set 3892 * by the machine reset code or by CAS. This really shouldn't fail at 3893 * this point. 3894 */ 3895 if (hotplugged) { 3896 for (i = 0; i < cc->nr_threads; i++) { 3897 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3898 &error_abort); 3899 } 3900 } 3901 3902 if (smc->pre_2_10_has_unused_icps) { 3903 for (i = 0; i < cc->nr_threads; i++) { 3904 cs = CPU(core->threads[i]); 3905 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3906 } 3907 } 3908 } 3909 3910 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3911 Error **errp) 3912 { 3913 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3914 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3915 CPUCore *cc = CPU_CORE(dev); 3916 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3917 const char *type = object_get_typename(OBJECT(dev)); 3918 CPUArchId *core_slot; 3919 int index; 3920 unsigned int smp_threads = machine->smp.threads; 3921 3922 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3923 error_setg(errp, "CPU hotplug not supported for this machine"); 3924 return; 3925 } 3926 3927 if (strcmp(base_core_type, type)) { 3928 error_setg(errp, "CPU core type should be %s", base_core_type); 3929 return; 3930 } 3931 3932 if (cc->core_id % smp_threads) { 3933 error_setg(errp, "invalid core id %d", cc->core_id); 3934 return; 3935 } 3936 3937 /* 3938 * In general we should have homogeneous threads-per-core, but old 3939 * (pre hotplug support) machine types allow the last core to have 3940 * reduced threads as a compatibility hack for when we allowed 3941 * total vcpus not a multiple of threads-per-core. 3942 */ 3943 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3944 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 3945 smp_threads); 3946 return; 3947 } 3948 3949 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3950 if (!core_slot) { 3951 error_setg(errp, "core id %d out of range", cc->core_id); 3952 return; 3953 } 3954 3955 if (core_slot->cpu) { 3956 error_setg(errp, "core %d already populated", cc->core_id); 3957 return; 3958 } 3959 3960 numa_cpu_pre_plug(core_slot, dev, errp); 3961 } 3962 3963 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3964 void *fdt, int *fdt_start_offset, Error **errp) 3965 { 3966 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3967 int intc_phandle; 3968 3969 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3970 if (intc_phandle <= 0) { 3971 return -1; 3972 } 3973 3974 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 3975 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3976 return -1; 3977 } 3978 3979 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3980 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3981 3982 return 0; 3983 } 3984 3985 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3986 Error **errp) 3987 { 3988 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3989 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3990 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3991 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3992 SpaprDrc *drc; 3993 3994 if (dev->hotplugged && !smc->dr_phb_enabled) { 3995 error_setg(errp, "PHB hotplug not supported for this machine"); 3996 return false; 3997 } 3998 3999 if (sphb->index == (uint32_t)-1) { 4000 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 4001 return false; 4002 } 4003 4004 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4005 if (drc && drc->dev) { 4006 error_setg(errp, "PHB %d already attached", sphb->index); 4007 return false; 4008 } 4009 4010 /* 4011 * This will check that sphb->index doesn't exceed the maximum number of 4012 * PHBs for the current machine type. 4013 */ 4014 return 4015 smc->phb_placement(spapr, sphb->index, 4016 &sphb->buid, &sphb->io_win_addr, 4017 &sphb->mem_win_addr, &sphb->mem64_win_addr, 4018 windows_supported, sphb->dma_liobn, 4019 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 4020 errp); 4021 } 4022 4023 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4024 { 4025 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4026 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4027 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4028 SpaprDrc *drc; 4029 bool hotplugged = spapr_drc_hotplugged(dev); 4030 4031 if (!smc->dr_phb_enabled) { 4032 return; 4033 } 4034 4035 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4036 /* hotplug hooks should check it's enabled before getting this far */ 4037 assert(drc); 4038 4039 /* spapr_phb_pre_plug() already checked the DRC is attachable */ 4040 spapr_drc_attach(drc, dev); 4041 4042 if (hotplugged) { 4043 spapr_hotplug_req_add_by_index(drc); 4044 } else { 4045 spapr_drc_reset(drc); 4046 } 4047 } 4048 4049 void spapr_phb_release(DeviceState *dev) 4050 { 4051 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4052 4053 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4054 object_unparent(OBJECT(dev)); 4055 } 4056 4057 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4058 { 4059 qdev_unrealize(dev); 4060 } 4061 4062 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4063 DeviceState *dev, Error **errp) 4064 { 4065 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4066 SpaprDrc *drc; 4067 4068 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4069 assert(drc); 4070 4071 if (!spapr_drc_unplug_requested(drc)) { 4072 spapr_drc_unplug_request(drc); 4073 spapr_hotplug_req_remove_by_index(drc); 4074 } else { 4075 error_setg(errp, 4076 "PCI Host Bridge unplug already in progress for device %s", 4077 dev->id); 4078 } 4079 } 4080 4081 static 4082 bool spapr_tpm_proxy_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4083 Error **errp) 4084 { 4085 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4086 4087 if (spapr->tpm_proxy != NULL) { 4088 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4089 return false; 4090 } 4091 4092 return true; 4093 } 4094 4095 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4096 { 4097 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4098 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4099 4100 /* Already checked in spapr_tpm_proxy_pre_plug() */ 4101 g_assert(spapr->tpm_proxy == NULL); 4102 4103 spapr->tpm_proxy = tpm_proxy; 4104 } 4105 4106 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4107 { 4108 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4109 4110 qdev_unrealize(dev); 4111 object_unparent(OBJECT(dev)); 4112 spapr->tpm_proxy = NULL; 4113 } 4114 4115 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4116 DeviceState *dev, Error **errp) 4117 { 4118 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4119 spapr_memory_plug(hotplug_dev, dev); 4120 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4121 spapr_core_plug(hotplug_dev, dev); 4122 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4123 spapr_phb_plug(hotplug_dev, dev); 4124 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4125 spapr_tpm_proxy_plug(hotplug_dev, dev); 4126 } 4127 } 4128 4129 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4130 DeviceState *dev, Error **errp) 4131 { 4132 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4133 spapr_memory_unplug(hotplug_dev, dev); 4134 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4135 spapr_core_unplug(hotplug_dev, dev); 4136 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4137 spapr_phb_unplug(hotplug_dev, dev); 4138 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4139 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4140 } 4141 } 4142 4143 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr) 4144 { 4145 return spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT) || 4146 /* 4147 * CAS will process all pending unplug requests. 4148 * 4149 * HACK: a guest could theoretically have cleared all bits in OV5, 4150 * but none of the guests we care for do. 4151 */ 4152 spapr_ovec_empty(spapr->ov5_cas); 4153 } 4154 4155 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4156 DeviceState *dev, Error **errp) 4157 { 4158 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4159 MachineClass *mc = MACHINE_GET_CLASS(sms); 4160 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4161 4162 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4163 if (spapr_memory_hot_unplug_supported(sms)) { 4164 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4165 } else { 4166 error_setg(errp, "Memory hot unplug not supported for this guest"); 4167 } 4168 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4169 if (!mc->has_hotpluggable_cpus) { 4170 error_setg(errp, "CPU hot unplug not supported on this machine"); 4171 return; 4172 } 4173 spapr_core_unplug_request(hotplug_dev, dev, errp); 4174 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4175 if (!smc->dr_phb_enabled) { 4176 error_setg(errp, "PHB hot unplug not supported on this machine"); 4177 return; 4178 } 4179 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4180 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4181 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4182 } 4183 } 4184 4185 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4186 DeviceState *dev, Error **errp) 4187 { 4188 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4189 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4190 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4191 spapr_core_pre_plug(hotplug_dev, dev, errp); 4192 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4193 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4194 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4195 spapr_tpm_proxy_pre_plug(hotplug_dev, dev, errp); 4196 } 4197 } 4198 4199 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4200 DeviceState *dev) 4201 { 4202 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4203 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4204 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4205 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4206 return HOTPLUG_HANDLER(machine); 4207 } 4208 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4209 PCIDevice *pcidev = PCI_DEVICE(dev); 4210 PCIBus *root = pci_device_root_bus(pcidev); 4211 SpaprPhbState *phb = 4212 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4213 TYPE_SPAPR_PCI_HOST_BRIDGE); 4214 4215 if (phb) { 4216 return HOTPLUG_HANDLER(phb); 4217 } 4218 } 4219 return NULL; 4220 } 4221 4222 static CpuInstanceProperties 4223 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4224 { 4225 CPUArchId *core_slot; 4226 MachineClass *mc = MACHINE_GET_CLASS(machine); 4227 4228 /* make sure possible_cpu are intialized */ 4229 mc->possible_cpu_arch_ids(machine); 4230 /* get CPU core slot containing thread that matches cpu_index */ 4231 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4232 assert(core_slot); 4233 return core_slot->props; 4234 } 4235 4236 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4237 { 4238 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4239 } 4240 4241 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4242 { 4243 int i; 4244 unsigned int smp_threads = machine->smp.threads; 4245 unsigned int smp_cpus = machine->smp.cpus; 4246 const char *core_type; 4247 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4248 MachineClass *mc = MACHINE_GET_CLASS(machine); 4249 4250 if (!mc->has_hotpluggable_cpus) { 4251 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4252 } 4253 if (machine->possible_cpus) { 4254 assert(machine->possible_cpus->len == spapr_max_cores); 4255 return machine->possible_cpus; 4256 } 4257 4258 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4259 if (!core_type) { 4260 error_report("Unable to find sPAPR CPU Core definition"); 4261 exit(1); 4262 } 4263 4264 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4265 sizeof(CPUArchId) * spapr_max_cores); 4266 machine->possible_cpus->len = spapr_max_cores; 4267 for (i = 0; i < machine->possible_cpus->len; i++) { 4268 int core_id = i * smp_threads; 4269 4270 machine->possible_cpus->cpus[i].type = core_type; 4271 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4272 machine->possible_cpus->cpus[i].arch_id = core_id; 4273 machine->possible_cpus->cpus[i].props.has_core_id = true; 4274 machine->possible_cpus->cpus[i].props.core_id = core_id; 4275 } 4276 return machine->possible_cpus; 4277 } 4278 4279 static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4280 uint64_t *buid, hwaddr *pio, 4281 hwaddr *mmio32, hwaddr *mmio64, 4282 unsigned n_dma, uint32_t *liobns, 4283 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4284 { 4285 /* 4286 * New-style PHB window placement. 4287 * 4288 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4289 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4290 * windows. 4291 * 4292 * Some guest kernels can't work with MMIO windows above 1<<46 4293 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4294 * 4295 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4296 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4297 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4298 * 1TiB 64-bit MMIO windows for each PHB. 4299 */ 4300 const uint64_t base_buid = 0x800000020000000ULL; 4301 int i; 4302 4303 /* Sanity check natural alignments */ 4304 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4305 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4306 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4307 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4308 /* Sanity check bounds */ 4309 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4310 SPAPR_PCI_MEM32_WIN_SIZE); 4311 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4312 SPAPR_PCI_MEM64_WIN_SIZE); 4313 4314 if (index >= SPAPR_MAX_PHBS) { 4315 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4316 SPAPR_MAX_PHBS - 1); 4317 return false; 4318 } 4319 4320 *buid = base_buid + index; 4321 for (i = 0; i < n_dma; ++i) { 4322 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4323 } 4324 4325 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4326 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4327 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4328 4329 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4330 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4331 return true; 4332 } 4333 4334 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4335 { 4336 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4337 4338 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4339 } 4340 4341 static void spapr_ics_resend(XICSFabric *dev) 4342 { 4343 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4344 4345 ics_resend(spapr->ics); 4346 } 4347 4348 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4349 { 4350 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4351 4352 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4353 } 4354 4355 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4356 Monitor *mon) 4357 { 4358 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4359 4360 spapr_irq_print_info(spapr, mon); 4361 monitor_printf(mon, "irqchip: %s\n", 4362 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4363 } 4364 4365 /* 4366 * This is a XIVE only operation 4367 */ 4368 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4369 uint8_t nvt_blk, uint32_t nvt_idx, 4370 bool cam_ignore, uint8_t priority, 4371 uint32_t logic_serv, XiveTCTXMatch *match) 4372 { 4373 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4374 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4375 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4376 int count; 4377 4378 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4379 priority, logic_serv, match); 4380 if (count < 0) { 4381 return count; 4382 } 4383 4384 /* 4385 * When we implement the save and restore of the thread interrupt 4386 * contexts in the enter/exit CPU handlers of the machine and the 4387 * escalations in QEMU, we should be able to handle non dispatched 4388 * vCPUs. 4389 * 4390 * Until this is done, the sPAPR machine should find at least one 4391 * matching context always. 4392 */ 4393 if (count == 0) { 4394 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4395 nvt_blk, nvt_idx); 4396 } 4397 4398 return count; 4399 } 4400 4401 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4402 { 4403 return cpu->vcpu_id; 4404 } 4405 4406 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4407 { 4408 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4409 MachineState *ms = MACHINE(spapr); 4410 int vcpu_id; 4411 4412 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4413 4414 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4415 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4416 error_append_hint(errp, "Adjust the number of cpus to %d " 4417 "or try to raise the number of threads per core\n", 4418 vcpu_id * ms->smp.threads / spapr->vsmt); 4419 return false; 4420 } 4421 4422 cpu->vcpu_id = vcpu_id; 4423 return true; 4424 } 4425 4426 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4427 { 4428 CPUState *cs; 4429 4430 CPU_FOREACH(cs) { 4431 PowerPCCPU *cpu = POWERPC_CPU(cs); 4432 4433 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4434 return cpu; 4435 } 4436 } 4437 4438 return NULL; 4439 } 4440 4441 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4442 { 4443 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4444 4445 /* These are only called by TCG, KVM maintains dispatch state */ 4446 4447 spapr_cpu->prod = false; 4448 if (spapr_cpu->vpa_addr) { 4449 CPUState *cs = CPU(cpu); 4450 uint32_t dispatch; 4451 4452 dispatch = ldl_be_phys(cs->as, 4453 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4454 dispatch++; 4455 if ((dispatch & 1) != 0) { 4456 qemu_log_mask(LOG_GUEST_ERROR, 4457 "VPA: incorrect dispatch counter value for " 4458 "dispatched partition %u, correcting.\n", dispatch); 4459 dispatch++; 4460 } 4461 stl_be_phys(cs->as, 4462 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4463 } 4464 } 4465 4466 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4467 { 4468 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4469 4470 if (spapr_cpu->vpa_addr) { 4471 CPUState *cs = CPU(cpu); 4472 uint32_t dispatch; 4473 4474 dispatch = ldl_be_phys(cs->as, 4475 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4476 dispatch++; 4477 if ((dispatch & 1) != 1) { 4478 qemu_log_mask(LOG_GUEST_ERROR, 4479 "VPA: incorrect dispatch counter value for " 4480 "preempted partition %u, correcting.\n", dispatch); 4481 dispatch++; 4482 } 4483 stl_be_phys(cs->as, 4484 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4485 } 4486 } 4487 4488 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4489 { 4490 MachineClass *mc = MACHINE_CLASS(oc); 4491 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4492 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4493 NMIClass *nc = NMI_CLASS(oc); 4494 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4495 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4496 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4497 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4498 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4499 4500 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4501 mc->ignore_boot_device_suffixes = true; 4502 4503 /* 4504 * We set up the default / latest behaviour here. The class_init 4505 * functions for the specific versioned machine types can override 4506 * these details for backwards compatibility 4507 */ 4508 mc->init = spapr_machine_init; 4509 mc->reset = spapr_machine_reset; 4510 mc->block_default_type = IF_SCSI; 4511 4512 /* 4513 * Setting max_cpus to INT32_MAX. Both KVM and TCG max_cpus values 4514 * should be limited by the host capability instead of hardcoded. 4515 * max_cpus for KVM guests will be checked in kvm_init(), and TCG 4516 * guests are welcome to have as many CPUs as the host are capable 4517 * of emulate. 4518 */ 4519 mc->max_cpus = INT32_MAX; 4520 4521 mc->no_parallel = 1; 4522 mc->default_boot_order = ""; 4523 mc->default_ram_size = 512 * MiB; 4524 mc->default_ram_id = "ppc_spapr.ram"; 4525 mc->default_display = "std"; 4526 mc->kvm_type = spapr_kvm_type; 4527 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4528 mc->pci_allow_0_address = true; 4529 assert(!mc->get_hotplug_handler); 4530 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4531 hc->pre_plug = spapr_machine_device_pre_plug; 4532 hc->plug = spapr_machine_device_plug; 4533 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4534 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4535 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4536 hc->unplug_request = spapr_machine_device_unplug_request; 4537 hc->unplug = spapr_machine_device_unplug; 4538 4539 smc->dr_lmb_enabled = true; 4540 smc->update_dt_enabled = true; 4541 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4542 mc->has_hotpluggable_cpus = true; 4543 mc->nvdimm_supported = true; 4544 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4545 fwc->get_dev_path = spapr_get_fw_dev_path; 4546 nc->nmi_monitor_handler = spapr_nmi; 4547 smc->phb_placement = spapr_phb_placement; 4548 vhc->hypercall = emulate_spapr_hypercall; 4549 vhc->hpt_mask = spapr_hpt_mask; 4550 vhc->map_hptes = spapr_map_hptes; 4551 vhc->unmap_hptes = spapr_unmap_hptes; 4552 vhc->hpte_set_c = spapr_hpte_set_c; 4553 vhc->hpte_set_r = spapr_hpte_set_r; 4554 vhc->get_pate = spapr_get_pate; 4555 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4556 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4557 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4558 xic->ics_get = spapr_ics_get; 4559 xic->ics_resend = spapr_ics_resend; 4560 xic->icp_get = spapr_icp_get; 4561 ispc->print_info = spapr_pic_print_info; 4562 /* Force NUMA node memory size to be a multiple of 4563 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4564 * in which LMBs are represented and hot-added 4565 */ 4566 mc->numa_mem_align_shift = 28; 4567 mc->auto_enable_numa = true; 4568 4569 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4570 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4571 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4572 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4573 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4574 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4575 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4576 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4577 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4578 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4579 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4580 spapr_caps_add_properties(smc); 4581 smc->irq = &spapr_irq_dual; 4582 smc->dr_phb_enabled = true; 4583 smc->linux_pci_probe = true; 4584 smc->smp_threads_vsmt = true; 4585 smc->nr_xirqs = SPAPR_NR_XIRQS; 4586 xfc->match_nvt = spapr_match_nvt; 4587 } 4588 4589 static const TypeInfo spapr_machine_info = { 4590 .name = TYPE_SPAPR_MACHINE, 4591 .parent = TYPE_MACHINE, 4592 .abstract = true, 4593 .instance_size = sizeof(SpaprMachineState), 4594 .instance_init = spapr_instance_init, 4595 .instance_finalize = spapr_machine_finalizefn, 4596 .class_size = sizeof(SpaprMachineClass), 4597 .class_init = spapr_machine_class_init, 4598 .interfaces = (InterfaceInfo[]) { 4599 { TYPE_FW_PATH_PROVIDER }, 4600 { TYPE_NMI }, 4601 { TYPE_HOTPLUG_HANDLER }, 4602 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4603 { TYPE_XICS_FABRIC }, 4604 { TYPE_INTERRUPT_STATS_PROVIDER }, 4605 { TYPE_XIVE_FABRIC }, 4606 { } 4607 }, 4608 }; 4609 4610 static void spapr_machine_latest_class_options(MachineClass *mc) 4611 { 4612 mc->alias = "pseries"; 4613 mc->is_default = true; 4614 } 4615 4616 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4617 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4618 void *data) \ 4619 { \ 4620 MachineClass *mc = MACHINE_CLASS(oc); \ 4621 spapr_machine_##suffix##_class_options(mc); \ 4622 if (latest) { \ 4623 spapr_machine_latest_class_options(mc); \ 4624 } \ 4625 } \ 4626 static const TypeInfo spapr_machine_##suffix##_info = { \ 4627 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4628 .parent = TYPE_SPAPR_MACHINE, \ 4629 .class_init = spapr_machine_##suffix##_class_init, \ 4630 }; \ 4631 static void spapr_machine_register_##suffix(void) \ 4632 { \ 4633 type_register(&spapr_machine_##suffix##_info); \ 4634 } \ 4635 type_init(spapr_machine_register_##suffix) 4636 4637 /* 4638 * pseries-6.1 4639 */ 4640 static void spapr_machine_6_1_class_options(MachineClass *mc) 4641 { 4642 /* Defaults for the latest behaviour inherited from the base class */ 4643 } 4644 4645 DEFINE_SPAPR_MACHINE(6_1, "6.1", true); 4646 4647 /* 4648 * pseries-6.0 4649 */ 4650 static void spapr_machine_6_0_class_options(MachineClass *mc) 4651 { 4652 spapr_machine_6_1_class_options(mc); 4653 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 4654 } 4655 4656 DEFINE_SPAPR_MACHINE(6_0, "6.0", false); 4657 4658 /* 4659 * pseries-5.2 4660 */ 4661 static void spapr_machine_5_2_class_options(MachineClass *mc) 4662 { 4663 spapr_machine_6_0_class_options(mc); 4664 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 4665 } 4666 4667 DEFINE_SPAPR_MACHINE(5_2, "5.2", false); 4668 4669 /* 4670 * pseries-5.1 4671 */ 4672 static void spapr_machine_5_1_class_options(MachineClass *mc) 4673 { 4674 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4675 4676 spapr_machine_5_2_class_options(mc); 4677 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4678 smc->pre_5_2_numa_associativity = true; 4679 } 4680 4681 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4682 4683 /* 4684 * pseries-5.0 4685 */ 4686 static void spapr_machine_5_0_class_options(MachineClass *mc) 4687 { 4688 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4689 static GlobalProperty compat[] = { 4690 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4691 }; 4692 4693 spapr_machine_5_1_class_options(mc); 4694 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4695 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4696 mc->numa_mem_supported = true; 4697 smc->pre_5_1_assoc_refpoints = true; 4698 } 4699 4700 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4701 4702 /* 4703 * pseries-4.2 4704 */ 4705 static void spapr_machine_4_2_class_options(MachineClass *mc) 4706 { 4707 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4708 4709 spapr_machine_5_0_class_options(mc); 4710 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4711 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4712 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4713 smc->rma_limit = 16 * GiB; 4714 mc->nvdimm_supported = false; 4715 } 4716 4717 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4718 4719 /* 4720 * pseries-4.1 4721 */ 4722 static void spapr_machine_4_1_class_options(MachineClass *mc) 4723 { 4724 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4725 static GlobalProperty compat[] = { 4726 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4727 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4728 }; 4729 4730 spapr_machine_4_2_class_options(mc); 4731 smc->linux_pci_probe = false; 4732 smc->smp_threads_vsmt = false; 4733 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4734 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4735 } 4736 4737 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4738 4739 /* 4740 * pseries-4.0 4741 */ 4742 static bool phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4743 uint64_t *buid, hwaddr *pio, 4744 hwaddr *mmio32, hwaddr *mmio64, 4745 unsigned n_dma, uint32_t *liobns, 4746 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4747 { 4748 if (!spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, 4749 liobns, nv2gpa, nv2atsd, errp)) { 4750 return false; 4751 } 4752 4753 *nv2gpa = 0; 4754 *nv2atsd = 0; 4755 return true; 4756 } 4757 static void spapr_machine_4_0_class_options(MachineClass *mc) 4758 { 4759 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4760 4761 spapr_machine_4_1_class_options(mc); 4762 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4763 smc->phb_placement = phb_placement_4_0; 4764 smc->irq = &spapr_irq_xics; 4765 smc->pre_4_1_migration = true; 4766 } 4767 4768 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4769 4770 /* 4771 * pseries-3.1 4772 */ 4773 static void spapr_machine_3_1_class_options(MachineClass *mc) 4774 { 4775 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4776 4777 spapr_machine_4_0_class_options(mc); 4778 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4779 4780 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4781 smc->update_dt_enabled = false; 4782 smc->dr_phb_enabled = false; 4783 smc->broken_host_serial_model = true; 4784 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4785 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4786 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4787 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4788 } 4789 4790 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4791 4792 /* 4793 * pseries-3.0 4794 */ 4795 4796 static void spapr_machine_3_0_class_options(MachineClass *mc) 4797 { 4798 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4799 4800 spapr_machine_3_1_class_options(mc); 4801 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4802 4803 smc->legacy_irq_allocation = true; 4804 smc->nr_xirqs = 0x400; 4805 smc->irq = &spapr_irq_xics_legacy; 4806 } 4807 4808 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4809 4810 /* 4811 * pseries-2.12 4812 */ 4813 static void spapr_machine_2_12_class_options(MachineClass *mc) 4814 { 4815 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4816 static GlobalProperty compat[] = { 4817 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4818 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4819 }; 4820 4821 spapr_machine_3_0_class_options(mc); 4822 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4823 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4824 4825 /* We depend on kvm_enabled() to choose a default value for the 4826 * hpt-max-page-size capability. Of course we can't do it here 4827 * because this is too early and the HW accelerator isn't initialzed 4828 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4829 */ 4830 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4831 } 4832 4833 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4834 4835 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4836 { 4837 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4838 4839 spapr_machine_2_12_class_options(mc); 4840 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4841 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4842 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4843 } 4844 4845 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4846 4847 /* 4848 * pseries-2.11 4849 */ 4850 4851 static void spapr_machine_2_11_class_options(MachineClass *mc) 4852 { 4853 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4854 4855 spapr_machine_2_12_class_options(mc); 4856 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4857 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4858 } 4859 4860 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4861 4862 /* 4863 * pseries-2.10 4864 */ 4865 4866 static void spapr_machine_2_10_class_options(MachineClass *mc) 4867 { 4868 spapr_machine_2_11_class_options(mc); 4869 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4870 } 4871 4872 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4873 4874 /* 4875 * pseries-2.9 4876 */ 4877 4878 static void spapr_machine_2_9_class_options(MachineClass *mc) 4879 { 4880 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4881 static GlobalProperty compat[] = { 4882 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4883 }; 4884 4885 spapr_machine_2_10_class_options(mc); 4886 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4887 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4888 smc->pre_2_10_has_unused_icps = true; 4889 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4890 } 4891 4892 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4893 4894 /* 4895 * pseries-2.8 4896 */ 4897 4898 static void spapr_machine_2_8_class_options(MachineClass *mc) 4899 { 4900 static GlobalProperty compat[] = { 4901 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4902 }; 4903 4904 spapr_machine_2_9_class_options(mc); 4905 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4906 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4907 mc->numa_mem_align_shift = 23; 4908 } 4909 4910 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4911 4912 /* 4913 * pseries-2.7 4914 */ 4915 4916 static bool phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 4917 uint64_t *buid, hwaddr *pio, 4918 hwaddr *mmio32, hwaddr *mmio64, 4919 unsigned n_dma, uint32_t *liobns, 4920 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4921 { 4922 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4923 const uint64_t base_buid = 0x800000020000000ULL; 4924 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4925 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4926 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4927 const uint32_t max_index = 255; 4928 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4929 4930 uint64_t ram_top = MACHINE(spapr)->ram_size; 4931 hwaddr phb0_base, phb_base; 4932 int i; 4933 4934 /* Do we have device memory? */ 4935 if (MACHINE(spapr)->maxram_size > ram_top) { 4936 /* Can't just use maxram_size, because there may be an 4937 * alignment gap between normal and device memory regions 4938 */ 4939 ram_top = MACHINE(spapr)->device_memory->base + 4940 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4941 } 4942 4943 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4944 4945 if (index > max_index) { 4946 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4947 max_index); 4948 return false; 4949 } 4950 4951 *buid = base_buid + index; 4952 for (i = 0; i < n_dma; ++i) { 4953 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4954 } 4955 4956 phb_base = phb0_base + index * phb_spacing; 4957 *pio = phb_base + pio_offset; 4958 *mmio32 = phb_base + mmio_offset; 4959 /* 4960 * We don't set the 64-bit MMIO window, relying on the PHB's 4961 * fallback behaviour of automatically splitting a large "32-bit" 4962 * window into contiguous 32-bit and 64-bit windows 4963 */ 4964 4965 *nv2gpa = 0; 4966 *nv2atsd = 0; 4967 return true; 4968 } 4969 4970 static void spapr_machine_2_7_class_options(MachineClass *mc) 4971 { 4972 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4973 static GlobalProperty compat[] = { 4974 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4975 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4976 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4977 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4978 }; 4979 4980 spapr_machine_2_8_class_options(mc); 4981 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4982 mc->default_machine_opts = "modern-hotplug-events=off"; 4983 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4984 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4985 smc->phb_placement = phb_placement_2_7; 4986 } 4987 4988 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4989 4990 /* 4991 * pseries-2.6 4992 */ 4993 4994 static void spapr_machine_2_6_class_options(MachineClass *mc) 4995 { 4996 static GlobalProperty compat[] = { 4997 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4998 }; 4999 5000 spapr_machine_2_7_class_options(mc); 5001 mc->has_hotpluggable_cpus = false; 5002 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 5003 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5004 } 5005 5006 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 5007 5008 /* 5009 * pseries-2.5 5010 */ 5011 5012 static void spapr_machine_2_5_class_options(MachineClass *mc) 5013 { 5014 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5015 static GlobalProperty compat[] = { 5016 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 5017 }; 5018 5019 spapr_machine_2_6_class_options(mc); 5020 smc->use_ohci_by_default = true; 5021 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 5022 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5023 } 5024 5025 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 5026 5027 /* 5028 * pseries-2.4 5029 */ 5030 5031 static void spapr_machine_2_4_class_options(MachineClass *mc) 5032 { 5033 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5034 5035 spapr_machine_2_5_class_options(mc); 5036 smc->dr_lmb_enabled = false; 5037 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 5038 } 5039 5040 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 5041 5042 /* 5043 * pseries-2.3 5044 */ 5045 5046 static void spapr_machine_2_3_class_options(MachineClass *mc) 5047 { 5048 static GlobalProperty compat[] = { 5049 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 5050 }; 5051 spapr_machine_2_4_class_options(mc); 5052 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 5053 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5054 } 5055 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 5056 5057 /* 5058 * pseries-2.2 5059 */ 5060 5061 static void spapr_machine_2_2_class_options(MachineClass *mc) 5062 { 5063 static GlobalProperty compat[] = { 5064 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 5065 }; 5066 5067 spapr_machine_2_3_class_options(mc); 5068 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 5069 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5070 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 5071 } 5072 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 5073 5074 /* 5075 * pseries-2.1 5076 */ 5077 5078 static void spapr_machine_2_1_class_options(MachineClass *mc) 5079 { 5080 spapr_machine_2_2_class_options(mc); 5081 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 5082 } 5083 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 5084 5085 static void spapr_machine_register_types(void) 5086 { 5087 type_register_static(&spapr_machine_info); 5088 } 5089 5090 type_init(spapr_machine_register_types) 5091