1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/numa.h" 31 #include "hw/hw.h" 32 #include "qemu/log.h" 33 #include "hw/fw-path-provider.h" 34 #include "elf.h" 35 #include "net/net.h" 36 #include "sysemu/device_tree.h" 37 #include "sysemu/block-backend.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/hw_accel.h" 40 #include "kvm_ppc.h" 41 #include "migration/migration.h" 42 #include "mmu-hash64.h" 43 #include "mmu-book3s-v3.h" 44 #include "qom/cpu.h" 45 46 #include "hw/boards.h" 47 #include "hw/ppc/ppc.h" 48 #include "hw/loader.h" 49 50 #include "hw/ppc/fdt.h" 51 #include "hw/ppc/spapr.h" 52 #include "hw/ppc/spapr_vio.h" 53 #include "hw/pci-host/spapr.h" 54 #include "hw/ppc/xics.h" 55 #include "hw/pci/msi.h" 56 57 #include "hw/pci/pci.h" 58 #include "hw/scsi/scsi.h" 59 #include "hw/virtio/virtio-scsi.h" 60 61 #include "exec/address-spaces.h" 62 #include "hw/usb.h" 63 #include "qemu/config-file.h" 64 #include "qemu/error-report.h" 65 #include "trace.h" 66 #include "hw/nmi.h" 67 #include "hw/intc/intc.h" 68 69 #include "hw/compat.h" 70 #include "qemu/cutils.h" 71 #include "hw/ppc/spapr_cpu_core.h" 72 #include "qmp-commands.h" 73 74 #include <libfdt.h> 75 76 /* SLOF memory layout: 77 * 78 * SLOF raw image loaded at 0, copies its romfs right below the flat 79 * device-tree, then position SLOF itself 31M below that 80 * 81 * So we set FW_OVERHEAD to 40MB which should account for all of that 82 * and more 83 * 84 * We load our kernel at 4M, leaving space for SLOF initial image 85 */ 86 #define FDT_MAX_SIZE 0x100000 87 #define RTAS_MAX_SIZE 0x10000 88 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 89 #define FW_MAX_SIZE 0x400000 90 #define FW_FILE_NAME "slof.bin" 91 #define FW_OVERHEAD 0x2800000 92 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 93 94 #define MIN_RMA_SLOF 128UL 95 96 #define PHANDLE_XICP 0x00001111 97 98 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 99 100 static ICSState *spapr_ics_create(sPAPRMachineState *spapr, 101 const char *type_ics, 102 int nr_irqs, Error **errp) 103 { 104 Error *local_err = NULL; 105 Object *obj; 106 107 obj = object_new(type_ics); 108 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); 109 object_property_add_const_link(obj, "xics", OBJECT(spapr), &error_abort); 110 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err); 111 if (local_err) { 112 goto error; 113 } 114 object_property_set_bool(obj, true, "realized", &local_err); 115 if (local_err) { 116 goto error; 117 } 118 119 return ICS_SIMPLE(obj); 120 121 error: 122 error_propagate(errp, local_err); 123 return NULL; 124 } 125 126 static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp) 127 { 128 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 129 130 if (kvm_enabled()) { 131 if (machine_kernel_irqchip_allowed(machine) && 132 !xics_kvm_init(spapr, errp)) { 133 spapr->icp_type = TYPE_KVM_ICP; 134 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp); 135 } 136 if (machine_kernel_irqchip_required(machine) && !spapr->ics) { 137 error_prepend(errp, "kernel_irqchip requested but unavailable: "); 138 return; 139 } 140 } 141 142 if (!spapr->ics) { 143 xics_spapr_init(spapr); 144 spapr->icp_type = TYPE_ICP; 145 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp); 146 if (!spapr->ics) { 147 return; 148 } 149 } 150 } 151 152 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 153 int smt_threads) 154 { 155 int i, ret = 0; 156 uint32_t servers_prop[smt_threads]; 157 uint32_t gservers_prop[smt_threads * 2]; 158 int index = ppc_get_vcpu_dt_id(cpu); 159 160 if (cpu->compat_pvr) { 161 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 162 if (ret < 0) { 163 return ret; 164 } 165 } 166 167 /* Build interrupt servers and gservers properties */ 168 for (i = 0; i < smt_threads; i++) { 169 servers_prop[i] = cpu_to_be32(index + i); 170 /* Hack, direct the group queues back to cpu 0 */ 171 gservers_prop[i*2] = cpu_to_be32(index + i); 172 gservers_prop[i*2 + 1] = 0; 173 } 174 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 175 servers_prop, sizeof(servers_prop)); 176 if (ret < 0) { 177 return ret; 178 } 179 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 180 gservers_prop, sizeof(gservers_prop)); 181 182 return ret; 183 } 184 185 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs) 186 { 187 int ret = 0; 188 PowerPCCPU *cpu = POWERPC_CPU(cs); 189 int index = ppc_get_vcpu_dt_id(cpu); 190 uint32_t associativity[] = {cpu_to_be32(0x5), 191 cpu_to_be32(0x0), 192 cpu_to_be32(0x0), 193 cpu_to_be32(0x0), 194 cpu_to_be32(cs->numa_node), 195 cpu_to_be32(index)}; 196 197 /* Advertise NUMA via ibm,associativity */ 198 if (nb_numa_nodes > 1) { 199 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 200 sizeof(associativity)); 201 } 202 203 return ret; 204 } 205 206 /* Populate the "ibm,pa-features" property */ 207 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset, 208 bool legacy_guest) 209 { 210 uint8_t pa_features_206[] = { 6, 0, 211 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 212 uint8_t pa_features_207[] = { 24, 0, 213 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 214 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 215 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 216 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 217 uint8_t pa_features_300[] = { 66, 0, 218 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 219 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 220 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 221 /* 6: DS207 */ 222 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 223 /* 16: Vector */ 224 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 225 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 226 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 227 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 228 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 229 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 230 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 231 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 232 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 233 /* 42: PM, 44: PC RA, 46: SC vec'd */ 234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 235 /* 48: SIMD, 50: QP BFP, 52: String */ 236 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 237 /* 54: DecFP, 56: DecI, 58: SHA */ 238 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 239 /* 60: NM atomic, 62: RNG */ 240 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 241 }; 242 uint8_t *pa_features; 243 size_t pa_size; 244 245 switch (POWERPC_MMU_VER(env->mmu_model)) { 246 case POWERPC_MMU_VER_2_06: 247 pa_features = pa_features_206; 248 pa_size = sizeof(pa_features_206); 249 break; 250 case POWERPC_MMU_VER_2_07: 251 pa_features = pa_features_207; 252 pa_size = sizeof(pa_features_207); 253 break; 254 case POWERPC_MMU_VER_3_00: 255 pa_features = pa_features_300; 256 pa_size = sizeof(pa_features_300); 257 break; 258 default: 259 return; 260 } 261 262 if (env->ci_large_pages) { 263 /* 264 * Note: we keep CI large pages off by default because a 64K capable 265 * guest provisioned with large pages might otherwise try to map a qemu 266 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 267 * even if that qemu runs on a 4k host. 268 * We dd this bit back here if we are confident this is not an issue 269 */ 270 pa_features[3] |= 0x20; 271 } 272 if (kvmppc_has_cap_htm() && pa_size > 24) { 273 pa_features[24] |= 0x80; /* Transactional memory support */ 274 } 275 if (legacy_guest && pa_size > 40) { 276 /* Workaround for broken kernels that attempt (guest) radix 277 * mode when they can't handle it, if they see the radix bit set 278 * in pa-features. So hide it from them. */ 279 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 280 } 281 282 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 283 } 284 285 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 286 { 287 int ret = 0, offset, cpus_offset; 288 CPUState *cs; 289 char cpu_model[32]; 290 int smt = kvmppc_smt_threads(); 291 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 292 293 CPU_FOREACH(cs) { 294 PowerPCCPU *cpu = POWERPC_CPU(cs); 295 CPUPPCState *env = &cpu->env; 296 DeviceClass *dc = DEVICE_GET_CLASS(cs); 297 int index = ppc_get_vcpu_dt_id(cpu); 298 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 299 300 if ((index % smt) != 0) { 301 continue; 302 } 303 304 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 305 306 cpus_offset = fdt_path_offset(fdt, "/cpus"); 307 if (cpus_offset < 0) { 308 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 309 "cpus"); 310 if (cpus_offset < 0) { 311 return cpus_offset; 312 } 313 } 314 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 315 if (offset < 0) { 316 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 317 if (offset < 0) { 318 return offset; 319 } 320 } 321 322 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 323 pft_size_prop, sizeof(pft_size_prop)); 324 if (ret < 0) { 325 return ret; 326 } 327 328 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs); 329 if (ret < 0) { 330 return ret; 331 } 332 333 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 334 if (ret < 0) { 335 return ret; 336 } 337 338 spapr_populate_pa_features(env, fdt, offset, 339 spapr->cas_legacy_guest_workaround); 340 } 341 return ret; 342 } 343 344 static hwaddr spapr_node0_size(void) 345 { 346 MachineState *machine = MACHINE(qdev_get_machine()); 347 348 if (nb_numa_nodes) { 349 int i; 350 for (i = 0; i < nb_numa_nodes; ++i) { 351 if (numa_info[i].node_mem) { 352 return MIN(pow2floor(numa_info[i].node_mem), 353 machine->ram_size); 354 } 355 } 356 } 357 return machine->ram_size; 358 } 359 360 static void add_str(GString *s, const gchar *s1) 361 { 362 g_string_append_len(s, s1, strlen(s1) + 1); 363 } 364 365 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 366 hwaddr size) 367 { 368 uint32_t associativity[] = { 369 cpu_to_be32(0x4), /* length */ 370 cpu_to_be32(0x0), cpu_to_be32(0x0), 371 cpu_to_be32(0x0), cpu_to_be32(nodeid) 372 }; 373 char mem_name[32]; 374 uint64_t mem_reg_property[2]; 375 int off; 376 377 mem_reg_property[0] = cpu_to_be64(start); 378 mem_reg_property[1] = cpu_to_be64(size); 379 380 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 381 off = fdt_add_subnode(fdt, 0, mem_name); 382 _FDT(off); 383 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 384 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 385 sizeof(mem_reg_property)))); 386 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 387 sizeof(associativity)))); 388 return off; 389 } 390 391 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 392 { 393 MachineState *machine = MACHINE(spapr); 394 hwaddr mem_start, node_size; 395 int i, nb_nodes = nb_numa_nodes; 396 NodeInfo *nodes = numa_info; 397 NodeInfo ramnode; 398 399 /* No NUMA nodes, assume there is just one node with whole RAM */ 400 if (!nb_numa_nodes) { 401 nb_nodes = 1; 402 ramnode.node_mem = machine->ram_size; 403 nodes = &ramnode; 404 } 405 406 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 407 if (!nodes[i].node_mem) { 408 continue; 409 } 410 if (mem_start >= machine->ram_size) { 411 node_size = 0; 412 } else { 413 node_size = nodes[i].node_mem; 414 if (node_size > machine->ram_size - mem_start) { 415 node_size = machine->ram_size - mem_start; 416 } 417 } 418 if (!mem_start) { 419 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 420 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 421 mem_start += spapr->rma_size; 422 node_size -= spapr->rma_size; 423 } 424 for ( ; node_size; ) { 425 hwaddr sizetmp = pow2floor(node_size); 426 427 /* mem_start != 0 here */ 428 if (ctzl(mem_start) < ctzl(sizetmp)) { 429 sizetmp = 1ULL << ctzl(mem_start); 430 } 431 432 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 433 node_size -= sizetmp; 434 mem_start += sizetmp; 435 } 436 } 437 438 return 0; 439 } 440 441 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 442 sPAPRMachineState *spapr) 443 { 444 PowerPCCPU *cpu = POWERPC_CPU(cs); 445 CPUPPCState *env = &cpu->env; 446 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 447 int index = ppc_get_vcpu_dt_id(cpu); 448 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 449 0xffffffff, 0xffffffff}; 450 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 451 : SPAPR_TIMEBASE_FREQ; 452 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 453 uint32_t page_sizes_prop[64]; 454 size_t page_sizes_prop_size; 455 uint32_t vcpus_per_socket = smp_threads * smp_cores; 456 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 457 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 458 sPAPRDRConnector *drc; 459 int drc_index; 460 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 461 int i; 462 463 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index); 464 if (drc) { 465 drc_index = spapr_drc_index(drc); 466 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 467 } 468 469 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 470 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 471 472 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 473 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 474 env->dcache_line_size))); 475 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 476 env->dcache_line_size))); 477 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 478 env->icache_line_size))); 479 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 480 env->icache_line_size))); 481 482 if (pcc->l1_dcache_size) { 483 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 484 pcc->l1_dcache_size))); 485 } else { 486 error_report("Warning: Unknown L1 dcache size for cpu"); 487 } 488 if (pcc->l1_icache_size) { 489 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 490 pcc->l1_icache_size))); 491 } else { 492 error_report("Warning: Unknown L1 icache size for cpu"); 493 } 494 495 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 496 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 497 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 498 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 499 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 500 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 501 502 if (env->spr_cb[SPR_PURR].oea_read) { 503 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 504 } 505 506 if (env->mmu_model & POWERPC_MMU_1TSEG) { 507 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 508 segs, sizeof(segs)))); 509 } 510 511 /* Advertise VMX/VSX (vector extensions) if available 512 * 0 / no property == no vector extensions 513 * 1 == VMX / Altivec available 514 * 2 == VSX available */ 515 if (env->insns_flags & PPC_ALTIVEC) { 516 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 517 518 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 519 } 520 521 /* Advertise DFP (Decimal Floating Point) if available 522 * 0 / no property == no DFP 523 * 1 == DFP available */ 524 if (env->insns_flags2 & PPC2_DFP) { 525 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 526 } 527 528 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 529 sizeof(page_sizes_prop)); 530 if (page_sizes_prop_size) { 531 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 532 page_sizes_prop, page_sizes_prop_size))); 533 } 534 535 spapr_populate_pa_features(env, fdt, offset, false); 536 537 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 538 cs->cpu_index / vcpus_per_socket))); 539 540 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 541 pft_size_prop, sizeof(pft_size_prop)))); 542 543 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs)); 544 545 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 546 547 if (pcc->radix_page_info) { 548 for (i = 0; i < pcc->radix_page_info->count; i++) { 549 radix_AP_encodings[i] = 550 cpu_to_be32(pcc->radix_page_info->entries[i]); 551 } 552 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 553 radix_AP_encodings, 554 pcc->radix_page_info->count * 555 sizeof(radix_AP_encodings[0])))); 556 } 557 } 558 559 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 560 { 561 CPUState *cs; 562 int cpus_offset; 563 char *nodename; 564 int smt = kvmppc_smt_threads(); 565 566 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 567 _FDT(cpus_offset); 568 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 569 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 570 571 /* 572 * We walk the CPUs in reverse order to ensure that CPU DT nodes 573 * created by fdt_add_subnode() end up in the right order in FDT 574 * for the guest kernel the enumerate the CPUs correctly. 575 */ 576 CPU_FOREACH_REVERSE(cs) { 577 PowerPCCPU *cpu = POWERPC_CPU(cs); 578 int index = ppc_get_vcpu_dt_id(cpu); 579 DeviceClass *dc = DEVICE_GET_CLASS(cs); 580 int offset; 581 582 if ((index % smt) != 0) { 583 continue; 584 } 585 586 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 587 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 588 g_free(nodename); 589 _FDT(offset); 590 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 591 } 592 593 } 594 595 /* 596 * Adds ibm,dynamic-reconfiguration-memory node. 597 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 598 * of this device tree node. 599 */ 600 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 601 { 602 MachineState *machine = MACHINE(spapr); 603 int ret, i, offset; 604 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 605 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 606 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 607 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 608 memory_region_size(&spapr->hotplug_memory.mr)) / 609 lmb_size; 610 uint32_t *int_buf, *cur_index, buf_len; 611 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 612 613 /* 614 * Don't create the node if there is no hotpluggable memory 615 */ 616 if (machine->ram_size == machine->maxram_size) { 617 return 0; 618 } 619 620 /* 621 * Allocate enough buffer size to fit in ibm,dynamic-memory 622 * or ibm,associativity-lookup-arrays 623 */ 624 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 625 * sizeof(uint32_t); 626 cur_index = int_buf = g_malloc0(buf_len); 627 628 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 629 630 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 631 sizeof(prop_lmb_size)); 632 if (ret < 0) { 633 goto out; 634 } 635 636 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 637 if (ret < 0) { 638 goto out; 639 } 640 641 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 642 if (ret < 0) { 643 goto out; 644 } 645 646 /* ibm,dynamic-memory */ 647 int_buf[0] = cpu_to_be32(nr_lmbs); 648 cur_index++; 649 for (i = 0; i < nr_lmbs; i++) { 650 uint64_t addr = i * lmb_size; 651 uint32_t *dynamic_memory = cur_index; 652 653 if (i >= hotplug_lmb_start) { 654 sPAPRDRConnector *drc; 655 656 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i); 657 g_assert(drc); 658 659 dynamic_memory[0] = cpu_to_be32(addr >> 32); 660 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 661 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 662 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 663 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); 664 if (memory_region_present(get_system_memory(), addr)) { 665 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 666 } else { 667 dynamic_memory[5] = cpu_to_be32(0); 668 } 669 } else { 670 /* 671 * LMB information for RMA, boot time RAM and gap b/n RAM and 672 * hotplug memory region -- all these are marked as reserved 673 * and as having no valid DRC. 674 */ 675 dynamic_memory[0] = cpu_to_be32(addr >> 32); 676 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 677 dynamic_memory[2] = cpu_to_be32(0); 678 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 679 dynamic_memory[4] = cpu_to_be32(-1); 680 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 681 SPAPR_LMB_FLAGS_DRC_INVALID); 682 } 683 684 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 685 } 686 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 687 if (ret < 0) { 688 goto out; 689 } 690 691 /* ibm,associativity-lookup-arrays */ 692 cur_index = int_buf; 693 int_buf[0] = cpu_to_be32(nr_nodes); 694 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 695 cur_index += 2; 696 for (i = 0; i < nr_nodes; i++) { 697 uint32_t associativity[] = { 698 cpu_to_be32(0x0), 699 cpu_to_be32(0x0), 700 cpu_to_be32(0x0), 701 cpu_to_be32(i) 702 }; 703 memcpy(cur_index, associativity, sizeof(associativity)); 704 cur_index += 4; 705 } 706 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 707 (cur_index - int_buf) * sizeof(uint32_t)); 708 out: 709 g_free(int_buf); 710 return ret; 711 } 712 713 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 714 sPAPROptionVector *ov5_updates) 715 { 716 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 717 int ret = 0, offset; 718 719 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 720 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 721 g_assert(smc->dr_lmb_enabled); 722 ret = spapr_populate_drconf_memory(spapr, fdt); 723 if (ret) { 724 goto out; 725 } 726 } 727 728 offset = fdt_path_offset(fdt, "/chosen"); 729 if (offset < 0) { 730 offset = fdt_add_subnode(fdt, 0, "chosen"); 731 if (offset < 0) { 732 return offset; 733 } 734 } 735 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 736 "ibm,architecture-vec-5"); 737 738 out: 739 return ret; 740 } 741 742 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 743 target_ulong addr, target_ulong size, 744 sPAPROptionVector *ov5_updates) 745 { 746 void *fdt, *fdt_skel; 747 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 748 749 size -= sizeof(hdr); 750 751 /* Create sceleton */ 752 fdt_skel = g_malloc0(size); 753 _FDT((fdt_create(fdt_skel, size))); 754 _FDT((fdt_begin_node(fdt_skel, ""))); 755 _FDT((fdt_end_node(fdt_skel))); 756 _FDT((fdt_finish(fdt_skel))); 757 fdt = g_malloc0(size); 758 _FDT((fdt_open_into(fdt_skel, fdt, size))); 759 g_free(fdt_skel); 760 761 /* Fixup cpu nodes */ 762 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 763 764 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 765 return -1; 766 } 767 768 /* Pack resulting tree */ 769 _FDT((fdt_pack(fdt))); 770 771 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 772 trace_spapr_cas_failed(size); 773 return -1; 774 } 775 776 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 777 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 778 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 779 g_free(fdt); 780 781 return 0; 782 } 783 784 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 785 { 786 int rtas; 787 GString *hypertas = g_string_sized_new(256); 788 GString *qemu_hypertas = g_string_sized_new(256); 789 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 790 uint64_t max_hotplug_addr = spapr->hotplug_memory.base + 791 memory_region_size(&spapr->hotplug_memory.mr); 792 uint32_t lrdr_capacity[] = { 793 cpu_to_be32(max_hotplug_addr >> 32), 794 cpu_to_be32(max_hotplug_addr & 0xffffffff), 795 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 796 cpu_to_be32(max_cpus / smp_threads), 797 }; 798 799 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 800 801 /* hypertas */ 802 add_str(hypertas, "hcall-pft"); 803 add_str(hypertas, "hcall-term"); 804 add_str(hypertas, "hcall-dabr"); 805 add_str(hypertas, "hcall-interrupt"); 806 add_str(hypertas, "hcall-tce"); 807 add_str(hypertas, "hcall-vio"); 808 add_str(hypertas, "hcall-splpar"); 809 add_str(hypertas, "hcall-bulk"); 810 add_str(hypertas, "hcall-set-mode"); 811 add_str(hypertas, "hcall-sprg0"); 812 add_str(hypertas, "hcall-copy"); 813 add_str(hypertas, "hcall-debug"); 814 add_str(qemu_hypertas, "hcall-memop1"); 815 816 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 817 add_str(hypertas, "hcall-multi-tce"); 818 } 819 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 820 hypertas->str, hypertas->len)); 821 g_string_free(hypertas, TRUE); 822 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 823 qemu_hypertas->str, qemu_hypertas->len)); 824 g_string_free(qemu_hypertas, TRUE); 825 826 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 827 refpoints, sizeof(refpoints))); 828 829 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 830 RTAS_ERROR_LOG_MAX)); 831 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 832 RTAS_EVENT_SCAN_RATE)); 833 834 if (msi_nonbroken) { 835 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 836 } 837 838 /* 839 * According to PAPR, rtas ibm,os-term does not guarantee a return 840 * back to the guest cpu. 841 * 842 * While an additional ibm,extended-os-term property indicates 843 * that rtas call return will always occur. Set this property. 844 */ 845 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 846 847 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 848 lrdr_capacity, sizeof(lrdr_capacity))); 849 850 spapr_dt_rtas_tokens(fdt, rtas); 851 } 852 853 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features 854 * that the guest may request and thus the valid values for bytes 24..26 of 855 * option vector 5: */ 856 static void spapr_dt_ov5_platform_support(void *fdt, int chosen) 857 { 858 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 859 860 char val[2 * 3] = { 861 24, 0x00, /* Hash/Radix, filled in below. */ 862 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 863 26, 0x40, /* Radix options: GTSE == yes. */ 864 }; 865 866 if (kvm_enabled()) { 867 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 868 val[1] = 0x80; /* OV5_MMU_BOTH */ 869 } else if (kvmppc_has_cap_mmu_radix()) { 870 val[1] = 0x40; /* OV5_MMU_RADIX_300 */ 871 } else { 872 val[1] = 0x00; /* Hash */ 873 } 874 } else { 875 if (first_ppc_cpu->env.mmu_model & POWERPC_MMU_V3) { 876 /* V3 MMU supports both hash and radix (with dynamic switching) */ 877 val[1] = 0xC0; 878 } else { 879 /* Otherwise we can only do hash */ 880 val[1] = 0x00; 881 } 882 } 883 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 884 val, sizeof(val))); 885 } 886 887 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 888 { 889 MachineState *machine = MACHINE(spapr); 890 int chosen; 891 const char *boot_device = machine->boot_order; 892 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 893 size_t cb = 0; 894 char *bootlist = get_boot_devices_list(&cb, true); 895 896 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 897 898 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 899 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 900 spapr->initrd_base)); 901 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 902 spapr->initrd_base + spapr->initrd_size)); 903 904 if (spapr->kernel_size) { 905 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 906 cpu_to_be64(spapr->kernel_size) }; 907 908 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 909 &kprop, sizeof(kprop))); 910 if (spapr->kernel_le) { 911 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 912 } 913 } 914 if (boot_menu) { 915 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 916 } 917 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 918 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 919 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 920 921 if (cb && bootlist) { 922 int i; 923 924 for (i = 0; i < cb; i++) { 925 if (bootlist[i] == '\n') { 926 bootlist[i] = ' '; 927 } 928 } 929 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 930 } 931 932 if (boot_device && strlen(boot_device)) { 933 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 934 } 935 936 if (!spapr->has_graphics && stdout_path) { 937 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 938 } 939 940 spapr_dt_ov5_platform_support(fdt, chosen); 941 942 g_free(stdout_path); 943 g_free(bootlist); 944 } 945 946 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 947 { 948 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 949 * KVM to work under pHyp with some guest co-operation */ 950 int hypervisor; 951 uint8_t hypercall[16]; 952 953 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 954 /* indicate KVM hypercall interface */ 955 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 956 if (kvmppc_has_cap_fixup_hcalls()) { 957 /* 958 * Older KVM versions with older guest kernels were broken 959 * with the magic page, don't allow the guest to map it. 960 */ 961 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 962 sizeof(hypercall))) { 963 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 964 hypercall, sizeof(hypercall))); 965 } 966 } 967 } 968 969 static void *spapr_build_fdt(sPAPRMachineState *spapr, 970 hwaddr rtas_addr, 971 hwaddr rtas_size) 972 { 973 MachineState *machine = MACHINE(qdev_get_machine()); 974 MachineClass *mc = MACHINE_GET_CLASS(machine); 975 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 976 int ret; 977 void *fdt; 978 sPAPRPHBState *phb; 979 char *buf; 980 int smt = kvmppc_smt_threads(); 981 982 fdt = g_malloc0(FDT_MAX_SIZE); 983 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 984 985 /* Root node */ 986 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 987 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 988 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 989 990 /* 991 * Add info to guest to indentify which host is it being run on 992 * and what is the uuid of the guest 993 */ 994 if (kvmppc_get_host_model(&buf)) { 995 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 996 g_free(buf); 997 } 998 if (kvmppc_get_host_serial(&buf)) { 999 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1000 g_free(buf); 1001 } 1002 1003 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1004 1005 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1006 if (qemu_uuid_set) { 1007 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1008 } 1009 g_free(buf); 1010 1011 if (qemu_get_vm_name()) { 1012 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1013 qemu_get_vm_name())); 1014 } 1015 1016 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1017 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1018 1019 /* /interrupt controller */ 1020 spapr_dt_xics(DIV_ROUND_UP(max_cpus * smt, smp_threads), fdt, PHANDLE_XICP); 1021 1022 ret = spapr_populate_memory(spapr, fdt); 1023 if (ret < 0) { 1024 error_report("couldn't setup memory nodes in fdt"); 1025 exit(1); 1026 } 1027 1028 /* /vdevice */ 1029 spapr_dt_vdevice(spapr->vio_bus, fdt); 1030 1031 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1032 ret = spapr_rng_populate_dt(fdt); 1033 if (ret < 0) { 1034 error_report("could not set up rng device in the fdt"); 1035 exit(1); 1036 } 1037 } 1038 1039 QLIST_FOREACH(phb, &spapr->phbs, list) { 1040 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 1041 if (ret < 0) { 1042 error_report("couldn't setup PCI devices in fdt"); 1043 exit(1); 1044 } 1045 } 1046 1047 /* cpus */ 1048 spapr_populate_cpus_dt_node(fdt, spapr); 1049 1050 if (smc->dr_lmb_enabled) { 1051 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1052 } 1053 1054 if (mc->has_hotpluggable_cpus) { 1055 int offset = fdt_path_offset(fdt, "/cpus"); 1056 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1057 SPAPR_DR_CONNECTOR_TYPE_CPU); 1058 if (ret < 0) { 1059 error_report("Couldn't set up CPU DR device tree properties"); 1060 exit(1); 1061 } 1062 } 1063 1064 /* /event-sources */ 1065 spapr_dt_events(spapr, fdt); 1066 1067 /* /rtas */ 1068 spapr_dt_rtas(spapr, fdt); 1069 1070 /* /chosen */ 1071 spapr_dt_chosen(spapr, fdt); 1072 1073 /* /hypervisor */ 1074 if (kvm_enabled()) { 1075 spapr_dt_hypervisor(spapr, fdt); 1076 } 1077 1078 /* Build memory reserve map */ 1079 if (spapr->kernel_size) { 1080 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1081 } 1082 if (spapr->initrd_size) { 1083 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1084 } 1085 1086 /* ibm,client-architecture-support updates */ 1087 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1088 if (ret < 0) { 1089 error_report("couldn't setup CAS properties fdt"); 1090 exit(1); 1091 } 1092 1093 return fdt; 1094 } 1095 1096 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1097 { 1098 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1099 } 1100 1101 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1102 PowerPCCPU *cpu) 1103 { 1104 CPUPPCState *env = &cpu->env; 1105 1106 /* The TCG path should also be holding the BQL at this point */ 1107 g_assert(qemu_mutex_iothread_locked()); 1108 1109 if (msr_pr) { 1110 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1111 env->gpr[3] = H_PRIVILEGE; 1112 } else { 1113 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1114 } 1115 } 1116 1117 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) 1118 { 1119 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1120 1121 return spapr->patb_entry; 1122 } 1123 1124 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1125 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1126 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1127 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1128 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1129 1130 /* 1131 * Get the fd to access the kernel htab, re-opening it if necessary 1132 */ 1133 static int get_htab_fd(sPAPRMachineState *spapr) 1134 { 1135 if (spapr->htab_fd >= 0) { 1136 return spapr->htab_fd; 1137 } 1138 1139 spapr->htab_fd = kvmppc_get_htab_fd(false); 1140 if (spapr->htab_fd < 0) { 1141 error_report("Unable to open fd for reading hash table from KVM: %s", 1142 strerror(errno)); 1143 } 1144 1145 return spapr->htab_fd; 1146 } 1147 1148 void close_htab_fd(sPAPRMachineState *spapr) 1149 { 1150 if (spapr->htab_fd >= 0) { 1151 close(spapr->htab_fd); 1152 } 1153 spapr->htab_fd = -1; 1154 } 1155 1156 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1157 { 1158 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1159 1160 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1161 } 1162 1163 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1164 hwaddr ptex, int n) 1165 { 1166 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1167 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1168 1169 if (!spapr->htab) { 1170 /* 1171 * HTAB is controlled by KVM. Fetch into temporary buffer 1172 */ 1173 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1174 kvmppc_read_hptes(hptes, ptex, n); 1175 return hptes; 1176 } 1177 1178 /* 1179 * HTAB is controlled by QEMU. Just point to the internally 1180 * accessible PTEG. 1181 */ 1182 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1183 } 1184 1185 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1186 const ppc_hash_pte64_t *hptes, 1187 hwaddr ptex, int n) 1188 { 1189 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1190 1191 if (!spapr->htab) { 1192 g_free((void *)hptes); 1193 } 1194 1195 /* Nothing to do for qemu managed HPT */ 1196 } 1197 1198 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1199 uint64_t pte0, uint64_t pte1) 1200 { 1201 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1202 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1203 1204 if (!spapr->htab) { 1205 kvmppc_write_hpte(ptex, pte0, pte1); 1206 } else { 1207 stq_p(spapr->htab + offset, pte0); 1208 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1209 } 1210 } 1211 1212 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1213 { 1214 int shift; 1215 1216 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1217 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1218 * that's much more than is needed for Linux guests */ 1219 shift = ctz64(pow2ceil(ramsize)) - 7; 1220 shift = MAX(shift, 18); /* Minimum architected size */ 1221 shift = MIN(shift, 46); /* Maximum architected size */ 1222 return shift; 1223 } 1224 1225 void spapr_free_hpt(sPAPRMachineState *spapr) 1226 { 1227 g_free(spapr->htab); 1228 spapr->htab = NULL; 1229 spapr->htab_shift = 0; 1230 close_htab_fd(spapr); 1231 } 1232 1233 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1234 Error **errp) 1235 { 1236 long rc; 1237 1238 /* Clean up any HPT info from a previous boot */ 1239 spapr_free_hpt(spapr); 1240 1241 rc = kvmppc_reset_htab(shift); 1242 if (rc < 0) { 1243 /* kernel-side HPT needed, but couldn't allocate one */ 1244 error_setg_errno(errp, errno, 1245 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1246 shift); 1247 /* This is almost certainly fatal, but if the caller really 1248 * wants to carry on with shift == 0, it's welcome to try */ 1249 } else if (rc > 0) { 1250 /* kernel-side HPT allocated */ 1251 if (rc != shift) { 1252 error_setg(errp, 1253 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1254 shift, rc); 1255 } 1256 1257 spapr->htab_shift = shift; 1258 spapr->htab = NULL; 1259 } else { 1260 /* kernel-side HPT not needed, allocate in userspace instead */ 1261 size_t size = 1ULL << shift; 1262 int i; 1263 1264 spapr->htab = qemu_memalign(size, size); 1265 if (!spapr->htab) { 1266 error_setg_errno(errp, errno, 1267 "Could not allocate HPT of order %d", shift); 1268 return; 1269 } 1270 1271 memset(spapr->htab, 0, size); 1272 spapr->htab_shift = shift; 1273 1274 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1275 DIRTY_HPTE(HPTE(spapr->htab, i)); 1276 } 1277 } 1278 } 1279 1280 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) 1281 { 1282 spapr_reallocate_hpt(spapr, 1283 spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size), 1284 &error_fatal); 1285 if (spapr->vrma_adjust) { 1286 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 1287 spapr->htab_shift); 1288 } 1289 /* We're setting up a hash table, so that means we're not radix */ 1290 spapr->patb_entry = 0; 1291 } 1292 1293 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1294 { 1295 bool matched = false; 1296 1297 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1298 matched = true; 1299 } 1300 1301 if (!matched) { 1302 error_report("Device %s is not supported by this machine yet.", 1303 qdev_fw_name(DEVICE(sbdev))); 1304 exit(1); 1305 } 1306 } 1307 1308 static void ppc_spapr_reset(void) 1309 { 1310 MachineState *machine = MACHINE(qdev_get_machine()); 1311 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1312 PowerPCCPU *first_ppc_cpu; 1313 uint32_t rtas_limit; 1314 hwaddr rtas_addr, fdt_addr; 1315 void *fdt; 1316 int rc; 1317 1318 /* Check for unknown sysbus devices */ 1319 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1320 1321 if (kvm_enabled() && kvmppc_has_cap_mmu_radix()) { 1322 /* If using KVM with radix mode available, VCPUs can be started 1323 * without a HPT because KVM will start them in radix mode. 1324 * Set the GR bit in PATB so that we know there is no HPT. */ 1325 spapr->patb_entry = PATBE1_GR; 1326 } else { 1327 spapr->patb_entry = 0; 1328 spapr_setup_hpt_and_vrma(spapr); 1329 } 1330 1331 qemu_devices_reset(); 1332 1333 /* 1334 * We place the device tree and RTAS just below either the top of the RMA, 1335 * or just below 2GB, whichever is lowere, so that it can be 1336 * processed with 32-bit real mode code if necessary 1337 */ 1338 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1339 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1340 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1341 1342 /* if this reset wasn't generated by CAS, we should reset our 1343 * negotiated options and start from scratch */ 1344 if (!spapr->cas_reboot) { 1345 spapr_ovec_cleanup(spapr->ov5_cas); 1346 spapr->ov5_cas = spapr_ovec_new(); 1347 } 1348 1349 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1350 1351 spapr_load_rtas(spapr, fdt, rtas_addr); 1352 1353 rc = fdt_pack(fdt); 1354 1355 /* Should only fail if we've built a corrupted tree */ 1356 assert(rc == 0); 1357 1358 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1359 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1360 fdt_totalsize(fdt), FDT_MAX_SIZE); 1361 exit(1); 1362 } 1363 1364 /* Load the fdt */ 1365 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1366 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1367 g_free(fdt); 1368 1369 /* Set up the entry state */ 1370 first_ppc_cpu = POWERPC_CPU(first_cpu); 1371 first_ppc_cpu->env.gpr[3] = fdt_addr; 1372 first_ppc_cpu->env.gpr[5] = 0; 1373 first_cpu->halted = 0; 1374 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1375 1376 spapr->cas_reboot = false; 1377 } 1378 1379 static void spapr_create_nvram(sPAPRMachineState *spapr) 1380 { 1381 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1382 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1383 1384 if (dinfo) { 1385 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1386 &error_fatal); 1387 } 1388 1389 qdev_init_nofail(dev); 1390 1391 spapr->nvram = (struct sPAPRNVRAM *)dev; 1392 } 1393 1394 static void spapr_rtc_create(sPAPRMachineState *spapr) 1395 { 1396 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); 1397 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), 1398 &error_fatal); 1399 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1400 &error_fatal); 1401 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1402 "date", &error_fatal); 1403 } 1404 1405 /* Returns whether we want to use VGA or not */ 1406 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1407 { 1408 switch (vga_interface_type) { 1409 case VGA_NONE: 1410 return false; 1411 case VGA_DEVICE: 1412 return true; 1413 case VGA_STD: 1414 case VGA_VIRTIO: 1415 return pci_vga_init(pci_bus) != NULL; 1416 default: 1417 error_setg(errp, 1418 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1419 return false; 1420 } 1421 } 1422 1423 static int spapr_post_load(void *opaque, int version_id) 1424 { 1425 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1426 int err = 0; 1427 1428 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { 1429 CPUState *cs; 1430 CPU_FOREACH(cs) { 1431 PowerPCCPU *cpu = POWERPC_CPU(cs); 1432 icp_resend(ICP(cpu->intc)); 1433 } 1434 } 1435 1436 /* In earlier versions, there was no separate qdev for the PAPR 1437 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1438 * So when migrating from those versions, poke the incoming offset 1439 * value into the RTC device */ 1440 if (version_id < 3) { 1441 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1442 } 1443 1444 return err; 1445 } 1446 1447 static bool version_before_3(void *opaque, int version_id) 1448 { 1449 return version_id < 3; 1450 } 1451 1452 static bool spapr_ov5_cas_needed(void *opaque) 1453 { 1454 sPAPRMachineState *spapr = opaque; 1455 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1456 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1457 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1458 bool cas_needed; 1459 1460 /* Prior to the introduction of sPAPROptionVector, we had two option 1461 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1462 * Both of these options encode machine topology into the device-tree 1463 * in such a way that the now-booted OS should still be able to interact 1464 * appropriately with QEMU regardless of what options were actually 1465 * negotiatied on the source side. 1466 * 1467 * As such, we can avoid migrating the CAS-negotiated options if these 1468 * are the only options available on the current machine/platform. 1469 * Since these are the only options available for pseries-2.7 and 1470 * earlier, this allows us to maintain old->new/new->old migration 1471 * compatibility. 1472 * 1473 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1474 * via default pseries-2.8 machines and explicit command-line parameters. 1475 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1476 * of the actual CAS-negotiated values to continue working properly. For 1477 * example, availability of memory unplug depends on knowing whether 1478 * OV5_HP_EVT was negotiated via CAS. 1479 * 1480 * Thus, for any cases where the set of available CAS-negotiatable 1481 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1482 * include the CAS-negotiated options in the migration stream. 1483 */ 1484 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1485 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1486 1487 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1488 * the mask itself since in the future it's possible "legacy" bits may be 1489 * removed via machine options, which could generate a false positive 1490 * that breaks migration. 1491 */ 1492 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1493 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1494 1495 spapr_ovec_cleanup(ov5_mask); 1496 spapr_ovec_cleanup(ov5_legacy); 1497 spapr_ovec_cleanup(ov5_removed); 1498 1499 return cas_needed; 1500 } 1501 1502 static const VMStateDescription vmstate_spapr_ov5_cas = { 1503 .name = "spapr_option_vector_ov5_cas", 1504 .version_id = 1, 1505 .minimum_version_id = 1, 1506 .needed = spapr_ov5_cas_needed, 1507 .fields = (VMStateField[]) { 1508 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1509 vmstate_spapr_ovec, sPAPROptionVector), 1510 VMSTATE_END_OF_LIST() 1511 }, 1512 }; 1513 1514 static bool spapr_patb_entry_needed(void *opaque) 1515 { 1516 sPAPRMachineState *spapr = opaque; 1517 1518 return !!spapr->patb_entry; 1519 } 1520 1521 static const VMStateDescription vmstate_spapr_patb_entry = { 1522 .name = "spapr_patb_entry", 1523 .version_id = 1, 1524 .minimum_version_id = 1, 1525 .needed = spapr_patb_entry_needed, 1526 .fields = (VMStateField[]) { 1527 VMSTATE_UINT64(patb_entry, sPAPRMachineState), 1528 VMSTATE_END_OF_LIST() 1529 }, 1530 }; 1531 1532 static const VMStateDescription vmstate_spapr = { 1533 .name = "spapr", 1534 .version_id = 3, 1535 .minimum_version_id = 1, 1536 .post_load = spapr_post_load, 1537 .fields = (VMStateField[]) { 1538 /* used to be @next_irq */ 1539 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1540 1541 /* RTC offset */ 1542 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1543 1544 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1545 VMSTATE_END_OF_LIST() 1546 }, 1547 .subsections = (const VMStateDescription*[]) { 1548 &vmstate_spapr_ov5_cas, 1549 &vmstate_spapr_patb_entry, 1550 NULL 1551 } 1552 }; 1553 1554 static int htab_save_setup(QEMUFile *f, void *opaque) 1555 { 1556 sPAPRMachineState *spapr = opaque; 1557 1558 /* "Iteration" header */ 1559 qemu_put_be32(f, spapr->htab_shift); 1560 1561 if (spapr->htab) { 1562 spapr->htab_save_index = 0; 1563 spapr->htab_first_pass = true; 1564 } else { 1565 assert(kvm_enabled()); 1566 } 1567 1568 1569 return 0; 1570 } 1571 1572 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1573 int64_t max_ns) 1574 { 1575 bool has_timeout = max_ns != -1; 1576 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1577 int index = spapr->htab_save_index; 1578 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1579 1580 assert(spapr->htab_first_pass); 1581 1582 do { 1583 int chunkstart; 1584 1585 /* Consume invalid HPTEs */ 1586 while ((index < htabslots) 1587 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1588 CLEAN_HPTE(HPTE(spapr->htab, index)); 1589 index++; 1590 } 1591 1592 /* Consume valid HPTEs */ 1593 chunkstart = index; 1594 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1595 && HPTE_VALID(HPTE(spapr->htab, index))) { 1596 CLEAN_HPTE(HPTE(spapr->htab, index)); 1597 index++; 1598 } 1599 1600 if (index > chunkstart) { 1601 int n_valid = index - chunkstart; 1602 1603 qemu_put_be32(f, chunkstart); 1604 qemu_put_be16(f, n_valid); 1605 qemu_put_be16(f, 0); 1606 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1607 HASH_PTE_SIZE_64 * n_valid); 1608 1609 if (has_timeout && 1610 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1611 break; 1612 } 1613 } 1614 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1615 1616 if (index >= htabslots) { 1617 assert(index == htabslots); 1618 index = 0; 1619 spapr->htab_first_pass = false; 1620 } 1621 spapr->htab_save_index = index; 1622 } 1623 1624 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1625 int64_t max_ns) 1626 { 1627 bool final = max_ns < 0; 1628 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1629 int examined = 0, sent = 0; 1630 int index = spapr->htab_save_index; 1631 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1632 1633 assert(!spapr->htab_first_pass); 1634 1635 do { 1636 int chunkstart, invalidstart; 1637 1638 /* Consume non-dirty HPTEs */ 1639 while ((index < htabslots) 1640 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1641 index++; 1642 examined++; 1643 } 1644 1645 chunkstart = index; 1646 /* Consume valid dirty HPTEs */ 1647 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1648 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1649 && HPTE_VALID(HPTE(spapr->htab, index))) { 1650 CLEAN_HPTE(HPTE(spapr->htab, index)); 1651 index++; 1652 examined++; 1653 } 1654 1655 invalidstart = index; 1656 /* Consume invalid dirty HPTEs */ 1657 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1658 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1659 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1660 CLEAN_HPTE(HPTE(spapr->htab, index)); 1661 index++; 1662 examined++; 1663 } 1664 1665 if (index > chunkstart) { 1666 int n_valid = invalidstart - chunkstart; 1667 int n_invalid = index - invalidstart; 1668 1669 qemu_put_be32(f, chunkstart); 1670 qemu_put_be16(f, n_valid); 1671 qemu_put_be16(f, n_invalid); 1672 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1673 HASH_PTE_SIZE_64 * n_valid); 1674 sent += index - chunkstart; 1675 1676 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1677 break; 1678 } 1679 } 1680 1681 if (examined >= htabslots) { 1682 break; 1683 } 1684 1685 if (index >= htabslots) { 1686 assert(index == htabslots); 1687 index = 0; 1688 } 1689 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1690 1691 if (index >= htabslots) { 1692 assert(index == htabslots); 1693 index = 0; 1694 } 1695 1696 spapr->htab_save_index = index; 1697 1698 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1699 } 1700 1701 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1702 #define MAX_KVM_BUF_SIZE 2048 1703 1704 static int htab_save_iterate(QEMUFile *f, void *opaque) 1705 { 1706 sPAPRMachineState *spapr = opaque; 1707 int fd; 1708 int rc = 0; 1709 1710 /* Iteration header */ 1711 qemu_put_be32(f, 0); 1712 1713 if (!spapr->htab) { 1714 assert(kvm_enabled()); 1715 1716 fd = get_htab_fd(spapr); 1717 if (fd < 0) { 1718 return fd; 1719 } 1720 1721 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1722 if (rc < 0) { 1723 return rc; 1724 } 1725 } else if (spapr->htab_first_pass) { 1726 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1727 } else { 1728 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1729 } 1730 1731 /* End marker */ 1732 qemu_put_be32(f, 0); 1733 qemu_put_be16(f, 0); 1734 qemu_put_be16(f, 0); 1735 1736 return rc; 1737 } 1738 1739 static int htab_save_complete(QEMUFile *f, void *opaque) 1740 { 1741 sPAPRMachineState *spapr = opaque; 1742 int fd; 1743 1744 /* Iteration header */ 1745 qemu_put_be32(f, 0); 1746 1747 if (!spapr->htab) { 1748 int rc; 1749 1750 assert(kvm_enabled()); 1751 1752 fd = get_htab_fd(spapr); 1753 if (fd < 0) { 1754 return fd; 1755 } 1756 1757 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 1758 if (rc < 0) { 1759 return rc; 1760 } 1761 } else { 1762 if (spapr->htab_first_pass) { 1763 htab_save_first_pass(f, spapr, -1); 1764 } 1765 htab_save_later_pass(f, spapr, -1); 1766 } 1767 1768 /* End marker */ 1769 qemu_put_be32(f, 0); 1770 qemu_put_be16(f, 0); 1771 qemu_put_be16(f, 0); 1772 1773 return 0; 1774 } 1775 1776 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1777 { 1778 sPAPRMachineState *spapr = opaque; 1779 uint32_t section_hdr; 1780 int fd = -1; 1781 1782 if (version_id < 1 || version_id > 1) { 1783 error_report("htab_load() bad version"); 1784 return -EINVAL; 1785 } 1786 1787 section_hdr = qemu_get_be32(f); 1788 1789 if (section_hdr) { 1790 Error *local_err = NULL; 1791 1792 /* First section gives the htab size */ 1793 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 1794 if (local_err) { 1795 error_report_err(local_err); 1796 return -EINVAL; 1797 } 1798 return 0; 1799 } 1800 1801 if (!spapr->htab) { 1802 assert(kvm_enabled()); 1803 1804 fd = kvmppc_get_htab_fd(true); 1805 if (fd < 0) { 1806 error_report("Unable to open fd to restore KVM hash table: %s", 1807 strerror(errno)); 1808 } 1809 } 1810 1811 while (true) { 1812 uint32_t index; 1813 uint16_t n_valid, n_invalid; 1814 1815 index = qemu_get_be32(f); 1816 n_valid = qemu_get_be16(f); 1817 n_invalid = qemu_get_be16(f); 1818 1819 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1820 /* End of Stream */ 1821 break; 1822 } 1823 1824 if ((index + n_valid + n_invalid) > 1825 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1826 /* Bad index in stream */ 1827 error_report( 1828 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 1829 index, n_valid, n_invalid, spapr->htab_shift); 1830 return -EINVAL; 1831 } 1832 1833 if (spapr->htab) { 1834 if (n_valid) { 1835 qemu_get_buffer(f, HPTE(spapr->htab, index), 1836 HASH_PTE_SIZE_64 * n_valid); 1837 } 1838 if (n_invalid) { 1839 memset(HPTE(spapr->htab, index + n_valid), 0, 1840 HASH_PTE_SIZE_64 * n_invalid); 1841 } 1842 } else { 1843 int rc; 1844 1845 assert(fd >= 0); 1846 1847 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1848 if (rc < 0) { 1849 return rc; 1850 } 1851 } 1852 } 1853 1854 if (!spapr->htab) { 1855 assert(fd >= 0); 1856 close(fd); 1857 } 1858 1859 return 0; 1860 } 1861 1862 static void htab_cleanup(void *opaque) 1863 { 1864 sPAPRMachineState *spapr = opaque; 1865 1866 close_htab_fd(spapr); 1867 } 1868 1869 static SaveVMHandlers savevm_htab_handlers = { 1870 .save_live_setup = htab_save_setup, 1871 .save_live_iterate = htab_save_iterate, 1872 .save_live_complete_precopy = htab_save_complete, 1873 .cleanup = htab_cleanup, 1874 .load_state = htab_load, 1875 }; 1876 1877 static void spapr_boot_set(void *opaque, const char *boot_device, 1878 Error **errp) 1879 { 1880 MachineState *machine = MACHINE(qdev_get_machine()); 1881 machine->boot_order = g_strdup(boot_device); 1882 } 1883 1884 /* 1885 * Reset routine for LMB DR devices. 1886 * 1887 * Unlike PCI DR devices, LMB DR devices explicitly register this reset 1888 * routine. Reset for PCI DR devices will be handled by PHB reset routine 1889 * when it walks all its children devices. LMB devices reset occurs 1890 * as part of spapr_ppc_reset(). 1891 */ 1892 static void spapr_drc_reset(void *opaque) 1893 { 1894 sPAPRDRConnector *drc = opaque; 1895 DeviceState *d = DEVICE(drc); 1896 1897 if (d) { 1898 device_reset(d); 1899 } 1900 } 1901 1902 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 1903 { 1904 MachineState *machine = MACHINE(spapr); 1905 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 1906 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 1907 int i; 1908 1909 for (i = 0; i < nr_lmbs; i++) { 1910 sPAPRDRConnector *drc; 1911 uint64_t addr; 1912 1913 addr = i * lmb_size + spapr->hotplug_memory.base; 1914 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB, 1915 addr/lmb_size); 1916 qemu_register_reset(spapr_drc_reset, drc); 1917 } 1918 } 1919 1920 /* 1921 * If RAM size, maxmem size and individual node mem sizes aren't aligned 1922 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 1923 * since we can't support such unaligned sizes with DRCONF_MEMORY. 1924 */ 1925 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 1926 { 1927 int i; 1928 1929 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1930 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 1931 " is not aligned to %llu MiB", 1932 machine->ram_size, 1933 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1934 return; 1935 } 1936 1937 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1938 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 1939 " is not aligned to %llu MiB", 1940 machine->ram_size, 1941 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1942 return; 1943 } 1944 1945 for (i = 0; i < nb_numa_nodes; i++) { 1946 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 1947 error_setg(errp, 1948 "Node %d memory size 0x%" PRIx64 1949 " is not aligned to %llu MiB", 1950 i, numa_info[i].node_mem, 1951 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1952 return; 1953 } 1954 } 1955 } 1956 1957 /* find cpu slot in machine->possible_cpus by core_id */ 1958 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 1959 { 1960 int index = id / smp_threads; 1961 1962 if (index >= ms->possible_cpus->len) { 1963 return NULL; 1964 } 1965 if (idx) { 1966 *idx = index; 1967 } 1968 return &ms->possible_cpus->cpus[index]; 1969 } 1970 1971 static void spapr_init_cpus(sPAPRMachineState *spapr) 1972 { 1973 MachineState *machine = MACHINE(spapr); 1974 MachineClass *mc = MACHINE_GET_CLASS(machine); 1975 char *type = spapr_get_cpu_core_type(machine->cpu_model); 1976 int smt = kvmppc_smt_threads(); 1977 const CPUArchIdList *possible_cpus; 1978 int boot_cores_nr = smp_cpus / smp_threads; 1979 int i; 1980 1981 if (!type) { 1982 error_report("Unable to find sPAPR CPU Core definition"); 1983 exit(1); 1984 } 1985 1986 possible_cpus = mc->possible_cpu_arch_ids(machine); 1987 if (mc->has_hotpluggable_cpus) { 1988 if (smp_cpus % smp_threads) { 1989 error_report("smp_cpus (%u) must be multiple of threads (%u)", 1990 smp_cpus, smp_threads); 1991 exit(1); 1992 } 1993 if (max_cpus % smp_threads) { 1994 error_report("max_cpus (%u) must be multiple of threads (%u)", 1995 max_cpus, smp_threads); 1996 exit(1); 1997 } 1998 } else { 1999 if (max_cpus != smp_cpus) { 2000 error_report("This machine version does not support CPU hotplug"); 2001 exit(1); 2002 } 2003 boot_cores_nr = possible_cpus->len; 2004 } 2005 2006 for (i = 0; i < possible_cpus->len; i++) { 2007 int core_id = i * smp_threads; 2008 2009 if (mc->has_hotpluggable_cpus) { 2010 sPAPRDRConnector *drc = 2011 spapr_dr_connector_new(OBJECT(spapr), 2012 SPAPR_DR_CONNECTOR_TYPE_CPU, 2013 (core_id / smp_threads) * smt); 2014 2015 qemu_register_reset(spapr_drc_reset, drc); 2016 } 2017 2018 if (i < boot_cores_nr) { 2019 Object *core = object_new(type); 2020 int nr_threads = smp_threads; 2021 2022 /* Handle the partially filled core for older machine types */ 2023 if ((i + 1) * smp_threads >= smp_cpus) { 2024 nr_threads = smp_cpus - i * smp_threads; 2025 } 2026 2027 object_property_set_int(core, nr_threads, "nr-threads", 2028 &error_fatal); 2029 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2030 &error_fatal); 2031 object_property_set_bool(core, true, "realized", &error_fatal); 2032 } 2033 } 2034 g_free(type); 2035 } 2036 2037 /* pSeries LPAR / sPAPR hardware init */ 2038 static void ppc_spapr_init(MachineState *machine) 2039 { 2040 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2041 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2042 const char *kernel_filename = machine->kernel_filename; 2043 const char *initrd_filename = machine->initrd_filename; 2044 PCIHostState *phb; 2045 int i; 2046 MemoryRegion *sysmem = get_system_memory(); 2047 MemoryRegion *ram = g_new(MemoryRegion, 1); 2048 MemoryRegion *rma_region; 2049 void *rma = NULL; 2050 hwaddr rma_alloc_size; 2051 hwaddr node0_size = spapr_node0_size(); 2052 long load_limit, fw_size; 2053 char *filename; 2054 2055 msi_nonbroken = true; 2056 2057 QLIST_INIT(&spapr->phbs); 2058 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2059 2060 /* Allocate RMA if necessary */ 2061 rma_alloc_size = kvmppc_alloc_rma(&rma); 2062 2063 if (rma_alloc_size == -1) { 2064 error_report("Unable to create RMA"); 2065 exit(1); 2066 } 2067 2068 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 2069 spapr->rma_size = rma_alloc_size; 2070 } else { 2071 spapr->rma_size = node0_size; 2072 2073 /* With KVM, we don't actually know whether KVM supports an 2074 * unbounded RMA (PR KVM) or is limited by the hash table size 2075 * (HV KVM using VRMA), so we always assume the latter 2076 * 2077 * In that case, we also limit the initial allocations for RTAS 2078 * etc... to 256M since we have no way to know what the VRMA size 2079 * is going to be as it depends on the size of the hash table 2080 * isn't determined yet. 2081 */ 2082 if (kvm_enabled()) { 2083 spapr->vrma_adjust = 1; 2084 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2085 } 2086 2087 /* Actually we don't support unbounded RMA anymore since we 2088 * added proper emulation of HV mode. The max we can get is 2089 * 16G which also happens to be what we configure for PAPR 2090 * mode so make sure we don't do anything bigger than that 2091 */ 2092 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2093 } 2094 2095 if (spapr->rma_size > node0_size) { 2096 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2097 spapr->rma_size); 2098 exit(1); 2099 } 2100 2101 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2102 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2103 2104 /* Set up Interrupt Controller before we create the VCPUs */ 2105 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal); 2106 2107 /* Set up containers for ibm,client-set-architecture negotiated options */ 2108 spapr->ov5 = spapr_ovec_new(); 2109 spapr->ov5_cas = spapr_ovec_new(); 2110 2111 if (smc->dr_lmb_enabled) { 2112 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2113 spapr_validate_node_memory(machine, &error_fatal); 2114 } 2115 2116 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2117 if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) { 2118 /* KVM and TCG always allow GTSE with radix... */ 2119 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2120 } 2121 /* ... but not with hash (currently). */ 2122 2123 /* advertise support for dedicated HP event source to guests */ 2124 if (spapr->use_hotplug_event_source) { 2125 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2126 } 2127 2128 /* init CPUs */ 2129 if (machine->cpu_model == NULL) { 2130 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu; 2131 } 2132 2133 ppc_cpu_parse_features(machine->cpu_model); 2134 2135 spapr_init_cpus(spapr); 2136 2137 if (kvm_enabled()) { 2138 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2139 kvmppc_enable_logical_ci_hcalls(); 2140 kvmppc_enable_set_mode_hcall(); 2141 2142 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2143 kvmppc_enable_clear_ref_mod_hcalls(); 2144 } 2145 2146 /* allocate RAM */ 2147 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2148 machine->ram_size); 2149 memory_region_add_subregion(sysmem, 0, ram); 2150 2151 if (rma_alloc_size && rma) { 2152 rma_region = g_new(MemoryRegion, 1); 2153 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 2154 rma_alloc_size, rma); 2155 vmstate_register_ram_global(rma_region); 2156 memory_region_add_subregion(sysmem, 0, rma_region); 2157 } 2158 2159 /* initialize hotplug memory address space */ 2160 if (machine->ram_size < machine->maxram_size) { 2161 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 2162 /* 2163 * Limit the number of hotpluggable memory slots to half the number 2164 * slots that KVM supports, leaving the other half for PCI and other 2165 * devices. However ensure that number of slots doesn't drop below 32. 2166 */ 2167 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2168 SPAPR_MAX_RAM_SLOTS; 2169 2170 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2171 max_memslots = SPAPR_MAX_RAM_SLOTS; 2172 } 2173 if (machine->ram_slots > max_memslots) { 2174 error_report("Specified number of memory slots %" 2175 PRIu64" exceeds max supported %d", 2176 machine->ram_slots, max_memslots); 2177 exit(1); 2178 } 2179 2180 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 2181 SPAPR_HOTPLUG_MEM_ALIGN); 2182 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 2183 "hotplug-memory", hotplug_mem_size); 2184 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 2185 &spapr->hotplug_memory.mr); 2186 } 2187 2188 if (smc->dr_lmb_enabled) { 2189 spapr_create_lmb_dr_connectors(spapr); 2190 } 2191 2192 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2193 if (!filename) { 2194 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2195 exit(1); 2196 } 2197 spapr->rtas_size = get_image_size(filename); 2198 if (spapr->rtas_size < 0) { 2199 error_report("Could not get size of LPAR rtas '%s'", filename); 2200 exit(1); 2201 } 2202 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2203 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2204 error_report("Could not load LPAR rtas '%s'", filename); 2205 exit(1); 2206 } 2207 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2208 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2209 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2210 exit(1); 2211 } 2212 g_free(filename); 2213 2214 /* Set up RTAS event infrastructure */ 2215 spapr_events_init(spapr); 2216 2217 /* Set up the RTC RTAS interfaces */ 2218 spapr_rtc_create(spapr); 2219 2220 /* Set up VIO bus */ 2221 spapr->vio_bus = spapr_vio_bus_init(); 2222 2223 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 2224 if (serial_hds[i]) { 2225 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 2226 } 2227 } 2228 2229 /* We always have at least the nvram device on VIO */ 2230 spapr_create_nvram(spapr); 2231 2232 /* Set up PCI */ 2233 spapr_pci_rtas_init(); 2234 2235 phb = spapr_create_phb(spapr, 0); 2236 2237 for (i = 0; i < nb_nics; i++) { 2238 NICInfo *nd = &nd_table[i]; 2239 2240 if (!nd->model) { 2241 nd->model = g_strdup("ibmveth"); 2242 } 2243 2244 if (strcmp(nd->model, "ibmveth") == 0) { 2245 spapr_vlan_create(spapr->vio_bus, nd); 2246 } else { 2247 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2248 } 2249 } 2250 2251 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2252 spapr_vscsi_create(spapr->vio_bus); 2253 } 2254 2255 /* Graphics */ 2256 if (spapr_vga_init(phb->bus, &error_fatal)) { 2257 spapr->has_graphics = true; 2258 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2259 } 2260 2261 if (machine->usb) { 2262 if (smc->use_ohci_by_default) { 2263 pci_create_simple(phb->bus, -1, "pci-ohci"); 2264 } else { 2265 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2266 } 2267 2268 if (spapr->has_graphics) { 2269 USBBus *usb_bus = usb_bus_find(-1); 2270 2271 usb_create_simple(usb_bus, "usb-kbd"); 2272 usb_create_simple(usb_bus, "usb-mouse"); 2273 } 2274 } 2275 2276 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 2277 error_report( 2278 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2279 MIN_RMA_SLOF); 2280 exit(1); 2281 } 2282 2283 if (kernel_filename) { 2284 uint64_t lowaddr = 0; 2285 2286 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2287 NULL, NULL, &lowaddr, NULL, 1, 2288 PPC_ELF_MACHINE, 0, 0); 2289 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2290 spapr->kernel_size = load_elf(kernel_filename, 2291 translate_kernel_address, NULL, NULL, 2292 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2293 0, 0); 2294 spapr->kernel_le = spapr->kernel_size > 0; 2295 } 2296 if (spapr->kernel_size < 0) { 2297 error_report("error loading %s: %s", kernel_filename, 2298 load_elf_strerror(spapr->kernel_size)); 2299 exit(1); 2300 } 2301 2302 /* load initrd */ 2303 if (initrd_filename) { 2304 /* Try to locate the initrd in the gap between the kernel 2305 * and the firmware. Add a bit of space just in case 2306 */ 2307 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2308 + 0x1ffff) & ~0xffff; 2309 spapr->initrd_size = load_image_targphys(initrd_filename, 2310 spapr->initrd_base, 2311 load_limit 2312 - spapr->initrd_base); 2313 if (spapr->initrd_size < 0) { 2314 error_report("could not load initial ram disk '%s'", 2315 initrd_filename); 2316 exit(1); 2317 } 2318 } 2319 } 2320 2321 if (bios_name == NULL) { 2322 bios_name = FW_FILE_NAME; 2323 } 2324 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2325 if (!filename) { 2326 error_report("Could not find LPAR firmware '%s'", bios_name); 2327 exit(1); 2328 } 2329 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2330 if (fw_size <= 0) { 2331 error_report("Could not load LPAR firmware '%s'", filename); 2332 exit(1); 2333 } 2334 g_free(filename); 2335 2336 /* FIXME: Should register things through the MachineState's qdev 2337 * interface, this is a legacy from the sPAPREnvironment structure 2338 * which predated MachineState but had a similar function */ 2339 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2340 register_savevm_live(NULL, "spapr/htab", -1, 1, 2341 &savevm_htab_handlers, spapr); 2342 2343 /* used by RTAS */ 2344 QTAILQ_INIT(&spapr->ccs_list); 2345 qemu_register_reset(spapr_ccs_reset_hook, spapr); 2346 2347 qemu_register_boot_set(spapr_boot_set, spapr); 2348 2349 if (kvm_enabled()) { 2350 /* to stop and start vmclock */ 2351 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2352 &spapr->tb); 2353 2354 kvmppc_spapr_enable_inkernel_multitce(); 2355 } 2356 } 2357 2358 static int spapr_kvm_type(const char *vm_type) 2359 { 2360 if (!vm_type) { 2361 return 0; 2362 } 2363 2364 if (!strcmp(vm_type, "HV")) { 2365 return 1; 2366 } 2367 2368 if (!strcmp(vm_type, "PR")) { 2369 return 2; 2370 } 2371 2372 error_report("Unknown kvm-type specified '%s'", vm_type); 2373 exit(1); 2374 } 2375 2376 /* 2377 * Implementation of an interface to adjust firmware path 2378 * for the bootindex property handling. 2379 */ 2380 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2381 DeviceState *dev) 2382 { 2383 #define CAST(type, obj, name) \ 2384 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2385 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2386 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2387 2388 if (d) { 2389 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2390 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2391 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2392 2393 if (spapr) { 2394 /* 2395 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2396 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2397 * in the top 16 bits of the 64-bit LUN 2398 */ 2399 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2400 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2401 (uint64_t)id << 48); 2402 } else if (virtio) { 2403 /* 2404 * We use SRP luns of the form 01000000 | (target << 8) | lun 2405 * in the top 32 bits of the 64-bit LUN 2406 * Note: the quote above is from SLOF and it is wrong, 2407 * the actual binding is: 2408 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2409 */ 2410 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2411 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2412 (uint64_t)id << 32); 2413 } else if (usb) { 2414 /* 2415 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2416 * in the top 32 bits of the 64-bit LUN 2417 */ 2418 unsigned usb_port = atoi(usb->port->path); 2419 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2420 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2421 (uint64_t)id << 32); 2422 } 2423 } 2424 2425 /* 2426 * SLOF probes the USB devices, and if it recognizes that the device is a 2427 * storage device, it changes its name to "storage" instead of "usb-host", 2428 * and additionally adds a child node for the SCSI LUN, so the correct 2429 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2430 */ 2431 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2432 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2433 if (usb_host_dev_is_scsi_storage(usbdev)) { 2434 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2435 } 2436 } 2437 2438 if (phb) { 2439 /* Replace "pci" with "pci@800000020000000" */ 2440 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2441 } 2442 2443 return NULL; 2444 } 2445 2446 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2447 { 2448 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2449 2450 return g_strdup(spapr->kvm_type); 2451 } 2452 2453 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2454 { 2455 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2456 2457 g_free(spapr->kvm_type); 2458 spapr->kvm_type = g_strdup(value); 2459 } 2460 2461 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2462 { 2463 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2464 2465 return spapr->use_hotplug_event_source; 2466 } 2467 2468 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2469 Error **errp) 2470 { 2471 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2472 2473 spapr->use_hotplug_event_source = value; 2474 } 2475 2476 static void spapr_machine_initfn(Object *obj) 2477 { 2478 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2479 2480 spapr->htab_fd = -1; 2481 spapr->use_hotplug_event_source = true; 2482 object_property_add_str(obj, "kvm-type", 2483 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2484 object_property_set_description(obj, "kvm-type", 2485 "Specifies the KVM virtualization mode (HV, PR)", 2486 NULL); 2487 object_property_add_bool(obj, "modern-hotplug-events", 2488 spapr_get_modern_hotplug_events, 2489 spapr_set_modern_hotplug_events, 2490 NULL); 2491 object_property_set_description(obj, "modern-hotplug-events", 2492 "Use dedicated hotplug event mechanism in" 2493 " place of standard EPOW events when possible" 2494 " (required for memory hot-unplug support)", 2495 NULL); 2496 } 2497 2498 static void spapr_machine_finalizefn(Object *obj) 2499 { 2500 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2501 2502 g_free(spapr->kvm_type); 2503 } 2504 2505 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 2506 { 2507 cpu_synchronize_state(cs); 2508 ppc_cpu_do_system_reset(cs); 2509 } 2510 2511 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2512 { 2513 CPUState *cs; 2514 2515 CPU_FOREACH(cs) { 2516 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 2517 } 2518 } 2519 2520 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2521 uint32_t node, bool dedicated_hp_event_source, 2522 Error **errp) 2523 { 2524 sPAPRDRConnector *drc; 2525 sPAPRDRConnectorClass *drck; 2526 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2527 int i, fdt_offset, fdt_size; 2528 void *fdt; 2529 uint64_t addr = addr_start; 2530 2531 for (i = 0; i < nr_lmbs; i++) { 2532 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2533 addr/SPAPR_MEMORY_BLOCK_SIZE); 2534 g_assert(drc); 2535 2536 fdt = create_device_tree(&fdt_size); 2537 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2538 SPAPR_MEMORY_BLOCK_SIZE); 2539 2540 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2541 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); 2542 addr += SPAPR_MEMORY_BLOCK_SIZE; 2543 if (!dev->hotplugged) { 2544 /* guests expect coldplugged LMBs to be pre-allocated */ 2545 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); 2546 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); 2547 } 2548 } 2549 /* send hotplug notification to the 2550 * guest only in case of hotplugged memory 2551 */ 2552 if (dev->hotplugged) { 2553 if (dedicated_hp_event_source) { 2554 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2555 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2556 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2557 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2558 nr_lmbs, 2559 spapr_drc_index(drc)); 2560 } else { 2561 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 2562 nr_lmbs); 2563 } 2564 } 2565 } 2566 2567 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2568 uint32_t node, Error **errp) 2569 { 2570 Error *local_err = NULL; 2571 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2572 PCDIMMDevice *dimm = PC_DIMM(dev); 2573 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2574 MemoryRegion *mr = ddc->get_memory_region(dimm); 2575 uint64_t align = memory_region_get_alignment(mr); 2576 uint64_t size = memory_region_size(mr); 2577 uint64_t addr; 2578 2579 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 2580 if (local_err) { 2581 goto out; 2582 } 2583 2584 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2585 if (local_err) { 2586 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2587 goto out; 2588 } 2589 2590 spapr_add_lmbs(dev, addr, size, node, 2591 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 2592 &error_abort); 2593 2594 out: 2595 error_propagate(errp, local_err); 2596 } 2597 2598 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2599 Error **errp) 2600 { 2601 PCDIMMDevice *dimm = PC_DIMM(dev); 2602 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2603 MemoryRegion *mr = ddc->get_memory_region(dimm); 2604 uint64_t size = memory_region_size(mr); 2605 char *mem_dev; 2606 2607 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 2608 error_setg(errp, "Hotplugged memory size must be a multiple of " 2609 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2610 return; 2611 } 2612 2613 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); 2614 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { 2615 error_setg(errp, "Memory backend has bad page size. " 2616 "Use 'memory-backend-file' with correct mem-path."); 2617 return; 2618 } 2619 } 2620 2621 struct sPAPRDIMMState { 2622 PCDIMMDevice *dimm; 2623 uint32_t nr_lmbs; 2624 QTAILQ_ENTRY(sPAPRDIMMState) next; 2625 }; 2626 2627 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, 2628 PCDIMMDevice *dimm) 2629 { 2630 sPAPRDIMMState *dimm_state = NULL; 2631 2632 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 2633 if (dimm_state->dimm == dimm) { 2634 break; 2635 } 2636 } 2637 return dimm_state; 2638 } 2639 2640 static void spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, 2641 sPAPRDIMMState *dimm_state) 2642 { 2643 g_assert(!spapr_pending_dimm_unplugs_find(spapr, dimm_state->dimm)); 2644 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, dimm_state, next); 2645 } 2646 2647 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, 2648 sPAPRDIMMState *dimm_state) 2649 { 2650 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 2651 g_free(dimm_state); 2652 } 2653 2654 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, 2655 PCDIMMDevice *dimm) 2656 { 2657 sPAPRDRConnector *drc; 2658 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2659 MemoryRegion *mr = ddc->get_memory_region(dimm); 2660 uint64_t size = memory_region_size(mr); 2661 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 2662 uint32_t avail_lmbs = 0; 2663 uint64_t addr_start, addr; 2664 int i; 2665 sPAPRDIMMState *ds; 2666 2667 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 2668 &error_abort); 2669 2670 addr = addr_start; 2671 for (i = 0; i < nr_lmbs; i++) { 2672 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2673 addr / SPAPR_MEMORY_BLOCK_SIZE); 2674 g_assert(drc); 2675 if (drc->indicator_state != SPAPR_DR_INDICATOR_STATE_INACTIVE) { 2676 avail_lmbs++; 2677 } 2678 addr += SPAPR_MEMORY_BLOCK_SIZE; 2679 } 2680 2681 ds = g_malloc0(sizeof(sPAPRDIMMState)); 2682 ds->nr_lmbs = avail_lmbs; 2683 ds->dimm = dimm; 2684 spapr_pending_dimm_unplugs_add(ms, ds); 2685 return ds; 2686 } 2687 2688 /* Callback to be called during DRC release. */ 2689 void spapr_lmb_release(DeviceState *dev) 2690 { 2691 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 2692 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 2693 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 2694 2695 /* This information will get lost if a migration occurs 2696 * during the unplug process. In this case recover it. */ 2697 if (ds == NULL) { 2698 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 2699 if (ds->nr_lmbs) { 2700 return; 2701 } 2702 } else if (--ds->nr_lmbs) { 2703 return; 2704 } 2705 2706 spapr_pending_dimm_unplugs_remove(spapr, ds); 2707 2708 /* 2709 * Now that all the LMBs have been removed by the guest, call the 2710 * pc-dimm unplug handler to cleanup up the pc-dimm device. 2711 */ 2712 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2713 } 2714 2715 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2716 Error **errp) 2717 { 2718 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2719 PCDIMMDevice *dimm = PC_DIMM(dev); 2720 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2721 MemoryRegion *mr = ddc->get_memory_region(dimm); 2722 2723 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2724 object_unparent(OBJECT(dev)); 2725 } 2726 2727 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 2728 DeviceState *dev, Error **errp) 2729 { 2730 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 2731 Error *local_err = NULL; 2732 PCDIMMDevice *dimm = PC_DIMM(dev); 2733 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2734 MemoryRegion *mr = ddc->get_memory_region(dimm); 2735 uint64_t size = memory_region_size(mr); 2736 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 2737 uint64_t addr_start, addr; 2738 int i; 2739 sPAPRDRConnector *drc; 2740 sPAPRDRConnectorClass *drck; 2741 sPAPRDIMMState *ds; 2742 2743 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 2744 &local_err); 2745 if (local_err) { 2746 goto out; 2747 } 2748 2749 ds = g_malloc0(sizeof(sPAPRDIMMState)); 2750 ds->nr_lmbs = nr_lmbs; 2751 ds->dimm = dimm; 2752 spapr_pending_dimm_unplugs_add(spapr, ds); 2753 2754 addr = addr_start; 2755 for (i = 0; i < nr_lmbs; i++) { 2756 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2757 addr / SPAPR_MEMORY_BLOCK_SIZE); 2758 g_assert(drc); 2759 2760 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2761 drck->detach(drc, dev, errp); 2762 addr += SPAPR_MEMORY_BLOCK_SIZE; 2763 } 2764 2765 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2766 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2767 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2768 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2769 nr_lmbs, spapr_drc_index(drc)); 2770 out: 2771 error_propagate(errp, local_err); 2772 } 2773 2774 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 2775 sPAPRMachineState *spapr) 2776 { 2777 PowerPCCPU *cpu = POWERPC_CPU(cs); 2778 DeviceClass *dc = DEVICE_GET_CLASS(cs); 2779 int id = ppc_get_vcpu_dt_id(cpu); 2780 void *fdt; 2781 int offset, fdt_size; 2782 char *nodename; 2783 2784 fdt = create_device_tree(&fdt_size); 2785 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 2786 offset = fdt_add_subnode(fdt, 0, nodename); 2787 2788 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 2789 g_free(nodename); 2790 2791 *fdt_offset = offset; 2792 return fdt; 2793 } 2794 2795 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2796 Error **errp) 2797 { 2798 MachineState *ms = MACHINE(qdev_get_machine()); 2799 CPUCore *cc = CPU_CORE(dev); 2800 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 2801 2802 assert(core_slot); 2803 core_slot->cpu = NULL; 2804 object_unparent(OBJECT(dev)); 2805 } 2806 2807 /* Callback to be called during DRC release. */ 2808 void spapr_core_release(DeviceState *dev) 2809 { 2810 HotplugHandler *hotplug_ctrl; 2811 2812 hotplug_ctrl = qdev_get_hotplug_handler(dev); 2813 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2814 } 2815 2816 static 2817 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 2818 Error **errp) 2819 { 2820 int index; 2821 sPAPRDRConnector *drc; 2822 sPAPRDRConnectorClass *drck; 2823 Error *local_err = NULL; 2824 CPUCore *cc = CPU_CORE(dev); 2825 int smt = kvmppc_smt_threads(); 2826 2827 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 2828 error_setg(errp, "Unable to find CPU core with core-id: %d", 2829 cc->core_id); 2830 return; 2831 } 2832 if (index == 0) { 2833 error_setg(errp, "Boot CPU core may not be unplugged"); 2834 return; 2835 } 2836 2837 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt); 2838 g_assert(drc); 2839 2840 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2841 drck->detach(drc, dev, &local_err); 2842 if (local_err) { 2843 error_propagate(errp, local_err); 2844 return; 2845 } 2846 2847 spapr_hotplug_req_remove_by_index(drc); 2848 } 2849 2850 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2851 Error **errp) 2852 { 2853 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 2854 MachineClass *mc = MACHINE_GET_CLASS(spapr); 2855 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 2856 CPUCore *cc = CPU_CORE(dev); 2857 CPUState *cs = CPU(core->threads); 2858 sPAPRDRConnector *drc; 2859 Error *local_err = NULL; 2860 void *fdt = NULL; 2861 int fdt_offset = 0; 2862 int smt = kvmppc_smt_threads(); 2863 CPUArchId *core_slot; 2864 int index; 2865 2866 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 2867 if (!core_slot) { 2868 error_setg(errp, "Unable to find CPU core with core-id: %d", 2869 cc->core_id); 2870 return; 2871 } 2872 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt); 2873 2874 g_assert(drc || !mc->has_hotpluggable_cpus); 2875 2876 /* 2877 * Setup CPU DT entries only for hotplugged CPUs. For boot time or 2878 * coldplugged CPUs DT entries are setup in spapr_build_fdt(). 2879 */ 2880 if (dev->hotplugged) { 2881 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 2882 } 2883 2884 if (drc) { 2885 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2886 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err); 2887 if (local_err) { 2888 g_free(fdt); 2889 error_propagate(errp, local_err); 2890 return; 2891 } 2892 } 2893 2894 if (dev->hotplugged) { 2895 /* 2896 * Send hotplug notification interrupt to the guest only in case 2897 * of hotplugged CPUs. 2898 */ 2899 spapr_hotplug_req_add_by_index(drc); 2900 } else { 2901 /* 2902 * Set the right DRC states for cold plugged CPU. 2903 */ 2904 if (drc) { 2905 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2906 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); 2907 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); 2908 } 2909 } 2910 core_slot->cpu = OBJECT(dev); 2911 } 2912 2913 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2914 Error **errp) 2915 { 2916 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 2917 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 2918 Error *local_err = NULL; 2919 CPUCore *cc = CPU_CORE(dev); 2920 sPAPRCPUCore *sc = SPAPR_CPU_CORE(dev); 2921 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model); 2922 const char *type = object_get_typename(OBJECT(dev)); 2923 CPUArchId *core_slot; 2924 int node_id; 2925 int index; 2926 2927 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 2928 error_setg(&local_err, "CPU hotplug not supported for this machine"); 2929 goto out; 2930 } 2931 2932 if (strcmp(base_core_type, type)) { 2933 error_setg(&local_err, "CPU core type should be %s", base_core_type); 2934 goto out; 2935 } 2936 2937 if (cc->core_id % smp_threads) { 2938 error_setg(&local_err, "invalid core id %d", cc->core_id); 2939 goto out; 2940 } 2941 2942 /* 2943 * In general we should have homogeneous threads-per-core, but old 2944 * (pre hotplug support) machine types allow the last core to have 2945 * reduced threads as a compatibility hack for when we allowed 2946 * total vcpus not a multiple of threads-per-core. 2947 */ 2948 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 2949 error_setg(errp, "invalid nr-threads %d, must be %d", 2950 cc->nr_threads, smp_threads); 2951 return; 2952 } 2953 2954 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 2955 if (!core_slot) { 2956 error_setg(&local_err, "core id %d out of range", cc->core_id); 2957 goto out; 2958 } 2959 2960 if (core_slot->cpu) { 2961 error_setg(&local_err, "core %d already populated", cc->core_id); 2962 goto out; 2963 } 2964 2965 node_id = core_slot->props.node_id; 2966 if (!core_slot->props.has_node_id) { 2967 /* by default CPUState::numa_node was 0 if it's not set via CLI 2968 * keep it this way for now but in future we probably should 2969 * refuse to start up with incomplete numa mapping */ 2970 node_id = 0; 2971 } 2972 if (sc->node_id == CPU_UNSET_NUMA_NODE_ID) { 2973 sc->node_id = node_id; 2974 } else if (sc->node_id != node_id) { 2975 error_setg(&local_err, "node-id %d must match numa node specified" 2976 "with -numa option for cpu-index %d", sc->node_id, cc->core_id); 2977 goto out; 2978 } 2979 2980 out: 2981 g_free(base_core_type); 2982 error_propagate(errp, local_err); 2983 } 2984 2985 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 2986 DeviceState *dev, Error **errp) 2987 { 2988 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 2989 2990 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2991 int node; 2992 2993 if (!smc->dr_lmb_enabled) { 2994 error_setg(errp, "Memory hotplug not supported for this machine"); 2995 return; 2996 } 2997 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 2998 if (*errp) { 2999 return; 3000 } 3001 if (node < 0 || node >= MAX_NODES) { 3002 error_setg(errp, "Invaild node %d", node); 3003 return; 3004 } 3005 3006 /* 3007 * Currently PowerPC kernel doesn't allow hot-adding memory to 3008 * memory-less node, but instead will silently add the memory 3009 * to the first node that has some memory. This causes two 3010 * unexpected behaviours for the user. 3011 * 3012 * - Memory gets hotplugged to a different node than what the user 3013 * specified. 3014 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 3015 * to memory-less node, a reboot will set things accordingly 3016 * and the previously hotplugged memory now ends in the right node. 3017 * This appears as if some memory moved from one node to another. 3018 * 3019 * So until kernel starts supporting memory hotplug to memory-less 3020 * nodes, just prevent such attempts upfront in QEMU. 3021 */ 3022 if (nb_numa_nodes && !numa_info[node].node_mem) { 3023 error_setg(errp, "Can't hotplug memory to memory-less node %d", 3024 node); 3025 return; 3026 } 3027 3028 spapr_memory_plug(hotplug_dev, dev, node, errp); 3029 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3030 spapr_core_plug(hotplug_dev, dev, errp); 3031 } 3032 } 3033 3034 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 3035 DeviceState *dev, Error **errp) 3036 { 3037 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 3038 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 3039 3040 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3041 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3042 spapr_memory_unplug(hotplug_dev, dev, errp); 3043 } else { 3044 error_setg(errp, "Memory hot unplug not supported for this guest"); 3045 } 3046 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3047 if (!mc->has_hotpluggable_cpus) { 3048 error_setg(errp, "CPU hot unplug not supported on this machine"); 3049 return; 3050 } 3051 spapr_core_unplug(hotplug_dev, dev, errp); 3052 } 3053 } 3054 3055 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 3056 DeviceState *dev, Error **errp) 3057 { 3058 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 3059 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 3060 3061 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3062 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3063 spapr_memory_unplug_request(hotplug_dev, dev, errp); 3064 } else { 3065 /* NOTE: this means there is a window after guest reset, prior to 3066 * CAS negotiation, where unplug requests will fail due to the 3067 * capability not being detected yet. This is a bit different than 3068 * the case with PCI unplug, where the events will be queued and 3069 * eventually handled by the guest after boot 3070 */ 3071 error_setg(errp, "Memory hot unplug not supported for this guest"); 3072 } 3073 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3074 if (!mc->has_hotpluggable_cpus) { 3075 error_setg(errp, "CPU hot unplug not supported on this machine"); 3076 return; 3077 } 3078 spapr_core_unplug_request(hotplug_dev, dev, errp); 3079 } 3080 } 3081 3082 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 3083 DeviceState *dev, Error **errp) 3084 { 3085 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3086 spapr_memory_pre_plug(hotplug_dev, dev, errp); 3087 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3088 spapr_core_pre_plug(hotplug_dev, dev, errp); 3089 } 3090 } 3091 3092 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 3093 DeviceState *dev) 3094 { 3095 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3096 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3097 return HOTPLUG_HANDLER(machine); 3098 } 3099 return NULL; 3100 } 3101 3102 static CpuInstanceProperties 3103 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 3104 { 3105 CPUArchId *core_slot; 3106 MachineClass *mc = MACHINE_GET_CLASS(machine); 3107 3108 /* make sure possible_cpu are intialized */ 3109 mc->possible_cpu_arch_ids(machine); 3110 /* get CPU core slot containing thread that matches cpu_index */ 3111 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 3112 assert(core_slot); 3113 return core_slot->props; 3114 } 3115 3116 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 3117 { 3118 int i; 3119 int spapr_max_cores = max_cpus / smp_threads; 3120 MachineClass *mc = MACHINE_GET_CLASS(machine); 3121 3122 if (!mc->has_hotpluggable_cpus) { 3123 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 3124 } 3125 if (machine->possible_cpus) { 3126 assert(machine->possible_cpus->len == spapr_max_cores); 3127 return machine->possible_cpus; 3128 } 3129 3130 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 3131 sizeof(CPUArchId) * spapr_max_cores); 3132 machine->possible_cpus->len = spapr_max_cores; 3133 for (i = 0; i < machine->possible_cpus->len; i++) { 3134 int core_id = i * smp_threads; 3135 3136 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 3137 machine->possible_cpus->cpus[i].arch_id = core_id; 3138 machine->possible_cpus->cpus[i].props.has_core_id = true; 3139 machine->possible_cpus->cpus[i].props.core_id = core_id; 3140 3141 /* default distribution of CPUs over NUMA nodes */ 3142 if (nb_numa_nodes) { 3143 /* preset values but do not enable them i.e. 'has_node_id = false', 3144 * numa init code will enable them later if manual mapping wasn't 3145 * present on CLI */ 3146 machine->possible_cpus->cpus[i].props.node_id = 3147 core_id / smp_threads / smp_cores % nb_numa_nodes; 3148 } 3149 } 3150 return machine->possible_cpus; 3151 } 3152 3153 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 3154 uint64_t *buid, hwaddr *pio, 3155 hwaddr *mmio32, hwaddr *mmio64, 3156 unsigned n_dma, uint32_t *liobns, Error **errp) 3157 { 3158 /* 3159 * New-style PHB window placement. 3160 * 3161 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 3162 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 3163 * windows. 3164 * 3165 * Some guest kernels can't work with MMIO windows above 1<<46 3166 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 3167 * 3168 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 3169 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 3170 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 3171 * 1TiB 64-bit MMIO windows for each PHB. 3172 */ 3173 const uint64_t base_buid = 0x800000020000000ULL; 3174 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 3175 SPAPR_PCI_MEM64_WIN_SIZE - 1) 3176 int i; 3177 3178 /* Sanity check natural alignments */ 3179 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3180 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3181 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 3182 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 3183 /* Sanity check bounds */ 3184 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 3185 SPAPR_PCI_MEM32_WIN_SIZE); 3186 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 3187 SPAPR_PCI_MEM64_WIN_SIZE); 3188 3189 if (index >= SPAPR_MAX_PHBS) { 3190 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 3191 SPAPR_MAX_PHBS - 1); 3192 return; 3193 } 3194 3195 *buid = base_buid + index; 3196 for (i = 0; i < n_dma; ++i) { 3197 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3198 } 3199 3200 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 3201 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 3202 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 3203 } 3204 3205 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 3206 { 3207 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3208 3209 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 3210 } 3211 3212 static void spapr_ics_resend(XICSFabric *dev) 3213 { 3214 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3215 3216 ics_resend(spapr->ics); 3217 } 3218 3219 static ICPState *spapr_icp_get(XICSFabric *xi, int cpu_dt_id) 3220 { 3221 PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id); 3222 3223 return cpu ? ICP(cpu->intc) : NULL; 3224 } 3225 3226 static void spapr_pic_print_info(InterruptStatsProvider *obj, 3227 Monitor *mon) 3228 { 3229 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3230 CPUState *cs; 3231 3232 CPU_FOREACH(cs) { 3233 PowerPCCPU *cpu = POWERPC_CPU(cs); 3234 3235 icp_pic_print_info(ICP(cpu->intc), mon); 3236 } 3237 3238 ics_pic_print_info(spapr->ics, mon); 3239 } 3240 3241 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3242 { 3243 MachineClass *mc = MACHINE_CLASS(oc); 3244 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3245 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3246 NMIClass *nc = NMI_CLASS(oc); 3247 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3248 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3249 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3250 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 3251 3252 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3253 3254 /* 3255 * We set up the default / latest behaviour here. The class_init 3256 * functions for the specific versioned machine types can override 3257 * these details for backwards compatibility 3258 */ 3259 mc->init = ppc_spapr_init; 3260 mc->reset = ppc_spapr_reset; 3261 mc->block_default_type = IF_SCSI; 3262 mc->max_cpus = 1024; 3263 mc->no_parallel = 1; 3264 mc->default_boot_order = ""; 3265 mc->default_ram_size = 512 * M_BYTE; 3266 mc->kvm_type = spapr_kvm_type; 3267 mc->has_dynamic_sysbus = true; 3268 mc->pci_allow_0_address = true; 3269 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3270 hc->pre_plug = spapr_machine_device_pre_plug; 3271 hc->plug = spapr_machine_device_plug; 3272 hc->unplug = spapr_machine_device_unplug; 3273 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 3274 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3275 hc->unplug_request = spapr_machine_device_unplug_request; 3276 3277 smc->dr_lmb_enabled = true; 3278 smc->tcg_default_cpu = "POWER8"; 3279 mc->has_hotpluggable_cpus = true; 3280 fwc->get_dev_path = spapr_get_fw_dev_path; 3281 nc->nmi_monitor_handler = spapr_nmi; 3282 smc->phb_placement = spapr_phb_placement; 3283 vhc->hypercall = emulate_spapr_hypercall; 3284 vhc->hpt_mask = spapr_hpt_mask; 3285 vhc->map_hptes = spapr_map_hptes; 3286 vhc->unmap_hptes = spapr_unmap_hptes; 3287 vhc->store_hpte = spapr_store_hpte; 3288 vhc->get_patbe = spapr_get_patbe; 3289 xic->ics_get = spapr_ics_get; 3290 xic->ics_resend = spapr_ics_resend; 3291 xic->icp_get = spapr_icp_get; 3292 ispc->print_info = spapr_pic_print_info; 3293 /* Force NUMA node memory size to be a multiple of 3294 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 3295 * in which LMBs are represented and hot-added 3296 */ 3297 mc->numa_mem_align_shift = 28; 3298 } 3299 3300 static const TypeInfo spapr_machine_info = { 3301 .name = TYPE_SPAPR_MACHINE, 3302 .parent = TYPE_MACHINE, 3303 .abstract = true, 3304 .instance_size = sizeof(sPAPRMachineState), 3305 .instance_init = spapr_machine_initfn, 3306 .instance_finalize = spapr_machine_finalizefn, 3307 .class_size = sizeof(sPAPRMachineClass), 3308 .class_init = spapr_machine_class_init, 3309 .interfaces = (InterfaceInfo[]) { 3310 { TYPE_FW_PATH_PROVIDER }, 3311 { TYPE_NMI }, 3312 { TYPE_HOTPLUG_HANDLER }, 3313 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 3314 { TYPE_XICS_FABRIC }, 3315 { TYPE_INTERRUPT_STATS_PROVIDER }, 3316 { } 3317 }, 3318 }; 3319 3320 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 3321 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 3322 void *data) \ 3323 { \ 3324 MachineClass *mc = MACHINE_CLASS(oc); \ 3325 spapr_machine_##suffix##_class_options(mc); \ 3326 if (latest) { \ 3327 mc->alias = "pseries"; \ 3328 mc->is_default = 1; \ 3329 } \ 3330 } \ 3331 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 3332 { \ 3333 MachineState *machine = MACHINE(obj); \ 3334 spapr_machine_##suffix##_instance_options(machine); \ 3335 } \ 3336 static const TypeInfo spapr_machine_##suffix##_info = { \ 3337 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 3338 .parent = TYPE_SPAPR_MACHINE, \ 3339 .class_init = spapr_machine_##suffix##_class_init, \ 3340 .instance_init = spapr_machine_##suffix##_instance_init, \ 3341 }; \ 3342 static void spapr_machine_register_##suffix(void) \ 3343 { \ 3344 type_register(&spapr_machine_##suffix##_info); \ 3345 } \ 3346 type_init(spapr_machine_register_##suffix) 3347 3348 /* 3349 * pseries-2.10 3350 */ 3351 static void spapr_machine_2_10_instance_options(MachineState *machine) 3352 { 3353 } 3354 3355 static void spapr_machine_2_10_class_options(MachineClass *mc) 3356 { 3357 /* Defaults for the latest behaviour inherited from the base class */ 3358 } 3359 3360 DEFINE_SPAPR_MACHINE(2_10, "2.10", true); 3361 3362 /* 3363 * pseries-2.9 3364 */ 3365 #define SPAPR_COMPAT_2_9 \ 3366 HW_COMPAT_2_9 3367 3368 static void spapr_machine_2_9_instance_options(MachineState *machine) 3369 { 3370 spapr_machine_2_10_instance_options(machine); 3371 } 3372 3373 static void spapr_machine_2_9_class_options(MachineClass *mc) 3374 { 3375 spapr_machine_2_10_class_options(mc); 3376 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); 3377 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 3378 } 3379 3380 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 3381 3382 /* 3383 * pseries-2.8 3384 */ 3385 #define SPAPR_COMPAT_2_8 \ 3386 HW_COMPAT_2_8 \ 3387 { \ 3388 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3389 .property = "pcie-extended-configuration-space", \ 3390 .value = "off", \ 3391 }, 3392 3393 static void spapr_machine_2_8_instance_options(MachineState *machine) 3394 { 3395 spapr_machine_2_9_instance_options(machine); 3396 } 3397 3398 static void spapr_machine_2_8_class_options(MachineClass *mc) 3399 { 3400 spapr_machine_2_9_class_options(mc); 3401 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 3402 mc->numa_mem_align_shift = 23; 3403 } 3404 3405 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 3406 3407 /* 3408 * pseries-2.7 3409 */ 3410 #define SPAPR_COMPAT_2_7 \ 3411 HW_COMPAT_2_7 \ 3412 { \ 3413 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3414 .property = "mem_win_size", \ 3415 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 3416 }, \ 3417 { \ 3418 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3419 .property = "mem64_win_size", \ 3420 .value = "0", \ 3421 }, \ 3422 { \ 3423 .driver = TYPE_POWERPC_CPU, \ 3424 .property = "pre-2.8-migration", \ 3425 .value = "on", \ 3426 }, \ 3427 { \ 3428 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3429 .property = "pre-2.8-migration", \ 3430 .value = "on", \ 3431 }, 3432 3433 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 3434 uint64_t *buid, hwaddr *pio, 3435 hwaddr *mmio32, hwaddr *mmio64, 3436 unsigned n_dma, uint32_t *liobns, Error **errp) 3437 { 3438 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 3439 const uint64_t base_buid = 0x800000020000000ULL; 3440 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 3441 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 3442 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 3443 const uint32_t max_index = 255; 3444 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 3445 3446 uint64_t ram_top = MACHINE(spapr)->ram_size; 3447 hwaddr phb0_base, phb_base; 3448 int i; 3449 3450 /* Do we have hotpluggable memory? */ 3451 if (MACHINE(spapr)->maxram_size > ram_top) { 3452 /* Can't just use maxram_size, because there may be an 3453 * alignment gap between normal and hotpluggable memory 3454 * regions */ 3455 ram_top = spapr->hotplug_memory.base + 3456 memory_region_size(&spapr->hotplug_memory.mr); 3457 } 3458 3459 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 3460 3461 if (index > max_index) { 3462 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 3463 max_index); 3464 return; 3465 } 3466 3467 *buid = base_buid + index; 3468 for (i = 0; i < n_dma; ++i) { 3469 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3470 } 3471 3472 phb_base = phb0_base + index * phb_spacing; 3473 *pio = phb_base + pio_offset; 3474 *mmio32 = phb_base + mmio_offset; 3475 /* 3476 * We don't set the 64-bit MMIO window, relying on the PHB's 3477 * fallback behaviour of automatically splitting a large "32-bit" 3478 * window into contiguous 32-bit and 64-bit windows 3479 */ 3480 } 3481 3482 static void spapr_machine_2_7_instance_options(MachineState *machine) 3483 { 3484 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 3485 3486 spapr_machine_2_8_instance_options(machine); 3487 spapr->use_hotplug_event_source = false; 3488 } 3489 3490 static void spapr_machine_2_7_class_options(MachineClass *mc) 3491 { 3492 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3493 3494 spapr_machine_2_8_class_options(mc); 3495 smc->tcg_default_cpu = "POWER7"; 3496 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 3497 smc->phb_placement = phb_placement_2_7; 3498 } 3499 3500 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 3501 3502 /* 3503 * pseries-2.6 3504 */ 3505 #define SPAPR_COMPAT_2_6 \ 3506 HW_COMPAT_2_6 \ 3507 { \ 3508 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3509 .property = "ddw",\ 3510 .value = stringify(off),\ 3511 }, 3512 3513 static void spapr_machine_2_6_instance_options(MachineState *machine) 3514 { 3515 spapr_machine_2_7_instance_options(machine); 3516 } 3517 3518 static void spapr_machine_2_6_class_options(MachineClass *mc) 3519 { 3520 spapr_machine_2_7_class_options(mc); 3521 mc->has_hotpluggable_cpus = false; 3522 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 3523 } 3524 3525 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 3526 3527 /* 3528 * pseries-2.5 3529 */ 3530 #define SPAPR_COMPAT_2_5 \ 3531 HW_COMPAT_2_5 \ 3532 { \ 3533 .driver = "spapr-vlan", \ 3534 .property = "use-rx-buffer-pools", \ 3535 .value = "off", \ 3536 }, 3537 3538 static void spapr_machine_2_5_instance_options(MachineState *machine) 3539 { 3540 spapr_machine_2_6_instance_options(machine); 3541 } 3542 3543 static void spapr_machine_2_5_class_options(MachineClass *mc) 3544 { 3545 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3546 3547 spapr_machine_2_6_class_options(mc); 3548 smc->use_ohci_by_default = true; 3549 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 3550 } 3551 3552 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 3553 3554 /* 3555 * pseries-2.4 3556 */ 3557 #define SPAPR_COMPAT_2_4 \ 3558 HW_COMPAT_2_4 3559 3560 static void spapr_machine_2_4_instance_options(MachineState *machine) 3561 { 3562 spapr_machine_2_5_instance_options(machine); 3563 } 3564 3565 static void spapr_machine_2_4_class_options(MachineClass *mc) 3566 { 3567 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3568 3569 spapr_machine_2_5_class_options(mc); 3570 smc->dr_lmb_enabled = false; 3571 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 3572 } 3573 3574 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 3575 3576 /* 3577 * pseries-2.3 3578 */ 3579 #define SPAPR_COMPAT_2_3 \ 3580 HW_COMPAT_2_3 \ 3581 {\ 3582 .driver = "spapr-pci-host-bridge",\ 3583 .property = "dynamic-reconfiguration",\ 3584 .value = "off",\ 3585 }, 3586 3587 static void spapr_machine_2_3_instance_options(MachineState *machine) 3588 { 3589 spapr_machine_2_4_instance_options(machine); 3590 savevm_skip_section_footers(); 3591 global_state_set_optional(); 3592 savevm_skip_configuration(); 3593 } 3594 3595 static void spapr_machine_2_3_class_options(MachineClass *mc) 3596 { 3597 spapr_machine_2_4_class_options(mc); 3598 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 3599 } 3600 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 3601 3602 /* 3603 * pseries-2.2 3604 */ 3605 3606 #define SPAPR_COMPAT_2_2 \ 3607 HW_COMPAT_2_2 \ 3608 {\ 3609 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3610 .property = "mem_win_size",\ 3611 .value = "0x20000000",\ 3612 }, 3613 3614 static void spapr_machine_2_2_instance_options(MachineState *machine) 3615 { 3616 spapr_machine_2_3_instance_options(machine); 3617 machine->suppress_vmdesc = true; 3618 } 3619 3620 static void spapr_machine_2_2_class_options(MachineClass *mc) 3621 { 3622 spapr_machine_2_3_class_options(mc); 3623 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 3624 } 3625 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 3626 3627 /* 3628 * pseries-2.1 3629 */ 3630 #define SPAPR_COMPAT_2_1 \ 3631 HW_COMPAT_2_1 3632 3633 static void spapr_machine_2_1_instance_options(MachineState *machine) 3634 { 3635 spapr_machine_2_2_instance_options(machine); 3636 } 3637 3638 static void spapr_machine_2_1_class_options(MachineClass *mc) 3639 { 3640 spapr_machine_2_2_class_options(mc); 3641 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 3642 } 3643 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 3644 3645 static void spapr_machine_register_types(void) 3646 { 3647 type_register_static(&spapr_machine_info); 3648 } 3649 3650 type_init(spapr_machine_register_types) 3651