1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu/datadir.h" 29 #include "qemu/memalign.h" 30 #include "qemu/guest-random.h" 31 #include "qapi/error.h" 32 #include "qapi/qapi-events-machine.h" 33 #include "qapi/qapi-events-qdev.h" 34 #include "qapi/visitor.h" 35 #include "sysemu/sysemu.h" 36 #include "sysemu/hostmem.h" 37 #include "sysemu/numa.h" 38 #include "sysemu/qtest.h" 39 #include "sysemu/reset.h" 40 #include "sysemu/runstate.h" 41 #include "qemu/log.h" 42 #include "hw/fw-path-provider.h" 43 #include "elf.h" 44 #include "net/net.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/cpus.h" 47 #include "sysemu/hw_accel.h" 48 #include "kvm_ppc.h" 49 #include "migration/misc.h" 50 #include "migration/qemu-file-types.h" 51 #include "migration/global_state.h" 52 #include "migration/register.h" 53 #include "migration/blocker.h" 54 #include "mmu-hash64.h" 55 #include "mmu-book3s-v3.h" 56 #include "cpu-models.h" 57 #include "hw/core/cpu.h" 58 59 #include "hw/ppc/ppc.h" 60 #include "hw/loader.h" 61 62 #include "hw/ppc/fdt.h" 63 #include "hw/ppc/spapr.h" 64 #include "hw/ppc/spapr_vio.h" 65 #include "hw/qdev-properties.h" 66 #include "hw/pci-host/spapr.h" 67 #include "hw/pci/msi.h" 68 69 #include "hw/pci/pci.h" 70 #include "hw/scsi/scsi.h" 71 #include "hw/virtio/virtio-scsi.h" 72 #include "hw/virtio/vhost-scsi-common.h" 73 74 #include "exec/ram_addr.h" 75 #include "hw/usb.h" 76 #include "qemu/config-file.h" 77 #include "qemu/error-report.h" 78 #include "trace.h" 79 #include "hw/nmi.h" 80 #include "hw/intc/intc.h" 81 82 #include "hw/ppc/spapr_cpu_core.h" 83 #include "hw/mem/memory-device.h" 84 #include "hw/ppc/spapr_tpm_proxy.h" 85 #include "hw/ppc/spapr_nvdimm.h" 86 #include "hw/ppc/spapr_numa.h" 87 #include "hw/ppc/pef.h" 88 89 #include "monitor/monitor.h" 90 91 #include <libfdt.h> 92 93 /* SLOF memory layout: 94 * 95 * SLOF raw image loaded at 0, copies its romfs right below the flat 96 * device-tree, then position SLOF itself 31M below that 97 * 98 * So we set FW_OVERHEAD to 40MB which should account for all of that 99 * and more 100 * 101 * We load our kernel at 4M, leaving space for SLOF initial image 102 */ 103 #define FDT_MAX_ADDR 0x80000000 /* FDT must stay below that */ 104 #define FW_MAX_SIZE 0x400000 105 #define FW_FILE_NAME "slof.bin" 106 #define FW_FILE_NAME_VOF "vof.bin" 107 #define FW_OVERHEAD 0x2800000 108 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 109 110 #define MIN_RMA_SLOF (128 * MiB) 111 112 #define PHANDLE_INTC 0x00001111 113 114 /* These two functions implement the VCPU id numbering: one to compute them 115 * all and one to identify thread 0 of a VCORE. Any change to the first one 116 * is likely to have an impact on the second one, so let's keep them close. 117 */ 118 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 119 { 120 MachineState *ms = MACHINE(spapr); 121 unsigned int smp_threads = ms->smp.threads; 122 123 assert(spapr->vsmt); 124 return 125 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 126 } 127 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 128 PowerPCCPU *cpu) 129 { 130 assert(spapr->vsmt); 131 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 132 } 133 134 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 135 { 136 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 137 * and newer QEMUs don't even have them. In both cases, we don't want 138 * to send anything on the wire. 139 */ 140 return false; 141 } 142 143 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 144 .name = "icp/server", 145 .version_id = 1, 146 .minimum_version_id = 1, 147 .needed = pre_2_10_vmstate_dummy_icp_needed, 148 .fields = (VMStateField[]) { 149 VMSTATE_UNUSED(4), /* uint32_t xirr */ 150 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 151 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 152 VMSTATE_END_OF_LIST() 153 }, 154 }; 155 156 static void pre_2_10_vmstate_register_dummy_icp(int i) 157 { 158 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 159 (void *)(uintptr_t) i); 160 } 161 162 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 163 { 164 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 165 (void *)(uintptr_t) i); 166 } 167 168 int spapr_max_server_number(SpaprMachineState *spapr) 169 { 170 MachineState *ms = MACHINE(spapr); 171 172 assert(spapr->vsmt); 173 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 174 } 175 176 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 177 int smt_threads) 178 { 179 int i, ret = 0; 180 uint32_t servers_prop[smt_threads]; 181 uint32_t gservers_prop[smt_threads * 2]; 182 int index = spapr_get_vcpu_id(cpu); 183 184 if (cpu->compat_pvr) { 185 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 186 if (ret < 0) { 187 return ret; 188 } 189 } 190 191 /* Build interrupt servers and gservers properties */ 192 for (i = 0; i < smt_threads; i++) { 193 servers_prop[i] = cpu_to_be32(index + i); 194 /* Hack, direct the group queues back to cpu 0 */ 195 gservers_prop[i*2] = cpu_to_be32(index + i); 196 gservers_prop[i*2 + 1] = 0; 197 } 198 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 199 servers_prop, sizeof(servers_prop)); 200 if (ret < 0) { 201 return ret; 202 } 203 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 204 gservers_prop, sizeof(gservers_prop)); 205 206 return ret; 207 } 208 209 static void spapr_dt_pa_features(SpaprMachineState *spapr, 210 PowerPCCPU *cpu, 211 void *fdt, int offset) 212 { 213 uint8_t pa_features_206[] = { 6, 0, 214 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 215 uint8_t pa_features_207[] = { 24, 0, 216 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 217 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 218 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 219 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 220 uint8_t pa_features_300[] = { 66, 0, 221 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 222 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 223 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 224 /* 6: DS207 */ 225 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 226 /* 16: Vector */ 227 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 228 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 229 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 230 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 231 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 232 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 233 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 234 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 235 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 236 /* 42: PM, 44: PC RA, 46: SC vec'd */ 237 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 238 /* 48: SIMD, 50: QP BFP, 52: String */ 239 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 240 /* 54: DecFP, 56: DecI, 58: SHA */ 241 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 242 /* 60: NM atomic, 62: RNG */ 243 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 244 }; 245 uint8_t *pa_features = NULL; 246 size_t pa_size; 247 248 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 249 pa_features = pa_features_206; 250 pa_size = sizeof(pa_features_206); 251 } 252 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 253 pa_features = pa_features_207; 254 pa_size = sizeof(pa_features_207); 255 } 256 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 257 pa_features = pa_features_300; 258 pa_size = sizeof(pa_features_300); 259 } 260 if (!pa_features) { 261 return; 262 } 263 264 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 265 /* 266 * Note: we keep CI large pages off by default because a 64K capable 267 * guest provisioned with large pages might otherwise try to map a qemu 268 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 269 * even if that qemu runs on a 4k host. 270 * We dd this bit back here if we are confident this is not an issue 271 */ 272 pa_features[3] |= 0x20; 273 } 274 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 275 pa_features[24] |= 0x80; /* Transactional memory support */ 276 } 277 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 278 /* Workaround for broken kernels that attempt (guest) radix 279 * mode when they can't handle it, if they see the radix bit set 280 * in pa-features. So hide it from them. */ 281 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 282 } 283 284 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 285 } 286 287 static hwaddr spapr_node0_size(MachineState *machine) 288 { 289 if (machine->numa_state->num_nodes) { 290 int i; 291 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 292 if (machine->numa_state->nodes[i].node_mem) { 293 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 294 machine->ram_size); 295 } 296 } 297 } 298 return machine->ram_size; 299 } 300 301 static void add_str(GString *s, const gchar *s1) 302 { 303 g_string_append_len(s, s1, strlen(s1) + 1); 304 } 305 306 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 307 hwaddr start, hwaddr size) 308 { 309 char mem_name[32]; 310 uint64_t mem_reg_property[2]; 311 int off; 312 313 mem_reg_property[0] = cpu_to_be64(start); 314 mem_reg_property[1] = cpu_to_be64(size); 315 316 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 317 off = fdt_add_subnode(fdt, 0, mem_name); 318 _FDT(off); 319 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 320 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 321 sizeof(mem_reg_property)))); 322 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 323 return off; 324 } 325 326 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 327 { 328 MemoryDeviceInfoList *info; 329 330 for (info = list; info; info = info->next) { 331 MemoryDeviceInfo *value = info->value; 332 333 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 334 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 335 336 if (addr >= pcdimm_info->addr && 337 addr < (pcdimm_info->addr + pcdimm_info->size)) { 338 return pcdimm_info->node; 339 } 340 } 341 } 342 343 return -1; 344 } 345 346 struct sPAPRDrconfCellV2 { 347 uint32_t seq_lmbs; 348 uint64_t base_addr; 349 uint32_t drc_index; 350 uint32_t aa_index; 351 uint32_t flags; 352 } QEMU_PACKED; 353 354 typedef struct DrconfCellQueue { 355 struct sPAPRDrconfCellV2 cell; 356 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 357 } DrconfCellQueue; 358 359 static DrconfCellQueue * 360 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 361 uint32_t drc_index, uint32_t aa_index, 362 uint32_t flags) 363 { 364 DrconfCellQueue *elem; 365 366 elem = g_malloc0(sizeof(*elem)); 367 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 368 elem->cell.base_addr = cpu_to_be64(base_addr); 369 elem->cell.drc_index = cpu_to_be32(drc_index); 370 elem->cell.aa_index = cpu_to_be32(aa_index); 371 elem->cell.flags = cpu_to_be32(flags); 372 373 return elem; 374 } 375 376 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 377 int offset, MemoryDeviceInfoList *dimms) 378 { 379 MachineState *machine = MACHINE(spapr); 380 uint8_t *int_buf, *cur_index; 381 int ret; 382 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 383 uint64_t addr, cur_addr, size; 384 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 385 uint64_t mem_end = machine->device_memory->base + 386 memory_region_size(&machine->device_memory->mr); 387 uint32_t node, buf_len, nr_entries = 0; 388 SpaprDrc *drc; 389 DrconfCellQueue *elem, *next; 390 MemoryDeviceInfoList *info; 391 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 392 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 393 394 /* Entry to cover RAM and the gap area */ 395 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 396 SPAPR_LMB_FLAGS_RESERVED | 397 SPAPR_LMB_FLAGS_DRC_INVALID); 398 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 399 nr_entries++; 400 401 cur_addr = machine->device_memory->base; 402 for (info = dimms; info; info = info->next) { 403 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 404 405 addr = di->addr; 406 size = di->size; 407 node = di->node; 408 409 /* 410 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 411 * area is marked hotpluggable in the next iteration for the bigger 412 * chunk including the NVDIMM occupied area. 413 */ 414 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 415 continue; 416 417 /* Entry for hot-pluggable area */ 418 if (cur_addr < addr) { 419 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 420 g_assert(drc); 421 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 422 cur_addr, spapr_drc_index(drc), -1, 0); 423 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 424 nr_entries++; 425 } 426 427 /* Entry for DIMM */ 428 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 429 g_assert(drc); 430 elem = spapr_get_drconf_cell(size / lmb_size, addr, 431 spapr_drc_index(drc), node, 432 (SPAPR_LMB_FLAGS_ASSIGNED | 433 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 434 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 435 nr_entries++; 436 cur_addr = addr + size; 437 } 438 439 /* Entry for remaining hotpluggable area */ 440 if (cur_addr < mem_end) { 441 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 442 g_assert(drc); 443 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 444 cur_addr, spapr_drc_index(drc), -1, 0); 445 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 446 nr_entries++; 447 } 448 449 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 450 int_buf = cur_index = g_malloc0(buf_len); 451 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 452 cur_index += sizeof(nr_entries); 453 454 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 455 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 456 cur_index += sizeof(elem->cell); 457 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 458 g_free(elem); 459 } 460 461 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 462 g_free(int_buf); 463 if (ret < 0) { 464 return -1; 465 } 466 return 0; 467 } 468 469 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 470 int offset, MemoryDeviceInfoList *dimms) 471 { 472 MachineState *machine = MACHINE(spapr); 473 int i, ret; 474 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 475 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 476 uint32_t nr_lmbs = (machine->device_memory->base + 477 memory_region_size(&machine->device_memory->mr)) / 478 lmb_size; 479 uint32_t *int_buf, *cur_index, buf_len; 480 481 /* 482 * Allocate enough buffer size to fit in ibm,dynamic-memory 483 */ 484 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 485 cur_index = int_buf = g_malloc0(buf_len); 486 int_buf[0] = cpu_to_be32(nr_lmbs); 487 cur_index++; 488 for (i = 0; i < nr_lmbs; i++) { 489 uint64_t addr = i * lmb_size; 490 uint32_t *dynamic_memory = cur_index; 491 492 if (i >= device_lmb_start) { 493 SpaprDrc *drc; 494 495 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 496 g_assert(drc); 497 498 dynamic_memory[0] = cpu_to_be32(addr >> 32); 499 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 500 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 501 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 502 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 503 if (memory_region_present(get_system_memory(), addr)) { 504 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 505 } else { 506 dynamic_memory[5] = cpu_to_be32(0); 507 } 508 } else { 509 /* 510 * LMB information for RMA, boot time RAM and gap b/n RAM and 511 * device memory region -- all these are marked as reserved 512 * and as having no valid DRC. 513 */ 514 dynamic_memory[0] = cpu_to_be32(addr >> 32); 515 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 516 dynamic_memory[2] = cpu_to_be32(0); 517 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 518 dynamic_memory[4] = cpu_to_be32(-1); 519 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 520 SPAPR_LMB_FLAGS_DRC_INVALID); 521 } 522 523 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 524 } 525 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 526 g_free(int_buf); 527 if (ret < 0) { 528 return -1; 529 } 530 return 0; 531 } 532 533 /* 534 * Adds ibm,dynamic-reconfiguration-memory node. 535 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 536 * of this device tree node. 537 */ 538 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 539 void *fdt) 540 { 541 MachineState *machine = MACHINE(spapr); 542 int ret, offset; 543 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 544 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 545 cpu_to_be32(lmb_size & 0xffffffff)}; 546 MemoryDeviceInfoList *dimms = NULL; 547 548 /* 549 * Don't create the node if there is no device memory 550 */ 551 if (machine->ram_size == machine->maxram_size) { 552 return 0; 553 } 554 555 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 556 557 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 558 sizeof(prop_lmb_size)); 559 if (ret < 0) { 560 return ret; 561 } 562 563 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 564 if (ret < 0) { 565 return ret; 566 } 567 568 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 569 if (ret < 0) { 570 return ret; 571 } 572 573 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 574 dimms = qmp_memory_device_list(); 575 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 576 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 577 } else { 578 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 579 } 580 qapi_free_MemoryDeviceInfoList(dimms); 581 582 if (ret < 0) { 583 return ret; 584 } 585 586 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 587 588 return ret; 589 } 590 591 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 592 { 593 MachineState *machine = MACHINE(spapr); 594 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 595 hwaddr mem_start, node_size; 596 int i, nb_nodes = machine->numa_state->num_nodes; 597 NodeInfo *nodes = machine->numa_state->nodes; 598 599 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 600 if (!nodes[i].node_mem) { 601 continue; 602 } 603 if (mem_start >= machine->ram_size) { 604 node_size = 0; 605 } else { 606 node_size = nodes[i].node_mem; 607 if (node_size > machine->ram_size - mem_start) { 608 node_size = machine->ram_size - mem_start; 609 } 610 } 611 if (!mem_start) { 612 /* spapr_machine_init() checks for rma_size <= node0_size 613 * already */ 614 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 615 mem_start += spapr->rma_size; 616 node_size -= spapr->rma_size; 617 } 618 for ( ; node_size; ) { 619 hwaddr sizetmp = pow2floor(node_size); 620 621 /* mem_start != 0 here */ 622 if (ctzl(mem_start) < ctzl(sizetmp)) { 623 sizetmp = 1ULL << ctzl(mem_start); 624 } 625 626 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 627 node_size -= sizetmp; 628 mem_start += sizetmp; 629 } 630 } 631 632 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 633 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 634 int ret; 635 636 g_assert(smc->dr_lmb_enabled); 637 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 638 if (ret) { 639 return ret; 640 } 641 } 642 643 return 0; 644 } 645 646 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 647 SpaprMachineState *spapr) 648 { 649 MachineState *ms = MACHINE(spapr); 650 PowerPCCPU *cpu = POWERPC_CPU(cs); 651 CPUPPCState *env = &cpu->env; 652 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 653 int index = spapr_get_vcpu_id(cpu); 654 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 655 0xffffffff, 0xffffffff}; 656 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 657 : SPAPR_TIMEBASE_FREQ; 658 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 659 uint32_t page_sizes_prop[64]; 660 size_t page_sizes_prop_size; 661 unsigned int smp_threads = ms->smp.threads; 662 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 663 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 664 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 665 SpaprDrc *drc; 666 int drc_index; 667 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 668 int i; 669 670 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 671 if (drc) { 672 drc_index = spapr_drc_index(drc); 673 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 674 } 675 676 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 677 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 678 679 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 680 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 681 env->dcache_line_size))); 682 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 683 env->dcache_line_size))); 684 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 685 env->icache_line_size))); 686 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 687 env->icache_line_size))); 688 689 if (pcc->l1_dcache_size) { 690 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 691 pcc->l1_dcache_size))); 692 } else { 693 warn_report("Unknown L1 dcache size for cpu"); 694 } 695 if (pcc->l1_icache_size) { 696 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 697 pcc->l1_icache_size))); 698 } else { 699 warn_report("Unknown L1 icache size for cpu"); 700 } 701 702 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 703 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 704 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 705 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 706 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 707 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 708 709 if (ppc_has_spr(cpu, SPR_PURR)) { 710 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 711 } 712 if (ppc_has_spr(cpu, SPR_PURR)) { 713 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 714 } 715 716 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 717 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 718 segs, sizeof(segs)))); 719 } 720 721 /* Advertise VSX (vector extensions) if available 722 * 1 == VMX / Altivec available 723 * 2 == VSX available 724 * 725 * Only CPUs for which we create core types in spapr_cpu_core.c 726 * are possible, and all of those have VMX */ 727 if (env->insns_flags & PPC_ALTIVEC) { 728 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 729 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 730 } else { 731 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 732 } 733 } 734 735 /* Advertise DFP (Decimal Floating Point) if available 736 * 0 / no property == no DFP 737 * 1 == DFP available */ 738 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 739 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 740 } 741 742 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 743 sizeof(page_sizes_prop)); 744 if (page_sizes_prop_size) { 745 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 746 page_sizes_prop, page_sizes_prop_size))); 747 } 748 749 spapr_dt_pa_features(spapr, cpu, fdt, offset); 750 751 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 752 cs->cpu_index / vcpus_per_socket))); 753 754 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 755 pft_size_prop, sizeof(pft_size_prop)))); 756 757 if (ms->numa_state->num_nodes > 1) { 758 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 759 } 760 761 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 762 763 if (pcc->radix_page_info) { 764 for (i = 0; i < pcc->radix_page_info->count; i++) { 765 radix_AP_encodings[i] = 766 cpu_to_be32(pcc->radix_page_info->entries[i]); 767 } 768 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 769 radix_AP_encodings, 770 pcc->radix_page_info->count * 771 sizeof(radix_AP_encodings[0])))); 772 } 773 774 /* 775 * We set this property to let the guest know that it can use the large 776 * decrementer and its width in bits. 777 */ 778 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 779 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 780 pcc->lrg_decr_bits))); 781 } 782 783 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 784 { 785 CPUState **rev; 786 CPUState *cs; 787 int n_cpus; 788 int cpus_offset; 789 int i; 790 791 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 792 _FDT(cpus_offset); 793 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 794 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 795 796 /* 797 * We walk the CPUs in reverse order to ensure that CPU DT nodes 798 * created by fdt_add_subnode() end up in the right order in FDT 799 * for the guest kernel the enumerate the CPUs correctly. 800 * 801 * The CPU list cannot be traversed in reverse order, so we need 802 * to do extra work. 803 */ 804 n_cpus = 0; 805 rev = NULL; 806 CPU_FOREACH(cs) { 807 rev = g_renew(CPUState *, rev, n_cpus + 1); 808 rev[n_cpus++] = cs; 809 } 810 811 for (i = n_cpus - 1; i >= 0; i--) { 812 CPUState *cs = rev[i]; 813 PowerPCCPU *cpu = POWERPC_CPU(cs); 814 int index = spapr_get_vcpu_id(cpu); 815 DeviceClass *dc = DEVICE_GET_CLASS(cs); 816 g_autofree char *nodename = NULL; 817 int offset; 818 819 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 820 continue; 821 } 822 823 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 824 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 825 _FDT(offset); 826 spapr_dt_cpu(cs, fdt, offset, spapr); 827 } 828 829 g_free(rev); 830 } 831 832 static int spapr_dt_rng(void *fdt) 833 { 834 int node; 835 int ret; 836 837 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 838 if (node <= 0) { 839 return -1; 840 } 841 ret = fdt_setprop_string(fdt, node, "device_type", 842 "ibm,platform-facilities"); 843 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 844 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 845 846 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 847 if (node <= 0) { 848 return -1; 849 } 850 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 851 852 return ret ? -1 : 0; 853 } 854 855 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 856 { 857 MachineState *ms = MACHINE(spapr); 858 int rtas; 859 GString *hypertas = g_string_sized_new(256); 860 GString *qemu_hypertas = g_string_sized_new(256); 861 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 862 memory_region_size(&MACHINE(spapr)->device_memory->mr); 863 uint32_t lrdr_capacity[] = { 864 cpu_to_be32(max_device_addr >> 32), 865 cpu_to_be32(max_device_addr & 0xffffffff), 866 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 867 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 868 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 869 }; 870 871 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 872 873 /* hypertas */ 874 add_str(hypertas, "hcall-pft"); 875 add_str(hypertas, "hcall-term"); 876 add_str(hypertas, "hcall-dabr"); 877 add_str(hypertas, "hcall-interrupt"); 878 add_str(hypertas, "hcall-tce"); 879 add_str(hypertas, "hcall-vio"); 880 add_str(hypertas, "hcall-splpar"); 881 add_str(hypertas, "hcall-join"); 882 add_str(hypertas, "hcall-bulk"); 883 add_str(hypertas, "hcall-set-mode"); 884 add_str(hypertas, "hcall-sprg0"); 885 add_str(hypertas, "hcall-copy"); 886 add_str(hypertas, "hcall-debug"); 887 add_str(hypertas, "hcall-vphn"); 888 if (spapr_get_cap(spapr, SPAPR_CAP_RPT_INVALIDATE) == SPAPR_CAP_ON) { 889 add_str(hypertas, "hcall-rpt-invalidate"); 890 } 891 892 add_str(qemu_hypertas, "hcall-memop1"); 893 894 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 895 add_str(hypertas, "hcall-multi-tce"); 896 } 897 898 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 899 add_str(hypertas, "hcall-hpt-resize"); 900 } 901 902 add_str(hypertas, "hcall-watchdog"); 903 904 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 905 hypertas->str, hypertas->len)); 906 g_string_free(hypertas, TRUE); 907 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 908 qemu_hypertas->str, qemu_hypertas->len)); 909 g_string_free(qemu_hypertas, TRUE); 910 911 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 912 913 /* 914 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 915 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 916 * 917 * The system reset requirements are driven by existing Linux and PowerVM 918 * implementation which (contrary to PAPR) saves r3 in the error log 919 * structure like machine check, so Linux expects to find the saved r3 920 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 921 * does not look at the error value). 922 * 923 * System reset interrupts are not subject to interlock like machine 924 * check, so this memory area could be corrupted if the sreset is 925 * interrupted by a machine check (or vice versa) if it was shared. To 926 * prevent this, system reset uses per-CPU areas for the sreset save 927 * area. A system reset that interrupts a system reset handler could 928 * still overwrite this area, but Linux doesn't try to recover in that 929 * case anyway. 930 * 931 * The extra 8 bytes is required because Linux's FWNMI error log check 932 * is off-by-one. 933 * 934 * RTAS_MIN_SIZE is required for the RTAS blob itself. 935 */ 936 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_MIN_SIZE + 937 RTAS_ERROR_LOG_MAX + 938 ms->smp.max_cpus * sizeof(uint64_t) * 2 + 939 sizeof(uint64_t))); 940 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 941 RTAS_ERROR_LOG_MAX)); 942 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 943 RTAS_EVENT_SCAN_RATE)); 944 945 g_assert(msi_nonbroken); 946 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 947 948 /* 949 * According to PAPR, rtas ibm,os-term does not guarantee a return 950 * back to the guest cpu. 951 * 952 * While an additional ibm,extended-os-term property indicates 953 * that rtas call return will always occur. Set this property. 954 */ 955 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 956 957 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 958 lrdr_capacity, sizeof(lrdr_capacity))); 959 960 spapr_dt_rtas_tokens(fdt, rtas); 961 } 962 963 /* 964 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 965 * and the XIVE features that the guest may request and thus the valid 966 * values for bytes 23..26 of option vector 5: 967 */ 968 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 969 int chosen) 970 { 971 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 972 973 char val[2 * 4] = { 974 23, 0x00, /* XICS / XIVE mode */ 975 24, 0x00, /* Hash/Radix, filled in below. */ 976 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 977 26, 0x40, /* Radix options: GTSE == yes. */ 978 }; 979 980 if (spapr->irq->xics && spapr->irq->xive) { 981 val[1] = SPAPR_OV5_XIVE_BOTH; 982 } else if (spapr->irq->xive) { 983 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 984 } else { 985 assert(spapr->irq->xics); 986 val[1] = SPAPR_OV5_XIVE_LEGACY; 987 } 988 989 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 990 first_ppc_cpu->compat_pvr)) { 991 /* 992 * If we're in a pre POWER9 compat mode then the guest should 993 * do hash and use the legacy interrupt mode 994 */ 995 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 996 val[3] = 0x00; /* Hash */ 997 spapr_check_mmu_mode(false); 998 } else if (kvm_enabled()) { 999 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1000 val[3] = 0x80; /* OV5_MMU_BOTH */ 1001 } else if (kvmppc_has_cap_mmu_radix()) { 1002 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1003 } else { 1004 val[3] = 0x00; /* Hash */ 1005 } 1006 } else { 1007 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1008 val[3] = 0xC0; 1009 } 1010 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1011 val, sizeof(val))); 1012 } 1013 1014 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1015 { 1016 MachineState *machine = MACHINE(spapr); 1017 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1018 uint8_t rng_seed[32]; 1019 int chosen; 1020 1021 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1022 1023 if (reset) { 1024 const char *boot_device = spapr->boot_device; 1025 g_autofree char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1026 size_t cb = 0; 1027 g_autofree char *bootlist = get_boot_devices_list(&cb); 1028 1029 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1030 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1031 machine->kernel_cmdline)); 1032 } 1033 1034 if (spapr->initrd_size) { 1035 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1036 spapr->initrd_base)); 1037 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1038 spapr->initrd_base + spapr->initrd_size)); 1039 } 1040 1041 if (spapr->kernel_size) { 1042 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1043 cpu_to_be64(spapr->kernel_size) }; 1044 1045 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1046 &kprop, sizeof(kprop))); 1047 if (spapr->kernel_le) { 1048 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1049 } 1050 } 1051 if (machine->boot_config.has_menu && machine->boot_config.menu) { 1052 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", true))); 1053 } 1054 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1055 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1056 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1057 1058 if (cb && bootlist) { 1059 int i; 1060 1061 for (i = 0; i < cb; i++) { 1062 if (bootlist[i] == '\n') { 1063 bootlist[i] = ' '; 1064 } 1065 } 1066 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1067 } 1068 1069 if (boot_device && strlen(boot_device)) { 1070 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1071 } 1072 1073 if (spapr->want_stdout_path && stdout_path) { 1074 /* 1075 * "linux,stdout-path" and "stdout" properties are 1076 * deprecated by linux kernel. New platforms should only 1077 * use the "stdout-path" property. Set the new property 1078 * and continue using older property to remain compatible 1079 * with the existing firmware. 1080 */ 1081 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1082 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1083 } 1084 1085 /* 1086 * We can deal with BAR reallocation just fine, advertise it 1087 * to the guest 1088 */ 1089 if (smc->linux_pci_probe) { 1090 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1091 } 1092 1093 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1094 } 1095 1096 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 1097 _FDT(fdt_setprop(fdt, chosen, "rng-seed", rng_seed, sizeof(rng_seed))); 1098 1099 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1100 } 1101 1102 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1103 { 1104 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1105 * KVM to work under pHyp with some guest co-operation */ 1106 int hypervisor; 1107 uint8_t hypercall[16]; 1108 1109 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1110 /* indicate KVM hypercall interface */ 1111 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1112 if (kvmppc_has_cap_fixup_hcalls()) { 1113 /* 1114 * Older KVM versions with older guest kernels were broken 1115 * with the magic page, don't allow the guest to map it. 1116 */ 1117 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1118 sizeof(hypercall))) { 1119 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1120 hypercall, sizeof(hypercall))); 1121 } 1122 } 1123 } 1124 1125 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1126 { 1127 MachineState *machine = MACHINE(spapr); 1128 MachineClass *mc = MACHINE_GET_CLASS(machine); 1129 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1130 uint32_t root_drc_type_mask = 0; 1131 int ret; 1132 void *fdt; 1133 SpaprPhbState *phb; 1134 char *buf; 1135 1136 fdt = g_malloc0(space); 1137 _FDT((fdt_create_empty_tree(fdt, space))); 1138 1139 /* Root node */ 1140 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1141 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1142 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1143 1144 /* Guest UUID & Name*/ 1145 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1146 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1147 if (qemu_uuid_set) { 1148 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1149 } 1150 g_free(buf); 1151 1152 if (qemu_get_vm_name()) { 1153 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1154 qemu_get_vm_name())); 1155 } 1156 1157 /* Host Model & Serial Number */ 1158 if (spapr->host_model) { 1159 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1160 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1161 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1162 g_free(buf); 1163 } 1164 1165 if (spapr->host_serial) { 1166 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1167 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1168 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1169 g_free(buf); 1170 } 1171 1172 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1173 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1174 1175 /* /interrupt controller */ 1176 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1177 1178 ret = spapr_dt_memory(spapr, fdt); 1179 if (ret < 0) { 1180 error_report("couldn't setup memory nodes in fdt"); 1181 exit(1); 1182 } 1183 1184 /* /vdevice */ 1185 spapr_dt_vdevice(spapr->vio_bus, fdt); 1186 1187 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1188 ret = spapr_dt_rng(fdt); 1189 if (ret < 0) { 1190 error_report("could not set up rng device in the fdt"); 1191 exit(1); 1192 } 1193 } 1194 1195 QLIST_FOREACH(phb, &spapr->phbs, list) { 1196 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1197 if (ret < 0) { 1198 error_report("couldn't setup PCI devices in fdt"); 1199 exit(1); 1200 } 1201 } 1202 1203 spapr_dt_cpus(fdt, spapr); 1204 1205 /* ibm,drc-indexes and friends */ 1206 if (smc->dr_lmb_enabled) { 1207 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; 1208 } 1209 if (smc->dr_phb_enabled) { 1210 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; 1211 } 1212 if (mc->nvdimm_supported) { 1213 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM; 1214 } 1215 if (root_drc_type_mask) { 1216 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask)); 1217 } 1218 1219 if (mc->has_hotpluggable_cpus) { 1220 int offset = fdt_path_offset(fdt, "/cpus"); 1221 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1222 if (ret < 0) { 1223 error_report("Couldn't set up CPU DR device tree properties"); 1224 exit(1); 1225 } 1226 } 1227 1228 /* /event-sources */ 1229 spapr_dt_events(spapr, fdt); 1230 1231 /* /rtas */ 1232 spapr_dt_rtas(spapr, fdt); 1233 1234 /* /chosen */ 1235 spapr_dt_chosen(spapr, fdt, reset); 1236 1237 /* /hypervisor */ 1238 if (kvm_enabled()) { 1239 spapr_dt_hypervisor(spapr, fdt); 1240 } 1241 1242 /* Build memory reserve map */ 1243 if (reset) { 1244 if (spapr->kernel_size) { 1245 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1246 spapr->kernel_size))); 1247 } 1248 if (spapr->initrd_size) { 1249 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1250 spapr->initrd_size))); 1251 } 1252 } 1253 1254 /* NVDIMM devices */ 1255 if (mc->nvdimm_supported) { 1256 spapr_dt_persistent_memory(spapr, fdt); 1257 } 1258 1259 return fdt; 1260 } 1261 1262 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1263 { 1264 SpaprMachineState *spapr = opaque; 1265 1266 return (addr & 0x0fffffff) + spapr->kernel_addr; 1267 } 1268 1269 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1270 PowerPCCPU *cpu) 1271 { 1272 CPUPPCState *env = &cpu->env; 1273 1274 /* The TCG path should also be holding the BQL at this point */ 1275 g_assert(qemu_mutex_iothread_locked()); 1276 1277 g_assert(!vhyp_cpu_in_nested(cpu)); 1278 1279 if (FIELD_EX64(env->msr, MSR, PR)) { 1280 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1281 env->gpr[3] = H_PRIVILEGE; 1282 } else { 1283 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1284 } 1285 } 1286 1287 struct LPCRSyncState { 1288 target_ulong value; 1289 target_ulong mask; 1290 }; 1291 1292 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1293 { 1294 struct LPCRSyncState *s = arg.host_ptr; 1295 PowerPCCPU *cpu = POWERPC_CPU(cs); 1296 CPUPPCState *env = &cpu->env; 1297 target_ulong lpcr; 1298 1299 cpu_synchronize_state(cs); 1300 lpcr = env->spr[SPR_LPCR]; 1301 lpcr &= ~s->mask; 1302 lpcr |= s->value; 1303 ppc_store_lpcr(cpu, lpcr); 1304 } 1305 1306 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1307 { 1308 CPUState *cs; 1309 struct LPCRSyncState s = { 1310 .value = value, 1311 .mask = mask 1312 }; 1313 CPU_FOREACH(cs) { 1314 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1315 } 1316 } 1317 1318 static bool spapr_get_pate(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu, 1319 target_ulong lpid, ppc_v3_pate_t *entry) 1320 { 1321 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1322 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 1323 1324 if (!spapr_cpu->in_nested) { 1325 assert(lpid == 0); 1326 1327 /* Copy PATE1:GR into PATE0:HR */ 1328 entry->dw0 = spapr->patb_entry & PATE0_HR; 1329 entry->dw1 = spapr->patb_entry; 1330 1331 } else { 1332 uint64_t patb, pats; 1333 1334 assert(lpid != 0); 1335 1336 patb = spapr->nested_ptcr & PTCR_PATB; 1337 pats = spapr->nested_ptcr & PTCR_PATS; 1338 1339 /* Check if partition table is properly aligned */ 1340 if (patb & MAKE_64BIT_MASK(0, pats + 12)) { 1341 return false; 1342 } 1343 1344 /* Calculate number of entries */ 1345 pats = 1ull << (pats + 12 - 4); 1346 if (pats <= lpid) { 1347 return false; 1348 } 1349 1350 /* Grab entry */ 1351 patb += 16 * lpid; 1352 entry->dw0 = ldq_phys(CPU(cpu)->as, patb); 1353 entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8); 1354 } 1355 1356 return true; 1357 } 1358 1359 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1360 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1361 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1362 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1363 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1364 1365 /* 1366 * Get the fd to access the kernel htab, re-opening it if necessary 1367 */ 1368 static int get_htab_fd(SpaprMachineState *spapr) 1369 { 1370 Error *local_err = NULL; 1371 1372 if (spapr->htab_fd >= 0) { 1373 return spapr->htab_fd; 1374 } 1375 1376 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1377 if (spapr->htab_fd < 0) { 1378 error_report_err(local_err); 1379 } 1380 1381 return spapr->htab_fd; 1382 } 1383 1384 void close_htab_fd(SpaprMachineState *spapr) 1385 { 1386 if (spapr->htab_fd >= 0) { 1387 close(spapr->htab_fd); 1388 } 1389 spapr->htab_fd = -1; 1390 } 1391 1392 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1393 { 1394 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1395 1396 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1397 } 1398 1399 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1400 { 1401 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1402 1403 assert(kvm_enabled()); 1404 1405 if (!spapr->htab) { 1406 return 0; 1407 } 1408 1409 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1410 } 1411 1412 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1413 hwaddr ptex, int n) 1414 { 1415 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1416 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1417 1418 if (!spapr->htab) { 1419 /* 1420 * HTAB is controlled by KVM. Fetch into temporary buffer 1421 */ 1422 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1423 kvmppc_read_hptes(hptes, ptex, n); 1424 return hptes; 1425 } 1426 1427 /* 1428 * HTAB is controlled by QEMU. Just point to the internally 1429 * accessible PTEG. 1430 */ 1431 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1432 } 1433 1434 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1435 const ppc_hash_pte64_t *hptes, 1436 hwaddr ptex, int n) 1437 { 1438 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1439 1440 if (!spapr->htab) { 1441 g_free((void *)hptes); 1442 } 1443 1444 /* Nothing to do for qemu managed HPT */ 1445 } 1446 1447 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1448 uint64_t pte0, uint64_t pte1) 1449 { 1450 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1451 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1452 1453 if (!spapr->htab) { 1454 kvmppc_write_hpte(ptex, pte0, pte1); 1455 } else { 1456 if (pte0 & HPTE64_V_VALID) { 1457 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1458 /* 1459 * When setting valid, we write PTE1 first. This ensures 1460 * proper synchronization with the reading code in 1461 * ppc_hash64_pteg_search() 1462 */ 1463 smp_wmb(); 1464 stq_p(spapr->htab + offset, pte0); 1465 } else { 1466 stq_p(spapr->htab + offset, pte0); 1467 /* 1468 * When clearing it we set PTE0 first. This ensures proper 1469 * synchronization with the reading code in 1470 * ppc_hash64_pteg_search() 1471 */ 1472 smp_wmb(); 1473 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1474 } 1475 } 1476 } 1477 1478 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1479 uint64_t pte1) 1480 { 1481 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_C; 1482 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1483 1484 if (!spapr->htab) { 1485 /* There should always be a hash table when this is called */ 1486 error_report("spapr_hpte_set_c called with no hash table !"); 1487 return; 1488 } 1489 1490 /* The HW performs a non-atomic byte update */ 1491 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1492 } 1493 1494 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1495 uint64_t pte1) 1496 { 1497 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_R; 1498 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1499 1500 if (!spapr->htab) { 1501 /* There should always be a hash table when this is called */ 1502 error_report("spapr_hpte_set_r called with no hash table !"); 1503 return; 1504 } 1505 1506 /* The HW performs a non-atomic byte update */ 1507 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1508 } 1509 1510 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1511 { 1512 int shift; 1513 1514 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1515 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1516 * that's much more than is needed for Linux guests */ 1517 shift = ctz64(pow2ceil(ramsize)) - 7; 1518 shift = MAX(shift, 18); /* Minimum architected size */ 1519 shift = MIN(shift, 46); /* Maximum architected size */ 1520 return shift; 1521 } 1522 1523 void spapr_free_hpt(SpaprMachineState *spapr) 1524 { 1525 qemu_vfree(spapr->htab); 1526 spapr->htab = NULL; 1527 spapr->htab_shift = 0; 1528 close_htab_fd(spapr); 1529 } 1530 1531 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1532 { 1533 ERRP_GUARD(); 1534 long rc; 1535 1536 /* Clean up any HPT info from a previous boot */ 1537 spapr_free_hpt(spapr); 1538 1539 rc = kvmppc_reset_htab(shift); 1540 1541 if (rc == -EOPNOTSUPP) { 1542 error_setg(errp, "HPT not supported in nested guests"); 1543 return -EOPNOTSUPP; 1544 } 1545 1546 if (rc < 0) { 1547 /* kernel-side HPT needed, but couldn't allocate one */ 1548 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1549 shift); 1550 error_append_hint(errp, "Try smaller maxmem?\n"); 1551 return -errno; 1552 } else if (rc > 0) { 1553 /* kernel-side HPT allocated */ 1554 if (rc != shift) { 1555 error_setg(errp, 1556 "Requested order %d HPT, but kernel allocated order %ld", 1557 shift, rc); 1558 error_append_hint(errp, "Try smaller maxmem?\n"); 1559 return -ENOSPC; 1560 } 1561 1562 spapr->htab_shift = shift; 1563 spapr->htab = NULL; 1564 } else { 1565 /* kernel-side HPT not needed, allocate in userspace instead */ 1566 size_t size = 1ULL << shift; 1567 int i; 1568 1569 spapr->htab = qemu_memalign(size, size); 1570 memset(spapr->htab, 0, size); 1571 spapr->htab_shift = shift; 1572 1573 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1574 DIRTY_HPTE(HPTE(spapr->htab, i)); 1575 } 1576 } 1577 /* We're setting up a hash table, so that means we're not radix */ 1578 spapr->patb_entry = 0; 1579 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1580 return 0; 1581 } 1582 1583 void spapr_setup_hpt(SpaprMachineState *spapr) 1584 { 1585 int hpt_shift; 1586 1587 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1588 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1589 } else { 1590 uint64_t current_ram_size; 1591 1592 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1593 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1594 } 1595 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1596 1597 if (kvm_enabled()) { 1598 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1599 1600 /* Check our RMA fits in the possible VRMA */ 1601 if (vrma_limit < spapr->rma_size) { 1602 error_report("Unable to create %" HWADDR_PRIu 1603 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1604 spapr->rma_size / MiB, vrma_limit / MiB); 1605 exit(EXIT_FAILURE); 1606 } 1607 } 1608 } 1609 1610 void spapr_check_mmu_mode(bool guest_radix) 1611 { 1612 if (guest_radix) { 1613 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 1614 error_report("Guest requested unavailable MMU mode (radix)."); 1615 exit(EXIT_FAILURE); 1616 } 1617 } else { 1618 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 1619 && !kvmppc_has_cap_mmu_hash_v3()) { 1620 error_report("Guest requested unavailable MMU mode (hash)."); 1621 exit(EXIT_FAILURE); 1622 } 1623 } 1624 } 1625 1626 static void spapr_machine_reset(MachineState *machine) 1627 { 1628 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1629 PowerPCCPU *first_ppc_cpu; 1630 hwaddr fdt_addr; 1631 void *fdt; 1632 int rc; 1633 1634 pef_kvm_reset(machine->cgs, &error_fatal); 1635 spapr_caps_apply(spapr); 1636 1637 first_ppc_cpu = POWERPC_CPU(first_cpu); 1638 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1639 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1640 spapr->max_compat_pvr)) { 1641 /* 1642 * If using KVM with radix mode available, VCPUs can be started 1643 * without a HPT because KVM will start them in radix mode. 1644 * Set the GR bit in PATE so that we know there is no HPT. 1645 */ 1646 spapr->patb_entry = PATE1_GR; 1647 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1648 } else { 1649 spapr_setup_hpt(spapr); 1650 } 1651 1652 qemu_devices_reset(); 1653 1654 spapr_ovec_cleanup(spapr->ov5_cas); 1655 spapr->ov5_cas = spapr_ovec_new(); 1656 1657 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1658 1659 /* 1660 * This is fixing some of the default configuration of the XIVE 1661 * devices. To be called after the reset of the machine devices. 1662 */ 1663 spapr_irq_reset(spapr, &error_fatal); 1664 1665 /* 1666 * There is no CAS under qtest. Simulate one to please the code that 1667 * depends on spapr->ov5_cas. This is especially needed to test device 1668 * unplug, so we do that before resetting the DRCs. 1669 */ 1670 if (qtest_enabled()) { 1671 spapr_ovec_cleanup(spapr->ov5_cas); 1672 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1673 } 1674 1675 spapr_nvdimm_finish_flushes(); 1676 1677 /* DRC reset may cause a device to be unplugged. This will cause troubles 1678 * if this device is used by another device (eg, a running vhost backend 1679 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1680 * situations, we reset DRCs after all devices have been reset. 1681 */ 1682 spapr_drc_reset_all(spapr); 1683 1684 spapr_clear_pending_events(spapr); 1685 1686 /* 1687 * We place the device tree just below either the top of the RMA, 1688 * or just below 2GB, whichever is lower, so that it can be 1689 * processed with 32-bit real mode code if necessary 1690 */ 1691 fdt_addr = MIN(spapr->rma_size, FDT_MAX_ADDR) - FDT_MAX_SIZE; 1692 1693 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1694 if (spapr->vof) { 1695 spapr_vof_reset(spapr, fdt, &error_fatal); 1696 /* 1697 * Do not pack the FDT as the client may change properties. 1698 * VOF client does not expect the FDT so we do not load it to the VM. 1699 */ 1700 } else { 1701 rc = fdt_pack(fdt); 1702 /* Should only fail if we've built a corrupted tree */ 1703 assert(rc == 0); 1704 1705 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 1706 0, fdt_addr, 0); 1707 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1708 } 1709 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1710 1711 g_free(spapr->fdt_blob); 1712 spapr->fdt_size = fdt_totalsize(fdt); 1713 spapr->fdt_initial_size = spapr->fdt_size; 1714 spapr->fdt_blob = fdt; 1715 1716 /* Set up the entry state */ 1717 first_ppc_cpu->env.gpr[5] = 0; 1718 1719 spapr->fwnmi_system_reset_addr = -1; 1720 spapr->fwnmi_machine_check_addr = -1; 1721 spapr->fwnmi_machine_check_interlock = -1; 1722 1723 /* Signal all vCPUs waiting on this condition */ 1724 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1725 1726 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1727 } 1728 1729 static void spapr_create_nvram(SpaprMachineState *spapr) 1730 { 1731 DeviceState *dev = qdev_new("spapr-nvram"); 1732 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1733 1734 if (dinfo) { 1735 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1736 &error_fatal); 1737 } 1738 1739 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1740 1741 spapr->nvram = (struct SpaprNvram *)dev; 1742 } 1743 1744 static void spapr_rtc_create(SpaprMachineState *spapr) 1745 { 1746 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1747 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1748 &error_fatal, NULL); 1749 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1750 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1751 "date"); 1752 } 1753 1754 /* Returns whether we want to use VGA or not */ 1755 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1756 { 1757 vga_interface_created = true; 1758 switch (vga_interface_type) { 1759 case VGA_NONE: 1760 return false; 1761 case VGA_DEVICE: 1762 return true; 1763 case VGA_STD: 1764 case VGA_VIRTIO: 1765 case VGA_CIRRUS: 1766 return pci_vga_init(pci_bus) != NULL; 1767 default: 1768 error_setg(errp, 1769 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1770 return false; 1771 } 1772 } 1773 1774 static int spapr_pre_load(void *opaque) 1775 { 1776 int rc; 1777 1778 rc = spapr_caps_pre_load(opaque); 1779 if (rc) { 1780 return rc; 1781 } 1782 1783 return 0; 1784 } 1785 1786 static int spapr_post_load(void *opaque, int version_id) 1787 { 1788 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1789 int err = 0; 1790 1791 err = spapr_caps_post_migration(spapr); 1792 if (err) { 1793 return err; 1794 } 1795 1796 /* 1797 * In earlier versions, there was no separate qdev for the PAPR 1798 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1799 * So when migrating from those versions, poke the incoming offset 1800 * value into the RTC device 1801 */ 1802 if (version_id < 3) { 1803 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1804 if (err) { 1805 return err; 1806 } 1807 } 1808 1809 if (kvm_enabled() && spapr->patb_entry) { 1810 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1811 bool radix = !!(spapr->patb_entry & PATE1_GR); 1812 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1813 1814 /* 1815 * Update LPCR:HR and UPRT as they may not be set properly in 1816 * the stream 1817 */ 1818 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1819 LPCR_HR | LPCR_UPRT); 1820 1821 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1822 if (err) { 1823 error_report("Process table config unsupported by the host"); 1824 return -EINVAL; 1825 } 1826 } 1827 1828 err = spapr_irq_post_load(spapr, version_id); 1829 if (err) { 1830 return err; 1831 } 1832 1833 return err; 1834 } 1835 1836 static int spapr_pre_save(void *opaque) 1837 { 1838 int rc; 1839 1840 rc = spapr_caps_pre_save(opaque); 1841 if (rc) { 1842 return rc; 1843 } 1844 1845 return 0; 1846 } 1847 1848 static bool version_before_3(void *opaque, int version_id) 1849 { 1850 return version_id < 3; 1851 } 1852 1853 static bool spapr_pending_events_needed(void *opaque) 1854 { 1855 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1856 return !QTAILQ_EMPTY(&spapr->pending_events); 1857 } 1858 1859 static const VMStateDescription vmstate_spapr_event_entry = { 1860 .name = "spapr_event_log_entry", 1861 .version_id = 1, 1862 .minimum_version_id = 1, 1863 .fields = (VMStateField[]) { 1864 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1865 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1866 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1867 NULL, extended_length), 1868 VMSTATE_END_OF_LIST() 1869 }, 1870 }; 1871 1872 static const VMStateDescription vmstate_spapr_pending_events = { 1873 .name = "spapr_pending_events", 1874 .version_id = 1, 1875 .minimum_version_id = 1, 1876 .needed = spapr_pending_events_needed, 1877 .fields = (VMStateField[]) { 1878 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1879 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1880 VMSTATE_END_OF_LIST() 1881 }, 1882 }; 1883 1884 static bool spapr_ov5_cas_needed(void *opaque) 1885 { 1886 SpaprMachineState *spapr = opaque; 1887 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1888 bool cas_needed; 1889 1890 /* Prior to the introduction of SpaprOptionVector, we had two option 1891 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1892 * Both of these options encode machine topology into the device-tree 1893 * in such a way that the now-booted OS should still be able to interact 1894 * appropriately with QEMU regardless of what options were actually 1895 * negotiatied on the source side. 1896 * 1897 * As such, we can avoid migrating the CAS-negotiated options if these 1898 * are the only options available on the current machine/platform. 1899 * Since these are the only options available for pseries-2.7 and 1900 * earlier, this allows us to maintain old->new/new->old migration 1901 * compatibility. 1902 * 1903 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1904 * via default pseries-2.8 machines and explicit command-line parameters. 1905 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1906 * of the actual CAS-negotiated values to continue working properly. For 1907 * example, availability of memory unplug depends on knowing whether 1908 * OV5_HP_EVT was negotiated via CAS. 1909 * 1910 * Thus, for any cases where the set of available CAS-negotiatable 1911 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1912 * include the CAS-negotiated options in the migration stream, unless 1913 * if they affect boot time behaviour only. 1914 */ 1915 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1916 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1917 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1918 1919 /* We need extra information if we have any bits outside the mask 1920 * defined above */ 1921 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1922 1923 spapr_ovec_cleanup(ov5_mask); 1924 1925 return cas_needed; 1926 } 1927 1928 static const VMStateDescription vmstate_spapr_ov5_cas = { 1929 .name = "spapr_option_vector_ov5_cas", 1930 .version_id = 1, 1931 .minimum_version_id = 1, 1932 .needed = spapr_ov5_cas_needed, 1933 .fields = (VMStateField[]) { 1934 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1935 vmstate_spapr_ovec, SpaprOptionVector), 1936 VMSTATE_END_OF_LIST() 1937 }, 1938 }; 1939 1940 static bool spapr_patb_entry_needed(void *opaque) 1941 { 1942 SpaprMachineState *spapr = opaque; 1943 1944 return !!spapr->patb_entry; 1945 } 1946 1947 static const VMStateDescription vmstate_spapr_patb_entry = { 1948 .name = "spapr_patb_entry", 1949 .version_id = 1, 1950 .minimum_version_id = 1, 1951 .needed = spapr_patb_entry_needed, 1952 .fields = (VMStateField[]) { 1953 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1954 VMSTATE_END_OF_LIST() 1955 }, 1956 }; 1957 1958 static bool spapr_irq_map_needed(void *opaque) 1959 { 1960 SpaprMachineState *spapr = opaque; 1961 1962 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1963 } 1964 1965 static const VMStateDescription vmstate_spapr_irq_map = { 1966 .name = "spapr_irq_map", 1967 .version_id = 1, 1968 .minimum_version_id = 1, 1969 .needed = spapr_irq_map_needed, 1970 .fields = (VMStateField[]) { 1971 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1972 VMSTATE_END_OF_LIST() 1973 }, 1974 }; 1975 1976 static bool spapr_dtb_needed(void *opaque) 1977 { 1978 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1979 1980 return smc->update_dt_enabled; 1981 } 1982 1983 static int spapr_dtb_pre_load(void *opaque) 1984 { 1985 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1986 1987 g_free(spapr->fdt_blob); 1988 spapr->fdt_blob = NULL; 1989 spapr->fdt_size = 0; 1990 1991 return 0; 1992 } 1993 1994 static const VMStateDescription vmstate_spapr_dtb = { 1995 .name = "spapr_dtb", 1996 .version_id = 1, 1997 .minimum_version_id = 1, 1998 .needed = spapr_dtb_needed, 1999 .pre_load = spapr_dtb_pre_load, 2000 .fields = (VMStateField[]) { 2001 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 2002 VMSTATE_UINT32(fdt_size, SpaprMachineState), 2003 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 2004 fdt_size), 2005 VMSTATE_END_OF_LIST() 2006 }, 2007 }; 2008 2009 static bool spapr_fwnmi_needed(void *opaque) 2010 { 2011 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2012 2013 return spapr->fwnmi_machine_check_addr != -1; 2014 } 2015 2016 static int spapr_fwnmi_pre_save(void *opaque) 2017 { 2018 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2019 2020 /* 2021 * Check if machine check handling is in progress and print a 2022 * warning message. 2023 */ 2024 if (spapr->fwnmi_machine_check_interlock != -1) { 2025 warn_report("A machine check is being handled during migration. The" 2026 "handler may run and log hardware error on the destination"); 2027 } 2028 2029 return 0; 2030 } 2031 2032 static const VMStateDescription vmstate_spapr_fwnmi = { 2033 .name = "spapr_fwnmi", 2034 .version_id = 1, 2035 .minimum_version_id = 1, 2036 .needed = spapr_fwnmi_needed, 2037 .pre_save = spapr_fwnmi_pre_save, 2038 .fields = (VMStateField[]) { 2039 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 2040 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 2041 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 2042 VMSTATE_END_OF_LIST() 2043 }, 2044 }; 2045 2046 static const VMStateDescription vmstate_spapr = { 2047 .name = "spapr", 2048 .version_id = 3, 2049 .minimum_version_id = 1, 2050 .pre_load = spapr_pre_load, 2051 .post_load = spapr_post_load, 2052 .pre_save = spapr_pre_save, 2053 .fields = (VMStateField[]) { 2054 /* used to be @next_irq */ 2055 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2056 2057 /* RTC offset */ 2058 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2059 2060 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2061 VMSTATE_END_OF_LIST() 2062 }, 2063 .subsections = (const VMStateDescription*[]) { 2064 &vmstate_spapr_ov5_cas, 2065 &vmstate_spapr_patb_entry, 2066 &vmstate_spapr_pending_events, 2067 &vmstate_spapr_cap_htm, 2068 &vmstate_spapr_cap_vsx, 2069 &vmstate_spapr_cap_dfp, 2070 &vmstate_spapr_cap_cfpc, 2071 &vmstate_spapr_cap_sbbc, 2072 &vmstate_spapr_cap_ibs, 2073 &vmstate_spapr_cap_hpt_maxpagesize, 2074 &vmstate_spapr_irq_map, 2075 &vmstate_spapr_cap_nested_kvm_hv, 2076 &vmstate_spapr_dtb, 2077 &vmstate_spapr_cap_large_decr, 2078 &vmstate_spapr_cap_ccf_assist, 2079 &vmstate_spapr_cap_fwnmi, 2080 &vmstate_spapr_fwnmi, 2081 &vmstate_spapr_cap_rpt_invalidate, 2082 NULL 2083 } 2084 }; 2085 2086 static int htab_save_setup(QEMUFile *f, void *opaque) 2087 { 2088 SpaprMachineState *spapr = opaque; 2089 2090 /* "Iteration" header */ 2091 if (!spapr->htab_shift) { 2092 qemu_put_be32(f, -1); 2093 } else { 2094 qemu_put_be32(f, spapr->htab_shift); 2095 } 2096 2097 if (spapr->htab) { 2098 spapr->htab_save_index = 0; 2099 spapr->htab_first_pass = true; 2100 } else { 2101 if (spapr->htab_shift) { 2102 assert(kvm_enabled()); 2103 } 2104 } 2105 2106 2107 return 0; 2108 } 2109 2110 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2111 int chunkstart, int n_valid, int n_invalid) 2112 { 2113 qemu_put_be32(f, chunkstart); 2114 qemu_put_be16(f, n_valid); 2115 qemu_put_be16(f, n_invalid); 2116 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2117 HASH_PTE_SIZE_64 * n_valid); 2118 } 2119 2120 static void htab_save_end_marker(QEMUFile *f) 2121 { 2122 qemu_put_be32(f, 0); 2123 qemu_put_be16(f, 0); 2124 qemu_put_be16(f, 0); 2125 } 2126 2127 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2128 int64_t max_ns) 2129 { 2130 bool has_timeout = max_ns != -1; 2131 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2132 int index = spapr->htab_save_index; 2133 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2134 2135 assert(spapr->htab_first_pass); 2136 2137 do { 2138 int chunkstart; 2139 2140 /* Consume invalid HPTEs */ 2141 while ((index < htabslots) 2142 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2143 CLEAN_HPTE(HPTE(spapr->htab, index)); 2144 index++; 2145 } 2146 2147 /* Consume valid HPTEs */ 2148 chunkstart = index; 2149 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2150 && HPTE_VALID(HPTE(spapr->htab, index))) { 2151 CLEAN_HPTE(HPTE(spapr->htab, index)); 2152 index++; 2153 } 2154 2155 if (index > chunkstart) { 2156 int n_valid = index - chunkstart; 2157 2158 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2159 2160 if (has_timeout && 2161 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2162 break; 2163 } 2164 } 2165 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2166 2167 if (index >= htabslots) { 2168 assert(index == htabslots); 2169 index = 0; 2170 spapr->htab_first_pass = false; 2171 } 2172 spapr->htab_save_index = index; 2173 } 2174 2175 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2176 int64_t max_ns) 2177 { 2178 bool final = max_ns < 0; 2179 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2180 int examined = 0, sent = 0; 2181 int index = spapr->htab_save_index; 2182 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2183 2184 assert(!spapr->htab_first_pass); 2185 2186 do { 2187 int chunkstart, invalidstart; 2188 2189 /* Consume non-dirty HPTEs */ 2190 while ((index < htabslots) 2191 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2192 index++; 2193 examined++; 2194 } 2195 2196 chunkstart = index; 2197 /* Consume valid dirty HPTEs */ 2198 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2199 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2200 && HPTE_VALID(HPTE(spapr->htab, index))) { 2201 CLEAN_HPTE(HPTE(spapr->htab, index)); 2202 index++; 2203 examined++; 2204 } 2205 2206 invalidstart = index; 2207 /* Consume invalid dirty HPTEs */ 2208 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2209 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2210 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2211 CLEAN_HPTE(HPTE(spapr->htab, index)); 2212 index++; 2213 examined++; 2214 } 2215 2216 if (index > chunkstart) { 2217 int n_valid = invalidstart - chunkstart; 2218 int n_invalid = index - invalidstart; 2219 2220 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2221 sent += index - chunkstart; 2222 2223 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2224 break; 2225 } 2226 } 2227 2228 if (examined >= htabslots) { 2229 break; 2230 } 2231 2232 if (index >= htabslots) { 2233 assert(index == htabslots); 2234 index = 0; 2235 } 2236 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2237 2238 if (index >= htabslots) { 2239 assert(index == htabslots); 2240 index = 0; 2241 } 2242 2243 spapr->htab_save_index = index; 2244 2245 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2246 } 2247 2248 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2249 #define MAX_KVM_BUF_SIZE 2048 2250 2251 static int htab_save_iterate(QEMUFile *f, void *opaque) 2252 { 2253 SpaprMachineState *spapr = opaque; 2254 int fd; 2255 int rc = 0; 2256 2257 /* Iteration header */ 2258 if (!spapr->htab_shift) { 2259 qemu_put_be32(f, -1); 2260 return 1; 2261 } else { 2262 qemu_put_be32(f, 0); 2263 } 2264 2265 if (!spapr->htab) { 2266 assert(kvm_enabled()); 2267 2268 fd = get_htab_fd(spapr); 2269 if (fd < 0) { 2270 return fd; 2271 } 2272 2273 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2274 if (rc < 0) { 2275 return rc; 2276 } 2277 } else if (spapr->htab_first_pass) { 2278 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2279 } else { 2280 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2281 } 2282 2283 htab_save_end_marker(f); 2284 2285 return rc; 2286 } 2287 2288 static int htab_save_complete(QEMUFile *f, void *opaque) 2289 { 2290 SpaprMachineState *spapr = opaque; 2291 int fd; 2292 2293 /* Iteration header */ 2294 if (!spapr->htab_shift) { 2295 qemu_put_be32(f, -1); 2296 return 0; 2297 } else { 2298 qemu_put_be32(f, 0); 2299 } 2300 2301 if (!spapr->htab) { 2302 int rc; 2303 2304 assert(kvm_enabled()); 2305 2306 fd = get_htab_fd(spapr); 2307 if (fd < 0) { 2308 return fd; 2309 } 2310 2311 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2312 if (rc < 0) { 2313 return rc; 2314 } 2315 } else { 2316 if (spapr->htab_first_pass) { 2317 htab_save_first_pass(f, spapr, -1); 2318 } 2319 htab_save_later_pass(f, spapr, -1); 2320 } 2321 2322 /* End marker */ 2323 htab_save_end_marker(f); 2324 2325 return 0; 2326 } 2327 2328 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2329 { 2330 SpaprMachineState *spapr = opaque; 2331 uint32_t section_hdr; 2332 int fd = -1; 2333 Error *local_err = NULL; 2334 2335 if (version_id < 1 || version_id > 1) { 2336 error_report("htab_load() bad version"); 2337 return -EINVAL; 2338 } 2339 2340 section_hdr = qemu_get_be32(f); 2341 2342 if (section_hdr == -1) { 2343 spapr_free_hpt(spapr); 2344 return 0; 2345 } 2346 2347 if (section_hdr) { 2348 int ret; 2349 2350 /* First section gives the htab size */ 2351 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2352 if (ret < 0) { 2353 error_report_err(local_err); 2354 return ret; 2355 } 2356 return 0; 2357 } 2358 2359 if (!spapr->htab) { 2360 assert(kvm_enabled()); 2361 2362 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2363 if (fd < 0) { 2364 error_report_err(local_err); 2365 return fd; 2366 } 2367 } 2368 2369 while (true) { 2370 uint32_t index; 2371 uint16_t n_valid, n_invalid; 2372 2373 index = qemu_get_be32(f); 2374 n_valid = qemu_get_be16(f); 2375 n_invalid = qemu_get_be16(f); 2376 2377 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2378 /* End of Stream */ 2379 break; 2380 } 2381 2382 if ((index + n_valid + n_invalid) > 2383 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2384 /* Bad index in stream */ 2385 error_report( 2386 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2387 index, n_valid, n_invalid, spapr->htab_shift); 2388 return -EINVAL; 2389 } 2390 2391 if (spapr->htab) { 2392 if (n_valid) { 2393 qemu_get_buffer(f, HPTE(spapr->htab, index), 2394 HASH_PTE_SIZE_64 * n_valid); 2395 } 2396 if (n_invalid) { 2397 memset(HPTE(spapr->htab, index + n_valid), 0, 2398 HASH_PTE_SIZE_64 * n_invalid); 2399 } 2400 } else { 2401 int rc; 2402 2403 assert(fd >= 0); 2404 2405 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2406 &local_err); 2407 if (rc < 0) { 2408 error_report_err(local_err); 2409 return rc; 2410 } 2411 } 2412 } 2413 2414 if (!spapr->htab) { 2415 assert(fd >= 0); 2416 close(fd); 2417 } 2418 2419 return 0; 2420 } 2421 2422 static void htab_save_cleanup(void *opaque) 2423 { 2424 SpaprMachineState *spapr = opaque; 2425 2426 close_htab_fd(spapr); 2427 } 2428 2429 static SaveVMHandlers savevm_htab_handlers = { 2430 .save_setup = htab_save_setup, 2431 .save_live_iterate = htab_save_iterate, 2432 .save_live_complete_precopy = htab_save_complete, 2433 .save_cleanup = htab_save_cleanup, 2434 .load_state = htab_load, 2435 }; 2436 2437 static void spapr_boot_set(void *opaque, const char *boot_device, 2438 Error **errp) 2439 { 2440 SpaprMachineState *spapr = SPAPR_MACHINE(opaque); 2441 2442 g_free(spapr->boot_device); 2443 spapr->boot_device = g_strdup(boot_device); 2444 } 2445 2446 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2447 { 2448 MachineState *machine = MACHINE(spapr); 2449 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2450 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2451 int i; 2452 2453 for (i = 0; i < nr_lmbs; i++) { 2454 uint64_t addr; 2455 2456 addr = i * lmb_size + machine->device_memory->base; 2457 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2458 addr / lmb_size); 2459 } 2460 } 2461 2462 /* 2463 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2464 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2465 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2466 */ 2467 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2468 { 2469 int i; 2470 2471 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2472 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2473 " is not aligned to %" PRIu64 " MiB", 2474 machine->ram_size, 2475 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2476 return; 2477 } 2478 2479 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2480 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2481 " is not aligned to %" PRIu64 " MiB", 2482 machine->ram_size, 2483 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2484 return; 2485 } 2486 2487 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2488 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2489 error_setg(errp, 2490 "Node %d memory size 0x%" PRIx64 2491 " is not aligned to %" PRIu64 " MiB", 2492 i, machine->numa_state->nodes[i].node_mem, 2493 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2494 return; 2495 } 2496 } 2497 } 2498 2499 /* find cpu slot in machine->possible_cpus by core_id */ 2500 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2501 { 2502 int index = id / ms->smp.threads; 2503 2504 if (index >= ms->possible_cpus->len) { 2505 return NULL; 2506 } 2507 if (idx) { 2508 *idx = index; 2509 } 2510 return &ms->possible_cpus->cpus[index]; 2511 } 2512 2513 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2514 { 2515 MachineState *ms = MACHINE(spapr); 2516 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2517 Error *local_err = NULL; 2518 bool vsmt_user = !!spapr->vsmt; 2519 int kvm_smt = kvmppc_smt_threads(); 2520 int ret; 2521 unsigned int smp_threads = ms->smp.threads; 2522 2523 if (!kvm_enabled() && (smp_threads > 1)) { 2524 error_setg(errp, "TCG cannot support more than 1 thread/core " 2525 "on a pseries machine"); 2526 return; 2527 } 2528 if (!is_power_of_2(smp_threads)) { 2529 error_setg(errp, "Cannot support %d threads/core on a pseries " 2530 "machine because it must be a power of 2", smp_threads); 2531 return; 2532 } 2533 2534 /* Detemine the VSMT mode to use: */ 2535 if (vsmt_user) { 2536 if (spapr->vsmt < smp_threads) { 2537 error_setg(errp, "Cannot support VSMT mode %d" 2538 " because it must be >= threads/core (%d)", 2539 spapr->vsmt, smp_threads); 2540 return; 2541 } 2542 /* In this case, spapr->vsmt has been set by the command line */ 2543 } else if (!smc->smp_threads_vsmt) { 2544 /* 2545 * Default VSMT value is tricky, because we need it to be as 2546 * consistent as possible (for migration), but this requires 2547 * changing it for at least some existing cases. We pick 8 as 2548 * the value that we'd get with KVM on POWER8, the 2549 * overwhelmingly common case in production systems. 2550 */ 2551 spapr->vsmt = MAX(8, smp_threads); 2552 } else { 2553 spapr->vsmt = smp_threads; 2554 } 2555 2556 /* KVM: If necessary, set the SMT mode: */ 2557 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2558 ret = kvmppc_set_smt_threads(spapr->vsmt); 2559 if (ret) { 2560 /* Looks like KVM isn't able to change VSMT mode */ 2561 error_setg(&local_err, 2562 "Failed to set KVM's VSMT mode to %d (errno %d)", 2563 spapr->vsmt, ret); 2564 /* We can live with that if the default one is big enough 2565 * for the number of threads, and a submultiple of the one 2566 * we want. In this case we'll waste some vcpu ids, but 2567 * behaviour will be correct */ 2568 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2569 warn_report_err(local_err); 2570 } else { 2571 if (!vsmt_user) { 2572 error_append_hint(&local_err, 2573 "On PPC, a VM with %d threads/core" 2574 " on a host with %d threads/core" 2575 " requires the use of VSMT mode %d.\n", 2576 smp_threads, kvm_smt, spapr->vsmt); 2577 } 2578 kvmppc_error_append_smt_possible_hint(&local_err); 2579 error_propagate(errp, local_err); 2580 } 2581 } 2582 } 2583 /* else TCG: nothing to do currently */ 2584 } 2585 2586 static void spapr_init_cpus(SpaprMachineState *spapr) 2587 { 2588 MachineState *machine = MACHINE(spapr); 2589 MachineClass *mc = MACHINE_GET_CLASS(machine); 2590 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2591 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2592 const CPUArchIdList *possible_cpus; 2593 unsigned int smp_cpus = machine->smp.cpus; 2594 unsigned int smp_threads = machine->smp.threads; 2595 unsigned int max_cpus = machine->smp.max_cpus; 2596 int boot_cores_nr = smp_cpus / smp_threads; 2597 int i; 2598 2599 possible_cpus = mc->possible_cpu_arch_ids(machine); 2600 if (mc->has_hotpluggable_cpus) { 2601 if (smp_cpus % smp_threads) { 2602 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2603 smp_cpus, smp_threads); 2604 exit(1); 2605 } 2606 if (max_cpus % smp_threads) { 2607 error_report("max_cpus (%u) must be multiple of threads (%u)", 2608 max_cpus, smp_threads); 2609 exit(1); 2610 } 2611 } else { 2612 if (max_cpus != smp_cpus) { 2613 error_report("This machine version does not support CPU hotplug"); 2614 exit(1); 2615 } 2616 boot_cores_nr = possible_cpus->len; 2617 } 2618 2619 if (smc->pre_2_10_has_unused_icps) { 2620 int i; 2621 2622 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2623 /* Dummy entries get deregistered when real ICPState objects 2624 * are registered during CPU core hotplug. 2625 */ 2626 pre_2_10_vmstate_register_dummy_icp(i); 2627 } 2628 } 2629 2630 for (i = 0; i < possible_cpus->len; i++) { 2631 int core_id = i * smp_threads; 2632 2633 if (mc->has_hotpluggable_cpus) { 2634 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2635 spapr_vcpu_id(spapr, core_id)); 2636 } 2637 2638 if (i < boot_cores_nr) { 2639 Object *core = object_new(type); 2640 int nr_threads = smp_threads; 2641 2642 /* Handle the partially filled core for older machine types */ 2643 if ((i + 1) * smp_threads >= smp_cpus) { 2644 nr_threads = smp_cpus - i * smp_threads; 2645 } 2646 2647 object_property_set_int(core, "nr-threads", nr_threads, 2648 &error_fatal); 2649 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2650 &error_fatal); 2651 qdev_realize(DEVICE(core), NULL, &error_fatal); 2652 2653 object_unref(core); 2654 } 2655 } 2656 } 2657 2658 static PCIHostState *spapr_create_default_phb(void) 2659 { 2660 DeviceState *dev; 2661 2662 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2663 qdev_prop_set_uint32(dev, "index", 0); 2664 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2665 2666 return PCI_HOST_BRIDGE(dev); 2667 } 2668 2669 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2670 { 2671 MachineState *machine = MACHINE(spapr); 2672 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2673 hwaddr rma_size = machine->ram_size; 2674 hwaddr node0_size = spapr_node0_size(machine); 2675 2676 /* RMA has to fit in the first NUMA node */ 2677 rma_size = MIN(rma_size, node0_size); 2678 2679 /* 2680 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2681 * never exceed that 2682 */ 2683 rma_size = MIN(rma_size, 1 * TiB); 2684 2685 /* 2686 * Clamp the RMA size based on machine type. This is for 2687 * migration compatibility with older qemu versions, which limited 2688 * the RMA size for complicated and mostly bad reasons. 2689 */ 2690 if (smc->rma_limit) { 2691 rma_size = MIN(rma_size, smc->rma_limit); 2692 } 2693 2694 if (rma_size < MIN_RMA_SLOF) { 2695 error_setg(errp, 2696 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2697 "ldMiB guest RMA (Real Mode Area memory)", 2698 MIN_RMA_SLOF / MiB); 2699 return 0; 2700 } 2701 2702 return rma_size; 2703 } 2704 2705 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2706 { 2707 MachineState *machine = MACHINE(spapr); 2708 int i; 2709 2710 for (i = 0; i < machine->ram_slots; i++) { 2711 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2712 } 2713 } 2714 2715 /* pSeries LPAR / sPAPR hardware init */ 2716 static void spapr_machine_init(MachineState *machine) 2717 { 2718 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2719 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2720 MachineClass *mc = MACHINE_GET_CLASS(machine); 2721 const char *bios_default = spapr->vof ? FW_FILE_NAME_VOF : FW_FILE_NAME; 2722 const char *bios_name = machine->firmware ?: bios_default; 2723 g_autofree char *filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2724 const char *kernel_filename = machine->kernel_filename; 2725 const char *initrd_filename = machine->initrd_filename; 2726 PCIHostState *phb; 2727 bool has_vga; 2728 int i; 2729 MemoryRegion *sysmem = get_system_memory(); 2730 long load_limit, fw_size; 2731 Error *resize_hpt_err = NULL; 2732 2733 if (!filename) { 2734 error_report("Could not find LPAR firmware '%s'", bios_name); 2735 exit(1); 2736 } 2737 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2738 if (fw_size <= 0) { 2739 error_report("Could not load LPAR firmware '%s'", filename); 2740 exit(1); 2741 } 2742 2743 /* 2744 * if Secure VM (PEF) support is configured, then initialize it 2745 */ 2746 pef_kvm_init(machine->cgs, &error_fatal); 2747 2748 msi_nonbroken = true; 2749 2750 QLIST_INIT(&spapr->phbs); 2751 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2752 2753 /* Determine capabilities to run with */ 2754 spapr_caps_init(spapr); 2755 2756 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2757 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2758 /* 2759 * If the user explicitly requested a mode we should either 2760 * supply it, or fail completely (which we do below). But if 2761 * it's not set explicitly, we reset our mode to something 2762 * that works 2763 */ 2764 if (resize_hpt_err) { 2765 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2766 error_free(resize_hpt_err); 2767 resize_hpt_err = NULL; 2768 } else { 2769 spapr->resize_hpt = smc->resize_hpt_default; 2770 } 2771 } 2772 2773 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2774 2775 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2776 /* 2777 * User requested HPT resize, but this host can't supply it. Bail out 2778 */ 2779 error_report_err(resize_hpt_err); 2780 exit(1); 2781 } 2782 error_free(resize_hpt_err); 2783 2784 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2785 2786 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2787 load_limit = MIN(spapr->rma_size, FDT_MAX_ADDR) - FW_OVERHEAD; 2788 2789 /* 2790 * VSMT must be set in order to be able to compute VCPU ids, ie to 2791 * call spapr_max_server_number() or spapr_vcpu_id(). 2792 */ 2793 spapr_set_vsmt_mode(spapr, &error_fatal); 2794 2795 /* Set up Interrupt Controller before we create the VCPUs */ 2796 spapr_irq_init(spapr, &error_fatal); 2797 2798 /* Set up containers for ibm,client-architecture-support negotiated options 2799 */ 2800 spapr->ov5 = spapr_ovec_new(); 2801 spapr->ov5_cas = spapr_ovec_new(); 2802 2803 if (smc->dr_lmb_enabled) { 2804 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2805 spapr_validate_node_memory(machine, &error_fatal); 2806 } 2807 2808 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2809 2810 /* Do not advertise FORM2 NUMA support for pseries-6.1 and older */ 2811 if (!smc->pre_6_2_numa_affinity) { 2812 spapr_ovec_set(spapr->ov5, OV5_FORM2_AFFINITY); 2813 } 2814 2815 /* advertise support for dedicated HP event source to guests */ 2816 if (spapr->use_hotplug_event_source) { 2817 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2818 } 2819 2820 /* advertise support for HPT resizing */ 2821 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2822 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2823 } 2824 2825 /* advertise support for ibm,dyamic-memory-v2 */ 2826 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2827 2828 /* advertise XIVE on POWER9 machines */ 2829 if (spapr->irq->xive) { 2830 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2831 } 2832 2833 /* init CPUs */ 2834 spapr_init_cpus(spapr); 2835 2836 spapr->gpu_numa_id = spapr_numa_initial_nvgpu_numa_id(machine); 2837 2838 /* Init numa_assoc_array */ 2839 spapr_numa_associativity_init(spapr, machine); 2840 2841 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2842 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2843 spapr->max_compat_pvr)) { 2844 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2845 /* KVM and TCG always allow GTSE with radix... */ 2846 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2847 } 2848 /* ... but not with hash (currently). */ 2849 2850 if (kvm_enabled()) { 2851 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2852 kvmppc_enable_logical_ci_hcalls(); 2853 kvmppc_enable_set_mode_hcall(); 2854 2855 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2856 kvmppc_enable_clear_ref_mod_hcalls(); 2857 2858 /* Enable H_PAGE_INIT */ 2859 kvmppc_enable_h_page_init(); 2860 } 2861 2862 /* map RAM */ 2863 memory_region_add_subregion(sysmem, 0, machine->ram); 2864 2865 /* always allocate the device memory information */ 2866 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2867 2868 /* initialize hotplug memory address space */ 2869 if (machine->ram_size < machine->maxram_size) { 2870 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2871 /* 2872 * Limit the number of hotpluggable memory slots to half the number 2873 * slots that KVM supports, leaving the other half for PCI and other 2874 * devices. However ensure that number of slots doesn't drop below 32. 2875 */ 2876 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2877 SPAPR_MAX_RAM_SLOTS; 2878 2879 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2880 max_memslots = SPAPR_MAX_RAM_SLOTS; 2881 } 2882 if (machine->ram_slots > max_memslots) { 2883 error_report("Specified number of memory slots %" 2884 PRIu64" exceeds max supported %d", 2885 machine->ram_slots, max_memslots); 2886 exit(1); 2887 } 2888 2889 machine->device_memory->base = ROUND_UP(machine->ram_size, 2890 SPAPR_DEVICE_MEM_ALIGN); 2891 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2892 "device-memory", device_mem_size); 2893 memory_region_add_subregion(sysmem, machine->device_memory->base, 2894 &machine->device_memory->mr); 2895 } 2896 2897 if (smc->dr_lmb_enabled) { 2898 spapr_create_lmb_dr_connectors(spapr); 2899 } 2900 2901 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { 2902 /* Create the error string for live migration blocker */ 2903 error_setg(&spapr->fwnmi_migration_blocker, 2904 "A machine check is being handled during migration. The handler" 2905 "may run and log hardware error on the destination"); 2906 } 2907 2908 if (mc->nvdimm_supported) { 2909 spapr_create_nvdimm_dr_connectors(spapr); 2910 } 2911 2912 /* Set up RTAS event infrastructure */ 2913 spapr_events_init(spapr); 2914 2915 /* Set up the RTC RTAS interfaces */ 2916 spapr_rtc_create(spapr); 2917 2918 /* Set up VIO bus */ 2919 spapr->vio_bus = spapr_vio_bus_init(); 2920 2921 for (i = 0; serial_hd(i); i++) { 2922 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2923 } 2924 2925 /* We always have at least the nvram device on VIO */ 2926 spapr_create_nvram(spapr); 2927 2928 /* 2929 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2930 * connectors (described in root DT node's "ibm,drc-types" property) 2931 * are pre-initialized here. additional child connectors (such as 2932 * connectors for a PHBs PCI slots) are added as needed during their 2933 * parent's realization. 2934 */ 2935 if (smc->dr_phb_enabled) { 2936 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2937 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2938 } 2939 } 2940 2941 /* Set up PCI */ 2942 spapr_pci_rtas_init(); 2943 2944 phb = spapr_create_default_phb(); 2945 2946 for (i = 0; i < nb_nics; i++) { 2947 NICInfo *nd = &nd_table[i]; 2948 2949 if (!nd->model) { 2950 nd->model = g_strdup("spapr-vlan"); 2951 } 2952 2953 if (g_str_equal(nd->model, "spapr-vlan") || 2954 g_str_equal(nd->model, "ibmveth")) { 2955 spapr_vlan_create(spapr->vio_bus, nd); 2956 } else { 2957 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2958 } 2959 } 2960 2961 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2962 spapr_vscsi_create(spapr->vio_bus); 2963 } 2964 2965 /* Graphics */ 2966 has_vga = spapr_vga_init(phb->bus, &error_fatal); 2967 if (has_vga) { 2968 spapr->want_stdout_path = !machine->enable_graphics; 2969 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2970 } else { 2971 spapr->want_stdout_path = true; 2972 } 2973 2974 if (machine->usb) { 2975 if (smc->use_ohci_by_default) { 2976 pci_create_simple(phb->bus, -1, "pci-ohci"); 2977 } else { 2978 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2979 } 2980 2981 if (has_vga) { 2982 USBBus *usb_bus = usb_bus_find(-1); 2983 2984 usb_create_simple(usb_bus, "usb-kbd"); 2985 usb_create_simple(usb_bus, "usb-mouse"); 2986 } 2987 } 2988 2989 if (kernel_filename) { 2990 uint64_t loaded_addr = 0; 2991 2992 spapr->kernel_size = load_elf(kernel_filename, NULL, 2993 translate_kernel_address, spapr, 2994 NULL, &loaded_addr, NULL, NULL, 1, 2995 PPC_ELF_MACHINE, 0, 0); 2996 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2997 spapr->kernel_size = load_elf(kernel_filename, NULL, 2998 translate_kernel_address, spapr, 2999 NULL, &loaded_addr, NULL, NULL, 0, 3000 PPC_ELF_MACHINE, 0, 0); 3001 spapr->kernel_le = spapr->kernel_size > 0; 3002 } 3003 if (spapr->kernel_size < 0) { 3004 error_report("error loading %s: %s", kernel_filename, 3005 load_elf_strerror(spapr->kernel_size)); 3006 exit(1); 3007 } 3008 3009 if (spapr->kernel_addr != loaded_addr) { 3010 warn_report("spapr: kernel_addr changed from 0x%"PRIx64 3011 " to 0x%"PRIx64, 3012 spapr->kernel_addr, loaded_addr); 3013 spapr->kernel_addr = loaded_addr; 3014 } 3015 3016 /* load initrd */ 3017 if (initrd_filename) { 3018 /* Try to locate the initrd in the gap between the kernel 3019 * and the firmware. Add a bit of space just in case 3020 */ 3021 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 3022 + 0x1ffff) & ~0xffff; 3023 spapr->initrd_size = load_image_targphys(initrd_filename, 3024 spapr->initrd_base, 3025 load_limit 3026 - spapr->initrd_base); 3027 if (spapr->initrd_size < 0) { 3028 error_report("could not load initial ram disk '%s'", 3029 initrd_filename); 3030 exit(1); 3031 } 3032 } 3033 } 3034 3035 /* FIXME: Should register things through the MachineState's qdev 3036 * interface, this is a legacy from the sPAPREnvironment structure 3037 * which predated MachineState but had a similar function */ 3038 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3039 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3040 &savevm_htab_handlers, spapr); 3041 3042 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 3043 3044 qemu_register_boot_set(spapr_boot_set, spapr); 3045 3046 /* 3047 * Nothing needs to be done to resume a suspended guest because 3048 * suspending does not change the machine state, so no need for 3049 * a ->wakeup method. 3050 */ 3051 qemu_register_wakeup_support(); 3052 3053 if (kvm_enabled()) { 3054 /* to stop and start vmclock */ 3055 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3056 &spapr->tb); 3057 3058 kvmppc_spapr_enable_inkernel_multitce(); 3059 } 3060 3061 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3062 if (spapr->vof) { 3063 spapr->vof->fw_size = fw_size; /* for claim() on itself */ 3064 spapr_register_hypercall(KVMPPC_H_VOF_CLIENT, spapr_h_vof_client); 3065 } 3066 3067 spapr_watchdog_init(spapr); 3068 } 3069 3070 #define DEFAULT_KVM_TYPE "auto" 3071 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3072 { 3073 /* 3074 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to 3075 * accomodate the 'HV' and 'PV' formats that exists in the 3076 * wild. The 'auto' mode is being introduced already as 3077 * lower-case, thus we don't need to bother checking for 3078 * "AUTO". 3079 */ 3080 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) { 3081 return 0; 3082 } 3083 3084 if (!g_ascii_strcasecmp(vm_type, "hv")) { 3085 return 1; 3086 } 3087 3088 if (!g_ascii_strcasecmp(vm_type, "pr")) { 3089 return 2; 3090 } 3091 3092 error_report("Unknown kvm-type specified '%s'", vm_type); 3093 exit(1); 3094 } 3095 3096 /* 3097 * Implementation of an interface to adjust firmware path 3098 * for the bootindex property handling. 3099 */ 3100 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3101 DeviceState *dev) 3102 { 3103 #define CAST(type, obj, name) \ 3104 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3105 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3106 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3107 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3108 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3109 3110 if (d && bus) { 3111 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3112 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3113 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3114 3115 if (spapr) { 3116 /* 3117 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3118 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3119 * 0x8000 | (target << 8) | (bus << 5) | lun 3120 * (see the "Logical unit addressing format" table in SAM5) 3121 */ 3122 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3123 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3124 (uint64_t)id << 48); 3125 } else if (virtio) { 3126 /* 3127 * We use SRP luns of the form 01000000 | (target << 8) | lun 3128 * in the top 32 bits of the 64-bit LUN 3129 * Note: the quote above is from SLOF and it is wrong, 3130 * the actual binding is: 3131 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3132 */ 3133 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3134 if (d->lun >= 256) { 3135 /* Use the LUN "flat space addressing method" */ 3136 id |= 0x4000; 3137 } 3138 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3139 (uint64_t)id << 32); 3140 } else if (usb) { 3141 /* 3142 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3143 * in the top 32 bits of the 64-bit LUN 3144 */ 3145 unsigned usb_port = atoi(usb->port->path); 3146 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3147 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3148 (uint64_t)id << 32); 3149 } 3150 } 3151 3152 /* 3153 * SLOF probes the USB devices, and if it recognizes that the device is a 3154 * storage device, it changes its name to "storage" instead of "usb-host", 3155 * and additionally adds a child node for the SCSI LUN, so the correct 3156 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3157 */ 3158 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3159 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3160 if (usb_device_is_scsi_storage(usbdev)) { 3161 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3162 } 3163 } 3164 3165 if (phb) { 3166 /* Replace "pci" with "pci@800000020000000" */ 3167 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3168 } 3169 3170 if (vsc) { 3171 /* Same logic as virtio above */ 3172 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3173 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3174 } 3175 3176 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3177 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3178 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3179 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3180 } 3181 3182 if (pcidev) { 3183 return spapr_pci_fw_dev_name(pcidev); 3184 } 3185 3186 return NULL; 3187 } 3188 3189 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3190 { 3191 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3192 3193 return g_strdup(spapr->kvm_type); 3194 } 3195 3196 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3197 { 3198 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3199 3200 g_free(spapr->kvm_type); 3201 spapr->kvm_type = g_strdup(value); 3202 } 3203 3204 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3205 { 3206 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3207 3208 return spapr->use_hotplug_event_source; 3209 } 3210 3211 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3212 Error **errp) 3213 { 3214 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3215 3216 spapr->use_hotplug_event_source = value; 3217 } 3218 3219 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3220 { 3221 return true; 3222 } 3223 3224 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3225 { 3226 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3227 3228 switch (spapr->resize_hpt) { 3229 case SPAPR_RESIZE_HPT_DEFAULT: 3230 return g_strdup("default"); 3231 case SPAPR_RESIZE_HPT_DISABLED: 3232 return g_strdup("disabled"); 3233 case SPAPR_RESIZE_HPT_ENABLED: 3234 return g_strdup("enabled"); 3235 case SPAPR_RESIZE_HPT_REQUIRED: 3236 return g_strdup("required"); 3237 } 3238 g_assert_not_reached(); 3239 } 3240 3241 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3242 { 3243 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3244 3245 if (strcmp(value, "default") == 0) { 3246 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3247 } else if (strcmp(value, "disabled") == 0) { 3248 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3249 } else if (strcmp(value, "enabled") == 0) { 3250 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3251 } else if (strcmp(value, "required") == 0) { 3252 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3253 } else { 3254 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3255 } 3256 } 3257 3258 static bool spapr_get_vof(Object *obj, Error **errp) 3259 { 3260 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3261 3262 return spapr->vof != NULL; 3263 } 3264 3265 static void spapr_set_vof(Object *obj, bool value, Error **errp) 3266 { 3267 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3268 3269 if (spapr->vof) { 3270 vof_cleanup(spapr->vof); 3271 g_free(spapr->vof); 3272 spapr->vof = NULL; 3273 } 3274 if (!value) { 3275 return; 3276 } 3277 spapr->vof = g_malloc0(sizeof(*spapr->vof)); 3278 } 3279 3280 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3281 { 3282 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3283 3284 if (spapr->irq == &spapr_irq_xics_legacy) { 3285 return g_strdup("legacy"); 3286 } else if (spapr->irq == &spapr_irq_xics) { 3287 return g_strdup("xics"); 3288 } else if (spapr->irq == &spapr_irq_xive) { 3289 return g_strdup("xive"); 3290 } else if (spapr->irq == &spapr_irq_dual) { 3291 return g_strdup("dual"); 3292 } 3293 g_assert_not_reached(); 3294 } 3295 3296 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3297 { 3298 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3299 3300 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3301 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3302 return; 3303 } 3304 3305 /* The legacy IRQ backend can not be set */ 3306 if (strcmp(value, "xics") == 0) { 3307 spapr->irq = &spapr_irq_xics; 3308 } else if (strcmp(value, "xive") == 0) { 3309 spapr->irq = &spapr_irq_xive; 3310 } else if (strcmp(value, "dual") == 0) { 3311 spapr->irq = &spapr_irq_dual; 3312 } else { 3313 error_setg(errp, "Bad value for \"ic-mode\" property"); 3314 } 3315 } 3316 3317 static char *spapr_get_host_model(Object *obj, Error **errp) 3318 { 3319 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3320 3321 return g_strdup(spapr->host_model); 3322 } 3323 3324 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3325 { 3326 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3327 3328 g_free(spapr->host_model); 3329 spapr->host_model = g_strdup(value); 3330 } 3331 3332 static char *spapr_get_host_serial(Object *obj, Error **errp) 3333 { 3334 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3335 3336 return g_strdup(spapr->host_serial); 3337 } 3338 3339 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3340 { 3341 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3342 3343 g_free(spapr->host_serial); 3344 spapr->host_serial = g_strdup(value); 3345 } 3346 3347 static void spapr_instance_init(Object *obj) 3348 { 3349 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3350 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3351 MachineState *ms = MACHINE(spapr); 3352 MachineClass *mc = MACHINE_GET_CLASS(ms); 3353 3354 /* 3355 * NVDIMM support went live in 5.1 without considering that, in 3356 * other archs, the user needs to enable NVDIMM support with the 3357 * 'nvdimm' machine option and the default behavior is NVDIMM 3358 * support disabled. It is too late to roll back to the standard 3359 * behavior without breaking 5.1 guests. 3360 */ 3361 if (mc->nvdimm_supported) { 3362 ms->nvdimms_state->is_enabled = true; 3363 } 3364 3365 spapr->htab_fd = -1; 3366 spapr->use_hotplug_event_source = true; 3367 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE); 3368 object_property_add_str(obj, "kvm-type", 3369 spapr_get_kvm_type, spapr_set_kvm_type); 3370 object_property_set_description(obj, "kvm-type", 3371 "Specifies the KVM virtualization mode (auto," 3372 " hv, pr). Defaults to 'auto'. This mode will use" 3373 " any available KVM module loaded in the host," 3374 " where kvm_hv takes precedence if both kvm_hv and" 3375 " kvm_pr are loaded."); 3376 object_property_add_bool(obj, "modern-hotplug-events", 3377 spapr_get_modern_hotplug_events, 3378 spapr_set_modern_hotplug_events); 3379 object_property_set_description(obj, "modern-hotplug-events", 3380 "Use dedicated hotplug event mechanism in" 3381 " place of standard EPOW events when possible" 3382 " (required for memory hot-unplug support)"); 3383 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3384 "Maximum permitted CPU compatibility mode"); 3385 3386 object_property_add_str(obj, "resize-hpt", 3387 spapr_get_resize_hpt, spapr_set_resize_hpt); 3388 object_property_set_description(obj, "resize-hpt", 3389 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3390 object_property_add_uint32_ptr(obj, "vsmt", 3391 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3392 object_property_set_description(obj, "vsmt", 3393 "Virtual SMT: KVM behaves as if this were" 3394 " the host's SMT mode"); 3395 3396 object_property_add_bool(obj, "vfio-no-msix-emulation", 3397 spapr_get_msix_emulation, NULL); 3398 3399 object_property_add_uint64_ptr(obj, "kernel-addr", 3400 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3401 object_property_set_description(obj, "kernel-addr", 3402 stringify(KERNEL_LOAD_ADDR) 3403 " for -kernel is the default"); 3404 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3405 3406 object_property_add_bool(obj, "x-vof", spapr_get_vof, spapr_set_vof); 3407 object_property_set_description(obj, "x-vof", 3408 "Enable Virtual Open Firmware (experimental)"); 3409 3410 /* The machine class defines the default interrupt controller mode */ 3411 spapr->irq = smc->irq; 3412 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3413 spapr_set_ic_mode); 3414 object_property_set_description(obj, "ic-mode", 3415 "Specifies the interrupt controller mode (xics, xive, dual)"); 3416 3417 object_property_add_str(obj, "host-model", 3418 spapr_get_host_model, spapr_set_host_model); 3419 object_property_set_description(obj, "host-model", 3420 "Host model to advertise in guest device tree"); 3421 object_property_add_str(obj, "host-serial", 3422 spapr_get_host_serial, spapr_set_host_serial); 3423 object_property_set_description(obj, "host-serial", 3424 "Host serial number to advertise in guest device tree"); 3425 } 3426 3427 static void spapr_machine_finalizefn(Object *obj) 3428 { 3429 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3430 3431 g_free(spapr->kvm_type); 3432 } 3433 3434 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3435 { 3436 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3437 PowerPCCPU *cpu = POWERPC_CPU(cs); 3438 CPUPPCState *env = &cpu->env; 3439 3440 cpu_synchronize_state(cs); 3441 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3442 if (spapr->fwnmi_system_reset_addr != -1) { 3443 uint64_t rtas_addr, addr; 3444 3445 /* get rtas addr from fdt */ 3446 rtas_addr = spapr_get_rtas_addr(); 3447 if (!rtas_addr) { 3448 qemu_system_guest_panicked(NULL); 3449 return; 3450 } 3451 3452 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3453 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3454 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3455 env->gpr[3] = addr; 3456 } 3457 ppc_cpu_do_system_reset(cs); 3458 if (spapr->fwnmi_system_reset_addr != -1) { 3459 env->nip = spapr->fwnmi_system_reset_addr; 3460 } 3461 } 3462 3463 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3464 { 3465 CPUState *cs; 3466 3467 CPU_FOREACH(cs) { 3468 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3469 } 3470 } 3471 3472 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3473 void *fdt, int *fdt_start_offset, Error **errp) 3474 { 3475 uint64_t addr; 3476 uint32_t node; 3477 3478 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3479 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3480 &error_abort); 3481 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3482 SPAPR_MEMORY_BLOCK_SIZE); 3483 return 0; 3484 } 3485 3486 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3487 bool dedicated_hp_event_source) 3488 { 3489 SpaprDrc *drc; 3490 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3491 int i; 3492 uint64_t addr = addr_start; 3493 bool hotplugged = spapr_drc_hotplugged(dev); 3494 3495 for (i = 0; i < nr_lmbs; i++) { 3496 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3497 addr / SPAPR_MEMORY_BLOCK_SIZE); 3498 g_assert(drc); 3499 3500 /* 3501 * memory_device_get_free_addr() provided a range of free addresses 3502 * that doesn't overlap with any existing mapping at pre-plug. The 3503 * corresponding LMB DRCs are thus assumed to be all attachable. 3504 */ 3505 spapr_drc_attach(drc, dev); 3506 if (!hotplugged) { 3507 spapr_drc_reset(drc); 3508 } 3509 addr += SPAPR_MEMORY_BLOCK_SIZE; 3510 } 3511 /* send hotplug notification to the 3512 * guest only in case of hotplugged memory 3513 */ 3514 if (hotplugged) { 3515 if (dedicated_hp_event_source) { 3516 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3517 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3518 g_assert(drc); 3519 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3520 nr_lmbs, 3521 spapr_drc_index(drc)); 3522 } else { 3523 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3524 nr_lmbs); 3525 } 3526 } 3527 } 3528 3529 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3530 { 3531 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3532 PCDIMMDevice *dimm = PC_DIMM(dev); 3533 uint64_t size, addr; 3534 int64_t slot; 3535 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3536 3537 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3538 3539 pc_dimm_plug(dimm, MACHINE(ms)); 3540 3541 if (!is_nvdimm) { 3542 addr = object_property_get_uint(OBJECT(dimm), 3543 PC_DIMM_ADDR_PROP, &error_abort); 3544 spapr_add_lmbs(dev, addr, size, 3545 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT)); 3546 } else { 3547 slot = object_property_get_int(OBJECT(dimm), 3548 PC_DIMM_SLOT_PROP, &error_abort); 3549 /* We should have valid slot number at this point */ 3550 g_assert(slot >= 0); 3551 spapr_add_nvdimm(dev, slot); 3552 } 3553 } 3554 3555 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3556 Error **errp) 3557 { 3558 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3559 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3560 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3561 PCDIMMDevice *dimm = PC_DIMM(dev); 3562 Error *local_err = NULL; 3563 uint64_t size; 3564 Object *memdev; 3565 hwaddr pagesize; 3566 3567 if (!smc->dr_lmb_enabled) { 3568 error_setg(errp, "Memory hotplug not supported for this machine"); 3569 return; 3570 } 3571 3572 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3573 if (local_err) { 3574 error_propagate(errp, local_err); 3575 return; 3576 } 3577 3578 if (is_nvdimm) { 3579 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3580 return; 3581 } 3582 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3583 error_setg(errp, "Hotplugged memory size must be a multiple of " 3584 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3585 return; 3586 } 3587 3588 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3589 &error_abort); 3590 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3591 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3592 return; 3593 } 3594 3595 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3596 } 3597 3598 struct SpaprDimmState { 3599 PCDIMMDevice *dimm; 3600 uint32_t nr_lmbs; 3601 QTAILQ_ENTRY(SpaprDimmState) next; 3602 }; 3603 3604 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3605 PCDIMMDevice *dimm) 3606 { 3607 SpaprDimmState *dimm_state = NULL; 3608 3609 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3610 if (dimm_state->dimm == dimm) { 3611 break; 3612 } 3613 } 3614 return dimm_state; 3615 } 3616 3617 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3618 uint32_t nr_lmbs, 3619 PCDIMMDevice *dimm) 3620 { 3621 SpaprDimmState *ds = NULL; 3622 3623 /* 3624 * If this request is for a DIMM whose removal had failed earlier 3625 * (due to guest's refusal to remove the LMBs), we would have this 3626 * dimm already in the pending_dimm_unplugs list. In that 3627 * case don't add again. 3628 */ 3629 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3630 if (!ds) { 3631 ds = g_new0(SpaprDimmState, 1); 3632 ds->nr_lmbs = nr_lmbs; 3633 ds->dimm = dimm; 3634 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3635 } 3636 return ds; 3637 } 3638 3639 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3640 SpaprDimmState *dimm_state) 3641 { 3642 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3643 g_free(dimm_state); 3644 } 3645 3646 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3647 PCDIMMDevice *dimm) 3648 { 3649 SpaprDrc *drc; 3650 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3651 &error_abort); 3652 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3653 uint32_t avail_lmbs = 0; 3654 uint64_t addr_start, addr; 3655 int i; 3656 3657 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3658 &error_abort); 3659 3660 addr = addr_start; 3661 for (i = 0; i < nr_lmbs; i++) { 3662 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3663 addr / SPAPR_MEMORY_BLOCK_SIZE); 3664 g_assert(drc); 3665 if (drc->dev) { 3666 avail_lmbs++; 3667 } 3668 addr += SPAPR_MEMORY_BLOCK_SIZE; 3669 } 3670 3671 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3672 } 3673 3674 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev) 3675 { 3676 SpaprDimmState *ds; 3677 PCDIMMDevice *dimm; 3678 SpaprDrc *drc; 3679 uint32_t nr_lmbs; 3680 uint64_t size, addr_start, addr; 3681 g_autofree char *qapi_error = NULL; 3682 int i; 3683 3684 if (!dev) { 3685 return; 3686 } 3687 3688 dimm = PC_DIMM(dev); 3689 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3690 3691 /* 3692 * 'ds == NULL' would mean that the DIMM doesn't have a pending 3693 * unplug state, but one of its DRC is marked as unplug_requested. 3694 * This is bad and weird enough to g_assert() out. 3695 */ 3696 g_assert(ds); 3697 3698 spapr_pending_dimm_unplugs_remove(spapr, ds); 3699 3700 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3701 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3702 3703 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3704 &error_abort); 3705 3706 addr = addr_start; 3707 for (i = 0; i < nr_lmbs; i++) { 3708 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3709 addr / SPAPR_MEMORY_BLOCK_SIZE); 3710 g_assert(drc); 3711 3712 drc->unplug_requested = false; 3713 addr += SPAPR_MEMORY_BLOCK_SIZE; 3714 } 3715 3716 /* 3717 * Tell QAPI that something happened and the memory 3718 * hotunplug wasn't successful. Keep sending 3719 * MEM_UNPLUG_ERROR even while sending 3720 * DEVICE_UNPLUG_GUEST_ERROR until the deprecation of 3721 * MEM_UNPLUG_ERROR is due. 3722 */ 3723 qapi_error = g_strdup_printf("Memory hotunplug rejected by the guest " 3724 "for device %s", dev->id); 3725 3726 qapi_event_send_mem_unplug_error(dev->id ? : "", qapi_error); 3727 3728 qapi_event_send_device_unplug_guest_error(!!dev->id, dev->id, 3729 dev->canonical_path); 3730 } 3731 3732 /* Callback to be called during DRC release. */ 3733 void spapr_lmb_release(DeviceState *dev) 3734 { 3735 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3736 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3737 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3738 3739 /* This information will get lost if a migration occurs 3740 * during the unplug process. In this case recover it. */ 3741 if (ds == NULL) { 3742 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3743 g_assert(ds); 3744 /* The DRC being examined by the caller at least must be counted */ 3745 g_assert(ds->nr_lmbs); 3746 } 3747 3748 if (--ds->nr_lmbs) { 3749 return; 3750 } 3751 3752 /* 3753 * Now that all the LMBs have been removed by the guest, call the 3754 * unplug handler chain. This can never fail. 3755 */ 3756 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3757 object_unparent(OBJECT(dev)); 3758 } 3759 3760 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3761 { 3762 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3763 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3764 3765 /* We really shouldn't get this far without anything to unplug */ 3766 g_assert(ds); 3767 3768 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3769 qdev_unrealize(dev); 3770 spapr_pending_dimm_unplugs_remove(spapr, ds); 3771 } 3772 3773 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3774 DeviceState *dev, Error **errp) 3775 { 3776 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3777 PCDIMMDevice *dimm = PC_DIMM(dev); 3778 uint32_t nr_lmbs; 3779 uint64_t size, addr_start, addr; 3780 int i; 3781 SpaprDrc *drc; 3782 3783 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3784 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3785 return; 3786 } 3787 3788 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3789 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3790 3791 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3792 &error_abort); 3793 3794 /* 3795 * An existing pending dimm state for this DIMM means that there is an 3796 * unplug operation in progress, waiting for the spapr_lmb_release 3797 * callback to complete the job (BQL can't cover that far). In this case, 3798 * bail out to avoid detaching DRCs that were already released. 3799 */ 3800 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3801 error_setg(errp, "Memory unplug already in progress for device %s", 3802 dev->id); 3803 return; 3804 } 3805 3806 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3807 3808 addr = addr_start; 3809 for (i = 0; i < nr_lmbs; i++) { 3810 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3811 addr / SPAPR_MEMORY_BLOCK_SIZE); 3812 g_assert(drc); 3813 3814 spapr_drc_unplug_request(drc); 3815 addr += SPAPR_MEMORY_BLOCK_SIZE; 3816 } 3817 3818 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3819 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3820 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3821 nr_lmbs, spapr_drc_index(drc)); 3822 } 3823 3824 /* Callback to be called during DRC release. */ 3825 void spapr_core_release(DeviceState *dev) 3826 { 3827 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3828 3829 /* Call the unplug handler chain. This can never fail. */ 3830 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3831 object_unparent(OBJECT(dev)); 3832 } 3833 3834 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3835 { 3836 MachineState *ms = MACHINE(hotplug_dev); 3837 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3838 CPUCore *cc = CPU_CORE(dev); 3839 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3840 3841 if (smc->pre_2_10_has_unused_icps) { 3842 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3843 int i; 3844 3845 for (i = 0; i < cc->nr_threads; i++) { 3846 CPUState *cs = CPU(sc->threads[i]); 3847 3848 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3849 } 3850 } 3851 3852 assert(core_slot); 3853 core_slot->cpu = NULL; 3854 qdev_unrealize(dev); 3855 } 3856 3857 static 3858 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3859 Error **errp) 3860 { 3861 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3862 int index; 3863 SpaprDrc *drc; 3864 CPUCore *cc = CPU_CORE(dev); 3865 3866 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3867 error_setg(errp, "Unable to find CPU core with core-id: %d", 3868 cc->core_id); 3869 return; 3870 } 3871 if (index == 0) { 3872 error_setg(errp, "Boot CPU core may not be unplugged"); 3873 return; 3874 } 3875 3876 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3877 spapr_vcpu_id(spapr, cc->core_id)); 3878 g_assert(drc); 3879 3880 if (!spapr_drc_unplug_requested(drc)) { 3881 spapr_drc_unplug_request(drc); 3882 } 3883 3884 /* 3885 * spapr_hotplug_req_remove_by_index is left unguarded, out of the 3886 * "!spapr_drc_unplug_requested" check, to allow for multiple IRQ 3887 * pulses removing the same CPU. Otherwise, in an failed hotunplug 3888 * attempt (e.g. the kernel will refuse to remove the last online 3889 * CPU), we will never attempt it again because unplug_requested 3890 * will still be 'true' in that case. 3891 */ 3892 spapr_hotplug_req_remove_by_index(drc); 3893 } 3894 3895 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3896 void *fdt, int *fdt_start_offset, Error **errp) 3897 { 3898 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3899 CPUState *cs = CPU(core->threads[0]); 3900 PowerPCCPU *cpu = POWERPC_CPU(cs); 3901 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3902 int id = spapr_get_vcpu_id(cpu); 3903 g_autofree char *nodename = NULL; 3904 int offset; 3905 3906 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3907 offset = fdt_add_subnode(fdt, 0, nodename); 3908 3909 spapr_dt_cpu(cs, fdt, offset, spapr); 3910 3911 /* 3912 * spapr_dt_cpu() does not fill the 'name' property in the 3913 * CPU node. The function is called during boot process, before 3914 * and after CAS, and overwriting the 'name' property written 3915 * by SLOF is not allowed. 3916 * 3917 * Write it manually after spapr_dt_cpu(). This makes the hotplug 3918 * CPUs more compatible with the coldplugged ones, which have 3919 * the 'name' property. Linux Kernel also relies on this 3920 * property to identify CPU nodes. 3921 */ 3922 _FDT((fdt_setprop_string(fdt, offset, "name", nodename))); 3923 3924 *fdt_start_offset = offset; 3925 return 0; 3926 } 3927 3928 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3929 { 3930 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3931 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3932 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3933 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3934 CPUCore *cc = CPU_CORE(dev); 3935 CPUState *cs; 3936 SpaprDrc *drc; 3937 CPUArchId *core_slot; 3938 int index; 3939 bool hotplugged = spapr_drc_hotplugged(dev); 3940 int i; 3941 3942 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3943 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */ 3944 3945 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3946 spapr_vcpu_id(spapr, cc->core_id)); 3947 3948 g_assert(drc || !mc->has_hotpluggable_cpus); 3949 3950 if (drc) { 3951 /* 3952 * spapr_core_pre_plug() already buys us this is a brand new 3953 * core being plugged into a free slot. Nothing should already 3954 * be attached to the corresponding DRC. 3955 */ 3956 spapr_drc_attach(drc, dev); 3957 3958 if (hotplugged) { 3959 /* 3960 * Send hotplug notification interrupt to the guest only 3961 * in case of hotplugged CPUs. 3962 */ 3963 spapr_hotplug_req_add_by_index(drc); 3964 } else { 3965 spapr_drc_reset(drc); 3966 } 3967 } 3968 3969 core_slot->cpu = OBJECT(dev); 3970 3971 /* 3972 * Set compatibility mode to match the boot CPU, which was either set 3973 * by the machine reset code or by CAS. This really shouldn't fail at 3974 * this point. 3975 */ 3976 if (hotplugged) { 3977 for (i = 0; i < cc->nr_threads; i++) { 3978 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3979 &error_abort); 3980 } 3981 } 3982 3983 if (smc->pre_2_10_has_unused_icps) { 3984 for (i = 0; i < cc->nr_threads; i++) { 3985 cs = CPU(core->threads[i]); 3986 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3987 } 3988 } 3989 } 3990 3991 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3992 Error **errp) 3993 { 3994 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3995 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3996 CPUCore *cc = CPU_CORE(dev); 3997 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3998 const char *type = object_get_typename(OBJECT(dev)); 3999 CPUArchId *core_slot; 4000 int index; 4001 unsigned int smp_threads = machine->smp.threads; 4002 4003 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 4004 error_setg(errp, "CPU hotplug not supported for this machine"); 4005 return; 4006 } 4007 4008 if (strcmp(base_core_type, type)) { 4009 error_setg(errp, "CPU core type should be %s", base_core_type); 4010 return; 4011 } 4012 4013 if (cc->core_id % smp_threads) { 4014 error_setg(errp, "invalid core id %d", cc->core_id); 4015 return; 4016 } 4017 4018 /* 4019 * In general we should have homogeneous threads-per-core, but old 4020 * (pre hotplug support) machine types allow the last core to have 4021 * reduced threads as a compatibility hack for when we allowed 4022 * total vcpus not a multiple of threads-per-core. 4023 */ 4024 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 4025 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 4026 smp_threads); 4027 return; 4028 } 4029 4030 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 4031 if (!core_slot) { 4032 error_setg(errp, "core id %d out of range", cc->core_id); 4033 return; 4034 } 4035 4036 if (core_slot->cpu) { 4037 error_setg(errp, "core %d already populated", cc->core_id); 4038 return; 4039 } 4040 4041 numa_cpu_pre_plug(core_slot, dev, errp); 4042 } 4043 4044 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 4045 void *fdt, int *fdt_start_offset, Error **errp) 4046 { 4047 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 4048 int intc_phandle; 4049 4050 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 4051 if (intc_phandle <= 0) { 4052 return -1; 4053 } 4054 4055 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 4056 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 4057 return -1; 4058 } 4059 4060 /* generally SLOF creates these, for hotplug it's up to QEMU */ 4061 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 4062 4063 return 0; 4064 } 4065 4066 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4067 Error **errp) 4068 { 4069 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4070 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4071 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4072 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 4073 SpaprDrc *drc; 4074 4075 if (dev->hotplugged && !smc->dr_phb_enabled) { 4076 error_setg(errp, "PHB hotplug not supported for this machine"); 4077 return false; 4078 } 4079 4080 if (sphb->index == (uint32_t)-1) { 4081 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 4082 return false; 4083 } 4084 4085 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4086 if (drc && drc->dev) { 4087 error_setg(errp, "PHB %d already attached", sphb->index); 4088 return false; 4089 } 4090 4091 /* 4092 * This will check that sphb->index doesn't exceed the maximum number of 4093 * PHBs for the current machine type. 4094 */ 4095 return 4096 smc->phb_placement(spapr, sphb->index, 4097 &sphb->buid, &sphb->io_win_addr, 4098 &sphb->mem_win_addr, &sphb->mem64_win_addr, 4099 windows_supported, sphb->dma_liobn, 4100 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 4101 errp); 4102 } 4103 4104 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4105 { 4106 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4107 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4108 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4109 SpaprDrc *drc; 4110 bool hotplugged = spapr_drc_hotplugged(dev); 4111 4112 if (!smc->dr_phb_enabled) { 4113 return; 4114 } 4115 4116 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4117 /* hotplug hooks should check it's enabled before getting this far */ 4118 assert(drc); 4119 4120 /* spapr_phb_pre_plug() already checked the DRC is attachable */ 4121 spapr_drc_attach(drc, dev); 4122 4123 if (hotplugged) { 4124 spapr_hotplug_req_add_by_index(drc); 4125 } else { 4126 spapr_drc_reset(drc); 4127 } 4128 } 4129 4130 void spapr_phb_release(DeviceState *dev) 4131 { 4132 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4133 4134 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4135 object_unparent(OBJECT(dev)); 4136 } 4137 4138 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4139 { 4140 qdev_unrealize(dev); 4141 } 4142 4143 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4144 DeviceState *dev, Error **errp) 4145 { 4146 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4147 SpaprDrc *drc; 4148 4149 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4150 assert(drc); 4151 4152 if (!spapr_drc_unplug_requested(drc)) { 4153 spapr_drc_unplug_request(drc); 4154 spapr_hotplug_req_remove_by_index(drc); 4155 } else { 4156 error_setg(errp, 4157 "PCI Host Bridge unplug already in progress for device %s", 4158 dev->id); 4159 } 4160 } 4161 4162 static 4163 bool spapr_tpm_proxy_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4164 Error **errp) 4165 { 4166 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4167 4168 if (spapr->tpm_proxy != NULL) { 4169 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4170 return false; 4171 } 4172 4173 return true; 4174 } 4175 4176 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4177 { 4178 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4179 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4180 4181 /* Already checked in spapr_tpm_proxy_pre_plug() */ 4182 g_assert(spapr->tpm_proxy == NULL); 4183 4184 spapr->tpm_proxy = tpm_proxy; 4185 } 4186 4187 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4188 { 4189 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4190 4191 qdev_unrealize(dev); 4192 object_unparent(OBJECT(dev)); 4193 spapr->tpm_proxy = NULL; 4194 } 4195 4196 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4197 DeviceState *dev, Error **errp) 4198 { 4199 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4200 spapr_memory_plug(hotplug_dev, dev); 4201 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4202 spapr_core_plug(hotplug_dev, dev); 4203 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4204 spapr_phb_plug(hotplug_dev, dev); 4205 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4206 spapr_tpm_proxy_plug(hotplug_dev, dev); 4207 } 4208 } 4209 4210 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4211 DeviceState *dev, Error **errp) 4212 { 4213 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4214 spapr_memory_unplug(hotplug_dev, dev); 4215 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4216 spapr_core_unplug(hotplug_dev, dev); 4217 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4218 spapr_phb_unplug(hotplug_dev, dev); 4219 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4220 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4221 } 4222 } 4223 4224 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr) 4225 { 4226 return spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT) || 4227 /* 4228 * CAS will process all pending unplug requests. 4229 * 4230 * HACK: a guest could theoretically have cleared all bits in OV5, 4231 * but none of the guests we care for do. 4232 */ 4233 spapr_ovec_empty(spapr->ov5_cas); 4234 } 4235 4236 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4237 DeviceState *dev, Error **errp) 4238 { 4239 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4240 MachineClass *mc = MACHINE_GET_CLASS(sms); 4241 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4242 4243 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4244 if (spapr_memory_hot_unplug_supported(sms)) { 4245 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4246 } else { 4247 error_setg(errp, "Memory hot unplug not supported for this guest"); 4248 } 4249 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4250 if (!mc->has_hotpluggable_cpus) { 4251 error_setg(errp, "CPU hot unplug not supported on this machine"); 4252 return; 4253 } 4254 spapr_core_unplug_request(hotplug_dev, dev, errp); 4255 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4256 if (!smc->dr_phb_enabled) { 4257 error_setg(errp, "PHB hot unplug not supported on this machine"); 4258 return; 4259 } 4260 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4261 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4262 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4263 } 4264 } 4265 4266 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4267 DeviceState *dev, Error **errp) 4268 { 4269 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4270 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4271 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4272 spapr_core_pre_plug(hotplug_dev, dev, errp); 4273 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4274 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4275 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4276 spapr_tpm_proxy_pre_plug(hotplug_dev, dev, errp); 4277 } 4278 } 4279 4280 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4281 DeviceState *dev) 4282 { 4283 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4284 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4285 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4286 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4287 return HOTPLUG_HANDLER(machine); 4288 } 4289 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4290 PCIDevice *pcidev = PCI_DEVICE(dev); 4291 PCIBus *root = pci_device_root_bus(pcidev); 4292 SpaprPhbState *phb = 4293 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4294 TYPE_SPAPR_PCI_HOST_BRIDGE); 4295 4296 if (phb) { 4297 return HOTPLUG_HANDLER(phb); 4298 } 4299 } 4300 return NULL; 4301 } 4302 4303 static CpuInstanceProperties 4304 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4305 { 4306 CPUArchId *core_slot; 4307 MachineClass *mc = MACHINE_GET_CLASS(machine); 4308 4309 /* make sure possible_cpu are intialized */ 4310 mc->possible_cpu_arch_ids(machine); 4311 /* get CPU core slot containing thread that matches cpu_index */ 4312 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4313 assert(core_slot); 4314 return core_slot->props; 4315 } 4316 4317 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4318 { 4319 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4320 } 4321 4322 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4323 { 4324 int i; 4325 unsigned int smp_threads = machine->smp.threads; 4326 unsigned int smp_cpus = machine->smp.cpus; 4327 const char *core_type; 4328 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4329 MachineClass *mc = MACHINE_GET_CLASS(machine); 4330 4331 if (!mc->has_hotpluggable_cpus) { 4332 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4333 } 4334 if (machine->possible_cpus) { 4335 assert(machine->possible_cpus->len == spapr_max_cores); 4336 return machine->possible_cpus; 4337 } 4338 4339 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4340 if (!core_type) { 4341 error_report("Unable to find sPAPR CPU Core definition"); 4342 exit(1); 4343 } 4344 4345 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4346 sizeof(CPUArchId) * spapr_max_cores); 4347 machine->possible_cpus->len = spapr_max_cores; 4348 for (i = 0; i < machine->possible_cpus->len; i++) { 4349 int core_id = i * smp_threads; 4350 4351 machine->possible_cpus->cpus[i].type = core_type; 4352 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4353 machine->possible_cpus->cpus[i].arch_id = core_id; 4354 machine->possible_cpus->cpus[i].props.has_core_id = true; 4355 machine->possible_cpus->cpus[i].props.core_id = core_id; 4356 } 4357 return machine->possible_cpus; 4358 } 4359 4360 static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4361 uint64_t *buid, hwaddr *pio, 4362 hwaddr *mmio32, hwaddr *mmio64, 4363 unsigned n_dma, uint32_t *liobns, 4364 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4365 { 4366 /* 4367 * New-style PHB window placement. 4368 * 4369 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4370 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4371 * windows. 4372 * 4373 * Some guest kernels can't work with MMIO windows above 1<<46 4374 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4375 * 4376 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4377 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4378 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4379 * 1TiB 64-bit MMIO windows for each PHB. 4380 */ 4381 const uint64_t base_buid = 0x800000020000000ULL; 4382 int i; 4383 4384 /* Sanity check natural alignments */ 4385 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4386 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4387 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4388 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4389 /* Sanity check bounds */ 4390 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4391 SPAPR_PCI_MEM32_WIN_SIZE); 4392 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4393 SPAPR_PCI_MEM64_WIN_SIZE); 4394 4395 if (index >= SPAPR_MAX_PHBS) { 4396 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4397 SPAPR_MAX_PHBS - 1); 4398 return false; 4399 } 4400 4401 *buid = base_buid + index; 4402 for (i = 0; i < n_dma; ++i) { 4403 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4404 } 4405 4406 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4407 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4408 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4409 4410 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4411 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4412 return true; 4413 } 4414 4415 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4416 { 4417 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4418 4419 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4420 } 4421 4422 static void spapr_ics_resend(XICSFabric *dev) 4423 { 4424 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4425 4426 ics_resend(spapr->ics); 4427 } 4428 4429 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4430 { 4431 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4432 4433 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4434 } 4435 4436 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4437 Monitor *mon) 4438 { 4439 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4440 4441 spapr_irq_print_info(spapr, mon); 4442 monitor_printf(mon, "irqchip: %s\n", 4443 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4444 } 4445 4446 /* 4447 * This is a XIVE only operation 4448 */ 4449 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4450 uint8_t nvt_blk, uint32_t nvt_idx, 4451 bool cam_ignore, uint8_t priority, 4452 uint32_t logic_serv, XiveTCTXMatch *match) 4453 { 4454 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4455 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4456 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4457 int count; 4458 4459 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4460 priority, logic_serv, match); 4461 if (count < 0) { 4462 return count; 4463 } 4464 4465 /* 4466 * When we implement the save and restore of the thread interrupt 4467 * contexts in the enter/exit CPU handlers of the machine and the 4468 * escalations in QEMU, we should be able to handle non dispatched 4469 * vCPUs. 4470 * 4471 * Until this is done, the sPAPR machine should find at least one 4472 * matching context always. 4473 */ 4474 if (count == 0) { 4475 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4476 nvt_blk, nvt_idx); 4477 } 4478 4479 return count; 4480 } 4481 4482 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4483 { 4484 return cpu->vcpu_id; 4485 } 4486 4487 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4488 { 4489 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4490 MachineState *ms = MACHINE(spapr); 4491 int vcpu_id; 4492 4493 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4494 4495 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4496 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4497 error_append_hint(errp, "Adjust the number of cpus to %d " 4498 "or try to raise the number of threads per core\n", 4499 vcpu_id * ms->smp.threads / spapr->vsmt); 4500 return false; 4501 } 4502 4503 cpu->vcpu_id = vcpu_id; 4504 return true; 4505 } 4506 4507 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4508 { 4509 CPUState *cs; 4510 4511 CPU_FOREACH(cs) { 4512 PowerPCCPU *cpu = POWERPC_CPU(cs); 4513 4514 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4515 return cpu; 4516 } 4517 } 4518 4519 return NULL; 4520 } 4521 4522 static bool spapr_cpu_in_nested(PowerPCCPU *cpu) 4523 { 4524 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4525 4526 return spapr_cpu->in_nested; 4527 } 4528 4529 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4530 { 4531 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4532 4533 /* These are only called by TCG, KVM maintains dispatch state */ 4534 4535 spapr_cpu->prod = false; 4536 if (spapr_cpu->vpa_addr) { 4537 CPUState *cs = CPU(cpu); 4538 uint32_t dispatch; 4539 4540 dispatch = ldl_be_phys(cs->as, 4541 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4542 dispatch++; 4543 if ((dispatch & 1) != 0) { 4544 qemu_log_mask(LOG_GUEST_ERROR, 4545 "VPA: incorrect dispatch counter value for " 4546 "dispatched partition %u, correcting.\n", dispatch); 4547 dispatch++; 4548 } 4549 stl_be_phys(cs->as, 4550 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4551 } 4552 } 4553 4554 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4555 { 4556 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4557 4558 if (spapr_cpu->vpa_addr) { 4559 CPUState *cs = CPU(cpu); 4560 uint32_t dispatch; 4561 4562 dispatch = ldl_be_phys(cs->as, 4563 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4564 dispatch++; 4565 if ((dispatch & 1) != 1) { 4566 qemu_log_mask(LOG_GUEST_ERROR, 4567 "VPA: incorrect dispatch counter value for " 4568 "preempted partition %u, correcting.\n", dispatch); 4569 dispatch++; 4570 } 4571 stl_be_phys(cs->as, 4572 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4573 } 4574 } 4575 4576 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4577 { 4578 MachineClass *mc = MACHINE_CLASS(oc); 4579 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4580 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4581 NMIClass *nc = NMI_CLASS(oc); 4582 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4583 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4584 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4585 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4586 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4587 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc); 4588 4589 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4590 mc->ignore_boot_device_suffixes = true; 4591 4592 /* 4593 * We set up the default / latest behaviour here. The class_init 4594 * functions for the specific versioned machine types can override 4595 * these details for backwards compatibility 4596 */ 4597 mc->init = spapr_machine_init; 4598 mc->reset = spapr_machine_reset; 4599 mc->block_default_type = IF_SCSI; 4600 4601 /* 4602 * Setting max_cpus to INT32_MAX. Both KVM and TCG max_cpus values 4603 * should be limited by the host capability instead of hardcoded. 4604 * max_cpus for KVM guests will be checked in kvm_init(), and TCG 4605 * guests are welcome to have as many CPUs as the host are capable 4606 * of emulate. 4607 */ 4608 mc->max_cpus = INT32_MAX; 4609 4610 mc->no_parallel = 1; 4611 mc->default_boot_order = ""; 4612 mc->default_ram_size = 512 * MiB; 4613 mc->default_ram_id = "ppc_spapr.ram"; 4614 mc->default_display = "std"; 4615 mc->kvm_type = spapr_kvm_type; 4616 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4617 mc->pci_allow_0_address = true; 4618 assert(!mc->get_hotplug_handler); 4619 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4620 hc->pre_plug = spapr_machine_device_pre_plug; 4621 hc->plug = spapr_machine_device_plug; 4622 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4623 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4624 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4625 hc->unplug_request = spapr_machine_device_unplug_request; 4626 hc->unplug = spapr_machine_device_unplug; 4627 4628 smc->dr_lmb_enabled = true; 4629 smc->update_dt_enabled = true; 4630 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4631 mc->has_hotpluggable_cpus = true; 4632 mc->nvdimm_supported = true; 4633 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4634 fwc->get_dev_path = spapr_get_fw_dev_path; 4635 nc->nmi_monitor_handler = spapr_nmi; 4636 smc->phb_placement = spapr_phb_placement; 4637 vhc->cpu_in_nested = spapr_cpu_in_nested; 4638 vhc->deliver_hv_excp = spapr_exit_nested; 4639 vhc->hypercall = emulate_spapr_hypercall; 4640 vhc->hpt_mask = spapr_hpt_mask; 4641 vhc->map_hptes = spapr_map_hptes; 4642 vhc->unmap_hptes = spapr_unmap_hptes; 4643 vhc->hpte_set_c = spapr_hpte_set_c; 4644 vhc->hpte_set_r = spapr_hpte_set_r; 4645 vhc->get_pate = spapr_get_pate; 4646 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4647 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4648 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4649 xic->ics_get = spapr_ics_get; 4650 xic->ics_resend = spapr_ics_resend; 4651 xic->icp_get = spapr_icp_get; 4652 ispc->print_info = spapr_pic_print_info; 4653 /* Force NUMA node memory size to be a multiple of 4654 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4655 * in which LMBs are represented and hot-added 4656 */ 4657 mc->numa_mem_align_shift = 28; 4658 mc->auto_enable_numa = true; 4659 4660 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4661 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4662 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4663 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4664 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4665 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4666 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4667 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4668 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4669 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4670 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4671 smc->default_caps.caps[SPAPR_CAP_RPT_INVALIDATE] = SPAPR_CAP_OFF; 4672 spapr_caps_add_properties(smc); 4673 smc->irq = &spapr_irq_dual; 4674 smc->dr_phb_enabled = true; 4675 smc->linux_pci_probe = true; 4676 smc->smp_threads_vsmt = true; 4677 smc->nr_xirqs = SPAPR_NR_XIRQS; 4678 xfc->match_nvt = spapr_match_nvt; 4679 vmc->client_architecture_support = spapr_vof_client_architecture_support; 4680 vmc->quiesce = spapr_vof_quiesce; 4681 vmc->setprop = spapr_vof_setprop; 4682 } 4683 4684 static const TypeInfo spapr_machine_info = { 4685 .name = TYPE_SPAPR_MACHINE, 4686 .parent = TYPE_MACHINE, 4687 .abstract = true, 4688 .instance_size = sizeof(SpaprMachineState), 4689 .instance_init = spapr_instance_init, 4690 .instance_finalize = spapr_machine_finalizefn, 4691 .class_size = sizeof(SpaprMachineClass), 4692 .class_init = spapr_machine_class_init, 4693 .interfaces = (InterfaceInfo[]) { 4694 { TYPE_FW_PATH_PROVIDER }, 4695 { TYPE_NMI }, 4696 { TYPE_HOTPLUG_HANDLER }, 4697 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4698 { TYPE_XICS_FABRIC }, 4699 { TYPE_INTERRUPT_STATS_PROVIDER }, 4700 { TYPE_XIVE_FABRIC }, 4701 { TYPE_VOF_MACHINE_IF }, 4702 { } 4703 }, 4704 }; 4705 4706 static void spapr_machine_latest_class_options(MachineClass *mc) 4707 { 4708 mc->alias = "pseries"; 4709 mc->is_default = true; 4710 } 4711 4712 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4713 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4714 void *data) \ 4715 { \ 4716 MachineClass *mc = MACHINE_CLASS(oc); \ 4717 spapr_machine_##suffix##_class_options(mc); \ 4718 if (latest) { \ 4719 spapr_machine_latest_class_options(mc); \ 4720 } \ 4721 } \ 4722 static const TypeInfo spapr_machine_##suffix##_info = { \ 4723 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4724 .parent = TYPE_SPAPR_MACHINE, \ 4725 .class_init = spapr_machine_##suffix##_class_init, \ 4726 }; \ 4727 static void spapr_machine_register_##suffix(void) \ 4728 { \ 4729 type_register(&spapr_machine_##suffix##_info); \ 4730 } \ 4731 type_init(spapr_machine_register_##suffix) 4732 4733 /* 4734 * pseries-7.2 4735 */ 4736 static void spapr_machine_7_2_class_options(MachineClass *mc) 4737 { 4738 /* Defaults for the latest behaviour inherited from the base class */ 4739 } 4740 4741 DEFINE_SPAPR_MACHINE(7_2, "7.2", true); 4742 4743 /* 4744 * pseries-7.1 4745 */ 4746 static void spapr_machine_7_1_class_options(MachineClass *mc) 4747 { 4748 spapr_machine_7_2_class_options(mc); 4749 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 4750 } 4751 4752 DEFINE_SPAPR_MACHINE(7_1, "7.1", false); 4753 4754 /* 4755 * pseries-7.0 4756 */ 4757 static void spapr_machine_7_0_class_options(MachineClass *mc) 4758 { 4759 spapr_machine_7_1_class_options(mc); 4760 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 4761 } 4762 4763 DEFINE_SPAPR_MACHINE(7_0, "7.0", false); 4764 4765 /* 4766 * pseries-6.2 4767 */ 4768 static void spapr_machine_6_2_class_options(MachineClass *mc) 4769 { 4770 spapr_machine_7_0_class_options(mc); 4771 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 4772 } 4773 4774 DEFINE_SPAPR_MACHINE(6_2, "6.2", false); 4775 4776 /* 4777 * pseries-6.1 4778 */ 4779 static void spapr_machine_6_1_class_options(MachineClass *mc) 4780 { 4781 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4782 4783 spapr_machine_6_2_class_options(mc); 4784 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 4785 smc->pre_6_2_numa_affinity = true; 4786 mc->smp_props.prefer_sockets = true; 4787 } 4788 4789 DEFINE_SPAPR_MACHINE(6_1, "6.1", false); 4790 4791 /* 4792 * pseries-6.0 4793 */ 4794 static void spapr_machine_6_0_class_options(MachineClass *mc) 4795 { 4796 spapr_machine_6_1_class_options(mc); 4797 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 4798 } 4799 4800 DEFINE_SPAPR_MACHINE(6_0, "6.0", false); 4801 4802 /* 4803 * pseries-5.2 4804 */ 4805 static void spapr_machine_5_2_class_options(MachineClass *mc) 4806 { 4807 spapr_machine_6_0_class_options(mc); 4808 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 4809 } 4810 4811 DEFINE_SPAPR_MACHINE(5_2, "5.2", false); 4812 4813 /* 4814 * pseries-5.1 4815 */ 4816 static void spapr_machine_5_1_class_options(MachineClass *mc) 4817 { 4818 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4819 4820 spapr_machine_5_2_class_options(mc); 4821 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4822 smc->pre_5_2_numa_associativity = true; 4823 } 4824 4825 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4826 4827 /* 4828 * pseries-5.0 4829 */ 4830 static void spapr_machine_5_0_class_options(MachineClass *mc) 4831 { 4832 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4833 static GlobalProperty compat[] = { 4834 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4835 }; 4836 4837 spapr_machine_5_1_class_options(mc); 4838 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4839 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4840 mc->numa_mem_supported = true; 4841 smc->pre_5_1_assoc_refpoints = true; 4842 } 4843 4844 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4845 4846 /* 4847 * pseries-4.2 4848 */ 4849 static void spapr_machine_4_2_class_options(MachineClass *mc) 4850 { 4851 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4852 4853 spapr_machine_5_0_class_options(mc); 4854 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4855 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4856 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4857 smc->rma_limit = 16 * GiB; 4858 mc->nvdimm_supported = false; 4859 } 4860 4861 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4862 4863 /* 4864 * pseries-4.1 4865 */ 4866 static void spapr_machine_4_1_class_options(MachineClass *mc) 4867 { 4868 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4869 static GlobalProperty compat[] = { 4870 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4871 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4872 }; 4873 4874 spapr_machine_4_2_class_options(mc); 4875 smc->linux_pci_probe = false; 4876 smc->smp_threads_vsmt = false; 4877 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4878 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4879 } 4880 4881 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4882 4883 /* 4884 * pseries-4.0 4885 */ 4886 static bool phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4887 uint64_t *buid, hwaddr *pio, 4888 hwaddr *mmio32, hwaddr *mmio64, 4889 unsigned n_dma, uint32_t *liobns, 4890 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4891 { 4892 if (!spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, 4893 liobns, nv2gpa, nv2atsd, errp)) { 4894 return false; 4895 } 4896 4897 *nv2gpa = 0; 4898 *nv2atsd = 0; 4899 return true; 4900 } 4901 static void spapr_machine_4_0_class_options(MachineClass *mc) 4902 { 4903 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4904 4905 spapr_machine_4_1_class_options(mc); 4906 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4907 smc->phb_placement = phb_placement_4_0; 4908 smc->irq = &spapr_irq_xics; 4909 smc->pre_4_1_migration = true; 4910 } 4911 4912 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4913 4914 /* 4915 * pseries-3.1 4916 */ 4917 static void spapr_machine_3_1_class_options(MachineClass *mc) 4918 { 4919 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4920 4921 spapr_machine_4_0_class_options(mc); 4922 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4923 4924 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4925 smc->update_dt_enabled = false; 4926 smc->dr_phb_enabled = false; 4927 smc->broken_host_serial_model = true; 4928 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4929 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4930 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4931 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4932 } 4933 4934 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4935 4936 /* 4937 * pseries-3.0 4938 */ 4939 4940 static void spapr_machine_3_0_class_options(MachineClass *mc) 4941 { 4942 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4943 4944 spapr_machine_3_1_class_options(mc); 4945 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4946 4947 smc->legacy_irq_allocation = true; 4948 smc->nr_xirqs = 0x400; 4949 smc->irq = &spapr_irq_xics_legacy; 4950 } 4951 4952 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4953 4954 /* 4955 * pseries-2.12 4956 */ 4957 static void spapr_machine_2_12_class_options(MachineClass *mc) 4958 { 4959 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4960 static GlobalProperty compat[] = { 4961 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4962 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4963 }; 4964 4965 spapr_machine_3_0_class_options(mc); 4966 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4967 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4968 4969 /* We depend on kvm_enabled() to choose a default value for the 4970 * hpt-max-page-size capability. Of course we can't do it here 4971 * because this is too early and the HW accelerator isn't initialzed 4972 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4973 */ 4974 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4975 } 4976 4977 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4978 4979 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4980 { 4981 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4982 4983 spapr_machine_2_12_class_options(mc); 4984 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4985 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4986 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4987 } 4988 4989 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4990 4991 /* 4992 * pseries-2.11 4993 */ 4994 4995 static void spapr_machine_2_11_class_options(MachineClass *mc) 4996 { 4997 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4998 4999 spapr_machine_2_12_class_options(mc); 5000 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 5001 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 5002 } 5003 5004 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 5005 5006 /* 5007 * pseries-2.10 5008 */ 5009 5010 static void spapr_machine_2_10_class_options(MachineClass *mc) 5011 { 5012 spapr_machine_2_11_class_options(mc); 5013 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 5014 } 5015 5016 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 5017 5018 /* 5019 * pseries-2.9 5020 */ 5021 5022 static void spapr_machine_2_9_class_options(MachineClass *mc) 5023 { 5024 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5025 static GlobalProperty compat[] = { 5026 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 5027 }; 5028 5029 spapr_machine_2_10_class_options(mc); 5030 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 5031 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5032 smc->pre_2_10_has_unused_icps = true; 5033 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 5034 } 5035 5036 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 5037 5038 /* 5039 * pseries-2.8 5040 */ 5041 5042 static void spapr_machine_2_8_class_options(MachineClass *mc) 5043 { 5044 static GlobalProperty compat[] = { 5045 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 5046 }; 5047 5048 spapr_machine_2_9_class_options(mc); 5049 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 5050 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5051 mc->numa_mem_align_shift = 23; 5052 } 5053 5054 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 5055 5056 /* 5057 * pseries-2.7 5058 */ 5059 5060 static bool phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 5061 uint64_t *buid, hwaddr *pio, 5062 hwaddr *mmio32, hwaddr *mmio64, 5063 unsigned n_dma, uint32_t *liobns, 5064 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 5065 { 5066 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 5067 const uint64_t base_buid = 0x800000020000000ULL; 5068 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 5069 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 5070 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 5071 const uint32_t max_index = 255; 5072 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 5073 5074 uint64_t ram_top = MACHINE(spapr)->ram_size; 5075 hwaddr phb0_base, phb_base; 5076 int i; 5077 5078 /* Do we have device memory? */ 5079 if (MACHINE(spapr)->maxram_size > ram_top) { 5080 /* Can't just use maxram_size, because there may be an 5081 * alignment gap between normal and device memory regions 5082 */ 5083 ram_top = MACHINE(spapr)->device_memory->base + 5084 memory_region_size(&MACHINE(spapr)->device_memory->mr); 5085 } 5086 5087 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 5088 5089 if (index > max_index) { 5090 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 5091 max_index); 5092 return false; 5093 } 5094 5095 *buid = base_buid + index; 5096 for (i = 0; i < n_dma; ++i) { 5097 liobns[i] = SPAPR_PCI_LIOBN(index, i); 5098 } 5099 5100 phb_base = phb0_base + index * phb_spacing; 5101 *pio = phb_base + pio_offset; 5102 *mmio32 = phb_base + mmio_offset; 5103 /* 5104 * We don't set the 64-bit MMIO window, relying on the PHB's 5105 * fallback behaviour of automatically splitting a large "32-bit" 5106 * window into contiguous 32-bit and 64-bit windows 5107 */ 5108 5109 *nv2gpa = 0; 5110 *nv2atsd = 0; 5111 return true; 5112 } 5113 5114 static void spapr_machine_2_7_class_options(MachineClass *mc) 5115 { 5116 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5117 static GlobalProperty compat[] = { 5118 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 5119 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 5120 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 5121 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 5122 }; 5123 5124 spapr_machine_2_8_class_options(mc); 5125 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 5126 mc->default_machine_opts = "modern-hotplug-events=off"; 5127 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 5128 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5129 smc->phb_placement = phb_placement_2_7; 5130 } 5131 5132 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 5133 5134 /* 5135 * pseries-2.6 5136 */ 5137 5138 static void spapr_machine_2_6_class_options(MachineClass *mc) 5139 { 5140 static GlobalProperty compat[] = { 5141 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 5142 }; 5143 5144 spapr_machine_2_7_class_options(mc); 5145 mc->has_hotpluggable_cpus = false; 5146 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 5147 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5148 } 5149 5150 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 5151 5152 /* 5153 * pseries-2.5 5154 */ 5155 5156 static void spapr_machine_2_5_class_options(MachineClass *mc) 5157 { 5158 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5159 static GlobalProperty compat[] = { 5160 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 5161 }; 5162 5163 spapr_machine_2_6_class_options(mc); 5164 smc->use_ohci_by_default = true; 5165 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 5166 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5167 } 5168 5169 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 5170 5171 /* 5172 * pseries-2.4 5173 */ 5174 5175 static void spapr_machine_2_4_class_options(MachineClass *mc) 5176 { 5177 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5178 5179 spapr_machine_2_5_class_options(mc); 5180 smc->dr_lmb_enabled = false; 5181 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 5182 } 5183 5184 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 5185 5186 /* 5187 * pseries-2.3 5188 */ 5189 5190 static void spapr_machine_2_3_class_options(MachineClass *mc) 5191 { 5192 static GlobalProperty compat[] = { 5193 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 5194 }; 5195 spapr_machine_2_4_class_options(mc); 5196 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 5197 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5198 } 5199 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 5200 5201 /* 5202 * pseries-2.2 5203 */ 5204 5205 static void spapr_machine_2_2_class_options(MachineClass *mc) 5206 { 5207 static GlobalProperty compat[] = { 5208 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 5209 }; 5210 5211 spapr_machine_2_3_class_options(mc); 5212 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 5213 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5214 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 5215 } 5216 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 5217 5218 /* 5219 * pseries-2.1 5220 */ 5221 5222 static void spapr_machine_2_1_class_options(MachineClass *mc) 5223 { 5224 spapr_machine_2_2_class_options(mc); 5225 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 5226 } 5227 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 5228 5229 static void spapr_machine_register_types(void) 5230 { 5231 type_register_static(&spapr_machine_info); 5232 } 5233 5234 type_init(spapr_machine_register_types) 5235