1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/numa.h" 32 #include "hw/hw.h" 33 #include "qemu/log.h" 34 #include "hw/fw-path-provider.h" 35 #include "elf.h" 36 #include "net/net.h" 37 #include "sysemu/device_tree.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/hw_accel.h" 40 #include "kvm_ppc.h" 41 #include "migration/misc.h" 42 #include "migration/global_state.h" 43 #include "migration/register.h" 44 #include "mmu-hash64.h" 45 #include "mmu-book3s-v3.h" 46 #include "cpu-models.h" 47 #include "qom/cpu.h" 48 49 #include "hw/boards.h" 50 #include "hw/ppc/ppc.h" 51 #include "hw/loader.h" 52 53 #include "hw/ppc/fdt.h" 54 #include "hw/ppc/spapr.h" 55 #include "hw/ppc/spapr_vio.h" 56 #include "hw/pci-host/spapr.h" 57 #include "hw/pci/msi.h" 58 59 #include "hw/pci/pci.h" 60 #include "hw/scsi/scsi.h" 61 #include "hw/virtio/virtio-scsi.h" 62 #include "hw/virtio/vhost-scsi-common.h" 63 64 #include "exec/address-spaces.h" 65 #include "exec/ram_addr.h" 66 #include "hw/usb.h" 67 #include "qemu/config-file.h" 68 #include "qemu/error-report.h" 69 #include "trace.h" 70 #include "hw/nmi.h" 71 #include "hw/intc/intc.h" 72 73 #include "qemu/cutils.h" 74 #include "hw/ppc/spapr_cpu_core.h" 75 #include "hw/mem/memory-device.h" 76 77 #include <libfdt.h> 78 79 /* SLOF memory layout: 80 * 81 * SLOF raw image loaded at 0, copies its romfs right below the flat 82 * device-tree, then position SLOF itself 31M below that 83 * 84 * So we set FW_OVERHEAD to 40MB which should account for all of that 85 * and more 86 * 87 * We load our kernel at 4M, leaving space for SLOF initial image 88 */ 89 #define FDT_MAX_SIZE 0x100000 90 #define RTAS_MAX_SIZE 0x10000 91 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 92 #define FW_MAX_SIZE 0x400000 93 #define FW_FILE_NAME "slof.bin" 94 #define FW_OVERHEAD 0x2800000 95 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 96 97 #define MIN_RMA_SLOF 128UL 98 99 #define PHANDLE_INTC 0x00001111 100 101 /* These two functions implement the VCPU id numbering: one to compute them 102 * all and one to identify thread 0 of a VCORE. Any change to the first one 103 * is likely to have an impact on the second one, so let's keep them close. 104 */ 105 static int spapr_vcpu_id(sPAPRMachineState *spapr, int cpu_index) 106 { 107 assert(spapr->vsmt); 108 return 109 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 110 } 111 static bool spapr_is_thread0_in_vcore(sPAPRMachineState *spapr, 112 PowerPCCPU *cpu) 113 { 114 assert(spapr->vsmt); 115 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 116 } 117 118 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 119 { 120 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 121 * and newer QEMUs don't even have them. In both cases, we don't want 122 * to send anything on the wire. 123 */ 124 return false; 125 } 126 127 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 128 .name = "icp/server", 129 .version_id = 1, 130 .minimum_version_id = 1, 131 .needed = pre_2_10_vmstate_dummy_icp_needed, 132 .fields = (VMStateField[]) { 133 VMSTATE_UNUSED(4), /* uint32_t xirr */ 134 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 135 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 136 VMSTATE_END_OF_LIST() 137 }, 138 }; 139 140 static void pre_2_10_vmstate_register_dummy_icp(int i) 141 { 142 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 143 (void *)(uintptr_t) i); 144 } 145 146 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 147 { 148 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 149 (void *)(uintptr_t) i); 150 } 151 152 int spapr_max_server_number(sPAPRMachineState *spapr) 153 { 154 assert(spapr->vsmt); 155 return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads); 156 } 157 158 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 159 int smt_threads) 160 { 161 int i, ret = 0; 162 uint32_t servers_prop[smt_threads]; 163 uint32_t gservers_prop[smt_threads * 2]; 164 int index = spapr_get_vcpu_id(cpu); 165 166 if (cpu->compat_pvr) { 167 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 168 if (ret < 0) { 169 return ret; 170 } 171 } 172 173 /* Build interrupt servers and gservers properties */ 174 for (i = 0; i < smt_threads; i++) { 175 servers_prop[i] = cpu_to_be32(index + i); 176 /* Hack, direct the group queues back to cpu 0 */ 177 gservers_prop[i*2] = cpu_to_be32(index + i); 178 gservers_prop[i*2 + 1] = 0; 179 } 180 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 181 servers_prop, sizeof(servers_prop)); 182 if (ret < 0) { 183 return ret; 184 } 185 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 186 gservers_prop, sizeof(gservers_prop)); 187 188 return ret; 189 } 190 191 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 192 { 193 int index = spapr_get_vcpu_id(cpu); 194 uint32_t associativity[] = {cpu_to_be32(0x5), 195 cpu_to_be32(0x0), 196 cpu_to_be32(0x0), 197 cpu_to_be32(0x0), 198 cpu_to_be32(cpu->node_id), 199 cpu_to_be32(index)}; 200 201 /* Advertise NUMA via ibm,associativity */ 202 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 203 sizeof(associativity)); 204 } 205 206 /* Populate the "ibm,pa-features" property */ 207 static void spapr_populate_pa_features(sPAPRMachineState *spapr, 208 PowerPCCPU *cpu, 209 void *fdt, int offset, 210 bool legacy_guest) 211 { 212 uint8_t pa_features_206[] = { 6, 0, 213 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 214 uint8_t pa_features_207[] = { 24, 0, 215 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 216 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 217 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 218 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 219 uint8_t pa_features_300[] = { 66, 0, 220 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 221 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 222 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 223 /* 6: DS207 */ 224 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 225 /* 16: Vector */ 226 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 227 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 228 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 229 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 230 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 231 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 232 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 233 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 235 /* 42: PM, 44: PC RA, 46: SC vec'd */ 236 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 237 /* 48: SIMD, 50: QP BFP, 52: String */ 238 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 239 /* 54: DecFP, 56: DecI, 58: SHA */ 240 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 241 /* 60: NM atomic, 62: RNG */ 242 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 243 }; 244 uint8_t *pa_features = NULL; 245 size_t pa_size; 246 247 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 248 pa_features = pa_features_206; 249 pa_size = sizeof(pa_features_206); 250 } 251 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 252 pa_features = pa_features_207; 253 pa_size = sizeof(pa_features_207); 254 } 255 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 256 pa_features = pa_features_300; 257 pa_size = sizeof(pa_features_300); 258 } 259 if (!pa_features) { 260 return; 261 } 262 263 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 264 /* 265 * Note: we keep CI large pages off by default because a 64K capable 266 * guest provisioned with large pages might otherwise try to map a qemu 267 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 268 * even if that qemu runs on a 4k host. 269 * We dd this bit back here if we are confident this is not an issue 270 */ 271 pa_features[3] |= 0x20; 272 } 273 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 274 pa_features[24] |= 0x80; /* Transactional memory support */ 275 } 276 if (legacy_guest && pa_size > 40) { 277 /* Workaround for broken kernels that attempt (guest) radix 278 * mode when they can't handle it, if they see the radix bit set 279 * in pa-features. So hide it from them. */ 280 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 281 } 282 283 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 284 } 285 286 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 287 { 288 int ret = 0, offset, cpus_offset; 289 CPUState *cs; 290 char cpu_model[32]; 291 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 292 293 CPU_FOREACH(cs) { 294 PowerPCCPU *cpu = POWERPC_CPU(cs); 295 DeviceClass *dc = DEVICE_GET_CLASS(cs); 296 int index = spapr_get_vcpu_id(cpu); 297 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 298 299 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 300 continue; 301 } 302 303 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 304 305 cpus_offset = fdt_path_offset(fdt, "/cpus"); 306 if (cpus_offset < 0) { 307 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 308 if (cpus_offset < 0) { 309 return cpus_offset; 310 } 311 } 312 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 313 if (offset < 0) { 314 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 315 if (offset < 0) { 316 return offset; 317 } 318 } 319 320 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 321 pft_size_prop, sizeof(pft_size_prop)); 322 if (ret < 0) { 323 return ret; 324 } 325 326 if (nb_numa_nodes > 1) { 327 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); 328 if (ret < 0) { 329 return ret; 330 } 331 } 332 333 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 334 if (ret < 0) { 335 return ret; 336 } 337 338 spapr_populate_pa_features(spapr, cpu, fdt, offset, 339 spapr->cas_legacy_guest_workaround); 340 } 341 return ret; 342 } 343 344 static hwaddr spapr_node0_size(MachineState *machine) 345 { 346 if (nb_numa_nodes) { 347 int i; 348 for (i = 0; i < nb_numa_nodes; ++i) { 349 if (numa_info[i].node_mem) { 350 return MIN(pow2floor(numa_info[i].node_mem), 351 machine->ram_size); 352 } 353 } 354 } 355 return machine->ram_size; 356 } 357 358 static void add_str(GString *s, const gchar *s1) 359 { 360 g_string_append_len(s, s1, strlen(s1) + 1); 361 } 362 363 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 364 hwaddr size) 365 { 366 uint32_t associativity[] = { 367 cpu_to_be32(0x4), /* length */ 368 cpu_to_be32(0x0), cpu_to_be32(0x0), 369 cpu_to_be32(0x0), cpu_to_be32(nodeid) 370 }; 371 char mem_name[32]; 372 uint64_t mem_reg_property[2]; 373 int off; 374 375 mem_reg_property[0] = cpu_to_be64(start); 376 mem_reg_property[1] = cpu_to_be64(size); 377 378 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 379 off = fdt_add_subnode(fdt, 0, mem_name); 380 _FDT(off); 381 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 382 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 383 sizeof(mem_reg_property)))); 384 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 385 sizeof(associativity)))); 386 return off; 387 } 388 389 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 390 { 391 MachineState *machine = MACHINE(spapr); 392 hwaddr mem_start, node_size; 393 int i, nb_nodes = nb_numa_nodes; 394 NodeInfo *nodes = numa_info; 395 NodeInfo ramnode; 396 397 /* No NUMA nodes, assume there is just one node with whole RAM */ 398 if (!nb_numa_nodes) { 399 nb_nodes = 1; 400 ramnode.node_mem = machine->ram_size; 401 nodes = &ramnode; 402 } 403 404 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 405 if (!nodes[i].node_mem) { 406 continue; 407 } 408 if (mem_start >= machine->ram_size) { 409 node_size = 0; 410 } else { 411 node_size = nodes[i].node_mem; 412 if (node_size > machine->ram_size - mem_start) { 413 node_size = machine->ram_size - mem_start; 414 } 415 } 416 if (!mem_start) { 417 /* spapr_machine_init() checks for rma_size <= node0_size 418 * already */ 419 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 420 mem_start += spapr->rma_size; 421 node_size -= spapr->rma_size; 422 } 423 for ( ; node_size; ) { 424 hwaddr sizetmp = pow2floor(node_size); 425 426 /* mem_start != 0 here */ 427 if (ctzl(mem_start) < ctzl(sizetmp)) { 428 sizetmp = 1ULL << ctzl(mem_start); 429 } 430 431 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 432 node_size -= sizetmp; 433 mem_start += sizetmp; 434 } 435 } 436 437 return 0; 438 } 439 440 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 441 sPAPRMachineState *spapr) 442 { 443 PowerPCCPU *cpu = POWERPC_CPU(cs); 444 CPUPPCState *env = &cpu->env; 445 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 446 int index = spapr_get_vcpu_id(cpu); 447 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 448 0xffffffff, 0xffffffff}; 449 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 450 : SPAPR_TIMEBASE_FREQ; 451 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 452 uint32_t page_sizes_prop[64]; 453 size_t page_sizes_prop_size; 454 uint32_t vcpus_per_socket = smp_threads * smp_cores; 455 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 456 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 457 sPAPRDRConnector *drc; 458 int drc_index; 459 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 460 int i; 461 462 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 463 if (drc) { 464 drc_index = spapr_drc_index(drc); 465 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 466 } 467 468 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 469 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 470 471 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 472 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 473 env->dcache_line_size))); 474 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 475 env->dcache_line_size))); 476 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 477 env->icache_line_size))); 478 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 479 env->icache_line_size))); 480 481 if (pcc->l1_dcache_size) { 482 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 483 pcc->l1_dcache_size))); 484 } else { 485 warn_report("Unknown L1 dcache size for cpu"); 486 } 487 if (pcc->l1_icache_size) { 488 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 489 pcc->l1_icache_size))); 490 } else { 491 warn_report("Unknown L1 icache size for cpu"); 492 } 493 494 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 495 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 496 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 497 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 498 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 499 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 500 501 if (env->spr_cb[SPR_PURR].oea_read) { 502 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 503 } 504 505 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 506 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 507 segs, sizeof(segs)))); 508 } 509 510 /* Advertise VSX (vector extensions) if available 511 * 1 == VMX / Altivec available 512 * 2 == VSX available 513 * 514 * Only CPUs for which we create core types in spapr_cpu_core.c 515 * are possible, and all of those have VMX */ 516 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 517 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 518 } else { 519 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 520 } 521 522 /* Advertise DFP (Decimal Floating Point) if available 523 * 0 / no property == no DFP 524 * 1 == DFP available */ 525 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 526 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 527 } 528 529 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 530 sizeof(page_sizes_prop)); 531 if (page_sizes_prop_size) { 532 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 533 page_sizes_prop, page_sizes_prop_size))); 534 } 535 536 spapr_populate_pa_features(spapr, cpu, fdt, offset, false); 537 538 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 539 cs->cpu_index / vcpus_per_socket))); 540 541 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 542 pft_size_prop, sizeof(pft_size_prop)))); 543 544 if (nb_numa_nodes > 1) { 545 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 546 } 547 548 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 549 550 if (pcc->radix_page_info) { 551 for (i = 0; i < pcc->radix_page_info->count; i++) { 552 radix_AP_encodings[i] = 553 cpu_to_be32(pcc->radix_page_info->entries[i]); 554 } 555 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 556 radix_AP_encodings, 557 pcc->radix_page_info->count * 558 sizeof(radix_AP_encodings[0])))); 559 } 560 } 561 562 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 563 { 564 CPUState **rev; 565 CPUState *cs; 566 int n_cpus; 567 int cpus_offset; 568 char *nodename; 569 int i; 570 571 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 572 _FDT(cpus_offset); 573 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 574 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 575 576 /* 577 * We walk the CPUs in reverse order to ensure that CPU DT nodes 578 * created by fdt_add_subnode() end up in the right order in FDT 579 * for the guest kernel the enumerate the CPUs correctly. 580 * 581 * The CPU list cannot be traversed in reverse order, so we need 582 * to do extra work. 583 */ 584 n_cpus = 0; 585 rev = NULL; 586 CPU_FOREACH(cs) { 587 rev = g_renew(CPUState *, rev, n_cpus + 1); 588 rev[n_cpus++] = cs; 589 } 590 591 for (i = n_cpus - 1; i >= 0; i--) { 592 CPUState *cs = rev[i]; 593 PowerPCCPU *cpu = POWERPC_CPU(cs); 594 int index = spapr_get_vcpu_id(cpu); 595 DeviceClass *dc = DEVICE_GET_CLASS(cs); 596 int offset; 597 598 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 599 continue; 600 } 601 602 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 603 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 604 g_free(nodename); 605 _FDT(offset); 606 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 607 } 608 609 g_free(rev); 610 } 611 612 static int spapr_rng_populate_dt(void *fdt) 613 { 614 int node; 615 int ret; 616 617 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 618 if (node <= 0) { 619 return -1; 620 } 621 ret = fdt_setprop_string(fdt, node, "device_type", 622 "ibm,platform-facilities"); 623 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 624 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 625 626 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 627 if (node <= 0) { 628 return -1; 629 } 630 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 631 632 return ret ? -1 : 0; 633 } 634 635 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 636 { 637 MemoryDeviceInfoList *info; 638 639 for (info = list; info; info = info->next) { 640 MemoryDeviceInfo *value = info->value; 641 642 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 643 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 644 645 if (addr >= pcdimm_info->addr && 646 addr < (pcdimm_info->addr + pcdimm_info->size)) { 647 return pcdimm_info->node; 648 } 649 } 650 } 651 652 return -1; 653 } 654 655 struct sPAPRDrconfCellV2 { 656 uint32_t seq_lmbs; 657 uint64_t base_addr; 658 uint32_t drc_index; 659 uint32_t aa_index; 660 uint32_t flags; 661 } QEMU_PACKED; 662 663 typedef struct DrconfCellQueue { 664 struct sPAPRDrconfCellV2 cell; 665 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 666 } DrconfCellQueue; 667 668 static DrconfCellQueue * 669 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 670 uint32_t drc_index, uint32_t aa_index, 671 uint32_t flags) 672 { 673 DrconfCellQueue *elem; 674 675 elem = g_malloc0(sizeof(*elem)); 676 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 677 elem->cell.base_addr = cpu_to_be64(base_addr); 678 elem->cell.drc_index = cpu_to_be32(drc_index); 679 elem->cell.aa_index = cpu_to_be32(aa_index); 680 elem->cell.flags = cpu_to_be32(flags); 681 682 return elem; 683 } 684 685 /* ibm,dynamic-memory-v2 */ 686 static int spapr_populate_drmem_v2(sPAPRMachineState *spapr, void *fdt, 687 int offset, MemoryDeviceInfoList *dimms) 688 { 689 MachineState *machine = MACHINE(spapr); 690 uint8_t *int_buf, *cur_index; 691 int ret; 692 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 693 uint64_t addr, cur_addr, size; 694 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 695 uint64_t mem_end = machine->device_memory->base + 696 memory_region_size(&machine->device_memory->mr); 697 uint32_t node, buf_len, nr_entries = 0; 698 sPAPRDRConnector *drc; 699 DrconfCellQueue *elem, *next; 700 MemoryDeviceInfoList *info; 701 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 702 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 703 704 /* Entry to cover RAM and the gap area */ 705 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 706 SPAPR_LMB_FLAGS_RESERVED | 707 SPAPR_LMB_FLAGS_DRC_INVALID); 708 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 709 nr_entries++; 710 711 cur_addr = machine->device_memory->base; 712 for (info = dimms; info; info = info->next) { 713 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 714 715 addr = di->addr; 716 size = di->size; 717 node = di->node; 718 719 /* Entry for hot-pluggable area */ 720 if (cur_addr < addr) { 721 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 722 g_assert(drc); 723 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 724 cur_addr, spapr_drc_index(drc), -1, 0); 725 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 726 nr_entries++; 727 } 728 729 /* Entry for DIMM */ 730 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 731 g_assert(drc); 732 elem = spapr_get_drconf_cell(size / lmb_size, addr, 733 spapr_drc_index(drc), node, 734 SPAPR_LMB_FLAGS_ASSIGNED); 735 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 736 nr_entries++; 737 cur_addr = addr + size; 738 } 739 740 /* Entry for remaining hotpluggable area */ 741 if (cur_addr < mem_end) { 742 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 743 g_assert(drc); 744 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 745 cur_addr, spapr_drc_index(drc), -1, 0); 746 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 747 nr_entries++; 748 } 749 750 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 751 int_buf = cur_index = g_malloc0(buf_len); 752 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 753 cur_index += sizeof(nr_entries); 754 755 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 756 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 757 cur_index += sizeof(elem->cell); 758 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 759 g_free(elem); 760 } 761 762 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 763 g_free(int_buf); 764 if (ret < 0) { 765 return -1; 766 } 767 return 0; 768 } 769 770 /* ibm,dynamic-memory */ 771 static int spapr_populate_drmem_v1(sPAPRMachineState *spapr, void *fdt, 772 int offset, MemoryDeviceInfoList *dimms) 773 { 774 MachineState *machine = MACHINE(spapr); 775 int i, ret; 776 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 777 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 778 uint32_t nr_lmbs = (machine->device_memory->base + 779 memory_region_size(&machine->device_memory->mr)) / 780 lmb_size; 781 uint32_t *int_buf, *cur_index, buf_len; 782 783 /* 784 * Allocate enough buffer size to fit in ibm,dynamic-memory 785 */ 786 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 787 cur_index = int_buf = g_malloc0(buf_len); 788 int_buf[0] = cpu_to_be32(nr_lmbs); 789 cur_index++; 790 for (i = 0; i < nr_lmbs; i++) { 791 uint64_t addr = i * lmb_size; 792 uint32_t *dynamic_memory = cur_index; 793 794 if (i >= device_lmb_start) { 795 sPAPRDRConnector *drc; 796 797 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 798 g_assert(drc); 799 800 dynamic_memory[0] = cpu_to_be32(addr >> 32); 801 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 802 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 803 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 804 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 805 if (memory_region_present(get_system_memory(), addr)) { 806 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 807 } else { 808 dynamic_memory[5] = cpu_to_be32(0); 809 } 810 } else { 811 /* 812 * LMB information for RMA, boot time RAM and gap b/n RAM and 813 * device memory region -- all these are marked as reserved 814 * and as having no valid DRC. 815 */ 816 dynamic_memory[0] = cpu_to_be32(addr >> 32); 817 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 818 dynamic_memory[2] = cpu_to_be32(0); 819 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 820 dynamic_memory[4] = cpu_to_be32(-1); 821 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 822 SPAPR_LMB_FLAGS_DRC_INVALID); 823 } 824 825 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 826 } 827 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 828 g_free(int_buf); 829 if (ret < 0) { 830 return -1; 831 } 832 return 0; 833 } 834 835 /* 836 * Adds ibm,dynamic-reconfiguration-memory node. 837 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 838 * of this device tree node. 839 */ 840 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 841 { 842 MachineState *machine = MACHINE(spapr); 843 int ret, i, offset; 844 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 845 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 846 uint32_t *int_buf, *cur_index, buf_len; 847 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 848 MemoryDeviceInfoList *dimms = NULL; 849 850 /* 851 * Don't create the node if there is no device memory 852 */ 853 if (machine->ram_size == machine->maxram_size) { 854 return 0; 855 } 856 857 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 858 859 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 860 sizeof(prop_lmb_size)); 861 if (ret < 0) { 862 return ret; 863 } 864 865 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 866 if (ret < 0) { 867 return ret; 868 } 869 870 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 871 if (ret < 0) { 872 return ret; 873 } 874 875 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 876 dimms = qmp_memory_device_list(); 877 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 878 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); 879 } else { 880 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); 881 } 882 qapi_free_MemoryDeviceInfoList(dimms); 883 884 if (ret < 0) { 885 return ret; 886 } 887 888 /* ibm,associativity-lookup-arrays */ 889 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); 890 cur_index = int_buf = g_malloc0(buf_len); 891 int_buf[0] = cpu_to_be32(nr_nodes); 892 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 893 cur_index += 2; 894 for (i = 0; i < nr_nodes; i++) { 895 uint32_t associativity[] = { 896 cpu_to_be32(0x0), 897 cpu_to_be32(0x0), 898 cpu_to_be32(0x0), 899 cpu_to_be32(i) 900 }; 901 memcpy(cur_index, associativity, sizeof(associativity)); 902 cur_index += 4; 903 } 904 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 905 (cur_index - int_buf) * sizeof(uint32_t)); 906 g_free(int_buf); 907 908 return ret; 909 } 910 911 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 912 sPAPROptionVector *ov5_updates) 913 { 914 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 915 int ret = 0, offset; 916 917 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 918 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 919 g_assert(smc->dr_lmb_enabled); 920 ret = spapr_populate_drconf_memory(spapr, fdt); 921 if (ret) { 922 goto out; 923 } 924 } 925 926 offset = fdt_path_offset(fdt, "/chosen"); 927 if (offset < 0) { 928 offset = fdt_add_subnode(fdt, 0, "chosen"); 929 if (offset < 0) { 930 return offset; 931 } 932 } 933 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 934 "ibm,architecture-vec-5"); 935 936 out: 937 return ret; 938 } 939 940 static bool spapr_hotplugged_dev_before_cas(void) 941 { 942 Object *drc_container, *obj; 943 ObjectProperty *prop; 944 ObjectPropertyIterator iter; 945 946 drc_container = container_get(object_get_root(), "/dr-connector"); 947 object_property_iter_init(&iter, drc_container); 948 while ((prop = object_property_iter_next(&iter))) { 949 if (!strstart(prop->type, "link<", NULL)) { 950 continue; 951 } 952 obj = object_property_get_link(drc_container, prop->name, NULL); 953 if (spapr_drc_needed(obj)) { 954 return true; 955 } 956 } 957 return false; 958 } 959 960 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 961 target_ulong addr, target_ulong size, 962 sPAPROptionVector *ov5_updates) 963 { 964 void *fdt, *fdt_skel; 965 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 966 967 if (spapr_hotplugged_dev_before_cas()) { 968 return 1; 969 } 970 971 if (size < sizeof(hdr) || size > FW_MAX_SIZE) { 972 error_report("SLOF provided an unexpected CAS buffer size " 973 TARGET_FMT_lu " (min: %zu, max: %u)", 974 size, sizeof(hdr), FW_MAX_SIZE); 975 exit(EXIT_FAILURE); 976 } 977 978 size -= sizeof(hdr); 979 980 /* Create skeleton */ 981 fdt_skel = g_malloc0(size); 982 _FDT((fdt_create(fdt_skel, size))); 983 _FDT((fdt_finish_reservemap(fdt_skel))); 984 _FDT((fdt_begin_node(fdt_skel, ""))); 985 _FDT((fdt_end_node(fdt_skel))); 986 _FDT((fdt_finish(fdt_skel))); 987 fdt = g_malloc0(size); 988 _FDT((fdt_open_into(fdt_skel, fdt, size))); 989 g_free(fdt_skel); 990 991 /* Fixup cpu nodes */ 992 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 993 994 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 995 return -1; 996 } 997 998 /* Pack resulting tree */ 999 _FDT((fdt_pack(fdt))); 1000 1001 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 1002 trace_spapr_cas_failed(size); 1003 return -1; 1004 } 1005 1006 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 1007 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 1008 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 1009 g_free(fdt); 1010 1011 return 0; 1012 } 1013 1014 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 1015 { 1016 int rtas; 1017 GString *hypertas = g_string_sized_new(256); 1018 GString *qemu_hypertas = g_string_sized_new(256); 1019 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 1020 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 1021 memory_region_size(&MACHINE(spapr)->device_memory->mr); 1022 uint32_t lrdr_capacity[] = { 1023 cpu_to_be32(max_device_addr >> 32), 1024 cpu_to_be32(max_device_addr & 0xffffffff), 1025 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 1026 cpu_to_be32(max_cpus / smp_threads), 1027 }; 1028 uint32_t maxdomains[] = { 1029 cpu_to_be32(4), 1030 cpu_to_be32(0), 1031 cpu_to_be32(0), 1032 cpu_to_be32(0), 1033 cpu_to_be32(nb_numa_nodes ? nb_numa_nodes : 1), 1034 }; 1035 1036 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 1037 1038 /* hypertas */ 1039 add_str(hypertas, "hcall-pft"); 1040 add_str(hypertas, "hcall-term"); 1041 add_str(hypertas, "hcall-dabr"); 1042 add_str(hypertas, "hcall-interrupt"); 1043 add_str(hypertas, "hcall-tce"); 1044 add_str(hypertas, "hcall-vio"); 1045 add_str(hypertas, "hcall-splpar"); 1046 add_str(hypertas, "hcall-bulk"); 1047 add_str(hypertas, "hcall-set-mode"); 1048 add_str(hypertas, "hcall-sprg0"); 1049 add_str(hypertas, "hcall-copy"); 1050 add_str(hypertas, "hcall-debug"); 1051 add_str(hypertas, "hcall-vphn"); 1052 add_str(qemu_hypertas, "hcall-memop1"); 1053 1054 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 1055 add_str(hypertas, "hcall-multi-tce"); 1056 } 1057 1058 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 1059 add_str(hypertas, "hcall-hpt-resize"); 1060 } 1061 1062 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 1063 hypertas->str, hypertas->len)); 1064 g_string_free(hypertas, TRUE); 1065 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 1066 qemu_hypertas->str, qemu_hypertas->len)); 1067 g_string_free(qemu_hypertas, TRUE); 1068 1069 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 1070 refpoints, sizeof(refpoints))); 1071 1072 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 1073 maxdomains, sizeof(maxdomains))); 1074 1075 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 1076 RTAS_ERROR_LOG_MAX)); 1077 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 1078 RTAS_EVENT_SCAN_RATE)); 1079 1080 g_assert(msi_nonbroken); 1081 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 1082 1083 /* 1084 * According to PAPR, rtas ibm,os-term does not guarantee a return 1085 * back to the guest cpu. 1086 * 1087 * While an additional ibm,extended-os-term property indicates 1088 * that rtas call return will always occur. Set this property. 1089 */ 1090 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 1091 1092 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 1093 lrdr_capacity, sizeof(lrdr_capacity))); 1094 1095 spapr_dt_rtas_tokens(fdt, rtas); 1096 } 1097 1098 /* 1099 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 1100 * and the XIVE features that the guest may request and thus the valid 1101 * values for bytes 23..26 of option vector 5: 1102 */ 1103 static void spapr_dt_ov5_platform_support(sPAPRMachineState *spapr, void *fdt, 1104 int chosen) 1105 { 1106 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1107 1108 char val[2 * 4] = { 1109 23, spapr->irq->ov5, /* Xive mode. */ 1110 24, 0x00, /* Hash/Radix, filled in below. */ 1111 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1112 26, 0x40, /* Radix options: GTSE == yes. */ 1113 }; 1114 1115 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1116 first_ppc_cpu->compat_pvr)) { 1117 /* 1118 * If we're in a pre POWER9 compat mode then the guest should 1119 * do hash and use the legacy interrupt mode 1120 */ 1121 val[1] = 0x00; /* XICS */ 1122 val[3] = 0x00; /* Hash */ 1123 } else if (kvm_enabled()) { 1124 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1125 val[3] = 0x80; /* OV5_MMU_BOTH */ 1126 } else if (kvmppc_has_cap_mmu_radix()) { 1127 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1128 } else { 1129 val[3] = 0x00; /* Hash */ 1130 } 1131 } else { 1132 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1133 val[3] = 0xC0; 1134 } 1135 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1136 val, sizeof(val))); 1137 } 1138 1139 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 1140 { 1141 MachineState *machine = MACHINE(spapr); 1142 int chosen; 1143 const char *boot_device = machine->boot_order; 1144 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1145 size_t cb = 0; 1146 char *bootlist = get_boot_devices_list(&cb); 1147 1148 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1149 1150 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 1151 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1152 spapr->initrd_base)); 1153 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1154 spapr->initrd_base + spapr->initrd_size)); 1155 1156 if (spapr->kernel_size) { 1157 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 1158 cpu_to_be64(spapr->kernel_size) }; 1159 1160 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1161 &kprop, sizeof(kprop))); 1162 if (spapr->kernel_le) { 1163 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1164 } 1165 } 1166 if (boot_menu) { 1167 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1168 } 1169 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1170 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1171 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1172 1173 if (cb && bootlist) { 1174 int i; 1175 1176 for (i = 0; i < cb; i++) { 1177 if (bootlist[i] == '\n') { 1178 bootlist[i] = ' '; 1179 } 1180 } 1181 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1182 } 1183 1184 if (boot_device && strlen(boot_device)) { 1185 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1186 } 1187 1188 if (!spapr->has_graphics && stdout_path) { 1189 /* 1190 * "linux,stdout-path" and "stdout" properties are deprecated by linux 1191 * kernel. New platforms should only use the "stdout-path" property. Set 1192 * the new property and continue using older property to remain 1193 * compatible with the existing firmware. 1194 */ 1195 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1196 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1197 } 1198 1199 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1200 1201 g_free(stdout_path); 1202 g_free(bootlist); 1203 } 1204 1205 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 1206 { 1207 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1208 * KVM to work under pHyp with some guest co-operation */ 1209 int hypervisor; 1210 uint8_t hypercall[16]; 1211 1212 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1213 /* indicate KVM hypercall interface */ 1214 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1215 if (kvmppc_has_cap_fixup_hcalls()) { 1216 /* 1217 * Older KVM versions with older guest kernels were broken 1218 * with the magic page, don't allow the guest to map it. 1219 */ 1220 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1221 sizeof(hypercall))) { 1222 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1223 hypercall, sizeof(hypercall))); 1224 } 1225 } 1226 } 1227 1228 static void *spapr_build_fdt(sPAPRMachineState *spapr) 1229 { 1230 MachineState *machine = MACHINE(spapr); 1231 MachineClass *mc = MACHINE_GET_CLASS(machine); 1232 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1233 int ret; 1234 void *fdt; 1235 sPAPRPHBState *phb; 1236 char *buf; 1237 1238 fdt = g_malloc0(FDT_MAX_SIZE); 1239 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 1240 1241 /* Root node */ 1242 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1243 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1244 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1245 1246 /* 1247 * Add info to guest to indentify which host is it being run on 1248 * and what is the uuid of the guest 1249 */ 1250 if (spapr->host_model && !g_str_equal(spapr->host_model, "none")) { 1251 if (g_str_equal(spapr->host_model, "passthrough")) { 1252 /* -M host-model=passthrough */ 1253 if (kvmppc_get_host_model(&buf)) { 1254 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1255 g_free(buf); 1256 } 1257 } else { 1258 /* -M host-model=<user-string> */ 1259 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1260 } 1261 } 1262 1263 if (spapr->host_serial && !g_str_equal(spapr->host_serial, "none")) { 1264 if (g_str_equal(spapr->host_serial, "passthrough")) { 1265 /* -M host-serial=passthrough */ 1266 if (kvmppc_get_host_serial(&buf)) { 1267 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1268 g_free(buf); 1269 } 1270 } else { 1271 /* -M host-serial=<user-string> */ 1272 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1273 } 1274 } 1275 1276 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1277 1278 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1279 if (qemu_uuid_set) { 1280 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1281 } 1282 g_free(buf); 1283 1284 if (qemu_get_vm_name()) { 1285 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1286 qemu_get_vm_name())); 1287 } 1288 1289 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1290 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1291 1292 /* /interrupt controller */ 1293 spapr->irq->dt_populate(spapr, spapr_max_server_number(spapr), fdt, 1294 PHANDLE_INTC); 1295 1296 ret = spapr_populate_memory(spapr, fdt); 1297 if (ret < 0) { 1298 error_report("couldn't setup memory nodes in fdt"); 1299 exit(1); 1300 } 1301 1302 /* /vdevice */ 1303 spapr_dt_vdevice(spapr->vio_bus, fdt); 1304 1305 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1306 ret = spapr_rng_populate_dt(fdt); 1307 if (ret < 0) { 1308 error_report("could not set up rng device in the fdt"); 1309 exit(1); 1310 } 1311 } 1312 1313 QLIST_FOREACH(phb, &spapr->phbs, list) { 1314 ret = spapr_populate_pci_dt(phb, PHANDLE_INTC, fdt, 1315 spapr->irq->nr_msis, NULL); 1316 if (ret < 0) { 1317 error_report("couldn't setup PCI devices in fdt"); 1318 exit(1); 1319 } 1320 } 1321 1322 /* cpus */ 1323 spapr_populate_cpus_dt_node(fdt, spapr); 1324 1325 if (smc->dr_lmb_enabled) { 1326 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1327 } 1328 1329 if (mc->has_hotpluggable_cpus) { 1330 int offset = fdt_path_offset(fdt, "/cpus"); 1331 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1332 SPAPR_DR_CONNECTOR_TYPE_CPU); 1333 if (ret < 0) { 1334 error_report("Couldn't set up CPU DR device tree properties"); 1335 exit(1); 1336 } 1337 } 1338 1339 /* /event-sources */ 1340 spapr_dt_events(spapr, fdt); 1341 1342 /* /rtas */ 1343 spapr_dt_rtas(spapr, fdt); 1344 1345 /* /chosen */ 1346 spapr_dt_chosen(spapr, fdt); 1347 1348 /* /hypervisor */ 1349 if (kvm_enabled()) { 1350 spapr_dt_hypervisor(spapr, fdt); 1351 } 1352 1353 /* Build memory reserve map */ 1354 if (spapr->kernel_size) { 1355 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1356 } 1357 if (spapr->initrd_size) { 1358 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1359 } 1360 1361 /* ibm,client-architecture-support updates */ 1362 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1363 if (ret < 0) { 1364 error_report("couldn't setup CAS properties fdt"); 1365 exit(1); 1366 } 1367 1368 if (smc->dr_phb_enabled) { 1369 ret = spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB); 1370 if (ret < 0) { 1371 error_report("Couldn't set up PHB DR device tree properties"); 1372 exit(1); 1373 } 1374 } 1375 1376 return fdt; 1377 } 1378 1379 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1380 { 1381 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1382 } 1383 1384 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1385 PowerPCCPU *cpu) 1386 { 1387 CPUPPCState *env = &cpu->env; 1388 1389 /* The TCG path should also be holding the BQL at this point */ 1390 g_assert(qemu_mutex_iothread_locked()); 1391 1392 if (msr_pr) { 1393 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1394 env->gpr[3] = H_PRIVILEGE; 1395 } else { 1396 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1397 } 1398 } 1399 1400 struct LPCRSyncState { 1401 target_ulong value; 1402 target_ulong mask; 1403 }; 1404 1405 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1406 { 1407 struct LPCRSyncState *s = arg.host_ptr; 1408 PowerPCCPU *cpu = POWERPC_CPU(cs); 1409 CPUPPCState *env = &cpu->env; 1410 target_ulong lpcr; 1411 1412 cpu_synchronize_state(cs); 1413 lpcr = env->spr[SPR_LPCR]; 1414 lpcr &= ~s->mask; 1415 lpcr |= s->value; 1416 ppc_store_lpcr(cpu, lpcr); 1417 } 1418 1419 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1420 { 1421 CPUState *cs; 1422 struct LPCRSyncState s = { 1423 .value = value, 1424 .mask = mask 1425 }; 1426 CPU_FOREACH(cs) { 1427 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1428 } 1429 } 1430 1431 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry) 1432 { 1433 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1434 1435 /* Copy PATE1:GR into PATE0:HR */ 1436 entry->dw0 = spapr->patb_entry & PATE0_HR; 1437 entry->dw1 = spapr->patb_entry; 1438 } 1439 1440 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1441 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1442 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1443 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1444 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1445 1446 /* 1447 * Get the fd to access the kernel htab, re-opening it if necessary 1448 */ 1449 static int get_htab_fd(sPAPRMachineState *spapr) 1450 { 1451 Error *local_err = NULL; 1452 1453 if (spapr->htab_fd >= 0) { 1454 return spapr->htab_fd; 1455 } 1456 1457 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1458 if (spapr->htab_fd < 0) { 1459 error_report_err(local_err); 1460 } 1461 1462 return spapr->htab_fd; 1463 } 1464 1465 void close_htab_fd(sPAPRMachineState *spapr) 1466 { 1467 if (spapr->htab_fd >= 0) { 1468 close(spapr->htab_fd); 1469 } 1470 spapr->htab_fd = -1; 1471 } 1472 1473 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1474 { 1475 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1476 1477 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1478 } 1479 1480 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1481 { 1482 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1483 1484 assert(kvm_enabled()); 1485 1486 if (!spapr->htab) { 1487 return 0; 1488 } 1489 1490 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1491 } 1492 1493 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1494 hwaddr ptex, int n) 1495 { 1496 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1497 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1498 1499 if (!spapr->htab) { 1500 /* 1501 * HTAB is controlled by KVM. Fetch into temporary buffer 1502 */ 1503 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1504 kvmppc_read_hptes(hptes, ptex, n); 1505 return hptes; 1506 } 1507 1508 /* 1509 * HTAB is controlled by QEMU. Just point to the internally 1510 * accessible PTEG. 1511 */ 1512 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1513 } 1514 1515 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1516 const ppc_hash_pte64_t *hptes, 1517 hwaddr ptex, int n) 1518 { 1519 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1520 1521 if (!spapr->htab) { 1522 g_free((void *)hptes); 1523 } 1524 1525 /* Nothing to do for qemu managed HPT */ 1526 } 1527 1528 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1529 uint64_t pte0, uint64_t pte1) 1530 { 1531 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1532 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1533 1534 if (!spapr->htab) { 1535 kvmppc_write_hpte(ptex, pte0, pte1); 1536 } else { 1537 if (pte0 & HPTE64_V_VALID) { 1538 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1539 /* 1540 * When setting valid, we write PTE1 first. This ensures 1541 * proper synchronization with the reading code in 1542 * ppc_hash64_pteg_search() 1543 */ 1544 smp_wmb(); 1545 stq_p(spapr->htab + offset, pte0); 1546 } else { 1547 stq_p(spapr->htab + offset, pte0); 1548 /* 1549 * When clearing it we set PTE0 first. This ensures proper 1550 * synchronization with the reading code in 1551 * ppc_hash64_pteg_search() 1552 */ 1553 smp_wmb(); 1554 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1555 } 1556 } 1557 } 1558 1559 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1560 { 1561 int shift; 1562 1563 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1564 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1565 * that's much more than is needed for Linux guests */ 1566 shift = ctz64(pow2ceil(ramsize)) - 7; 1567 shift = MAX(shift, 18); /* Minimum architected size */ 1568 shift = MIN(shift, 46); /* Maximum architected size */ 1569 return shift; 1570 } 1571 1572 void spapr_free_hpt(sPAPRMachineState *spapr) 1573 { 1574 g_free(spapr->htab); 1575 spapr->htab = NULL; 1576 spapr->htab_shift = 0; 1577 close_htab_fd(spapr); 1578 } 1579 1580 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1581 Error **errp) 1582 { 1583 long rc; 1584 1585 /* Clean up any HPT info from a previous boot */ 1586 spapr_free_hpt(spapr); 1587 1588 rc = kvmppc_reset_htab(shift); 1589 if (rc < 0) { 1590 /* kernel-side HPT needed, but couldn't allocate one */ 1591 error_setg_errno(errp, errno, 1592 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1593 shift); 1594 /* This is almost certainly fatal, but if the caller really 1595 * wants to carry on with shift == 0, it's welcome to try */ 1596 } else if (rc > 0) { 1597 /* kernel-side HPT allocated */ 1598 if (rc != shift) { 1599 error_setg(errp, 1600 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1601 shift, rc); 1602 } 1603 1604 spapr->htab_shift = shift; 1605 spapr->htab = NULL; 1606 } else { 1607 /* kernel-side HPT not needed, allocate in userspace instead */ 1608 size_t size = 1ULL << shift; 1609 int i; 1610 1611 spapr->htab = qemu_memalign(size, size); 1612 if (!spapr->htab) { 1613 error_setg_errno(errp, errno, 1614 "Could not allocate HPT of order %d", shift); 1615 return; 1616 } 1617 1618 memset(spapr->htab, 0, size); 1619 spapr->htab_shift = shift; 1620 1621 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1622 DIRTY_HPTE(HPTE(spapr->htab, i)); 1623 } 1624 } 1625 /* We're setting up a hash table, so that means we're not radix */ 1626 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1627 } 1628 1629 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) 1630 { 1631 int hpt_shift; 1632 1633 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1634 || (spapr->cas_reboot 1635 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1636 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1637 } else { 1638 uint64_t current_ram_size; 1639 1640 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1641 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1642 } 1643 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1644 1645 if (spapr->vrma_adjust) { 1646 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), 1647 spapr->htab_shift); 1648 } 1649 } 1650 1651 static int spapr_reset_drcs(Object *child, void *opaque) 1652 { 1653 sPAPRDRConnector *drc = 1654 (sPAPRDRConnector *) object_dynamic_cast(child, 1655 TYPE_SPAPR_DR_CONNECTOR); 1656 1657 if (drc) { 1658 spapr_drc_reset(drc); 1659 } 1660 1661 return 0; 1662 } 1663 1664 static void spapr_machine_reset(void) 1665 { 1666 MachineState *machine = MACHINE(qdev_get_machine()); 1667 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1668 PowerPCCPU *first_ppc_cpu; 1669 uint32_t rtas_limit; 1670 hwaddr rtas_addr, fdt_addr; 1671 void *fdt; 1672 int rc; 1673 1674 spapr_caps_apply(spapr); 1675 1676 first_ppc_cpu = POWERPC_CPU(first_cpu); 1677 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1678 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1679 spapr->max_compat_pvr)) { 1680 /* 1681 * If using KVM with radix mode available, VCPUs can be started 1682 * without a HPT because KVM will start them in radix mode. 1683 * Set the GR bit in PATE so that we know there is no HPT. 1684 */ 1685 spapr->patb_entry = PATE1_GR; 1686 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1687 } else { 1688 spapr_setup_hpt_and_vrma(spapr); 1689 } 1690 1691 /* 1692 * If this reset wasn't generated by CAS, we should reset our 1693 * negotiated options and start from scratch 1694 */ 1695 if (!spapr->cas_reboot) { 1696 spapr_ovec_cleanup(spapr->ov5_cas); 1697 spapr->ov5_cas = spapr_ovec_new(); 1698 1699 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal); 1700 } 1701 1702 if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 1703 spapr_irq_msi_reset(spapr); 1704 } 1705 1706 qemu_devices_reset(); 1707 1708 /* 1709 * This is fixing some of the default configuration of the XIVE 1710 * devices. To be called after the reset of the machine devices. 1711 */ 1712 spapr_irq_reset(spapr, &error_fatal); 1713 1714 /* DRC reset may cause a device to be unplugged. This will cause troubles 1715 * if this device is used by another device (eg, a running vhost backend 1716 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1717 * situations, we reset DRCs after all devices have been reset. 1718 */ 1719 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1720 1721 spapr_clear_pending_events(spapr); 1722 1723 /* 1724 * We place the device tree and RTAS just below either the top of the RMA, 1725 * or just below 2GB, whichever is lower, so that it can be 1726 * processed with 32-bit real mode code if necessary 1727 */ 1728 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1729 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1730 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1731 1732 fdt = spapr_build_fdt(spapr); 1733 1734 spapr_load_rtas(spapr, fdt, rtas_addr); 1735 1736 rc = fdt_pack(fdt); 1737 1738 /* Should only fail if we've built a corrupted tree */ 1739 assert(rc == 0); 1740 1741 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1742 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1743 fdt_totalsize(fdt), FDT_MAX_SIZE); 1744 exit(1); 1745 } 1746 1747 /* Load the fdt */ 1748 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1749 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1750 g_free(spapr->fdt_blob); 1751 spapr->fdt_size = fdt_totalsize(fdt); 1752 spapr->fdt_initial_size = spapr->fdt_size; 1753 spapr->fdt_blob = fdt; 1754 1755 /* Set up the entry state */ 1756 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); 1757 first_ppc_cpu->env.gpr[5] = 0; 1758 1759 spapr->cas_reboot = false; 1760 } 1761 1762 static void spapr_create_nvram(sPAPRMachineState *spapr) 1763 { 1764 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1765 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1766 1767 if (dinfo) { 1768 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1769 &error_fatal); 1770 } 1771 1772 qdev_init_nofail(dev); 1773 1774 spapr->nvram = (struct sPAPRNVRAM *)dev; 1775 } 1776 1777 static void spapr_rtc_create(sPAPRMachineState *spapr) 1778 { 1779 object_initialize_child(OBJECT(spapr), "rtc", 1780 &spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1781 &error_fatal, NULL); 1782 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1783 &error_fatal); 1784 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1785 "date", &error_fatal); 1786 } 1787 1788 /* Returns whether we want to use VGA or not */ 1789 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1790 { 1791 switch (vga_interface_type) { 1792 case VGA_NONE: 1793 return false; 1794 case VGA_DEVICE: 1795 return true; 1796 case VGA_STD: 1797 case VGA_VIRTIO: 1798 case VGA_CIRRUS: 1799 return pci_vga_init(pci_bus) != NULL; 1800 default: 1801 error_setg(errp, 1802 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1803 return false; 1804 } 1805 } 1806 1807 static int spapr_pre_load(void *opaque) 1808 { 1809 int rc; 1810 1811 rc = spapr_caps_pre_load(opaque); 1812 if (rc) { 1813 return rc; 1814 } 1815 1816 return 0; 1817 } 1818 1819 static int spapr_post_load(void *opaque, int version_id) 1820 { 1821 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1822 int err = 0; 1823 1824 err = spapr_caps_post_migration(spapr); 1825 if (err) { 1826 return err; 1827 } 1828 1829 /* 1830 * In earlier versions, there was no separate qdev for the PAPR 1831 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1832 * So when migrating from those versions, poke the incoming offset 1833 * value into the RTC device 1834 */ 1835 if (version_id < 3) { 1836 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1837 if (err) { 1838 return err; 1839 } 1840 } 1841 1842 if (kvm_enabled() && spapr->patb_entry) { 1843 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1844 bool radix = !!(spapr->patb_entry & PATE1_GR); 1845 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1846 1847 /* 1848 * Update LPCR:HR and UPRT as they may not be set properly in 1849 * the stream 1850 */ 1851 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1852 LPCR_HR | LPCR_UPRT); 1853 1854 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1855 if (err) { 1856 error_report("Process table config unsupported by the host"); 1857 return -EINVAL; 1858 } 1859 } 1860 1861 err = spapr_irq_post_load(spapr, version_id); 1862 if (err) { 1863 return err; 1864 } 1865 1866 return err; 1867 } 1868 1869 static int spapr_pre_save(void *opaque) 1870 { 1871 int rc; 1872 1873 rc = spapr_caps_pre_save(opaque); 1874 if (rc) { 1875 return rc; 1876 } 1877 1878 return 0; 1879 } 1880 1881 static bool version_before_3(void *opaque, int version_id) 1882 { 1883 return version_id < 3; 1884 } 1885 1886 static bool spapr_pending_events_needed(void *opaque) 1887 { 1888 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1889 return !QTAILQ_EMPTY(&spapr->pending_events); 1890 } 1891 1892 static const VMStateDescription vmstate_spapr_event_entry = { 1893 .name = "spapr_event_log_entry", 1894 .version_id = 1, 1895 .minimum_version_id = 1, 1896 .fields = (VMStateField[]) { 1897 VMSTATE_UINT32(summary, sPAPREventLogEntry), 1898 VMSTATE_UINT32(extended_length, sPAPREventLogEntry), 1899 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0, 1900 NULL, extended_length), 1901 VMSTATE_END_OF_LIST() 1902 }, 1903 }; 1904 1905 static const VMStateDescription vmstate_spapr_pending_events = { 1906 .name = "spapr_pending_events", 1907 .version_id = 1, 1908 .minimum_version_id = 1, 1909 .needed = spapr_pending_events_needed, 1910 .fields = (VMStateField[]) { 1911 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1, 1912 vmstate_spapr_event_entry, sPAPREventLogEntry, next), 1913 VMSTATE_END_OF_LIST() 1914 }, 1915 }; 1916 1917 static bool spapr_ov5_cas_needed(void *opaque) 1918 { 1919 sPAPRMachineState *spapr = opaque; 1920 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1921 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1922 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1923 bool cas_needed; 1924 1925 /* Prior to the introduction of sPAPROptionVector, we had two option 1926 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1927 * Both of these options encode machine topology into the device-tree 1928 * in such a way that the now-booted OS should still be able to interact 1929 * appropriately with QEMU regardless of what options were actually 1930 * negotiatied on the source side. 1931 * 1932 * As such, we can avoid migrating the CAS-negotiated options if these 1933 * are the only options available on the current machine/platform. 1934 * Since these are the only options available for pseries-2.7 and 1935 * earlier, this allows us to maintain old->new/new->old migration 1936 * compatibility. 1937 * 1938 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1939 * via default pseries-2.8 machines and explicit command-line parameters. 1940 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1941 * of the actual CAS-negotiated values to continue working properly. For 1942 * example, availability of memory unplug depends on knowing whether 1943 * OV5_HP_EVT was negotiated via CAS. 1944 * 1945 * Thus, for any cases where the set of available CAS-negotiatable 1946 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1947 * include the CAS-negotiated options in the migration stream, unless 1948 * if they affect boot time behaviour only. 1949 */ 1950 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1951 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1952 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1953 1954 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1955 * the mask itself since in the future it's possible "legacy" bits may be 1956 * removed via machine options, which could generate a false positive 1957 * that breaks migration. 1958 */ 1959 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1960 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1961 1962 spapr_ovec_cleanup(ov5_mask); 1963 spapr_ovec_cleanup(ov5_legacy); 1964 spapr_ovec_cleanup(ov5_removed); 1965 1966 return cas_needed; 1967 } 1968 1969 static const VMStateDescription vmstate_spapr_ov5_cas = { 1970 .name = "spapr_option_vector_ov5_cas", 1971 .version_id = 1, 1972 .minimum_version_id = 1, 1973 .needed = spapr_ov5_cas_needed, 1974 .fields = (VMStateField[]) { 1975 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1976 vmstate_spapr_ovec, sPAPROptionVector), 1977 VMSTATE_END_OF_LIST() 1978 }, 1979 }; 1980 1981 static bool spapr_patb_entry_needed(void *opaque) 1982 { 1983 sPAPRMachineState *spapr = opaque; 1984 1985 return !!spapr->patb_entry; 1986 } 1987 1988 static const VMStateDescription vmstate_spapr_patb_entry = { 1989 .name = "spapr_patb_entry", 1990 .version_id = 1, 1991 .minimum_version_id = 1, 1992 .needed = spapr_patb_entry_needed, 1993 .fields = (VMStateField[]) { 1994 VMSTATE_UINT64(patb_entry, sPAPRMachineState), 1995 VMSTATE_END_OF_LIST() 1996 }, 1997 }; 1998 1999 static bool spapr_irq_map_needed(void *opaque) 2000 { 2001 sPAPRMachineState *spapr = opaque; 2002 2003 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 2004 } 2005 2006 static const VMStateDescription vmstate_spapr_irq_map = { 2007 .name = "spapr_irq_map", 2008 .version_id = 1, 2009 .minimum_version_id = 1, 2010 .needed = spapr_irq_map_needed, 2011 .fields = (VMStateField[]) { 2012 VMSTATE_BITMAP(irq_map, sPAPRMachineState, 0, irq_map_nr), 2013 VMSTATE_END_OF_LIST() 2014 }, 2015 }; 2016 2017 static bool spapr_dtb_needed(void *opaque) 2018 { 2019 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 2020 2021 return smc->update_dt_enabled; 2022 } 2023 2024 static int spapr_dtb_pre_load(void *opaque) 2025 { 2026 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 2027 2028 g_free(spapr->fdt_blob); 2029 spapr->fdt_blob = NULL; 2030 spapr->fdt_size = 0; 2031 2032 return 0; 2033 } 2034 2035 static const VMStateDescription vmstate_spapr_dtb = { 2036 .name = "spapr_dtb", 2037 .version_id = 1, 2038 .minimum_version_id = 1, 2039 .needed = spapr_dtb_needed, 2040 .pre_load = spapr_dtb_pre_load, 2041 .fields = (VMStateField[]) { 2042 VMSTATE_UINT32(fdt_initial_size, sPAPRMachineState), 2043 VMSTATE_UINT32(fdt_size, sPAPRMachineState), 2044 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, sPAPRMachineState, 0, NULL, 2045 fdt_size), 2046 VMSTATE_END_OF_LIST() 2047 }, 2048 }; 2049 2050 static const VMStateDescription vmstate_spapr = { 2051 .name = "spapr", 2052 .version_id = 3, 2053 .minimum_version_id = 1, 2054 .pre_load = spapr_pre_load, 2055 .post_load = spapr_post_load, 2056 .pre_save = spapr_pre_save, 2057 .fields = (VMStateField[]) { 2058 /* used to be @next_irq */ 2059 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2060 2061 /* RTC offset */ 2062 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 2063 2064 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 2065 VMSTATE_END_OF_LIST() 2066 }, 2067 .subsections = (const VMStateDescription*[]) { 2068 &vmstate_spapr_ov5_cas, 2069 &vmstate_spapr_patb_entry, 2070 &vmstate_spapr_pending_events, 2071 &vmstate_spapr_cap_htm, 2072 &vmstate_spapr_cap_vsx, 2073 &vmstate_spapr_cap_dfp, 2074 &vmstate_spapr_cap_cfpc, 2075 &vmstate_spapr_cap_sbbc, 2076 &vmstate_spapr_cap_ibs, 2077 &vmstate_spapr_irq_map, 2078 &vmstate_spapr_cap_nested_kvm_hv, 2079 &vmstate_spapr_dtb, 2080 NULL 2081 } 2082 }; 2083 2084 static int htab_save_setup(QEMUFile *f, void *opaque) 2085 { 2086 sPAPRMachineState *spapr = opaque; 2087 2088 /* "Iteration" header */ 2089 if (!spapr->htab_shift) { 2090 qemu_put_be32(f, -1); 2091 } else { 2092 qemu_put_be32(f, spapr->htab_shift); 2093 } 2094 2095 if (spapr->htab) { 2096 spapr->htab_save_index = 0; 2097 spapr->htab_first_pass = true; 2098 } else { 2099 if (spapr->htab_shift) { 2100 assert(kvm_enabled()); 2101 } 2102 } 2103 2104 2105 return 0; 2106 } 2107 2108 static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr, 2109 int chunkstart, int n_valid, int n_invalid) 2110 { 2111 qemu_put_be32(f, chunkstart); 2112 qemu_put_be16(f, n_valid); 2113 qemu_put_be16(f, n_invalid); 2114 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2115 HASH_PTE_SIZE_64 * n_valid); 2116 } 2117 2118 static void htab_save_end_marker(QEMUFile *f) 2119 { 2120 qemu_put_be32(f, 0); 2121 qemu_put_be16(f, 0); 2122 qemu_put_be16(f, 0); 2123 } 2124 2125 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 2126 int64_t max_ns) 2127 { 2128 bool has_timeout = max_ns != -1; 2129 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2130 int index = spapr->htab_save_index; 2131 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2132 2133 assert(spapr->htab_first_pass); 2134 2135 do { 2136 int chunkstart; 2137 2138 /* Consume invalid HPTEs */ 2139 while ((index < htabslots) 2140 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2141 CLEAN_HPTE(HPTE(spapr->htab, index)); 2142 index++; 2143 } 2144 2145 /* Consume valid HPTEs */ 2146 chunkstart = index; 2147 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2148 && HPTE_VALID(HPTE(spapr->htab, index))) { 2149 CLEAN_HPTE(HPTE(spapr->htab, index)); 2150 index++; 2151 } 2152 2153 if (index > chunkstart) { 2154 int n_valid = index - chunkstart; 2155 2156 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2157 2158 if (has_timeout && 2159 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2160 break; 2161 } 2162 } 2163 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2164 2165 if (index >= htabslots) { 2166 assert(index == htabslots); 2167 index = 0; 2168 spapr->htab_first_pass = false; 2169 } 2170 spapr->htab_save_index = index; 2171 } 2172 2173 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 2174 int64_t max_ns) 2175 { 2176 bool final = max_ns < 0; 2177 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2178 int examined = 0, sent = 0; 2179 int index = spapr->htab_save_index; 2180 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2181 2182 assert(!spapr->htab_first_pass); 2183 2184 do { 2185 int chunkstart, invalidstart; 2186 2187 /* Consume non-dirty HPTEs */ 2188 while ((index < htabslots) 2189 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2190 index++; 2191 examined++; 2192 } 2193 2194 chunkstart = index; 2195 /* Consume valid dirty HPTEs */ 2196 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2197 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2198 && HPTE_VALID(HPTE(spapr->htab, index))) { 2199 CLEAN_HPTE(HPTE(spapr->htab, index)); 2200 index++; 2201 examined++; 2202 } 2203 2204 invalidstart = index; 2205 /* Consume invalid dirty HPTEs */ 2206 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2207 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2208 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2209 CLEAN_HPTE(HPTE(spapr->htab, index)); 2210 index++; 2211 examined++; 2212 } 2213 2214 if (index > chunkstart) { 2215 int n_valid = invalidstart - chunkstart; 2216 int n_invalid = index - invalidstart; 2217 2218 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2219 sent += index - chunkstart; 2220 2221 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2222 break; 2223 } 2224 } 2225 2226 if (examined >= htabslots) { 2227 break; 2228 } 2229 2230 if (index >= htabslots) { 2231 assert(index == htabslots); 2232 index = 0; 2233 } 2234 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2235 2236 if (index >= htabslots) { 2237 assert(index == htabslots); 2238 index = 0; 2239 } 2240 2241 spapr->htab_save_index = index; 2242 2243 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2244 } 2245 2246 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2247 #define MAX_KVM_BUF_SIZE 2048 2248 2249 static int htab_save_iterate(QEMUFile *f, void *opaque) 2250 { 2251 sPAPRMachineState *spapr = opaque; 2252 int fd; 2253 int rc = 0; 2254 2255 /* Iteration header */ 2256 if (!spapr->htab_shift) { 2257 qemu_put_be32(f, -1); 2258 return 1; 2259 } else { 2260 qemu_put_be32(f, 0); 2261 } 2262 2263 if (!spapr->htab) { 2264 assert(kvm_enabled()); 2265 2266 fd = get_htab_fd(spapr); 2267 if (fd < 0) { 2268 return fd; 2269 } 2270 2271 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2272 if (rc < 0) { 2273 return rc; 2274 } 2275 } else if (spapr->htab_first_pass) { 2276 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2277 } else { 2278 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2279 } 2280 2281 htab_save_end_marker(f); 2282 2283 return rc; 2284 } 2285 2286 static int htab_save_complete(QEMUFile *f, void *opaque) 2287 { 2288 sPAPRMachineState *spapr = opaque; 2289 int fd; 2290 2291 /* Iteration header */ 2292 if (!spapr->htab_shift) { 2293 qemu_put_be32(f, -1); 2294 return 0; 2295 } else { 2296 qemu_put_be32(f, 0); 2297 } 2298 2299 if (!spapr->htab) { 2300 int rc; 2301 2302 assert(kvm_enabled()); 2303 2304 fd = get_htab_fd(spapr); 2305 if (fd < 0) { 2306 return fd; 2307 } 2308 2309 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2310 if (rc < 0) { 2311 return rc; 2312 } 2313 } else { 2314 if (spapr->htab_first_pass) { 2315 htab_save_first_pass(f, spapr, -1); 2316 } 2317 htab_save_later_pass(f, spapr, -1); 2318 } 2319 2320 /* End marker */ 2321 htab_save_end_marker(f); 2322 2323 return 0; 2324 } 2325 2326 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2327 { 2328 sPAPRMachineState *spapr = opaque; 2329 uint32_t section_hdr; 2330 int fd = -1; 2331 Error *local_err = NULL; 2332 2333 if (version_id < 1 || version_id > 1) { 2334 error_report("htab_load() bad version"); 2335 return -EINVAL; 2336 } 2337 2338 section_hdr = qemu_get_be32(f); 2339 2340 if (section_hdr == -1) { 2341 spapr_free_hpt(spapr); 2342 return 0; 2343 } 2344 2345 if (section_hdr) { 2346 /* First section gives the htab size */ 2347 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2348 if (local_err) { 2349 error_report_err(local_err); 2350 return -EINVAL; 2351 } 2352 return 0; 2353 } 2354 2355 if (!spapr->htab) { 2356 assert(kvm_enabled()); 2357 2358 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2359 if (fd < 0) { 2360 error_report_err(local_err); 2361 return fd; 2362 } 2363 } 2364 2365 while (true) { 2366 uint32_t index; 2367 uint16_t n_valid, n_invalid; 2368 2369 index = qemu_get_be32(f); 2370 n_valid = qemu_get_be16(f); 2371 n_invalid = qemu_get_be16(f); 2372 2373 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2374 /* End of Stream */ 2375 break; 2376 } 2377 2378 if ((index + n_valid + n_invalid) > 2379 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2380 /* Bad index in stream */ 2381 error_report( 2382 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2383 index, n_valid, n_invalid, spapr->htab_shift); 2384 return -EINVAL; 2385 } 2386 2387 if (spapr->htab) { 2388 if (n_valid) { 2389 qemu_get_buffer(f, HPTE(spapr->htab, index), 2390 HASH_PTE_SIZE_64 * n_valid); 2391 } 2392 if (n_invalid) { 2393 memset(HPTE(spapr->htab, index + n_valid), 0, 2394 HASH_PTE_SIZE_64 * n_invalid); 2395 } 2396 } else { 2397 int rc; 2398 2399 assert(fd >= 0); 2400 2401 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2402 if (rc < 0) { 2403 return rc; 2404 } 2405 } 2406 } 2407 2408 if (!spapr->htab) { 2409 assert(fd >= 0); 2410 close(fd); 2411 } 2412 2413 return 0; 2414 } 2415 2416 static void htab_save_cleanup(void *opaque) 2417 { 2418 sPAPRMachineState *spapr = opaque; 2419 2420 close_htab_fd(spapr); 2421 } 2422 2423 static SaveVMHandlers savevm_htab_handlers = { 2424 .save_setup = htab_save_setup, 2425 .save_live_iterate = htab_save_iterate, 2426 .save_live_complete_precopy = htab_save_complete, 2427 .save_cleanup = htab_save_cleanup, 2428 .load_state = htab_load, 2429 }; 2430 2431 static void spapr_boot_set(void *opaque, const char *boot_device, 2432 Error **errp) 2433 { 2434 MachineState *machine = MACHINE(opaque); 2435 machine->boot_order = g_strdup(boot_device); 2436 } 2437 2438 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 2439 { 2440 MachineState *machine = MACHINE(spapr); 2441 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2442 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2443 int i; 2444 2445 for (i = 0; i < nr_lmbs; i++) { 2446 uint64_t addr; 2447 2448 addr = i * lmb_size + machine->device_memory->base; 2449 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2450 addr / lmb_size); 2451 } 2452 } 2453 2454 /* 2455 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2456 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2457 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2458 */ 2459 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2460 { 2461 int i; 2462 2463 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2464 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2465 " is not aligned to %" PRIu64 " MiB", 2466 machine->ram_size, 2467 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2468 return; 2469 } 2470 2471 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2472 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2473 " is not aligned to %" PRIu64 " MiB", 2474 machine->ram_size, 2475 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2476 return; 2477 } 2478 2479 for (i = 0; i < nb_numa_nodes; i++) { 2480 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2481 error_setg(errp, 2482 "Node %d memory size 0x%" PRIx64 2483 " is not aligned to %" PRIu64 " MiB", 2484 i, numa_info[i].node_mem, 2485 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2486 return; 2487 } 2488 } 2489 } 2490 2491 /* find cpu slot in machine->possible_cpus by core_id */ 2492 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2493 { 2494 int index = id / smp_threads; 2495 2496 if (index >= ms->possible_cpus->len) { 2497 return NULL; 2498 } 2499 if (idx) { 2500 *idx = index; 2501 } 2502 return &ms->possible_cpus->cpus[index]; 2503 } 2504 2505 static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp) 2506 { 2507 Error *local_err = NULL; 2508 bool vsmt_user = !!spapr->vsmt; 2509 int kvm_smt = kvmppc_smt_threads(); 2510 int ret; 2511 2512 if (!kvm_enabled() && (smp_threads > 1)) { 2513 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2514 "on a pseries machine"); 2515 goto out; 2516 } 2517 if (!is_power_of_2(smp_threads)) { 2518 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2519 "machine because it must be a power of 2", smp_threads); 2520 goto out; 2521 } 2522 2523 /* Detemine the VSMT mode to use: */ 2524 if (vsmt_user) { 2525 if (spapr->vsmt < smp_threads) { 2526 error_setg(&local_err, "Cannot support VSMT mode %d" 2527 " because it must be >= threads/core (%d)", 2528 spapr->vsmt, smp_threads); 2529 goto out; 2530 } 2531 /* In this case, spapr->vsmt has been set by the command line */ 2532 } else { 2533 /* 2534 * Default VSMT value is tricky, because we need it to be as 2535 * consistent as possible (for migration), but this requires 2536 * changing it for at least some existing cases. We pick 8 as 2537 * the value that we'd get with KVM on POWER8, the 2538 * overwhelmingly common case in production systems. 2539 */ 2540 spapr->vsmt = MAX(8, smp_threads); 2541 } 2542 2543 /* KVM: If necessary, set the SMT mode: */ 2544 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2545 ret = kvmppc_set_smt_threads(spapr->vsmt); 2546 if (ret) { 2547 /* Looks like KVM isn't able to change VSMT mode */ 2548 error_setg(&local_err, 2549 "Failed to set KVM's VSMT mode to %d (errno %d)", 2550 spapr->vsmt, ret); 2551 /* We can live with that if the default one is big enough 2552 * for the number of threads, and a submultiple of the one 2553 * we want. In this case we'll waste some vcpu ids, but 2554 * behaviour will be correct */ 2555 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2556 warn_report_err(local_err); 2557 local_err = NULL; 2558 goto out; 2559 } else { 2560 if (!vsmt_user) { 2561 error_append_hint(&local_err, 2562 "On PPC, a VM with %d threads/core" 2563 " on a host with %d threads/core" 2564 " requires the use of VSMT mode %d.\n", 2565 smp_threads, kvm_smt, spapr->vsmt); 2566 } 2567 kvmppc_hint_smt_possible(&local_err); 2568 goto out; 2569 } 2570 } 2571 } 2572 /* else TCG: nothing to do currently */ 2573 out: 2574 error_propagate(errp, local_err); 2575 } 2576 2577 static void spapr_init_cpus(sPAPRMachineState *spapr) 2578 { 2579 MachineState *machine = MACHINE(spapr); 2580 MachineClass *mc = MACHINE_GET_CLASS(machine); 2581 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2582 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2583 const CPUArchIdList *possible_cpus; 2584 int boot_cores_nr = smp_cpus / smp_threads; 2585 int i; 2586 2587 possible_cpus = mc->possible_cpu_arch_ids(machine); 2588 if (mc->has_hotpluggable_cpus) { 2589 if (smp_cpus % smp_threads) { 2590 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2591 smp_cpus, smp_threads); 2592 exit(1); 2593 } 2594 if (max_cpus % smp_threads) { 2595 error_report("max_cpus (%u) must be multiple of threads (%u)", 2596 max_cpus, smp_threads); 2597 exit(1); 2598 } 2599 } else { 2600 if (max_cpus != smp_cpus) { 2601 error_report("This machine version does not support CPU hotplug"); 2602 exit(1); 2603 } 2604 boot_cores_nr = possible_cpus->len; 2605 } 2606 2607 if (smc->pre_2_10_has_unused_icps) { 2608 int i; 2609 2610 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2611 /* Dummy entries get deregistered when real ICPState objects 2612 * are registered during CPU core hotplug. 2613 */ 2614 pre_2_10_vmstate_register_dummy_icp(i); 2615 } 2616 } 2617 2618 for (i = 0; i < possible_cpus->len; i++) { 2619 int core_id = i * smp_threads; 2620 2621 if (mc->has_hotpluggable_cpus) { 2622 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2623 spapr_vcpu_id(spapr, core_id)); 2624 } 2625 2626 if (i < boot_cores_nr) { 2627 Object *core = object_new(type); 2628 int nr_threads = smp_threads; 2629 2630 /* Handle the partially filled core for older machine types */ 2631 if ((i + 1) * smp_threads >= smp_cpus) { 2632 nr_threads = smp_cpus - i * smp_threads; 2633 } 2634 2635 object_property_set_int(core, nr_threads, "nr-threads", 2636 &error_fatal); 2637 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2638 &error_fatal); 2639 object_property_set_bool(core, true, "realized", &error_fatal); 2640 2641 object_unref(core); 2642 } 2643 } 2644 } 2645 2646 static PCIHostState *spapr_create_default_phb(void) 2647 { 2648 DeviceState *dev; 2649 2650 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); 2651 qdev_prop_set_uint32(dev, "index", 0); 2652 qdev_init_nofail(dev); 2653 2654 return PCI_HOST_BRIDGE(dev); 2655 } 2656 2657 /* pSeries LPAR / sPAPR hardware init */ 2658 static void spapr_machine_init(MachineState *machine) 2659 { 2660 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2661 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2662 const char *kernel_filename = machine->kernel_filename; 2663 const char *initrd_filename = machine->initrd_filename; 2664 PCIHostState *phb; 2665 int i; 2666 MemoryRegion *sysmem = get_system_memory(); 2667 MemoryRegion *ram = g_new(MemoryRegion, 1); 2668 hwaddr node0_size = spapr_node0_size(machine); 2669 long load_limit, fw_size; 2670 char *filename; 2671 Error *resize_hpt_err = NULL; 2672 2673 msi_nonbroken = true; 2674 2675 QLIST_INIT(&spapr->phbs); 2676 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2677 2678 /* Determine capabilities to run with */ 2679 spapr_caps_init(spapr); 2680 2681 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2682 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2683 /* 2684 * If the user explicitly requested a mode we should either 2685 * supply it, or fail completely (which we do below). But if 2686 * it's not set explicitly, we reset our mode to something 2687 * that works 2688 */ 2689 if (resize_hpt_err) { 2690 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2691 error_free(resize_hpt_err); 2692 resize_hpt_err = NULL; 2693 } else { 2694 spapr->resize_hpt = smc->resize_hpt_default; 2695 } 2696 } 2697 2698 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2699 2700 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2701 /* 2702 * User requested HPT resize, but this host can't supply it. Bail out 2703 */ 2704 error_report_err(resize_hpt_err); 2705 exit(1); 2706 } 2707 2708 spapr->rma_size = node0_size; 2709 2710 /* With KVM, we don't actually know whether KVM supports an 2711 * unbounded RMA (PR KVM) or is limited by the hash table size 2712 * (HV KVM using VRMA), so we always assume the latter 2713 * 2714 * In that case, we also limit the initial allocations for RTAS 2715 * etc... to 256M since we have no way to know what the VRMA size 2716 * is going to be as it depends on the size of the hash table 2717 * which isn't determined yet. 2718 */ 2719 if (kvm_enabled()) { 2720 spapr->vrma_adjust = 1; 2721 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2722 } 2723 2724 /* Actually we don't support unbounded RMA anymore since we added 2725 * proper emulation of HV mode. The max we can get is 16G which 2726 * also happens to be what we configure for PAPR mode so make sure 2727 * we don't do anything bigger than that 2728 */ 2729 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2730 2731 if (spapr->rma_size > node0_size) { 2732 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2733 spapr->rma_size); 2734 exit(1); 2735 } 2736 2737 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2738 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2739 2740 /* 2741 * VSMT must be set in order to be able to compute VCPU ids, ie to 2742 * call spapr_max_server_number() or spapr_vcpu_id(). 2743 */ 2744 spapr_set_vsmt_mode(spapr, &error_fatal); 2745 2746 /* Set up Interrupt Controller before we create the VCPUs */ 2747 spapr_irq_init(spapr, &error_fatal); 2748 2749 /* Set up containers for ibm,client-architecture-support negotiated options 2750 */ 2751 spapr->ov5 = spapr_ovec_new(); 2752 spapr->ov5_cas = spapr_ovec_new(); 2753 2754 if (smc->dr_lmb_enabled) { 2755 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2756 spapr_validate_node_memory(machine, &error_fatal); 2757 } 2758 2759 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2760 2761 /* advertise support for dedicated HP event source to guests */ 2762 if (spapr->use_hotplug_event_source) { 2763 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2764 } 2765 2766 /* advertise support for HPT resizing */ 2767 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2768 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2769 } 2770 2771 /* advertise support for ibm,dyamic-memory-v2 */ 2772 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2773 2774 /* advertise XIVE on POWER9 machines */ 2775 if (spapr->irq->ov5 & (SPAPR_OV5_XIVE_EXPLOIT | SPAPR_OV5_XIVE_BOTH)) { 2776 if (ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 2777 0, spapr->max_compat_pvr)) { 2778 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2779 } else if (spapr->irq->ov5 & SPAPR_OV5_XIVE_EXPLOIT) { 2780 error_report("XIVE-only machines require a POWER9 CPU"); 2781 exit(1); 2782 } 2783 } 2784 2785 /* init CPUs */ 2786 spapr_init_cpus(spapr); 2787 2788 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2789 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2790 spapr->max_compat_pvr)) { 2791 /* KVM and TCG always allow GTSE with radix... */ 2792 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2793 } 2794 /* ... but not with hash (currently). */ 2795 2796 if (kvm_enabled()) { 2797 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2798 kvmppc_enable_logical_ci_hcalls(); 2799 kvmppc_enable_set_mode_hcall(); 2800 2801 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2802 kvmppc_enable_clear_ref_mod_hcalls(); 2803 } 2804 2805 /* allocate RAM */ 2806 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2807 machine->ram_size); 2808 memory_region_add_subregion(sysmem, 0, ram); 2809 2810 /* always allocate the device memory information */ 2811 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2812 2813 /* initialize hotplug memory address space */ 2814 if (machine->ram_size < machine->maxram_size) { 2815 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2816 /* 2817 * Limit the number of hotpluggable memory slots to half the number 2818 * slots that KVM supports, leaving the other half for PCI and other 2819 * devices. However ensure that number of slots doesn't drop below 32. 2820 */ 2821 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2822 SPAPR_MAX_RAM_SLOTS; 2823 2824 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2825 max_memslots = SPAPR_MAX_RAM_SLOTS; 2826 } 2827 if (machine->ram_slots > max_memslots) { 2828 error_report("Specified number of memory slots %" 2829 PRIu64" exceeds max supported %d", 2830 machine->ram_slots, max_memslots); 2831 exit(1); 2832 } 2833 2834 machine->device_memory->base = ROUND_UP(machine->ram_size, 2835 SPAPR_DEVICE_MEM_ALIGN); 2836 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2837 "device-memory", device_mem_size); 2838 memory_region_add_subregion(sysmem, machine->device_memory->base, 2839 &machine->device_memory->mr); 2840 } 2841 2842 if (smc->dr_lmb_enabled) { 2843 spapr_create_lmb_dr_connectors(spapr); 2844 } 2845 2846 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2847 if (!filename) { 2848 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2849 exit(1); 2850 } 2851 spapr->rtas_size = get_image_size(filename); 2852 if (spapr->rtas_size < 0) { 2853 error_report("Could not get size of LPAR rtas '%s'", filename); 2854 exit(1); 2855 } 2856 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2857 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2858 error_report("Could not load LPAR rtas '%s'", filename); 2859 exit(1); 2860 } 2861 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2862 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2863 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2864 exit(1); 2865 } 2866 g_free(filename); 2867 2868 /* Set up RTAS event infrastructure */ 2869 spapr_events_init(spapr); 2870 2871 /* Set up the RTC RTAS interfaces */ 2872 spapr_rtc_create(spapr); 2873 2874 /* Set up VIO bus */ 2875 spapr->vio_bus = spapr_vio_bus_init(); 2876 2877 for (i = 0; i < serial_max_hds(); i++) { 2878 if (serial_hd(i)) { 2879 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2880 } 2881 } 2882 2883 /* We always have at least the nvram device on VIO */ 2884 spapr_create_nvram(spapr); 2885 2886 /* 2887 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2888 * connectors (described in root DT node's "ibm,drc-types" property) 2889 * are pre-initialized here. additional child connectors (such as 2890 * connectors for a PHBs PCI slots) are added as needed during their 2891 * parent's realization. 2892 */ 2893 if (smc->dr_phb_enabled) { 2894 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2895 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2896 } 2897 } 2898 2899 /* Set up PCI */ 2900 spapr_pci_rtas_init(); 2901 2902 phb = spapr_create_default_phb(); 2903 2904 for (i = 0; i < nb_nics; i++) { 2905 NICInfo *nd = &nd_table[i]; 2906 2907 if (!nd->model) { 2908 nd->model = g_strdup("spapr-vlan"); 2909 } 2910 2911 if (g_str_equal(nd->model, "spapr-vlan") || 2912 g_str_equal(nd->model, "ibmveth")) { 2913 spapr_vlan_create(spapr->vio_bus, nd); 2914 } else { 2915 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2916 } 2917 } 2918 2919 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2920 spapr_vscsi_create(spapr->vio_bus); 2921 } 2922 2923 /* Graphics */ 2924 if (spapr_vga_init(phb->bus, &error_fatal)) { 2925 spapr->has_graphics = true; 2926 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2927 } 2928 2929 if (machine->usb) { 2930 if (smc->use_ohci_by_default) { 2931 pci_create_simple(phb->bus, -1, "pci-ohci"); 2932 } else { 2933 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2934 } 2935 2936 if (spapr->has_graphics) { 2937 USBBus *usb_bus = usb_bus_find(-1); 2938 2939 usb_create_simple(usb_bus, "usb-kbd"); 2940 usb_create_simple(usb_bus, "usb-mouse"); 2941 } 2942 } 2943 2944 if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) { 2945 error_report( 2946 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2947 MIN_RMA_SLOF); 2948 exit(1); 2949 } 2950 2951 if (kernel_filename) { 2952 uint64_t lowaddr = 0; 2953 2954 spapr->kernel_size = load_elf(kernel_filename, NULL, 2955 translate_kernel_address, NULL, 2956 NULL, &lowaddr, NULL, 1, 2957 PPC_ELF_MACHINE, 0, 0); 2958 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2959 spapr->kernel_size = load_elf(kernel_filename, NULL, 2960 translate_kernel_address, NULL, NULL, 2961 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2962 0, 0); 2963 spapr->kernel_le = spapr->kernel_size > 0; 2964 } 2965 if (spapr->kernel_size < 0) { 2966 error_report("error loading %s: %s", kernel_filename, 2967 load_elf_strerror(spapr->kernel_size)); 2968 exit(1); 2969 } 2970 2971 /* load initrd */ 2972 if (initrd_filename) { 2973 /* Try to locate the initrd in the gap between the kernel 2974 * and the firmware. Add a bit of space just in case 2975 */ 2976 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2977 + 0x1ffff) & ~0xffff; 2978 spapr->initrd_size = load_image_targphys(initrd_filename, 2979 spapr->initrd_base, 2980 load_limit 2981 - spapr->initrd_base); 2982 if (spapr->initrd_size < 0) { 2983 error_report("could not load initial ram disk '%s'", 2984 initrd_filename); 2985 exit(1); 2986 } 2987 } 2988 } 2989 2990 if (bios_name == NULL) { 2991 bios_name = FW_FILE_NAME; 2992 } 2993 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2994 if (!filename) { 2995 error_report("Could not find LPAR firmware '%s'", bios_name); 2996 exit(1); 2997 } 2998 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2999 if (fw_size <= 0) { 3000 error_report("Could not load LPAR firmware '%s'", filename); 3001 exit(1); 3002 } 3003 g_free(filename); 3004 3005 /* FIXME: Should register things through the MachineState's qdev 3006 * interface, this is a legacy from the sPAPREnvironment structure 3007 * which predated MachineState but had a similar function */ 3008 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3009 register_savevm_live(NULL, "spapr/htab", -1, 1, 3010 &savevm_htab_handlers, spapr); 3011 3012 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine), 3013 &error_fatal); 3014 3015 qemu_register_boot_set(spapr_boot_set, spapr); 3016 3017 if (kvm_enabled()) { 3018 /* to stop and start vmclock */ 3019 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3020 &spapr->tb); 3021 3022 kvmppc_spapr_enable_inkernel_multitce(); 3023 } 3024 } 3025 3026 static int spapr_kvm_type(const char *vm_type) 3027 { 3028 if (!vm_type) { 3029 return 0; 3030 } 3031 3032 if (!strcmp(vm_type, "HV")) { 3033 return 1; 3034 } 3035 3036 if (!strcmp(vm_type, "PR")) { 3037 return 2; 3038 } 3039 3040 error_report("Unknown kvm-type specified '%s'", vm_type); 3041 exit(1); 3042 } 3043 3044 /* 3045 * Implementation of an interface to adjust firmware path 3046 * for the bootindex property handling. 3047 */ 3048 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3049 DeviceState *dev) 3050 { 3051 #define CAST(type, obj, name) \ 3052 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3053 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3054 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3055 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3056 3057 if (d) { 3058 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3059 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3060 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3061 3062 if (spapr) { 3063 /* 3064 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3065 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3066 * 0x8000 | (target << 8) | (bus << 5) | lun 3067 * (see the "Logical unit addressing format" table in SAM5) 3068 */ 3069 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3070 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3071 (uint64_t)id << 48); 3072 } else if (virtio) { 3073 /* 3074 * We use SRP luns of the form 01000000 | (target << 8) | lun 3075 * in the top 32 bits of the 64-bit LUN 3076 * Note: the quote above is from SLOF and it is wrong, 3077 * the actual binding is: 3078 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3079 */ 3080 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3081 if (d->lun >= 256) { 3082 /* Use the LUN "flat space addressing method" */ 3083 id |= 0x4000; 3084 } 3085 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3086 (uint64_t)id << 32); 3087 } else if (usb) { 3088 /* 3089 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3090 * in the top 32 bits of the 64-bit LUN 3091 */ 3092 unsigned usb_port = atoi(usb->port->path); 3093 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3094 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3095 (uint64_t)id << 32); 3096 } 3097 } 3098 3099 /* 3100 * SLOF probes the USB devices, and if it recognizes that the device is a 3101 * storage device, it changes its name to "storage" instead of "usb-host", 3102 * and additionally adds a child node for the SCSI LUN, so the correct 3103 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3104 */ 3105 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3106 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3107 if (usb_host_dev_is_scsi_storage(usbdev)) { 3108 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3109 } 3110 } 3111 3112 if (phb) { 3113 /* Replace "pci" with "pci@800000020000000" */ 3114 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3115 } 3116 3117 if (vsc) { 3118 /* Same logic as virtio above */ 3119 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3120 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3121 } 3122 3123 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3124 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3125 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3126 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3127 } 3128 3129 return NULL; 3130 } 3131 3132 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3133 { 3134 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3135 3136 return g_strdup(spapr->kvm_type); 3137 } 3138 3139 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3140 { 3141 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3142 3143 g_free(spapr->kvm_type); 3144 spapr->kvm_type = g_strdup(value); 3145 } 3146 3147 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3148 { 3149 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3150 3151 return spapr->use_hotplug_event_source; 3152 } 3153 3154 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3155 Error **errp) 3156 { 3157 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3158 3159 spapr->use_hotplug_event_source = value; 3160 } 3161 3162 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3163 { 3164 return true; 3165 } 3166 3167 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3168 { 3169 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3170 3171 switch (spapr->resize_hpt) { 3172 case SPAPR_RESIZE_HPT_DEFAULT: 3173 return g_strdup("default"); 3174 case SPAPR_RESIZE_HPT_DISABLED: 3175 return g_strdup("disabled"); 3176 case SPAPR_RESIZE_HPT_ENABLED: 3177 return g_strdup("enabled"); 3178 case SPAPR_RESIZE_HPT_REQUIRED: 3179 return g_strdup("required"); 3180 } 3181 g_assert_not_reached(); 3182 } 3183 3184 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3185 { 3186 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3187 3188 if (strcmp(value, "default") == 0) { 3189 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3190 } else if (strcmp(value, "disabled") == 0) { 3191 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3192 } else if (strcmp(value, "enabled") == 0) { 3193 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3194 } else if (strcmp(value, "required") == 0) { 3195 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3196 } else { 3197 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3198 } 3199 } 3200 3201 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 3202 void *opaque, Error **errp) 3203 { 3204 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3205 } 3206 3207 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 3208 void *opaque, Error **errp) 3209 { 3210 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 3211 } 3212 3213 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3214 { 3215 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3216 3217 if (spapr->irq == &spapr_irq_xics_legacy) { 3218 return g_strdup("legacy"); 3219 } else if (spapr->irq == &spapr_irq_xics) { 3220 return g_strdup("xics"); 3221 } else if (spapr->irq == &spapr_irq_xive) { 3222 return g_strdup("xive"); 3223 } else if (spapr->irq == &spapr_irq_dual) { 3224 return g_strdup("dual"); 3225 } 3226 g_assert_not_reached(); 3227 } 3228 3229 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3230 { 3231 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3232 3233 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3234 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3235 return; 3236 } 3237 3238 /* The legacy IRQ backend can not be set */ 3239 if (strcmp(value, "xics") == 0) { 3240 spapr->irq = &spapr_irq_xics; 3241 } else if (strcmp(value, "xive") == 0) { 3242 spapr->irq = &spapr_irq_xive; 3243 } else if (strcmp(value, "dual") == 0) { 3244 spapr->irq = &spapr_irq_dual; 3245 } else { 3246 error_setg(errp, "Bad value for \"ic-mode\" property"); 3247 } 3248 } 3249 3250 static char *spapr_get_host_model(Object *obj, Error **errp) 3251 { 3252 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3253 3254 return g_strdup(spapr->host_model); 3255 } 3256 3257 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3258 { 3259 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3260 3261 g_free(spapr->host_model); 3262 spapr->host_model = g_strdup(value); 3263 } 3264 3265 static char *spapr_get_host_serial(Object *obj, Error **errp) 3266 { 3267 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3268 3269 return g_strdup(spapr->host_serial); 3270 } 3271 3272 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3273 { 3274 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3275 3276 g_free(spapr->host_serial); 3277 spapr->host_serial = g_strdup(value); 3278 } 3279 3280 static void spapr_instance_init(Object *obj) 3281 { 3282 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3283 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3284 3285 spapr->htab_fd = -1; 3286 spapr->use_hotplug_event_source = true; 3287 object_property_add_str(obj, "kvm-type", 3288 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 3289 object_property_set_description(obj, "kvm-type", 3290 "Specifies the KVM virtualization mode (HV, PR)", 3291 NULL); 3292 object_property_add_bool(obj, "modern-hotplug-events", 3293 spapr_get_modern_hotplug_events, 3294 spapr_set_modern_hotplug_events, 3295 NULL); 3296 object_property_set_description(obj, "modern-hotplug-events", 3297 "Use dedicated hotplug event mechanism in" 3298 " place of standard EPOW events when possible" 3299 " (required for memory hot-unplug support)", 3300 NULL); 3301 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3302 "Maximum permitted CPU compatibility mode", 3303 &error_fatal); 3304 3305 object_property_add_str(obj, "resize-hpt", 3306 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 3307 object_property_set_description(obj, "resize-hpt", 3308 "Resizing of the Hash Page Table (enabled, disabled, required)", 3309 NULL); 3310 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 3311 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 3312 object_property_set_description(obj, "vsmt", 3313 "Virtual SMT: KVM behaves as if this were" 3314 " the host's SMT mode", &error_abort); 3315 object_property_add_bool(obj, "vfio-no-msix-emulation", 3316 spapr_get_msix_emulation, NULL, NULL); 3317 3318 /* The machine class defines the default interrupt controller mode */ 3319 spapr->irq = smc->irq; 3320 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3321 spapr_set_ic_mode, NULL); 3322 object_property_set_description(obj, "ic-mode", 3323 "Specifies the interrupt controller mode (xics, xive, dual)", 3324 NULL); 3325 3326 object_property_add_str(obj, "host-model", 3327 spapr_get_host_model, spapr_set_host_model, 3328 &error_abort); 3329 object_property_set_description(obj, "host-model", 3330 "Set host's model-id to use - none|passthrough|string", &error_abort); 3331 object_property_add_str(obj, "host-serial", 3332 spapr_get_host_serial, spapr_set_host_serial, 3333 &error_abort); 3334 object_property_set_description(obj, "host-serial", 3335 "Set host's system-id to use - none|passthrough|string", &error_abort); 3336 } 3337 3338 static void spapr_machine_finalizefn(Object *obj) 3339 { 3340 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3341 3342 g_free(spapr->kvm_type); 3343 } 3344 3345 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3346 { 3347 cpu_synchronize_state(cs); 3348 ppc_cpu_do_system_reset(cs); 3349 } 3350 3351 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3352 { 3353 CPUState *cs; 3354 3355 CPU_FOREACH(cs) { 3356 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3357 } 3358 } 3359 3360 int spapr_lmb_dt_populate(sPAPRDRConnector *drc, sPAPRMachineState *spapr, 3361 void *fdt, int *fdt_start_offset, Error **errp) 3362 { 3363 uint64_t addr; 3364 uint32_t node; 3365 3366 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3367 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3368 &error_abort); 3369 *fdt_start_offset = spapr_populate_memory_node(fdt, node, addr, 3370 SPAPR_MEMORY_BLOCK_SIZE); 3371 return 0; 3372 } 3373 3374 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3375 bool dedicated_hp_event_source, Error **errp) 3376 { 3377 sPAPRDRConnector *drc; 3378 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3379 int i; 3380 uint64_t addr = addr_start; 3381 bool hotplugged = spapr_drc_hotplugged(dev); 3382 Error *local_err = NULL; 3383 3384 for (i = 0; i < nr_lmbs; i++) { 3385 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3386 addr / SPAPR_MEMORY_BLOCK_SIZE); 3387 g_assert(drc); 3388 3389 spapr_drc_attach(drc, dev, &local_err); 3390 if (local_err) { 3391 while (addr > addr_start) { 3392 addr -= SPAPR_MEMORY_BLOCK_SIZE; 3393 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3394 addr / SPAPR_MEMORY_BLOCK_SIZE); 3395 spapr_drc_detach(drc); 3396 } 3397 error_propagate(errp, local_err); 3398 return; 3399 } 3400 if (!hotplugged) { 3401 spapr_drc_reset(drc); 3402 } 3403 addr += SPAPR_MEMORY_BLOCK_SIZE; 3404 } 3405 /* send hotplug notification to the 3406 * guest only in case of hotplugged memory 3407 */ 3408 if (hotplugged) { 3409 if (dedicated_hp_event_source) { 3410 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3411 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3412 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3413 nr_lmbs, 3414 spapr_drc_index(drc)); 3415 } else { 3416 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3417 nr_lmbs); 3418 } 3419 } 3420 } 3421 3422 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3423 Error **errp) 3424 { 3425 Error *local_err = NULL; 3426 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3427 PCDIMMDevice *dimm = PC_DIMM(dev); 3428 uint64_t size, addr; 3429 3430 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3431 3432 pc_dimm_plug(dimm, MACHINE(ms), &local_err); 3433 if (local_err) { 3434 goto out; 3435 } 3436 3437 addr = object_property_get_uint(OBJECT(dimm), 3438 PC_DIMM_ADDR_PROP, &local_err); 3439 if (local_err) { 3440 goto out_unplug; 3441 } 3442 3443 spapr_add_lmbs(dev, addr, size, spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3444 &local_err); 3445 if (local_err) { 3446 goto out_unplug; 3447 } 3448 3449 return; 3450 3451 out_unplug: 3452 pc_dimm_unplug(dimm, MACHINE(ms)); 3453 out: 3454 error_propagate(errp, local_err); 3455 } 3456 3457 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3458 Error **errp) 3459 { 3460 const sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3461 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3462 PCDIMMDevice *dimm = PC_DIMM(dev); 3463 Error *local_err = NULL; 3464 uint64_t size; 3465 Object *memdev; 3466 hwaddr pagesize; 3467 3468 if (!smc->dr_lmb_enabled) { 3469 error_setg(errp, "Memory hotplug not supported for this machine"); 3470 return; 3471 } 3472 3473 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3474 if (local_err) { 3475 error_propagate(errp, local_err); 3476 return; 3477 } 3478 3479 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3480 error_setg(errp, "Hotplugged memory size must be a multiple of " 3481 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3482 return; 3483 } 3484 3485 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3486 &error_abort); 3487 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3488 spapr_check_pagesize(spapr, pagesize, &local_err); 3489 if (local_err) { 3490 error_propagate(errp, local_err); 3491 return; 3492 } 3493 3494 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3495 } 3496 3497 struct sPAPRDIMMState { 3498 PCDIMMDevice *dimm; 3499 uint32_t nr_lmbs; 3500 QTAILQ_ENTRY(sPAPRDIMMState) next; 3501 }; 3502 3503 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, 3504 PCDIMMDevice *dimm) 3505 { 3506 sPAPRDIMMState *dimm_state = NULL; 3507 3508 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3509 if (dimm_state->dimm == dimm) { 3510 break; 3511 } 3512 } 3513 return dimm_state; 3514 } 3515 3516 static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, 3517 uint32_t nr_lmbs, 3518 PCDIMMDevice *dimm) 3519 { 3520 sPAPRDIMMState *ds = NULL; 3521 3522 /* 3523 * If this request is for a DIMM whose removal had failed earlier 3524 * (due to guest's refusal to remove the LMBs), we would have this 3525 * dimm already in the pending_dimm_unplugs list. In that 3526 * case don't add again. 3527 */ 3528 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3529 if (!ds) { 3530 ds = g_malloc0(sizeof(sPAPRDIMMState)); 3531 ds->nr_lmbs = nr_lmbs; 3532 ds->dimm = dimm; 3533 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3534 } 3535 return ds; 3536 } 3537 3538 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, 3539 sPAPRDIMMState *dimm_state) 3540 { 3541 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3542 g_free(dimm_state); 3543 } 3544 3545 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, 3546 PCDIMMDevice *dimm) 3547 { 3548 sPAPRDRConnector *drc; 3549 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3550 &error_abort); 3551 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3552 uint32_t avail_lmbs = 0; 3553 uint64_t addr_start, addr; 3554 int i; 3555 3556 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3557 &error_abort); 3558 3559 addr = addr_start; 3560 for (i = 0; i < nr_lmbs; i++) { 3561 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3562 addr / SPAPR_MEMORY_BLOCK_SIZE); 3563 g_assert(drc); 3564 if (drc->dev) { 3565 avail_lmbs++; 3566 } 3567 addr += SPAPR_MEMORY_BLOCK_SIZE; 3568 } 3569 3570 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3571 } 3572 3573 /* Callback to be called during DRC release. */ 3574 void spapr_lmb_release(DeviceState *dev) 3575 { 3576 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3577 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3578 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3579 3580 /* This information will get lost if a migration occurs 3581 * during the unplug process. In this case recover it. */ 3582 if (ds == NULL) { 3583 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3584 g_assert(ds); 3585 /* The DRC being examined by the caller at least must be counted */ 3586 g_assert(ds->nr_lmbs); 3587 } 3588 3589 if (--ds->nr_lmbs) { 3590 return; 3591 } 3592 3593 /* 3594 * Now that all the LMBs have been removed by the guest, call the 3595 * unplug handler chain. This can never fail. 3596 */ 3597 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3598 } 3599 3600 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3601 { 3602 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3603 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3604 3605 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3606 object_unparent(OBJECT(dev)); 3607 spapr_pending_dimm_unplugs_remove(spapr, ds); 3608 } 3609 3610 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3611 DeviceState *dev, Error **errp) 3612 { 3613 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3614 Error *local_err = NULL; 3615 PCDIMMDevice *dimm = PC_DIMM(dev); 3616 uint32_t nr_lmbs; 3617 uint64_t size, addr_start, addr; 3618 int i; 3619 sPAPRDRConnector *drc; 3620 3621 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3622 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3623 3624 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3625 &local_err); 3626 if (local_err) { 3627 goto out; 3628 } 3629 3630 /* 3631 * An existing pending dimm state for this DIMM means that there is an 3632 * unplug operation in progress, waiting for the spapr_lmb_release 3633 * callback to complete the job (BQL can't cover that far). In this case, 3634 * bail out to avoid detaching DRCs that were already released. 3635 */ 3636 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3637 error_setg(&local_err, 3638 "Memory unplug already in progress for device %s", 3639 dev->id); 3640 goto out; 3641 } 3642 3643 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3644 3645 addr = addr_start; 3646 for (i = 0; i < nr_lmbs; i++) { 3647 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3648 addr / SPAPR_MEMORY_BLOCK_SIZE); 3649 g_assert(drc); 3650 3651 spapr_drc_detach(drc); 3652 addr += SPAPR_MEMORY_BLOCK_SIZE; 3653 } 3654 3655 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3656 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3657 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3658 nr_lmbs, spapr_drc_index(drc)); 3659 out: 3660 error_propagate(errp, local_err); 3661 } 3662 3663 /* Callback to be called during DRC release. */ 3664 void spapr_core_release(DeviceState *dev) 3665 { 3666 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3667 3668 /* Call the unplug handler chain. This can never fail. */ 3669 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3670 } 3671 3672 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3673 { 3674 MachineState *ms = MACHINE(hotplug_dev); 3675 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3676 CPUCore *cc = CPU_CORE(dev); 3677 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3678 3679 if (smc->pre_2_10_has_unused_icps) { 3680 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3681 int i; 3682 3683 for (i = 0; i < cc->nr_threads; i++) { 3684 CPUState *cs = CPU(sc->threads[i]); 3685 3686 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3687 } 3688 } 3689 3690 assert(core_slot); 3691 core_slot->cpu = NULL; 3692 object_unparent(OBJECT(dev)); 3693 } 3694 3695 static 3696 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3697 Error **errp) 3698 { 3699 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3700 int index; 3701 sPAPRDRConnector *drc; 3702 CPUCore *cc = CPU_CORE(dev); 3703 3704 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3705 error_setg(errp, "Unable to find CPU core with core-id: %d", 3706 cc->core_id); 3707 return; 3708 } 3709 if (index == 0) { 3710 error_setg(errp, "Boot CPU core may not be unplugged"); 3711 return; 3712 } 3713 3714 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3715 spapr_vcpu_id(spapr, cc->core_id)); 3716 g_assert(drc); 3717 3718 spapr_drc_detach(drc); 3719 3720 spapr_hotplug_req_remove_by_index(drc); 3721 } 3722 3723 int spapr_core_dt_populate(sPAPRDRConnector *drc, sPAPRMachineState *spapr, 3724 void *fdt, int *fdt_start_offset, Error **errp) 3725 { 3726 sPAPRCPUCore *core = SPAPR_CPU_CORE(drc->dev); 3727 CPUState *cs = CPU(core->threads[0]); 3728 PowerPCCPU *cpu = POWERPC_CPU(cs); 3729 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3730 int id = spapr_get_vcpu_id(cpu); 3731 char *nodename; 3732 int offset; 3733 3734 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3735 offset = fdt_add_subnode(fdt, 0, nodename); 3736 g_free(nodename); 3737 3738 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3739 3740 *fdt_start_offset = offset; 3741 return 0; 3742 } 3743 3744 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3745 Error **errp) 3746 { 3747 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3748 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3749 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3750 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3751 CPUCore *cc = CPU_CORE(dev); 3752 CPUState *cs; 3753 sPAPRDRConnector *drc; 3754 Error *local_err = NULL; 3755 CPUArchId *core_slot; 3756 int index; 3757 bool hotplugged = spapr_drc_hotplugged(dev); 3758 3759 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3760 if (!core_slot) { 3761 error_setg(errp, "Unable to find CPU core with core-id: %d", 3762 cc->core_id); 3763 return; 3764 } 3765 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3766 spapr_vcpu_id(spapr, cc->core_id)); 3767 3768 g_assert(drc || !mc->has_hotpluggable_cpus); 3769 3770 if (drc) { 3771 spapr_drc_attach(drc, dev, &local_err); 3772 if (local_err) { 3773 error_propagate(errp, local_err); 3774 return; 3775 } 3776 3777 if (hotplugged) { 3778 /* 3779 * Send hotplug notification interrupt to the guest only 3780 * in case of hotplugged CPUs. 3781 */ 3782 spapr_hotplug_req_add_by_index(drc); 3783 } else { 3784 spapr_drc_reset(drc); 3785 } 3786 } 3787 3788 core_slot->cpu = OBJECT(dev); 3789 3790 if (smc->pre_2_10_has_unused_icps) { 3791 int i; 3792 3793 for (i = 0; i < cc->nr_threads; i++) { 3794 cs = CPU(core->threads[i]); 3795 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3796 } 3797 } 3798 } 3799 3800 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3801 Error **errp) 3802 { 3803 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3804 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3805 Error *local_err = NULL; 3806 CPUCore *cc = CPU_CORE(dev); 3807 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3808 const char *type = object_get_typename(OBJECT(dev)); 3809 CPUArchId *core_slot; 3810 int index; 3811 3812 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3813 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3814 goto out; 3815 } 3816 3817 if (strcmp(base_core_type, type)) { 3818 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3819 goto out; 3820 } 3821 3822 if (cc->core_id % smp_threads) { 3823 error_setg(&local_err, "invalid core id %d", cc->core_id); 3824 goto out; 3825 } 3826 3827 /* 3828 * In general we should have homogeneous threads-per-core, but old 3829 * (pre hotplug support) machine types allow the last core to have 3830 * reduced threads as a compatibility hack for when we allowed 3831 * total vcpus not a multiple of threads-per-core. 3832 */ 3833 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3834 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3835 cc->nr_threads, smp_threads); 3836 goto out; 3837 } 3838 3839 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3840 if (!core_slot) { 3841 error_setg(&local_err, "core id %d out of range", cc->core_id); 3842 goto out; 3843 } 3844 3845 if (core_slot->cpu) { 3846 error_setg(&local_err, "core %d already populated", cc->core_id); 3847 goto out; 3848 } 3849 3850 numa_cpu_pre_plug(core_slot, dev, &local_err); 3851 3852 out: 3853 error_propagate(errp, local_err); 3854 } 3855 3856 int spapr_phb_dt_populate(sPAPRDRConnector *drc, sPAPRMachineState *spapr, 3857 void *fdt, int *fdt_start_offset, Error **errp) 3858 { 3859 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 3860 int intc_phandle; 3861 3862 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 3863 if (intc_phandle <= 0) { 3864 return -1; 3865 } 3866 3867 if (spapr_populate_pci_dt(sphb, intc_phandle, fdt, spapr->irq->nr_msis, 3868 fdt_start_offset)) { 3869 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 3870 return -1; 3871 } 3872 3873 /* generally SLOF creates these, for hotplug it's up to QEMU */ 3874 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 3875 3876 return 0; 3877 } 3878 3879 static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3880 Error **errp) 3881 { 3882 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3883 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3884 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3885 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 3886 3887 if (dev->hotplugged && !smc->dr_phb_enabled) { 3888 error_setg(errp, "PHB hotplug not supported for this machine"); 3889 return; 3890 } 3891 3892 if (sphb->index == (uint32_t)-1) { 3893 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 3894 return; 3895 } 3896 3897 /* 3898 * This will check that sphb->index doesn't exceed the maximum number of 3899 * PHBs for the current machine type. 3900 */ 3901 smc->phb_placement(spapr, sphb->index, 3902 &sphb->buid, &sphb->io_win_addr, 3903 &sphb->mem_win_addr, &sphb->mem64_win_addr, 3904 windows_supported, sphb->dma_liobn, errp); 3905 } 3906 3907 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3908 Error **errp) 3909 { 3910 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3911 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3912 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3913 sPAPRDRConnector *drc; 3914 bool hotplugged = spapr_drc_hotplugged(dev); 3915 Error *local_err = NULL; 3916 3917 if (!smc->dr_phb_enabled) { 3918 return; 3919 } 3920 3921 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3922 /* hotplug hooks should check it's enabled before getting this far */ 3923 assert(drc); 3924 3925 spapr_drc_attach(drc, DEVICE(dev), &local_err); 3926 if (local_err) { 3927 error_propagate(errp, local_err); 3928 return; 3929 } 3930 3931 if (hotplugged) { 3932 spapr_hotplug_req_add_by_index(drc); 3933 } else { 3934 spapr_drc_reset(drc); 3935 } 3936 } 3937 3938 void spapr_phb_release(DeviceState *dev) 3939 { 3940 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3941 3942 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3943 } 3944 3945 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3946 { 3947 object_unparent(OBJECT(dev)); 3948 } 3949 3950 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 3951 DeviceState *dev, Error **errp) 3952 { 3953 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 3954 sPAPRDRConnector *drc; 3955 3956 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 3957 assert(drc); 3958 3959 if (!spapr_drc_unplug_requested(drc)) { 3960 spapr_drc_detach(drc); 3961 spapr_hotplug_req_remove_by_index(drc); 3962 } 3963 } 3964 3965 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 3966 DeviceState *dev, Error **errp) 3967 { 3968 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3969 spapr_memory_plug(hotplug_dev, dev, errp); 3970 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3971 spapr_core_plug(hotplug_dev, dev, errp); 3972 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 3973 spapr_phb_plug(hotplug_dev, dev, errp); 3974 } 3975 } 3976 3977 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 3978 DeviceState *dev, Error **errp) 3979 { 3980 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3981 spapr_memory_unplug(hotplug_dev, dev); 3982 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3983 spapr_core_unplug(hotplug_dev, dev); 3984 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 3985 spapr_phb_unplug(hotplug_dev, dev); 3986 } 3987 } 3988 3989 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 3990 DeviceState *dev, Error **errp) 3991 { 3992 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3993 MachineClass *mc = MACHINE_GET_CLASS(sms); 3994 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3995 3996 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3997 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3998 spapr_memory_unplug_request(hotplug_dev, dev, errp); 3999 } else { 4000 /* NOTE: this means there is a window after guest reset, prior to 4001 * CAS negotiation, where unplug requests will fail due to the 4002 * capability not being detected yet. This is a bit different than 4003 * the case with PCI unplug, where the events will be queued and 4004 * eventually handled by the guest after boot 4005 */ 4006 error_setg(errp, "Memory hot unplug not supported for this guest"); 4007 } 4008 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4009 if (!mc->has_hotpluggable_cpus) { 4010 error_setg(errp, "CPU hot unplug not supported on this machine"); 4011 return; 4012 } 4013 spapr_core_unplug_request(hotplug_dev, dev, errp); 4014 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4015 if (!smc->dr_phb_enabled) { 4016 error_setg(errp, "PHB hot unplug not supported on this machine"); 4017 return; 4018 } 4019 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4020 } 4021 } 4022 4023 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4024 DeviceState *dev, Error **errp) 4025 { 4026 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4027 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4028 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4029 spapr_core_pre_plug(hotplug_dev, dev, errp); 4030 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4031 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4032 } 4033 } 4034 4035 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4036 DeviceState *dev) 4037 { 4038 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4039 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4040 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4041 return HOTPLUG_HANDLER(machine); 4042 } 4043 return NULL; 4044 } 4045 4046 static CpuInstanceProperties 4047 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4048 { 4049 CPUArchId *core_slot; 4050 MachineClass *mc = MACHINE_GET_CLASS(machine); 4051 4052 /* make sure possible_cpu are intialized */ 4053 mc->possible_cpu_arch_ids(machine); 4054 /* get CPU core slot containing thread that matches cpu_index */ 4055 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4056 assert(core_slot); 4057 return core_slot->props; 4058 } 4059 4060 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4061 { 4062 return idx / smp_cores % nb_numa_nodes; 4063 } 4064 4065 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4066 { 4067 int i; 4068 const char *core_type; 4069 int spapr_max_cores = max_cpus / smp_threads; 4070 MachineClass *mc = MACHINE_GET_CLASS(machine); 4071 4072 if (!mc->has_hotpluggable_cpus) { 4073 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4074 } 4075 if (machine->possible_cpus) { 4076 assert(machine->possible_cpus->len == spapr_max_cores); 4077 return machine->possible_cpus; 4078 } 4079 4080 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4081 if (!core_type) { 4082 error_report("Unable to find sPAPR CPU Core definition"); 4083 exit(1); 4084 } 4085 4086 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4087 sizeof(CPUArchId) * spapr_max_cores); 4088 machine->possible_cpus->len = spapr_max_cores; 4089 for (i = 0; i < machine->possible_cpus->len; i++) { 4090 int core_id = i * smp_threads; 4091 4092 machine->possible_cpus->cpus[i].type = core_type; 4093 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4094 machine->possible_cpus->cpus[i].arch_id = core_id; 4095 machine->possible_cpus->cpus[i].props.has_core_id = true; 4096 machine->possible_cpus->cpus[i].props.core_id = core_id; 4097 } 4098 return machine->possible_cpus; 4099 } 4100 4101 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 4102 uint64_t *buid, hwaddr *pio, 4103 hwaddr *mmio32, hwaddr *mmio64, 4104 unsigned n_dma, uint32_t *liobns, Error **errp) 4105 { 4106 /* 4107 * New-style PHB window placement. 4108 * 4109 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4110 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4111 * windows. 4112 * 4113 * Some guest kernels can't work with MMIO windows above 1<<46 4114 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4115 * 4116 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4117 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4118 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4119 * 1TiB 64-bit MMIO windows for each PHB. 4120 */ 4121 const uint64_t base_buid = 0x800000020000000ULL; 4122 int i; 4123 4124 /* Sanity check natural alignments */ 4125 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4126 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4127 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4128 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4129 /* Sanity check bounds */ 4130 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4131 SPAPR_PCI_MEM32_WIN_SIZE); 4132 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4133 SPAPR_PCI_MEM64_WIN_SIZE); 4134 4135 if (index >= SPAPR_MAX_PHBS) { 4136 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4137 SPAPR_MAX_PHBS - 1); 4138 return; 4139 } 4140 4141 *buid = base_buid + index; 4142 for (i = 0; i < n_dma; ++i) { 4143 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4144 } 4145 4146 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4147 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4148 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4149 } 4150 4151 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4152 { 4153 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 4154 4155 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4156 } 4157 4158 static void spapr_ics_resend(XICSFabric *dev) 4159 { 4160 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 4161 4162 ics_resend(spapr->ics); 4163 } 4164 4165 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4166 { 4167 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4168 4169 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4170 } 4171 4172 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4173 Monitor *mon) 4174 { 4175 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 4176 4177 spapr->irq->print_info(spapr, mon); 4178 } 4179 4180 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4181 { 4182 return cpu->vcpu_id; 4183 } 4184 4185 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4186 { 4187 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4188 int vcpu_id; 4189 4190 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4191 4192 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4193 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4194 error_append_hint(errp, "Adjust the number of cpus to %d " 4195 "or try to raise the number of threads per core\n", 4196 vcpu_id * smp_threads / spapr->vsmt); 4197 return; 4198 } 4199 4200 cpu->vcpu_id = vcpu_id; 4201 } 4202 4203 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4204 { 4205 CPUState *cs; 4206 4207 CPU_FOREACH(cs) { 4208 PowerPCCPU *cpu = POWERPC_CPU(cs); 4209 4210 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4211 return cpu; 4212 } 4213 } 4214 4215 return NULL; 4216 } 4217 4218 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4219 { 4220 MachineClass *mc = MACHINE_CLASS(oc); 4221 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4222 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4223 NMIClass *nc = NMI_CLASS(oc); 4224 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4225 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4226 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4227 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4228 4229 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4230 mc->ignore_boot_device_suffixes = true; 4231 4232 /* 4233 * We set up the default / latest behaviour here. The class_init 4234 * functions for the specific versioned machine types can override 4235 * these details for backwards compatibility 4236 */ 4237 mc->init = spapr_machine_init; 4238 mc->reset = spapr_machine_reset; 4239 mc->block_default_type = IF_SCSI; 4240 mc->max_cpus = 1024; 4241 mc->no_parallel = 1; 4242 mc->default_boot_order = ""; 4243 mc->default_ram_size = 512 * MiB; 4244 mc->default_display = "std"; 4245 mc->kvm_type = spapr_kvm_type; 4246 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4247 mc->pci_allow_0_address = true; 4248 assert(!mc->get_hotplug_handler); 4249 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4250 hc->pre_plug = spapr_machine_device_pre_plug; 4251 hc->plug = spapr_machine_device_plug; 4252 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4253 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4254 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4255 hc->unplug_request = spapr_machine_device_unplug_request; 4256 hc->unplug = spapr_machine_device_unplug; 4257 4258 smc->dr_lmb_enabled = true; 4259 smc->update_dt_enabled = true; 4260 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4261 mc->has_hotpluggable_cpus = true; 4262 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4263 fwc->get_dev_path = spapr_get_fw_dev_path; 4264 nc->nmi_monitor_handler = spapr_nmi; 4265 smc->phb_placement = spapr_phb_placement; 4266 vhc->hypercall = emulate_spapr_hypercall; 4267 vhc->hpt_mask = spapr_hpt_mask; 4268 vhc->map_hptes = spapr_map_hptes; 4269 vhc->unmap_hptes = spapr_unmap_hptes; 4270 vhc->store_hpte = spapr_store_hpte; 4271 vhc->get_pate = spapr_get_pate; 4272 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4273 xic->ics_get = spapr_ics_get; 4274 xic->ics_resend = spapr_ics_resend; 4275 xic->icp_get = spapr_icp_get; 4276 ispc->print_info = spapr_pic_print_info; 4277 /* Force NUMA node memory size to be a multiple of 4278 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4279 * in which LMBs are represented and hot-added 4280 */ 4281 mc->numa_mem_align_shift = 28; 4282 4283 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4284 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4285 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4286 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4287 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4288 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4289 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4290 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4291 spapr_caps_add_properties(smc, &error_abort); 4292 smc->irq = &spapr_irq_xics; 4293 smc->dr_phb_enabled = true; 4294 } 4295 4296 static const TypeInfo spapr_machine_info = { 4297 .name = TYPE_SPAPR_MACHINE, 4298 .parent = TYPE_MACHINE, 4299 .abstract = true, 4300 .instance_size = sizeof(sPAPRMachineState), 4301 .instance_init = spapr_instance_init, 4302 .instance_finalize = spapr_machine_finalizefn, 4303 .class_size = sizeof(sPAPRMachineClass), 4304 .class_init = spapr_machine_class_init, 4305 .interfaces = (InterfaceInfo[]) { 4306 { TYPE_FW_PATH_PROVIDER }, 4307 { TYPE_NMI }, 4308 { TYPE_HOTPLUG_HANDLER }, 4309 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4310 { TYPE_XICS_FABRIC }, 4311 { TYPE_INTERRUPT_STATS_PROVIDER }, 4312 { } 4313 }, 4314 }; 4315 4316 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4317 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4318 void *data) \ 4319 { \ 4320 MachineClass *mc = MACHINE_CLASS(oc); \ 4321 spapr_machine_##suffix##_class_options(mc); \ 4322 if (latest) { \ 4323 mc->alias = "pseries"; \ 4324 mc->is_default = 1; \ 4325 } \ 4326 } \ 4327 static const TypeInfo spapr_machine_##suffix##_info = { \ 4328 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4329 .parent = TYPE_SPAPR_MACHINE, \ 4330 .class_init = spapr_machine_##suffix##_class_init, \ 4331 }; \ 4332 static void spapr_machine_register_##suffix(void) \ 4333 { \ 4334 type_register(&spapr_machine_##suffix##_info); \ 4335 } \ 4336 type_init(spapr_machine_register_##suffix) 4337 4338 /* 4339 * pseries-4.0 4340 */ 4341 static void spapr_machine_4_0_class_options(MachineClass *mc) 4342 { 4343 /* Defaults for the latest behaviour inherited from the base class */ 4344 } 4345 4346 DEFINE_SPAPR_MACHINE(4_0, "4.0", true); 4347 4348 /* 4349 * pseries-3.1 4350 */ 4351 static void spapr_machine_3_1_class_options(MachineClass *mc) 4352 { 4353 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4354 static GlobalProperty compat[] = { 4355 { TYPE_SPAPR_MACHINE, "host-model", "passthrough" }, 4356 { TYPE_SPAPR_MACHINE, "host-serial", "passthrough" }, 4357 }; 4358 4359 spapr_machine_4_0_class_options(mc); 4360 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4361 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4362 4363 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4364 smc->update_dt_enabled = false; 4365 smc->dr_phb_enabled = false; 4366 } 4367 4368 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4369 4370 /* 4371 * pseries-3.0 4372 */ 4373 4374 static void spapr_machine_3_0_class_options(MachineClass *mc) 4375 { 4376 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4377 4378 spapr_machine_3_1_class_options(mc); 4379 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4380 4381 smc->legacy_irq_allocation = true; 4382 smc->irq = &spapr_irq_xics_legacy; 4383 } 4384 4385 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4386 4387 /* 4388 * pseries-2.12 4389 */ 4390 static void spapr_machine_2_12_class_options(MachineClass *mc) 4391 { 4392 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4393 static GlobalProperty compat[] = { 4394 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4395 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4396 }; 4397 4398 spapr_machine_3_0_class_options(mc); 4399 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4400 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4401 4402 /* We depend on kvm_enabled() to choose a default value for the 4403 * hpt-max-page-size capability. Of course we can't do it here 4404 * because this is too early and the HW accelerator isn't initialzed 4405 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4406 */ 4407 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4408 } 4409 4410 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4411 4412 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4413 { 4414 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4415 4416 spapr_machine_2_12_class_options(mc); 4417 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4418 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4419 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4420 } 4421 4422 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4423 4424 /* 4425 * pseries-2.11 4426 */ 4427 4428 static void spapr_machine_2_11_class_options(MachineClass *mc) 4429 { 4430 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4431 4432 spapr_machine_2_12_class_options(mc); 4433 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4434 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4435 } 4436 4437 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4438 4439 /* 4440 * pseries-2.10 4441 */ 4442 4443 static void spapr_machine_2_10_class_options(MachineClass *mc) 4444 { 4445 spapr_machine_2_11_class_options(mc); 4446 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4447 } 4448 4449 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4450 4451 /* 4452 * pseries-2.9 4453 */ 4454 4455 static void spapr_machine_2_9_class_options(MachineClass *mc) 4456 { 4457 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4458 static GlobalProperty compat[] = { 4459 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 4460 }; 4461 4462 spapr_machine_2_10_class_options(mc); 4463 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 4464 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4465 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4466 smc->pre_2_10_has_unused_icps = true; 4467 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4468 } 4469 4470 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4471 4472 /* 4473 * pseries-2.8 4474 */ 4475 4476 static void spapr_machine_2_8_class_options(MachineClass *mc) 4477 { 4478 static GlobalProperty compat[] = { 4479 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 4480 }; 4481 4482 spapr_machine_2_9_class_options(mc); 4483 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 4484 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4485 mc->numa_mem_align_shift = 23; 4486 } 4487 4488 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4489 4490 /* 4491 * pseries-2.7 4492 */ 4493 4494 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 4495 uint64_t *buid, hwaddr *pio, 4496 hwaddr *mmio32, hwaddr *mmio64, 4497 unsigned n_dma, uint32_t *liobns, Error **errp) 4498 { 4499 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4500 const uint64_t base_buid = 0x800000020000000ULL; 4501 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4502 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4503 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4504 const uint32_t max_index = 255; 4505 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4506 4507 uint64_t ram_top = MACHINE(spapr)->ram_size; 4508 hwaddr phb0_base, phb_base; 4509 int i; 4510 4511 /* Do we have device memory? */ 4512 if (MACHINE(spapr)->maxram_size > ram_top) { 4513 /* Can't just use maxram_size, because there may be an 4514 * alignment gap between normal and device memory regions 4515 */ 4516 ram_top = MACHINE(spapr)->device_memory->base + 4517 memory_region_size(&MACHINE(spapr)->device_memory->mr); 4518 } 4519 4520 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4521 4522 if (index > max_index) { 4523 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4524 max_index); 4525 return; 4526 } 4527 4528 *buid = base_buid + index; 4529 for (i = 0; i < n_dma; ++i) { 4530 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4531 } 4532 4533 phb_base = phb0_base + index * phb_spacing; 4534 *pio = phb_base + pio_offset; 4535 *mmio32 = phb_base + mmio_offset; 4536 /* 4537 * We don't set the 64-bit MMIO window, relying on the PHB's 4538 * fallback behaviour of automatically splitting a large "32-bit" 4539 * window into contiguous 32-bit and 64-bit windows 4540 */ 4541 } 4542 4543 static void spapr_machine_2_7_class_options(MachineClass *mc) 4544 { 4545 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4546 static GlobalProperty compat[] = { 4547 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 4548 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 4549 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 4550 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 4551 }; 4552 4553 spapr_machine_2_8_class_options(mc); 4554 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4555 mc->default_machine_opts = "modern-hotplug-events=off"; 4556 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 4557 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4558 smc->phb_placement = phb_placement_2_7; 4559 } 4560 4561 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4562 4563 /* 4564 * pseries-2.6 4565 */ 4566 4567 static void spapr_machine_2_6_class_options(MachineClass *mc) 4568 { 4569 static GlobalProperty compat[] = { 4570 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 4571 }; 4572 4573 spapr_machine_2_7_class_options(mc); 4574 mc->has_hotpluggable_cpus = false; 4575 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 4576 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4577 } 4578 4579 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4580 4581 /* 4582 * pseries-2.5 4583 */ 4584 4585 static void spapr_machine_2_5_class_options(MachineClass *mc) 4586 { 4587 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4588 static GlobalProperty compat[] = { 4589 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 4590 }; 4591 4592 spapr_machine_2_6_class_options(mc); 4593 smc->use_ohci_by_default = true; 4594 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 4595 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4596 } 4597 4598 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4599 4600 /* 4601 * pseries-2.4 4602 */ 4603 4604 static void spapr_machine_2_4_class_options(MachineClass *mc) 4605 { 4606 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4607 4608 spapr_machine_2_5_class_options(mc); 4609 smc->dr_lmb_enabled = false; 4610 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 4611 } 4612 4613 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4614 4615 /* 4616 * pseries-2.3 4617 */ 4618 4619 static void spapr_machine_2_3_class_options(MachineClass *mc) 4620 { 4621 static GlobalProperty compat[] = { 4622 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 4623 }; 4624 spapr_machine_2_4_class_options(mc); 4625 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 4626 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4627 } 4628 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4629 4630 /* 4631 * pseries-2.2 4632 */ 4633 4634 static void spapr_machine_2_2_class_options(MachineClass *mc) 4635 { 4636 static GlobalProperty compat[] = { 4637 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 4638 }; 4639 4640 spapr_machine_2_3_class_options(mc); 4641 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 4642 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4643 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 4644 } 4645 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4646 4647 /* 4648 * pseries-2.1 4649 */ 4650 4651 static void spapr_machine_2_1_class_options(MachineClass *mc) 4652 { 4653 spapr_machine_2_2_class_options(mc); 4654 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 4655 } 4656 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4657 4658 static void spapr_machine_register_types(void) 4659 { 4660 type_register_static(&spapr_machine_info); 4661 } 4662 4663 type_init(spapr_machine_register_types) 4664