1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "sysemu/sysemu.h" 28 #include "hw/hw.h" 29 #include "hw/fw-path-provider.h" 30 #include "elf.h" 31 #include "net/net.h" 32 #include "sysemu/block-backend.h" 33 #include "sysemu/cpus.h" 34 #include "sysemu/kvm.h" 35 #include "kvm_ppc.h" 36 #include "mmu-hash64.h" 37 #include "qom/cpu.h" 38 39 #include "hw/boards.h" 40 #include "hw/ppc/ppc.h" 41 #include "hw/loader.h" 42 43 #include "hw/ppc/spapr.h" 44 #include "hw/ppc/spapr_vio.h" 45 #include "hw/pci-host/spapr.h" 46 #include "hw/ppc/xics.h" 47 #include "hw/pci/msi.h" 48 49 #include "hw/pci/pci.h" 50 #include "hw/scsi/scsi.h" 51 #include "hw/virtio/virtio-scsi.h" 52 53 #include "exec/address-spaces.h" 54 #include "hw/usb.h" 55 #include "qemu/config-file.h" 56 #include "qemu/error-report.h" 57 #include "trace.h" 58 #include "hw/nmi.h" 59 60 #include "hw/compat.h" 61 62 #include <libfdt.h> 63 64 /* SLOF memory layout: 65 * 66 * SLOF raw image loaded at 0, copies its romfs right below the flat 67 * device-tree, then position SLOF itself 31M below that 68 * 69 * So we set FW_OVERHEAD to 40MB which should account for all of that 70 * and more 71 * 72 * We load our kernel at 4M, leaving space for SLOF initial image 73 */ 74 #define FDT_MAX_SIZE 0x40000 75 #define RTAS_MAX_SIZE 0x10000 76 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 77 #define FW_MAX_SIZE 0x400000 78 #define FW_FILE_NAME "slof.bin" 79 #define FW_OVERHEAD 0x2800000 80 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 81 82 #define MIN_RMA_SLOF 128UL 83 84 #define TIMEBASE_FREQ 512000000ULL 85 86 #define MAX_CPUS 255 87 88 #define PHANDLE_XICP 0x00001111 89 90 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 91 92 typedef struct sPAPRMachineState sPAPRMachineState; 93 94 #define TYPE_SPAPR_MACHINE "spapr-machine" 95 #define SPAPR_MACHINE(obj) \ 96 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) 97 98 /** 99 * sPAPRMachineState: 100 */ 101 struct sPAPRMachineState { 102 /*< private >*/ 103 MachineState parent_obj; 104 105 /*< public >*/ 106 char *kvm_type; 107 }; 108 109 sPAPREnvironment *spapr; 110 111 static XICSState *try_create_xics(const char *type, int nr_servers, 112 int nr_irqs) 113 { 114 DeviceState *dev; 115 116 dev = qdev_create(NULL, type); 117 qdev_prop_set_uint32(dev, "nr_servers", nr_servers); 118 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); 119 if (qdev_init(dev) < 0) { 120 return NULL; 121 } 122 123 return XICS_COMMON(dev); 124 } 125 126 static XICSState *xics_system_init(int nr_servers, int nr_irqs) 127 { 128 XICSState *icp = NULL; 129 130 if (kvm_enabled()) { 131 QemuOpts *machine_opts = qemu_get_machine_opts(); 132 bool irqchip_allowed = qemu_opt_get_bool(machine_opts, 133 "kernel_irqchip", true); 134 bool irqchip_required = qemu_opt_get_bool(machine_opts, 135 "kernel_irqchip", false); 136 if (irqchip_allowed) { 137 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs); 138 } 139 140 if (irqchip_required && !icp) { 141 perror("Failed to create in-kernel XICS\n"); 142 abort(); 143 } 144 } 145 146 if (!icp) { 147 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs); 148 } 149 150 if (!icp) { 151 perror("Failed to create XICS\n"); 152 abort(); 153 } 154 155 return icp; 156 } 157 158 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 159 int smt_threads) 160 { 161 int i, ret = 0; 162 uint32_t servers_prop[smt_threads]; 163 uint32_t gservers_prop[smt_threads * 2]; 164 int index = ppc_get_vcpu_dt_id(cpu); 165 166 if (cpu->cpu_version) { 167 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version); 168 if (ret < 0) { 169 return ret; 170 } 171 } 172 173 /* Build interrupt servers and gservers properties */ 174 for (i = 0; i < smt_threads; i++) { 175 servers_prop[i] = cpu_to_be32(index + i); 176 /* Hack, direct the group queues back to cpu 0 */ 177 gservers_prop[i*2] = cpu_to_be32(index + i); 178 gservers_prop[i*2 + 1] = 0; 179 } 180 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 181 servers_prop, sizeof(servers_prop)); 182 if (ret < 0) { 183 return ret; 184 } 185 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 186 gservers_prop, sizeof(gservers_prop)); 187 188 return ret; 189 } 190 191 static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr) 192 { 193 int ret = 0, offset, cpus_offset; 194 CPUState *cs; 195 char cpu_model[32]; 196 int smt = kvmppc_smt_threads(); 197 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 198 199 CPU_FOREACH(cs) { 200 PowerPCCPU *cpu = POWERPC_CPU(cs); 201 DeviceClass *dc = DEVICE_GET_CLASS(cs); 202 int index = ppc_get_vcpu_dt_id(cpu); 203 uint32_t associativity[] = {cpu_to_be32(0x5), 204 cpu_to_be32(0x0), 205 cpu_to_be32(0x0), 206 cpu_to_be32(0x0), 207 cpu_to_be32(cs->numa_node), 208 cpu_to_be32(index)}; 209 210 if ((index % smt) != 0) { 211 continue; 212 } 213 214 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 215 216 cpus_offset = fdt_path_offset(fdt, "/cpus"); 217 if (cpus_offset < 0) { 218 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 219 "cpus"); 220 if (cpus_offset < 0) { 221 return cpus_offset; 222 } 223 } 224 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 225 if (offset < 0) { 226 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 227 if (offset < 0) { 228 return offset; 229 } 230 } 231 232 if (nb_numa_nodes > 1) { 233 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 234 sizeof(associativity)); 235 if (ret < 0) { 236 return ret; 237 } 238 } 239 240 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 241 pft_size_prop, sizeof(pft_size_prop)); 242 if (ret < 0) { 243 return ret; 244 } 245 246 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 247 ppc_get_compat_smt_threads(cpu)); 248 if (ret < 0) { 249 return ret; 250 } 251 } 252 return ret; 253 } 254 255 256 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, 257 size_t maxsize) 258 { 259 size_t maxcells = maxsize / sizeof(uint32_t); 260 int i, j, count; 261 uint32_t *p = prop; 262 263 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 264 struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; 265 266 if (!sps->page_shift) { 267 break; 268 } 269 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { 270 if (sps->enc[count].page_shift == 0) { 271 break; 272 } 273 } 274 if ((p - prop) >= (maxcells - 3 - count * 2)) { 275 break; 276 } 277 *(p++) = cpu_to_be32(sps->page_shift); 278 *(p++) = cpu_to_be32(sps->slb_enc); 279 *(p++) = cpu_to_be32(count); 280 for (j = 0; j < count; j++) { 281 *(p++) = cpu_to_be32(sps->enc[j].page_shift); 282 *(p++) = cpu_to_be32(sps->enc[j].pte_enc); 283 } 284 } 285 286 return (p - prop) * sizeof(uint32_t); 287 } 288 289 static hwaddr spapr_node0_size(void) 290 { 291 if (nb_numa_nodes) { 292 int i; 293 for (i = 0; i < nb_numa_nodes; ++i) { 294 if (numa_info[i].node_mem) { 295 return MIN(pow2floor(numa_info[i].node_mem), ram_size); 296 } 297 } 298 } 299 return ram_size; 300 } 301 302 #define _FDT(exp) \ 303 do { \ 304 int ret = (exp); \ 305 if (ret < 0) { \ 306 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ 307 #exp, fdt_strerror(ret)); \ 308 exit(1); \ 309 } \ 310 } while (0) 311 312 static void add_str(GString *s, const gchar *s1) 313 { 314 g_string_append_len(s, s1, strlen(s1) + 1); 315 } 316 317 static void *spapr_create_fdt_skel(hwaddr initrd_base, 318 hwaddr initrd_size, 319 hwaddr kernel_size, 320 bool little_endian, 321 const char *boot_device, 322 const char *kernel_cmdline, 323 uint32_t epow_irq) 324 { 325 void *fdt; 326 CPUState *cs; 327 uint32_t start_prop = cpu_to_be32(initrd_base); 328 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); 329 GString *hypertas = g_string_sized_new(256); 330 GString *qemu_hypertas = g_string_sized_new(256); 331 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; 332 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)}; 333 int smt = kvmppc_smt_threads(); 334 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; 335 QemuOpts *opts = qemu_opts_find(qemu_find_opts("smp-opts"), NULL); 336 unsigned sockets = opts ? qemu_opt_get_number(opts, "sockets", 0) : 0; 337 uint32_t cpus_per_socket = sockets ? (smp_cpus / sockets) : 1; 338 char *buf; 339 340 add_str(hypertas, "hcall-pft"); 341 add_str(hypertas, "hcall-term"); 342 add_str(hypertas, "hcall-dabr"); 343 add_str(hypertas, "hcall-interrupt"); 344 add_str(hypertas, "hcall-tce"); 345 add_str(hypertas, "hcall-vio"); 346 add_str(hypertas, "hcall-splpar"); 347 add_str(hypertas, "hcall-bulk"); 348 add_str(hypertas, "hcall-set-mode"); 349 add_str(qemu_hypertas, "hcall-memop1"); 350 351 fdt = g_malloc0(FDT_MAX_SIZE); 352 _FDT((fdt_create(fdt, FDT_MAX_SIZE))); 353 354 if (kernel_size) { 355 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); 356 } 357 if (initrd_size) { 358 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); 359 } 360 _FDT((fdt_finish_reservemap(fdt))); 361 362 /* Root node */ 363 _FDT((fdt_begin_node(fdt, ""))); 364 _FDT((fdt_property_string(fdt, "device_type", "chrp"))); 365 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); 366 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); 367 368 /* 369 * Add info to guest to indentify which host is it being run on 370 * and what is the uuid of the guest 371 */ 372 if (kvmppc_get_host_model(&buf)) { 373 _FDT((fdt_property_string(fdt, "host-model", buf))); 374 g_free(buf); 375 } 376 if (kvmppc_get_host_serial(&buf)) { 377 _FDT((fdt_property_string(fdt, "host-serial", buf))); 378 g_free(buf); 379 } 380 381 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1], 382 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4], 383 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7], 384 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10], 385 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13], 386 qemu_uuid[14], qemu_uuid[15]); 387 388 _FDT((fdt_property_string(fdt, "vm,uuid", buf))); 389 g_free(buf); 390 391 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); 392 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); 393 394 /* /chosen */ 395 _FDT((fdt_begin_node(fdt, "chosen"))); 396 397 /* Set Form1_affinity */ 398 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); 399 400 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); 401 _FDT((fdt_property(fdt, "linux,initrd-start", 402 &start_prop, sizeof(start_prop)))); 403 _FDT((fdt_property(fdt, "linux,initrd-end", 404 &end_prop, sizeof(end_prop)))); 405 if (kernel_size) { 406 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 407 cpu_to_be64(kernel_size) }; 408 409 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); 410 if (little_endian) { 411 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); 412 } 413 } 414 if (boot_device) { 415 _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device))); 416 } 417 if (boot_menu) { 418 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu))); 419 } 420 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); 421 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); 422 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); 423 424 _FDT((fdt_end_node(fdt))); 425 426 /* cpus */ 427 _FDT((fdt_begin_node(fdt, "cpus"))); 428 429 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 430 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 431 432 CPU_FOREACH(cs) { 433 PowerPCCPU *cpu = POWERPC_CPU(cs); 434 CPUPPCState *env = &cpu->env; 435 DeviceClass *dc = DEVICE_GET_CLASS(cs); 436 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 437 int index = ppc_get_vcpu_dt_id(cpu); 438 char *nodename; 439 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 440 0xffffffff, 0xffffffff}; 441 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; 442 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 443 uint32_t page_sizes_prop[64]; 444 size_t page_sizes_prop_size; 445 446 if ((index % smt) != 0) { 447 continue; 448 } 449 450 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 451 452 _FDT((fdt_begin_node(fdt, nodename))); 453 454 g_free(nodename); 455 456 _FDT((fdt_property_cell(fdt, "reg", index))); 457 _FDT((fdt_property_string(fdt, "device_type", "cpu"))); 458 459 _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR]))); 460 _FDT((fdt_property_cell(fdt, "d-cache-block-size", 461 env->dcache_line_size))); 462 _FDT((fdt_property_cell(fdt, "d-cache-line-size", 463 env->dcache_line_size))); 464 _FDT((fdt_property_cell(fdt, "i-cache-block-size", 465 env->icache_line_size))); 466 _FDT((fdt_property_cell(fdt, "i-cache-line-size", 467 env->icache_line_size))); 468 469 if (pcc->l1_dcache_size) { 470 _FDT((fdt_property_cell(fdt, "d-cache-size", pcc->l1_dcache_size))); 471 } else { 472 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); 473 } 474 if (pcc->l1_icache_size) { 475 _FDT((fdt_property_cell(fdt, "i-cache-size", pcc->l1_icache_size))); 476 } else { 477 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); 478 } 479 480 _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq))); 481 _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq))); 482 _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr))); 483 _FDT((fdt_property_string(fdt, "status", "okay"))); 484 _FDT((fdt_property(fdt, "64-bit", NULL, 0))); 485 486 if (env->spr_cb[SPR_PURR].oea_read) { 487 _FDT((fdt_property(fdt, "ibm,purr", NULL, 0))); 488 } 489 490 if (env->mmu_model & POWERPC_MMU_1TSEG) { 491 _FDT((fdt_property(fdt, "ibm,processor-segment-sizes", 492 segs, sizeof(segs)))); 493 } 494 495 /* Advertise VMX/VSX (vector extensions) if available 496 * 0 / no property == no vector extensions 497 * 1 == VMX / Altivec available 498 * 2 == VSX available */ 499 if (env->insns_flags & PPC_ALTIVEC) { 500 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 501 502 _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx))); 503 } 504 505 /* Advertise DFP (Decimal Floating Point) if available 506 * 0 / no property == no DFP 507 * 1 == DFP available */ 508 if (env->insns_flags2 & PPC2_DFP) { 509 _FDT((fdt_property_cell(fdt, "ibm,dfp", 1))); 510 } 511 512 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, 513 sizeof(page_sizes_prop)); 514 if (page_sizes_prop_size) { 515 _FDT((fdt_property(fdt, "ibm,segment-page-sizes", 516 page_sizes_prop, page_sizes_prop_size))); 517 } 518 519 _FDT((fdt_property_cell(fdt, "ibm,chip-id", 520 cs->cpu_index / cpus_per_socket))); 521 522 _FDT((fdt_end_node(fdt))); 523 } 524 525 _FDT((fdt_end_node(fdt))); 526 527 /* RTAS */ 528 _FDT((fdt_begin_node(fdt, "rtas"))); 529 530 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 531 add_str(hypertas, "hcall-multi-tce"); 532 } 533 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str, 534 hypertas->len))); 535 g_string_free(hypertas, TRUE); 536 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str, 537 qemu_hypertas->len))); 538 g_string_free(qemu_hypertas, TRUE); 539 540 _FDT((fdt_property(fdt, "ibm,associativity-reference-points", 541 refpoints, sizeof(refpoints)))); 542 543 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); 544 545 /* 546 * According to PAPR, rtas ibm,os-term does not guarantee a return 547 * back to the guest cpu. 548 * 549 * While an additional ibm,extended-os-term property indicates that 550 * rtas call return will always occur. Set this property. 551 */ 552 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0))); 553 554 _FDT((fdt_end_node(fdt))); 555 556 /* interrupt controller */ 557 _FDT((fdt_begin_node(fdt, "interrupt-controller"))); 558 559 _FDT((fdt_property_string(fdt, "device_type", 560 "PowerPC-External-Interrupt-Presentation"))); 561 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); 562 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 563 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", 564 interrupt_server_ranges_prop, 565 sizeof(interrupt_server_ranges_prop)))); 566 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); 567 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); 568 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); 569 570 _FDT((fdt_end_node(fdt))); 571 572 /* vdevice */ 573 _FDT((fdt_begin_node(fdt, "vdevice"))); 574 575 _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); 576 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); 577 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 578 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 579 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); 580 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 581 582 _FDT((fdt_end_node(fdt))); 583 584 /* event-sources */ 585 spapr_events_fdt_skel(fdt, epow_irq); 586 587 /* /hypervisor node */ 588 if (kvm_enabled()) { 589 uint8_t hypercall[16]; 590 591 /* indicate KVM hypercall interface */ 592 _FDT((fdt_begin_node(fdt, "hypervisor"))); 593 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm"))); 594 if (kvmppc_has_cap_fixup_hcalls()) { 595 /* 596 * Older KVM versions with older guest kernels were broken with the 597 * magic page, don't allow the guest to map it. 598 */ 599 kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 600 sizeof(hypercall)); 601 _FDT((fdt_property(fdt, "hcall-instructions", hypercall, 602 sizeof(hypercall)))); 603 } 604 _FDT((fdt_end_node(fdt))); 605 } 606 607 _FDT((fdt_end_node(fdt))); /* close root node */ 608 _FDT((fdt_finish(fdt))); 609 610 return fdt; 611 } 612 613 int spapr_h_cas_compose_response(target_ulong addr, target_ulong size) 614 { 615 void *fdt, *fdt_skel; 616 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 617 618 size -= sizeof(hdr); 619 620 /* Create sceleton */ 621 fdt_skel = g_malloc0(size); 622 _FDT((fdt_create(fdt_skel, size))); 623 _FDT((fdt_begin_node(fdt_skel, ""))); 624 _FDT((fdt_end_node(fdt_skel))); 625 _FDT((fdt_finish(fdt_skel))); 626 fdt = g_malloc0(size); 627 _FDT((fdt_open_into(fdt_skel, fdt, size))); 628 g_free(fdt_skel); 629 630 /* Fix skeleton up */ 631 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 632 633 /* Pack resulting tree */ 634 _FDT((fdt_pack(fdt))); 635 636 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 637 trace_spapr_cas_failed(size); 638 return -1; 639 } 640 641 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 642 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 643 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 644 g_free(fdt); 645 646 return 0; 647 } 648 649 static void spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 650 hwaddr size) 651 { 652 uint32_t associativity[] = { 653 cpu_to_be32(0x4), /* length */ 654 cpu_to_be32(0x0), cpu_to_be32(0x0), 655 cpu_to_be32(0x0), cpu_to_be32(nodeid) 656 }; 657 char mem_name[32]; 658 uint64_t mem_reg_property[2]; 659 int off; 660 661 mem_reg_property[0] = cpu_to_be64(start); 662 mem_reg_property[1] = cpu_to_be64(size); 663 664 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 665 off = fdt_add_subnode(fdt, 0, mem_name); 666 _FDT(off); 667 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 668 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 669 sizeof(mem_reg_property)))); 670 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 671 sizeof(associativity)))); 672 } 673 674 static int spapr_populate_memory(sPAPREnvironment *spapr, void *fdt) 675 { 676 hwaddr mem_start, node_size; 677 int i, nb_nodes = nb_numa_nodes; 678 NodeInfo *nodes = numa_info; 679 NodeInfo ramnode; 680 681 /* No NUMA nodes, assume there is just one node with whole RAM */ 682 if (!nb_numa_nodes) { 683 nb_nodes = 1; 684 ramnode.node_mem = ram_size; 685 nodes = &ramnode; 686 } 687 688 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 689 if (!nodes[i].node_mem) { 690 continue; 691 } 692 if (mem_start >= ram_size) { 693 node_size = 0; 694 } else { 695 node_size = nodes[i].node_mem; 696 if (node_size > ram_size - mem_start) { 697 node_size = ram_size - mem_start; 698 } 699 } 700 if (!mem_start) { 701 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 702 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 703 mem_start += spapr->rma_size; 704 node_size -= spapr->rma_size; 705 } 706 for ( ; node_size; ) { 707 hwaddr sizetmp = pow2floor(node_size); 708 709 /* mem_start != 0 here */ 710 if (ctzl(mem_start) < ctzl(sizetmp)) { 711 sizetmp = 1ULL << ctzl(mem_start); 712 } 713 714 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 715 node_size -= sizetmp; 716 mem_start += sizetmp; 717 } 718 } 719 720 return 0; 721 } 722 723 static void spapr_finalize_fdt(sPAPREnvironment *spapr, 724 hwaddr fdt_addr, 725 hwaddr rtas_addr, 726 hwaddr rtas_size) 727 { 728 int ret, i; 729 size_t cb = 0; 730 char *bootlist; 731 void *fdt; 732 sPAPRPHBState *phb; 733 734 fdt = g_malloc(FDT_MAX_SIZE); 735 736 /* open out the base tree into a temp buffer for the final tweaks */ 737 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); 738 739 ret = spapr_populate_memory(spapr, fdt); 740 if (ret < 0) { 741 fprintf(stderr, "couldn't setup memory nodes in fdt\n"); 742 exit(1); 743 } 744 745 ret = spapr_populate_vdevice(spapr->vio_bus, fdt); 746 if (ret < 0) { 747 fprintf(stderr, "couldn't setup vio devices in fdt\n"); 748 exit(1); 749 } 750 751 QLIST_FOREACH(phb, &spapr->phbs, list) { 752 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 753 } 754 755 if (ret < 0) { 756 fprintf(stderr, "couldn't setup PCI devices in fdt\n"); 757 exit(1); 758 } 759 760 /* RTAS */ 761 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); 762 if (ret < 0) { 763 fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); 764 } 765 766 /* Advertise NUMA via ibm,associativity */ 767 ret = spapr_fixup_cpu_dt(fdt, spapr); 768 if (ret < 0) { 769 fprintf(stderr, "Couldn't finalize CPU device tree properties\n"); 770 } 771 772 bootlist = get_boot_devices_list(&cb, true); 773 if (cb && bootlist) { 774 int offset = fdt_path_offset(fdt, "/chosen"); 775 if (offset < 0) { 776 exit(1); 777 } 778 for (i = 0; i < cb; i++) { 779 if (bootlist[i] == '\n') { 780 bootlist[i] = ' '; 781 } 782 783 } 784 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist); 785 } 786 787 if (!spapr->has_graphics) { 788 spapr_populate_chosen_stdout(fdt, spapr->vio_bus); 789 } 790 791 _FDT((fdt_pack(fdt))); 792 793 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 794 hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n", 795 fdt_totalsize(fdt), FDT_MAX_SIZE); 796 exit(1); 797 } 798 799 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 800 801 g_free(bootlist); 802 g_free(fdt); 803 } 804 805 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 806 { 807 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 808 } 809 810 static void emulate_spapr_hypercall(PowerPCCPU *cpu) 811 { 812 CPUPPCState *env = &cpu->env; 813 814 if (msr_pr) { 815 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 816 env->gpr[3] = H_PRIVILEGE; 817 } else { 818 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 819 } 820 } 821 822 static void spapr_reset_htab(sPAPREnvironment *spapr) 823 { 824 long shift; 825 826 /* allocate hash page table. For now we always make this 16mb, 827 * later we should probably make it scale to the size of guest 828 * RAM */ 829 830 shift = kvmppc_reset_htab(spapr->htab_shift); 831 832 if (shift > 0) { 833 /* Kernel handles htab, we don't need to allocate one */ 834 spapr->htab_shift = shift; 835 kvmppc_kern_htab = true; 836 } else { 837 if (!spapr->htab) { 838 /* Allocate an htab if we don't yet have one */ 839 spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); 840 } 841 842 /* And clear it */ 843 memset(spapr->htab, 0, HTAB_SIZE(spapr)); 844 } 845 846 /* Update the RMA size if necessary */ 847 if (spapr->vrma_adjust) { 848 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 849 spapr->htab_shift); 850 } 851 } 852 853 static void ppc_spapr_reset(void) 854 { 855 PowerPCCPU *first_ppc_cpu; 856 uint32_t rtas_limit; 857 858 /* Reset the hash table & recalc the RMA */ 859 spapr_reset_htab(spapr); 860 861 qemu_devices_reset(); 862 863 /* 864 * We place the device tree and RTAS just below either the top of the RMA, 865 * or just below 2GB, whichever is lowere, so that it can be 866 * processed with 32-bit real mode code if necessary 867 */ 868 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 869 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; 870 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; 871 872 /* Load the fdt */ 873 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, 874 spapr->rtas_size); 875 876 /* Copy RTAS over */ 877 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob, 878 spapr->rtas_size); 879 880 /* Set up the entry state */ 881 first_ppc_cpu = POWERPC_CPU(first_cpu); 882 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; 883 first_ppc_cpu->env.gpr[5] = 0; 884 first_cpu->halted = 0; 885 first_ppc_cpu->env.nip = spapr->entry_point; 886 887 } 888 889 static void spapr_cpu_reset(void *opaque) 890 { 891 PowerPCCPU *cpu = opaque; 892 CPUState *cs = CPU(cpu); 893 CPUPPCState *env = &cpu->env; 894 895 cpu_reset(cs); 896 897 /* All CPUs start halted. CPU0 is unhalted from the machine level 898 * reset code and the rest are explicitly started up by the guest 899 * using an RTAS call */ 900 cs->halted = 1; 901 902 env->spr[SPR_HIOR] = 0; 903 904 env->external_htab = (uint8_t *)spapr->htab; 905 if (kvm_enabled() && !env->external_htab) { 906 /* 907 * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte* 908 * functions do the right thing. 909 */ 910 env->external_htab = (void *)1; 911 } 912 env->htab_base = -1; 913 /* 914 * htab_mask is the mask used to normalize hash value to PTEG index. 915 * htab_shift is log2 of hash table size. 916 * We have 8 hpte per group, and each hpte is 16 bytes. 917 * ie have 128 bytes per hpte entry. 918 */ 919 env->htab_mask = (1ULL << ((spapr)->htab_shift - 7)) - 1; 920 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | 921 (spapr->htab_shift - 18); 922 } 923 924 static void spapr_create_nvram(sPAPREnvironment *spapr) 925 { 926 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 927 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 928 929 if (dinfo) { 930 qdev_prop_set_drive_nofail(dev, "drive", blk_by_legacy_dinfo(dinfo)); 931 } 932 933 qdev_init_nofail(dev); 934 935 spapr->nvram = (struct sPAPRNVRAM *)dev; 936 } 937 938 /* Returns whether we want to use VGA or not */ 939 static int spapr_vga_init(PCIBus *pci_bus) 940 { 941 switch (vga_interface_type) { 942 case VGA_NONE: 943 return false; 944 case VGA_DEVICE: 945 return true; 946 case VGA_STD: 947 return pci_vga_init(pci_bus) != NULL; 948 default: 949 fprintf(stderr, "This vga model is not supported," 950 "currently it only supports -vga std\n"); 951 exit(0); 952 } 953 } 954 955 static const VMStateDescription vmstate_spapr = { 956 .name = "spapr", 957 .version_id = 2, 958 .minimum_version_id = 1, 959 .fields = (VMStateField[]) { 960 VMSTATE_UNUSED(4), /* used to be @next_irq */ 961 962 /* RTC offset */ 963 VMSTATE_UINT64(rtc_offset, sPAPREnvironment), 964 VMSTATE_PPC_TIMEBASE_V(tb, sPAPREnvironment, 2), 965 VMSTATE_END_OF_LIST() 966 }, 967 }; 968 969 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 970 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 971 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 972 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 973 974 static int htab_save_setup(QEMUFile *f, void *opaque) 975 { 976 sPAPREnvironment *spapr = opaque; 977 978 /* "Iteration" header */ 979 qemu_put_be32(f, spapr->htab_shift); 980 981 if (spapr->htab) { 982 spapr->htab_save_index = 0; 983 spapr->htab_first_pass = true; 984 } else { 985 assert(kvm_enabled()); 986 987 spapr->htab_fd = kvmppc_get_htab_fd(false); 988 if (spapr->htab_fd < 0) { 989 fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n", 990 strerror(errno)); 991 return -1; 992 } 993 } 994 995 996 return 0; 997 } 998 999 static void htab_save_first_pass(QEMUFile *f, sPAPREnvironment *spapr, 1000 int64_t max_ns) 1001 { 1002 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1003 int index = spapr->htab_save_index; 1004 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1005 1006 assert(spapr->htab_first_pass); 1007 1008 do { 1009 int chunkstart; 1010 1011 /* Consume invalid HPTEs */ 1012 while ((index < htabslots) 1013 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1014 index++; 1015 CLEAN_HPTE(HPTE(spapr->htab, index)); 1016 } 1017 1018 /* Consume valid HPTEs */ 1019 chunkstart = index; 1020 while ((index < htabslots) 1021 && HPTE_VALID(HPTE(spapr->htab, index))) { 1022 index++; 1023 CLEAN_HPTE(HPTE(spapr->htab, index)); 1024 } 1025 1026 if (index > chunkstart) { 1027 int n_valid = index - chunkstart; 1028 1029 qemu_put_be32(f, chunkstart); 1030 qemu_put_be16(f, n_valid); 1031 qemu_put_be16(f, 0); 1032 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1033 HASH_PTE_SIZE_64 * n_valid); 1034 1035 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1036 break; 1037 } 1038 } 1039 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1040 1041 if (index >= htabslots) { 1042 assert(index == htabslots); 1043 index = 0; 1044 spapr->htab_first_pass = false; 1045 } 1046 spapr->htab_save_index = index; 1047 } 1048 1049 static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr, 1050 int64_t max_ns) 1051 { 1052 bool final = max_ns < 0; 1053 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1054 int examined = 0, sent = 0; 1055 int index = spapr->htab_save_index; 1056 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1057 1058 assert(!spapr->htab_first_pass); 1059 1060 do { 1061 int chunkstart, invalidstart; 1062 1063 /* Consume non-dirty HPTEs */ 1064 while ((index < htabslots) 1065 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1066 index++; 1067 examined++; 1068 } 1069 1070 chunkstart = index; 1071 /* Consume valid dirty HPTEs */ 1072 while ((index < htabslots) 1073 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1074 && HPTE_VALID(HPTE(spapr->htab, index))) { 1075 CLEAN_HPTE(HPTE(spapr->htab, index)); 1076 index++; 1077 examined++; 1078 } 1079 1080 invalidstart = index; 1081 /* Consume invalid dirty HPTEs */ 1082 while ((index < htabslots) 1083 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1084 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1085 CLEAN_HPTE(HPTE(spapr->htab, index)); 1086 index++; 1087 examined++; 1088 } 1089 1090 if (index > chunkstart) { 1091 int n_valid = invalidstart - chunkstart; 1092 int n_invalid = index - invalidstart; 1093 1094 qemu_put_be32(f, chunkstart); 1095 qemu_put_be16(f, n_valid); 1096 qemu_put_be16(f, n_invalid); 1097 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1098 HASH_PTE_SIZE_64 * n_valid); 1099 sent += index - chunkstart; 1100 1101 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1102 break; 1103 } 1104 } 1105 1106 if (examined >= htabslots) { 1107 break; 1108 } 1109 1110 if (index >= htabslots) { 1111 assert(index == htabslots); 1112 index = 0; 1113 } 1114 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1115 1116 if (index >= htabslots) { 1117 assert(index == htabslots); 1118 index = 0; 1119 } 1120 1121 spapr->htab_save_index = index; 1122 1123 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1124 } 1125 1126 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1127 #define MAX_KVM_BUF_SIZE 2048 1128 1129 static int htab_save_iterate(QEMUFile *f, void *opaque) 1130 { 1131 sPAPREnvironment *spapr = opaque; 1132 int rc = 0; 1133 1134 /* Iteration header */ 1135 qemu_put_be32(f, 0); 1136 1137 if (!spapr->htab) { 1138 assert(kvm_enabled()); 1139 1140 rc = kvmppc_save_htab(f, spapr->htab_fd, 1141 MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1142 if (rc < 0) { 1143 return rc; 1144 } 1145 } else if (spapr->htab_first_pass) { 1146 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1147 } else { 1148 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1149 } 1150 1151 /* End marker */ 1152 qemu_put_be32(f, 0); 1153 qemu_put_be16(f, 0); 1154 qemu_put_be16(f, 0); 1155 1156 return rc; 1157 } 1158 1159 static int htab_save_complete(QEMUFile *f, void *opaque) 1160 { 1161 sPAPREnvironment *spapr = opaque; 1162 1163 /* Iteration header */ 1164 qemu_put_be32(f, 0); 1165 1166 if (!spapr->htab) { 1167 int rc; 1168 1169 assert(kvm_enabled()); 1170 1171 rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1); 1172 if (rc < 0) { 1173 return rc; 1174 } 1175 close(spapr->htab_fd); 1176 spapr->htab_fd = -1; 1177 } else { 1178 htab_save_later_pass(f, spapr, -1); 1179 } 1180 1181 /* End marker */ 1182 qemu_put_be32(f, 0); 1183 qemu_put_be16(f, 0); 1184 qemu_put_be16(f, 0); 1185 1186 return 0; 1187 } 1188 1189 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1190 { 1191 sPAPREnvironment *spapr = opaque; 1192 uint32_t section_hdr; 1193 int fd = -1; 1194 1195 if (version_id < 1 || version_id > 1) { 1196 fprintf(stderr, "htab_load() bad version\n"); 1197 return -EINVAL; 1198 } 1199 1200 section_hdr = qemu_get_be32(f); 1201 1202 if (section_hdr) { 1203 /* First section, just the hash shift */ 1204 if (spapr->htab_shift != section_hdr) { 1205 return -EINVAL; 1206 } 1207 return 0; 1208 } 1209 1210 if (!spapr->htab) { 1211 assert(kvm_enabled()); 1212 1213 fd = kvmppc_get_htab_fd(true); 1214 if (fd < 0) { 1215 fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n", 1216 strerror(errno)); 1217 } 1218 } 1219 1220 while (true) { 1221 uint32_t index; 1222 uint16_t n_valid, n_invalid; 1223 1224 index = qemu_get_be32(f); 1225 n_valid = qemu_get_be16(f); 1226 n_invalid = qemu_get_be16(f); 1227 1228 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1229 /* End of Stream */ 1230 break; 1231 } 1232 1233 if ((index + n_valid + n_invalid) > 1234 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1235 /* Bad index in stream */ 1236 fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) " 1237 "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid, 1238 spapr->htab_shift); 1239 return -EINVAL; 1240 } 1241 1242 if (spapr->htab) { 1243 if (n_valid) { 1244 qemu_get_buffer(f, HPTE(spapr->htab, index), 1245 HASH_PTE_SIZE_64 * n_valid); 1246 } 1247 if (n_invalid) { 1248 memset(HPTE(spapr->htab, index + n_valid), 0, 1249 HASH_PTE_SIZE_64 * n_invalid); 1250 } 1251 } else { 1252 int rc; 1253 1254 assert(fd >= 0); 1255 1256 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1257 if (rc < 0) { 1258 return rc; 1259 } 1260 } 1261 } 1262 1263 if (!spapr->htab) { 1264 assert(fd >= 0); 1265 close(fd); 1266 } 1267 1268 return 0; 1269 } 1270 1271 static SaveVMHandlers savevm_htab_handlers = { 1272 .save_live_setup = htab_save_setup, 1273 .save_live_iterate = htab_save_iterate, 1274 .save_live_complete = htab_save_complete, 1275 .load_state = htab_load, 1276 }; 1277 1278 /* pSeries LPAR / sPAPR hardware init */ 1279 static void ppc_spapr_init(MachineState *machine) 1280 { 1281 ram_addr_t ram_size = machine->ram_size; 1282 const char *cpu_model = machine->cpu_model; 1283 const char *kernel_filename = machine->kernel_filename; 1284 const char *kernel_cmdline = machine->kernel_cmdline; 1285 const char *initrd_filename = machine->initrd_filename; 1286 const char *boot_device = machine->boot_order; 1287 PowerPCCPU *cpu; 1288 CPUPPCState *env; 1289 PCIHostState *phb; 1290 int i; 1291 MemoryRegion *sysmem = get_system_memory(); 1292 MemoryRegion *ram = g_new(MemoryRegion, 1); 1293 MemoryRegion *rma_region; 1294 void *rma = NULL; 1295 hwaddr rma_alloc_size; 1296 hwaddr node0_size = spapr_node0_size(); 1297 uint32_t initrd_base = 0; 1298 long kernel_size = 0, initrd_size = 0; 1299 long load_limit, fw_size; 1300 bool kernel_le = false; 1301 char *filename; 1302 1303 msi_supported = true; 1304 1305 spapr = g_malloc0(sizeof(*spapr)); 1306 QLIST_INIT(&spapr->phbs); 1307 1308 cpu_ppc_hypercall = emulate_spapr_hypercall; 1309 1310 /* Allocate RMA if necessary */ 1311 rma_alloc_size = kvmppc_alloc_rma(&rma); 1312 1313 if (rma_alloc_size == -1) { 1314 hw_error("qemu: Unable to create RMA\n"); 1315 exit(1); 1316 } 1317 1318 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1319 spapr->rma_size = rma_alloc_size; 1320 } else { 1321 spapr->rma_size = node0_size; 1322 1323 /* With KVM, we don't actually know whether KVM supports an 1324 * unbounded RMA (PR KVM) or is limited by the hash table size 1325 * (HV KVM using VRMA), so we always assume the latter 1326 * 1327 * In that case, we also limit the initial allocations for RTAS 1328 * etc... to 256M since we have no way to know what the VRMA size 1329 * is going to be as it depends on the size of the hash table 1330 * isn't determined yet. 1331 */ 1332 if (kvm_enabled()) { 1333 spapr->vrma_adjust = 1; 1334 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1335 } 1336 } 1337 1338 if (spapr->rma_size > node0_size) { 1339 fprintf(stderr, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")\n", 1340 spapr->rma_size); 1341 exit(1); 1342 } 1343 1344 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 1345 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 1346 1347 /* We aim for a hash table of size 1/128 the size of RAM. The 1348 * normal rule of thumb is 1/64 the size of RAM, but that's much 1349 * more than needed for the Linux guests we support. */ 1350 spapr->htab_shift = 18; /* Minimum architected size */ 1351 while (spapr->htab_shift <= 46) { 1352 if ((1ULL << (spapr->htab_shift + 7)) >= ram_size) { 1353 break; 1354 } 1355 spapr->htab_shift++; 1356 } 1357 1358 /* Set up Interrupt Controller before we create the VCPUs */ 1359 spapr->icp = xics_system_init(smp_cpus * kvmppc_smt_threads() / smp_threads, 1360 XICS_IRQS); 1361 1362 /* init CPUs */ 1363 if (cpu_model == NULL) { 1364 cpu_model = kvm_enabled() ? "host" : "POWER7"; 1365 } 1366 for (i = 0; i < smp_cpus; i++) { 1367 cpu = cpu_ppc_init(cpu_model); 1368 if (cpu == NULL) { 1369 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 1370 exit(1); 1371 } 1372 env = &cpu->env; 1373 1374 /* Set time-base frequency to 512 MHz */ 1375 cpu_ppc_tb_init(env, TIMEBASE_FREQ); 1376 1377 /* PAPR always has exception vectors in RAM not ROM. To ensure this, 1378 * MSR[IP] should never be set. 1379 */ 1380 env->msr_mask &= ~(1 << 6); 1381 1382 /* Tell KVM that we're in PAPR mode */ 1383 if (kvm_enabled()) { 1384 kvmppc_set_papr(cpu); 1385 } 1386 1387 if (cpu->max_compat) { 1388 if (ppc_set_compat(cpu, cpu->max_compat) < 0) { 1389 exit(1); 1390 } 1391 } 1392 1393 xics_cpu_setup(spapr->icp, cpu); 1394 1395 qemu_register_reset(spapr_cpu_reset, cpu); 1396 } 1397 1398 /* allocate RAM */ 1399 spapr->ram_limit = ram_size; 1400 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 1401 spapr->ram_limit); 1402 memory_region_add_subregion(sysmem, 0, ram); 1403 1404 if (rma_alloc_size && rma) { 1405 rma_region = g_new(MemoryRegion, 1); 1406 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 1407 rma_alloc_size, rma); 1408 vmstate_register_ram_global(rma_region); 1409 memory_region_add_subregion(sysmem, 0, rma_region); 1410 } 1411 1412 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 1413 spapr->rtas_size = get_image_size(filename); 1414 spapr->rtas_blob = g_malloc(spapr->rtas_size); 1415 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 1416 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 1417 exit(1); 1418 } 1419 if (spapr->rtas_size > RTAS_MAX_SIZE) { 1420 hw_error("RTAS too big ! 0x%zx bytes (max is 0x%x)\n", 1421 spapr->rtas_size, RTAS_MAX_SIZE); 1422 exit(1); 1423 } 1424 g_free(filename); 1425 1426 /* Set up EPOW events infrastructure */ 1427 spapr_events_init(spapr); 1428 1429 /* Set up VIO bus */ 1430 spapr->vio_bus = spapr_vio_bus_init(); 1431 1432 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 1433 if (serial_hds[i]) { 1434 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 1435 } 1436 } 1437 1438 /* We always have at least the nvram device on VIO */ 1439 spapr_create_nvram(spapr); 1440 1441 /* Set up PCI */ 1442 spapr_pci_rtas_init(); 1443 1444 phb = spapr_create_phb(spapr, 0); 1445 1446 for (i = 0; i < nb_nics; i++) { 1447 NICInfo *nd = &nd_table[i]; 1448 1449 if (!nd->model) { 1450 nd->model = g_strdup("ibmveth"); 1451 } 1452 1453 if (strcmp(nd->model, "ibmveth") == 0) { 1454 spapr_vlan_create(spapr->vio_bus, nd); 1455 } else { 1456 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 1457 } 1458 } 1459 1460 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 1461 spapr_vscsi_create(spapr->vio_bus); 1462 } 1463 1464 /* Graphics */ 1465 if (spapr_vga_init(phb->bus)) { 1466 spapr->has_graphics = true; 1467 } 1468 1469 if (usb_enabled(spapr->has_graphics)) { 1470 pci_create_simple(phb->bus, -1, "pci-ohci"); 1471 if (spapr->has_graphics) { 1472 usbdevice_create("keyboard"); 1473 usbdevice_create("mouse"); 1474 } 1475 } 1476 1477 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 1478 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= " 1479 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF); 1480 exit(1); 1481 } 1482 1483 if (kernel_filename) { 1484 uint64_t lowaddr = 0; 1485 1486 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 1487 NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); 1488 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) { 1489 kernel_size = load_elf(kernel_filename, 1490 translate_kernel_address, NULL, 1491 NULL, &lowaddr, NULL, 0, ELF_MACHINE, 0); 1492 kernel_le = kernel_size > 0; 1493 } 1494 if (kernel_size < 0) { 1495 fprintf(stderr, "qemu: error loading %s: %s\n", 1496 kernel_filename, load_elf_strerror(kernel_size)); 1497 exit(1); 1498 } 1499 1500 /* load initrd */ 1501 if (initrd_filename) { 1502 /* Try to locate the initrd in the gap between the kernel 1503 * and the firmware. Add a bit of space just in case 1504 */ 1505 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; 1506 initrd_size = load_image_targphys(initrd_filename, initrd_base, 1507 load_limit - initrd_base); 1508 if (initrd_size < 0) { 1509 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 1510 initrd_filename); 1511 exit(1); 1512 } 1513 } else { 1514 initrd_base = 0; 1515 initrd_size = 0; 1516 } 1517 } 1518 1519 if (bios_name == NULL) { 1520 bios_name = FW_FILE_NAME; 1521 } 1522 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1523 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 1524 if (fw_size < 0) { 1525 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 1526 exit(1); 1527 } 1528 g_free(filename); 1529 1530 spapr->entry_point = 0x100; 1531 1532 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 1533 register_savevm_live(NULL, "spapr/htab", -1, 1, 1534 &savevm_htab_handlers, spapr); 1535 1536 /* Prepare the device tree */ 1537 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, 1538 kernel_size, kernel_le, 1539 boot_device, kernel_cmdline, 1540 spapr->epow_irq); 1541 assert(spapr->fdt_skel != NULL); 1542 } 1543 1544 static int spapr_kvm_type(const char *vm_type) 1545 { 1546 if (!vm_type) { 1547 return 0; 1548 } 1549 1550 if (!strcmp(vm_type, "HV")) { 1551 return 1; 1552 } 1553 1554 if (!strcmp(vm_type, "PR")) { 1555 return 2; 1556 } 1557 1558 error_report("Unknown kvm-type specified '%s'", vm_type); 1559 exit(1); 1560 } 1561 1562 /* 1563 * Implementation of an interface to adjust firmware patch 1564 * for the bootindex property handling. 1565 */ 1566 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 1567 DeviceState *dev) 1568 { 1569 #define CAST(type, obj, name) \ 1570 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 1571 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 1572 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 1573 1574 if (d) { 1575 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 1576 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 1577 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 1578 1579 if (spapr) { 1580 /* 1581 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 1582 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 1583 * in the top 16 bits of the 64-bit LUN 1584 */ 1585 unsigned id = 0x8000 | (d->id << 8) | d->lun; 1586 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1587 (uint64_t)id << 48); 1588 } else if (virtio) { 1589 /* 1590 * We use SRP luns of the form 01000000 | (target << 8) | lun 1591 * in the top 32 bits of the 64-bit LUN 1592 * Note: the quote above is from SLOF and it is wrong, 1593 * the actual binding is: 1594 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 1595 */ 1596 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 1597 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1598 (uint64_t)id << 32); 1599 } else if (usb) { 1600 /* 1601 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 1602 * in the top 32 bits of the 64-bit LUN 1603 */ 1604 unsigned usb_port = atoi(usb->port->path); 1605 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 1606 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1607 (uint64_t)id << 32); 1608 } 1609 } 1610 1611 if (phb) { 1612 /* Replace "pci" with "pci@800000020000000" */ 1613 return g_strdup_printf("pci@%"PRIX64, phb->buid); 1614 } 1615 1616 return NULL; 1617 } 1618 1619 static char *spapr_get_kvm_type(Object *obj, Error **errp) 1620 { 1621 sPAPRMachineState *sm = SPAPR_MACHINE(obj); 1622 1623 return g_strdup(sm->kvm_type); 1624 } 1625 1626 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 1627 { 1628 sPAPRMachineState *sm = SPAPR_MACHINE(obj); 1629 1630 g_free(sm->kvm_type); 1631 sm->kvm_type = g_strdup(value); 1632 } 1633 1634 static void spapr_machine_initfn(Object *obj) 1635 { 1636 object_property_add_str(obj, "kvm-type", 1637 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 1638 } 1639 1640 static void ppc_cpu_do_nmi_on_cpu(void *arg) 1641 { 1642 CPUState *cs = arg; 1643 1644 cpu_synchronize_state(cs); 1645 ppc_cpu_do_system_reset(cs); 1646 } 1647 1648 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 1649 { 1650 CPUState *cs; 1651 1652 CPU_FOREACH(cs) { 1653 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs); 1654 } 1655 } 1656 1657 static void spapr_machine_class_init(ObjectClass *oc, void *data) 1658 { 1659 MachineClass *mc = MACHINE_CLASS(oc); 1660 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 1661 NMIClass *nc = NMI_CLASS(oc); 1662 1663 mc->init = ppc_spapr_init; 1664 mc->reset = ppc_spapr_reset; 1665 mc->block_default_type = IF_SCSI; 1666 mc->max_cpus = MAX_CPUS; 1667 mc->no_parallel = 1; 1668 mc->default_boot_order = NULL; 1669 mc->kvm_type = spapr_kvm_type; 1670 1671 fwc->get_dev_path = spapr_get_fw_dev_path; 1672 nc->nmi_monitor_handler = spapr_nmi; 1673 } 1674 1675 static const TypeInfo spapr_machine_info = { 1676 .name = TYPE_SPAPR_MACHINE, 1677 .parent = TYPE_MACHINE, 1678 .abstract = true, 1679 .instance_size = sizeof(sPAPRMachineState), 1680 .instance_init = spapr_machine_initfn, 1681 .class_init = spapr_machine_class_init, 1682 .interfaces = (InterfaceInfo[]) { 1683 { TYPE_FW_PATH_PROVIDER }, 1684 { TYPE_NMI }, 1685 { } 1686 }, 1687 }; 1688 1689 static void spapr_machine_2_1_class_init(ObjectClass *oc, void *data) 1690 { 1691 MachineClass *mc = MACHINE_CLASS(oc); 1692 static GlobalProperty compat_props[] = { 1693 HW_COMPAT_2_1, 1694 { /* end of list */ } 1695 }; 1696 1697 mc->name = "pseries-2.1"; 1698 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.1"; 1699 mc->compat_props = compat_props; 1700 } 1701 1702 static const TypeInfo spapr_machine_2_1_info = { 1703 .name = TYPE_SPAPR_MACHINE "2.1", 1704 .parent = TYPE_SPAPR_MACHINE, 1705 .class_init = spapr_machine_2_1_class_init, 1706 }; 1707 1708 static void spapr_machine_2_2_class_init(ObjectClass *oc, void *data) 1709 { 1710 MachineClass *mc = MACHINE_CLASS(oc); 1711 1712 mc->name = "pseries-2.2"; 1713 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.2"; 1714 mc->alias = "pseries"; 1715 mc->is_default = 1; 1716 } 1717 1718 static const TypeInfo spapr_machine_2_2_info = { 1719 .name = TYPE_SPAPR_MACHINE "2.2", 1720 .parent = TYPE_SPAPR_MACHINE, 1721 .class_init = spapr_machine_2_2_class_init, 1722 }; 1723 1724 static void spapr_machine_register_types(void) 1725 { 1726 type_register_static(&spapr_machine_info); 1727 type_register_static(&spapr_machine_2_1_info); 1728 type_register_static(&spapr_machine_2_2_info); 1729 } 1730 1731 type_init(spapr_machine_register_types) 1732