1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu/datadir.h" 29 #include "qemu/memalign.h" 30 #include "qemu/guest-random.h" 31 #include "qapi/error.h" 32 #include "qapi/qapi-events-machine.h" 33 #include "qapi/qapi-events-qdev.h" 34 #include "qapi/visitor.h" 35 #include "sysemu/sysemu.h" 36 #include "sysemu/hostmem.h" 37 #include "sysemu/numa.h" 38 #include "sysemu/qtest.h" 39 #include "sysemu/reset.h" 40 #include "sysemu/runstate.h" 41 #include "qemu/log.h" 42 #include "hw/fw-path-provider.h" 43 #include "elf.h" 44 #include "net/net.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/cpus.h" 47 #include "sysemu/hw_accel.h" 48 #include "kvm_ppc.h" 49 #include "migration/misc.h" 50 #include "migration/qemu-file-types.h" 51 #include "migration/global_state.h" 52 #include "migration/register.h" 53 #include "migration/blocker.h" 54 #include "mmu-hash64.h" 55 #include "mmu-book3s-v3.h" 56 #include "cpu-models.h" 57 #include "hw/core/cpu.h" 58 59 #include "hw/ppc/ppc.h" 60 #include "hw/loader.h" 61 62 #include "hw/ppc/fdt.h" 63 #include "hw/ppc/spapr.h" 64 #include "hw/ppc/spapr_nested.h" 65 #include "hw/ppc/spapr_vio.h" 66 #include "hw/ppc/vof.h" 67 #include "hw/qdev-properties.h" 68 #include "hw/pci-host/spapr.h" 69 #include "hw/pci/msi.h" 70 71 #include "hw/pci/pci.h" 72 #include "hw/scsi/scsi.h" 73 #include "hw/virtio/virtio-scsi.h" 74 #include "hw/virtio/vhost-scsi-common.h" 75 76 #include "exec/ram_addr.h" 77 #include "hw/usb.h" 78 #include "qemu/config-file.h" 79 #include "qemu/error-report.h" 80 #include "trace.h" 81 #include "hw/nmi.h" 82 #include "hw/intc/intc.h" 83 84 #include "hw/ppc/spapr_cpu_core.h" 85 #include "hw/mem/memory-device.h" 86 #include "hw/ppc/spapr_tpm_proxy.h" 87 #include "hw/ppc/spapr_nvdimm.h" 88 #include "hw/ppc/spapr_numa.h" 89 #include "hw/ppc/pef.h" 90 91 #include "monitor/monitor.h" 92 93 #include <libfdt.h> 94 95 /* SLOF memory layout: 96 * 97 * SLOF raw image loaded at 0, copies its romfs right below the flat 98 * device-tree, then position SLOF itself 31M below that 99 * 100 * So we set FW_OVERHEAD to 40MB which should account for all of that 101 * and more 102 * 103 * We load our kernel at 4M, leaving space for SLOF initial image 104 */ 105 #define FDT_MAX_ADDR 0x80000000 /* FDT must stay below that */ 106 #define FW_MAX_SIZE 0x400000 107 #define FW_FILE_NAME "slof.bin" 108 #define FW_FILE_NAME_VOF "vof.bin" 109 #define FW_OVERHEAD 0x2800000 110 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 111 112 #define MIN_RMA_SLOF (128 * MiB) 113 114 #define PHANDLE_INTC 0x00001111 115 116 /* These two functions implement the VCPU id numbering: one to compute them 117 * all and one to identify thread 0 of a VCORE. Any change to the first one 118 * is likely to have an impact on the second one, so let's keep them close. 119 */ 120 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 121 { 122 MachineState *ms = MACHINE(spapr); 123 unsigned int smp_threads = ms->smp.threads; 124 125 assert(spapr->vsmt); 126 return 127 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 128 } 129 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 130 PowerPCCPU *cpu) 131 { 132 assert(spapr->vsmt); 133 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 134 } 135 136 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 137 { 138 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 139 * and newer QEMUs don't even have them. In both cases, we don't want 140 * to send anything on the wire. 141 */ 142 return false; 143 } 144 145 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 146 /* 147 * Hack ahead. We can't have two devices with the same name and 148 * instance id. So I rename this to pass make check. 149 * Real help from people who knows the hardware is needed. 150 */ 151 .name = "icp/server", 152 .version_id = 1, 153 .minimum_version_id = 1, 154 .needed = pre_2_10_vmstate_dummy_icp_needed, 155 .fields = (const VMStateField[]) { 156 VMSTATE_UNUSED(4), /* uint32_t xirr */ 157 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 158 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 159 VMSTATE_END_OF_LIST() 160 }, 161 }; 162 163 /* 164 * See comment in hw/intc/xics.c:icp_realize() 165 * 166 * You have to remove vmstate_replace_hack_for_ppc() when you remove 167 * the machine types that need the following function. 168 */ 169 static void pre_2_10_vmstate_register_dummy_icp(int i) 170 { 171 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 172 (void *)(uintptr_t) i); 173 } 174 175 /* 176 * See comment in hw/intc/xics.c:icp_realize() 177 * 178 * You have to remove vmstate_replace_hack_for_ppc() when you remove 179 * the machine types that need the following function. 180 */ 181 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 182 { 183 /* 184 * This used to be: 185 * 186 * vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 187 * (void *)(uintptr_t) i); 188 */ 189 } 190 191 int spapr_max_server_number(SpaprMachineState *spapr) 192 { 193 MachineState *ms = MACHINE(spapr); 194 195 assert(spapr->vsmt); 196 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 197 } 198 199 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 200 int smt_threads) 201 { 202 int i, ret = 0; 203 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads); 204 g_autofree uint32_t *gservers_prop = g_new(uint32_t, smt_threads * 2); 205 int index = spapr_get_vcpu_id(cpu); 206 207 if (cpu->compat_pvr) { 208 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 209 if (ret < 0) { 210 return ret; 211 } 212 } 213 214 /* Build interrupt servers and gservers properties */ 215 for (i = 0; i < smt_threads; i++) { 216 servers_prop[i] = cpu_to_be32(index + i); 217 /* Hack, direct the group queues back to cpu 0 */ 218 gservers_prop[i*2] = cpu_to_be32(index + i); 219 gservers_prop[i*2 + 1] = 0; 220 } 221 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 222 servers_prop, sizeof(*servers_prop) * smt_threads); 223 if (ret < 0) { 224 return ret; 225 } 226 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 227 gservers_prop, sizeof(*gservers_prop) * smt_threads * 2); 228 229 return ret; 230 } 231 232 static void spapr_dt_pa_features(SpaprMachineState *spapr, 233 PowerPCCPU *cpu, 234 void *fdt, int offset) 235 { 236 /* 237 * SSO (SAO) ordering is supported on KVM and thread=single hosts, 238 * but not MTTCG, so disable it. To advertise it, a cap would have 239 * to be added, or support implemented for MTTCG. 240 * 241 * Copy/paste is not supported by TCG, so it is not advertised. KVM 242 * can execute them but it has no accelerator drivers which are usable, 243 * so there isn't much need for it anyway. 244 */ 245 246 /* These should be kept in sync with pnv */ 247 uint8_t pa_features_206[] = { 6, 0, 248 0xf6, 0x1f, 0xc7, 0x00, 0x00, 0xc0 }; 249 uint8_t pa_features_207[] = { 24, 0, 250 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, 251 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 252 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 253 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 254 uint8_t pa_features_300[] = { 66, 0, 255 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 256 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 257 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 258 /* 6: DS207 */ 259 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 260 /* 16: Vector */ 261 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 262 /* 18: Vec. Scalar, 20: Vec. XOR */ 263 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 264 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 265 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 266 /* 32: LE atomic, 34: EBB + ext EBB */ 267 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 268 /* 40: Radix MMU */ 269 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 270 /* 42: PM, 44: PC RA, 46: SC vec'd */ 271 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 272 /* 48: SIMD, 50: QP BFP, 52: String */ 273 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 274 /* 54: DecFP, 56: DecI, 58: SHA */ 275 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 276 /* 60: NM atomic, 62: RNG */ 277 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 278 }; 279 /* 3.1 removes SAO, HTM support */ 280 uint8_t pa_features_31[] = { 74, 0, 281 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 282 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 283 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 284 /* 6: DS207 */ 285 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 286 /* 16: Vector */ 287 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 288 /* 18: Vec. Scalar, 20: Vec. XOR */ 289 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 290 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 291 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 292 /* 32: LE atomic, 34: EBB + ext EBB */ 293 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 294 /* 40: Radix MMU */ 295 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 296 /* 42: PM, 44: PC RA, 46: SC vec'd */ 297 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 298 /* 48: SIMD, 50: QP BFP, 52: String */ 299 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 300 /* 54: DecFP, 56: DecI, 58: SHA */ 301 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 302 /* 60: NM atomic, 62: RNG */ 303 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 304 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */ 305 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */ 306 /* 72: [P]HASHST/[P]HASHCHK */ 307 0x80, 0x00, /* 72 - 73 */ 308 }; 309 uint8_t *pa_features = NULL; 310 size_t pa_size; 311 312 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 313 pa_features = pa_features_206; 314 pa_size = sizeof(pa_features_206); 315 } 316 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 317 pa_features = pa_features_207; 318 pa_size = sizeof(pa_features_207); 319 } 320 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 321 pa_features = pa_features_300; 322 pa_size = sizeof(pa_features_300); 323 } 324 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10, 0, cpu->compat_pvr)) { 325 pa_features = pa_features_31; 326 pa_size = sizeof(pa_features_31); 327 } 328 if (!pa_features) { 329 return; 330 } 331 332 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 333 /* 334 * Note: we keep CI large pages off by default because a 64K capable 335 * guest provisioned with large pages might otherwise try to map a qemu 336 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 337 * even if that qemu runs on a 4k host. 338 * We dd this bit back here if we are confident this is not an issue 339 */ 340 pa_features[3] |= 0x20; 341 } 342 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 343 pa_features[24] |= 0x80; /* Transactional memory support */ 344 } 345 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 346 /* Workaround for broken kernels that attempt (guest) radix 347 * mode when they can't handle it, if they see the radix bit set 348 * in pa-features. So hide it from them. */ 349 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 350 } 351 352 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 353 } 354 355 static hwaddr spapr_node0_size(MachineState *machine) 356 { 357 if (machine->numa_state->num_nodes) { 358 int i; 359 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 360 if (machine->numa_state->nodes[i].node_mem) { 361 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 362 machine->ram_size); 363 } 364 } 365 } 366 return machine->ram_size; 367 } 368 369 static void add_str(GString *s, const gchar *s1) 370 { 371 g_string_append_len(s, s1, strlen(s1) + 1); 372 } 373 374 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 375 hwaddr start, hwaddr size) 376 { 377 char mem_name[32]; 378 uint64_t mem_reg_property[2]; 379 int off; 380 381 mem_reg_property[0] = cpu_to_be64(start); 382 mem_reg_property[1] = cpu_to_be64(size); 383 384 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 385 off = fdt_add_subnode(fdt, 0, mem_name); 386 _FDT(off); 387 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 388 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 389 sizeof(mem_reg_property)))); 390 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 391 return off; 392 } 393 394 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 395 { 396 MemoryDeviceInfoList *info; 397 398 for (info = list; info; info = info->next) { 399 MemoryDeviceInfo *value = info->value; 400 401 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 402 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 403 404 if (addr >= pcdimm_info->addr && 405 addr < (pcdimm_info->addr + pcdimm_info->size)) { 406 return pcdimm_info->node; 407 } 408 } 409 } 410 411 return -1; 412 } 413 414 struct sPAPRDrconfCellV2 { 415 uint32_t seq_lmbs; 416 uint64_t base_addr; 417 uint32_t drc_index; 418 uint32_t aa_index; 419 uint32_t flags; 420 } QEMU_PACKED; 421 422 typedef struct DrconfCellQueue { 423 struct sPAPRDrconfCellV2 cell; 424 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 425 } DrconfCellQueue; 426 427 static DrconfCellQueue * 428 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 429 uint32_t drc_index, uint32_t aa_index, 430 uint32_t flags) 431 { 432 DrconfCellQueue *elem; 433 434 elem = g_malloc0(sizeof(*elem)); 435 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 436 elem->cell.base_addr = cpu_to_be64(base_addr); 437 elem->cell.drc_index = cpu_to_be32(drc_index); 438 elem->cell.aa_index = cpu_to_be32(aa_index); 439 elem->cell.flags = cpu_to_be32(flags); 440 441 return elem; 442 } 443 444 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 445 int offset, MemoryDeviceInfoList *dimms) 446 { 447 MachineState *machine = MACHINE(spapr); 448 uint8_t *int_buf, *cur_index; 449 int ret; 450 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 451 uint64_t addr, cur_addr, size; 452 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 453 uint64_t mem_end = machine->device_memory->base + 454 memory_region_size(&machine->device_memory->mr); 455 uint32_t node, buf_len, nr_entries = 0; 456 SpaprDrc *drc; 457 DrconfCellQueue *elem, *next; 458 MemoryDeviceInfoList *info; 459 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 460 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 461 462 /* Entry to cover RAM and the gap area */ 463 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 464 SPAPR_LMB_FLAGS_RESERVED | 465 SPAPR_LMB_FLAGS_DRC_INVALID); 466 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 467 nr_entries++; 468 469 cur_addr = machine->device_memory->base; 470 for (info = dimms; info; info = info->next) { 471 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 472 473 addr = di->addr; 474 size = di->size; 475 node = di->node; 476 477 /* 478 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 479 * area is marked hotpluggable in the next iteration for the bigger 480 * chunk including the NVDIMM occupied area. 481 */ 482 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 483 continue; 484 485 /* Entry for hot-pluggable area */ 486 if (cur_addr < addr) { 487 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 488 g_assert(drc); 489 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 490 cur_addr, spapr_drc_index(drc), -1, 0); 491 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 492 nr_entries++; 493 } 494 495 /* Entry for DIMM */ 496 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 497 g_assert(drc); 498 elem = spapr_get_drconf_cell(size / lmb_size, addr, 499 spapr_drc_index(drc), node, 500 (SPAPR_LMB_FLAGS_ASSIGNED | 501 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 502 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 503 nr_entries++; 504 cur_addr = addr + size; 505 } 506 507 /* Entry for remaining hotpluggable area */ 508 if (cur_addr < mem_end) { 509 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 510 g_assert(drc); 511 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 512 cur_addr, spapr_drc_index(drc), -1, 0); 513 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 514 nr_entries++; 515 } 516 517 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 518 int_buf = cur_index = g_malloc0(buf_len); 519 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 520 cur_index += sizeof(nr_entries); 521 522 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 523 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 524 cur_index += sizeof(elem->cell); 525 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 526 g_free(elem); 527 } 528 529 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 530 g_free(int_buf); 531 if (ret < 0) { 532 return -1; 533 } 534 return 0; 535 } 536 537 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 538 int offset, MemoryDeviceInfoList *dimms) 539 { 540 MachineState *machine = MACHINE(spapr); 541 int i, ret; 542 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 543 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 544 uint32_t nr_lmbs = (machine->device_memory->base + 545 memory_region_size(&machine->device_memory->mr)) / 546 lmb_size; 547 uint32_t *int_buf, *cur_index, buf_len; 548 549 /* 550 * Allocate enough buffer size to fit in ibm,dynamic-memory 551 */ 552 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 553 cur_index = int_buf = g_malloc0(buf_len); 554 int_buf[0] = cpu_to_be32(nr_lmbs); 555 cur_index++; 556 for (i = 0; i < nr_lmbs; i++) { 557 uint64_t addr = i * lmb_size; 558 uint32_t *dynamic_memory = cur_index; 559 560 if (i >= device_lmb_start) { 561 SpaprDrc *drc; 562 563 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 564 g_assert(drc); 565 566 dynamic_memory[0] = cpu_to_be32(addr >> 32); 567 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 568 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 569 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 570 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 571 if (memory_region_present(get_system_memory(), addr)) { 572 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 573 } else { 574 dynamic_memory[5] = cpu_to_be32(0); 575 } 576 } else { 577 /* 578 * LMB information for RMA, boot time RAM and gap b/n RAM and 579 * device memory region -- all these are marked as reserved 580 * and as having no valid DRC. 581 */ 582 dynamic_memory[0] = cpu_to_be32(addr >> 32); 583 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 584 dynamic_memory[2] = cpu_to_be32(0); 585 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 586 dynamic_memory[4] = cpu_to_be32(-1); 587 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 588 SPAPR_LMB_FLAGS_DRC_INVALID); 589 } 590 591 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 592 } 593 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 594 g_free(int_buf); 595 if (ret < 0) { 596 return -1; 597 } 598 return 0; 599 } 600 601 /* 602 * Adds ibm,dynamic-reconfiguration-memory node. 603 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 604 * of this device tree node. 605 */ 606 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 607 void *fdt) 608 { 609 MachineState *machine = MACHINE(spapr); 610 int ret, offset; 611 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 612 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 613 cpu_to_be32(lmb_size & 0xffffffff)}; 614 MemoryDeviceInfoList *dimms = NULL; 615 616 /* Don't create the node if there is no device memory. */ 617 if (!machine->device_memory) { 618 return 0; 619 } 620 621 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 622 623 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 624 sizeof(prop_lmb_size)); 625 if (ret < 0) { 626 return ret; 627 } 628 629 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 630 if (ret < 0) { 631 return ret; 632 } 633 634 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 635 if (ret < 0) { 636 return ret; 637 } 638 639 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 640 dimms = qmp_memory_device_list(); 641 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 642 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 643 } else { 644 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 645 } 646 qapi_free_MemoryDeviceInfoList(dimms); 647 648 if (ret < 0) { 649 return ret; 650 } 651 652 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 653 654 return ret; 655 } 656 657 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 658 { 659 MachineState *machine = MACHINE(spapr); 660 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 661 hwaddr mem_start, node_size; 662 int i, nb_nodes = machine->numa_state->num_nodes; 663 NodeInfo *nodes = machine->numa_state->nodes; 664 665 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 666 if (!nodes[i].node_mem) { 667 continue; 668 } 669 if (mem_start >= machine->ram_size) { 670 node_size = 0; 671 } else { 672 node_size = nodes[i].node_mem; 673 if (node_size > machine->ram_size - mem_start) { 674 node_size = machine->ram_size - mem_start; 675 } 676 } 677 if (!mem_start) { 678 /* spapr_machine_init() checks for rma_size <= node0_size 679 * already */ 680 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 681 mem_start += spapr->rma_size; 682 node_size -= spapr->rma_size; 683 } 684 for ( ; node_size; ) { 685 hwaddr sizetmp = pow2floor(node_size); 686 687 /* mem_start != 0 here */ 688 if (ctzl(mem_start) < ctzl(sizetmp)) { 689 sizetmp = 1ULL << ctzl(mem_start); 690 } 691 692 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 693 node_size -= sizetmp; 694 mem_start += sizetmp; 695 } 696 } 697 698 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 699 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 700 int ret; 701 702 g_assert(smc->dr_lmb_enabled); 703 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 704 if (ret) { 705 return ret; 706 } 707 } 708 709 return 0; 710 } 711 712 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 713 SpaprMachineState *spapr) 714 { 715 MachineState *ms = MACHINE(spapr); 716 PowerPCCPU *cpu = POWERPC_CPU(cs); 717 CPUPPCState *env = &cpu->env; 718 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 719 int index = spapr_get_vcpu_id(cpu); 720 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 721 0xffffffff, 0xffffffff}; 722 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 723 : SPAPR_TIMEBASE_FREQ; 724 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 725 uint32_t page_sizes_prop[64]; 726 size_t page_sizes_prop_size; 727 unsigned int smp_threads = ms->smp.threads; 728 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 729 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 730 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 731 SpaprDrc *drc; 732 int drc_index; 733 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 734 int i; 735 736 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 737 if (drc) { 738 drc_index = spapr_drc_index(drc); 739 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 740 } 741 742 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 743 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 744 745 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 746 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 747 env->dcache_line_size))); 748 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 749 env->dcache_line_size))); 750 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 751 env->icache_line_size))); 752 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 753 env->icache_line_size))); 754 755 if (pcc->l1_dcache_size) { 756 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 757 pcc->l1_dcache_size))); 758 } else { 759 warn_report("Unknown L1 dcache size for cpu"); 760 } 761 if (pcc->l1_icache_size) { 762 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 763 pcc->l1_icache_size))); 764 } else { 765 warn_report("Unknown L1 icache size for cpu"); 766 } 767 768 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 769 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 770 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 771 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 772 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 773 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 774 775 if (ppc_has_spr(cpu, SPR_PURR)) { 776 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 777 } 778 if (ppc_has_spr(cpu, SPR_PURR)) { 779 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 780 } 781 782 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 783 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 784 segs, sizeof(segs)))); 785 } 786 787 /* Advertise VSX (vector extensions) if available 788 * 1 == VMX / Altivec available 789 * 2 == VSX available 790 * 791 * Only CPUs for which we create core types in spapr_cpu_core.c 792 * are possible, and all of those have VMX */ 793 if (env->insns_flags & PPC_ALTIVEC) { 794 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 795 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 796 } else { 797 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 798 } 799 } 800 801 /* Advertise DFP (Decimal Floating Point) if available 802 * 0 / no property == no DFP 803 * 1 == DFP available */ 804 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 805 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 806 } 807 808 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 809 sizeof(page_sizes_prop)); 810 if (page_sizes_prop_size) { 811 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 812 page_sizes_prop, page_sizes_prop_size))); 813 } 814 815 spapr_dt_pa_features(spapr, cpu, fdt, offset); 816 817 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 818 cs->cpu_index / vcpus_per_socket))); 819 820 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 821 pft_size_prop, sizeof(pft_size_prop)))); 822 823 if (ms->numa_state->num_nodes > 1) { 824 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 825 } 826 827 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 828 829 if (pcc->radix_page_info) { 830 for (i = 0; i < pcc->radix_page_info->count; i++) { 831 radix_AP_encodings[i] = 832 cpu_to_be32(pcc->radix_page_info->entries[i]); 833 } 834 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 835 radix_AP_encodings, 836 pcc->radix_page_info->count * 837 sizeof(radix_AP_encodings[0])))); 838 } 839 840 /* 841 * We set this property to let the guest know that it can use the large 842 * decrementer and its width in bits. 843 */ 844 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 845 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 846 pcc->lrg_decr_bits))); 847 } 848 849 static void spapr_dt_one_cpu(void *fdt, SpaprMachineState *spapr, CPUState *cs, 850 int cpus_offset) 851 { 852 PowerPCCPU *cpu = POWERPC_CPU(cs); 853 int index = spapr_get_vcpu_id(cpu); 854 DeviceClass *dc = DEVICE_GET_CLASS(cs); 855 g_autofree char *nodename = NULL; 856 int offset; 857 858 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 859 return; 860 } 861 862 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 863 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 864 _FDT(offset); 865 spapr_dt_cpu(cs, fdt, offset, spapr); 866 } 867 868 869 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 870 { 871 CPUState **rev; 872 CPUState *cs; 873 int n_cpus; 874 int cpus_offset; 875 int i; 876 877 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 878 _FDT(cpus_offset); 879 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 880 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 881 882 /* 883 * We walk the CPUs in reverse order to ensure that CPU DT nodes 884 * created by fdt_add_subnode() end up in the right order in FDT 885 * for the guest kernel the enumerate the CPUs correctly. 886 * 887 * The CPU list cannot be traversed in reverse order, so we need 888 * to do extra work. 889 */ 890 n_cpus = 0; 891 rev = NULL; 892 CPU_FOREACH(cs) { 893 rev = g_renew(CPUState *, rev, n_cpus + 1); 894 rev[n_cpus++] = cs; 895 } 896 897 for (i = n_cpus - 1; i >= 0; i--) { 898 spapr_dt_one_cpu(fdt, spapr, rev[i], cpus_offset); 899 } 900 901 g_free(rev); 902 } 903 904 static int spapr_dt_rng(void *fdt) 905 { 906 int node; 907 int ret; 908 909 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 910 if (node <= 0) { 911 return -1; 912 } 913 ret = fdt_setprop_string(fdt, node, "device_type", 914 "ibm,platform-facilities"); 915 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 916 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 917 918 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 919 if (node <= 0) { 920 return -1; 921 } 922 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 923 924 return ret ? -1 : 0; 925 } 926 927 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 928 { 929 MachineState *ms = MACHINE(spapr); 930 int rtas; 931 GString *hypertas = g_string_sized_new(256); 932 GString *qemu_hypertas = g_string_sized_new(256); 933 uint32_t lrdr_capacity[] = { 934 0, 935 0, 936 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 937 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 938 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 939 }; 940 941 /* Do we have device memory? */ 942 if (MACHINE(spapr)->device_memory) { 943 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 944 memory_region_size(&MACHINE(spapr)->device_memory->mr); 945 946 lrdr_capacity[0] = cpu_to_be32(max_device_addr >> 32); 947 lrdr_capacity[1] = cpu_to_be32(max_device_addr & 0xffffffff); 948 } 949 950 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 951 952 /* hypertas */ 953 add_str(hypertas, "hcall-pft"); 954 add_str(hypertas, "hcall-term"); 955 add_str(hypertas, "hcall-dabr"); 956 add_str(hypertas, "hcall-interrupt"); 957 add_str(hypertas, "hcall-tce"); 958 add_str(hypertas, "hcall-vio"); 959 add_str(hypertas, "hcall-splpar"); 960 add_str(hypertas, "hcall-join"); 961 add_str(hypertas, "hcall-bulk"); 962 add_str(hypertas, "hcall-set-mode"); 963 add_str(hypertas, "hcall-sprg0"); 964 add_str(hypertas, "hcall-copy"); 965 add_str(hypertas, "hcall-debug"); 966 add_str(hypertas, "hcall-vphn"); 967 if (spapr_get_cap(spapr, SPAPR_CAP_RPT_INVALIDATE) == SPAPR_CAP_ON) { 968 add_str(hypertas, "hcall-rpt-invalidate"); 969 } 970 971 add_str(qemu_hypertas, "hcall-memop1"); 972 973 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 974 add_str(hypertas, "hcall-multi-tce"); 975 } 976 977 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 978 add_str(hypertas, "hcall-hpt-resize"); 979 } 980 981 add_str(hypertas, "hcall-watchdog"); 982 983 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 984 hypertas->str, hypertas->len)); 985 g_string_free(hypertas, TRUE); 986 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 987 qemu_hypertas->str, qemu_hypertas->len)); 988 g_string_free(qemu_hypertas, TRUE); 989 990 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 991 992 /* 993 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 994 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 995 * 996 * The system reset requirements are driven by existing Linux and PowerVM 997 * implementation which (contrary to PAPR) saves r3 in the error log 998 * structure like machine check, so Linux expects to find the saved r3 999 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 1000 * does not look at the error value). 1001 * 1002 * System reset interrupts are not subject to interlock like machine 1003 * check, so this memory area could be corrupted if the sreset is 1004 * interrupted by a machine check (or vice versa) if it was shared. To 1005 * prevent this, system reset uses per-CPU areas for the sreset save 1006 * area. A system reset that interrupts a system reset handler could 1007 * still overwrite this area, but Linux doesn't try to recover in that 1008 * case anyway. 1009 * 1010 * The extra 8 bytes is required because Linux's FWNMI error log check 1011 * is off-by-one. 1012 * 1013 * RTAS_MIN_SIZE is required for the RTAS blob itself. 1014 */ 1015 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_MIN_SIZE + 1016 RTAS_ERROR_LOG_MAX + 1017 ms->smp.max_cpus * sizeof(uint64_t) * 2 + 1018 sizeof(uint64_t))); 1019 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 1020 RTAS_ERROR_LOG_MAX)); 1021 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 1022 RTAS_EVENT_SCAN_RATE)); 1023 1024 g_assert(msi_nonbroken); 1025 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 1026 1027 /* 1028 * According to PAPR, rtas ibm,os-term does not guarantee a return 1029 * back to the guest cpu. 1030 * 1031 * While an additional ibm,extended-os-term property indicates 1032 * that rtas call return will always occur. Set this property. 1033 */ 1034 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 1035 1036 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 1037 lrdr_capacity, sizeof(lrdr_capacity))); 1038 1039 spapr_dt_rtas_tokens(fdt, rtas); 1040 } 1041 1042 /* 1043 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 1044 * and the XIVE features that the guest may request and thus the valid 1045 * values for bytes 23..26 of option vector 5: 1046 */ 1047 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 1048 int chosen) 1049 { 1050 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1051 1052 char val[2 * 4] = { 1053 23, 0x00, /* XICS / XIVE mode */ 1054 24, 0x00, /* Hash/Radix, filled in below. */ 1055 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 1056 26, 0x40, /* Radix options: GTSE == yes. */ 1057 }; 1058 1059 if (spapr->irq->xics && spapr->irq->xive) { 1060 val[1] = SPAPR_OV5_XIVE_BOTH; 1061 } else if (spapr->irq->xive) { 1062 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 1063 } else { 1064 assert(spapr->irq->xics); 1065 val[1] = SPAPR_OV5_XIVE_LEGACY; 1066 } 1067 1068 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1069 first_ppc_cpu->compat_pvr)) { 1070 /* 1071 * If we're in a pre POWER9 compat mode then the guest should 1072 * do hash and use the legacy interrupt mode 1073 */ 1074 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 1075 val[3] = 0x00; /* Hash */ 1076 spapr_check_mmu_mode(false); 1077 } else if (kvm_enabled()) { 1078 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 1079 val[3] = 0x80; /* OV5_MMU_BOTH */ 1080 } else if (kvmppc_has_cap_mmu_radix()) { 1081 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1082 } else { 1083 val[3] = 0x00; /* Hash */ 1084 } 1085 } else { 1086 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1087 val[3] = 0xC0; 1088 } 1089 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1090 val, sizeof(val))); 1091 } 1092 1093 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1094 { 1095 MachineState *machine = MACHINE(spapr); 1096 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1097 int chosen; 1098 1099 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1100 1101 if (reset) { 1102 const char *boot_device = spapr->boot_device; 1103 g_autofree char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1104 size_t cb = 0; 1105 g_autofree char *bootlist = get_boot_devices_list(&cb); 1106 1107 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1108 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1109 machine->kernel_cmdline)); 1110 } 1111 1112 if (spapr->initrd_size) { 1113 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1114 spapr->initrd_base)); 1115 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1116 spapr->initrd_base + spapr->initrd_size)); 1117 } 1118 1119 if (spapr->kernel_size) { 1120 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1121 cpu_to_be64(spapr->kernel_size) }; 1122 1123 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1124 &kprop, sizeof(kprop))); 1125 if (spapr->kernel_le) { 1126 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1127 } 1128 } 1129 if (machine->boot_config.has_menu && machine->boot_config.menu) { 1130 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", true))); 1131 } 1132 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1133 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1134 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1135 1136 if (cb && bootlist) { 1137 int i; 1138 1139 for (i = 0; i < cb; i++) { 1140 if (bootlist[i] == '\n') { 1141 bootlist[i] = ' '; 1142 } 1143 } 1144 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1145 } 1146 1147 if (boot_device && strlen(boot_device)) { 1148 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1149 } 1150 1151 if (spapr->want_stdout_path && stdout_path) { 1152 /* 1153 * "linux,stdout-path" and "stdout" properties are 1154 * deprecated by linux kernel. New platforms should only 1155 * use the "stdout-path" property. Set the new property 1156 * and continue using older property to remain compatible 1157 * with the existing firmware. 1158 */ 1159 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1160 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1161 } 1162 1163 /* 1164 * We can deal with BAR reallocation just fine, advertise it 1165 * to the guest 1166 */ 1167 if (smc->linux_pci_probe) { 1168 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1169 } 1170 1171 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1172 } 1173 1174 _FDT(fdt_setprop(fdt, chosen, "rng-seed", spapr->fdt_rng_seed, 32)); 1175 1176 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1177 } 1178 1179 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1180 { 1181 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1182 * KVM to work under pHyp with some guest co-operation */ 1183 int hypervisor; 1184 uint8_t hypercall[16]; 1185 1186 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1187 /* indicate KVM hypercall interface */ 1188 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1189 if (kvmppc_has_cap_fixup_hcalls()) { 1190 /* 1191 * Older KVM versions with older guest kernels were broken 1192 * with the magic page, don't allow the guest to map it. 1193 */ 1194 if (!kvmppc_get_hypercall(cpu_env(first_cpu), hypercall, 1195 sizeof(hypercall))) { 1196 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1197 hypercall, sizeof(hypercall))); 1198 } 1199 } 1200 } 1201 1202 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1203 { 1204 MachineState *machine = MACHINE(spapr); 1205 MachineClass *mc = MACHINE_GET_CLASS(machine); 1206 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1207 uint32_t root_drc_type_mask = 0; 1208 int ret; 1209 void *fdt; 1210 SpaprPhbState *phb; 1211 char *buf; 1212 1213 fdt = g_malloc0(space); 1214 _FDT((fdt_create_empty_tree(fdt, space))); 1215 1216 /* Root node */ 1217 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1218 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1219 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1220 1221 /* Guest UUID & Name*/ 1222 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1223 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1224 if (qemu_uuid_set) { 1225 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1226 } 1227 g_free(buf); 1228 1229 if (qemu_get_vm_name()) { 1230 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1231 qemu_get_vm_name())); 1232 } 1233 1234 /* Host Model & Serial Number */ 1235 if (spapr->host_model) { 1236 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1237 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1238 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1239 g_free(buf); 1240 } 1241 1242 if (spapr->host_serial) { 1243 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1244 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1245 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1246 g_free(buf); 1247 } 1248 1249 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1250 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1251 1252 /* /interrupt controller */ 1253 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1254 1255 ret = spapr_dt_memory(spapr, fdt); 1256 if (ret < 0) { 1257 error_report("couldn't setup memory nodes in fdt"); 1258 exit(1); 1259 } 1260 1261 /* /vdevice */ 1262 spapr_dt_vdevice(spapr->vio_bus, fdt); 1263 1264 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1265 ret = spapr_dt_rng(fdt); 1266 if (ret < 0) { 1267 error_report("could not set up rng device in the fdt"); 1268 exit(1); 1269 } 1270 } 1271 1272 QLIST_FOREACH(phb, &spapr->phbs, list) { 1273 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1274 if (ret < 0) { 1275 error_report("couldn't setup PCI devices in fdt"); 1276 exit(1); 1277 } 1278 } 1279 1280 spapr_dt_cpus(fdt, spapr); 1281 1282 /* ibm,drc-indexes and friends */ 1283 if (smc->dr_lmb_enabled) { 1284 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; 1285 } 1286 if (smc->dr_phb_enabled) { 1287 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; 1288 } 1289 if (mc->nvdimm_supported) { 1290 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM; 1291 } 1292 if (root_drc_type_mask) { 1293 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask)); 1294 } 1295 1296 if (mc->has_hotpluggable_cpus) { 1297 int offset = fdt_path_offset(fdt, "/cpus"); 1298 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1299 if (ret < 0) { 1300 error_report("Couldn't set up CPU DR device tree properties"); 1301 exit(1); 1302 } 1303 } 1304 1305 /* /event-sources */ 1306 spapr_dt_events(spapr, fdt); 1307 1308 /* /rtas */ 1309 spapr_dt_rtas(spapr, fdt); 1310 1311 /* /chosen */ 1312 spapr_dt_chosen(spapr, fdt, reset); 1313 1314 /* /hypervisor */ 1315 if (kvm_enabled()) { 1316 spapr_dt_hypervisor(spapr, fdt); 1317 } 1318 1319 /* Build memory reserve map */ 1320 if (reset) { 1321 if (spapr->kernel_size) { 1322 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1323 spapr->kernel_size))); 1324 } 1325 if (spapr->initrd_size) { 1326 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1327 spapr->initrd_size))); 1328 } 1329 } 1330 1331 /* NVDIMM devices */ 1332 if (mc->nvdimm_supported) { 1333 spapr_dt_persistent_memory(spapr, fdt); 1334 } 1335 1336 return fdt; 1337 } 1338 1339 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1340 { 1341 SpaprMachineState *spapr = opaque; 1342 1343 return (addr & 0x0fffffff) + spapr->kernel_addr; 1344 } 1345 1346 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1347 PowerPCCPU *cpu) 1348 { 1349 CPUPPCState *env = &cpu->env; 1350 1351 /* The TCG path should also be holding the BQL at this point */ 1352 g_assert(bql_locked()); 1353 1354 g_assert(!vhyp_cpu_in_nested(cpu)); 1355 1356 if (FIELD_EX64(env->msr, MSR, PR)) { 1357 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1358 env->gpr[3] = H_PRIVILEGE; 1359 } else { 1360 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1361 } 1362 } 1363 1364 struct LPCRSyncState { 1365 target_ulong value; 1366 target_ulong mask; 1367 }; 1368 1369 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1370 { 1371 struct LPCRSyncState *s = arg.host_ptr; 1372 PowerPCCPU *cpu = POWERPC_CPU(cs); 1373 CPUPPCState *env = &cpu->env; 1374 target_ulong lpcr; 1375 1376 cpu_synchronize_state(cs); 1377 lpcr = env->spr[SPR_LPCR]; 1378 lpcr &= ~s->mask; 1379 lpcr |= s->value; 1380 ppc_store_lpcr(cpu, lpcr); 1381 } 1382 1383 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1384 { 1385 CPUState *cs; 1386 struct LPCRSyncState s = { 1387 .value = value, 1388 .mask = mask 1389 }; 1390 CPU_FOREACH(cs) { 1391 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1392 } 1393 } 1394 1395 /* May be used when the machine is not running */ 1396 void spapr_init_all_lpcrs(target_ulong value, target_ulong mask) 1397 { 1398 CPUState *cs; 1399 CPU_FOREACH(cs) { 1400 PowerPCCPU *cpu = POWERPC_CPU(cs); 1401 CPUPPCState *env = &cpu->env; 1402 target_ulong lpcr; 1403 1404 lpcr = env->spr[SPR_LPCR]; 1405 lpcr &= ~(LPCR_HR | LPCR_UPRT); 1406 ppc_store_lpcr(cpu, lpcr); 1407 } 1408 } 1409 1410 1411 static bool spapr_get_pate(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu, 1412 target_ulong lpid, ppc_v3_pate_t *entry) 1413 { 1414 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1415 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 1416 1417 if (!spapr_cpu->in_nested) { 1418 assert(lpid == 0); 1419 1420 /* Copy PATE1:GR into PATE0:HR */ 1421 entry->dw0 = spapr->patb_entry & PATE0_HR; 1422 entry->dw1 = spapr->patb_entry; 1423 1424 } else { 1425 uint64_t patb, pats; 1426 1427 assert(lpid != 0); 1428 1429 patb = spapr->nested_ptcr & PTCR_PATB; 1430 pats = spapr->nested_ptcr & PTCR_PATS; 1431 1432 /* Check if partition table is properly aligned */ 1433 if (patb & MAKE_64BIT_MASK(0, pats + 12)) { 1434 return false; 1435 } 1436 1437 /* Calculate number of entries */ 1438 pats = 1ull << (pats + 12 - 4); 1439 if (pats <= lpid) { 1440 return false; 1441 } 1442 1443 /* Grab entry */ 1444 patb += 16 * lpid; 1445 entry->dw0 = ldq_phys(CPU(cpu)->as, patb); 1446 entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8); 1447 } 1448 1449 return true; 1450 } 1451 1452 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1453 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1454 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1455 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1456 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1457 1458 /* 1459 * Get the fd to access the kernel htab, re-opening it if necessary 1460 */ 1461 static int get_htab_fd(SpaprMachineState *spapr) 1462 { 1463 Error *local_err = NULL; 1464 1465 if (spapr->htab_fd >= 0) { 1466 return spapr->htab_fd; 1467 } 1468 1469 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1470 if (spapr->htab_fd < 0) { 1471 error_report_err(local_err); 1472 } 1473 1474 return spapr->htab_fd; 1475 } 1476 1477 void close_htab_fd(SpaprMachineState *spapr) 1478 { 1479 if (spapr->htab_fd >= 0) { 1480 close(spapr->htab_fd); 1481 } 1482 spapr->htab_fd = -1; 1483 } 1484 1485 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1486 { 1487 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1488 1489 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1490 } 1491 1492 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1493 { 1494 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1495 1496 assert(kvm_enabled()); 1497 1498 if (!spapr->htab) { 1499 return 0; 1500 } 1501 1502 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1503 } 1504 1505 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1506 hwaddr ptex, int n) 1507 { 1508 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1509 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1510 1511 if (!spapr->htab) { 1512 /* 1513 * HTAB is controlled by KVM. Fetch into temporary buffer 1514 */ 1515 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1516 kvmppc_read_hptes(hptes, ptex, n); 1517 return hptes; 1518 } 1519 1520 /* 1521 * HTAB is controlled by QEMU. Just point to the internally 1522 * accessible PTEG. 1523 */ 1524 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1525 } 1526 1527 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1528 const ppc_hash_pte64_t *hptes, 1529 hwaddr ptex, int n) 1530 { 1531 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1532 1533 if (!spapr->htab) { 1534 g_free((void *)hptes); 1535 } 1536 1537 /* Nothing to do for qemu managed HPT */ 1538 } 1539 1540 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1541 uint64_t pte0, uint64_t pte1) 1542 { 1543 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1544 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1545 1546 if (!spapr->htab) { 1547 kvmppc_write_hpte(ptex, pte0, pte1); 1548 } else { 1549 if (pte0 & HPTE64_V_VALID) { 1550 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1551 /* 1552 * When setting valid, we write PTE1 first. This ensures 1553 * proper synchronization with the reading code in 1554 * ppc_hash64_pteg_search() 1555 */ 1556 smp_wmb(); 1557 stq_p(spapr->htab + offset, pte0); 1558 } else { 1559 stq_p(spapr->htab + offset, pte0); 1560 /* 1561 * When clearing it we set PTE0 first. This ensures proper 1562 * synchronization with the reading code in 1563 * ppc_hash64_pteg_search() 1564 */ 1565 smp_wmb(); 1566 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1567 } 1568 } 1569 } 1570 1571 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1572 uint64_t pte1) 1573 { 1574 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_C; 1575 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1576 1577 if (!spapr->htab) { 1578 /* There should always be a hash table when this is called */ 1579 error_report("spapr_hpte_set_c called with no hash table !"); 1580 return; 1581 } 1582 1583 /* The HW performs a non-atomic byte update */ 1584 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1585 } 1586 1587 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1588 uint64_t pte1) 1589 { 1590 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_R; 1591 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1592 1593 if (!spapr->htab) { 1594 /* There should always be a hash table when this is called */ 1595 error_report("spapr_hpte_set_r called with no hash table !"); 1596 return; 1597 } 1598 1599 /* The HW performs a non-atomic byte update */ 1600 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1601 } 1602 1603 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1604 { 1605 int shift; 1606 1607 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1608 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1609 * that's much more than is needed for Linux guests */ 1610 shift = ctz64(pow2ceil(ramsize)) - 7; 1611 shift = MAX(shift, 18); /* Minimum architected size */ 1612 shift = MIN(shift, 46); /* Maximum architected size */ 1613 return shift; 1614 } 1615 1616 void spapr_free_hpt(SpaprMachineState *spapr) 1617 { 1618 qemu_vfree(spapr->htab); 1619 spapr->htab = NULL; 1620 spapr->htab_shift = 0; 1621 close_htab_fd(spapr); 1622 } 1623 1624 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1625 { 1626 ERRP_GUARD(); 1627 long rc; 1628 1629 /* Clean up any HPT info from a previous boot */ 1630 spapr_free_hpt(spapr); 1631 1632 rc = kvmppc_reset_htab(shift); 1633 1634 if (rc == -EOPNOTSUPP) { 1635 error_setg(errp, "HPT not supported in nested guests"); 1636 return -EOPNOTSUPP; 1637 } 1638 1639 if (rc < 0) { 1640 /* kernel-side HPT needed, but couldn't allocate one */ 1641 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1642 shift); 1643 error_append_hint(errp, "Try smaller maxmem?\n"); 1644 return -errno; 1645 } else if (rc > 0) { 1646 /* kernel-side HPT allocated */ 1647 if (rc != shift) { 1648 error_setg(errp, 1649 "Requested order %d HPT, but kernel allocated order %ld", 1650 shift, rc); 1651 error_append_hint(errp, "Try smaller maxmem?\n"); 1652 return -ENOSPC; 1653 } 1654 1655 spapr->htab_shift = shift; 1656 spapr->htab = NULL; 1657 } else { 1658 /* kernel-side HPT not needed, allocate in userspace instead */ 1659 size_t size = 1ULL << shift; 1660 int i; 1661 1662 spapr->htab = qemu_memalign(size, size); 1663 memset(spapr->htab, 0, size); 1664 spapr->htab_shift = shift; 1665 1666 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1667 DIRTY_HPTE(HPTE(spapr->htab, i)); 1668 } 1669 } 1670 /* We're setting up a hash table, so that means we're not radix */ 1671 spapr->patb_entry = 0; 1672 spapr_init_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1673 return 0; 1674 } 1675 1676 void spapr_setup_hpt(SpaprMachineState *spapr) 1677 { 1678 int hpt_shift; 1679 1680 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1681 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1682 } else { 1683 uint64_t current_ram_size; 1684 1685 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1686 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1687 } 1688 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1689 1690 if (kvm_enabled()) { 1691 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1692 1693 /* Check our RMA fits in the possible VRMA */ 1694 if (vrma_limit < spapr->rma_size) { 1695 error_report("Unable to create %" HWADDR_PRIu 1696 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1697 spapr->rma_size / MiB, vrma_limit / MiB); 1698 exit(EXIT_FAILURE); 1699 } 1700 } 1701 } 1702 1703 void spapr_check_mmu_mode(bool guest_radix) 1704 { 1705 if (guest_radix) { 1706 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 1707 error_report("Guest requested unavailable MMU mode (radix)."); 1708 exit(EXIT_FAILURE); 1709 } 1710 } else { 1711 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 1712 && !kvmppc_has_cap_mmu_hash_v3()) { 1713 error_report("Guest requested unavailable MMU mode (hash)."); 1714 exit(EXIT_FAILURE); 1715 } 1716 } 1717 } 1718 1719 static void spapr_machine_reset(MachineState *machine, ShutdownCause reason) 1720 { 1721 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1722 PowerPCCPU *first_ppc_cpu; 1723 hwaddr fdt_addr; 1724 void *fdt; 1725 int rc; 1726 1727 if (reason != SHUTDOWN_CAUSE_SNAPSHOT_LOAD) { 1728 /* 1729 * Record-replay snapshot load must not consume random, this was 1730 * already replayed from initial machine reset. 1731 */ 1732 qemu_guest_getrandom_nofail(spapr->fdt_rng_seed, 32); 1733 } 1734 1735 pef_kvm_reset(machine->cgs, &error_fatal); 1736 spapr_caps_apply(spapr); 1737 1738 first_ppc_cpu = POWERPC_CPU(first_cpu); 1739 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1740 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1741 spapr->max_compat_pvr)) { 1742 /* 1743 * If using KVM with radix mode available, VCPUs can be started 1744 * without a HPT because KVM will start them in radix mode. 1745 * Set the GR bit in PATE so that we know there is no HPT. 1746 */ 1747 spapr->patb_entry = PATE1_GR; 1748 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1749 } else { 1750 spapr_setup_hpt(spapr); 1751 } 1752 1753 qemu_devices_reset(reason); 1754 1755 spapr_ovec_cleanup(spapr->ov5_cas); 1756 spapr->ov5_cas = spapr_ovec_new(); 1757 1758 ppc_init_compat_all(spapr->max_compat_pvr, &error_fatal); 1759 1760 /* 1761 * This is fixing some of the default configuration of the XIVE 1762 * devices. To be called after the reset of the machine devices. 1763 */ 1764 spapr_irq_reset(spapr, &error_fatal); 1765 1766 /* 1767 * There is no CAS under qtest. Simulate one to please the code that 1768 * depends on spapr->ov5_cas. This is especially needed to test device 1769 * unplug, so we do that before resetting the DRCs. 1770 */ 1771 if (qtest_enabled()) { 1772 spapr_ovec_cleanup(spapr->ov5_cas); 1773 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1774 } 1775 1776 spapr_nvdimm_finish_flushes(); 1777 1778 /* DRC reset may cause a device to be unplugged. This will cause troubles 1779 * if this device is used by another device (eg, a running vhost backend 1780 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1781 * situations, we reset DRCs after all devices have been reset. 1782 */ 1783 spapr_drc_reset_all(spapr); 1784 1785 spapr_clear_pending_events(spapr); 1786 1787 /* 1788 * We place the device tree just below either the top of the RMA, 1789 * or just below 2GB, whichever is lower, so that it can be 1790 * processed with 32-bit real mode code if necessary 1791 */ 1792 fdt_addr = MIN(spapr->rma_size, FDT_MAX_ADDR) - FDT_MAX_SIZE; 1793 1794 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1795 if (spapr->vof) { 1796 spapr_vof_reset(spapr, fdt, &error_fatal); 1797 /* 1798 * Do not pack the FDT as the client may change properties. 1799 * VOF client does not expect the FDT so we do not load it to the VM. 1800 */ 1801 } else { 1802 rc = fdt_pack(fdt); 1803 /* Should only fail if we've built a corrupted tree */ 1804 assert(rc == 0); 1805 1806 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 1807 0, fdt_addr, 0); 1808 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1809 } 1810 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1811 1812 g_free(spapr->fdt_blob); 1813 spapr->fdt_size = fdt_totalsize(fdt); 1814 spapr->fdt_initial_size = spapr->fdt_size; 1815 spapr->fdt_blob = fdt; 1816 1817 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ 1818 machine->fdt = fdt; 1819 1820 /* Set up the entry state */ 1821 first_ppc_cpu->env.gpr[5] = 0; 1822 1823 spapr->fwnmi_system_reset_addr = -1; 1824 spapr->fwnmi_machine_check_addr = -1; 1825 spapr->fwnmi_machine_check_interlock = -1; 1826 1827 /* Signal all vCPUs waiting on this condition */ 1828 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1829 1830 migrate_del_blocker(&spapr->fwnmi_migration_blocker); 1831 } 1832 1833 static void spapr_create_nvram(SpaprMachineState *spapr) 1834 { 1835 DeviceState *dev = qdev_new("spapr-nvram"); 1836 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1837 1838 if (dinfo) { 1839 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1840 &error_fatal); 1841 } 1842 1843 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1844 1845 spapr->nvram = (struct SpaprNvram *)dev; 1846 } 1847 1848 static void spapr_rtc_create(SpaprMachineState *spapr) 1849 { 1850 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1851 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1852 &error_fatal, NULL); 1853 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1854 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1855 "date"); 1856 } 1857 1858 /* Returns whether we want to use VGA or not */ 1859 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1860 { 1861 vga_interface_created = true; 1862 switch (vga_interface_type) { 1863 case VGA_NONE: 1864 return false; 1865 case VGA_DEVICE: 1866 return true; 1867 case VGA_STD: 1868 case VGA_VIRTIO: 1869 case VGA_CIRRUS: 1870 return pci_vga_init(pci_bus) != NULL; 1871 default: 1872 error_setg(errp, 1873 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1874 return false; 1875 } 1876 } 1877 1878 static int spapr_pre_load(void *opaque) 1879 { 1880 int rc; 1881 1882 rc = spapr_caps_pre_load(opaque); 1883 if (rc) { 1884 return rc; 1885 } 1886 1887 return 0; 1888 } 1889 1890 static int spapr_post_load(void *opaque, int version_id) 1891 { 1892 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1893 int err = 0; 1894 1895 err = spapr_caps_post_migration(spapr); 1896 if (err) { 1897 return err; 1898 } 1899 1900 /* 1901 * In earlier versions, there was no separate qdev for the PAPR 1902 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1903 * So when migrating from those versions, poke the incoming offset 1904 * value into the RTC device 1905 */ 1906 if (version_id < 3) { 1907 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1908 if (err) { 1909 return err; 1910 } 1911 } 1912 1913 if (kvm_enabled() && spapr->patb_entry) { 1914 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1915 bool radix = !!(spapr->patb_entry & PATE1_GR); 1916 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1917 1918 /* 1919 * Update LPCR:HR and UPRT as they may not be set properly in 1920 * the stream 1921 */ 1922 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1923 LPCR_HR | LPCR_UPRT); 1924 1925 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1926 if (err) { 1927 error_report("Process table config unsupported by the host"); 1928 return -EINVAL; 1929 } 1930 } 1931 1932 err = spapr_irq_post_load(spapr, version_id); 1933 if (err) { 1934 return err; 1935 } 1936 1937 return err; 1938 } 1939 1940 static int spapr_pre_save(void *opaque) 1941 { 1942 int rc; 1943 1944 rc = spapr_caps_pre_save(opaque); 1945 if (rc) { 1946 return rc; 1947 } 1948 1949 return 0; 1950 } 1951 1952 static bool version_before_3(void *opaque, int version_id) 1953 { 1954 return version_id < 3; 1955 } 1956 1957 static bool spapr_pending_events_needed(void *opaque) 1958 { 1959 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1960 return !QTAILQ_EMPTY(&spapr->pending_events); 1961 } 1962 1963 static const VMStateDescription vmstate_spapr_event_entry = { 1964 .name = "spapr_event_log_entry", 1965 .version_id = 1, 1966 .minimum_version_id = 1, 1967 .fields = (const VMStateField[]) { 1968 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1969 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1970 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1971 NULL, extended_length), 1972 VMSTATE_END_OF_LIST() 1973 }, 1974 }; 1975 1976 static const VMStateDescription vmstate_spapr_pending_events = { 1977 .name = "spapr_pending_events", 1978 .version_id = 1, 1979 .minimum_version_id = 1, 1980 .needed = spapr_pending_events_needed, 1981 .fields = (const VMStateField[]) { 1982 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1983 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1984 VMSTATE_END_OF_LIST() 1985 }, 1986 }; 1987 1988 static bool spapr_ov5_cas_needed(void *opaque) 1989 { 1990 SpaprMachineState *spapr = opaque; 1991 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1992 bool cas_needed; 1993 1994 /* Prior to the introduction of SpaprOptionVector, we had two option 1995 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1996 * Both of these options encode machine topology into the device-tree 1997 * in such a way that the now-booted OS should still be able to interact 1998 * appropriately with QEMU regardless of what options were actually 1999 * negotiatied on the source side. 2000 * 2001 * As such, we can avoid migrating the CAS-negotiated options if these 2002 * are the only options available on the current machine/platform. 2003 * Since these are the only options available for pseries-2.7 and 2004 * earlier, this allows us to maintain old->new/new->old migration 2005 * compatibility. 2006 * 2007 * For QEMU 2.8+, there are additional CAS-negotiatable options available 2008 * via default pseries-2.8 machines and explicit command-line parameters. 2009 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 2010 * of the actual CAS-negotiated values to continue working properly. For 2011 * example, availability of memory unplug depends on knowing whether 2012 * OV5_HP_EVT was negotiated via CAS. 2013 * 2014 * Thus, for any cases where the set of available CAS-negotiatable 2015 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 2016 * include the CAS-negotiated options in the migration stream, unless 2017 * if they affect boot time behaviour only. 2018 */ 2019 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 2020 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 2021 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 2022 2023 /* We need extra information if we have any bits outside the mask 2024 * defined above */ 2025 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 2026 2027 spapr_ovec_cleanup(ov5_mask); 2028 2029 return cas_needed; 2030 } 2031 2032 static const VMStateDescription vmstate_spapr_ov5_cas = { 2033 .name = "spapr_option_vector_ov5_cas", 2034 .version_id = 1, 2035 .minimum_version_id = 1, 2036 .needed = spapr_ov5_cas_needed, 2037 .fields = (const VMStateField[]) { 2038 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 2039 vmstate_spapr_ovec, SpaprOptionVector), 2040 VMSTATE_END_OF_LIST() 2041 }, 2042 }; 2043 2044 static bool spapr_patb_entry_needed(void *opaque) 2045 { 2046 SpaprMachineState *spapr = opaque; 2047 2048 return !!spapr->patb_entry; 2049 } 2050 2051 static const VMStateDescription vmstate_spapr_patb_entry = { 2052 .name = "spapr_patb_entry", 2053 .version_id = 1, 2054 .minimum_version_id = 1, 2055 .needed = spapr_patb_entry_needed, 2056 .fields = (const VMStateField[]) { 2057 VMSTATE_UINT64(patb_entry, SpaprMachineState), 2058 VMSTATE_END_OF_LIST() 2059 }, 2060 }; 2061 2062 static bool spapr_irq_map_needed(void *opaque) 2063 { 2064 SpaprMachineState *spapr = opaque; 2065 2066 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 2067 } 2068 2069 static const VMStateDescription vmstate_spapr_irq_map = { 2070 .name = "spapr_irq_map", 2071 .version_id = 1, 2072 .minimum_version_id = 1, 2073 .needed = spapr_irq_map_needed, 2074 .fields = (const VMStateField[]) { 2075 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 2076 VMSTATE_END_OF_LIST() 2077 }, 2078 }; 2079 2080 static bool spapr_dtb_needed(void *opaque) 2081 { 2082 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 2083 2084 return smc->update_dt_enabled; 2085 } 2086 2087 static int spapr_dtb_pre_load(void *opaque) 2088 { 2089 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2090 2091 g_free(spapr->fdt_blob); 2092 spapr->fdt_blob = NULL; 2093 spapr->fdt_size = 0; 2094 2095 return 0; 2096 } 2097 2098 static const VMStateDescription vmstate_spapr_dtb = { 2099 .name = "spapr_dtb", 2100 .version_id = 1, 2101 .minimum_version_id = 1, 2102 .needed = spapr_dtb_needed, 2103 .pre_load = spapr_dtb_pre_load, 2104 .fields = (const VMStateField[]) { 2105 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 2106 VMSTATE_UINT32(fdt_size, SpaprMachineState), 2107 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 2108 fdt_size), 2109 VMSTATE_END_OF_LIST() 2110 }, 2111 }; 2112 2113 static bool spapr_fwnmi_needed(void *opaque) 2114 { 2115 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2116 2117 return spapr->fwnmi_machine_check_addr != -1; 2118 } 2119 2120 static int spapr_fwnmi_pre_save(void *opaque) 2121 { 2122 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2123 2124 /* 2125 * Check if machine check handling is in progress and print a 2126 * warning message. 2127 */ 2128 if (spapr->fwnmi_machine_check_interlock != -1) { 2129 warn_report("A machine check is being handled during migration. The" 2130 "handler may run and log hardware error on the destination"); 2131 } 2132 2133 return 0; 2134 } 2135 2136 static const VMStateDescription vmstate_spapr_fwnmi = { 2137 .name = "spapr_fwnmi", 2138 .version_id = 1, 2139 .minimum_version_id = 1, 2140 .needed = spapr_fwnmi_needed, 2141 .pre_save = spapr_fwnmi_pre_save, 2142 .fields = (const VMStateField[]) { 2143 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 2144 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 2145 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 2146 VMSTATE_END_OF_LIST() 2147 }, 2148 }; 2149 2150 static const VMStateDescription vmstate_spapr = { 2151 .name = "spapr", 2152 .version_id = 3, 2153 .minimum_version_id = 1, 2154 .pre_load = spapr_pre_load, 2155 .post_load = spapr_post_load, 2156 .pre_save = spapr_pre_save, 2157 .fields = (const VMStateField[]) { 2158 /* used to be @next_irq */ 2159 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2160 2161 /* RTC offset */ 2162 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2163 2164 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2165 VMSTATE_END_OF_LIST() 2166 }, 2167 .subsections = (const VMStateDescription * const []) { 2168 &vmstate_spapr_ov5_cas, 2169 &vmstate_spapr_patb_entry, 2170 &vmstate_spapr_pending_events, 2171 &vmstate_spapr_cap_htm, 2172 &vmstate_spapr_cap_vsx, 2173 &vmstate_spapr_cap_dfp, 2174 &vmstate_spapr_cap_cfpc, 2175 &vmstate_spapr_cap_sbbc, 2176 &vmstate_spapr_cap_ibs, 2177 &vmstate_spapr_cap_hpt_maxpagesize, 2178 &vmstate_spapr_irq_map, 2179 &vmstate_spapr_cap_nested_kvm_hv, 2180 &vmstate_spapr_dtb, 2181 &vmstate_spapr_cap_large_decr, 2182 &vmstate_spapr_cap_ccf_assist, 2183 &vmstate_spapr_cap_fwnmi, 2184 &vmstate_spapr_fwnmi, 2185 &vmstate_spapr_cap_rpt_invalidate, 2186 NULL 2187 } 2188 }; 2189 2190 static int htab_save_setup(QEMUFile *f, void *opaque) 2191 { 2192 SpaprMachineState *spapr = opaque; 2193 2194 /* "Iteration" header */ 2195 if (!spapr->htab_shift) { 2196 qemu_put_be32(f, -1); 2197 } else { 2198 qemu_put_be32(f, spapr->htab_shift); 2199 } 2200 2201 if (spapr->htab) { 2202 spapr->htab_save_index = 0; 2203 spapr->htab_first_pass = true; 2204 } else { 2205 if (spapr->htab_shift) { 2206 assert(kvm_enabled()); 2207 } 2208 } 2209 2210 2211 return 0; 2212 } 2213 2214 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2215 int chunkstart, int n_valid, int n_invalid) 2216 { 2217 qemu_put_be32(f, chunkstart); 2218 qemu_put_be16(f, n_valid); 2219 qemu_put_be16(f, n_invalid); 2220 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2221 HASH_PTE_SIZE_64 * n_valid); 2222 } 2223 2224 static void htab_save_end_marker(QEMUFile *f) 2225 { 2226 qemu_put_be32(f, 0); 2227 qemu_put_be16(f, 0); 2228 qemu_put_be16(f, 0); 2229 } 2230 2231 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2232 int64_t max_ns) 2233 { 2234 bool has_timeout = max_ns != -1; 2235 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2236 int index = spapr->htab_save_index; 2237 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2238 2239 assert(spapr->htab_first_pass); 2240 2241 do { 2242 int chunkstart; 2243 2244 /* Consume invalid HPTEs */ 2245 while ((index < htabslots) 2246 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2247 CLEAN_HPTE(HPTE(spapr->htab, index)); 2248 index++; 2249 } 2250 2251 /* Consume valid HPTEs */ 2252 chunkstart = index; 2253 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2254 && HPTE_VALID(HPTE(spapr->htab, index))) { 2255 CLEAN_HPTE(HPTE(spapr->htab, index)); 2256 index++; 2257 } 2258 2259 if (index > chunkstart) { 2260 int n_valid = index - chunkstart; 2261 2262 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2263 2264 if (has_timeout && 2265 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2266 break; 2267 } 2268 } 2269 } while ((index < htabslots) && !migration_rate_exceeded(f)); 2270 2271 if (index >= htabslots) { 2272 assert(index == htabslots); 2273 index = 0; 2274 spapr->htab_first_pass = false; 2275 } 2276 spapr->htab_save_index = index; 2277 } 2278 2279 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2280 int64_t max_ns) 2281 { 2282 bool final = max_ns < 0; 2283 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2284 int examined = 0, sent = 0; 2285 int index = spapr->htab_save_index; 2286 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2287 2288 assert(!spapr->htab_first_pass); 2289 2290 do { 2291 int chunkstart, invalidstart; 2292 2293 /* Consume non-dirty HPTEs */ 2294 while ((index < htabslots) 2295 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2296 index++; 2297 examined++; 2298 } 2299 2300 chunkstart = index; 2301 /* Consume valid dirty HPTEs */ 2302 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2303 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2304 && HPTE_VALID(HPTE(spapr->htab, index))) { 2305 CLEAN_HPTE(HPTE(spapr->htab, index)); 2306 index++; 2307 examined++; 2308 } 2309 2310 invalidstart = index; 2311 /* Consume invalid dirty HPTEs */ 2312 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2313 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2314 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2315 CLEAN_HPTE(HPTE(spapr->htab, index)); 2316 index++; 2317 examined++; 2318 } 2319 2320 if (index > chunkstart) { 2321 int n_valid = invalidstart - chunkstart; 2322 int n_invalid = index - invalidstart; 2323 2324 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2325 sent += index - chunkstart; 2326 2327 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2328 break; 2329 } 2330 } 2331 2332 if (examined >= htabslots) { 2333 break; 2334 } 2335 2336 if (index >= htabslots) { 2337 assert(index == htabslots); 2338 index = 0; 2339 } 2340 } while ((examined < htabslots) && (!migration_rate_exceeded(f) || final)); 2341 2342 if (index >= htabslots) { 2343 assert(index == htabslots); 2344 index = 0; 2345 } 2346 2347 spapr->htab_save_index = index; 2348 2349 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2350 } 2351 2352 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2353 #define MAX_KVM_BUF_SIZE 2048 2354 2355 static int htab_save_iterate(QEMUFile *f, void *opaque) 2356 { 2357 SpaprMachineState *spapr = opaque; 2358 int fd; 2359 int rc = 0; 2360 2361 /* Iteration header */ 2362 if (!spapr->htab_shift) { 2363 qemu_put_be32(f, -1); 2364 return 1; 2365 } else { 2366 qemu_put_be32(f, 0); 2367 } 2368 2369 if (!spapr->htab) { 2370 assert(kvm_enabled()); 2371 2372 fd = get_htab_fd(spapr); 2373 if (fd < 0) { 2374 return fd; 2375 } 2376 2377 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2378 if (rc < 0) { 2379 return rc; 2380 } 2381 } else if (spapr->htab_first_pass) { 2382 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2383 } else { 2384 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2385 } 2386 2387 htab_save_end_marker(f); 2388 2389 return rc; 2390 } 2391 2392 static int htab_save_complete(QEMUFile *f, void *opaque) 2393 { 2394 SpaprMachineState *spapr = opaque; 2395 int fd; 2396 2397 /* Iteration header */ 2398 if (!spapr->htab_shift) { 2399 qemu_put_be32(f, -1); 2400 return 0; 2401 } else { 2402 qemu_put_be32(f, 0); 2403 } 2404 2405 if (!spapr->htab) { 2406 int rc; 2407 2408 assert(kvm_enabled()); 2409 2410 fd = get_htab_fd(spapr); 2411 if (fd < 0) { 2412 return fd; 2413 } 2414 2415 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2416 if (rc < 0) { 2417 return rc; 2418 } 2419 } else { 2420 if (spapr->htab_first_pass) { 2421 htab_save_first_pass(f, spapr, -1); 2422 } 2423 htab_save_later_pass(f, spapr, -1); 2424 } 2425 2426 /* End marker */ 2427 htab_save_end_marker(f); 2428 2429 return 0; 2430 } 2431 2432 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2433 { 2434 SpaprMachineState *spapr = opaque; 2435 uint32_t section_hdr; 2436 int fd = -1; 2437 Error *local_err = NULL; 2438 2439 if (version_id < 1 || version_id > 1) { 2440 error_report("htab_load() bad version"); 2441 return -EINVAL; 2442 } 2443 2444 section_hdr = qemu_get_be32(f); 2445 2446 if (section_hdr == -1) { 2447 spapr_free_hpt(spapr); 2448 return 0; 2449 } 2450 2451 if (section_hdr) { 2452 int ret; 2453 2454 /* First section gives the htab size */ 2455 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2456 if (ret < 0) { 2457 error_report_err(local_err); 2458 return ret; 2459 } 2460 return 0; 2461 } 2462 2463 if (!spapr->htab) { 2464 assert(kvm_enabled()); 2465 2466 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2467 if (fd < 0) { 2468 error_report_err(local_err); 2469 return fd; 2470 } 2471 } 2472 2473 while (true) { 2474 uint32_t index; 2475 uint16_t n_valid, n_invalid; 2476 2477 index = qemu_get_be32(f); 2478 n_valid = qemu_get_be16(f); 2479 n_invalid = qemu_get_be16(f); 2480 2481 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2482 /* End of Stream */ 2483 break; 2484 } 2485 2486 if ((index + n_valid + n_invalid) > 2487 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2488 /* Bad index in stream */ 2489 error_report( 2490 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2491 index, n_valid, n_invalid, spapr->htab_shift); 2492 return -EINVAL; 2493 } 2494 2495 if (spapr->htab) { 2496 if (n_valid) { 2497 qemu_get_buffer(f, HPTE(spapr->htab, index), 2498 HASH_PTE_SIZE_64 * n_valid); 2499 } 2500 if (n_invalid) { 2501 memset(HPTE(spapr->htab, index + n_valid), 0, 2502 HASH_PTE_SIZE_64 * n_invalid); 2503 } 2504 } else { 2505 int rc; 2506 2507 assert(fd >= 0); 2508 2509 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2510 &local_err); 2511 if (rc < 0) { 2512 error_report_err(local_err); 2513 return rc; 2514 } 2515 } 2516 } 2517 2518 if (!spapr->htab) { 2519 assert(fd >= 0); 2520 close(fd); 2521 } 2522 2523 return 0; 2524 } 2525 2526 static void htab_save_cleanup(void *opaque) 2527 { 2528 SpaprMachineState *spapr = opaque; 2529 2530 close_htab_fd(spapr); 2531 } 2532 2533 static SaveVMHandlers savevm_htab_handlers = { 2534 .save_setup = htab_save_setup, 2535 .save_live_iterate = htab_save_iterate, 2536 .save_live_complete_precopy = htab_save_complete, 2537 .save_cleanup = htab_save_cleanup, 2538 .load_state = htab_load, 2539 }; 2540 2541 static void spapr_boot_set(void *opaque, const char *boot_device, 2542 Error **errp) 2543 { 2544 SpaprMachineState *spapr = SPAPR_MACHINE(opaque); 2545 2546 g_free(spapr->boot_device); 2547 spapr->boot_device = g_strdup(boot_device); 2548 } 2549 2550 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2551 { 2552 MachineState *machine = MACHINE(spapr); 2553 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2554 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2555 int i; 2556 2557 g_assert(!nr_lmbs || machine->device_memory); 2558 for (i = 0; i < nr_lmbs; i++) { 2559 uint64_t addr; 2560 2561 addr = i * lmb_size + machine->device_memory->base; 2562 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2563 addr / lmb_size); 2564 } 2565 } 2566 2567 /* 2568 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2569 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2570 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2571 */ 2572 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2573 { 2574 int i; 2575 2576 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2577 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2578 " is not aligned to %" PRIu64 " MiB", 2579 machine->ram_size, 2580 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2581 return; 2582 } 2583 2584 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2585 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2586 " is not aligned to %" PRIu64 " MiB", 2587 machine->ram_size, 2588 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2589 return; 2590 } 2591 2592 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2593 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2594 error_setg(errp, 2595 "Node %d memory size 0x%" PRIx64 2596 " is not aligned to %" PRIu64 " MiB", 2597 i, machine->numa_state->nodes[i].node_mem, 2598 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2599 return; 2600 } 2601 } 2602 } 2603 2604 /* find cpu slot in machine->possible_cpus by core_id */ 2605 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2606 { 2607 int index = id / ms->smp.threads; 2608 2609 if (index >= ms->possible_cpus->len) { 2610 return NULL; 2611 } 2612 if (idx) { 2613 *idx = index; 2614 } 2615 return &ms->possible_cpus->cpus[index]; 2616 } 2617 2618 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2619 { 2620 MachineState *ms = MACHINE(spapr); 2621 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2622 Error *local_err = NULL; 2623 bool vsmt_user = !!spapr->vsmt; 2624 int kvm_smt = kvmppc_smt_threads(); 2625 int ret; 2626 unsigned int smp_threads = ms->smp.threads; 2627 2628 if (tcg_enabled()) { 2629 if (smp_threads > 1 && 2630 !ppc_type_check_compat(ms->cpu_type, CPU_POWERPC_LOGICAL_2_07, 0, 2631 spapr->max_compat_pvr)) { 2632 error_setg(errp, "TCG only supports SMT on POWER8 or newer CPUs"); 2633 return; 2634 } 2635 2636 if (smp_threads > 8) { 2637 error_setg(errp, "TCG cannot support more than 8 threads/core " 2638 "on a pseries machine"); 2639 return; 2640 } 2641 } 2642 if (!is_power_of_2(smp_threads)) { 2643 error_setg(errp, "Cannot support %d threads/core on a pseries " 2644 "machine because it must be a power of 2", smp_threads); 2645 return; 2646 } 2647 2648 /* Determine the VSMT mode to use: */ 2649 if (vsmt_user) { 2650 if (spapr->vsmt < smp_threads) { 2651 error_setg(errp, "Cannot support VSMT mode %d" 2652 " because it must be >= threads/core (%d)", 2653 spapr->vsmt, smp_threads); 2654 return; 2655 } 2656 /* In this case, spapr->vsmt has been set by the command line */ 2657 } else if (!smc->smp_threads_vsmt) { 2658 /* 2659 * Default VSMT value is tricky, because we need it to be as 2660 * consistent as possible (for migration), but this requires 2661 * changing it for at least some existing cases. We pick 8 as 2662 * the value that we'd get with KVM on POWER8, the 2663 * overwhelmingly common case in production systems. 2664 */ 2665 spapr->vsmt = MAX(8, smp_threads); 2666 } else { 2667 spapr->vsmt = smp_threads; 2668 } 2669 2670 /* KVM: If necessary, set the SMT mode: */ 2671 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2672 ret = kvmppc_set_smt_threads(spapr->vsmt); 2673 if (ret) { 2674 /* Looks like KVM isn't able to change VSMT mode */ 2675 error_setg(&local_err, 2676 "Failed to set KVM's VSMT mode to %d (errno %d)", 2677 spapr->vsmt, ret); 2678 /* We can live with that if the default one is big enough 2679 * for the number of threads, and a submultiple of the one 2680 * we want. In this case we'll waste some vcpu ids, but 2681 * behaviour will be correct */ 2682 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2683 warn_report_err(local_err); 2684 } else { 2685 if (!vsmt_user) { 2686 error_append_hint(&local_err, 2687 "On PPC, a VM with %d threads/core" 2688 " on a host with %d threads/core" 2689 " requires the use of VSMT mode %d.\n", 2690 smp_threads, kvm_smt, spapr->vsmt); 2691 } 2692 kvmppc_error_append_smt_possible_hint(&local_err); 2693 error_propagate(errp, local_err); 2694 } 2695 } 2696 } 2697 /* else TCG: nothing to do currently */ 2698 } 2699 2700 static void spapr_init_cpus(SpaprMachineState *spapr) 2701 { 2702 MachineState *machine = MACHINE(spapr); 2703 MachineClass *mc = MACHINE_GET_CLASS(machine); 2704 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2705 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2706 const CPUArchIdList *possible_cpus; 2707 unsigned int smp_cpus = machine->smp.cpus; 2708 unsigned int smp_threads = machine->smp.threads; 2709 unsigned int max_cpus = machine->smp.max_cpus; 2710 int boot_cores_nr = smp_cpus / smp_threads; 2711 int i; 2712 2713 possible_cpus = mc->possible_cpu_arch_ids(machine); 2714 if (mc->has_hotpluggable_cpus) { 2715 if (smp_cpus % smp_threads) { 2716 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2717 smp_cpus, smp_threads); 2718 exit(1); 2719 } 2720 if (max_cpus % smp_threads) { 2721 error_report("max_cpus (%u) must be multiple of threads (%u)", 2722 max_cpus, smp_threads); 2723 exit(1); 2724 } 2725 } else { 2726 if (max_cpus != smp_cpus) { 2727 error_report("This machine version does not support CPU hotplug"); 2728 exit(1); 2729 } 2730 boot_cores_nr = possible_cpus->len; 2731 } 2732 2733 if (smc->pre_2_10_has_unused_icps) { 2734 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2735 /* Dummy entries get deregistered when real ICPState objects 2736 * are registered during CPU core hotplug. 2737 */ 2738 pre_2_10_vmstate_register_dummy_icp(i); 2739 } 2740 } 2741 2742 for (i = 0; i < possible_cpus->len; i++) { 2743 int core_id = i * smp_threads; 2744 2745 if (mc->has_hotpluggable_cpus) { 2746 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2747 spapr_vcpu_id(spapr, core_id)); 2748 } 2749 2750 if (i < boot_cores_nr) { 2751 Object *core = object_new(type); 2752 int nr_threads = smp_threads; 2753 2754 /* Handle the partially filled core for older machine types */ 2755 if ((i + 1) * smp_threads >= smp_cpus) { 2756 nr_threads = smp_cpus - i * smp_threads; 2757 } 2758 2759 object_property_set_int(core, "nr-threads", nr_threads, 2760 &error_fatal); 2761 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2762 &error_fatal); 2763 qdev_realize(DEVICE(core), NULL, &error_fatal); 2764 2765 object_unref(core); 2766 } 2767 } 2768 } 2769 2770 static PCIHostState *spapr_create_default_phb(void) 2771 { 2772 DeviceState *dev; 2773 2774 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2775 qdev_prop_set_uint32(dev, "index", 0); 2776 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2777 2778 return PCI_HOST_BRIDGE(dev); 2779 } 2780 2781 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2782 { 2783 MachineState *machine = MACHINE(spapr); 2784 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2785 hwaddr rma_size = machine->ram_size; 2786 hwaddr node0_size = spapr_node0_size(machine); 2787 2788 /* RMA has to fit in the first NUMA node */ 2789 rma_size = MIN(rma_size, node0_size); 2790 2791 /* 2792 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2793 * never exceed that 2794 */ 2795 rma_size = MIN(rma_size, 1 * TiB); 2796 2797 /* 2798 * Clamp the RMA size based on machine type. This is for 2799 * migration compatibility with older qemu versions, which limited 2800 * the RMA size for complicated and mostly bad reasons. 2801 */ 2802 if (smc->rma_limit) { 2803 rma_size = MIN(rma_size, smc->rma_limit); 2804 } 2805 2806 if (rma_size < MIN_RMA_SLOF) { 2807 error_setg(errp, 2808 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2809 "ldMiB guest RMA (Real Mode Area memory)", 2810 MIN_RMA_SLOF / MiB); 2811 return 0; 2812 } 2813 2814 return rma_size; 2815 } 2816 2817 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2818 { 2819 MachineState *machine = MACHINE(spapr); 2820 int i; 2821 2822 for (i = 0; i < machine->ram_slots; i++) { 2823 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2824 } 2825 } 2826 2827 /* pSeries LPAR / sPAPR hardware init */ 2828 static void spapr_machine_init(MachineState *machine) 2829 { 2830 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2831 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2832 MachineClass *mc = MACHINE_GET_CLASS(machine); 2833 const char *bios_default = spapr->vof ? FW_FILE_NAME_VOF : FW_FILE_NAME; 2834 const char *bios_name = machine->firmware ?: bios_default; 2835 g_autofree char *filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2836 const char *kernel_filename = machine->kernel_filename; 2837 const char *initrd_filename = machine->initrd_filename; 2838 PCIHostState *phb; 2839 bool has_vga; 2840 int i; 2841 MemoryRegion *sysmem = get_system_memory(); 2842 long load_limit, fw_size; 2843 Error *resize_hpt_err = NULL; 2844 NICInfo *nd; 2845 2846 if (!filename) { 2847 error_report("Could not find LPAR firmware '%s'", bios_name); 2848 exit(1); 2849 } 2850 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2851 if (fw_size <= 0) { 2852 error_report("Could not load LPAR firmware '%s'", filename); 2853 exit(1); 2854 } 2855 2856 /* 2857 * if Secure VM (PEF) support is configured, then initialize it 2858 */ 2859 pef_kvm_init(machine->cgs, &error_fatal); 2860 2861 msi_nonbroken = true; 2862 2863 QLIST_INIT(&spapr->phbs); 2864 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2865 2866 /* Determine capabilities to run with */ 2867 spapr_caps_init(spapr); 2868 2869 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2870 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2871 /* 2872 * If the user explicitly requested a mode we should either 2873 * supply it, or fail completely (which we do below). But if 2874 * it's not set explicitly, we reset our mode to something 2875 * that works 2876 */ 2877 if (resize_hpt_err) { 2878 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2879 error_free(resize_hpt_err); 2880 resize_hpt_err = NULL; 2881 } else { 2882 spapr->resize_hpt = smc->resize_hpt_default; 2883 } 2884 } 2885 2886 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2887 2888 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2889 /* 2890 * User requested HPT resize, but this host can't supply it. Bail out 2891 */ 2892 error_report_err(resize_hpt_err); 2893 exit(1); 2894 } 2895 error_free(resize_hpt_err); 2896 2897 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2898 2899 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2900 load_limit = MIN(spapr->rma_size, FDT_MAX_ADDR) - FW_OVERHEAD; 2901 2902 /* 2903 * VSMT must be set in order to be able to compute VCPU ids, ie to 2904 * call spapr_max_server_number() or spapr_vcpu_id(). 2905 */ 2906 spapr_set_vsmt_mode(spapr, &error_fatal); 2907 2908 /* Set up Interrupt Controller before we create the VCPUs */ 2909 spapr_irq_init(spapr, &error_fatal); 2910 2911 /* Set up containers for ibm,client-architecture-support negotiated options 2912 */ 2913 spapr->ov5 = spapr_ovec_new(); 2914 spapr->ov5_cas = spapr_ovec_new(); 2915 2916 if (smc->dr_lmb_enabled) { 2917 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2918 spapr_validate_node_memory(machine, &error_fatal); 2919 } 2920 2921 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2922 2923 /* Do not advertise FORM2 NUMA support for pseries-6.1 and older */ 2924 if (!smc->pre_6_2_numa_affinity) { 2925 spapr_ovec_set(spapr->ov5, OV5_FORM2_AFFINITY); 2926 } 2927 2928 /* advertise support for dedicated HP event source to guests */ 2929 if (spapr->use_hotplug_event_source) { 2930 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2931 } 2932 2933 /* advertise support for HPT resizing */ 2934 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2935 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2936 } 2937 2938 /* advertise support for ibm,dyamic-memory-v2 */ 2939 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2940 2941 /* advertise XIVE on POWER9 machines */ 2942 if (spapr->irq->xive) { 2943 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2944 } 2945 2946 /* init CPUs */ 2947 spapr_init_cpus(spapr); 2948 2949 /* Init numa_assoc_array */ 2950 spapr_numa_associativity_init(spapr, machine); 2951 2952 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2953 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2954 spapr->max_compat_pvr)) { 2955 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2956 /* KVM and TCG always allow GTSE with radix... */ 2957 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2958 } 2959 /* ... but not with hash (currently). */ 2960 2961 if (kvm_enabled()) { 2962 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2963 kvmppc_enable_logical_ci_hcalls(); 2964 kvmppc_enable_set_mode_hcall(); 2965 2966 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2967 kvmppc_enable_clear_ref_mod_hcalls(); 2968 2969 /* Enable H_PAGE_INIT */ 2970 kvmppc_enable_h_page_init(); 2971 } 2972 2973 /* map RAM */ 2974 memory_region_add_subregion(sysmem, 0, machine->ram); 2975 2976 /* initialize hotplug memory address space */ 2977 if (machine->ram_size < machine->maxram_size) { 2978 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2979 hwaddr device_mem_base; 2980 2981 /* 2982 * Limit the number of hotpluggable memory slots to half the number 2983 * slots that KVM supports, leaving the other half for PCI and other 2984 * devices. However ensure that number of slots doesn't drop below 32. 2985 */ 2986 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2987 SPAPR_MAX_RAM_SLOTS; 2988 2989 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2990 max_memslots = SPAPR_MAX_RAM_SLOTS; 2991 } 2992 if (machine->ram_slots > max_memslots) { 2993 error_report("Specified number of memory slots %" 2994 PRIu64" exceeds max supported %d", 2995 machine->ram_slots, max_memslots); 2996 exit(1); 2997 } 2998 2999 device_mem_base = ROUND_UP(machine->ram_size, SPAPR_DEVICE_MEM_ALIGN); 3000 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 3001 } 3002 3003 if (smc->dr_lmb_enabled) { 3004 spapr_create_lmb_dr_connectors(spapr); 3005 } 3006 3007 if (mc->nvdimm_supported) { 3008 spapr_create_nvdimm_dr_connectors(spapr); 3009 } 3010 3011 /* Set up RTAS event infrastructure */ 3012 spapr_events_init(spapr); 3013 3014 /* Set up the RTC RTAS interfaces */ 3015 spapr_rtc_create(spapr); 3016 3017 /* Set up VIO bus */ 3018 spapr->vio_bus = spapr_vio_bus_init(); 3019 3020 for (i = 0; serial_hd(i); i++) { 3021 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 3022 } 3023 3024 /* We always have at least the nvram device on VIO */ 3025 spapr_create_nvram(spapr); 3026 3027 /* 3028 * Setup hotplug / dynamic-reconfiguration connectors. top-level 3029 * connectors (described in root DT node's "ibm,drc-types" property) 3030 * are pre-initialized here. additional child connectors (such as 3031 * connectors for a PHBs PCI slots) are added as needed during their 3032 * parent's realization. 3033 */ 3034 if (smc->dr_phb_enabled) { 3035 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 3036 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 3037 } 3038 } 3039 3040 /* Set up PCI */ 3041 spapr_pci_rtas_init(); 3042 3043 phb = spapr_create_default_phb(); 3044 3045 while ((nd = qemu_find_nic_info("spapr-vlan", true, "ibmveth"))) { 3046 spapr_vlan_create(spapr->vio_bus, nd); 3047 } 3048 3049 pci_init_nic_devices(phb->bus, NULL); 3050 3051 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 3052 spapr_vscsi_create(spapr->vio_bus); 3053 } 3054 3055 /* Graphics */ 3056 has_vga = spapr_vga_init(phb->bus, &error_fatal); 3057 if (has_vga) { 3058 spapr->want_stdout_path = !machine->enable_graphics; 3059 machine->usb |= defaults_enabled() && !machine->usb_disabled; 3060 } else { 3061 spapr->want_stdout_path = true; 3062 } 3063 3064 if (machine->usb) { 3065 if (smc->use_ohci_by_default) { 3066 pci_create_simple(phb->bus, -1, "pci-ohci"); 3067 } else { 3068 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 3069 } 3070 3071 if (has_vga) { 3072 USBBus *usb_bus; 3073 3074 usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS, 3075 &error_abort)); 3076 usb_create_simple(usb_bus, "usb-kbd"); 3077 usb_create_simple(usb_bus, "usb-mouse"); 3078 } 3079 } 3080 3081 if (kernel_filename) { 3082 uint64_t loaded_addr = 0; 3083 3084 spapr->kernel_size = load_elf(kernel_filename, NULL, 3085 translate_kernel_address, spapr, 3086 NULL, &loaded_addr, NULL, NULL, 1, 3087 PPC_ELF_MACHINE, 0, 0); 3088 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 3089 spapr->kernel_size = load_elf(kernel_filename, NULL, 3090 translate_kernel_address, spapr, 3091 NULL, &loaded_addr, NULL, NULL, 0, 3092 PPC_ELF_MACHINE, 0, 0); 3093 spapr->kernel_le = spapr->kernel_size > 0; 3094 } 3095 if (spapr->kernel_size < 0) { 3096 error_report("error loading %s: %s", kernel_filename, 3097 load_elf_strerror(spapr->kernel_size)); 3098 exit(1); 3099 } 3100 3101 if (spapr->kernel_addr != loaded_addr) { 3102 warn_report("spapr: kernel_addr changed from 0x%"PRIx64 3103 " to 0x%"PRIx64, 3104 spapr->kernel_addr, loaded_addr); 3105 spapr->kernel_addr = loaded_addr; 3106 } 3107 3108 /* load initrd */ 3109 if (initrd_filename) { 3110 /* Try to locate the initrd in the gap between the kernel 3111 * and the firmware. Add a bit of space just in case 3112 */ 3113 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 3114 + 0x1ffff) & ~0xffff; 3115 spapr->initrd_size = load_image_targphys(initrd_filename, 3116 spapr->initrd_base, 3117 load_limit 3118 - spapr->initrd_base); 3119 if (spapr->initrd_size < 0) { 3120 error_report("could not load initial ram disk '%s'", 3121 initrd_filename); 3122 exit(1); 3123 } 3124 } 3125 } 3126 3127 /* FIXME: Should register things through the MachineState's qdev 3128 * interface, this is a legacy from the sPAPREnvironment structure 3129 * which predated MachineState but had a similar function */ 3130 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3131 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3132 &savevm_htab_handlers, spapr); 3133 3134 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 3135 3136 qemu_register_boot_set(spapr_boot_set, spapr); 3137 3138 /* 3139 * Nothing needs to be done to resume a suspended guest because 3140 * suspending does not change the machine state, so no need for 3141 * a ->wakeup method. 3142 */ 3143 qemu_register_wakeup_support(); 3144 3145 if (kvm_enabled()) { 3146 /* to stop and start vmclock */ 3147 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3148 &spapr->tb); 3149 3150 kvmppc_spapr_enable_inkernel_multitce(); 3151 } 3152 3153 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3154 if (spapr->vof) { 3155 spapr->vof->fw_size = fw_size; /* for claim() on itself */ 3156 spapr_register_hypercall(KVMPPC_H_VOF_CLIENT, spapr_h_vof_client); 3157 } 3158 3159 spapr_watchdog_init(spapr); 3160 } 3161 3162 #define DEFAULT_KVM_TYPE "auto" 3163 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3164 { 3165 /* 3166 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to 3167 * accommodate the 'HV' and 'PV' formats that exists in the 3168 * wild. The 'auto' mode is being introduced already as 3169 * lower-case, thus we don't need to bother checking for 3170 * "AUTO". 3171 */ 3172 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) { 3173 return 0; 3174 } 3175 3176 if (!g_ascii_strcasecmp(vm_type, "hv")) { 3177 return 1; 3178 } 3179 3180 if (!g_ascii_strcasecmp(vm_type, "pr")) { 3181 return 2; 3182 } 3183 3184 error_report("Unknown kvm-type specified '%s'", vm_type); 3185 return -1; 3186 } 3187 3188 /* 3189 * Implementation of an interface to adjust firmware path 3190 * for the bootindex property handling. 3191 */ 3192 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3193 DeviceState *dev) 3194 { 3195 #define CAST(type, obj, name) \ 3196 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3197 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3198 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3199 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3200 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3201 3202 if (d && bus) { 3203 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3204 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3205 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3206 3207 if (spapr) { 3208 /* 3209 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3210 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3211 * 0x8000 | (target << 8) | (bus << 5) | lun 3212 * (see the "Logical unit addressing format" table in SAM5) 3213 */ 3214 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3215 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3216 (uint64_t)id << 48); 3217 } else if (virtio) { 3218 /* 3219 * We use SRP luns of the form 01000000 | (target << 8) | lun 3220 * in the top 32 bits of the 64-bit LUN 3221 * Note: the quote above is from SLOF and it is wrong, 3222 * the actual binding is: 3223 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3224 */ 3225 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3226 if (d->lun >= 256) { 3227 /* Use the LUN "flat space addressing method" */ 3228 id |= 0x4000; 3229 } 3230 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3231 (uint64_t)id << 32); 3232 } else if (usb) { 3233 /* 3234 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3235 * in the top 32 bits of the 64-bit LUN 3236 */ 3237 unsigned usb_port = atoi(usb->port->path); 3238 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3239 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3240 (uint64_t)id << 32); 3241 } 3242 } 3243 3244 /* 3245 * SLOF probes the USB devices, and if it recognizes that the device is a 3246 * storage device, it changes its name to "storage" instead of "usb-host", 3247 * and additionally adds a child node for the SCSI LUN, so the correct 3248 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3249 */ 3250 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3251 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3252 if (usb_device_is_scsi_storage(usbdev)) { 3253 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3254 } 3255 } 3256 3257 if (phb) { 3258 /* Replace "pci" with "pci@800000020000000" */ 3259 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3260 } 3261 3262 if (vsc) { 3263 /* Same logic as virtio above */ 3264 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3265 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3266 } 3267 3268 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3269 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3270 PCIDevice *pdev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3271 return g_strdup_printf("pci@%x", PCI_SLOT(pdev->devfn)); 3272 } 3273 3274 if (pcidev) { 3275 return spapr_pci_fw_dev_name(pcidev); 3276 } 3277 3278 return NULL; 3279 } 3280 3281 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3282 { 3283 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3284 3285 return g_strdup(spapr->kvm_type); 3286 } 3287 3288 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3289 { 3290 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3291 3292 g_free(spapr->kvm_type); 3293 spapr->kvm_type = g_strdup(value); 3294 } 3295 3296 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3297 { 3298 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3299 3300 return spapr->use_hotplug_event_source; 3301 } 3302 3303 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3304 Error **errp) 3305 { 3306 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3307 3308 spapr->use_hotplug_event_source = value; 3309 } 3310 3311 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3312 { 3313 return true; 3314 } 3315 3316 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3317 { 3318 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3319 3320 switch (spapr->resize_hpt) { 3321 case SPAPR_RESIZE_HPT_DEFAULT: 3322 return g_strdup("default"); 3323 case SPAPR_RESIZE_HPT_DISABLED: 3324 return g_strdup("disabled"); 3325 case SPAPR_RESIZE_HPT_ENABLED: 3326 return g_strdup("enabled"); 3327 case SPAPR_RESIZE_HPT_REQUIRED: 3328 return g_strdup("required"); 3329 } 3330 g_assert_not_reached(); 3331 } 3332 3333 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3334 { 3335 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3336 3337 if (strcmp(value, "default") == 0) { 3338 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3339 } else if (strcmp(value, "disabled") == 0) { 3340 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3341 } else if (strcmp(value, "enabled") == 0) { 3342 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3343 } else if (strcmp(value, "required") == 0) { 3344 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3345 } else { 3346 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3347 } 3348 } 3349 3350 static bool spapr_get_vof(Object *obj, Error **errp) 3351 { 3352 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3353 3354 return spapr->vof != NULL; 3355 } 3356 3357 static void spapr_set_vof(Object *obj, bool value, Error **errp) 3358 { 3359 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3360 3361 if (spapr->vof) { 3362 vof_cleanup(spapr->vof); 3363 g_free(spapr->vof); 3364 spapr->vof = NULL; 3365 } 3366 if (!value) { 3367 return; 3368 } 3369 spapr->vof = g_malloc0(sizeof(*spapr->vof)); 3370 } 3371 3372 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3373 { 3374 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3375 3376 if (spapr->irq == &spapr_irq_xics_legacy) { 3377 return g_strdup("legacy"); 3378 } else if (spapr->irq == &spapr_irq_xics) { 3379 return g_strdup("xics"); 3380 } else if (spapr->irq == &spapr_irq_xive) { 3381 return g_strdup("xive"); 3382 } else if (spapr->irq == &spapr_irq_dual) { 3383 return g_strdup("dual"); 3384 } 3385 g_assert_not_reached(); 3386 } 3387 3388 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3389 { 3390 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3391 3392 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3393 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3394 return; 3395 } 3396 3397 /* The legacy IRQ backend can not be set */ 3398 if (strcmp(value, "xics") == 0) { 3399 spapr->irq = &spapr_irq_xics; 3400 } else if (strcmp(value, "xive") == 0) { 3401 spapr->irq = &spapr_irq_xive; 3402 } else if (strcmp(value, "dual") == 0) { 3403 spapr->irq = &spapr_irq_dual; 3404 } else { 3405 error_setg(errp, "Bad value for \"ic-mode\" property"); 3406 } 3407 } 3408 3409 static char *spapr_get_host_model(Object *obj, Error **errp) 3410 { 3411 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3412 3413 return g_strdup(spapr->host_model); 3414 } 3415 3416 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3417 { 3418 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3419 3420 g_free(spapr->host_model); 3421 spapr->host_model = g_strdup(value); 3422 } 3423 3424 static char *spapr_get_host_serial(Object *obj, Error **errp) 3425 { 3426 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3427 3428 return g_strdup(spapr->host_serial); 3429 } 3430 3431 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3432 { 3433 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3434 3435 g_free(spapr->host_serial); 3436 spapr->host_serial = g_strdup(value); 3437 } 3438 3439 static void spapr_instance_init(Object *obj) 3440 { 3441 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3442 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3443 MachineState *ms = MACHINE(spapr); 3444 MachineClass *mc = MACHINE_GET_CLASS(ms); 3445 3446 /* 3447 * NVDIMM support went live in 5.1 without considering that, in 3448 * other archs, the user needs to enable NVDIMM support with the 3449 * 'nvdimm' machine option and the default behavior is NVDIMM 3450 * support disabled. It is too late to roll back to the standard 3451 * behavior without breaking 5.1 guests. 3452 */ 3453 if (mc->nvdimm_supported) { 3454 ms->nvdimms_state->is_enabled = true; 3455 } 3456 3457 spapr->htab_fd = -1; 3458 spapr->use_hotplug_event_source = true; 3459 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE); 3460 object_property_add_str(obj, "kvm-type", 3461 spapr_get_kvm_type, spapr_set_kvm_type); 3462 object_property_set_description(obj, "kvm-type", 3463 "Specifies the KVM virtualization mode (auto," 3464 " hv, pr). Defaults to 'auto'. This mode will use" 3465 " any available KVM module loaded in the host," 3466 " where kvm_hv takes precedence if both kvm_hv and" 3467 " kvm_pr are loaded."); 3468 object_property_add_bool(obj, "modern-hotplug-events", 3469 spapr_get_modern_hotplug_events, 3470 spapr_set_modern_hotplug_events); 3471 object_property_set_description(obj, "modern-hotplug-events", 3472 "Use dedicated hotplug event mechanism in" 3473 " place of standard EPOW events when possible" 3474 " (required for memory hot-unplug support)"); 3475 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3476 "Maximum permitted CPU compatibility mode"); 3477 3478 object_property_add_str(obj, "resize-hpt", 3479 spapr_get_resize_hpt, spapr_set_resize_hpt); 3480 object_property_set_description(obj, "resize-hpt", 3481 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3482 object_property_add_uint32_ptr(obj, "vsmt", 3483 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3484 object_property_set_description(obj, "vsmt", 3485 "Virtual SMT: KVM behaves as if this were" 3486 " the host's SMT mode"); 3487 3488 object_property_add_bool(obj, "vfio-no-msix-emulation", 3489 spapr_get_msix_emulation, NULL); 3490 3491 object_property_add_uint64_ptr(obj, "kernel-addr", 3492 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3493 object_property_set_description(obj, "kernel-addr", 3494 stringify(KERNEL_LOAD_ADDR) 3495 " for -kernel is the default"); 3496 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3497 3498 object_property_add_bool(obj, "x-vof", spapr_get_vof, spapr_set_vof); 3499 object_property_set_description(obj, "x-vof", 3500 "Enable Virtual Open Firmware (experimental)"); 3501 3502 /* The machine class defines the default interrupt controller mode */ 3503 spapr->irq = smc->irq; 3504 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3505 spapr_set_ic_mode); 3506 object_property_set_description(obj, "ic-mode", 3507 "Specifies the interrupt controller mode (xics, xive, dual)"); 3508 3509 object_property_add_str(obj, "host-model", 3510 spapr_get_host_model, spapr_set_host_model); 3511 object_property_set_description(obj, "host-model", 3512 "Host model to advertise in guest device tree"); 3513 object_property_add_str(obj, "host-serial", 3514 spapr_get_host_serial, spapr_set_host_serial); 3515 object_property_set_description(obj, "host-serial", 3516 "Host serial number to advertise in guest device tree"); 3517 } 3518 3519 static void spapr_machine_finalizefn(Object *obj) 3520 { 3521 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3522 3523 g_free(spapr->kvm_type); 3524 } 3525 3526 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3527 { 3528 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3529 PowerPCCPU *cpu = POWERPC_CPU(cs); 3530 CPUPPCState *env = &cpu->env; 3531 3532 cpu_synchronize_state(cs); 3533 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3534 if (spapr->fwnmi_system_reset_addr != -1) { 3535 uint64_t rtas_addr, addr; 3536 3537 /* get rtas addr from fdt */ 3538 rtas_addr = spapr_get_rtas_addr(); 3539 if (!rtas_addr) { 3540 qemu_system_guest_panicked(NULL); 3541 return; 3542 } 3543 3544 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3545 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3546 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3547 env->gpr[3] = addr; 3548 } 3549 ppc_cpu_do_system_reset(cs); 3550 if (spapr->fwnmi_system_reset_addr != -1) { 3551 env->nip = spapr->fwnmi_system_reset_addr; 3552 } 3553 } 3554 3555 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3556 { 3557 CPUState *cs; 3558 3559 CPU_FOREACH(cs) { 3560 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3561 } 3562 } 3563 3564 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3565 void *fdt, int *fdt_start_offset, Error **errp) 3566 { 3567 uint64_t addr; 3568 uint32_t node; 3569 3570 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3571 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3572 &error_abort); 3573 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3574 SPAPR_MEMORY_BLOCK_SIZE); 3575 return 0; 3576 } 3577 3578 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3579 bool dedicated_hp_event_source) 3580 { 3581 SpaprDrc *drc; 3582 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3583 int i; 3584 uint64_t addr = addr_start; 3585 bool hotplugged = spapr_drc_hotplugged(dev); 3586 3587 for (i = 0; i < nr_lmbs; i++) { 3588 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3589 addr / SPAPR_MEMORY_BLOCK_SIZE); 3590 g_assert(drc); 3591 3592 /* 3593 * memory_device_get_free_addr() provided a range of free addresses 3594 * that doesn't overlap with any existing mapping at pre-plug. The 3595 * corresponding LMB DRCs are thus assumed to be all attachable. 3596 */ 3597 spapr_drc_attach(drc, dev); 3598 if (!hotplugged) { 3599 spapr_drc_reset(drc); 3600 } 3601 addr += SPAPR_MEMORY_BLOCK_SIZE; 3602 } 3603 /* send hotplug notification to the 3604 * guest only in case of hotplugged memory 3605 */ 3606 if (hotplugged) { 3607 if (dedicated_hp_event_source) { 3608 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3609 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3610 g_assert(drc); 3611 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3612 nr_lmbs, 3613 spapr_drc_index(drc)); 3614 } else { 3615 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3616 nr_lmbs); 3617 } 3618 } 3619 } 3620 3621 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3622 { 3623 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3624 PCDIMMDevice *dimm = PC_DIMM(dev); 3625 uint64_t size, addr; 3626 int64_t slot; 3627 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3628 3629 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3630 3631 pc_dimm_plug(dimm, MACHINE(ms)); 3632 3633 if (!is_nvdimm) { 3634 addr = object_property_get_uint(OBJECT(dimm), 3635 PC_DIMM_ADDR_PROP, &error_abort); 3636 spapr_add_lmbs(dev, addr, size, 3637 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT)); 3638 } else { 3639 slot = object_property_get_int(OBJECT(dimm), 3640 PC_DIMM_SLOT_PROP, &error_abort); 3641 /* We should have valid slot number at this point */ 3642 g_assert(slot >= 0); 3643 spapr_add_nvdimm(dev, slot); 3644 } 3645 } 3646 3647 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3648 Error **errp) 3649 { 3650 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3651 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3652 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3653 PCDIMMDevice *dimm = PC_DIMM(dev); 3654 Error *local_err = NULL; 3655 uint64_t size; 3656 Object *memdev; 3657 hwaddr pagesize; 3658 3659 if (!smc->dr_lmb_enabled) { 3660 error_setg(errp, "Memory hotplug not supported for this machine"); 3661 return; 3662 } 3663 3664 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3665 if (local_err) { 3666 error_propagate(errp, local_err); 3667 return; 3668 } 3669 3670 if (is_nvdimm) { 3671 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3672 return; 3673 } 3674 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3675 error_setg(errp, "Hotplugged memory size must be a multiple of " 3676 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3677 return; 3678 } 3679 3680 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3681 &error_abort); 3682 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3683 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3684 return; 3685 } 3686 3687 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3688 } 3689 3690 struct SpaprDimmState { 3691 PCDIMMDevice *dimm; 3692 uint32_t nr_lmbs; 3693 QTAILQ_ENTRY(SpaprDimmState) next; 3694 }; 3695 3696 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3697 PCDIMMDevice *dimm) 3698 { 3699 SpaprDimmState *dimm_state = NULL; 3700 3701 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3702 if (dimm_state->dimm == dimm) { 3703 break; 3704 } 3705 } 3706 return dimm_state; 3707 } 3708 3709 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3710 uint32_t nr_lmbs, 3711 PCDIMMDevice *dimm) 3712 { 3713 SpaprDimmState *ds = NULL; 3714 3715 /* 3716 * If this request is for a DIMM whose removal had failed earlier 3717 * (due to guest's refusal to remove the LMBs), we would have this 3718 * dimm already in the pending_dimm_unplugs list. In that 3719 * case don't add again. 3720 */ 3721 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3722 if (!ds) { 3723 ds = g_new0(SpaprDimmState, 1); 3724 ds->nr_lmbs = nr_lmbs; 3725 ds->dimm = dimm; 3726 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3727 } 3728 return ds; 3729 } 3730 3731 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3732 SpaprDimmState *dimm_state) 3733 { 3734 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3735 g_free(dimm_state); 3736 } 3737 3738 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3739 PCDIMMDevice *dimm) 3740 { 3741 SpaprDrc *drc; 3742 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3743 &error_abort); 3744 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3745 uint32_t avail_lmbs = 0; 3746 uint64_t addr_start, addr; 3747 int i; 3748 3749 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3750 &error_abort); 3751 3752 addr = addr_start; 3753 for (i = 0; i < nr_lmbs; i++) { 3754 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3755 addr / SPAPR_MEMORY_BLOCK_SIZE); 3756 g_assert(drc); 3757 if (drc->dev) { 3758 avail_lmbs++; 3759 } 3760 addr += SPAPR_MEMORY_BLOCK_SIZE; 3761 } 3762 3763 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3764 } 3765 3766 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev) 3767 { 3768 SpaprDimmState *ds; 3769 PCDIMMDevice *dimm; 3770 SpaprDrc *drc; 3771 uint32_t nr_lmbs; 3772 uint64_t size, addr_start, addr; 3773 g_autofree char *qapi_error = NULL; 3774 int i; 3775 3776 if (!dev) { 3777 return; 3778 } 3779 3780 dimm = PC_DIMM(dev); 3781 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3782 3783 /* 3784 * 'ds == NULL' would mean that the DIMM doesn't have a pending 3785 * unplug state, but one of its DRC is marked as unplug_requested. 3786 * This is bad and weird enough to g_assert() out. 3787 */ 3788 g_assert(ds); 3789 3790 spapr_pending_dimm_unplugs_remove(spapr, ds); 3791 3792 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3793 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3794 3795 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3796 &error_abort); 3797 3798 addr = addr_start; 3799 for (i = 0; i < nr_lmbs; i++) { 3800 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3801 addr / SPAPR_MEMORY_BLOCK_SIZE); 3802 g_assert(drc); 3803 3804 drc->unplug_requested = false; 3805 addr += SPAPR_MEMORY_BLOCK_SIZE; 3806 } 3807 3808 /* 3809 * Tell QAPI that something happened and the memory 3810 * hotunplug wasn't successful. Keep sending 3811 * MEM_UNPLUG_ERROR even while sending 3812 * DEVICE_UNPLUG_GUEST_ERROR until the deprecation of 3813 * MEM_UNPLUG_ERROR is due. 3814 */ 3815 qapi_error = g_strdup_printf("Memory hotunplug rejected by the guest " 3816 "for device %s", dev->id); 3817 3818 qapi_event_send_mem_unplug_error(dev->id ? : "", qapi_error); 3819 3820 qapi_event_send_device_unplug_guest_error(dev->id, 3821 dev->canonical_path); 3822 } 3823 3824 /* Callback to be called during DRC release. */ 3825 void spapr_lmb_release(DeviceState *dev) 3826 { 3827 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3828 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3829 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3830 3831 /* This information will get lost if a migration occurs 3832 * during the unplug process. In this case recover it. */ 3833 if (ds == NULL) { 3834 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3835 g_assert(ds); 3836 /* The DRC being examined by the caller at least must be counted */ 3837 g_assert(ds->nr_lmbs); 3838 } 3839 3840 if (--ds->nr_lmbs) { 3841 return; 3842 } 3843 3844 /* 3845 * Now that all the LMBs have been removed by the guest, call the 3846 * unplug handler chain. This can never fail. 3847 */ 3848 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3849 object_unparent(OBJECT(dev)); 3850 } 3851 3852 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3853 { 3854 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3855 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3856 3857 /* We really shouldn't get this far without anything to unplug */ 3858 g_assert(ds); 3859 3860 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3861 qdev_unrealize(dev); 3862 spapr_pending_dimm_unplugs_remove(spapr, ds); 3863 } 3864 3865 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3866 DeviceState *dev, Error **errp) 3867 { 3868 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3869 PCDIMMDevice *dimm = PC_DIMM(dev); 3870 uint32_t nr_lmbs; 3871 uint64_t size, addr_start, addr; 3872 int i; 3873 SpaprDrc *drc; 3874 3875 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3876 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3877 return; 3878 } 3879 3880 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3881 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3882 3883 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3884 &error_abort); 3885 3886 /* 3887 * An existing pending dimm state for this DIMM means that there is an 3888 * unplug operation in progress, waiting for the spapr_lmb_release 3889 * callback to complete the job (BQL can't cover that far). In this case, 3890 * bail out to avoid detaching DRCs that were already released. 3891 */ 3892 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3893 error_setg(errp, "Memory unplug already in progress for device %s", 3894 dev->id); 3895 return; 3896 } 3897 3898 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3899 3900 addr = addr_start; 3901 for (i = 0; i < nr_lmbs; i++) { 3902 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3903 addr / SPAPR_MEMORY_BLOCK_SIZE); 3904 g_assert(drc); 3905 3906 spapr_drc_unplug_request(drc); 3907 addr += SPAPR_MEMORY_BLOCK_SIZE; 3908 } 3909 3910 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3911 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3912 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3913 nr_lmbs, spapr_drc_index(drc)); 3914 } 3915 3916 /* Callback to be called during DRC release. */ 3917 void spapr_core_release(DeviceState *dev) 3918 { 3919 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3920 3921 /* Call the unplug handler chain. This can never fail. */ 3922 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3923 object_unparent(OBJECT(dev)); 3924 } 3925 3926 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3927 { 3928 MachineState *ms = MACHINE(hotplug_dev); 3929 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3930 CPUCore *cc = CPU_CORE(dev); 3931 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3932 3933 if (smc->pre_2_10_has_unused_icps) { 3934 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3935 int i; 3936 3937 for (i = 0; i < cc->nr_threads; i++) { 3938 CPUState *cs = CPU(sc->threads[i]); 3939 3940 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3941 } 3942 } 3943 3944 assert(core_slot); 3945 core_slot->cpu = NULL; 3946 qdev_unrealize(dev); 3947 } 3948 3949 static 3950 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3951 Error **errp) 3952 { 3953 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3954 int index; 3955 SpaprDrc *drc; 3956 CPUCore *cc = CPU_CORE(dev); 3957 3958 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3959 error_setg(errp, "Unable to find CPU core with core-id: %d", 3960 cc->core_id); 3961 return; 3962 } 3963 if (index == 0) { 3964 error_setg(errp, "Boot CPU core may not be unplugged"); 3965 return; 3966 } 3967 3968 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3969 spapr_vcpu_id(spapr, cc->core_id)); 3970 g_assert(drc); 3971 3972 if (!spapr_drc_unplug_requested(drc)) { 3973 spapr_drc_unplug_request(drc); 3974 } 3975 3976 /* 3977 * spapr_hotplug_req_remove_by_index is left unguarded, out of the 3978 * "!spapr_drc_unplug_requested" check, to allow for multiple IRQ 3979 * pulses removing the same CPU. Otherwise, in an failed hotunplug 3980 * attempt (e.g. the kernel will refuse to remove the last online 3981 * CPU), we will never attempt it again because unplug_requested 3982 * will still be 'true' in that case. 3983 */ 3984 spapr_hotplug_req_remove_by_index(drc); 3985 } 3986 3987 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3988 void *fdt, int *fdt_start_offset, Error **errp) 3989 { 3990 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3991 CPUState *cs = CPU(core->threads[0]); 3992 PowerPCCPU *cpu = POWERPC_CPU(cs); 3993 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3994 int id = spapr_get_vcpu_id(cpu); 3995 g_autofree char *nodename = NULL; 3996 int offset; 3997 3998 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3999 offset = fdt_add_subnode(fdt, 0, nodename); 4000 4001 spapr_dt_cpu(cs, fdt, offset, spapr); 4002 4003 /* 4004 * spapr_dt_cpu() does not fill the 'name' property in the 4005 * CPU node. The function is called during boot process, before 4006 * and after CAS, and overwriting the 'name' property written 4007 * by SLOF is not allowed. 4008 * 4009 * Write it manually after spapr_dt_cpu(). This makes the hotplug 4010 * CPUs more compatible with the coldplugged ones, which have 4011 * the 'name' property. Linux Kernel also relies on this 4012 * property to identify CPU nodes. 4013 */ 4014 _FDT((fdt_setprop_string(fdt, offset, "name", nodename))); 4015 4016 *fdt_start_offset = offset; 4017 return 0; 4018 } 4019 4020 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4021 { 4022 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4023 MachineClass *mc = MACHINE_GET_CLASS(spapr); 4024 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4025 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 4026 CPUCore *cc = CPU_CORE(dev); 4027 CPUState *cs; 4028 SpaprDrc *drc; 4029 CPUArchId *core_slot; 4030 int index; 4031 bool hotplugged = spapr_drc_hotplugged(dev); 4032 int i; 4033 4034 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 4035 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */ 4036 4037 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 4038 spapr_vcpu_id(spapr, cc->core_id)); 4039 4040 g_assert(drc || !mc->has_hotpluggable_cpus); 4041 4042 if (drc) { 4043 /* 4044 * spapr_core_pre_plug() already buys us this is a brand new 4045 * core being plugged into a free slot. Nothing should already 4046 * be attached to the corresponding DRC. 4047 */ 4048 spapr_drc_attach(drc, dev); 4049 4050 if (hotplugged) { 4051 /* 4052 * Send hotplug notification interrupt to the guest only 4053 * in case of hotplugged CPUs. 4054 */ 4055 spapr_hotplug_req_add_by_index(drc); 4056 } else { 4057 spapr_drc_reset(drc); 4058 } 4059 } 4060 4061 core_slot->cpu = OBJECT(dev); 4062 4063 /* 4064 * Set compatibility mode to match the boot CPU, which was either set 4065 * by the machine reset code or by CAS. This really shouldn't fail at 4066 * this point. 4067 */ 4068 if (hotplugged) { 4069 for (i = 0; i < cc->nr_threads; i++) { 4070 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 4071 &error_abort); 4072 } 4073 } 4074 4075 if (smc->pre_2_10_has_unused_icps) { 4076 for (i = 0; i < cc->nr_threads; i++) { 4077 cs = CPU(core->threads[i]); 4078 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 4079 } 4080 } 4081 } 4082 4083 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4084 Error **errp) 4085 { 4086 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 4087 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 4088 CPUCore *cc = CPU_CORE(dev); 4089 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 4090 const char *type = object_get_typename(OBJECT(dev)); 4091 CPUArchId *core_slot; 4092 int index; 4093 unsigned int smp_threads = machine->smp.threads; 4094 4095 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 4096 error_setg(errp, "CPU hotplug not supported for this machine"); 4097 return; 4098 } 4099 4100 if (strcmp(base_core_type, type)) { 4101 error_setg(errp, "CPU core type should be %s", base_core_type); 4102 return; 4103 } 4104 4105 if (cc->core_id % smp_threads) { 4106 error_setg(errp, "invalid core id %d", cc->core_id); 4107 return; 4108 } 4109 4110 /* 4111 * In general we should have homogeneous threads-per-core, but old 4112 * (pre hotplug support) machine types allow the last core to have 4113 * reduced threads as a compatibility hack for when we allowed 4114 * total vcpus not a multiple of threads-per-core. 4115 */ 4116 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 4117 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 4118 smp_threads); 4119 return; 4120 } 4121 4122 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 4123 if (!core_slot) { 4124 error_setg(errp, "core id %d out of range", cc->core_id); 4125 return; 4126 } 4127 4128 if (core_slot->cpu) { 4129 error_setg(errp, "core %d already populated", cc->core_id); 4130 return; 4131 } 4132 4133 numa_cpu_pre_plug(core_slot, dev, errp); 4134 } 4135 4136 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 4137 void *fdt, int *fdt_start_offset, Error **errp) 4138 { 4139 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 4140 int intc_phandle; 4141 4142 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 4143 if (intc_phandle <= 0) { 4144 return -1; 4145 } 4146 4147 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 4148 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 4149 return -1; 4150 } 4151 4152 /* generally SLOF creates these, for hotplug it's up to QEMU */ 4153 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 4154 4155 return 0; 4156 } 4157 4158 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4159 Error **errp) 4160 { 4161 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4162 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4163 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4164 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 4165 SpaprDrc *drc; 4166 4167 if (dev->hotplugged && !smc->dr_phb_enabled) { 4168 error_setg(errp, "PHB hotplug not supported for this machine"); 4169 return false; 4170 } 4171 4172 if (sphb->index == (uint32_t)-1) { 4173 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 4174 return false; 4175 } 4176 4177 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4178 if (drc && drc->dev) { 4179 error_setg(errp, "PHB %d already attached", sphb->index); 4180 return false; 4181 } 4182 4183 /* 4184 * This will check that sphb->index doesn't exceed the maximum number of 4185 * PHBs for the current machine type. 4186 */ 4187 return 4188 smc->phb_placement(spapr, sphb->index, 4189 &sphb->buid, &sphb->io_win_addr, 4190 &sphb->mem_win_addr, &sphb->mem64_win_addr, 4191 windows_supported, sphb->dma_liobn, 4192 errp); 4193 } 4194 4195 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4196 { 4197 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4198 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4199 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4200 SpaprDrc *drc; 4201 bool hotplugged = spapr_drc_hotplugged(dev); 4202 4203 if (!smc->dr_phb_enabled) { 4204 return; 4205 } 4206 4207 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4208 /* hotplug hooks should check it's enabled before getting this far */ 4209 assert(drc); 4210 4211 /* spapr_phb_pre_plug() already checked the DRC is attachable */ 4212 spapr_drc_attach(drc, dev); 4213 4214 if (hotplugged) { 4215 spapr_hotplug_req_add_by_index(drc); 4216 } else { 4217 spapr_drc_reset(drc); 4218 } 4219 } 4220 4221 void spapr_phb_release(DeviceState *dev) 4222 { 4223 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4224 4225 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4226 object_unparent(OBJECT(dev)); 4227 } 4228 4229 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4230 { 4231 qdev_unrealize(dev); 4232 } 4233 4234 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4235 DeviceState *dev, Error **errp) 4236 { 4237 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4238 SpaprDrc *drc; 4239 4240 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4241 assert(drc); 4242 4243 if (!spapr_drc_unplug_requested(drc)) { 4244 spapr_drc_unplug_request(drc); 4245 spapr_hotplug_req_remove_by_index(drc); 4246 } else { 4247 error_setg(errp, 4248 "PCI Host Bridge unplug already in progress for device %s", 4249 dev->id); 4250 } 4251 } 4252 4253 static 4254 bool spapr_tpm_proxy_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4255 Error **errp) 4256 { 4257 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4258 4259 if (spapr->tpm_proxy != NULL) { 4260 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4261 return false; 4262 } 4263 4264 return true; 4265 } 4266 4267 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4268 { 4269 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4270 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4271 4272 /* Already checked in spapr_tpm_proxy_pre_plug() */ 4273 g_assert(spapr->tpm_proxy == NULL); 4274 4275 spapr->tpm_proxy = tpm_proxy; 4276 } 4277 4278 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4279 { 4280 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4281 4282 qdev_unrealize(dev); 4283 object_unparent(OBJECT(dev)); 4284 spapr->tpm_proxy = NULL; 4285 } 4286 4287 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4288 DeviceState *dev, Error **errp) 4289 { 4290 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4291 spapr_memory_plug(hotplug_dev, dev); 4292 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4293 spapr_core_plug(hotplug_dev, dev); 4294 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4295 spapr_phb_plug(hotplug_dev, dev); 4296 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4297 spapr_tpm_proxy_plug(hotplug_dev, dev); 4298 } 4299 } 4300 4301 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4302 DeviceState *dev, Error **errp) 4303 { 4304 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4305 spapr_memory_unplug(hotplug_dev, dev); 4306 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4307 spapr_core_unplug(hotplug_dev, dev); 4308 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4309 spapr_phb_unplug(hotplug_dev, dev); 4310 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4311 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4312 } 4313 } 4314 4315 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr) 4316 { 4317 return spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT) || 4318 /* 4319 * CAS will process all pending unplug requests. 4320 * 4321 * HACK: a guest could theoretically have cleared all bits in OV5, 4322 * but none of the guests we care for do. 4323 */ 4324 spapr_ovec_empty(spapr->ov5_cas); 4325 } 4326 4327 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4328 DeviceState *dev, Error **errp) 4329 { 4330 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4331 MachineClass *mc = MACHINE_GET_CLASS(sms); 4332 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4333 4334 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4335 if (spapr_memory_hot_unplug_supported(sms)) { 4336 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4337 } else { 4338 error_setg(errp, "Memory hot unplug not supported for this guest"); 4339 } 4340 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4341 if (!mc->has_hotpluggable_cpus) { 4342 error_setg(errp, "CPU hot unplug not supported on this machine"); 4343 return; 4344 } 4345 spapr_core_unplug_request(hotplug_dev, dev, errp); 4346 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4347 if (!smc->dr_phb_enabled) { 4348 error_setg(errp, "PHB hot unplug not supported on this machine"); 4349 return; 4350 } 4351 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4352 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4353 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4354 } 4355 } 4356 4357 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4358 DeviceState *dev, Error **errp) 4359 { 4360 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4361 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4362 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4363 spapr_core_pre_plug(hotplug_dev, dev, errp); 4364 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4365 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4366 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4367 spapr_tpm_proxy_pre_plug(hotplug_dev, dev, errp); 4368 } 4369 } 4370 4371 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4372 DeviceState *dev) 4373 { 4374 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4375 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4376 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4377 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4378 return HOTPLUG_HANDLER(machine); 4379 } 4380 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4381 PCIDevice *pcidev = PCI_DEVICE(dev); 4382 PCIBus *root = pci_device_root_bus(pcidev); 4383 SpaprPhbState *phb = 4384 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4385 TYPE_SPAPR_PCI_HOST_BRIDGE); 4386 4387 if (phb) { 4388 return HOTPLUG_HANDLER(phb); 4389 } 4390 } 4391 return NULL; 4392 } 4393 4394 static CpuInstanceProperties 4395 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4396 { 4397 CPUArchId *core_slot; 4398 MachineClass *mc = MACHINE_GET_CLASS(machine); 4399 4400 /* make sure possible_cpu are initialized */ 4401 mc->possible_cpu_arch_ids(machine); 4402 /* get CPU core slot containing thread that matches cpu_index */ 4403 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4404 assert(core_slot); 4405 return core_slot->props; 4406 } 4407 4408 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4409 { 4410 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4411 } 4412 4413 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4414 { 4415 int i; 4416 unsigned int smp_threads = machine->smp.threads; 4417 unsigned int smp_cpus = machine->smp.cpus; 4418 const char *core_type; 4419 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4420 MachineClass *mc = MACHINE_GET_CLASS(machine); 4421 4422 if (!mc->has_hotpluggable_cpus) { 4423 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4424 } 4425 if (machine->possible_cpus) { 4426 assert(machine->possible_cpus->len == spapr_max_cores); 4427 return machine->possible_cpus; 4428 } 4429 4430 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4431 if (!core_type) { 4432 error_report("Unable to find sPAPR CPU Core definition"); 4433 exit(1); 4434 } 4435 4436 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4437 sizeof(CPUArchId) * spapr_max_cores); 4438 machine->possible_cpus->len = spapr_max_cores; 4439 for (i = 0; i < machine->possible_cpus->len; i++) { 4440 int core_id = i * smp_threads; 4441 4442 machine->possible_cpus->cpus[i].type = core_type; 4443 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4444 machine->possible_cpus->cpus[i].arch_id = core_id; 4445 machine->possible_cpus->cpus[i].props.has_core_id = true; 4446 machine->possible_cpus->cpus[i].props.core_id = core_id; 4447 } 4448 return machine->possible_cpus; 4449 } 4450 4451 static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4452 uint64_t *buid, hwaddr *pio, 4453 hwaddr *mmio32, hwaddr *mmio64, 4454 unsigned n_dma, uint32_t *liobns, Error **errp) 4455 { 4456 /* 4457 * New-style PHB window placement. 4458 * 4459 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4460 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4461 * windows. 4462 * 4463 * Some guest kernels can't work with MMIO windows above 1<<46 4464 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4465 * 4466 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4467 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4468 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4469 * 1TiB 64-bit MMIO windows for each PHB. 4470 */ 4471 const uint64_t base_buid = 0x800000020000000ULL; 4472 int i; 4473 4474 /* Sanity check natural alignments */ 4475 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4476 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4477 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4478 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4479 /* Sanity check bounds */ 4480 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4481 SPAPR_PCI_MEM32_WIN_SIZE); 4482 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4483 SPAPR_PCI_MEM64_WIN_SIZE); 4484 4485 if (index >= SPAPR_MAX_PHBS) { 4486 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4487 SPAPR_MAX_PHBS - 1); 4488 return false; 4489 } 4490 4491 *buid = base_buid + index; 4492 for (i = 0; i < n_dma; ++i) { 4493 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4494 } 4495 4496 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4497 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4498 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4499 return true; 4500 } 4501 4502 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4503 { 4504 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4505 4506 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4507 } 4508 4509 static void spapr_ics_resend(XICSFabric *dev) 4510 { 4511 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4512 4513 ics_resend(spapr->ics); 4514 } 4515 4516 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4517 { 4518 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4519 4520 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4521 } 4522 4523 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4524 Monitor *mon) 4525 { 4526 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4527 4528 spapr_irq_print_info(spapr, mon); 4529 monitor_printf(mon, "irqchip: %s\n", 4530 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4531 } 4532 4533 /* 4534 * This is a XIVE only operation 4535 */ 4536 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4537 uint8_t nvt_blk, uint32_t nvt_idx, 4538 bool cam_ignore, uint8_t priority, 4539 uint32_t logic_serv, XiveTCTXMatch *match) 4540 { 4541 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4542 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4543 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4544 int count; 4545 4546 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4547 priority, logic_serv, match); 4548 if (count < 0) { 4549 return count; 4550 } 4551 4552 /* 4553 * When we implement the save and restore of the thread interrupt 4554 * contexts in the enter/exit CPU handlers of the machine and the 4555 * escalations in QEMU, we should be able to handle non dispatched 4556 * vCPUs. 4557 * 4558 * Until this is done, the sPAPR machine should find at least one 4559 * matching context always. 4560 */ 4561 if (count == 0) { 4562 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4563 nvt_blk, nvt_idx); 4564 } 4565 4566 return count; 4567 } 4568 4569 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4570 { 4571 return cpu->vcpu_id; 4572 } 4573 4574 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4575 { 4576 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4577 MachineState *ms = MACHINE(spapr); 4578 int vcpu_id; 4579 4580 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4581 4582 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4583 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4584 error_append_hint(errp, "Adjust the number of cpus to %d " 4585 "or try to raise the number of threads per core\n", 4586 vcpu_id * ms->smp.threads / spapr->vsmt); 4587 return false; 4588 } 4589 4590 cpu->vcpu_id = vcpu_id; 4591 return true; 4592 } 4593 4594 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4595 { 4596 CPUState *cs; 4597 4598 CPU_FOREACH(cs) { 4599 PowerPCCPU *cpu = POWERPC_CPU(cs); 4600 4601 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4602 return cpu; 4603 } 4604 } 4605 4606 return NULL; 4607 } 4608 4609 static bool spapr_cpu_in_nested(PowerPCCPU *cpu) 4610 { 4611 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4612 4613 return spapr_cpu->in_nested; 4614 } 4615 4616 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4617 { 4618 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4619 4620 /* These are only called by TCG, KVM maintains dispatch state */ 4621 4622 spapr_cpu->prod = false; 4623 if (spapr_cpu->vpa_addr) { 4624 CPUState *cs = CPU(cpu); 4625 uint32_t dispatch; 4626 4627 dispatch = ldl_be_phys(cs->as, 4628 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4629 dispatch++; 4630 if ((dispatch & 1) != 0) { 4631 qemu_log_mask(LOG_GUEST_ERROR, 4632 "VPA: incorrect dispatch counter value for " 4633 "dispatched partition %u, correcting.\n", dispatch); 4634 dispatch++; 4635 } 4636 stl_be_phys(cs->as, 4637 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4638 } 4639 } 4640 4641 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4642 { 4643 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4644 4645 if (spapr_cpu->vpa_addr) { 4646 CPUState *cs = CPU(cpu); 4647 uint32_t dispatch; 4648 4649 dispatch = ldl_be_phys(cs->as, 4650 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4651 dispatch++; 4652 if ((dispatch & 1) != 1) { 4653 qemu_log_mask(LOG_GUEST_ERROR, 4654 "VPA: incorrect dispatch counter value for " 4655 "preempted partition %u, correcting.\n", dispatch); 4656 dispatch++; 4657 } 4658 stl_be_phys(cs->as, 4659 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4660 } 4661 } 4662 4663 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4664 { 4665 MachineClass *mc = MACHINE_CLASS(oc); 4666 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4667 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4668 NMIClass *nc = NMI_CLASS(oc); 4669 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4670 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4671 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4672 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4673 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4674 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc); 4675 4676 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4677 mc->ignore_boot_device_suffixes = true; 4678 4679 /* 4680 * We set up the default / latest behaviour here. The class_init 4681 * functions for the specific versioned machine types can override 4682 * these details for backwards compatibility 4683 */ 4684 mc->init = spapr_machine_init; 4685 mc->reset = spapr_machine_reset; 4686 mc->block_default_type = IF_SCSI; 4687 4688 /* 4689 * While KVM determines max cpus in kvm_init() using kvm_max_vcpus(), 4690 * In TCG the limit is restricted by the range of CPU IPIs available. 4691 */ 4692 mc->max_cpus = SPAPR_IRQ_NR_IPIS; 4693 4694 mc->no_parallel = 1; 4695 mc->default_boot_order = ""; 4696 mc->default_ram_size = 512 * MiB; 4697 mc->default_ram_id = "ppc_spapr.ram"; 4698 mc->default_display = "std"; 4699 mc->kvm_type = spapr_kvm_type; 4700 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4701 mc->pci_allow_0_address = true; 4702 assert(!mc->get_hotplug_handler); 4703 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4704 hc->pre_plug = spapr_machine_device_pre_plug; 4705 hc->plug = spapr_machine_device_plug; 4706 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4707 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4708 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4709 hc->unplug_request = spapr_machine_device_unplug_request; 4710 hc->unplug = spapr_machine_device_unplug; 4711 4712 smc->dr_lmb_enabled = true; 4713 smc->update_dt_enabled = true; 4714 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 4715 mc->has_hotpluggable_cpus = true; 4716 mc->nvdimm_supported = true; 4717 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4718 fwc->get_dev_path = spapr_get_fw_dev_path; 4719 nc->nmi_monitor_handler = spapr_nmi; 4720 smc->phb_placement = spapr_phb_placement; 4721 vhc->cpu_in_nested = spapr_cpu_in_nested; 4722 vhc->deliver_hv_excp = spapr_exit_nested; 4723 vhc->hypercall = emulate_spapr_hypercall; 4724 vhc->hpt_mask = spapr_hpt_mask; 4725 vhc->map_hptes = spapr_map_hptes; 4726 vhc->unmap_hptes = spapr_unmap_hptes; 4727 vhc->hpte_set_c = spapr_hpte_set_c; 4728 vhc->hpte_set_r = spapr_hpte_set_r; 4729 vhc->get_pate = spapr_get_pate; 4730 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4731 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4732 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4733 xic->ics_get = spapr_ics_get; 4734 xic->ics_resend = spapr_ics_resend; 4735 xic->icp_get = spapr_icp_get; 4736 ispc->print_info = spapr_pic_print_info; 4737 /* Force NUMA node memory size to be a multiple of 4738 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4739 * in which LMBs are represented and hot-added 4740 */ 4741 mc->numa_mem_align_shift = 28; 4742 mc->auto_enable_numa = true; 4743 4744 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4745 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4746 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4747 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4748 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4749 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4750 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4751 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4752 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4753 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4754 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4755 smc->default_caps.caps[SPAPR_CAP_RPT_INVALIDATE] = SPAPR_CAP_OFF; 4756 4757 /* 4758 * This cap specifies whether the AIL 3 mode for 4759 * H_SET_RESOURCE is supported. The default is modified 4760 * by default_caps_with_cpu(). 4761 */ 4762 smc->default_caps.caps[SPAPR_CAP_AIL_MODE_3] = SPAPR_CAP_ON; 4763 spapr_caps_add_properties(smc); 4764 smc->irq = &spapr_irq_dual; 4765 smc->dr_phb_enabled = true; 4766 smc->linux_pci_probe = true; 4767 smc->smp_threads_vsmt = true; 4768 smc->nr_xirqs = SPAPR_NR_XIRQS; 4769 xfc->match_nvt = spapr_match_nvt; 4770 vmc->client_architecture_support = spapr_vof_client_architecture_support; 4771 vmc->quiesce = spapr_vof_quiesce; 4772 vmc->setprop = spapr_vof_setprop; 4773 } 4774 4775 static const TypeInfo spapr_machine_info = { 4776 .name = TYPE_SPAPR_MACHINE, 4777 .parent = TYPE_MACHINE, 4778 .abstract = true, 4779 .instance_size = sizeof(SpaprMachineState), 4780 .instance_init = spapr_instance_init, 4781 .instance_finalize = spapr_machine_finalizefn, 4782 .class_size = sizeof(SpaprMachineClass), 4783 .class_init = spapr_machine_class_init, 4784 .interfaces = (InterfaceInfo[]) { 4785 { TYPE_FW_PATH_PROVIDER }, 4786 { TYPE_NMI }, 4787 { TYPE_HOTPLUG_HANDLER }, 4788 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4789 { TYPE_XICS_FABRIC }, 4790 { TYPE_INTERRUPT_STATS_PROVIDER }, 4791 { TYPE_XIVE_FABRIC }, 4792 { TYPE_VOF_MACHINE_IF }, 4793 { } 4794 }, 4795 }; 4796 4797 static void spapr_machine_latest_class_options(MachineClass *mc) 4798 { 4799 mc->alias = "pseries"; 4800 mc->is_default = true; 4801 } 4802 4803 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4804 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4805 void *data) \ 4806 { \ 4807 MachineClass *mc = MACHINE_CLASS(oc); \ 4808 spapr_machine_##suffix##_class_options(mc); \ 4809 if (latest) { \ 4810 spapr_machine_latest_class_options(mc); \ 4811 } \ 4812 } \ 4813 static const TypeInfo spapr_machine_##suffix##_info = { \ 4814 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4815 .parent = TYPE_SPAPR_MACHINE, \ 4816 .class_init = spapr_machine_##suffix##_class_init, \ 4817 }; \ 4818 static void spapr_machine_register_##suffix(void) \ 4819 { \ 4820 type_register(&spapr_machine_##suffix##_info); \ 4821 } \ 4822 type_init(spapr_machine_register_##suffix) 4823 4824 /* 4825 * pseries-9.0 4826 */ 4827 static void spapr_machine_9_0_class_options(MachineClass *mc) 4828 { 4829 /* Defaults for the latest behaviour inherited from the base class */ 4830 } 4831 4832 DEFINE_SPAPR_MACHINE(9_0, "9.0", true); 4833 4834 /* 4835 * pseries-8.2 4836 */ 4837 static void spapr_machine_8_2_class_options(MachineClass *mc) 4838 { 4839 spapr_machine_9_0_class_options(mc); 4840 compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len); 4841 } 4842 4843 DEFINE_SPAPR_MACHINE(8_2, "8.2", false); 4844 4845 /* 4846 * pseries-8.1 4847 */ 4848 static void spapr_machine_8_1_class_options(MachineClass *mc) 4849 { 4850 spapr_machine_8_2_class_options(mc); 4851 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len); 4852 } 4853 4854 DEFINE_SPAPR_MACHINE(8_1, "8.1", false); 4855 4856 /* 4857 * pseries-8.0 4858 */ 4859 static void spapr_machine_8_0_class_options(MachineClass *mc) 4860 { 4861 spapr_machine_8_1_class_options(mc); 4862 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len); 4863 } 4864 4865 DEFINE_SPAPR_MACHINE(8_0, "8.0", false); 4866 4867 /* 4868 * pseries-7.2 4869 */ 4870 static void spapr_machine_7_2_class_options(MachineClass *mc) 4871 { 4872 spapr_machine_8_0_class_options(mc); 4873 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len); 4874 } 4875 4876 DEFINE_SPAPR_MACHINE(7_2, "7.2", false); 4877 4878 /* 4879 * pseries-7.1 4880 */ 4881 static void spapr_machine_7_1_class_options(MachineClass *mc) 4882 { 4883 spapr_machine_7_2_class_options(mc); 4884 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 4885 } 4886 4887 DEFINE_SPAPR_MACHINE(7_1, "7.1", false); 4888 4889 /* 4890 * pseries-7.0 4891 */ 4892 static void spapr_machine_7_0_class_options(MachineClass *mc) 4893 { 4894 spapr_machine_7_1_class_options(mc); 4895 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 4896 } 4897 4898 DEFINE_SPAPR_MACHINE(7_0, "7.0", false); 4899 4900 /* 4901 * pseries-6.2 4902 */ 4903 static void spapr_machine_6_2_class_options(MachineClass *mc) 4904 { 4905 spapr_machine_7_0_class_options(mc); 4906 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 4907 } 4908 4909 DEFINE_SPAPR_MACHINE(6_2, "6.2", false); 4910 4911 /* 4912 * pseries-6.1 4913 */ 4914 static void spapr_machine_6_1_class_options(MachineClass *mc) 4915 { 4916 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4917 4918 spapr_machine_6_2_class_options(mc); 4919 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 4920 smc->pre_6_2_numa_affinity = true; 4921 mc->smp_props.prefer_sockets = true; 4922 } 4923 4924 DEFINE_SPAPR_MACHINE(6_1, "6.1", false); 4925 4926 /* 4927 * pseries-6.0 4928 */ 4929 static void spapr_machine_6_0_class_options(MachineClass *mc) 4930 { 4931 spapr_machine_6_1_class_options(mc); 4932 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 4933 } 4934 4935 DEFINE_SPAPR_MACHINE(6_0, "6.0", false); 4936 4937 /* 4938 * pseries-5.2 4939 */ 4940 static void spapr_machine_5_2_class_options(MachineClass *mc) 4941 { 4942 spapr_machine_6_0_class_options(mc); 4943 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 4944 } 4945 4946 DEFINE_SPAPR_MACHINE(5_2, "5.2", false); 4947 4948 /* 4949 * pseries-5.1 4950 */ 4951 static void spapr_machine_5_1_class_options(MachineClass *mc) 4952 { 4953 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4954 4955 spapr_machine_5_2_class_options(mc); 4956 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4957 smc->pre_5_2_numa_associativity = true; 4958 } 4959 4960 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4961 4962 /* 4963 * pseries-5.0 4964 */ 4965 static void spapr_machine_5_0_class_options(MachineClass *mc) 4966 { 4967 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4968 static GlobalProperty compat[] = { 4969 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4970 }; 4971 4972 spapr_machine_5_1_class_options(mc); 4973 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4974 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4975 mc->numa_mem_supported = true; 4976 smc->pre_5_1_assoc_refpoints = true; 4977 } 4978 4979 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4980 4981 /* 4982 * pseries-4.2 4983 */ 4984 static void spapr_machine_4_2_class_options(MachineClass *mc) 4985 { 4986 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4987 4988 spapr_machine_5_0_class_options(mc); 4989 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4990 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4991 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4992 smc->rma_limit = 16 * GiB; 4993 mc->nvdimm_supported = false; 4994 } 4995 4996 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4997 4998 /* 4999 * pseries-4.1 5000 */ 5001 static void spapr_machine_4_1_class_options(MachineClass *mc) 5002 { 5003 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5004 static GlobalProperty compat[] = { 5005 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 5006 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 5007 }; 5008 5009 spapr_machine_4_2_class_options(mc); 5010 smc->linux_pci_probe = false; 5011 smc->smp_threads_vsmt = false; 5012 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 5013 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5014 } 5015 5016 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 5017 5018 /* 5019 * pseries-4.0 5020 */ 5021 static bool phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 5022 uint64_t *buid, hwaddr *pio, 5023 hwaddr *mmio32, hwaddr *mmio64, 5024 unsigned n_dma, uint32_t *liobns, Error **errp) 5025 { 5026 if (!spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, 5027 liobns, errp)) { 5028 return false; 5029 } 5030 return true; 5031 } 5032 static void spapr_machine_4_0_class_options(MachineClass *mc) 5033 { 5034 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5035 5036 spapr_machine_4_1_class_options(mc); 5037 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 5038 smc->phb_placement = phb_placement_4_0; 5039 smc->irq = &spapr_irq_xics; 5040 smc->pre_4_1_migration = true; 5041 } 5042 5043 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 5044 5045 /* 5046 * pseries-3.1 5047 */ 5048 static void spapr_machine_3_1_class_options(MachineClass *mc) 5049 { 5050 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5051 5052 spapr_machine_4_0_class_options(mc); 5053 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 5054 5055 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 5056 smc->update_dt_enabled = false; 5057 smc->dr_phb_enabled = false; 5058 smc->broken_host_serial_model = true; 5059 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 5060 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 5061 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 5062 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 5063 } 5064 5065 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 5066 5067 /* 5068 * pseries-3.0 5069 */ 5070 5071 static void spapr_machine_3_0_class_options(MachineClass *mc) 5072 { 5073 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5074 5075 spapr_machine_3_1_class_options(mc); 5076 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 5077 5078 smc->legacy_irq_allocation = true; 5079 smc->nr_xirqs = 0x400; 5080 smc->irq = &spapr_irq_xics_legacy; 5081 } 5082 5083 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 5084 5085 /* 5086 * pseries-2.12 5087 */ 5088 static void spapr_machine_2_12_class_options(MachineClass *mc) 5089 { 5090 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5091 static GlobalProperty compat[] = { 5092 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 5093 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 5094 }; 5095 5096 spapr_machine_3_0_class_options(mc); 5097 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 5098 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5099 5100 /* We depend on kvm_enabled() to choose a default value for the 5101 * hpt-max-page-size capability. Of course we can't do it here 5102 * because this is too early and the HW accelerator isn't initialized 5103 * yet. Postpone this to machine init (see default_caps_with_cpu()). 5104 */ 5105 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 5106 } 5107 5108 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 5109 5110 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 5111 { 5112 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5113 5114 spapr_machine_2_12_class_options(mc); 5115 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 5116 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 5117 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 5118 } 5119 5120 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 5121 5122 /* 5123 * pseries-2.11 5124 */ 5125 5126 static void spapr_machine_2_11_class_options(MachineClass *mc) 5127 { 5128 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5129 5130 spapr_machine_2_12_class_options(mc); 5131 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 5132 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 5133 mc->deprecation_reason = "old and not maintained - use a 2.12+ version"; 5134 } 5135 5136 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 5137 5138 /* 5139 * pseries-2.10 5140 */ 5141 5142 static void spapr_machine_2_10_class_options(MachineClass *mc) 5143 { 5144 spapr_machine_2_11_class_options(mc); 5145 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 5146 } 5147 5148 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 5149 5150 /* 5151 * pseries-2.9 5152 */ 5153 5154 static void spapr_machine_2_9_class_options(MachineClass *mc) 5155 { 5156 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5157 static GlobalProperty compat[] = { 5158 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 5159 }; 5160 5161 spapr_machine_2_10_class_options(mc); 5162 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 5163 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5164 smc->pre_2_10_has_unused_icps = true; 5165 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 5166 } 5167 5168 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 5169 5170 /* 5171 * pseries-2.8 5172 */ 5173 5174 static void spapr_machine_2_8_class_options(MachineClass *mc) 5175 { 5176 static GlobalProperty compat[] = { 5177 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 5178 }; 5179 5180 spapr_machine_2_9_class_options(mc); 5181 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 5182 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5183 mc->numa_mem_align_shift = 23; 5184 } 5185 5186 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 5187 5188 /* 5189 * pseries-2.7 5190 */ 5191 5192 static bool phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 5193 uint64_t *buid, hwaddr *pio, 5194 hwaddr *mmio32, hwaddr *mmio64, 5195 unsigned n_dma, uint32_t *liobns, Error **errp) 5196 { 5197 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 5198 const uint64_t base_buid = 0x800000020000000ULL; 5199 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 5200 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 5201 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 5202 const uint32_t max_index = 255; 5203 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 5204 5205 uint64_t ram_top = MACHINE(spapr)->ram_size; 5206 hwaddr phb0_base, phb_base; 5207 int i; 5208 5209 /* Do we have device memory? */ 5210 if (MACHINE(spapr)->device_memory) { 5211 /* Can't just use maxram_size, because there may be an 5212 * alignment gap between normal and device memory regions 5213 */ 5214 ram_top = MACHINE(spapr)->device_memory->base + 5215 memory_region_size(&MACHINE(spapr)->device_memory->mr); 5216 } 5217 5218 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 5219 5220 if (index > max_index) { 5221 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 5222 max_index); 5223 return false; 5224 } 5225 5226 *buid = base_buid + index; 5227 for (i = 0; i < n_dma; ++i) { 5228 liobns[i] = SPAPR_PCI_LIOBN(index, i); 5229 } 5230 5231 phb_base = phb0_base + index * phb_spacing; 5232 *pio = phb_base + pio_offset; 5233 *mmio32 = phb_base + mmio_offset; 5234 /* 5235 * We don't set the 64-bit MMIO window, relying on the PHB's 5236 * fallback behaviour of automatically splitting a large "32-bit" 5237 * window into contiguous 32-bit and 64-bit windows 5238 */ 5239 5240 return true; 5241 } 5242 5243 static void spapr_machine_2_7_class_options(MachineClass *mc) 5244 { 5245 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5246 static GlobalProperty compat[] = { 5247 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 5248 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 5249 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 5250 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 5251 }; 5252 5253 spapr_machine_2_8_class_options(mc); 5254 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 5255 mc->default_machine_opts = "modern-hotplug-events=off"; 5256 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 5257 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5258 smc->phb_placement = phb_placement_2_7; 5259 } 5260 5261 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 5262 5263 /* 5264 * pseries-2.6 5265 */ 5266 5267 static void spapr_machine_2_6_class_options(MachineClass *mc) 5268 { 5269 static GlobalProperty compat[] = { 5270 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 5271 }; 5272 5273 spapr_machine_2_7_class_options(mc); 5274 mc->has_hotpluggable_cpus = false; 5275 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 5276 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5277 } 5278 5279 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 5280 5281 /* 5282 * pseries-2.5 5283 */ 5284 5285 static void spapr_machine_2_5_class_options(MachineClass *mc) 5286 { 5287 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5288 static GlobalProperty compat[] = { 5289 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 5290 }; 5291 5292 spapr_machine_2_6_class_options(mc); 5293 smc->use_ohci_by_default = true; 5294 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 5295 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5296 } 5297 5298 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 5299 5300 /* 5301 * pseries-2.4 5302 */ 5303 5304 static void spapr_machine_2_4_class_options(MachineClass *mc) 5305 { 5306 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5307 5308 spapr_machine_2_5_class_options(mc); 5309 smc->dr_lmb_enabled = false; 5310 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 5311 } 5312 5313 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 5314 5315 /* 5316 * pseries-2.3 5317 */ 5318 5319 static void spapr_machine_2_3_class_options(MachineClass *mc) 5320 { 5321 static GlobalProperty compat[] = { 5322 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 5323 }; 5324 spapr_machine_2_4_class_options(mc); 5325 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 5326 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5327 } 5328 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 5329 5330 /* 5331 * pseries-2.2 5332 */ 5333 5334 static void spapr_machine_2_2_class_options(MachineClass *mc) 5335 { 5336 static GlobalProperty compat[] = { 5337 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 5338 }; 5339 5340 spapr_machine_2_3_class_options(mc); 5341 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 5342 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5343 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 5344 } 5345 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 5346 5347 /* 5348 * pseries-2.1 5349 */ 5350 5351 static void spapr_machine_2_1_class_options(MachineClass *mc) 5352 { 5353 spapr_machine_2_2_class_options(mc); 5354 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 5355 } 5356 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 5357 5358 static void spapr_machine_register_types(void) 5359 { 5360 type_register_static(&spapr_machine_info); 5361 } 5362 5363 type_init(spapr_machine_register_types) 5364