xref: /openbmc/qemu/hw/ppc/spapr.c (revision 988717b46b6424907618cb845ace9d69062703af)
1  /*
2   * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3   *
4   * Copyright (c) 2004-2007 Fabrice Bellard
5   * Copyright (c) 2007 Jocelyn Mayer
6   * Copyright (c) 2010 David Gibson, IBM Corporation.
7   *
8   * Permission is hereby granted, free of charge, to any person obtaining a copy
9   * of this software and associated documentation files (the "Software"), to deal
10   * in the Software without restriction, including without limitation the rights
11   * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12   * copies of the Software, and to permit persons to whom the Software is
13   * furnished to do so, subject to the following conditions:
14   *
15   * The above copyright notice and this permission notice shall be included in
16   * all copies or substantial portions of the Software.
17   *
18   * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19   * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20   * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21   * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22   * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23   * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24   * THE SOFTWARE.
25   */
26  
27  #include "qemu/osdep.h"
28  #include "qemu-common.h"
29  #include "qapi/error.h"
30  #include "qapi/visitor.h"
31  #include "sysemu/sysemu.h"
32  #include "sysemu/hostmem.h"
33  #include "sysemu/numa.h"
34  #include "sysemu/qtest.h"
35  #include "sysemu/reset.h"
36  #include "sysemu/runstate.h"
37  #include "qemu/log.h"
38  #include "hw/fw-path-provider.h"
39  #include "elf.h"
40  #include "net/net.h"
41  #include "sysemu/device_tree.h"
42  #include "sysemu/cpus.h"
43  #include "sysemu/hw_accel.h"
44  #include "kvm_ppc.h"
45  #include "migration/misc.h"
46  #include "migration/qemu-file-types.h"
47  #include "migration/global_state.h"
48  #include "migration/register.h"
49  #include "migration/blocker.h"
50  #include "mmu-hash64.h"
51  #include "mmu-book3s-v3.h"
52  #include "cpu-models.h"
53  #include "hw/core/cpu.h"
54  
55  #include "hw/boards.h"
56  #include "hw/ppc/ppc.h"
57  #include "hw/loader.h"
58  
59  #include "hw/ppc/fdt.h"
60  #include "hw/ppc/spapr.h"
61  #include "hw/ppc/spapr_vio.h"
62  #include "hw/qdev-properties.h"
63  #include "hw/pci-host/spapr.h"
64  #include "hw/pci/msi.h"
65  
66  #include "hw/pci/pci.h"
67  #include "hw/scsi/scsi.h"
68  #include "hw/virtio/virtio-scsi.h"
69  #include "hw/virtio/vhost-scsi-common.h"
70  
71  #include "exec/address-spaces.h"
72  #include "exec/ram_addr.h"
73  #include "hw/usb.h"
74  #include "qemu/config-file.h"
75  #include "qemu/error-report.h"
76  #include "trace.h"
77  #include "hw/nmi.h"
78  #include "hw/intc/intc.h"
79  
80  #include "hw/ppc/spapr_cpu_core.h"
81  #include "hw/mem/memory-device.h"
82  #include "hw/ppc/spapr_tpm_proxy.h"
83  
84  #include "monitor/monitor.h"
85  
86  #include <libfdt.h>
87  
88  /* SLOF memory layout:
89   *
90   * SLOF raw image loaded at 0, copies its romfs right below the flat
91   * device-tree, then position SLOF itself 31M below that
92   *
93   * So we set FW_OVERHEAD to 40MB which should account for all of that
94   * and more
95   *
96   * We load our kernel at 4M, leaving space for SLOF initial image
97   */
98  #define FDT_MAX_SIZE            0x100000
99  #define RTAS_MAX_ADDR           0x80000000 /* RTAS must stay below that */
100  #define FW_MAX_SIZE             0x400000
101  #define FW_FILE_NAME            "slof.bin"
102  #define FW_OVERHEAD             0x2800000
103  #define KERNEL_LOAD_ADDR        FW_MAX_SIZE
104  
105  #define MIN_RMA_SLOF            128UL
106  
107  #define PHANDLE_INTC            0x00001111
108  
109  /* These two functions implement the VCPU id numbering: one to compute them
110   * all and one to identify thread 0 of a VCORE. Any change to the first one
111   * is likely to have an impact on the second one, so let's keep them close.
112   */
113  static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index)
114  {
115      MachineState *ms = MACHINE(spapr);
116      unsigned int smp_threads = ms->smp.threads;
117  
118      assert(spapr->vsmt);
119      return
120          (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads;
121  }
122  static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr,
123                                        PowerPCCPU *cpu)
124  {
125      assert(spapr->vsmt);
126      return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0;
127  }
128  
129  static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque)
130  {
131      /* Dummy entries correspond to unused ICPState objects in older QEMUs,
132       * and newer QEMUs don't even have them. In both cases, we don't want
133       * to send anything on the wire.
134       */
135      return false;
136  }
137  
138  static const VMStateDescription pre_2_10_vmstate_dummy_icp = {
139      .name = "icp/server",
140      .version_id = 1,
141      .minimum_version_id = 1,
142      .needed = pre_2_10_vmstate_dummy_icp_needed,
143      .fields = (VMStateField[]) {
144          VMSTATE_UNUSED(4), /* uint32_t xirr */
145          VMSTATE_UNUSED(1), /* uint8_t pending_priority */
146          VMSTATE_UNUSED(1), /* uint8_t mfrr */
147          VMSTATE_END_OF_LIST()
148      },
149  };
150  
151  static void pre_2_10_vmstate_register_dummy_icp(int i)
152  {
153      vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp,
154                       (void *)(uintptr_t) i);
155  }
156  
157  static void pre_2_10_vmstate_unregister_dummy_icp(int i)
158  {
159      vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp,
160                         (void *)(uintptr_t) i);
161  }
162  
163  int spapr_max_server_number(SpaprMachineState *spapr)
164  {
165      MachineState *ms = MACHINE(spapr);
166  
167      assert(spapr->vsmt);
168      return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads);
169  }
170  
171  static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
172                                    int smt_threads)
173  {
174      int i, ret = 0;
175      uint32_t servers_prop[smt_threads];
176      uint32_t gservers_prop[smt_threads * 2];
177      int index = spapr_get_vcpu_id(cpu);
178  
179      if (cpu->compat_pvr) {
180          ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
181          if (ret < 0) {
182              return ret;
183          }
184      }
185  
186      /* Build interrupt servers and gservers properties */
187      for (i = 0; i < smt_threads; i++) {
188          servers_prop[i] = cpu_to_be32(index + i);
189          /* Hack, direct the group queues back to cpu 0 */
190          gservers_prop[i*2] = cpu_to_be32(index + i);
191          gservers_prop[i*2 + 1] = 0;
192      }
193      ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
194                        servers_prop, sizeof(servers_prop));
195      if (ret < 0) {
196          return ret;
197      }
198      ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
199                        gservers_prop, sizeof(gservers_prop));
200  
201      return ret;
202  }
203  
204  static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu)
205  {
206      int index = spapr_get_vcpu_id(cpu);
207      uint32_t associativity[] = {cpu_to_be32(0x5),
208                                  cpu_to_be32(0x0),
209                                  cpu_to_be32(0x0),
210                                  cpu_to_be32(0x0),
211                                  cpu_to_be32(cpu->node_id),
212                                  cpu_to_be32(index)};
213  
214      /* Advertise NUMA via ibm,associativity */
215      return fdt_setprop(fdt, offset, "ibm,associativity", associativity,
216                            sizeof(associativity));
217  }
218  
219  /* Populate the "ibm,pa-features" property */
220  static void spapr_populate_pa_features(SpaprMachineState *spapr,
221                                         PowerPCCPU *cpu,
222                                         void *fdt, int offset)
223  {
224      uint8_t pa_features_206[] = { 6, 0,
225          0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
226      uint8_t pa_features_207[] = { 24, 0,
227          0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
228          0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
229          0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
230          0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
231      uint8_t pa_features_300[] = { 66, 0,
232          /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
233          /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
234          0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
235          /* 6: DS207 */
236          0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
237          /* 16: Vector */
238          0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
239          /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
240          0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
241          /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
242          0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
243          /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
244          0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
245          /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
246          0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
247          /* 42: PM, 44: PC RA, 46: SC vec'd */
248          0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
249          /* 48: SIMD, 50: QP BFP, 52: String */
250          0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
251          /* 54: DecFP, 56: DecI, 58: SHA */
252          0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
253          /* 60: NM atomic, 62: RNG */
254          0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
255      };
256      uint8_t *pa_features = NULL;
257      size_t pa_size;
258  
259      if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) {
260          pa_features = pa_features_206;
261          pa_size = sizeof(pa_features_206);
262      }
263      if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) {
264          pa_features = pa_features_207;
265          pa_size = sizeof(pa_features_207);
266      }
267      if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) {
268          pa_features = pa_features_300;
269          pa_size = sizeof(pa_features_300);
270      }
271      if (!pa_features) {
272          return;
273      }
274  
275      if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
276          /*
277           * Note: we keep CI large pages off by default because a 64K capable
278           * guest provisioned with large pages might otherwise try to map a qemu
279           * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
280           * even if that qemu runs on a 4k host.
281           * We dd this bit back here if we are confident this is not an issue
282           */
283          pa_features[3] |= 0x20;
284      }
285      if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) {
286          pa_features[24] |= 0x80;    /* Transactional memory support */
287      }
288      if (spapr->cas_pre_isa3_guest && pa_size > 40) {
289          /* Workaround for broken kernels that attempt (guest) radix
290           * mode when they can't handle it, if they see the radix bit set
291           * in pa-features. So hide it from them. */
292          pa_features[40 + 2] &= ~0x80; /* Radix MMU */
293      }
294  
295      _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
296  }
297  
298  static hwaddr spapr_node0_size(MachineState *machine)
299  {
300      if (machine->numa_state->num_nodes) {
301          int i;
302          for (i = 0; i < machine->numa_state->num_nodes; ++i) {
303              if (machine->numa_state->nodes[i].node_mem) {
304                  return MIN(pow2floor(machine->numa_state->nodes[i].node_mem),
305                             machine->ram_size);
306              }
307          }
308      }
309      return machine->ram_size;
310  }
311  
312  static void add_str(GString *s, const gchar *s1)
313  {
314      g_string_append_len(s, s1, strlen(s1) + 1);
315  }
316  
317  static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
318                                         hwaddr size)
319  {
320      uint32_t associativity[] = {
321          cpu_to_be32(0x4), /* length */
322          cpu_to_be32(0x0), cpu_to_be32(0x0),
323          cpu_to_be32(0x0), cpu_to_be32(nodeid)
324      };
325      char mem_name[32];
326      uint64_t mem_reg_property[2];
327      int off;
328  
329      mem_reg_property[0] = cpu_to_be64(start);
330      mem_reg_property[1] = cpu_to_be64(size);
331  
332      sprintf(mem_name, "memory@%" HWADDR_PRIx, start);
333      off = fdt_add_subnode(fdt, 0, mem_name);
334      _FDT(off);
335      _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
336      _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
337                        sizeof(mem_reg_property))));
338      _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
339                        sizeof(associativity))));
340      return off;
341  }
342  
343  static int spapr_populate_memory(SpaprMachineState *spapr, void *fdt)
344  {
345      MachineState *machine = MACHINE(spapr);
346      hwaddr mem_start, node_size;
347      int i, nb_nodes = machine->numa_state->num_nodes;
348      NodeInfo *nodes = machine->numa_state->nodes;
349  
350      for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
351          if (!nodes[i].node_mem) {
352              continue;
353          }
354          if (mem_start >= machine->ram_size) {
355              node_size = 0;
356          } else {
357              node_size = nodes[i].node_mem;
358              if (node_size > machine->ram_size - mem_start) {
359                  node_size = machine->ram_size - mem_start;
360              }
361          }
362          if (!mem_start) {
363              /* spapr_machine_init() checks for rma_size <= node0_size
364               * already */
365              spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
366              mem_start += spapr->rma_size;
367              node_size -= spapr->rma_size;
368          }
369          for ( ; node_size; ) {
370              hwaddr sizetmp = pow2floor(node_size);
371  
372              /* mem_start != 0 here */
373              if (ctzl(mem_start) < ctzl(sizetmp)) {
374                  sizetmp = 1ULL << ctzl(mem_start);
375              }
376  
377              spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
378              node_size -= sizetmp;
379              mem_start += sizetmp;
380          }
381      }
382  
383      return 0;
384  }
385  
386  static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
387                                    SpaprMachineState *spapr)
388  {
389      MachineState *ms = MACHINE(spapr);
390      PowerPCCPU *cpu = POWERPC_CPU(cs);
391      CPUPPCState *env = &cpu->env;
392      PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
393      int index = spapr_get_vcpu_id(cpu);
394      uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
395                         0xffffffff, 0xffffffff};
396      uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
397          : SPAPR_TIMEBASE_FREQ;
398      uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
399      uint32_t page_sizes_prop[64];
400      size_t page_sizes_prop_size;
401      unsigned int smp_threads = ms->smp.threads;
402      uint32_t vcpus_per_socket = smp_threads * ms->smp.cores;
403      uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
404      int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
405      SpaprDrc *drc;
406      int drc_index;
407      uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
408      int i;
409  
410      drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index);
411      if (drc) {
412          drc_index = spapr_drc_index(drc);
413          _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
414      }
415  
416      _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
417      _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
418  
419      _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
420      _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
421                             env->dcache_line_size)));
422      _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
423                             env->dcache_line_size)));
424      _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
425                             env->icache_line_size)));
426      _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
427                             env->icache_line_size)));
428  
429      if (pcc->l1_dcache_size) {
430          _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
431                                 pcc->l1_dcache_size)));
432      } else {
433          warn_report("Unknown L1 dcache size for cpu");
434      }
435      if (pcc->l1_icache_size) {
436          _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
437                                 pcc->l1_icache_size)));
438      } else {
439          warn_report("Unknown L1 icache size for cpu");
440      }
441  
442      _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
443      _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
444      _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size)));
445      _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size)));
446      _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
447      _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
448  
449      if (env->spr_cb[SPR_PURR].oea_read) {
450          _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1)));
451      }
452      if (env->spr_cb[SPR_SPURR].oea_read) {
453          _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1)));
454      }
455  
456      if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
457          _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
458                            segs, sizeof(segs))));
459      }
460  
461      /* Advertise VSX (vector extensions) if available
462       *   1               == VMX / Altivec available
463       *   2               == VSX available
464       *
465       * Only CPUs for which we create core types in spapr_cpu_core.c
466       * are possible, and all of those have VMX */
467      if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) {
468          _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2)));
469      } else {
470          _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1)));
471      }
472  
473      /* Advertise DFP (Decimal Floating Point) if available
474       *   0 / no property == no DFP
475       *   1               == DFP available */
476      if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) {
477          _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
478      }
479  
480      page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
481                                                        sizeof(page_sizes_prop));
482      if (page_sizes_prop_size) {
483          _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
484                            page_sizes_prop, page_sizes_prop_size)));
485      }
486  
487      spapr_populate_pa_features(spapr, cpu, fdt, offset);
488  
489      _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
490                             cs->cpu_index / vcpus_per_socket)));
491  
492      _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
493                        pft_size_prop, sizeof(pft_size_prop))));
494  
495      if (ms->numa_state->num_nodes > 1) {
496          _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu));
497      }
498  
499      _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
500  
501      if (pcc->radix_page_info) {
502          for (i = 0; i < pcc->radix_page_info->count; i++) {
503              radix_AP_encodings[i] =
504                  cpu_to_be32(pcc->radix_page_info->entries[i]);
505          }
506          _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings",
507                            radix_AP_encodings,
508                            pcc->radix_page_info->count *
509                            sizeof(radix_AP_encodings[0]))));
510      }
511  
512      /*
513       * We set this property to let the guest know that it can use the large
514       * decrementer and its width in bits.
515       */
516      if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF)
517          _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits",
518                                pcc->lrg_decr_bits)));
519  }
520  
521  static void spapr_populate_cpus_dt_node(void *fdt, SpaprMachineState *spapr)
522  {
523      CPUState **rev;
524      CPUState *cs;
525      int n_cpus;
526      int cpus_offset;
527      char *nodename;
528      int i;
529  
530      cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
531      _FDT(cpus_offset);
532      _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
533      _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
534  
535      /*
536       * We walk the CPUs in reverse order to ensure that CPU DT nodes
537       * created by fdt_add_subnode() end up in the right order in FDT
538       * for the guest kernel the enumerate the CPUs correctly.
539       *
540       * The CPU list cannot be traversed in reverse order, so we need
541       * to do extra work.
542       */
543      n_cpus = 0;
544      rev = NULL;
545      CPU_FOREACH(cs) {
546          rev = g_renew(CPUState *, rev, n_cpus + 1);
547          rev[n_cpus++] = cs;
548      }
549  
550      for (i = n_cpus - 1; i >= 0; i--) {
551          CPUState *cs = rev[i];
552          PowerPCCPU *cpu = POWERPC_CPU(cs);
553          int index = spapr_get_vcpu_id(cpu);
554          DeviceClass *dc = DEVICE_GET_CLASS(cs);
555          int offset;
556  
557          if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
558              continue;
559          }
560  
561          nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
562          offset = fdt_add_subnode(fdt, cpus_offset, nodename);
563          g_free(nodename);
564          _FDT(offset);
565          spapr_populate_cpu_dt(cs, fdt, offset, spapr);
566      }
567  
568      g_free(rev);
569  }
570  
571  static int spapr_rng_populate_dt(void *fdt)
572  {
573      int node;
574      int ret;
575  
576      node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities");
577      if (node <= 0) {
578          return -1;
579      }
580      ret = fdt_setprop_string(fdt, node, "device_type",
581                               "ibm,platform-facilities");
582      ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1);
583      ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0);
584  
585      node = fdt_add_subnode(fdt, node, "ibm,random-v1");
586      if (node <= 0) {
587          return -1;
588      }
589      ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random");
590  
591      return ret ? -1 : 0;
592  }
593  
594  static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr)
595  {
596      MemoryDeviceInfoList *info;
597  
598      for (info = list; info; info = info->next) {
599          MemoryDeviceInfo *value = info->value;
600  
601          if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) {
602              PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data;
603  
604              if (addr >= pcdimm_info->addr &&
605                  addr < (pcdimm_info->addr + pcdimm_info->size)) {
606                  return pcdimm_info->node;
607              }
608          }
609      }
610  
611      return -1;
612  }
613  
614  struct sPAPRDrconfCellV2 {
615       uint32_t seq_lmbs;
616       uint64_t base_addr;
617       uint32_t drc_index;
618       uint32_t aa_index;
619       uint32_t flags;
620  } QEMU_PACKED;
621  
622  typedef struct DrconfCellQueue {
623      struct sPAPRDrconfCellV2 cell;
624      QSIMPLEQ_ENTRY(DrconfCellQueue) entry;
625  } DrconfCellQueue;
626  
627  static DrconfCellQueue *
628  spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr,
629                        uint32_t drc_index, uint32_t aa_index,
630                        uint32_t flags)
631  {
632      DrconfCellQueue *elem;
633  
634      elem = g_malloc0(sizeof(*elem));
635      elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs);
636      elem->cell.base_addr = cpu_to_be64(base_addr);
637      elem->cell.drc_index = cpu_to_be32(drc_index);
638      elem->cell.aa_index = cpu_to_be32(aa_index);
639      elem->cell.flags = cpu_to_be32(flags);
640  
641      return elem;
642  }
643  
644  /* ibm,dynamic-memory-v2 */
645  static int spapr_populate_drmem_v2(SpaprMachineState *spapr, void *fdt,
646                                     int offset, MemoryDeviceInfoList *dimms)
647  {
648      MachineState *machine = MACHINE(spapr);
649      uint8_t *int_buf, *cur_index;
650      int ret;
651      uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
652      uint64_t addr, cur_addr, size;
653      uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size);
654      uint64_t mem_end = machine->device_memory->base +
655                         memory_region_size(&machine->device_memory->mr);
656      uint32_t node, buf_len, nr_entries = 0;
657      SpaprDrc *drc;
658      DrconfCellQueue *elem, *next;
659      MemoryDeviceInfoList *info;
660      QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue
661          = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue);
662  
663      /* Entry to cover RAM and the gap area */
664      elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1,
665                                   SPAPR_LMB_FLAGS_RESERVED |
666                                   SPAPR_LMB_FLAGS_DRC_INVALID);
667      QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
668      nr_entries++;
669  
670      cur_addr = machine->device_memory->base;
671      for (info = dimms; info; info = info->next) {
672          PCDIMMDeviceInfo *di = info->value->u.dimm.data;
673  
674          addr = di->addr;
675          size = di->size;
676          node = di->node;
677  
678          /* Entry for hot-pluggable area */
679          if (cur_addr < addr) {
680              drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
681              g_assert(drc);
682              elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size,
683                                           cur_addr, spapr_drc_index(drc), -1, 0);
684              QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
685              nr_entries++;
686          }
687  
688          /* Entry for DIMM */
689          drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size);
690          g_assert(drc);
691          elem = spapr_get_drconf_cell(size / lmb_size, addr,
692                                       spapr_drc_index(drc), node,
693                                       SPAPR_LMB_FLAGS_ASSIGNED);
694          QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
695          nr_entries++;
696          cur_addr = addr + size;
697      }
698  
699      /* Entry for remaining hotpluggable area */
700      if (cur_addr < mem_end) {
701          drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
702          g_assert(drc);
703          elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size,
704                                       cur_addr, spapr_drc_index(drc), -1, 0);
705          QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
706          nr_entries++;
707      }
708  
709      buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t);
710      int_buf = cur_index = g_malloc0(buf_len);
711      *(uint32_t *)int_buf = cpu_to_be32(nr_entries);
712      cur_index += sizeof(nr_entries);
713  
714      QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) {
715          memcpy(cur_index, &elem->cell, sizeof(elem->cell));
716          cur_index += sizeof(elem->cell);
717          QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry);
718          g_free(elem);
719      }
720  
721      ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len);
722      g_free(int_buf);
723      if (ret < 0) {
724          return -1;
725      }
726      return 0;
727  }
728  
729  /* ibm,dynamic-memory */
730  static int spapr_populate_drmem_v1(SpaprMachineState *spapr, void *fdt,
731                                     int offset, MemoryDeviceInfoList *dimms)
732  {
733      MachineState *machine = MACHINE(spapr);
734      int i, ret;
735      uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
736      uint32_t device_lmb_start = machine->device_memory->base / lmb_size;
737      uint32_t nr_lmbs = (machine->device_memory->base +
738                         memory_region_size(&machine->device_memory->mr)) /
739                         lmb_size;
740      uint32_t *int_buf, *cur_index, buf_len;
741  
742      /*
743       * Allocate enough buffer size to fit in ibm,dynamic-memory
744       */
745      buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t);
746      cur_index = int_buf = g_malloc0(buf_len);
747      int_buf[0] = cpu_to_be32(nr_lmbs);
748      cur_index++;
749      for (i = 0; i < nr_lmbs; i++) {
750          uint64_t addr = i * lmb_size;
751          uint32_t *dynamic_memory = cur_index;
752  
753          if (i >= device_lmb_start) {
754              SpaprDrc *drc;
755  
756              drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i);
757              g_assert(drc);
758  
759              dynamic_memory[0] = cpu_to_be32(addr >> 32);
760              dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
761              dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc));
762              dynamic_memory[3] = cpu_to_be32(0); /* reserved */
763              dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr));
764              if (memory_region_present(get_system_memory(), addr)) {
765                  dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
766              } else {
767                  dynamic_memory[5] = cpu_to_be32(0);
768              }
769          } else {
770              /*
771               * LMB information for RMA, boot time RAM and gap b/n RAM and
772               * device memory region -- all these are marked as reserved
773               * and as having no valid DRC.
774               */
775              dynamic_memory[0] = cpu_to_be32(addr >> 32);
776              dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
777              dynamic_memory[2] = cpu_to_be32(0);
778              dynamic_memory[3] = cpu_to_be32(0); /* reserved */
779              dynamic_memory[4] = cpu_to_be32(-1);
780              dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
781                                              SPAPR_LMB_FLAGS_DRC_INVALID);
782          }
783  
784          cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
785      }
786      ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
787      g_free(int_buf);
788      if (ret < 0) {
789          return -1;
790      }
791      return 0;
792  }
793  
794  /*
795   * Adds ibm,dynamic-reconfiguration-memory node.
796   * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
797   * of this device tree node.
798   */
799  static int spapr_populate_drconf_memory(SpaprMachineState *spapr, void *fdt)
800  {
801      MachineState *machine = MACHINE(spapr);
802      int nb_numa_nodes = machine->numa_state->num_nodes;
803      int ret, i, offset;
804      uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
805      uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
806      uint32_t *int_buf, *cur_index, buf_len;
807      int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
808      MemoryDeviceInfoList *dimms = NULL;
809  
810      /*
811       * Don't create the node if there is no device memory
812       */
813      if (machine->ram_size == machine->maxram_size) {
814          return 0;
815      }
816  
817      offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
818  
819      ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
820                      sizeof(prop_lmb_size));
821      if (ret < 0) {
822          return ret;
823      }
824  
825      ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
826      if (ret < 0) {
827          return ret;
828      }
829  
830      ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
831      if (ret < 0) {
832          return ret;
833      }
834  
835      /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
836      dimms = qmp_memory_device_list();
837      if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) {
838          ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms);
839      } else {
840          ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms);
841      }
842      qapi_free_MemoryDeviceInfoList(dimms);
843  
844      if (ret < 0) {
845          return ret;
846      }
847  
848      /* ibm,associativity-lookup-arrays */
849      buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t);
850      cur_index = int_buf = g_malloc0(buf_len);
851      int_buf[0] = cpu_to_be32(nr_nodes);
852      int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
853      cur_index += 2;
854      for (i = 0; i < nr_nodes; i++) {
855          uint32_t associativity[] = {
856              cpu_to_be32(0x0),
857              cpu_to_be32(0x0),
858              cpu_to_be32(0x0),
859              cpu_to_be32(i)
860          };
861          memcpy(cur_index, associativity, sizeof(associativity));
862          cur_index += 4;
863      }
864      ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
865              (cur_index - int_buf) * sizeof(uint32_t));
866      g_free(int_buf);
867  
868      return ret;
869  }
870  
871  static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt,
872                                  SpaprOptionVector *ov5_updates)
873  {
874      SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
875      int ret = 0, offset;
876  
877      /* Generate ibm,dynamic-reconfiguration-memory node if required */
878      if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
879          g_assert(smc->dr_lmb_enabled);
880          ret = spapr_populate_drconf_memory(spapr, fdt);
881          if (ret) {
882              return ret;
883          }
884      }
885  
886      offset = fdt_path_offset(fdt, "/chosen");
887      if (offset < 0) {
888          offset = fdt_add_subnode(fdt, 0, "chosen");
889          if (offset < 0) {
890              return offset;
891          }
892      }
893      return spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
894                                    "ibm,architecture-vec-5");
895  }
896  
897  static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt)
898  {
899      MachineState *ms = MACHINE(spapr);
900      int rtas;
901      GString *hypertas = g_string_sized_new(256);
902      GString *qemu_hypertas = g_string_sized_new(256);
903      uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
904      uint64_t max_device_addr = MACHINE(spapr)->device_memory->base +
905          memory_region_size(&MACHINE(spapr)->device_memory->mr);
906      uint32_t lrdr_capacity[] = {
907          cpu_to_be32(max_device_addr >> 32),
908          cpu_to_be32(max_device_addr & 0xffffffff),
909          0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
910          cpu_to_be32(ms->smp.max_cpus / ms->smp.threads),
911      };
912      uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0);
913      uint32_t maxdomains[] = {
914          cpu_to_be32(4),
915          maxdomain,
916          maxdomain,
917          maxdomain,
918          cpu_to_be32(spapr->gpu_numa_id),
919      };
920  
921      _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
922  
923      /* hypertas */
924      add_str(hypertas, "hcall-pft");
925      add_str(hypertas, "hcall-term");
926      add_str(hypertas, "hcall-dabr");
927      add_str(hypertas, "hcall-interrupt");
928      add_str(hypertas, "hcall-tce");
929      add_str(hypertas, "hcall-vio");
930      add_str(hypertas, "hcall-splpar");
931      add_str(hypertas, "hcall-join");
932      add_str(hypertas, "hcall-bulk");
933      add_str(hypertas, "hcall-set-mode");
934      add_str(hypertas, "hcall-sprg0");
935      add_str(hypertas, "hcall-copy");
936      add_str(hypertas, "hcall-debug");
937      add_str(hypertas, "hcall-vphn");
938      add_str(qemu_hypertas, "hcall-memop1");
939  
940      if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
941          add_str(hypertas, "hcall-multi-tce");
942      }
943  
944      if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
945          add_str(hypertas, "hcall-hpt-resize");
946      }
947  
948      _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
949                       hypertas->str, hypertas->len));
950      g_string_free(hypertas, TRUE);
951      _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
952                       qemu_hypertas->str, qemu_hypertas->len));
953      g_string_free(qemu_hypertas, TRUE);
954  
955      _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
956                       refpoints, sizeof(refpoints)));
957  
958      _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains",
959                       maxdomains, sizeof(maxdomains)));
960  
961      _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
962                            RTAS_ERROR_LOG_MAX));
963      _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
964                            RTAS_EVENT_SCAN_RATE));
965  
966      g_assert(msi_nonbroken);
967      _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
968  
969      /*
970       * According to PAPR, rtas ibm,os-term does not guarantee a return
971       * back to the guest cpu.
972       *
973       * While an additional ibm,extended-os-term property indicates
974       * that rtas call return will always occur. Set this property.
975       */
976      _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
977  
978      _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
979                       lrdr_capacity, sizeof(lrdr_capacity)));
980  
981      spapr_dt_rtas_tokens(fdt, rtas);
982  }
983  
984  /*
985   * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU
986   * and the XIVE features that the guest may request and thus the valid
987   * values for bytes 23..26 of option vector 5:
988   */
989  static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt,
990                                            int chosen)
991  {
992      PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
993  
994      char val[2 * 4] = {
995          23, 0x00, /* XICS / XIVE mode */
996          24, 0x00, /* Hash/Radix, filled in below. */
997          25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
998          26, 0x40, /* Radix options: GTSE == yes. */
999      };
1000  
1001      if (spapr->irq->xics && spapr->irq->xive) {
1002          val[1] = SPAPR_OV5_XIVE_BOTH;
1003      } else if (spapr->irq->xive) {
1004          val[1] = SPAPR_OV5_XIVE_EXPLOIT;
1005      } else {
1006          assert(spapr->irq->xics);
1007          val[1] = SPAPR_OV5_XIVE_LEGACY;
1008      }
1009  
1010      if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
1011                            first_ppc_cpu->compat_pvr)) {
1012          /*
1013           * If we're in a pre POWER9 compat mode then the guest should
1014           * do hash and use the legacy interrupt mode
1015           */
1016          val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */
1017          val[3] = 0x00; /* Hash */
1018      } else if (kvm_enabled()) {
1019          if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
1020              val[3] = 0x80; /* OV5_MMU_BOTH */
1021          } else if (kvmppc_has_cap_mmu_radix()) {
1022              val[3] = 0x40; /* OV5_MMU_RADIX_300 */
1023          } else {
1024              val[3] = 0x00; /* Hash */
1025          }
1026      } else {
1027          /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
1028          val[3] = 0xC0;
1029      }
1030      _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
1031                       val, sizeof(val)));
1032  }
1033  
1034  static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt)
1035  {
1036      MachineState *machine = MACHINE(spapr);
1037      SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1038      int chosen;
1039      const char *boot_device = machine->boot_order;
1040      char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
1041      size_t cb = 0;
1042      char *bootlist = get_boot_devices_list(&cb);
1043  
1044      _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
1045  
1046      if (machine->kernel_cmdline && machine->kernel_cmdline[0]) {
1047          _FDT(fdt_setprop_string(fdt, chosen, "bootargs",
1048                                  machine->kernel_cmdline));
1049      }
1050      if (spapr->initrd_size) {
1051          _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
1052                                spapr->initrd_base));
1053          _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
1054                                spapr->initrd_base + spapr->initrd_size));
1055      }
1056  
1057      if (spapr->kernel_size) {
1058          uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
1059                                cpu_to_be64(spapr->kernel_size) };
1060  
1061          _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
1062                           &kprop, sizeof(kprop)));
1063          if (spapr->kernel_le) {
1064              _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
1065          }
1066      }
1067      if (boot_menu) {
1068          _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
1069      }
1070      _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
1071      _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
1072      _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
1073  
1074      if (cb && bootlist) {
1075          int i;
1076  
1077          for (i = 0; i < cb; i++) {
1078              if (bootlist[i] == '\n') {
1079                  bootlist[i] = ' ';
1080              }
1081          }
1082          _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
1083      }
1084  
1085      if (boot_device && strlen(boot_device)) {
1086          _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
1087      }
1088  
1089      if (!spapr->has_graphics && stdout_path) {
1090          /*
1091           * "linux,stdout-path" and "stdout" properties are deprecated by linux
1092           * kernel. New platforms should only use the "stdout-path" property. Set
1093           * the new property and continue using older property to remain
1094           * compatible with the existing firmware.
1095           */
1096          _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
1097          _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path));
1098      }
1099  
1100      /* We can deal with BAR reallocation just fine, advertise it to the guest */
1101      if (smc->linux_pci_probe) {
1102          _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0));
1103      }
1104  
1105      spapr_dt_ov5_platform_support(spapr, fdt, chosen);
1106  
1107      g_free(stdout_path);
1108      g_free(bootlist);
1109  }
1110  
1111  static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt)
1112  {
1113      /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1114       * KVM to work under pHyp with some guest co-operation */
1115      int hypervisor;
1116      uint8_t hypercall[16];
1117  
1118      _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
1119      /* indicate KVM hypercall interface */
1120      _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
1121      if (kvmppc_has_cap_fixup_hcalls()) {
1122          /*
1123           * Older KVM versions with older guest kernels were broken
1124           * with the magic page, don't allow the guest to map it.
1125           */
1126          if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
1127                                    sizeof(hypercall))) {
1128              _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
1129                               hypercall, sizeof(hypercall)));
1130          }
1131      }
1132  }
1133  
1134  void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space)
1135  {
1136      MachineState *machine = MACHINE(spapr);
1137      MachineClass *mc = MACHINE_GET_CLASS(machine);
1138      SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1139      int ret;
1140      void *fdt;
1141      SpaprPhbState *phb;
1142      char *buf;
1143  
1144      fdt = g_malloc0(space);
1145      _FDT((fdt_create_empty_tree(fdt, space)));
1146  
1147      /* Root node */
1148      _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
1149      _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
1150      _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
1151  
1152      /* Guest UUID & Name*/
1153      buf = qemu_uuid_unparse_strdup(&qemu_uuid);
1154      _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
1155      if (qemu_uuid_set) {
1156          _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
1157      }
1158      g_free(buf);
1159  
1160      if (qemu_get_vm_name()) {
1161          _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
1162                                  qemu_get_vm_name()));
1163      }
1164  
1165      /* Host Model & Serial Number */
1166      if (spapr->host_model) {
1167          _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model));
1168      } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) {
1169          _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
1170          g_free(buf);
1171      }
1172  
1173      if (spapr->host_serial) {
1174          _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial));
1175      } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) {
1176          _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
1177          g_free(buf);
1178      }
1179  
1180      _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
1181      _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
1182  
1183      /* /interrupt controller */
1184      spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC);
1185  
1186      ret = spapr_populate_memory(spapr, fdt);
1187      if (ret < 0) {
1188          error_report("couldn't setup memory nodes in fdt");
1189          exit(1);
1190      }
1191  
1192      /* /vdevice */
1193      spapr_dt_vdevice(spapr->vio_bus, fdt);
1194  
1195      if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
1196          ret = spapr_rng_populate_dt(fdt);
1197          if (ret < 0) {
1198              error_report("could not set up rng device in the fdt");
1199              exit(1);
1200          }
1201      }
1202  
1203      QLIST_FOREACH(phb, &spapr->phbs, list) {
1204          ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL);
1205          if (ret < 0) {
1206              error_report("couldn't setup PCI devices in fdt");
1207              exit(1);
1208          }
1209      }
1210  
1211      /* cpus */
1212      spapr_populate_cpus_dt_node(fdt, spapr);
1213  
1214      if (smc->dr_lmb_enabled) {
1215          _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1216      }
1217  
1218      if (mc->has_hotpluggable_cpus) {
1219          int offset = fdt_path_offset(fdt, "/cpus");
1220          ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU);
1221          if (ret < 0) {
1222              error_report("Couldn't set up CPU DR device tree properties");
1223              exit(1);
1224          }
1225      }
1226  
1227      /* /event-sources */
1228      spapr_dt_events(spapr, fdt);
1229  
1230      /* /rtas */
1231      spapr_dt_rtas(spapr, fdt);
1232  
1233      /* /chosen */
1234      if (reset) {
1235          spapr_dt_chosen(spapr, fdt);
1236      }
1237  
1238      /* /hypervisor */
1239      if (kvm_enabled()) {
1240          spapr_dt_hypervisor(spapr, fdt);
1241      }
1242  
1243      /* Build memory reserve map */
1244      if (reset) {
1245          if (spapr->kernel_size) {
1246              _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
1247          }
1248          if (spapr->initrd_size) {
1249              _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base,
1250                                    spapr->initrd_size)));
1251          }
1252      }
1253  
1254      /* ibm,client-architecture-support updates */
1255      ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
1256      if (ret < 0) {
1257          error_report("couldn't setup CAS properties fdt");
1258          exit(1);
1259      }
1260  
1261      if (smc->dr_phb_enabled) {
1262          ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB);
1263          if (ret < 0) {
1264              error_report("Couldn't set up PHB DR device tree properties");
1265              exit(1);
1266          }
1267      }
1268  
1269      return fdt;
1270  }
1271  
1272  static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1273  {
1274      return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1275  }
1276  
1277  static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1278                                      PowerPCCPU *cpu)
1279  {
1280      CPUPPCState *env = &cpu->env;
1281  
1282      /* The TCG path should also be holding the BQL at this point */
1283      g_assert(qemu_mutex_iothread_locked());
1284  
1285      if (msr_pr) {
1286          hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1287          env->gpr[3] = H_PRIVILEGE;
1288      } else {
1289          env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1290      }
1291  }
1292  
1293  struct LPCRSyncState {
1294      target_ulong value;
1295      target_ulong mask;
1296  };
1297  
1298  static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg)
1299  {
1300      struct LPCRSyncState *s = arg.host_ptr;
1301      PowerPCCPU *cpu = POWERPC_CPU(cs);
1302      CPUPPCState *env = &cpu->env;
1303      target_ulong lpcr;
1304  
1305      cpu_synchronize_state(cs);
1306      lpcr = env->spr[SPR_LPCR];
1307      lpcr &= ~s->mask;
1308      lpcr |= s->value;
1309      ppc_store_lpcr(cpu, lpcr);
1310  }
1311  
1312  void spapr_set_all_lpcrs(target_ulong value, target_ulong mask)
1313  {
1314      CPUState *cs;
1315      struct LPCRSyncState s = {
1316          .value = value,
1317          .mask = mask
1318      };
1319      CPU_FOREACH(cs) {
1320          run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s));
1321      }
1322  }
1323  
1324  static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry)
1325  {
1326      SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1327  
1328      /* Copy PATE1:GR into PATE0:HR */
1329      entry->dw0 = spapr->patb_entry & PATE0_HR;
1330      entry->dw1 = spapr->patb_entry;
1331  }
1332  
1333  #define HPTE(_table, _i)   (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1334  #define HPTE_VALID(_hpte)  (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1335  #define HPTE_DIRTY(_hpte)  (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1336  #define CLEAN_HPTE(_hpte)  ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1337  #define DIRTY_HPTE(_hpte)  ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1338  
1339  /*
1340   * Get the fd to access the kernel htab, re-opening it if necessary
1341   */
1342  static int get_htab_fd(SpaprMachineState *spapr)
1343  {
1344      Error *local_err = NULL;
1345  
1346      if (spapr->htab_fd >= 0) {
1347          return spapr->htab_fd;
1348      }
1349  
1350      spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err);
1351      if (spapr->htab_fd < 0) {
1352          error_report_err(local_err);
1353      }
1354  
1355      return spapr->htab_fd;
1356  }
1357  
1358  void close_htab_fd(SpaprMachineState *spapr)
1359  {
1360      if (spapr->htab_fd >= 0) {
1361          close(spapr->htab_fd);
1362      }
1363      spapr->htab_fd = -1;
1364  }
1365  
1366  static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1367  {
1368      SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1369  
1370      return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1371  }
1372  
1373  static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
1374  {
1375      SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1376  
1377      assert(kvm_enabled());
1378  
1379      if (!spapr->htab) {
1380          return 0;
1381      }
1382  
1383      return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18);
1384  }
1385  
1386  static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1387                                                  hwaddr ptex, int n)
1388  {
1389      SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1390      hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1391  
1392      if (!spapr->htab) {
1393          /*
1394           * HTAB is controlled by KVM. Fetch into temporary buffer
1395           */
1396          ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1397          kvmppc_read_hptes(hptes, ptex, n);
1398          return hptes;
1399      }
1400  
1401      /*
1402       * HTAB is controlled by QEMU. Just point to the internally
1403       * accessible PTEG.
1404       */
1405      return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1406  }
1407  
1408  static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1409                                const ppc_hash_pte64_t *hptes,
1410                                hwaddr ptex, int n)
1411  {
1412      SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1413  
1414      if (!spapr->htab) {
1415          g_free((void *)hptes);
1416      }
1417  
1418      /* Nothing to do for qemu managed HPT */
1419  }
1420  
1421  void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
1422                        uint64_t pte0, uint64_t pte1)
1423  {
1424      SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp);
1425      hwaddr offset = ptex * HASH_PTE_SIZE_64;
1426  
1427      if (!spapr->htab) {
1428          kvmppc_write_hpte(ptex, pte0, pte1);
1429      } else {
1430          if (pte0 & HPTE64_V_VALID) {
1431              stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1432              /*
1433               * When setting valid, we write PTE1 first. This ensures
1434               * proper synchronization with the reading code in
1435               * ppc_hash64_pteg_search()
1436               */
1437              smp_wmb();
1438              stq_p(spapr->htab + offset, pte0);
1439          } else {
1440              stq_p(spapr->htab + offset, pte0);
1441              /*
1442               * When clearing it we set PTE0 first. This ensures proper
1443               * synchronization with the reading code in
1444               * ppc_hash64_pteg_search()
1445               */
1446              smp_wmb();
1447              stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1448          }
1449      }
1450  }
1451  
1452  static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1453                               uint64_t pte1)
1454  {
1455      hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15;
1456      SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1457  
1458      if (!spapr->htab) {
1459          /* There should always be a hash table when this is called */
1460          error_report("spapr_hpte_set_c called with no hash table !");
1461          return;
1462      }
1463  
1464      /* The HW performs a non-atomic byte update */
1465      stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80);
1466  }
1467  
1468  static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1469                               uint64_t pte1)
1470  {
1471      hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14;
1472      SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1473  
1474      if (!spapr->htab) {
1475          /* There should always be a hash table when this is called */
1476          error_report("spapr_hpte_set_r called with no hash table !");
1477          return;
1478      }
1479  
1480      /* The HW performs a non-atomic byte update */
1481      stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01);
1482  }
1483  
1484  int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1485  {
1486      int shift;
1487  
1488      /* We aim for a hash table of size 1/128 the size of RAM (rounded
1489       * up).  The PAPR recommendation is actually 1/64 of RAM size, but
1490       * that's much more than is needed for Linux guests */
1491      shift = ctz64(pow2ceil(ramsize)) - 7;
1492      shift = MAX(shift, 18); /* Minimum architected size */
1493      shift = MIN(shift, 46); /* Maximum architected size */
1494      return shift;
1495  }
1496  
1497  void spapr_free_hpt(SpaprMachineState *spapr)
1498  {
1499      g_free(spapr->htab);
1500      spapr->htab = NULL;
1501      spapr->htab_shift = 0;
1502      close_htab_fd(spapr);
1503  }
1504  
1505  void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift,
1506                            Error **errp)
1507  {
1508      long rc;
1509  
1510      /* Clean up any HPT info from a previous boot */
1511      spapr_free_hpt(spapr);
1512  
1513      rc = kvmppc_reset_htab(shift);
1514      if (rc < 0) {
1515          /* kernel-side HPT needed, but couldn't allocate one */
1516          error_setg_errno(errp, errno,
1517                           "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1518                           shift);
1519          /* This is almost certainly fatal, but if the caller really
1520           * wants to carry on with shift == 0, it's welcome to try */
1521      } else if (rc > 0) {
1522          /* kernel-side HPT allocated */
1523          if (rc != shift) {
1524              error_setg(errp,
1525                         "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1526                         shift, rc);
1527          }
1528  
1529          spapr->htab_shift = shift;
1530          spapr->htab = NULL;
1531      } else {
1532          /* kernel-side HPT not needed, allocate in userspace instead */
1533          size_t size = 1ULL << shift;
1534          int i;
1535  
1536          spapr->htab = qemu_memalign(size, size);
1537          if (!spapr->htab) {
1538              error_setg_errno(errp, errno,
1539                               "Could not allocate HPT of order %d", shift);
1540              return;
1541          }
1542  
1543          memset(spapr->htab, 0, size);
1544          spapr->htab_shift = shift;
1545  
1546          for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1547              DIRTY_HPTE(HPTE(spapr->htab, i));
1548          }
1549      }
1550      /* We're setting up a hash table, so that means we're not radix */
1551      spapr->patb_entry = 0;
1552      spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT);
1553  }
1554  
1555  void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr)
1556  {
1557      int hpt_shift;
1558  
1559      if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED)
1560          || (spapr->cas_reboot
1561              && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) {
1562          hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1563      } else {
1564          uint64_t current_ram_size;
1565  
1566          current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size();
1567          hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size);
1568      }
1569      spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal);
1570  
1571      if (spapr->vrma_adjust) {
1572          spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)),
1573                                            spapr->htab_shift);
1574      }
1575  }
1576  
1577  static int spapr_reset_drcs(Object *child, void *opaque)
1578  {
1579      SpaprDrc *drc =
1580          (SpaprDrc *) object_dynamic_cast(child,
1581                                                   TYPE_SPAPR_DR_CONNECTOR);
1582  
1583      if (drc) {
1584          spapr_drc_reset(drc);
1585      }
1586  
1587      return 0;
1588  }
1589  
1590  static void spapr_machine_reset(MachineState *machine)
1591  {
1592      SpaprMachineState *spapr = SPAPR_MACHINE(machine);
1593      PowerPCCPU *first_ppc_cpu;
1594      hwaddr fdt_addr;
1595      void *fdt;
1596      int rc;
1597  
1598      kvmppc_svm_off(&error_fatal);
1599      spapr_caps_apply(spapr);
1600  
1601      first_ppc_cpu = POWERPC_CPU(first_cpu);
1602      if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1603          ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
1604                                spapr->max_compat_pvr)) {
1605          /*
1606           * If using KVM with radix mode available, VCPUs can be started
1607           * without a HPT because KVM will start them in radix mode.
1608           * Set the GR bit in PATE so that we know there is no HPT.
1609           */
1610          spapr->patb_entry = PATE1_GR;
1611          spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT);
1612      } else {
1613          spapr_setup_hpt_and_vrma(spapr);
1614      }
1615  
1616      qemu_devices_reset();
1617  
1618      /*
1619       * If this reset wasn't generated by CAS, we should reset our
1620       * negotiated options and start from scratch
1621       */
1622      if (!spapr->cas_reboot) {
1623          spapr_ovec_cleanup(spapr->ov5_cas);
1624          spapr->ov5_cas = spapr_ovec_new();
1625  
1626          ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal);
1627      }
1628  
1629      /*
1630       * This is fixing some of the default configuration of the XIVE
1631       * devices. To be called after the reset of the machine devices.
1632       */
1633      spapr_irq_reset(spapr, &error_fatal);
1634  
1635      /*
1636       * There is no CAS under qtest. Simulate one to please the code that
1637       * depends on spapr->ov5_cas. This is especially needed to test device
1638       * unplug, so we do that before resetting the DRCs.
1639       */
1640      if (qtest_enabled()) {
1641          spapr_ovec_cleanup(spapr->ov5_cas);
1642          spapr->ov5_cas = spapr_ovec_clone(spapr->ov5);
1643      }
1644  
1645      /* DRC reset may cause a device to be unplugged. This will cause troubles
1646       * if this device is used by another device (eg, a running vhost backend
1647       * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1648       * situations, we reset DRCs after all devices have been reset.
1649       */
1650      object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL);
1651  
1652      spapr_clear_pending_events(spapr);
1653  
1654      /*
1655       * We place the device tree and RTAS just below either the top of the RMA,
1656       * or just below 2GB, whichever is lower, so that it can be
1657       * processed with 32-bit real mode code if necessary
1658       */
1659      fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE;
1660  
1661      fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE);
1662  
1663      rc = fdt_pack(fdt);
1664  
1665      /* Should only fail if we've built a corrupted tree */
1666      assert(rc == 0);
1667  
1668      /* Load the fdt */
1669      qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1670      cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1671      g_free(spapr->fdt_blob);
1672      spapr->fdt_size = fdt_totalsize(fdt);
1673      spapr->fdt_initial_size = spapr->fdt_size;
1674      spapr->fdt_blob = fdt;
1675  
1676      /* Set up the entry state */
1677      spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr);
1678      first_ppc_cpu->env.gpr[5] = 0;
1679  
1680      spapr->cas_reboot = false;
1681  
1682      spapr->mc_status = -1;
1683      spapr->guest_machine_check_addr = -1;
1684  
1685      /* Signal all vCPUs waiting on this condition */
1686      qemu_cond_broadcast(&spapr->mc_delivery_cond);
1687  
1688      migrate_del_blocker(spapr->fwnmi_migration_blocker);
1689  }
1690  
1691  static void spapr_create_nvram(SpaprMachineState *spapr)
1692  {
1693      DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1694      DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1695  
1696      if (dinfo) {
1697          qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1698                              &error_fatal);
1699      }
1700  
1701      qdev_init_nofail(dev);
1702  
1703      spapr->nvram = (struct SpaprNvram *)dev;
1704  }
1705  
1706  static void spapr_rtc_create(SpaprMachineState *spapr)
1707  {
1708      object_initialize_child(OBJECT(spapr), "rtc",
1709                              &spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC,
1710                              &error_fatal, NULL);
1711      object_property_set_bool(OBJECT(&spapr->rtc), true, "realized",
1712                                &error_fatal);
1713      object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
1714                                "date", &error_fatal);
1715  }
1716  
1717  /* Returns whether we want to use VGA or not */
1718  static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1719  {
1720      switch (vga_interface_type) {
1721      case VGA_NONE:
1722          return false;
1723      case VGA_DEVICE:
1724          return true;
1725      case VGA_STD:
1726      case VGA_VIRTIO:
1727      case VGA_CIRRUS:
1728          return pci_vga_init(pci_bus) != NULL;
1729      default:
1730          error_setg(errp,
1731                     "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1732          return false;
1733      }
1734  }
1735  
1736  static int spapr_pre_load(void *opaque)
1737  {
1738      int rc;
1739  
1740      rc = spapr_caps_pre_load(opaque);
1741      if (rc) {
1742          return rc;
1743      }
1744  
1745      return 0;
1746  }
1747  
1748  static int spapr_post_load(void *opaque, int version_id)
1749  {
1750      SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1751      int err = 0;
1752  
1753      err = spapr_caps_post_migration(spapr);
1754      if (err) {
1755          return err;
1756      }
1757  
1758      /*
1759       * In earlier versions, there was no separate qdev for the PAPR
1760       * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1761       * So when migrating from those versions, poke the incoming offset
1762       * value into the RTC device
1763       */
1764      if (version_id < 3) {
1765          err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset);
1766          if (err) {
1767              return err;
1768          }
1769      }
1770  
1771      if (kvm_enabled() && spapr->patb_entry) {
1772          PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
1773          bool radix = !!(spapr->patb_entry & PATE1_GR);
1774          bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE);
1775  
1776          /*
1777           * Update LPCR:HR and UPRT as they may not be set properly in
1778           * the stream
1779           */
1780          spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0,
1781                              LPCR_HR | LPCR_UPRT);
1782  
1783          err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry);
1784          if (err) {
1785              error_report("Process table config unsupported by the host");
1786              return -EINVAL;
1787          }
1788      }
1789  
1790      err = spapr_irq_post_load(spapr, version_id);
1791      if (err) {
1792          return err;
1793      }
1794  
1795      return err;
1796  }
1797  
1798  static int spapr_pre_save(void *opaque)
1799  {
1800      int rc;
1801  
1802      rc = spapr_caps_pre_save(opaque);
1803      if (rc) {
1804          return rc;
1805      }
1806  
1807      return 0;
1808  }
1809  
1810  static bool version_before_3(void *opaque, int version_id)
1811  {
1812      return version_id < 3;
1813  }
1814  
1815  static bool spapr_pending_events_needed(void *opaque)
1816  {
1817      SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1818      return !QTAILQ_EMPTY(&spapr->pending_events);
1819  }
1820  
1821  static const VMStateDescription vmstate_spapr_event_entry = {
1822      .name = "spapr_event_log_entry",
1823      .version_id = 1,
1824      .minimum_version_id = 1,
1825      .fields = (VMStateField[]) {
1826          VMSTATE_UINT32(summary, SpaprEventLogEntry),
1827          VMSTATE_UINT32(extended_length, SpaprEventLogEntry),
1828          VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0,
1829                                       NULL, extended_length),
1830          VMSTATE_END_OF_LIST()
1831      },
1832  };
1833  
1834  static const VMStateDescription vmstate_spapr_pending_events = {
1835      .name = "spapr_pending_events",
1836      .version_id = 1,
1837      .minimum_version_id = 1,
1838      .needed = spapr_pending_events_needed,
1839      .fields = (VMStateField[]) {
1840          VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1,
1841                           vmstate_spapr_event_entry, SpaprEventLogEntry, next),
1842          VMSTATE_END_OF_LIST()
1843      },
1844  };
1845  
1846  static bool spapr_ov5_cas_needed(void *opaque)
1847  {
1848      SpaprMachineState *spapr = opaque;
1849      SpaprOptionVector *ov5_mask = spapr_ovec_new();
1850      bool cas_needed;
1851  
1852      /* Prior to the introduction of SpaprOptionVector, we had two option
1853       * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1854       * Both of these options encode machine topology into the device-tree
1855       * in such a way that the now-booted OS should still be able to interact
1856       * appropriately with QEMU regardless of what options were actually
1857       * negotiatied on the source side.
1858       *
1859       * As such, we can avoid migrating the CAS-negotiated options if these
1860       * are the only options available on the current machine/platform.
1861       * Since these are the only options available for pseries-2.7 and
1862       * earlier, this allows us to maintain old->new/new->old migration
1863       * compatibility.
1864       *
1865       * For QEMU 2.8+, there are additional CAS-negotiatable options available
1866       * via default pseries-2.8 machines and explicit command-line parameters.
1867       * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1868       * of the actual CAS-negotiated values to continue working properly. For
1869       * example, availability of memory unplug depends on knowing whether
1870       * OV5_HP_EVT was negotiated via CAS.
1871       *
1872       * Thus, for any cases where the set of available CAS-negotiatable
1873       * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1874       * include the CAS-negotiated options in the migration stream, unless
1875       * if they affect boot time behaviour only.
1876       */
1877      spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1878      spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1879      spapr_ovec_set(ov5_mask, OV5_DRMEM_V2);
1880  
1881      /* We need extra information if we have any bits outside the mask
1882       * defined above */
1883      cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask);
1884  
1885      spapr_ovec_cleanup(ov5_mask);
1886  
1887      return cas_needed;
1888  }
1889  
1890  static const VMStateDescription vmstate_spapr_ov5_cas = {
1891      .name = "spapr_option_vector_ov5_cas",
1892      .version_id = 1,
1893      .minimum_version_id = 1,
1894      .needed = spapr_ov5_cas_needed,
1895      .fields = (VMStateField[]) {
1896          VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1,
1897                                   vmstate_spapr_ovec, SpaprOptionVector),
1898          VMSTATE_END_OF_LIST()
1899      },
1900  };
1901  
1902  static bool spapr_patb_entry_needed(void *opaque)
1903  {
1904      SpaprMachineState *spapr = opaque;
1905  
1906      return !!spapr->patb_entry;
1907  }
1908  
1909  static const VMStateDescription vmstate_spapr_patb_entry = {
1910      .name = "spapr_patb_entry",
1911      .version_id = 1,
1912      .minimum_version_id = 1,
1913      .needed = spapr_patb_entry_needed,
1914      .fields = (VMStateField[]) {
1915          VMSTATE_UINT64(patb_entry, SpaprMachineState),
1916          VMSTATE_END_OF_LIST()
1917      },
1918  };
1919  
1920  static bool spapr_irq_map_needed(void *opaque)
1921  {
1922      SpaprMachineState *spapr = opaque;
1923  
1924      return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr);
1925  }
1926  
1927  static const VMStateDescription vmstate_spapr_irq_map = {
1928      .name = "spapr_irq_map",
1929      .version_id = 1,
1930      .minimum_version_id = 1,
1931      .needed = spapr_irq_map_needed,
1932      .fields = (VMStateField[]) {
1933          VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr),
1934          VMSTATE_END_OF_LIST()
1935      },
1936  };
1937  
1938  static bool spapr_dtb_needed(void *opaque)
1939  {
1940      SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque);
1941  
1942      return smc->update_dt_enabled;
1943  }
1944  
1945  static int spapr_dtb_pre_load(void *opaque)
1946  {
1947      SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1948  
1949      g_free(spapr->fdt_blob);
1950      spapr->fdt_blob = NULL;
1951      spapr->fdt_size = 0;
1952  
1953      return 0;
1954  }
1955  
1956  static const VMStateDescription vmstate_spapr_dtb = {
1957      .name = "spapr_dtb",
1958      .version_id = 1,
1959      .minimum_version_id = 1,
1960      .needed = spapr_dtb_needed,
1961      .pre_load = spapr_dtb_pre_load,
1962      .fields = (VMStateField[]) {
1963          VMSTATE_UINT32(fdt_initial_size, SpaprMachineState),
1964          VMSTATE_UINT32(fdt_size, SpaprMachineState),
1965          VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL,
1966                                       fdt_size),
1967          VMSTATE_END_OF_LIST()
1968      },
1969  };
1970  
1971  static bool spapr_fwnmi_needed(void *opaque)
1972  {
1973      SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1974  
1975      return spapr->guest_machine_check_addr != -1;
1976  }
1977  
1978  static int spapr_fwnmi_pre_save(void *opaque)
1979  {
1980      SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1981  
1982      /*
1983       * Check if machine check handling is in progress and print a
1984       * warning message.
1985       */
1986      if (spapr->mc_status != -1) {
1987          warn_report("A machine check is being handled during migration. The"
1988                  "handler may run and log hardware error on the destination");
1989      }
1990  
1991      return 0;
1992  }
1993  
1994  static const VMStateDescription vmstate_spapr_machine_check = {
1995      .name = "spapr_machine_check",
1996      .version_id = 1,
1997      .minimum_version_id = 1,
1998      .needed = spapr_fwnmi_needed,
1999      .pre_save = spapr_fwnmi_pre_save,
2000      .fields = (VMStateField[]) {
2001          VMSTATE_UINT64(guest_machine_check_addr, SpaprMachineState),
2002          VMSTATE_INT32(mc_status, SpaprMachineState),
2003          VMSTATE_END_OF_LIST()
2004      },
2005  };
2006  
2007  static const VMStateDescription vmstate_spapr = {
2008      .name = "spapr",
2009      .version_id = 3,
2010      .minimum_version_id = 1,
2011      .pre_load = spapr_pre_load,
2012      .post_load = spapr_post_load,
2013      .pre_save = spapr_pre_save,
2014      .fields = (VMStateField[]) {
2015          /* used to be @next_irq */
2016          VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
2017  
2018          /* RTC offset */
2019          VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3),
2020  
2021          VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2),
2022          VMSTATE_END_OF_LIST()
2023      },
2024      .subsections = (const VMStateDescription*[]) {
2025          &vmstate_spapr_ov5_cas,
2026          &vmstate_spapr_patb_entry,
2027          &vmstate_spapr_pending_events,
2028          &vmstate_spapr_cap_htm,
2029          &vmstate_spapr_cap_vsx,
2030          &vmstate_spapr_cap_dfp,
2031          &vmstate_spapr_cap_cfpc,
2032          &vmstate_spapr_cap_sbbc,
2033          &vmstate_spapr_cap_ibs,
2034          &vmstate_spapr_cap_hpt_maxpagesize,
2035          &vmstate_spapr_irq_map,
2036          &vmstate_spapr_cap_nested_kvm_hv,
2037          &vmstate_spapr_dtb,
2038          &vmstate_spapr_cap_large_decr,
2039          &vmstate_spapr_cap_ccf_assist,
2040          &vmstate_spapr_cap_fwnmi,
2041          &vmstate_spapr_machine_check,
2042          NULL
2043      }
2044  };
2045  
2046  static int htab_save_setup(QEMUFile *f, void *opaque)
2047  {
2048      SpaprMachineState *spapr = opaque;
2049  
2050      /* "Iteration" header */
2051      if (!spapr->htab_shift) {
2052          qemu_put_be32(f, -1);
2053      } else {
2054          qemu_put_be32(f, spapr->htab_shift);
2055      }
2056  
2057      if (spapr->htab) {
2058          spapr->htab_save_index = 0;
2059          spapr->htab_first_pass = true;
2060      } else {
2061          if (spapr->htab_shift) {
2062              assert(kvm_enabled());
2063          }
2064      }
2065  
2066  
2067      return 0;
2068  }
2069  
2070  static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr,
2071                              int chunkstart, int n_valid, int n_invalid)
2072  {
2073      qemu_put_be32(f, chunkstart);
2074      qemu_put_be16(f, n_valid);
2075      qemu_put_be16(f, n_invalid);
2076      qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
2077                      HASH_PTE_SIZE_64 * n_valid);
2078  }
2079  
2080  static void htab_save_end_marker(QEMUFile *f)
2081  {
2082      qemu_put_be32(f, 0);
2083      qemu_put_be16(f, 0);
2084      qemu_put_be16(f, 0);
2085  }
2086  
2087  static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr,
2088                                   int64_t max_ns)
2089  {
2090      bool has_timeout = max_ns != -1;
2091      int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2092      int index = spapr->htab_save_index;
2093      int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2094  
2095      assert(spapr->htab_first_pass);
2096  
2097      do {
2098          int chunkstart;
2099  
2100          /* Consume invalid HPTEs */
2101          while ((index < htabslots)
2102                 && !HPTE_VALID(HPTE(spapr->htab, index))) {
2103              CLEAN_HPTE(HPTE(spapr->htab, index));
2104              index++;
2105          }
2106  
2107          /* Consume valid HPTEs */
2108          chunkstart = index;
2109          while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2110                 && HPTE_VALID(HPTE(spapr->htab, index))) {
2111              CLEAN_HPTE(HPTE(spapr->htab, index));
2112              index++;
2113          }
2114  
2115          if (index > chunkstart) {
2116              int n_valid = index - chunkstart;
2117  
2118              htab_save_chunk(f, spapr, chunkstart, n_valid, 0);
2119  
2120              if (has_timeout &&
2121                  (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2122                  break;
2123              }
2124          }
2125      } while ((index < htabslots) && !qemu_file_rate_limit(f));
2126  
2127      if (index >= htabslots) {
2128          assert(index == htabslots);
2129          index = 0;
2130          spapr->htab_first_pass = false;
2131      }
2132      spapr->htab_save_index = index;
2133  }
2134  
2135  static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr,
2136                                  int64_t max_ns)
2137  {
2138      bool final = max_ns < 0;
2139      int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2140      int examined = 0, sent = 0;
2141      int index = spapr->htab_save_index;
2142      int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2143  
2144      assert(!spapr->htab_first_pass);
2145  
2146      do {
2147          int chunkstart, invalidstart;
2148  
2149          /* Consume non-dirty HPTEs */
2150          while ((index < htabslots)
2151                 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
2152              index++;
2153              examined++;
2154          }
2155  
2156          chunkstart = index;
2157          /* Consume valid dirty HPTEs */
2158          while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2159                 && HPTE_DIRTY(HPTE(spapr->htab, index))
2160                 && HPTE_VALID(HPTE(spapr->htab, index))) {
2161              CLEAN_HPTE(HPTE(spapr->htab, index));
2162              index++;
2163              examined++;
2164          }
2165  
2166          invalidstart = index;
2167          /* Consume invalid dirty HPTEs */
2168          while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
2169                 && HPTE_DIRTY(HPTE(spapr->htab, index))
2170                 && !HPTE_VALID(HPTE(spapr->htab, index))) {
2171              CLEAN_HPTE(HPTE(spapr->htab, index));
2172              index++;
2173              examined++;
2174          }
2175  
2176          if (index > chunkstart) {
2177              int n_valid = invalidstart - chunkstart;
2178              int n_invalid = index - invalidstart;
2179  
2180              htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid);
2181              sent += index - chunkstart;
2182  
2183              if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2184                  break;
2185              }
2186          }
2187  
2188          if (examined >= htabslots) {
2189              break;
2190          }
2191  
2192          if (index >= htabslots) {
2193              assert(index == htabslots);
2194              index = 0;
2195          }
2196      } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
2197  
2198      if (index >= htabslots) {
2199          assert(index == htabslots);
2200          index = 0;
2201      }
2202  
2203      spapr->htab_save_index = index;
2204  
2205      return (examined >= htabslots) && (sent == 0) ? 1 : 0;
2206  }
2207  
2208  #define MAX_ITERATION_NS    5000000 /* 5 ms */
2209  #define MAX_KVM_BUF_SIZE    2048
2210  
2211  static int htab_save_iterate(QEMUFile *f, void *opaque)
2212  {
2213      SpaprMachineState *spapr = opaque;
2214      int fd;
2215      int rc = 0;
2216  
2217      /* Iteration header */
2218      if (!spapr->htab_shift) {
2219          qemu_put_be32(f, -1);
2220          return 1;
2221      } else {
2222          qemu_put_be32(f, 0);
2223      }
2224  
2225      if (!spapr->htab) {
2226          assert(kvm_enabled());
2227  
2228          fd = get_htab_fd(spapr);
2229          if (fd < 0) {
2230              return fd;
2231          }
2232  
2233          rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
2234          if (rc < 0) {
2235              return rc;
2236          }
2237      } else  if (spapr->htab_first_pass) {
2238          htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
2239      } else {
2240          rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
2241      }
2242  
2243      htab_save_end_marker(f);
2244  
2245      return rc;
2246  }
2247  
2248  static int htab_save_complete(QEMUFile *f, void *opaque)
2249  {
2250      SpaprMachineState *spapr = opaque;
2251      int fd;
2252  
2253      /* Iteration header */
2254      if (!spapr->htab_shift) {
2255          qemu_put_be32(f, -1);
2256          return 0;
2257      } else {
2258          qemu_put_be32(f, 0);
2259      }
2260  
2261      if (!spapr->htab) {
2262          int rc;
2263  
2264          assert(kvm_enabled());
2265  
2266          fd = get_htab_fd(spapr);
2267          if (fd < 0) {
2268              return fd;
2269          }
2270  
2271          rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
2272          if (rc < 0) {
2273              return rc;
2274          }
2275      } else {
2276          if (spapr->htab_first_pass) {
2277              htab_save_first_pass(f, spapr, -1);
2278          }
2279          htab_save_later_pass(f, spapr, -1);
2280      }
2281  
2282      /* End marker */
2283      htab_save_end_marker(f);
2284  
2285      return 0;
2286  }
2287  
2288  static int htab_load(QEMUFile *f, void *opaque, int version_id)
2289  {
2290      SpaprMachineState *spapr = opaque;
2291      uint32_t section_hdr;
2292      int fd = -1;
2293      Error *local_err = NULL;
2294  
2295      if (version_id < 1 || version_id > 1) {
2296          error_report("htab_load() bad version");
2297          return -EINVAL;
2298      }
2299  
2300      section_hdr = qemu_get_be32(f);
2301  
2302      if (section_hdr == -1) {
2303          spapr_free_hpt(spapr);
2304          return 0;
2305      }
2306  
2307      if (section_hdr) {
2308          /* First section gives the htab size */
2309          spapr_reallocate_hpt(spapr, section_hdr, &local_err);
2310          if (local_err) {
2311              error_report_err(local_err);
2312              return -EINVAL;
2313          }
2314          return 0;
2315      }
2316  
2317      if (!spapr->htab) {
2318          assert(kvm_enabled());
2319  
2320          fd = kvmppc_get_htab_fd(true, 0, &local_err);
2321          if (fd < 0) {
2322              error_report_err(local_err);
2323              return fd;
2324          }
2325      }
2326  
2327      while (true) {
2328          uint32_t index;
2329          uint16_t n_valid, n_invalid;
2330  
2331          index = qemu_get_be32(f);
2332          n_valid = qemu_get_be16(f);
2333          n_invalid = qemu_get_be16(f);
2334  
2335          if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
2336              /* End of Stream */
2337              break;
2338          }
2339  
2340          if ((index + n_valid + n_invalid) >
2341              (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
2342              /* Bad index in stream */
2343              error_report(
2344                  "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2345                  index, n_valid, n_invalid, spapr->htab_shift);
2346              return -EINVAL;
2347          }
2348  
2349          if (spapr->htab) {
2350              if (n_valid) {
2351                  qemu_get_buffer(f, HPTE(spapr->htab, index),
2352                                  HASH_PTE_SIZE_64 * n_valid);
2353              }
2354              if (n_invalid) {
2355                  memset(HPTE(spapr->htab, index + n_valid), 0,
2356                         HASH_PTE_SIZE_64 * n_invalid);
2357              }
2358          } else {
2359              int rc;
2360  
2361              assert(fd >= 0);
2362  
2363              rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
2364              if (rc < 0) {
2365                  return rc;
2366              }
2367          }
2368      }
2369  
2370      if (!spapr->htab) {
2371          assert(fd >= 0);
2372          close(fd);
2373      }
2374  
2375      return 0;
2376  }
2377  
2378  static void htab_save_cleanup(void *opaque)
2379  {
2380      SpaprMachineState *spapr = opaque;
2381  
2382      close_htab_fd(spapr);
2383  }
2384  
2385  static SaveVMHandlers savevm_htab_handlers = {
2386      .save_setup = htab_save_setup,
2387      .save_live_iterate = htab_save_iterate,
2388      .save_live_complete_precopy = htab_save_complete,
2389      .save_cleanup = htab_save_cleanup,
2390      .load_state = htab_load,
2391  };
2392  
2393  static void spapr_boot_set(void *opaque, const char *boot_device,
2394                             Error **errp)
2395  {
2396      MachineState *machine = MACHINE(opaque);
2397      machine->boot_order = g_strdup(boot_device);
2398  }
2399  
2400  static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr)
2401  {
2402      MachineState *machine = MACHINE(spapr);
2403      uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
2404      uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
2405      int i;
2406  
2407      for (i = 0; i < nr_lmbs; i++) {
2408          uint64_t addr;
2409  
2410          addr = i * lmb_size + machine->device_memory->base;
2411          spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB,
2412                                 addr / lmb_size);
2413      }
2414  }
2415  
2416  /*
2417   * If RAM size, maxmem size and individual node mem sizes aren't aligned
2418   * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2419   * since we can't support such unaligned sizes with DRCONF_MEMORY.
2420   */
2421  static void spapr_validate_node_memory(MachineState *machine, Error **errp)
2422  {
2423      int i;
2424  
2425      if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2426          error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
2427                     " is not aligned to %" PRIu64 " MiB",
2428                     machine->ram_size,
2429                     SPAPR_MEMORY_BLOCK_SIZE / MiB);
2430          return;
2431      }
2432  
2433      if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2434          error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
2435                     " is not aligned to %" PRIu64 " MiB",
2436                     machine->ram_size,
2437                     SPAPR_MEMORY_BLOCK_SIZE / MiB);
2438          return;
2439      }
2440  
2441      for (i = 0; i < machine->numa_state->num_nodes; i++) {
2442          if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
2443              error_setg(errp,
2444                         "Node %d memory size 0x%" PRIx64
2445                         " is not aligned to %" PRIu64 " MiB",
2446                         i, machine->numa_state->nodes[i].node_mem,
2447                         SPAPR_MEMORY_BLOCK_SIZE / MiB);
2448              return;
2449          }
2450      }
2451  }
2452  
2453  /* find cpu slot in machine->possible_cpus by core_id */
2454  static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2455  {
2456      int index = id / ms->smp.threads;
2457  
2458      if (index >= ms->possible_cpus->len) {
2459          return NULL;
2460      }
2461      if (idx) {
2462          *idx = index;
2463      }
2464      return &ms->possible_cpus->cpus[index];
2465  }
2466  
2467  static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp)
2468  {
2469      MachineState *ms = MACHINE(spapr);
2470      SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
2471      Error *local_err = NULL;
2472      bool vsmt_user = !!spapr->vsmt;
2473      int kvm_smt = kvmppc_smt_threads();
2474      int ret;
2475      unsigned int smp_threads = ms->smp.threads;
2476  
2477      if (!kvm_enabled() && (smp_threads > 1)) {
2478          error_setg(&local_err, "TCG cannot support more than 1 thread/core "
2479                       "on a pseries machine");
2480          goto out;
2481      }
2482      if (!is_power_of_2(smp_threads)) {
2483          error_setg(&local_err, "Cannot support %d threads/core on a pseries "
2484                       "machine because it must be a power of 2", smp_threads);
2485          goto out;
2486      }
2487  
2488      /* Detemine the VSMT mode to use: */
2489      if (vsmt_user) {
2490          if (spapr->vsmt < smp_threads) {
2491              error_setg(&local_err, "Cannot support VSMT mode %d"
2492                           " because it must be >= threads/core (%d)",
2493                           spapr->vsmt, smp_threads);
2494              goto out;
2495          }
2496          /* In this case, spapr->vsmt has been set by the command line */
2497      } else if (!smc->smp_threads_vsmt) {
2498          /*
2499           * Default VSMT value is tricky, because we need it to be as
2500           * consistent as possible (for migration), but this requires
2501           * changing it for at least some existing cases.  We pick 8 as
2502           * the value that we'd get with KVM on POWER8, the
2503           * overwhelmingly common case in production systems.
2504           */
2505          spapr->vsmt = MAX(8, smp_threads);
2506      } else {
2507          spapr->vsmt = smp_threads;
2508      }
2509  
2510      /* KVM: If necessary, set the SMT mode: */
2511      if (kvm_enabled() && (spapr->vsmt != kvm_smt)) {
2512          ret = kvmppc_set_smt_threads(spapr->vsmt);
2513          if (ret) {
2514              /* Looks like KVM isn't able to change VSMT mode */
2515              error_setg(&local_err,
2516                         "Failed to set KVM's VSMT mode to %d (errno %d)",
2517                         spapr->vsmt, ret);
2518              /* We can live with that if the default one is big enough
2519               * for the number of threads, and a submultiple of the one
2520               * we want.  In this case we'll waste some vcpu ids, but
2521               * behaviour will be correct */
2522              if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) {
2523                  warn_report_err(local_err);
2524                  local_err = NULL;
2525                  goto out;
2526              } else {
2527                  if (!vsmt_user) {
2528                      error_append_hint(&local_err,
2529                                        "On PPC, a VM with %d threads/core"
2530                                        " on a host with %d threads/core"
2531                                        " requires the use of VSMT mode %d.\n",
2532                                        smp_threads, kvm_smt, spapr->vsmt);
2533                  }
2534                  kvmppc_error_append_smt_possible_hint(&local_err);
2535                  goto out;
2536              }
2537          }
2538      }
2539      /* else TCG: nothing to do currently */
2540  out:
2541      error_propagate(errp, local_err);
2542  }
2543  
2544  static void spapr_init_cpus(SpaprMachineState *spapr)
2545  {
2546      MachineState *machine = MACHINE(spapr);
2547      MachineClass *mc = MACHINE_GET_CLASS(machine);
2548      SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2549      const char *type = spapr_get_cpu_core_type(machine->cpu_type);
2550      const CPUArchIdList *possible_cpus;
2551      unsigned int smp_cpus = machine->smp.cpus;
2552      unsigned int smp_threads = machine->smp.threads;
2553      unsigned int max_cpus = machine->smp.max_cpus;
2554      int boot_cores_nr = smp_cpus / smp_threads;
2555      int i;
2556  
2557      possible_cpus = mc->possible_cpu_arch_ids(machine);
2558      if (mc->has_hotpluggable_cpus) {
2559          if (smp_cpus % smp_threads) {
2560              error_report("smp_cpus (%u) must be multiple of threads (%u)",
2561                           smp_cpus, smp_threads);
2562              exit(1);
2563          }
2564          if (max_cpus % smp_threads) {
2565              error_report("max_cpus (%u) must be multiple of threads (%u)",
2566                           max_cpus, smp_threads);
2567              exit(1);
2568          }
2569      } else {
2570          if (max_cpus != smp_cpus) {
2571              error_report("This machine version does not support CPU hotplug");
2572              exit(1);
2573          }
2574          boot_cores_nr = possible_cpus->len;
2575      }
2576  
2577      if (smc->pre_2_10_has_unused_icps) {
2578          int i;
2579  
2580          for (i = 0; i < spapr_max_server_number(spapr); i++) {
2581              /* Dummy entries get deregistered when real ICPState objects
2582               * are registered during CPU core hotplug.
2583               */
2584              pre_2_10_vmstate_register_dummy_icp(i);
2585          }
2586      }
2587  
2588      for (i = 0; i < possible_cpus->len; i++) {
2589          int core_id = i * smp_threads;
2590  
2591          if (mc->has_hotpluggable_cpus) {
2592              spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU,
2593                                     spapr_vcpu_id(spapr, core_id));
2594          }
2595  
2596          if (i < boot_cores_nr) {
2597              Object *core  = object_new(type);
2598              int nr_threads = smp_threads;
2599  
2600              /* Handle the partially filled core for older machine types */
2601              if ((i + 1) * smp_threads >= smp_cpus) {
2602                  nr_threads = smp_cpus - i * smp_threads;
2603              }
2604  
2605              object_property_set_int(core, nr_threads, "nr-threads",
2606                                      &error_fatal);
2607              object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
2608                                      &error_fatal);
2609              object_property_set_bool(core, true, "realized", &error_fatal);
2610  
2611              object_unref(core);
2612          }
2613      }
2614  }
2615  
2616  static PCIHostState *spapr_create_default_phb(void)
2617  {
2618      DeviceState *dev;
2619  
2620      dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE);
2621      qdev_prop_set_uint32(dev, "index", 0);
2622      qdev_init_nofail(dev);
2623  
2624      return PCI_HOST_BRIDGE(dev);
2625  }
2626  
2627  /* pSeries LPAR / sPAPR hardware init */
2628  static void spapr_machine_init(MachineState *machine)
2629  {
2630      SpaprMachineState *spapr = SPAPR_MACHINE(machine);
2631      SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2632      const char *kernel_filename = machine->kernel_filename;
2633      const char *initrd_filename = machine->initrd_filename;
2634      PCIHostState *phb;
2635      int i;
2636      MemoryRegion *sysmem = get_system_memory();
2637      MemoryRegion *ram = g_new(MemoryRegion, 1);
2638      hwaddr node0_size = spapr_node0_size(machine);
2639      long load_limit, fw_size;
2640      char *filename;
2641      Error *resize_hpt_err = NULL;
2642  
2643      msi_nonbroken = true;
2644  
2645      QLIST_INIT(&spapr->phbs);
2646      QTAILQ_INIT(&spapr->pending_dimm_unplugs);
2647  
2648      /* Determine capabilities to run with */
2649      spapr_caps_init(spapr);
2650  
2651      kvmppc_check_papr_resize_hpt(&resize_hpt_err);
2652      if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) {
2653          /*
2654           * If the user explicitly requested a mode we should either
2655           * supply it, or fail completely (which we do below).  But if
2656           * it's not set explicitly, we reset our mode to something
2657           * that works
2658           */
2659          if (resize_hpt_err) {
2660              spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2661              error_free(resize_hpt_err);
2662              resize_hpt_err = NULL;
2663          } else {
2664              spapr->resize_hpt = smc->resize_hpt_default;
2665          }
2666      }
2667  
2668      assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT);
2669  
2670      if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) {
2671          /*
2672           * User requested HPT resize, but this host can't supply it.  Bail out
2673           */
2674          error_report_err(resize_hpt_err);
2675          exit(1);
2676      }
2677  
2678      spapr->rma_size = node0_size;
2679  
2680      /* With KVM, we don't actually know whether KVM supports an
2681       * unbounded RMA (PR KVM) or is limited by the hash table size
2682       * (HV KVM using VRMA), so we always assume the latter
2683       *
2684       * In that case, we also limit the initial allocations for RTAS
2685       * etc... to 256M since we have no way to know what the VRMA size
2686       * is going to be as it depends on the size of the hash table
2687       * which isn't determined yet.
2688       */
2689      if (kvm_enabled()) {
2690          spapr->vrma_adjust = 1;
2691          spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
2692      }
2693  
2694      /* Actually we don't support unbounded RMA anymore since we added
2695       * proper emulation of HV mode. The max we can get is 16G which
2696       * also happens to be what we configure for PAPR mode so make sure
2697       * we don't do anything bigger than that
2698       */
2699      spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
2700  
2701      if (spapr->rma_size > node0_size) {
2702          error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
2703                       spapr->rma_size);
2704          exit(1);
2705      }
2706  
2707      /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2708      load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2709  
2710      /*
2711       * VSMT must be set in order to be able to compute VCPU ids, ie to
2712       * call spapr_max_server_number() or spapr_vcpu_id().
2713       */
2714      spapr_set_vsmt_mode(spapr, &error_fatal);
2715  
2716      /* Set up Interrupt Controller before we create the VCPUs */
2717      spapr_irq_init(spapr, &error_fatal);
2718  
2719      /* Set up containers for ibm,client-architecture-support negotiated options
2720       */
2721      spapr->ov5 = spapr_ovec_new();
2722      spapr->ov5_cas = spapr_ovec_new();
2723  
2724      if (smc->dr_lmb_enabled) {
2725          spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2726          spapr_validate_node_memory(machine, &error_fatal);
2727      }
2728  
2729      spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2730  
2731      /* advertise support for dedicated HP event source to guests */
2732      if (spapr->use_hotplug_event_source) {
2733          spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2734      }
2735  
2736      /* advertise support for HPT resizing */
2737      if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
2738          spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE);
2739      }
2740  
2741      /* advertise support for ibm,dyamic-memory-v2 */
2742      spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2);
2743  
2744      /* advertise XIVE on POWER9 machines */
2745      if (spapr->irq->xive) {
2746          spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT);
2747      }
2748  
2749      /* init CPUs */
2750      spapr_init_cpus(spapr);
2751  
2752      /*
2753       * check we don't have a memory-less/cpu-less NUMA node
2754       * Firmware relies on the existing memory/cpu topology to provide the
2755       * NUMA topology to the kernel.
2756       * And the linux kernel needs to know the NUMA topology at start
2757       * to be able to hotplug CPUs later.
2758       */
2759      if (machine->numa_state->num_nodes) {
2760          for (i = 0; i < machine->numa_state->num_nodes; ++i) {
2761              /* check for memory-less node */
2762              if (machine->numa_state->nodes[i].node_mem == 0) {
2763                  CPUState *cs;
2764                  int found = 0;
2765                  /* check for cpu-less node */
2766                  CPU_FOREACH(cs) {
2767                      PowerPCCPU *cpu = POWERPC_CPU(cs);
2768                      if (cpu->node_id == i) {
2769                          found = 1;
2770                          break;
2771                      }
2772                  }
2773                  /* memory-less and cpu-less node */
2774                  if (!found) {
2775                      error_report(
2776                         "Memory-less/cpu-less nodes are not supported (node %d)",
2777                                   i);
2778                      exit(1);
2779                  }
2780              }
2781          }
2782  
2783      }
2784  
2785      /*
2786       * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node.
2787       * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is
2788       * called from vPHB reset handler so we initialize the counter here.
2789       * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM
2790       * must be equally distant from any other node.
2791       * The final value of spapr->gpu_numa_id is going to be written to
2792       * max-associativity-domains in spapr_build_fdt().
2793       */
2794      spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes);
2795  
2796      if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2797          ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
2798                                spapr->max_compat_pvr)) {
2799          /* KVM and TCG always allow GTSE with radix... */
2800          spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
2801      }
2802      /* ... but not with hash (currently). */
2803  
2804      if (kvm_enabled()) {
2805          /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2806          kvmppc_enable_logical_ci_hcalls();
2807          kvmppc_enable_set_mode_hcall();
2808  
2809          /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2810          kvmppc_enable_clear_ref_mod_hcalls();
2811  
2812          /* Enable H_PAGE_INIT */
2813          kvmppc_enable_h_page_init();
2814      }
2815  
2816      /* allocate RAM */
2817      memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
2818                                           machine->ram_size);
2819      memory_region_add_subregion(sysmem, 0, ram);
2820  
2821      /* always allocate the device memory information */
2822      machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
2823  
2824      /* initialize hotplug memory address space */
2825      if (machine->ram_size < machine->maxram_size) {
2826          ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
2827          /*
2828           * Limit the number of hotpluggable memory slots to half the number
2829           * slots that KVM supports, leaving the other half for PCI and other
2830           * devices. However ensure that number of slots doesn't drop below 32.
2831           */
2832          int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2833                             SPAPR_MAX_RAM_SLOTS;
2834  
2835          if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2836              max_memslots = SPAPR_MAX_RAM_SLOTS;
2837          }
2838          if (machine->ram_slots > max_memslots) {
2839              error_report("Specified number of memory slots %"
2840                           PRIu64" exceeds max supported %d",
2841                           machine->ram_slots, max_memslots);
2842              exit(1);
2843          }
2844  
2845          machine->device_memory->base = ROUND_UP(machine->ram_size,
2846                                                  SPAPR_DEVICE_MEM_ALIGN);
2847          memory_region_init(&machine->device_memory->mr, OBJECT(spapr),
2848                             "device-memory", device_mem_size);
2849          memory_region_add_subregion(sysmem, machine->device_memory->base,
2850                                      &machine->device_memory->mr);
2851      }
2852  
2853      if (smc->dr_lmb_enabled) {
2854          spapr_create_lmb_dr_connectors(spapr);
2855      }
2856  
2857      if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI_MCE) == SPAPR_CAP_ON) {
2858          /* Create the error string for live migration blocker */
2859          error_setg(&spapr->fwnmi_migration_blocker,
2860              "A machine check is being handled during migration. The handler"
2861              "may run and log hardware error on the destination");
2862      }
2863  
2864      /* Set up RTAS event infrastructure */
2865      spapr_events_init(spapr);
2866  
2867      /* Set up the RTC RTAS interfaces */
2868      spapr_rtc_create(spapr);
2869  
2870      /* Set up VIO bus */
2871      spapr->vio_bus = spapr_vio_bus_init();
2872  
2873      for (i = 0; i < serial_max_hds(); i++) {
2874          if (serial_hd(i)) {
2875              spapr_vty_create(spapr->vio_bus, serial_hd(i));
2876          }
2877      }
2878  
2879      /* We always have at least the nvram device on VIO */
2880      spapr_create_nvram(spapr);
2881  
2882      /*
2883       * Setup hotplug / dynamic-reconfiguration connectors. top-level
2884       * connectors (described in root DT node's "ibm,drc-types" property)
2885       * are pre-initialized here. additional child connectors (such as
2886       * connectors for a PHBs PCI slots) are added as needed during their
2887       * parent's realization.
2888       */
2889      if (smc->dr_phb_enabled) {
2890          for (i = 0; i < SPAPR_MAX_PHBS; i++) {
2891              spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i);
2892          }
2893      }
2894  
2895      /* Set up PCI */
2896      spapr_pci_rtas_init();
2897  
2898      phb = spapr_create_default_phb();
2899  
2900      for (i = 0; i < nb_nics; i++) {
2901          NICInfo *nd = &nd_table[i];
2902  
2903          if (!nd->model) {
2904              nd->model = g_strdup("spapr-vlan");
2905          }
2906  
2907          if (g_str_equal(nd->model, "spapr-vlan") ||
2908              g_str_equal(nd->model, "ibmveth")) {
2909              spapr_vlan_create(spapr->vio_bus, nd);
2910          } else {
2911              pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2912          }
2913      }
2914  
2915      for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2916          spapr_vscsi_create(spapr->vio_bus);
2917      }
2918  
2919      /* Graphics */
2920      if (spapr_vga_init(phb->bus, &error_fatal)) {
2921          spapr->has_graphics = true;
2922          machine->usb |= defaults_enabled() && !machine->usb_disabled;
2923      }
2924  
2925      if (machine->usb) {
2926          if (smc->use_ohci_by_default) {
2927              pci_create_simple(phb->bus, -1, "pci-ohci");
2928          } else {
2929              pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2930          }
2931  
2932          if (spapr->has_graphics) {
2933              USBBus *usb_bus = usb_bus_find(-1);
2934  
2935              usb_create_simple(usb_bus, "usb-kbd");
2936              usb_create_simple(usb_bus, "usb-mouse");
2937          }
2938      }
2939  
2940      if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) {
2941          error_report(
2942              "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2943              MIN_RMA_SLOF);
2944          exit(1);
2945      }
2946  
2947      if (kernel_filename) {
2948          uint64_t lowaddr = 0;
2949  
2950          spapr->kernel_size = load_elf(kernel_filename, NULL,
2951                                        translate_kernel_address, NULL,
2952                                        NULL, &lowaddr, NULL, NULL, 1,
2953                                        PPC_ELF_MACHINE, 0, 0);
2954          if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2955              spapr->kernel_size = load_elf(kernel_filename, NULL,
2956                                            translate_kernel_address, NULL, NULL,
2957                                            &lowaddr, NULL, NULL, 0,
2958                                            PPC_ELF_MACHINE, 0, 0);
2959              spapr->kernel_le = spapr->kernel_size > 0;
2960          }
2961          if (spapr->kernel_size < 0) {
2962              error_report("error loading %s: %s", kernel_filename,
2963                           load_elf_strerror(spapr->kernel_size));
2964              exit(1);
2965          }
2966  
2967          /* load initrd */
2968          if (initrd_filename) {
2969              /* Try to locate the initrd in the gap between the kernel
2970               * and the firmware. Add a bit of space just in case
2971               */
2972              spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
2973                                    + 0x1ffff) & ~0xffff;
2974              spapr->initrd_size = load_image_targphys(initrd_filename,
2975                                                       spapr->initrd_base,
2976                                                       load_limit
2977                                                       - spapr->initrd_base);
2978              if (spapr->initrd_size < 0) {
2979                  error_report("could not load initial ram disk '%s'",
2980                               initrd_filename);
2981                  exit(1);
2982              }
2983          }
2984      }
2985  
2986      if (bios_name == NULL) {
2987          bios_name = FW_FILE_NAME;
2988      }
2989      filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2990      if (!filename) {
2991          error_report("Could not find LPAR firmware '%s'", bios_name);
2992          exit(1);
2993      }
2994      fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2995      if (fw_size <= 0) {
2996          error_report("Could not load LPAR firmware '%s'", filename);
2997          exit(1);
2998      }
2999      g_free(filename);
3000  
3001      /* FIXME: Should register things through the MachineState's qdev
3002       * interface, this is a legacy from the sPAPREnvironment structure
3003       * which predated MachineState but had a similar function */
3004      vmstate_register(NULL, 0, &vmstate_spapr, spapr);
3005      register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1,
3006                           &savevm_htab_handlers, spapr);
3007  
3008      qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine),
3009                               &error_fatal);
3010  
3011      qemu_register_boot_set(spapr_boot_set, spapr);
3012  
3013      /*
3014       * Nothing needs to be done to resume a suspended guest because
3015       * suspending does not change the machine state, so no need for
3016       * a ->wakeup method.
3017       */
3018      qemu_register_wakeup_support();
3019  
3020      if (kvm_enabled()) {
3021          /* to stop and start vmclock */
3022          qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
3023                                           &spapr->tb);
3024  
3025          kvmppc_spapr_enable_inkernel_multitce();
3026      }
3027  
3028      qemu_cond_init(&spapr->mc_delivery_cond);
3029  }
3030  
3031  static int spapr_kvm_type(MachineState *machine, const char *vm_type)
3032  {
3033      if (!vm_type) {
3034          return 0;
3035      }
3036  
3037      if (!strcmp(vm_type, "HV")) {
3038          return 1;
3039      }
3040  
3041      if (!strcmp(vm_type, "PR")) {
3042          return 2;
3043      }
3044  
3045      error_report("Unknown kvm-type specified '%s'", vm_type);
3046      exit(1);
3047  }
3048  
3049  /*
3050   * Implementation of an interface to adjust firmware path
3051   * for the bootindex property handling.
3052   */
3053  static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
3054                                     DeviceState *dev)
3055  {
3056  #define CAST(type, obj, name) \
3057      ((type *)object_dynamic_cast(OBJECT(obj), (name)))
3058      SCSIDevice *d = CAST(SCSIDevice,  dev, TYPE_SCSI_DEVICE);
3059      SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
3060      VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON);
3061  
3062      if (d) {
3063          void *spapr = CAST(void, bus->parent, "spapr-vscsi");
3064          VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
3065          USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
3066  
3067          if (spapr) {
3068              /*
3069               * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
3070               * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form
3071               * 0x8000 | (target << 8) | (bus << 5) | lun
3072               * (see the "Logical unit addressing format" table in SAM5)
3073               */
3074              unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun;
3075              return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3076                                     (uint64_t)id << 48);
3077          } else if (virtio) {
3078              /*
3079               * We use SRP luns of the form 01000000 | (target << 8) | lun
3080               * in the top 32 bits of the 64-bit LUN
3081               * Note: the quote above is from SLOF and it is wrong,
3082               * the actual binding is:
3083               * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
3084               */
3085              unsigned id = 0x1000000 | (d->id << 16) | d->lun;
3086              if (d->lun >= 256) {
3087                  /* Use the LUN "flat space addressing method" */
3088                  id |= 0x4000;
3089              }
3090              return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3091                                     (uint64_t)id << 32);
3092          } else if (usb) {
3093              /*
3094               * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
3095               * in the top 32 bits of the 64-bit LUN
3096               */
3097              unsigned usb_port = atoi(usb->port->path);
3098              unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
3099              return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3100                                     (uint64_t)id << 32);
3101          }
3102      }
3103  
3104      /*
3105       * SLOF probes the USB devices, and if it recognizes that the device is a
3106       * storage device, it changes its name to "storage" instead of "usb-host",
3107       * and additionally adds a child node for the SCSI LUN, so the correct
3108       * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
3109       */
3110      if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
3111          USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
3112          if (usb_host_dev_is_scsi_storage(usbdev)) {
3113              return g_strdup_printf("storage@%s/disk", usbdev->port->path);
3114          }
3115      }
3116  
3117      if (phb) {
3118          /* Replace "pci" with "pci@800000020000000" */
3119          return g_strdup_printf("pci@%"PRIX64, phb->buid);
3120      }
3121  
3122      if (vsc) {
3123          /* Same logic as virtio above */
3124          unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun;
3125          return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32);
3126      }
3127  
3128      if (g_str_equal("pci-bridge", qdev_fw_name(dev))) {
3129          /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
3130          PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE);
3131          return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn));
3132      }
3133  
3134      return NULL;
3135  }
3136  
3137  static char *spapr_get_kvm_type(Object *obj, Error **errp)
3138  {
3139      SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3140  
3141      return g_strdup(spapr->kvm_type);
3142  }
3143  
3144  static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
3145  {
3146      SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3147  
3148      g_free(spapr->kvm_type);
3149      spapr->kvm_type = g_strdup(value);
3150  }
3151  
3152  static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
3153  {
3154      SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3155  
3156      return spapr->use_hotplug_event_source;
3157  }
3158  
3159  static void spapr_set_modern_hotplug_events(Object *obj, bool value,
3160                                              Error **errp)
3161  {
3162      SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3163  
3164      spapr->use_hotplug_event_source = value;
3165  }
3166  
3167  static bool spapr_get_msix_emulation(Object *obj, Error **errp)
3168  {
3169      return true;
3170  }
3171  
3172  static char *spapr_get_resize_hpt(Object *obj, Error **errp)
3173  {
3174      SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3175  
3176      switch (spapr->resize_hpt) {
3177      case SPAPR_RESIZE_HPT_DEFAULT:
3178          return g_strdup("default");
3179      case SPAPR_RESIZE_HPT_DISABLED:
3180          return g_strdup("disabled");
3181      case SPAPR_RESIZE_HPT_ENABLED:
3182          return g_strdup("enabled");
3183      case SPAPR_RESIZE_HPT_REQUIRED:
3184          return g_strdup("required");
3185      }
3186      g_assert_not_reached();
3187  }
3188  
3189  static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp)
3190  {
3191      SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3192  
3193      if (strcmp(value, "default") == 0) {
3194          spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT;
3195      } else if (strcmp(value, "disabled") == 0) {
3196          spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
3197      } else if (strcmp(value, "enabled") == 0) {
3198          spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED;
3199      } else if (strcmp(value, "required") == 0) {
3200          spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED;
3201      } else {
3202          error_setg(errp, "Bad value for \"resize-hpt\" property");
3203      }
3204  }
3205  
3206  static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name,
3207                                     void *opaque, Error **errp)
3208  {
3209      visit_type_uint32(v, name, (uint32_t *)opaque, errp);
3210  }
3211  
3212  static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name,
3213                                     void *opaque, Error **errp)
3214  {
3215      visit_type_uint32(v, name, (uint32_t *)opaque, errp);
3216  }
3217  
3218  static char *spapr_get_ic_mode(Object *obj, Error **errp)
3219  {
3220      SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3221  
3222      if (spapr->irq == &spapr_irq_xics_legacy) {
3223          return g_strdup("legacy");
3224      } else if (spapr->irq == &spapr_irq_xics) {
3225          return g_strdup("xics");
3226      } else if (spapr->irq == &spapr_irq_xive) {
3227          return g_strdup("xive");
3228      } else if (spapr->irq == &spapr_irq_dual) {
3229          return g_strdup("dual");
3230      }
3231      g_assert_not_reached();
3232  }
3233  
3234  static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp)
3235  {
3236      SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3237  
3238      if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
3239          error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode");
3240          return;
3241      }
3242  
3243      /* The legacy IRQ backend can not be set */
3244      if (strcmp(value, "xics") == 0) {
3245          spapr->irq = &spapr_irq_xics;
3246      } else if (strcmp(value, "xive") == 0) {
3247          spapr->irq = &spapr_irq_xive;
3248      } else if (strcmp(value, "dual") == 0) {
3249          spapr->irq = &spapr_irq_dual;
3250      } else {
3251          error_setg(errp, "Bad value for \"ic-mode\" property");
3252      }
3253  }
3254  
3255  static char *spapr_get_host_model(Object *obj, Error **errp)
3256  {
3257      SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3258  
3259      return g_strdup(spapr->host_model);
3260  }
3261  
3262  static void spapr_set_host_model(Object *obj, const char *value, Error **errp)
3263  {
3264      SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3265  
3266      g_free(spapr->host_model);
3267      spapr->host_model = g_strdup(value);
3268  }
3269  
3270  static char *spapr_get_host_serial(Object *obj, Error **errp)
3271  {
3272      SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3273  
3274      return g_strdup(spapr->host_serial);
3275  }
3276  
3277  static void spapr_set_host_serial(Object *obj, const char *value, Error **errp)
3278  {
3279      SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3280  
3281      g_free(spapr->host_serial);
3282      spapr->host_serial = g_strdup(value);
3283  }
3284  
3285  static void spapr_instance_init(Object *obj)
3286  {
3287      SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3288      SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
3289  
3290      spapr->htab_fd = -1;
3291      spapr->use_hotplug_event_source = true;
3292      object_property_add_str(obj, "kvm-type",
3293                              spapr_get_kvm_type, spapr_set_kvm_type, NULL);
3294      object_property_set_description(obj, "kvm-type",
3295                                      "Specifies the KVM virtualization mode (HV, PR)",
3296                                      NULL);
3297      object_property_add_bool(obj, "modern-hotplug-events",
3298                              spapr_get_modern_hotplug_events,
3299                              spapr_set_modern_hotplug_events,
3300                              NULL);
3301      object_property_set_description(obj, "modern-hotplug-events",
3302                                      "Use dedicated hotplug event mechanism in"
3303                                      " place of standard EPOW events when possible"
3304                                      " (required for memory hot-unplug support)",
3305                                      NULL);
3306      ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr,
3307                              "Maximum permitted CPU compatibility mode",
3308                              &error_fatal);
3309  
3310      object_property_add_str(obj, "resize-hpt",
3311                              spapr_get_resize_hpt, spapr_set_resize_hpt, NULL);
3312      object_property_set_description(obj, "resize-hpt",
3313                                      "Resizing of the Hash Page Table (enabled, disabled, required)",
3314                                      NULL);
3315      object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt,
3316                          spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort);
3317      object_property_set_description(obj, "vsmt",
3318                                      "Virtual SMT: KVM behaves as if this were"
3319                                      " the host's SMT mode", &error_abort);
3320      object_property_add_bool(obj, "vfio-no-msix-emulation",
3321                               spapr_get_msix_emulation, NULL, NULL);
3322  
3323      /* The machine class defines the default interrupt controller mode */
3324      spapr->irq = smc->irq;
3325      object_property_add_str(obj, "ic-mode", spapr_get_ic_mode,
3326                              spapr_set_ic_mode, NULL);
3327      object_property_set_description(obj, "ic-mode",
3328                   "Specifies the interrupt controller mode (xics, xive, dual)",
3329                   NULL);
3330  
3331      object_property_add_str(obj, "host-model",
3332          spapr_get_host_model, spapr_set_host_model,
3333          &error_abort);
3334      object_property_set_description(obj, "host-model",
3335          "Host model to advertise in guest device tree", &error_abort);
3336      object_property_add_str(obj, "host-serial",
3337          spapr_get_host_serial, spapr_set_host_serial,
3338          &error_abort);
3339      object_property_set_description(obj, "host-serial",
3340          "Host serial number to advertise in guest device tree", &error_abort);
3341  }
3342  
3343  static void spapr_machine_finalizefn(Object *obj)
3344  {
3345      SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3346  
3347      g_free(spapr->kvm_type);
3348  }
3349  
3350  void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
3351  {
3352      cpu_synchronize_state(cs);
3353      ppc_cpu_do_system_reset(cs);
3354  }
3355  
3356  static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
3357  {
3358      CPUState *cs;
3359  
3360      CPU_FOREACH(cs) {
3361          async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
3362      }
3363  }
3364  
3365  int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
3366                            void *fdt, int *fdt_start_offset, Error **errp)
3367  {
3368      uint64_t addr;
3369      uint32_t node;
3370  
3371      addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE;
3372      node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP,
3373                                      &error_abort);
3374      *fdt_start_offset = spapr_populate_memory_node(fdt, node, addr,
3375                                                     SPAPR_MEMORY_BLOCK_SIZE);
3376      return 0;
3377  }
3378  
3379  static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
3380                             bool dedicated_hp_event_source, Error **errp)
3381  {
3382      SpaprDrc *drc;
3383      uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
3384      int i;
3385      uint64_t addr = addr_start;
3386      bool hotplugged = spapr_drc_hotplugged(dev);
3387      Error *local_err = NULL;
3388  
3389      for (i = 0; i < nr_lmbs; i++) {
3390          drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3391                                addr / SPAPR_MEMORY_BLOCK_SIZE);
3392          g_assert(drc);
3393  
3394          spapr_drc_attach(drc, dev, &local_err);
3395          if (local_err) {
3396              while (addr > addr_start) {
3397                  addr -= SPAPR_MEMORY_BLOCK_SIZE;
3398                  drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3399                                        addr / SPAPR_MEMORY_BLOCK_SIZE);
3400                  spapr_drc_detach(drc);
3401              }
3402              error_propagate(errp, local_err);
3403              return;
3404          }
3405          if (!hotplugged) {
3406              spapr_drc_reset(drc);
3407          }
3408          addr += SPAPR_MEMORY_BLOCK_SIZE;
3409      }
3410      /* send hotplug notification to the
3411       * guest only in case of hotplugged memory
3412       */
3413      if (hotplugged) {
3414          if (dedicated_hp_event_source) {
3415              drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3416                                    addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3417              spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3418                                                     nr_lmbs,
3419                                                     spapr_drc_index(drc));
3420          } else {
3421              spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
3422                                             nr_lmbs);
3423          }
3424      }
3425  }
3426  
3427  static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3428                                Error **errp)
3429  {
3430      Error *local_err = NULL;
3431      SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev);
3432      PCDIMMDevice *dimm = PC_DIMM(dev);
3433      uint64_t size, addr;
3434  
3435      size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort);
3436  
3437      pc_dimm_plug(dimm, MACHINE(ms), &local_err);
3438      if (local_err) {
3439          goto out;
3440      }
3441  
3442      addr = object_property_get_uint(OBJECT(dimm),
3443                                      PC_DIMM_ADDR_PROP, &local_err);
3444      if (local_err) {
3445          goto out_unplug;
3446      }
3447  
3448      spapr_add_lmbs(dev, addr, size, spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
3449                     &local_err);
3450      if (local_err) {
3451          goto out_unplug;
3452      }
3453  
3454      return;
3455  
3456  out_unplug:
3457      pc_dimm_unplug(dimm, MACHINE(ms));
3458  out:
3459      error_propagate(errp, local_err);
3460  }
3461  
3462  static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3463                                    Error **errp)
3464  {
3465      const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev);
3466      SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3467      PCDIMMDevice *dimm = PC_DIMM(dev);
3468      Error *local_err = NULL;
3469      uint64_t size;
3470      Object *memdev;
3471      hwaddr pagesize;
3472  
3473      if (!smc->dr_lmb_enabled) {
3474          error_setg(errp, "Memory hotplug not supported for this machine");
3475          return;
3476      }
3477  
3478      size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err);
3479      if (local_err) {
3480          error_propagate(errp, local_err);
3481          return;
3482      }
3483  
3484      if (size % SPAPR_MEMORY_BLOCK_SIZE) {
3485          error_setg(errp, "Hotplugged memory size must be a multiple of "
3486                        "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB);
3487          return;
3488      }
3489  
3490      memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP,
3491                                        &error_abort);
3492      pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev));
3493      spapr_check_pagesize(spapr, pagesize, &local_err);
3494      if (local_err) {
3495          error_propagate(errp, local_err);
3496          return;
3497      }
3498  
3499      pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp);
3500  }
3501  
3502  struct SpaprDimmState {
3503      PCDIMMDevice *dimm;
3504      uint32_t nr_lmbs;
3505      QTAILQ_ENTRY(SpaprDimmState) next;
3506  };
3507  
3508  static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s,
3509                                                         PCDIMMDevice *dimm)
3510  {
3511      SpaprDimmState *dimm_state = NULL;
3512  
3513      QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) {
3514          if (dimm_state->dimm == dimm) {
3515              break;
3516          }
3517      }
3518      return dimm_state;
3519  }
3520  
3521  static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr,
3522                                                        uint32_t nr_lmbs,
3523                                                        PCDIMMDevice *dimm)
3524  {
3525      SpaprDimmState *ds = NULL;
3526  
3527      /*
3528       * If this request is for a DIMM whose removal had failed earlier
3529       * (due to guest's refusal to remove the LMBs), we would have this
3530       * dimm already in the pending_dimm_unplugs list. In that
3531       * case don't add again.
3532       */
3533      ds = spapr_pending_dimm_unplugs_find(spapr, dimm);
3534      if (!ds) {
3535          ds = g_malloc0(sizeof(SpaprDimmState));
3536          ds->nr_lmbs = nr_lmbs;
3537          ds->dimm = dimm;
3538          QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next);
3539      }
3540      return ds;
3541  }
3542  
3543  static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr,
3544                                                SpaprDimmState *dimm_state)
3545  {
3546      QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next);
3547      g_free(dimm_state);
3548  }
3549  
3550  static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms,
3551                                                          PCDIMMDevice *dimm)
3552  {
3553      SpaprDrc *drc;
3554      uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm),
3555                                                    &error_abort);
3556      uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3557      uint32_t avail_lmbs = 0;
3558      uint64_t addr_start, addr;
3559      int i;
3560  
3561      addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3562                                           &error_abort);
3563  
3564      addr = addr_start;
3565      for (i = 0; i < nr_lmbs; i++) {
3566          drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3567                                addr / SPAPR_MEMORY_BLOCK_SIZE);
3568          g_assert(drc);
3569          if (drc->dev) {
3570              avail_lmbs++;
3571          }
3572          addr += SPAPR_MEMORY_BLOCK_SIZE;
3573      }
3574  
3575      return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm);
3576  }
3577  
3578  /* Callback to be called during DRC release. */
3579  void spapr_lmb_release(DeviceState *dev)
3580  {
3581      HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
3582      SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl);
3583      SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3584  
3585      /* This information will get lost if a migration occurs
3586       * during the unplug process. In this case recover it. */
3587      if (ds == NULL) {
3588          ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev));
3589          g_assert(ds);
3590          /* The DRC being examined by the caller at least must be counted */
3591          g_assert(ds->nr_lmbs);
3592      }
3593  
3594      if (--ds->nr_lmbs) {
3595          return;
3596      }
3597  
3598      /*
3599       * Now that all the LMBs have been removed by the guest, call the
3600       * unplug handler chain. This can never fail.
3601       */
3602      hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
3603      object_unparent(OBJECT(dev));
3604  }
3605  
3606  static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
3607  {
3608      SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3609      SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3610  
3611      pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev));
3612      object_property_set_bool(OBJECT(dev), false, "realized", NULL);
3613      spapr_pending_dimm_unplugs_remove(spapr, ds);
3614  }
3615  
3616  static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
3617                                          DeviceState *dev, Error **errp)
3618  {
3619      SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3620      Error *local_err = NULL;
3621      PCDIMMDevice *dimm = PC_DIMM(dev);
3622      uint32_t nr_lmbs;
3623      uint64_t size, addr_start, addr;
3624      int i;
3625      SpaprDrc *drc;
3626  
3627      size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort);
3628      nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3629  
3630      addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3631                                           &local_err);
3632      if (local_err) {
3633          goto out;
3634      }
3635  
3636      /*
3637       * An existing pending dimm state for this DIMM means that there is an
3638       * unplug operation in progress, waiting for the spapr_lmb_release
3639       * callback to complete the job (BQL can't cover that far). In this case,
3640       * bail out to avoid detaching DRCs that were already released.
3641       */
3642      if (spapr_pending_dimm_unplugs_find(spapr, dimm)) {
3643          error_setg(&local_err,
3644                     "Memory unplug already in progress for device %s",
3645                     dev->id);
3646          goto out;
3647      }
3648  
3649      spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm);
3650  
3651      addr = addr_start;
3652      for (i = 0; i < nr_lmbs; i++) {
3653          drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3654                                addr / SPAPR_MEMORY_BLOCK_SIZE);
3655          g_assert(drc);
3656  
3657          spapr_drc_detach(drc);
3658          addr += SPAPR_MEMORY_BLOCK_SIZE;
3659      }
3660  
3661      drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3662                            addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3663      spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3664                                                nr_lmbs, spapr_drc_index(drc));
3665  out:
3666      error_propagate(errp, local_err);
3667  }
3668  
3669  /* Callback to be called during DRC release. */
3670  void spapr_core_release(DeviceState *dev)
3671  {
3672      HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
3673  
3674      /* Call the unplug handler chain. This can never fail. */
3675      hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
3676      object_unparent(OBJECT(dev));
3677  }
3678  
3679  static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
3680  {
3681      MachineState *ms = MACHINE(hotplug_dev);
3682      SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
3683      CPUCore *cc = CPU_CORE(dev);
3684      CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
3685  
3686      if (smc->pre_2_10_has_unused_icps) {
3687          SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
3688          int i;
3689  
3690          for (i = 0; i < cc->nr_threads; i++) {
3691              CPUState *cs = CPU(sc->threads[i]);
3692  
3693              pre_2_10_vmstate_register_dummy_icp(cs->cpu_index);
3694          }
3695      }
3696  
3697      assert(core_slot);
3698      core_slot->cpu = NULL;
3699      object_property_set_bool(OBJECT(dev), false, "realized", NULL);
3700  }
3701  
3702  static
3703  void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
3704                                 Error **errp)
3705  {
3706      SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3707      int index;
3708      SpaprDrc *drc;
3709      CPUCore *cc = CPU_CORE(dev);
3710  
3711      if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
3712          error_setg(errp, "Unable to find CPU core with core-id: %d",
3713                     cc->core_id);
3714          return;
3715      }
3716      if (index == 0) {
3717          error_setg(errp, "Boot CPU core may not be unplugged");
3718          return;
3719      }
3720  
3721      drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3722                            spapr_vcpu_id(spapr, cc->core_id));
3723      g_assert(drc);
3724  
3725      if (!spapr_drc_unplug_requested(drc)) {
3726          spapr_drc_detach(drc);
3727          spapr_hotplug_req_remove_by_index(drc);
3728      }
3729  }
3730  
3731  int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
3732                             void *fdt, int *fdt_start_offset, Error **errp)
3733  {
3734      SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev);
3735      CPUState *cs = CPU(core->threads[0]);
3736      PowerPCCPU *cpu = POWERPC_CPU(cs);
3737      DeviceClass *dc = DEVICE_GET_CLASS(cs);
3738      int id = spapr_get_vcpu_id(cpu);
3739      char *nodename;
3740      int offset;
3741  
3742      nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
3743      offset = fdt_add_subnode(fdt, 0, nodename);
3744      g_free(nodename);
3745  
3746      spapr_populate_cpu_dt(cs, fdt, offset, spapr);
3747  
3748      *fdt_start_offset = offset;
3749      return 0;
3750  }
3751  
3752  static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3753                              Error **errp)
3754  {
3755      SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3756      MachineClass *mc = MACHINE_GET_CLASS(spapr);
3757      SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3758      SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev));
3759      CPUCore *cc = CPU_CORE(dev);
3760      CPUState *cs;
3761      SpaprDrc *drc;
3762      Error *local_err = NULL;
3763      CPUArchId *core_slot;
3764      int index;
3765      bool hotplugged = spapr_drc_hotplugged(dev);
3766      int i;
3767  
3768      core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3769      if (!core_slot) {
3770          error_setg(errp, "Unable to find CPU core with core-id: %d",
3771                     cc->core_id);
3772          return;
3773      }
3774      drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3775                            spapr_vcpu_id(spapr, cc->core_id));
3776  
3777      g_assert(drc || !mc->has_hotpluggable_cpus);
3778  
3779      if (drc) {
3780          spapr_drc_attach(drc, dev, &local_err);
3781          if (local_err) {
3782              error_propagate(errp, local_err);
3783              return;
3784          }
3785  
3786          if (hotplugged) {
3787              /*
3788               * Send hotplug notification interrupt to the guest only
3789               * in case of hotplugged CPUs.
3790               */
3791              spapr_hotplug_req_add_by_index(drc);
3792          } else {
3793              spapr_drc_reset(drc);
3794          }
3795      }
3796  
3797      core_slot->cpu = OBJECT(dev);
3798  
3799      if (smc->pre_2_10_has_unused_icps) {
3800          for (i = 0; i < cc->nr_threads; i++) {
3801              cs = CPU(core->threads[i]);
3802              pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index);
3803          }
3804      }
3805  
3806      /*
3807       * Set compatibility mode to match the boot CPU, which was either set
3808       * by the machine reset code or by CAS.
3809       */
3810      if (hotplugged) {
3811          for (i = 0; i < cc->nr_threads; i++) {
3812              ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr,
3813                             &local_err);
3814              if (local_err) {
3815                  error_propagate(errp, local_err);
3816                  return;
3817              }
3818          }
3819      }
3820  }
3821  
3822  static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3823                                  Error **errp)
3824  {
3825      MachineState *machine = MACHINE(OBJECT(hotplug_dev));
3826      MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
3827      Error *local_err = NULL;
3828      CPUCore *cc = CPU_CORE(dev);
3829      const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type);
3830      const char *type = object_get_typename(OBJECT(dev));
3831      CPUArchId *core_slot;
3832      int index;
3833      unsigned int smp_threads = machine->smp.threads;
3834  
3835      if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
3836          error_setg(&local_err, "CPU hotplug not supported for this machine");
3837          goto out;
3838      }
3839  
3840      if (strcmp(base_core_type, type)) {
3841          error_setg(&local_err, "CPU core type should be %s", base_core_type);
3842          goto out;
3843      }
3844  
3845      if (cc->core_id % smp_threads) {
3846          error_setg(&local_err, "invalid core id %d", cc->core_id);
3847          goto out;
3848      }
3849  
3850      /*
3851       * In general we should have homogeneous threads-per-core, but old
3852       * (pre hotplug support) machine types allow the last core to have
3853       * reduced threads as a compatibility hack for when we allowed
3854       * total vcpus not a multiple of threads-per-core.
3855       */
3856      if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) {
3857          error_setg(&local_err, "invalid nr-threads %d, must be %d",
3858                     cc->nr_threads, smp_threads);
3859          goto out;
3860      }
3861  
3862      core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3863      if (!core_slot) {
3864          error_setg(&local_err, "core id %d out of range", cc->core_id);
3865          goto out;
3866      }
3867  
3868      if (core_slot->cpu) {
3869          error_setg(&local_err, "core %d already populated", cc->core_id);
3870          goto out;
3871      }
3872  
3873      numa_cpu_pre_plug(core_slot, dev, &local_err);
3874  
3875  out:
3876      error_propagate(errp, local_err);
3877  }
3878  
3879  int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
3880                            void *fdt, int *fdt_start_offset, Error **errp)
3881  {
3882      SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev);
3883      int intc_phandle;
3884  
3885      intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp);
3886      if (intc_phandle <= 0) {
3887          return -1;
3888      }
3889  
3890      if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) {
3891          error_setg(errp, "unable to create FDT node for PHB %d", sphb->index);
3892          return -1;
3893      }
3894  
3895      /* generally SLOF creates these, for hotplug it's up to QEMU */
3896      _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci"));
3897  
3898      return 0;
3899  }
3900  
3901  static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3902                                 Error **errp)
3903  {
3904      SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3905      SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev);
3906      SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
3907      const unsigned windows_supported = spapr_phb_windows_supported(sphb);
3908  
3909      if (dev->hotplugged && !smc->dr_phb_enabled) {
3910          error_setg(errp, "PHB hotplug not supported for this machine");
3911          return;
3912      }
3913  
3914      if (sphb->index == (uint32_t)-1) {
3915          error_setg(errp, "\"index\" for PAPR PHB is mandatory");
3916          return;
3917      }
3918  
3919      /*
3920       * This will check that sphb->index doesn't exceed the maximum number of
3921       * PHBs for the current machine type.
3922       */
3923      smc->phb_placement(spapr, sphb->index,
3924                         &sphb->buid, &sphb->io_win_addr,
3925                         &sphb->mem_win_addr, &sphb->mem64_win_addr,
3926                         windows_supported, sphb->dma_liobn,
3927                         &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr,
3928                         errp);
3929  }
3930  
3931  static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3932                             Error **errp)
3933  {
3934      SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3935      SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
3936      SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev);
3937      SpaprDrc *drc;
3938      bool hotplugged = spapr_drc_hotplugged(dev);
3939      Error *local_err = NULL;
3940  
3941      if (!smc->dr_phb_enabled) {
3942          return;
3943      }
3944  
3945      drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index);
3946      /* hotplug hooks should check it's enabled before getting this far */
3947      assert(drc);
3948  
3949      spapr_drc_attach(drc, DEVICE(dev), &local_err);
3950      if (local_err) {
3951          error_propagate(errp, local_err);
3952          return;
3953      }
3954  
3955      if (hotplugged) {
3956          spapr_hotplug_req_add_by_index(drc);
3957      } else {
3958          spapr_drc_reset(drc);
3959      }
3960  }
3961  
3962  void spapr_phb_release(DeviceState *dev)
3963  {
3964      HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
3965  
3966      hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
3967      object_unparent(OBJECT(dev));
3968  }
3969  
3970  static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
3971  {
3972      object_property_set_bool(OBJECT(dev), false, "realized", NULL);
3973  }
3974  
3975  static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev,
3976                                       DeviceState *dev, Error **errp)
3977  {
3978      SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev);
3979      SpaprDrc *drc;
3980  
3981      drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index);
3982      assert(drc);
3983  
3984      if (!spapr_drc_unplug_requested(drc)) {
3985          spapr_drc_detach(drc);
3986          spapr_hotplug_req_remove_by_index(drc);
3987      }
3988  }
3989  
3990  static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3991                                   Error **errp)
3992  {
3993      SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3994      SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev);
3995  
3996      if (spapr->tpm_proxy != NULL) {
3997          error_setg(errp, "Only one TPM proxy can be specified for this machine");
3998          return;
3999      }
4000  
4001      spapr->tpm_proxy = tpm_proxy;
4002  }
4003  
4004  static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
4005  {
4006      SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
4007  
4008      object_property_set_bool(OBJECT(dev), false, "realized", NULL);
4009      object_unparent(OBJECT(dev));
4010      spapr->tpm_proxy = NULL;
4011  }
4012  
4013  static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
4014                                        DeviceState *dev, Error **errp)
4015  {
4016      if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4017          spapr_memory_plug(hotplug_dev, dev, errp);
4018      } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
4019          spapr_core_plug(hotplug_dev, dev, errp);
4020      } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4021          spapr_phb_plug(hotplug_dev, dev, errp);
4022      } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) {
4023          spapr_tpm_proxy_plug(hotplug_dev, dev, errp);
4024      }
4025  }
4026  
4027  static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
4028                                          DeviceState *dev, Error **errp)
4029  {
4030      if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4031          spapr_memory_unplug(hotplug_dev, dev);
4032      } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
4033          spapr_core_unplug(hotplug_dev, dev);
4034      } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4035          spapr_phb_unplug(hotplug_dev, dev);
4036      } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) {
4037          spapr_tpm_proxy_unplug(hotplug_dev, dev);
4038      }
4039  }
4040  
4041  static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
4042                                                  DeviceState *dev, Error **errp)
4043  {
4044      SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev));
4045      MachineClass *mc = MACHINE_GET_CLASS(sms);
4046      SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4047  
4048      if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4049          if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
4050              spapr_memory_unplug_request(hotplug_dev, dev, errp);
4051          } else {
4052              /* NOTE: this means there is a window after guest reset, prior to
4053               * CAS negotiation, where unplug requests will fail due to the
4054               * capability not being detected yet. This is a bit different than
4055               * the case with PCI unplug, where the events will be queued and
4056               * eventually handled by the guest after boot
4057               */
4058              error_setg(errp, "Memory hot unplug not supported for this guest");
4059          }
4060      } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
4061          if (!mc->has_hotpluggable_cpus) {
4062              error_setg(errp, "CPU hot unplug not supported on this machine");
4063              return;
4064          }
4065          spapr_core_unplug_request(hotplug_dev, dev, errp);
4066      } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4067          if (!smc->dr_phb_enabled) {
4068              error_setg(errp, "PHB hot unplug not supported on this machine");
4069              return;
4070          }
4071          spapr_phb_unplug_request(hotplug_dev, dev, errp);
4072      } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) {
4073          spapr_tpm_proxy_unplug(hotplug_dev, dev);
4074      }
4075  }
4076  
4077  static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
4078                                            DeviceState *dev, Error **errp)
4079  {
4080      if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4081          spapr_memory_pre_plug(hotplug_dev, dev, errp);
4082      } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
4083          spapr_core_pre_plug(hotplug_dev, dev, errp);
4084      } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4085          spapr_phb_pre_plug(hotplug_dev, dev, errp);
4086      }
4087  }
4088  
4089  static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
4090                                                   DeviceState *dev)
4091  {
4092      if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
4093          object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) ||
4094          object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) ||
4095          object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) {
4096          return HOTPLUG_HANDLER(machine);
4097      }
4098      if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
4099          PCIDevice *pcidev = PCI_DEVICE(dev);
4100          PCIBus *root = pci_device_root_bus(pcidev);
4101          SpaprPhbState *phb =
4102              (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent),
4103                                                   TYPE_SPAPR_PCI_HOST_BRIDGE);
4104  
4105          if (phb) {
4106              return HOTPLUG_HANDLER(phb);
4107          }
4108      }
4109      return NULL;
4110  }
4111  
4112  static CpuInstanceProperties
4113  spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index)
4114  {
4115      CPUArchId *core_slot;
4116      MachineClass *mc = MACHINE_GET_CLASS(machine);
4117  
4118      /* make sure possible_cpu are intialized */
4119      mc->possible_cpu_arch_ids(machine);
4120      /* get CPU core slot containing thread that matches cpu_index */
4121      core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL);
4122      assert(core_slot);
4123      return core_slot->props;
4124  }
4125  
4126  static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx)
4127  {
4128      return idx / ms->smp.cores % ms->numa_state->num_nodes;
4129  }
4130  
4131  static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
4132  {
4133      int i;
4134      unsigned int smp_threads = machine->smp.threads;
4135      unsigned int smp_cpus = machine->smp.cpus;
4136      const char *core_type;
4137      int spapr_max_cores = machine->smp.max_cpus / smp_threads;
4138      MachineClass *mc = MACHINE_GET_CLASS(machine);
4139  
4140      if (!mc->has_hotpluggable_cpus) {
4141          spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
4142      }
4143      if (machine->possible_cpus) {
4144          assert(machine->possible_cpus->len == spapr_max_cores);
4145          return machine->possible_cpus;
4146      }
4147  
4148      core_type = spapr_get_cpu_core_type(machine->cpu_type);
4149      if (!core_type) {
4150          error_report("Unable to find sPAPR CPU Core definition");
4151          exit(1);
4152      }
4153  
4154      machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
4155                               sizeof(CPUArchId) * spapr_max_cores);
4156      machine->possible_cpus->len = spapr_max_cores;
4157      for (i = 0; i < machine->possible_cpus->len; i++) {
4158          int core_id = i * smp_threads;
4159  
4160          machine->possible_cpus->cpus[i].type = core_type;
4161          machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
4162          machine->possible_cpus->cpus[i].arch_id = core_id;
4163          machine->possible_cpus->cpus[i].props.has_core_id = true;
4164          machine->possible_cpus->cpus[i].props.core_id = core_id;
4165      }
4166      return machine->possible_cpus;
4167  }
4168  
4169  static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index,
4170                                  uint64_t *buid, hwaddr *pio,
4171                                  hwaddr *mmio32, hwaddr *mmio64,
4172                                  unsigned n_dma, uint32_t *liobns,
4173                                  hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp)
4174  {
4175      /*
4176       * New-style PHB window placement.
4177       *
4178       * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
4179       * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
4180       * windows.
4181       *
4182       * Some guest kernels can't work with MMIO windows above 1<<46
4183       * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
4184       *
4185       * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
4186       * PHB stacked together.  (32TiB+2GiB)..(32TiB+64GiB) contains the
4187       * 2GiB 32-bit MMIO windows for each PHB.  Then 33..64TiB has the
4188       * 1TiB 64-bit MMIO windows for each PHB.
4189       */
4190      const uint64_t base_buid = 0x800000020000000ULL;
4191      int i;
4192  
4193      /* Sanity check natural alignments */
4194      QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
4195      QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
4196      QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
4197      QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
4198      /* Sanity check bounds */
4199      QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) >
4200                        SPAPR_PCI_MEM32_WIN_SIZE);
4201      QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) >
4202                        SPAPR_PCI_MEM64_WIN_SIZE);
4203  
4204      if (index >= SPAPR_MAX_PHBS) {
4205          error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)",
4206                     SPAPR_MAX_PHBS - 1);
4207          return;
4208      }
4209  
4210      *buid = base_buid + index;
4211      for (i = 0; i < n_dma; ++i) {
4212          liobns[i] = SPAPR_PCI_LIOBN(index, i);
4213      }
4214  
4215      *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
4216      *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
4217      *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
4218  
4219      *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE;
4220      *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE;
4221  }
4222  
4223  static ICSState *spapr_ics_get(XICSFabric *dev, int irq)
4224  {
4225      SpaprMachineState *spapr = SPAPR_MACHINE(dev);
4226  
4227      return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL;
4228  }
4229  
4230  static void spapr_ics_resend(XICSFabric *dev)
4231  {
4232      SpaprMachineState *spapr = SPAPR_MACHINE(dev);
4233  
4234      ics_resend(spapr->ics);
4235  }
4236  
4237  static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id)
4238  {
4239      PowerPCCPU *cpu = spapr_find_cpu(vcpu_id);
4240  
4241      return cpu ? spapr_cpu_state(cpu)->icp : NULL;
4242  }
4243  
4244  static void spapr_pic_print_info(InterruptStatsProvider *obj,
4245                                   Monitor *mon)
4246  {
4247      SpaprMachineState *spapr = SPAPR_MACHINE(obj);
4248  
4249      spapr_irq_print_info(spapr, mon);
4250      monitor_printf(mon, "irqchip: %s\n",
4251                     kvm_irqchip_in_kernel() ? "in-kernel" : "emulated");
4252  }
4253  
4254  /*
4255   * This is a XIVE only operation
4256   */
4257  static int spapr_match_nvt(XiveFabric *xfb, uint8_t format,
4258                             uint8_t nvt_blk, uint32_t nvt_idx,
4259                             bool cam_ignore, uint8_t priority,
4260                             uint32_t logic_serv, XiveTCTXMatch *match)
4261  {
4262      SpaprMachineState *spapr = SPAPR_MACHINE(xfb);
4263      XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc);
4264      XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
4265      int count;
4266  
4267      count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
4268                             priority, logic_serv, match);
4269      if (count < 0) {
4270          return count;
4271      }
4272  
4273      /*
4274       * When we implement the save and restore of the thread interrupt
4275       * contexts in the enter/exit CPU handlers of the machine and the
4276       * escalations in QEMU, we should be able to handle non dispatched
4277       * vCPUs.
4278       *
4279       * Until this is done, the sPAPR machine should find at least one
4280       * matching context always.
4281       */
4282      if (count == 0) {
4283          qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n",
4284                        nvt_blk, nvt_idx);
4285      }
4286  
4287      return count;
4288  }
4289  
4290  int spapr_get_vcpu_id(PowerPCCPU *cpu)
4291  {
4292      return cpu->vcpu_id;
4293  }
4294  
4295  void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp)
4296  {
4297      SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
4298      MachineState *ms = MACHINE(spapr);
4299      int vcpu_id;
4300  
4301      vcpu_id = spapr_vcpu_id(spapr, cpu_index);
4302  
4303      if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) {
4304          error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id);
4305          error_append_hint(errp, "Adjust the number of cpus to %d "
4306                            "or try to raise the number of threads per core\n",
4307                            vcpu_id * ms->smp.threads / spapr->vsmt);
4308          return;
4309      }
4310  
4311      cpu->vcpu_id = vcpu_id;
4312  }
4313  
4314  PowerPCCPU *spapr_find_cpu(int vcpu_id)
4315  {
4316      CPUState *cs;
4317  
4318      CPU_FOREACH(cs) {
4319          PowerPCCPU *cpu = POWERPC_CPU(cs);
4320  
4321          if (spapr_get_vcpu_id(cpu) == vcpu_id) {
4322              return cpu;
4323          }
4324      }
4325  
4326      return NULL;
4327  }
4328  
4329  static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
4330  {
4331      SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
4332  
4333      /* These are only called by TCG, KVM maintains dispatch state */
4334  
4335      spapr_cpu->prod = false;
4336      if (spapr_cpu->vpa_addr) {
4337          CPUState *cs = CPU(cpu);
4338          uint32_t dispatch;
4339  
4340          dispatch = ldl_be_phys(cs->as,
4341                                 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER);
4342          dispatch++;
4343          if ((dispatch & 1) != 0) {
4344              qemu_log_mask(LOG_GUEST_ERROR,
4345                            "VPA: incorrect dispatch counter value for "
4346                            "dispatched partition %u, correcting.\n", dispatch);
4347              dispatch++;
4348          }
4349          stl_be_phys(cs->as,
4350                      spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch);
4351      }
4352  }
4353  
4354  static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
4355  {
4356      SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
4357  
4358      if (spapr_cpu->vpa_addr) {
4359          CPUState *cs = CPU(cpu);
4360          uint32_t dispatch;
4361  
4362          dispatch = ldl_be_phys(cs->as,
4363                                 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER);
4364          dispatch++;
4365          if ((dispatch & 1) != 1) {
4366              qemu_log_mask(LOG_GUEST_ERROR,
4367                            "VPA: incorrect dispatch counter value for "
4368                            "preempted partition %u, correcting.\n", dispatch);
4369              dispatch++;
4370          }
4371          stl_be_phys(cs->as,
4372                      spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch);
4373      }
4374  }
4375  
4376  static void spapr_machine_class_init(ObjectClass *oc, void *data)
4377  {
4378      MachineClass *mc = MACHINE_CLASS(oc);
4379      SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
4380      FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
4381      NMIClass *nc = NMI_CLASS(oc);
4382      HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
4383      PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
4384      XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
4385      InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
4386      XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
4387  
4388      mc->desc = "pSeries Logical Partition (PAPR compliant)";
4389      mc->ignore_boot_device_suffixes = true;
4390  
4391      /*
4392       * We set up the default / latest behaviour here.  The class_init
4393       * functions for the specific versioned machine types can override
4394       * these details for backwards compatibility
4395       */
4396      mc->init = spapr_machine_init;
4397      mc->reset = spapr_machine_reset;
4398      mc->block_default_type = IF_SCSI;
4399      mc->max_cpus = 1024;
4400      mc->no_parallel = 1;
4401      mc->default_boot_order = "";
4402      mc->default_ram_size = 512 * MiB;
4403      mc->default_display = "std";
4404      mc->kvm_type = spapr_kvm_type;
4405      machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE);
4406      mc->pci_allow_0_address = true;
4407      assert(!mc->get_hotplug_handler);
4408      mc->get_hotplug_handler = spapr_get_hotplug_handler;
4409      hc->pre_plug = spapr_machine_device_pre_plug;
4410      hc->plug = spapr_machine_device_plug;
4411      mc->cpu_index_to_instance_props = spapr_cpu_index_to_props;
4412      mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id;
4413      mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
4414      hc->unplug_request = spapr_machine_device_unplug_request;
4415      hc->unplug = spapr_machine_device_unplug;
4416  
4417      smc->dr_lmb_enabled = true;
4418      smc->update_dt_enabled = true;
4419      mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
4420      mc->has_hotpluggable_cpus = true;
4421      smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
4422      fwc->get_dev_path = spapr_get_fw_dev_path;
4423      nc->nmi_monitor_handler = spapr_nmi;
4424      smc->phb_placement = spapr_phb_placement;
4425      vhc->hypercall = emulate_spapr_hypercall;
4426      vhc->hpt_mask = spapr_hpt_mask;
4427      vhc->map_hptes = spapr_map_hptes;
4428      vhc->unmap_hptes = spapr_unmap_hptes;
4429      vhc->hpte_set_c = spapr_hpte_set_c;
4430      vhc->hpte_set_r = spapr_hpte_set_r;
4431      vhc->get_pate = spapr_get_pate;
4432      vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr;
4433      vhc->cpu_exec_enter = spapr_cpu_exec_enter;
4434      vhc->cpu_exec_exit = spapr_cpu_exec_exit;
4435      xic->ics_get = spapr_ics_get;
4436      xic->ics_resend = spapr_ics_resend;
4437      xic->icp_get = spapr_icp_get;
4438      ispc->print_info = spapr_pic_print_info;
4439      /* Force NUMA node memory size to be a multiple of
4440       * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
4441       * in which LMBs are represented and hot-added
4442       */
4443      mc->numa_mem_align_shift = 28;
4444      mc->numa_mem_supported = true;
4445      mc->auto_enable_numa = true;
4446  
4447      smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF;
4448      smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON;
4449      smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON;
4450      smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND;
4451      smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND;
4452      smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND;
4453      smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */
4454      smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF;
4455      smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON;
4456      smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON;
4457      smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] = SPAPR_CAP_ON;
4458      spapr_caps_add_properties(smc, &error_abort);
4459      smc->irq = &spapr_irq_dual;
4460      smc->dr_phb_enabled = true;
4461      smc->linux_pci_probe = true;
4462      smc->smp_threads_vsmt = true;
4463      smc->nr_xirqs = SPAPR_NR_XIRQS;
4464      xfc->match_nvt = spapr_match_nvt;
4465  }
4466  
4467  static const TypeInfo spapr_machine_info = {
4468      .name          = TYPE_SPAPR_MACHINE,
4469      .parent        = TYPE_MACHINE,
4470      .abstract      = true,
4471      .instance_size = sizeof(SpaprMachineState),
4472      .instance_init = spapr_instance_init,
4473      .instance_finalize = spapr_machine_finalizefn,
4474      .class_size    = sizeof(SpaprMachineClass),
4475      .class_init    = spapr_machine_class_init,
4476      .interfaces = (InterfaceInfo[]) {
4477          { TYPE_FW_PATH_PROVIDER },
4478          { TYPE_NMI },
4479          { TYPE_HOTPLUG_HANDLER },
4480          { TYPE_PPC_VIRTUAL_HYPERVISOR },
4481          { TYPE_XICS_FABRIC },
4482          { TYPE_INTERRUPT_STATS_PROVIDER },
4483          { TYPE_XIVE_FABRIC },
4484          { }
4485      },
4486  };
4487  
4488  #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest)                 \
4489      static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
4490                                                      void *data)      \
4491      {                                                                \
4492          MachineClass *mc = MACHINE_CLASS(oc);                        \
4493          spapr_machine_##suffix##_class_options(mc);                  \
4494          if (latest) {                                                \
4495              mc->alias = "pseries";                                   \
4496              mc->is_default = 1;                                      \
4497          }                                                            \
4498      }                                                                \
4499      static const TypeInfo spapr_machine_##suffix##_info = {          \
4500          .name = MACHINE_TYPE_NAME("pseries-" verstr),                \
4501          .parent = TYPE_SPAPR_MACHINE,                                \
4502          .class_init = spapr_machine_##suffix##_class_init,           \
4503      };                                                               \
4504      static void spapr_machine_register_##suffix(void)                \
4505      {                                                                \
4506          type_register(&spapr_machine_##suffix##_info);               \
4507      }                                                                \
4508      type_init(spapr_machine_register_##suffix)
4509  
4510  /*
4511   * pseries-5.0
4512   */
4513  static void spapr_machine_5_0_class_options(MachineClass *mc)
4514  {
4515      /* Defaults for the latest behaviour inherited from the base class */
4516  }
4517  
4518  DEFINE_SPAPR_MACHINE(5_0, "5.0", true);
4519  
4520  /*
4521   * pseries-4.2
4522   */
4523  static void spapr_machine_4_2_class_options(MachineClass *mc)
4524  {
4525      SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4526  
4527      spapr_machine_5_0_class_options(mc);
4528      compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
4529      smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF;
4530      smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] = SPAPR_CAP_OFF;
4531  }
4532  
4533  DEFINE_SPAPR_MACHINE(4_2, "4.2", false);
4534  
4535  /*
4536   * pseries-4.1
4537   */
4538  static void spapr_machine_4_1_class_options(MachineClass *mc)
4539  {
4540      SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4541      static GlobalProperty compat[] = {
4542          /* Only allow 4kiB and 64kiB IOMMU pagesizes */
4543          { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" },
4544      };
4545  
4546      spapr_machine_4_2_class_options(mc);
4547      smc->linux_pci_probe = false;
4548      smc->smp_threads_vsmt = false;
4549      compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
4550      compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4551  }
4552  
4553  DEFINE_SPAPR_MACHINE(4_1, "4.1", false);
4554  
4555  /*
4556   * pseries-4.0
4557   */
4558  static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index,
4559                                uint64_t *buid, hwaddr *pio,
4560                                hwaddr *mmio32, hwaddr *mmio64,
4561                                unsigned n_dma, uint32_t *liobns,
4562                                hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp)
4563  {
4564      spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns,
4565                          nv2gpa, nv2atsd, errp);
4566      *nv2gpa = 0;
4567      *nv2atsd = 0;
4568  }
4569  
4570  static void spapr_machine_4_0_class_options(MachineClass *mc)
4571  {
4572      SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4573  
4574      spapr_machine_4_1_class_options(mc);
4575      compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
4576      smc->phb_placement = phb_placement_4_0;
4577      smc->irq = &spapr_irq_xics;
4578      smc->pre_4_1_migration = true;
4579  }
4580  
4581  DEFINE_SPAPR_MACHINE(4_0, "4.0", false);
4582  
4583  /*
4584   * pseries-3.1
4585   */
4586  static void spapr_machine_3_1_class_options(MachineClass *mc)
4587  {
4588      SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4589  
4590      spapr_machine_4_0_class_options(mc);
4591      compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
4592  
4593      mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
4594      smc->update_dt_enabled = false;
4595      smc->dr_phb_enabled = false;
4596      smc->broken_host_serial_model = true;
4597      smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN;
4598      smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN;
4599      smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN;
4600      smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF;
4601  }
4602  
4603  DEFINE_SPAPR_MACHINE(3_1, "3.1", false);
4604  
4605  /*
4606   * pseries-3.0
4607   */
4608  
4609  static void spapr_machine_3_0_class_options(MachineClass *mc)
4610  {
4611      SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4612  
4613      spapr_machine_3_1_class_options(mc);
4614      compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
4615  
4616      smc->legacy_irq_allocation = true;
4617      smc->nr_xirqs = 0x400;
4618      smc->irq = &spapr_irq_xics_legacy;
4619  }
4620  
4621  DEFINE_SPAPR_MACHINE(3_0, "3.0", false);
4622  
4623  /*
4624   * pseries-2.12
4625   */
4626  static void spapr_machine_2_12_class_options(MachineClass *mc)
4627  {
4628      SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4629      static GlobalProperty compat[] = {
4630          { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" },
4631          { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" },
4632      };
4633  
4634      spapr_machine_3_0_class_options(mc);
4635      compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
4636      compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4637  
4638      /* We depend on kvm_enabled() to choose a default value for the
4639       * hpt-max-page-size capability. Of course we can't do it here
4640       * because this is too early and the HW accelerator isn't initialzed
4641       * yet. Postpone this to machine init (see default_caps_with_cpu()).
4642       */
4643      smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0;
4644  }
4645  
4646  DEFINE_SPAPR_MACHINE(2_12, "2.12", false);
4647  
4648  static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc)
4649  {
4650      SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4651  
4652      spapr_machine_2_12_class_options(mc);
4653      smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND;
4654      smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND;
4655      smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD;
4656  }
4657  
4658  DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false);
4659  
4660  /*
4661   * pseries-2.11
4662   */
4663  
4664  static void spapr_machine_2_11_class_options(MachineClass *mc)
4665  {
4666      SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4667  
4668      spapr_machine_2_12_class_options(mc);
4669      smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON;
4670      compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
4671  }
4672  
4673  DEFINE_SPAPR_MACHINE(2_11, "2.11", false);
4674  
4675  /*
4676   * pseries-2.10
4677   */
4678  
4679  static void spapr_machine_2_10_class_options(MachineClass *mc)
4680  {
4681      spapr_machine_2_11_class_options(mc);
4682      compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
4683  }
4684  
4685  DEFINE_SPAPR_MACHINE(2_10, "2.10", false);
4686  
4687  /*
4688   * pseries-2.9
4689   */
4690  
4691  static void spapr_machine_2_9_class_options(MachineClass *mc)
4692  {
4693      SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4694      static GlobalProperty compat[] = {
4695          { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" },
4696      };
4697  
4698      spapr_machine_2_10_class_options(mc);
4699      compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
4700      compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4701      mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
4702      smc->pre_2_10_has_unused_icps = true;
4703      smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED;
4704  }
4705  
4706  DEFINE_SPAPR_MACHINE(2_9, "2.9", false);
4707  
4708  /*
4709   * pseries-2.8
4710   */
4711  
4712  static void spapr_machine_2_8_class_options(MachineClass *mc)
4713  {
4714      static GlobalProperty compat[] = {
4715          { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" },
4716      };
4717  
4718      spapr_machine_2_9_class_options(mc);
4719      compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
4720      compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4721      mc->numa_mem_align_shift = 23;
4722  }
4723  
4724  DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
4725  
4726  /*
4727   * pseries-2.7
4728   */
4729  
4730  static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index,
4731                                uint64_t *buid, hwaddr *pio,
4732                                hwaddr *mmio32, hwaddr *mmio64,
4733                                unsigned n_dma, uint32_t *liobns,
4734                                hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp)
4735  {
4736      /* Legacy PHB placement for pseries-2.7 and earlier machine types */
4737      const uint64_t base_buid = 0x800000020000000ULL;
4738      const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */
4739      const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */
4740      const hwaddr pio_offset = 0x80000000; /* 2 GiB */
4741      const uint32_t max_index = 255;
4742      const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */
4743  
4744      uint64_t ram_top = MACHINE(spapr)->ram_size;
4745      hwaddr phb0_base, phb_base;
4746      int i;
4747  
4748      /* Do we have device memory? */
4749      if (MACHINE(spapr)->maxram_size > ram_top) {
4750          /* Can't just use maxram_size, because there may be an
4751           * alignment gap between normal and device memory regions
4752           */
4753          ram_top = MACHINE(spapr)->device_memory->base +
4754              memory_region_size(&MACHINE(spapr)->device_memory->mr);
4755      }
4756  
4757      phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
4758  
4759      if (index > max_index) {
4760          error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
4761                     max_index);
4762          return;
4763      }
4764  
4765      *buid = base_buid + index;
4766      for (i = 0; i < n_dma; ++i) {
4767          liobns[i] = SPAPR_PCI_LIOBN(index, i);
4768      }
4769  
4770      phb_base = phb0_base + index * phb_spacing;
4771      *pio = phb_base + pio_offset;
4772      *mmio32 = phb_base + mmio_offset;
4773      /*
4774       * We don't set the 64-bit MMIO window, relying on the PHB's
4775       * fallback behaviour of automatically splitting a large "32-bit"
4776       * window into contiguous 32-bit and 64-bit windows
4777       */
4778  
4779      *nv2gpa = 0;
4780      *nv2atsd = 0;
4781  }
4782  
4783  static void spapr_machine_2_7_class_options(MachineClass *mc)
4784  {
4785      SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4786      static GlobalProperty compat[] = {
4787          { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", },
4788          { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", },
4789          { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", },
4790          { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", },
4791      };
4792  
4793      spapr_machine_2_8_class_options(mc);
4794      mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3");
4795      mc->default_machine_opts = "modern-hotplug-events=off";
4796      compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
4797      compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4798      smc->phb_placement = phb_placement_2_7;
4799  }
4800  
4801  DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
4802  
4803  /*
4804   * pseries-2.6
4805   */
4806  
4807  static void spapr_machine_2_6_class_options(MachineClass *mc)
4808  {
4809      static GlobalProperty compat[] = {
4810          { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" },
4811      };
4812  
4813      spapr_machine_2_7_class_options(mc);
4814      mc->has_hotpluggable_cpus = false;
4815      compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
4816      compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4817  }
4818  
4819  DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
4820  
4821  /*
4822   * pseries-2.5
4823   */
4824  
4825  static void spapr_machine_2_5_class_options(MachineClass *mc)
4826  {
4827      SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4828      static GlobalProperty compat[] = {
4829          { "spapr-vlan", "use-rx-buffer-pools", "off" },
4830      };
4831  
4832      spapr_machine_2_6_class_options(mc);
4833      smc->use_ohci_by_default = true;
4834      compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len);
4835      compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4836  }
4837  
4838  DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
4839  
4840  /*
4841   * pseries-2.4
4842   */
4843  
4844  static void spapr_machine_2_4_class_options(MachineClass *mc)
4845  {
4846      SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4847  
4848      spapr_machine_2_5_class_options(mc);
4849      smc->dr_lmb_enabled = false;
4850      compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len);
4851  }
4852  
4853  DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
4854  
4855  /*
4856   * pseries-2.3
4857   */
4858  
4859  static void spapr_machine_2_3_class_options(MachineClass *mc)
4860  {
4861      static GlobalProperty compat[] = {
4862          { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" },
4863      };
4864      spapr_machine_2_4_class_options(mc);
4865      compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len);
4866      compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4867  }
4868  DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
4869  
4870  /*
4871   * pseries-2.2
4872   */
4873  
4874  static void spapr_machine_2_2_class_options(MachineClass *mc)
4875  {
4876      static GlobalProperty compat[] = {
4877          { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" },
4878      };
4879  
4880      spapr_machine_2_3_class_options(mc);
4881      compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len);
4882      compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4883      mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on";
4884  }
4885  DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
4886  
4887  /*
4888   * pseries-2.1
4889   */
4890  
4891  static void spapr_machine_2_1_class_options(MachineClass *mc)
4892  {
4893      spapr_machine_2_2_class_options(mc);
4894      compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len);
4895  }
4896  DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
4897  
4898  static void spapr_machine_register_types(void)
4899  {
4900      type_register_static(&spapr_machine_info);
4901  }
4902  
4903  type_init(spapr_machine_register_types)
4904