1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/numa.h" 32 #include "hw/hw.h" 33 #include "qemu/log.h" 34 #include "hw/fw-path-provider.h" 35 #include "elf.h" 36 #include "net/net.h" 37 #include "sysemu/device_tree.h" 38 #include "sysemu/block-backend.h" 39 #include "sysemu/cpus.h" 40 #include "sysemu/hw_accel.h" 41 #include "kvm_ppc.h" 42 #include "migration/misc.h" 43 #include "migration/global_state.h" 44 #include "migration/register.h" 45 #include "mmu-hash64.h" 46 #include "mmu-book3s-v3.h" 47 #include "cpu-models.h" 48 #include "qom/cpu.h" 49 50 #include "hw/boards.h" 51 #include "hw/ppc/ppc.h" 52 #include "hw/loader.h" 53 54 #include "hw/ppc/fdt.h" 55 #include "hw/ppc/spapr.h" 56 #include "hw/ppc/spapr_vio.h" 57 #include "hw/pci-host/spapr.h" 58 #include "hw/ppc/xics.h" 59 #include "hw/pci/msi.h" 60 61 #include "hw/pci/pci.h" 62 #include "hw/scsi/scsi.h" 63 #include "hw/virtio/virtio-scsi.h" 64 #include "hw/virtio/vhost-scsi-common.h" 65 66 #include "exec/address-spaces.h" 67 #include "hw/usb.h" 68 #include "qemu/config-file.h" 69 #include "qemu/error-report.h" 70 #include "trace.h" 71 #include "hw/nmi.h" 72 #include "hw/intc/intc.h" 73 74 #include "hw/compat.h" 75 #include "qemu/cutils.h" 76 #include "hw/ppc/spapr_cpu_core.h" 77 78 #include <libfdt.h> 79 80 /* SLOF memory layout: 81 * 82 * SLOF raw image loaded at 0, copies its romfs right below the flat 83 * device-tree, then position SLOF itself 31M below that 84 * 85 * So we set FW_OVERHEAD to 40MB which should account for all of that 86 * and more 87 * 88 * We load our kernel at 4M, leaving space for SLOF initial image 89 */ 90 #define FDT_MAX_SIZE 0x100000 91 #define RTAS_MAX_SIZE 0x10000 92 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 93 #define FW_MAX_SIZE 0x400000 94 #define FW_FILE_NAME "slof.bin" 95 #define FW_OVERHEAD 0x2800000 96 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 97 98 #define MIN_RMA_SLOF 128UL 99 100 #define PHANDLE_XICP 0x00001111 101 102 static ICSState *spapr_ics_create(sPAPRMachineState *spapr, 103 const char *type_ics, 104 int nr_irqs, Error **errp) 105 { 106 Error *local_err = NULL; 107 Object *obj; 108 109 obj = object_new(type_ics); 110 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); 111 object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr), 112 &error_abort); 113 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err); 114 if (local_err) { 115 goto error; 116 } 117 object_property_set_bool(obj, true, "realized", &local_err); 118 if (local_err) { 119 goto error; 120 } 121 122 return ICS_SIMPLE(obj); 123 124 error: 125 error_propagate(errp, local_err); 126 return NULL; 127 } 128 129 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 130 { 131 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 132 * and newer QEMUs don't even have them. In both cases, we don't want 133 * to send anything on the wire. 134 */ 135 return false; 136 } 137 138 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 139 .name = "icp/server", 140 .version_id = 1, 141 .minimum_version_id = 1, 142 .needed = pre_2_10_vmstate_dummy_icp_needed, 143 .fields = (VMStateField[]) { 144 VMSTATE_UNUSED(4), /* uint32_t xirr */ 145 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 146 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 147 VMSTATE_END_OF_LIST() 148 }, 149 }; 150 151 static void pre_2_10_vmstate_register_dummy_icp(int i) 152 { 153 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 154 (void *)(uintptr_t) i); 155 } 156 157 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 158 { 159 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 160 (void *)(uintptr_t) i); 161 } 162 163 static inline int xics_max_server_number(void) 164 { 165 return DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(), smp_threads); 166 } 167 168 static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp) 169 { 170 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 171 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 172 173 if (kvm_enabled()) { 174 if (machine_kernel_irqchip_allowed(machine) && 175 !xics_kvm_init(spapr, errp)) { 176 spapr->icp_type = TYPE_KVM_ICP; 177 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp); 178 } 179 if (machine_kernel_irqchip_required(machine) && !spapr->ics) { 180 error_prepend(errp, "kernel_irqchip requested but unavailable: "); 181 return; 182 } 183 } 184 185 if (!spapr->ics) { 186 xics_spapr_init(spapr); 187 spapr->icp_type = TYPE_ICP; 188 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp); 189 if (!spapr->ics) { 190 return; 191 } 192 } 193 194 if (smc->pre_2_10_has_unused_icps) { 195 int i; 196 197 for (i = 0; i < xics_max_server_number(); i++) { 198 /* Dummy entries get deregistered when real ICPState objects 199 * are registered during CPU core hotplug. 200 */ 201 pre_2_10_vmstate_register_dummy_icp(i); 202 } 203 } 204 } 205 206 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 207 int smt_threads) 208 { 209 int i, ret = 0; 210 uint32_t servers_prop[smt_threads]; 211 uint32_t gservers_prop[smt_threads * 2]; 212 int index = spapr_vcpu_id(cpu); 213 214 if (cpu->compat_pvr) { 215 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 216 if (ret < 0) { 217 return ret; 218 } 219 } 220 221 /* Build interrupt servers and gservers properties */ 222 for (i = 0; i < smt_threads; i++) { 223 servers_prop[i] = cpu_to_be32(index + i); 224 /* Hack, direct the group queues back to cpu 0 */ 225 gservers_prop[i*2] = cpu_to_be32(index + i); 226 gservers_prop[i*2 + 1] = 0; 227 } 228 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 229 servers_prop, sizeof(servers_prop)); 230 if (ret < 0) { 231 return ret; 232 } 233 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 234 gservers_prop, sizeof(gservers_prop)); 235 236 return ret; 237 } 238 239 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 240 { 241 int index = spapr_vcpu_id(cpu); 242 uint32_t associativity[] = {cpu_to_be32(0x5), 243 cpu_to_be32(0x0), 244 cpu_to_be32(0x0), 245 cpu_to_be32(0x0), 246 cpu_to_be32(cpu->node_id), 247 cpu_to_be32(index)}; 248 249 /* Advertise NUMA via ibm,associativity */ 250 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 251 sizeof(associativity)); 252 } 253 254 /* Populate the "ibm,pa-features" property */ 255 static void spapr_populate_pa_features(sPAPRMachineState *spapr, 256 PowerPCCPU *cpu, 257 void *fdt, int offset, 258 bool legacy_guest) 259 { 260 CPUPPCState *env = &cpu->env; 261 uint8_t pa_features_206[] = { 6, 0, 262 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 263 uint8_t pa_features_207[] = { 24, 0, 264 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 265 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 266 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 267 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 268 uint8_t pa_features_300[] = { 66, 0, 269 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 270 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 271 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 272 /* 6: DS207 */ 273 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 274 /* 16: Vector */ 275 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 276 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 277 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 278 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 279 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 280 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 281 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 282 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 283 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 284 /* 42: PM, 44: PC RA, 46: SC vec'd */ 285 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 286 /* 48: SIMD, 50: QP BFP, 52: String */ 287 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 288 /* 54: DecFP, 56: DecI, 58: SHA */ 289 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 290 /* 60: NM atomic, 62: RNG */ 291 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 292 }; 293 uint8_t *pa_features = NULL; 294 size_t pa_size; 295 296 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 297 pa_features = pa_features_206; 298 pa_size = sizeof(pa_features_206); 299 } 300 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 301 pa_features = pa_features_207; 302 pa_size = sizeof(pa_features_207); 303 } 304 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 305 pa_features = pa_features_300; 306 pa_size = sizeof(pa_features_300); 307 } 308 if (!pa_features) { 309 return; 310 } 311 312 if (env->ci_large_pages) { 313 /* 314 * Note: we keep CI large pages off by default because a 64K capable 315 * guest provisioned with large pages might otherwise try to map a qemu 316 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 317 * even if that qemu runs on a 4k host. 318 * We dd this bit back here if we are confident this is not an issue 319 */ 320 pa_features[3] |= 0x20; 321 } 322 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 323 pa_features[24] |= 0x80; /* Transactional memory support */ 324 } 325 if (legacy_guest && pa_size > 40) { 326 /* Workaround for broken kernels that attempt (guest) radix 327 * mode when they can't handle it, if they see the radix bit set 328 * in pa-features. So hide it from them. */ 329 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 330 } 331 332 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 333 } 334 335 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 336 { 337 int ret = 0, offset, cpus_offset; 338 CPUState *cs; 339 char cpu_model[32]; 340 int smt = kvmppc_smt_threads(); 341 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 342 343 CPU_FOREACH(cs) { 344 PowerPCCPU *cpu = POWERPC_CPU(cs); 345 DeviceClass *dc = DEVICE_GET_CLASS(cs); 346 int index = spapr_vcpu_id(cpu); 347 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 348 349 if ((index % smt) != 0) { 350 continue; 351 } 352 353 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 354 355 cpus_offset = fdt_path_offset(fdt, "/cpus"); 356 if (cpus_offset < 0) { 357 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 358 if (cpus_offset < 0) { 359 return cpus_offset; 360 } 361 } 362 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 363 if (offset < 0) { 364 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 365 if (offset < 0) { 366 return offset; 367 } 368 } 369 370 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 371 pft_size_prop, sizeof(pft_size_prop)); 372 if (ret < 0) { 373 return ret; 374 } 375 376 if (nb_numa_nodes > 1) { 377 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); 378 if (ret < 0) { 379 return ret; 380 } 381 } 382 383 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 384 if (ret < 0) { 385 return ret; 386 } 387 388 spapr_populate_pa_features(spapr, cpu, fdt, offset, 389 spapr->cas_legacy_guest_workaround); 390 } 391 return ret; 392 } 393 394 static hwaddr spapr_node0_size(MachineState *machine) 395 { 396 if (nb_numa_nodes) { 397 int i; 398 for (i = 0; i < nb_numa_nodes; ++i) { 399 if (numa_info[i].node_mem) { 400 return MIN(pow2floor(numa_info[i].node_mem), 401 machine->ram_size); 402 } 403 } 404 } 405 return machine->ram_size; 406 } 407 408 static void add_str(GString *s, const gchar *s1) 409 { 410 g_string_append_len(s, s1, strlen(s1) + 1); 411 } 412 413 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 414 hwaddr size) 415 { 416 uint32_t associativity[] = { 417 cpu_to_be32(0x4), /* length */ 418 cpu_to_be32(0x0), cpu_to_be32(0x0), 419 cpu_to_be32(0x0), cpu_to_be32(nodeid) 420 }; 421 char mem_name[32]; 422 uint64_t mem_reg_property[2]; 423 int off; 424 425 mem_reg_property[0] = cpu_to_be64(start); 426 mem_reg_property[1] = cpu_to_be64(size); 427 428 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 429 off = fdt_add_subnode(fdt, 0, mem_name); 430 _FDT(off); 431 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 432 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 433 sizeof(mem_reg_property)))); 434 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 435 sizeof(associativity)))); 436 return off; 437 } 438 439 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 440 { 441 MachineState *machine = MACHINE(spapr); 442 hwaddr mem_start, node_size; 443 int i, nb_nodes = nb_numa_nodes; 444 NodeInfo *nodes = numa_info; 445 NodeInfo ramnode; 446 447 /* No NUMA nodes, assume there is just one node with whole RAM */ 448 if (!nb_numa_nodes) { 449 nb_nodes = 1; 450 ramnode.node_mem = machine->ram_size; 451 nodes = &ramnode; 452 } 453 454 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 455 if (!nodes[i].node_mem) { 456 continue; 457 } 458 if (mem_start >= machine->ram_size) { 459 node_size = 0; 460 } else { 461 node_size = nodes[i].node_mem; 462 if (node_size > machine->ram_size - mem_start) { 463 node_size = machine->ram_size - mem_start; 464 } 465 } 466 if (!mem_start) { 467 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 468 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 469 mem_start += spapr->rma_size; 470 node_size -= spapr->rma_size; 471 } 472 for ( ; node_size; ) { 473 hwaddr sizetmp = pow2floor(node_size); 474 475 /* mem_start != 0 here */ 476 if (ctzl(mem_start) < ctzl(sizetmp)) { 477 sizetmp = 1ULL << ctzl(mem_start); 478 } 479 480 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 481 node_size -= sizetmp; 482 mem_start += sizetmp; 483 } 484 } 485 486 return 0; 487 } 488 489 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 490 sPAPRMachineState *spapr) 491 { 492 PowerPCCPU *cpu = POWERPC_CPU(cs); 493 CPUPPCState *env = &cpu->env; 494 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 495 int index = spapr_vcpu_id(cpu); 496 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 497 0xffffffff, 0xffffffff}; 498 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 499 : SPAPR_TIMEBASE_FREQ; 500 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 501 uint32_t page_sizes_prop[64]; 502 size_t page_sizes_prop_size; 503 uint32_t vcpus_per_socket = smp_threads * smp_cores; 504 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 505 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 506 sPAPRDRConnector *drc; 507 int drc_index; 508 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 509 int i; 510 511 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 512 if (drc) { 513 drc_index = spapr_drc_index(drc); 514 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 515 } 516 517 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 518 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 519 520 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 521 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 522 env->dcache_line_size))); 523 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 524 env->dcache_line_size))); 525 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 526 env->icache_line_size))); 527 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 528 env->icache_line_size))); 529 530 if (pcc->l1_dcache_size) { 531 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 532 pcc->l1_dcache_size))); 533 } else { 534 warn_report("Unknown L1 dcache size for cpu"); 535 } 536 if (pcc->l1_icache_size) { 537 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 538 pcc->l1_icache_size))); 539 } else { 540 warn_report("Unknown L1 icache size for cpu"); 541 } 542 543 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 544 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 545 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 546 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 547 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 548 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 549 550 if (env->spr_cb[SPR_PURR].oea_read) { 551 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 552 } 553 554 if (env->mmu_model & POWERPC_MMU_1TSEG) { 555 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 556 segs, sizeof(segs)))); 557 } 558 559 /* Advertise VSX (vector extensions) if available 560 * 1 == VMX / Altivec available 561 * 2 == VSX available 562 * 563 * Only CPUs for which we create core types in spapr_cpu_core.c 564 * are possible, and all of those have VMX */ 565 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 566 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 567 } else { 568 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 569 } 570 571 /* Advertise DFP (Decimal Floating Point) if available 572 * 0 / no property == no DFP 573 * 1 == DFP available */ 574 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 575 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 576 } 577 578 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 579 sizeof(page_sizes_prop)); 580 if (page_sizes_prop_size) { 581 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 582 page_sizes_prop, page_sizes_prop_size))); 583 } 584 585 spapr_populate_pa_features(spapr, cpu, fdt, offset, false); 586 587 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 588 cs->cpu_index / vcpus_per_socket))); 589 590 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 591 pft_size_prop, sizeof(pft_size_prop)))); 592 593 if (nb_numa_nodes > 1) { 594 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 595 } 596 597 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 598 599 if (pcc->radix_page_info) { 600 for (i = 0; i < pcc->radix_page_info->count; i++) { 601 radix_AP_encodings[i] = 602 cpu_to_be32(pcc->radix_page_info->entries[i]); 603 } 604 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 605 radix_AP_encodings, 606 pcc->radix_page_info->count * 607 sizeof(radix_AP_encodings[0])))); 608 } 609 } 610 611 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 612 { 613 CPUState *cs; 614 int cpus_offset; 615 char *nodename; 616 int smt = kvmppc_smt_threads(); 617 618 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 619 _FDT(cpus_offset); 620 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 621 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 622 623 /* 624 * We walk the CPUs in reverse order to ensure that CPU DT nodes 625 * created by fdt_add_subnode() end up in the right order in FDT 626 * for the guest kernel the enumerate the CPUs correctly. 627 */ 628 CPU_FOREACH_REVERSE(cs) { 629 PowerPCCPU *cpu = POWERPC_CPU(cs); 630 int index = spapr_vcpu_id(cpu); 631 DeviceClass *dc = DEVICE_GET_CLASS(cs); 632 int offset; 633 634 if ((index % smt) != 0) { 635 continue; 636 } 637 638 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 639 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 640 g_free(nodename); 641 _FDT(offset); 642 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 643 } 644 645 } 646 647 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 648 { 649 MemoryDeviceInfoList *info; 650 651 for (info = list; info; info = info->next) { 652 MemoryDeviceInfo *value = info->value; 653 654 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 655 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 656 657 if (pcdimm_info->addr >= addr && 658 addr < (pcdimm_info->addr + pcdimm_info->size)) { 659 return pcdimm_info->node; 660 } 661 } 662 } 663 664 return -1; 665 } 666 667 /* 668 * Adds ibm,dynamic-reconfiguration-memory node. 669 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 670 * of this device tree node. 671 */ 672 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 673 { 674 MachineState *machine = MACHINE(spapr); 675 int ret, i, offset; 676 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 677 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 678 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 679 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 680 memory_region_size(&spapr->hotplug_memory.mr)) / 681 lmb_size; 682 uint32_t *int_buf, *cur_index, buf_len; 683 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 684 MemoryDeviceInfoList *dimms = NULL; 685 686 /* 687 * Don't create the node if there is no hotpluggable memory 688 */ 689 if (machine->ram_size == machine->maxram_size) { 690 return 0; 691 } 692 693 /* 694 * Allocate enough buffer size to fit in ibm,dynamic-memory 695 * or ibm,associativity-lookup-arrays 696 */ 697 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 698 * sizeof(uint32_t); 699 cur_index = int_buf = g_malloc0(buf_len); 700 701 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 702 703 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 704 sizeof(prop_lmb_size)); 705 if (ret < 0) { 706 goto out; 707 } 708 709 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 710 if (ret < 0) { 711 goto out; 712 } 713 714 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 715 if (ret < 0) { 716 goto out; 717 } 718 719 if (hotplug_lmb_start) { 720 MemoryDeviceInfoList **prev = &dimms; 721 qmp_pc_dimm_device_list(qdev_get_machine(), &prev); 722 } 723 724 /* ibm,dynamic-memory */ 725 int_buf[0] = cpu_to_be32(nr_lmbs); 726 cur_index++; 727 for (i = 0; i < nr_lmbs; i++) { 728 uint64_t addr = i * lmb_size; 729 uint32_t *dynamic_memory = cur_index; 730 731 if (i >= hotplug_lmb_start) { 732 sPAPRDRConnector *drc; 733 734 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 735 g_assert(drc); 736 737 dynamic_memory[0] = cpu_to_be32(addr >> 32); 738 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 739 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 740 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 741 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 742 if (memory_region_present(get_system_memory(), addr)) { 743 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 744 } else { 745 dynamic_memory[5] = cpu_to_be32(0); 746 } 747 } else { 748 /* 749 * LMB information for RMA, boot time RAM and gap b/n RAM and 750 * hotplug memory region -- all these are marked as reserved 751 * and as having no valid DRC. 752 */ 753 dynamic_memory[0] = cpu_to_be32(addr >> 32); 754 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 755 dynamic_memory[2] = cpu_to_be32(0); 756 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 757 dynamic_memory[4] = cpu_to_be32(-1); 758 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 759 SPAPR_LMB_FLAGS_DRC_INVALID); 760 } 761 762 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 763 } 764 qapi_free_MemoryDeviceInfoList(dimms); 765 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 766 if (ret < 0) { 767 goto out; 768 } 769 770 /* ibm,associativity-lookup-arrays */ 771 cur_index = int_buf; 772 int_buf[0] = cpu_to_be32(nr_nodes); 773 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 774 cur_index += 2; 775 for (i = 0; i < nr_nodes; i++) { 776 uint32_t associativity[] = { 777 cpu_to_be32(0x0), 778 cpu_to_be32(0x0), 779 cpu_to_be32(0x0), 780 cpu_to_be32(i) 781 }; 782 memcpy(cur_index, associativity, sizeof(associativity)); 783 cur_index += 4; 784 } 785 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 786 (cur_index - int_buf) * sizeof(uint32_t)); 787 out: 788 g_free(int_buf); 789 return ret; 790 } 791 792 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 793 sPAPROptionVector *ov5_updates) 794 { 795 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 796 int ret = 0, offset; 797 798 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 799 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 800 g_assert(smc->dr_lmb_enabled); 801 ret = spapr_populate_drconf_memory(spapr, fdt); 802 if (ret) { 803 goto out; 804 } 805 } 806 807 offset = fdt_path_offset(fdt, "/chosen"); 808 if (offset < 0) { 809 offset = fdt_add_subnode(fdt, 0, "chosen"); 810 if (offset < 0) { 811 return offset; 812 } 813 } 814 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 815 "ibm,architecture-vec-5"); 816 817 out: 818 return ret; 819 } 820 821 static bool spapr_hotplugged_dev_before_cas(void) 822 { 823 Object *drc_container, *obj; 824 ObjectProperty *prop; 825 ObjectPropertyIterator iter; 826 827 drc_container = container_get(object_get_root(), "/dr-connector"); 828 object_property_iter_init(&iter, drc_container); 829 while ((prop = object_property_iter_next(&iter))) { 830 if (!strstart(prop->type, "link<", NULL)) { 831 continue; 832 } 833 obj = object_property_get_link(drc_container, prop->name, NULL); 834 if (spapr_drc_needed(obj)) { 835 return true; 836 } 837 } 838 return false; 839 } 840 841 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 842 target_ulong addr, target_ulong size, 843 sPAPROptionVector *ov5_updates) 844 { 845 void *fdt, *fdt_skel; 846 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 847 848 if (spapr_hotplugged_dev_before_cas()) { 849 return 1; 850 } 851 852 if (size < sizeof(hdr) || size > FW_MAX_SIZE) { 853 error_report("SLOF provided an unexpected CAS buffer size " 854 TARGET_FMT_lu " (min: %zu, max: %u)", 855 size, sizeof(hdr), FW_MAX_SIZE); 856 exit(EXIT_FAILURE); 857 } 858 859 size -= sizeof(hdr); 860 861 /* Create skeleton */ 862 fdt_skel = g_malloc0(size); 863 _FDT((fdt_create(fdt_skel, size))); 864 _FDT((fdt_begin_node(fdt_skel, ""))); 865 _FDT((fdt_end_node(fdt_skel))); 866 _FDT((fdt_finish(fdt_skel))); 867 fdt = g_malloc0(size); 868 _FDT((fdt_open_into(fdt_skel, fdt, size))); 869 g_free(fdt_skel); 870 871 /* Fixup cpu nodes */ 872 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 873 874 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 875 return -1; 876 } 877 878 /* Pack resulting tree */ 879 _FDT((fdt_pack(fdt))); 880 881 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 882 trace_spapr_cas_failed(size); 883 return -1; 884 } 885 886 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 887 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 888 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 889 g_free(fdt); 890 891 return 0; 892 } 893 894 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 895 { 896 int rtas; 897 GString *hypertas = g_string_sized_new(256); 898 GString *qemu_hypertas = g_string_sized_new(256); 899 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 900 uint64_t max_hotplug_addr = spapr->hotplug_memory.base + 901 memory_region_size(&spapr->hotplug_memory.mr); 902 uint32_t lrdr_capacity[] = { 903 cpu_to_be32(max_hotplug_addr >> 32), 904 cpu_to_be32(max_hotplug_addr & 0xffffffff), 905 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 906 cpu_to_be32(max_cpus / smp_threads), 907 }; 908 909 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 910 911 /* hypertas */ 912 add_str(hypertas, "hcall-pft"); 913 add_str(hypertas, "hcall-term"); 914 add_str(hypertas, "hcall-dabr"); 915 add_str(hypertas, "hcall-interrupt"); 916 add_str(hypertas, "hcall-tce"); 917 add_str(hypertas, "hcall-vio"); 918 add_str(hypertas, "hcall-splpar"); 919 add_str(hypertas, "hcall-bulk"); 920 add_str(hypertas, "hcall-set-mode"); 921 add_str(hypertas, "hcall-sprg0"); 922 add_str(hypertas, "hcall-copy"); 923 add_str(hypertas, "hcall-debug"); 924 add_str(qemu_hypertas, "hcall-memop1"); 925 926 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 927 add_str(hypertas, "hcall-multi-tce"); 928 } 929 930 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 931 add_str(hypertas, "hcall-hpt-resize"); 932 } 933 934 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 935 hypertas->str, hypertas->len)); 936 g_string_free(hypertas, TRUE); 937 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 938 qemu_hypertas->str, qemu_hypertas->len)); 939 g_string_free(qemu_hypertas, TRUE); 940 941 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 942 refpoints, sizeof(refpoints))); 943 944 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 945 RTAS_ERROR_LOG_MAX)); 946 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 947 RTAS_EVENT_SCAN_RATE)); 948 949 g_assert(msi_nonbroken); 950 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 951 952 /* 953 * According to PAPR, rtas ibm,os-term does not guarantee a return 954 * back to the guest cpu. 955 * 956 * While an additional ibm,extended-os-term property indicates 957 * that rtas call return will always occur. Set this property. 958 */ 959 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 960 961 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 962 lrdr_capacity, sizeof(lrdr_capacity))); 963 964 spapr_dt_rtas_tokens(fdt, rtas); 965 } 966 967 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features 968 * that the guest may request and thus the valid values for bytes 24..26 of 969 * option vector 5: */ 970 static void spapr_dt_ov5_platform_support(void *fdt, int chosen) 971 { 972 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 973 974 char val[2 * 4] = { 975 23, 0x00, /* Xive mode, filled in below. */ 976 24, 0x00, /* Hash/Radix, filled in below. */ 977 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 978 26, 0x40, /* Radix options: GTSE == yes. */ 979 }; 980 981 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 982 first_ppc_cpu->compat_pvr)) { 983 /* If we're in a pre POWER9 compat mode then the guest should do hash */ 984 val[3] = 0x00; /* Hash */ 985 } else if (kvm_enabled()) { 986 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 987 val[3] = 0x80; /* OV5_MMU_BOTH */ 988 } else if (kvmppc_has_cap_mmu_radix()) { 989 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 990 } else { 991 val[3] = 0x00; /* Hash */ 992 } 993 } else { 994 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 995 val[3] = 0xC0; 996 } 997 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 998 val, sizeof(val))); 999 } 1000 1001 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 1002 { 1003 MachineState *machine = MACHINE(spapr); 1004 int chosen; 1005 const char *boot_device = machine->boot_order; 1006 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1007 size_t cb = 0; 1008 char *bootlist = get_boot_devices_list(&cb, true); 1009 1010 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1011 1012 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 1013 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1014 spapr->initrd_base)); 1015 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1016 spapr->initrd_base + spapr->initrd_size)); 1017 1018 if (spapr->kernel_size) { 1019 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 1020 cpu_to_be64(spapr->kernel_size) }; 1021 1022 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1023 &kprop, sizeof(kprop))); 1024 if (spapr->kernel_le) { 1025 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1026 } 1027 } 1028 if (boot_menu) { 1029 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 1030 } 1031 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1032 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1033 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1034 1035 if (cb && bootlist) { 1036 int i; 1037 1038 for (i = 0; i < cb; i++) { 1039 if (bootlist[i] == '\n') { 1040 bootlist[i] = ' '; 1041 } 1042 } 1043 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1044 } 1045 1046 if (boot_device && strlen(boot_device)) { 1047 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1048 } 1049 1050 if (!spapr->has_graphics && stdout_path) { 1051 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1052 } 1053 1054 spapr_dt_ov5_platform_support(fdt, chosen); 1055 1056 g_free(stdout_path); 1057 g_free(bootlist); 1058 } 1059 1060 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 1061 { 1062 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1063 * KVM to work under pHyp with some guest co-operation */ 1064 int hypervisor; 1065 uint8_t hypercall[16]; 1066 1067 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1068 /* indicate KVM hypercall interface */ 1069 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1070 if (kvmppc_has_cap_fixup_hcalls()) { 1071 /* 1072 * Older KVM versions with older guest kernels were broken 1073 * with the magic page, don't allow the guest to map it. 1074 */ 1075 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1076 sizeof(hypercall))) { 1077 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1078 hypercall, sizeof(hypercall))); 1079 } 1080 } 1081 } 1082 1083 static void *spapr_build_fdt(sPAPRMachineState *spapr, 1084 hwaddr rtas_addr, 1085 hwaddr rtas_size) 1086 { 1087 MachineState *machine = MACHINE(spapr); 1088 MachineClass *mc = MACHINE_GET_CLASS(machine); 1089 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1090 int ret; 1091 void *fdt; 1092 sPAPRPHBState *phb; 1093 char *buf; 1094 1095 fdt = g_malloc0(FDT_MAX_SIZE); 1096 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 1097 1098 /* Root node */ 1099 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1100 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1101 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1102 1103 /* 1104 * Add info to guest to indentify which host is it being run on 1105 * and what is the uuid of the guest 1106 */ 1107 if (kvmppc_get_host_model(&buf)) { 1108 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1109 g_free(buf); 1110 } 1111 if (kvmppc_get_host_serial(&buf)) { 1112 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1113 g_free(buf); 1114 } 1115 1116 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1117 1118 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1119 if (qemu_uuid_set) { 1120 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1121 } 1122 g_free(buf); 1123 1124 if (qemu_get_vm_name()) { 1125 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1126 qemu_get_vm_name())); 1127 } 1128 1129 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1130 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1131 1132 /* /interrupt controller */ 1133 spapr_dt_xics(xics_max_server_number(), fdt, PHANDLE_XICP); 1134 1135 ret = spapr_populate_memory(spapr, fdt); 1136 if (ret < 0) { 1137 error_report("couldn't setup memory nodes in fdt"); 1138 exit(1); 1139 } 1140 1141 /* /vdevice */ 1142 spapr_dt_vdevice(spapr->vio_bus, fdt); 1143 1144 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1145 ret = spapr_rng_populate_dt(fdt); 1146 if (ret < 0) { 1147 error_report("could not set up rng device in the fdt"); 1148 exit(1); 1149 } 1150 } 1151 1152 QLIST_FOREACH(phb, &spapr->phbs, list) { 1153 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 1154 if (ret < 0) { 1155 error_report("couldn't setup PCI devices in fdt"); 1156 exit(1); 1157 } 1158 } 1159 1160 /* cpus */ 1161 spapr_populate_cpus_dt_node(fdt, spapr); 1162 1163 if (smc->dr_lmb_enabled) { 1164 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1165 } 1166 1167 if (mc->has_hotpluggable_cpus) { 1168 int offset = fdt_path_offset(fdt, "/cpus"); 1169 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1170 SPAPR_DR_CONNECTOR_TYPE_CPU); 1171 if (ret < 0) { 1172 error_report("Couldn't set up CPU DR device tree properties"); 1173 exit(1); 1174 } 1175 } 1176 1177 /* /event-sources */ 1178 spapr_dt_events(spapr, fdt); 1179 1180 /* /rtas */ 1181 spapr_dt_rtas(spapr, fdt); 1182 1183 /* /chosen */ 1184 spapr_dt_chosen(spapr, fdt); 1185 1186 /* /hypervisor */ 1187 if (kvm_enabled()) { 1188 spapr_dt_hypervisor(spapr, fdt); 1189 } 1190 1191 /* Build memory reserve map */ 1192 if (spapr->kernel_size) { 1193 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1194 } 1195 if (spapr->initrd_size) { 1196 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1197 } 1198 1199 /* ibm,client-architecture-support updates */ 1200 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1201 if (ret < 0) { 1202 error_report("couldn't setup CAS properties fdt"); 1203 exit(1); 1204 } 1205 1206 return fdt; 1207 } 1208 1209 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1210 { 1211 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1212 } 1213 1214 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1215 PowerPCCPU *cpu) 1216 { 1217 CPUPPCState *env = &cpu->env; 1218 1219 /* The TCG path should also be holding the BQL at this point */ 1220 g_assert(qemu_mutex_iothread_locked()); 1221 1222 if (msr_pr) { 1223 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1224 env->gpr[3] = H_PRIVILEGE; 1225 } else { 1226 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1227 } 1228 } 1229 1230 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) 1231 { 1232 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1233 1234 return spapr->patb_entry; 1235 } 1236 1237 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1238 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1239 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1240 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1241 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1242 1243 /* 1244 * Get the fd to access the kernel htab, re-opening it if necessary 1245 */ 1246 static int get_htab_fd(sPAPRMachineState *spapr) 1247 { 1248 Error *local_err = NULL; 1249 1250 if (spapr->htab_fd >= 0) { 1251 return spapr->htab_fd; 1252 } 1253 1254 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1255 if (spapr->htab_fd < 0) { 1256 error_report_err(local_err); 1257 } 1258 1259 return spapr->htab_fd; 1260 } 1261 1262 void close_htab_fd(sPAPRMachineState *spapr) 1263 { 1264 if (spapr->htab_fd >= 0) { 1265 close(spapr->htab_fd); 1266 } 1267 spapr->htab_fd = -1; 1268 } 1269 1270 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1271 { 1272 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1273 1274 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1275 } 1276 1277 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1278 { 1279 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1280 1281 assert(kvm_enabled()); 1282 1283 if (!spapr->htab) { 1284 return 0; 1285 } 1286 1287 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1288 } 1289 1290 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1291 hwaddr ptex, int n) 1292 { 1293 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1294 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1295 1296 if (!spapr->htab) { 1297 /* 1298 * HTAB is controlled by KVM. Fetch into temporary buffer 1299 */ 1300 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1301 kvmppc_read_hptes(hptes, ptex, n); 1302 return hptes; 1303 } 1304 1305 /* 1306 * HTAB is controlled by QEMU. Just point to the internally 1307 * accessible PTEG. 1308 */ 1309 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1310 } 1311 1312 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1313 const ppc_hash_pte64_t *hptes, 1314 hwaddr ptex, int n) 1315 { 1316 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1317 1318 if (!spapr->htab) { 1319 g_free((void *)hptes); 1320 } 1321 1322 /* Nothing to do for qemu managed HPT */ 1323 } 1324 1325 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1326 uint64_t pte0, uint64_t pte1) 1327 { 1328 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1329 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1330 1331 if (!spapr->htab) { 1332 kvmppc_write_hpte(ptex, pte0, pte1); 1333 } else { 1334 stq_p(spapr->htab + offset, pte0); 1335 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1336 } 1337 } 1338 1339 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1340 { 1341 int shift; 1342 1343 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1344 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1345 * that's much more than is needed for Linux guests */ 1346 shift = ctz64(pow2ceil(ramsize)) - 7; 1347 shift = MAX(shift, 18); /* Minimum architected size */ 1348 shift = MIN(shift, 46); /* Maximum architected size */ 1349 return shift; 1350 } 1351 1352 void spapr_free_hpt(sPAPRMachineState *spapr) 1353 { 1354 g_free(spapr->htab); 1355 spapr->htab = NULL; 1356 spapr->htab_shift = 0; 1357 close_htab_fd(spapr); 1358 } 1359 1360 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1361 Error **errp) 1362 { 1363 long rc; 1364 1365 /* Clean up any HPT info from a previous boot */ 1366 spapr_free_hpt(spapr); 1367 1368 rc = kvmppc_reset_htab(shift); 1369 if (rc < 0) { 1370 /* kernel-side HPT needed, but couldn't allocate one */ 1371 error_setg_errno(errp, errno, 1372 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1373 shift); 1374 /* This is almost certainly fatal, but if the caller really 1375 * wants to carry on with shift == 0, it's welcome to try */ 1376 } else if (rc > 0) { 1377 /* kernel-side HPT allocated */ 1378 if (rc != shift) { 1379 error_setg(errp, 1380 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1381 shift, rc); 1382 } 1383 1384 spapr->htab_shift = shift; 1385 spapr->htab = NULL; 1386 } else { 1387 /* kernel-side HPT not needed, allocate in userspace instead */ 1388 size_t size = 1ULL << shift; 1389 int i; 1390 1391 spapr->htab = qemu_memalign(size, size); 1392 if (!spapr->htab) { 1393 error_setg_errno(errp, errno, 1394 "Could not allocate HPT of order %d", shift); 1395 return; 1396 } 1397 1398 memset(spapr->htab, 0, size); 1399 spapr->htab_shift = shift; 1400 1401 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1402 DIRTY_HPTE(HPTE(spapr->htab, i)); 1403 } 1404 } 1405 /* We're setting up a hash table, so that means we're not radix */ 1406 spapr->patb_entry = 0; 1407 } 1408 1409 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) 1410 { 1411 int hpt_shift; 1412 1413 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1414 || (spapr->cas_reboot 1415 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1416 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1417 } else { 1418 uint64_t current_ram_size; 1419 1420 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1421 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1422 } 1423 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1424 1425 if (spapr->vrma_adjust) { 1426 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), 1427 spapr->htab_shift); 1428 } 1429 } 1430 1431 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1432 { 1433 bool matched = false; 1434 1435 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1436 matched = true; 1437 } 1438 1439 if (!matched) { 1440 error_report("Device %s is not supported by this machine yet.", 1441 qdev_fw_name(DEVICE(sbdev))); 1442 exit(1); 1443 } 1444 } 1445 1446 static int spapr_reset_drcs(Object *child, void *opaque) 1447 { 1448 sPAPRDRConnector *drc = 1449 (sPAPRDRConnector *) object_dynamic_cast(child, 1450 TYPE_SPAPR_DR_CONNECTOR); 1451 1452 if (drc) { 1453 spapr_drc_reset(drc); 1454 } 1455 1456 return 0; 1457 } 1458 1459 static void spapr_machine_reset(void) 1460 { 1461 MachineState *machine = MACHINE(qdev_get_machine()); 1462 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1463 PowerPCCPU *first_ppc_cpu; 1464 uint32_t rtas_limit; 1465 hwaddr rtas_addr, fdt_addr; 1466 void *fdt; 1467 int rc; 1468 1469 /* Check for unknown sysbus devices */ 1470 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1471 1472 spapr_caps_reset(spapr); 1473 1474 first_ppc_cpu = POWERPC_CPU(first_cpu); 1475 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1476 ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 1477 spapr->max_compat_pvr)) { 1478 /* If using KVM with radix mode available, VCPUs can be started 1479 * without a HPT because KVM will start them in radix mode. 1480 * Set the GR bit in PATB so that we know there is no HPT. */ 1481 spapr->patb_entry = PATBE1_GR; 1482 } else { 1483 spapr_setup_hpt_and_vrma(spapr); 1484 } 1485 1486 /* if this reset wasn't generated by CAS, we should reset our 1487 * negotiated options and start from scratch */ 1488 if (!spapr->cas_reboot) { 1489 spapr_ovec_cleanup(spapr->ov5_cas); 1490 spapr->ov5_cas = spapr_ovec_new(); 1491 1492 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal); 1493 } 1494 1495 qemu_devices_reset(); 1496 1497 /* DRC reset may cause a device to be unplugged. This will cause troubles 1498 * if this device is used by another device (eg, a running vhost backend 1499 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1500 * situations, we reset DRCs after all devices have been reset. 1501 */ 1502 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); 1503 1504 spapr_clear_pending_events(spapr); 1505 1506 /* 1507 * We place the device tree and RTAS just below either the top of the RMA, 1508 * or just below 2GB, whichever is lowere, so that it can be 1509 * processed with 32-bit real mode code if necessary 1510 */ 1511 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1512 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1513 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1514 1515 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1516 1517 spapr_load_rtas(spapr, fdt, rtas_addr); 1518 1519 rc = fdt_pack(fdt); 1520 1521 /* Should only fail if we've built a corrupted tree */ 1522 assert(rc == 0); 1523 1524 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1525 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1526 fdt_totalsize(fdt), FDT_MAX_SIZE); 1527 exit(1); 1528 } 1529 1530 /* Load the fdt */ 1531 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1532 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1533 g_free(fdt); 1534 1535 /* Set up the entry state */ 1536 first_ppc_cpu->env.gpr[3] = fdt_addr; 1537 first_ppc_cpu->env.gpr[5] = 0; 1538 first_cpu->halted = 0; 1539 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1540 1541 spapr->cas_reboot = false; 1542 } 1543 1544 static void spapr_create_nvram(sPAPRMachineState *spapr) 1545 { 1546 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1547 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1548 1549 if (dinfo) { 1550 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1551 &error_fatal); 1552 } 1553 1554 qdev_init_nofail(dev); 1555 1556 spapr->nvram = (struct sPAPRNVRAM *)dev; 1557 } 1558 1559 static void spapr_rtc_create(sPAPRMachineState *spapr) 1560 { 1561 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); 1562 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), 1563 &error_fatal); 1564 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1565 &error_fatal); 1566 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1567 "date", &error_fatal); 1568 } 1569 1570 /* Returns whether we want to use VGA or not */ 1571 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1572 { 1573 switch (vga_interface_type) { 1574 case VGA_NONE: 1575 return false; 1576 case VGA_DEVICE: 1577 return true; 1578 case VGA_STD: 1579 case VGA_VIRTIO: 1580 return pci_vga_init(pci_bus) != NULL; 1581 default: 1582 error_setg(errp, 1583 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1584 return false; 1585 } 1586 } 1587 1588 static int spapr_pre_load(void *opaque) 1589 { 1590 int rc; 1591 1592 rc = spapr_caps_pre_load(opaque); 1593 if (rc) { 1594 return rc; 1595 } 1596 1597 return 0; 1598 } 1599 1600 static int spapr_post_load(void *opaque, int version_id) 1601 { 1602 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1603 int err = 0; 1604 1605 err = spapr_caps_post_migration(spapr); 1606 if (err) { 1607 return err; 1608 } 1609 1610 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { 1611 CPUState *cs; 1612 CPU_FOREACH(cs) { 1613 PowerPCCPU *cpu = POWERPC_CPU(cs); 1614 icp_resend(ICP(cpu->intc)); 1615 } 1616 } 1617 1618 /* In earlier versions, there was no separate qdev for the PAPR 1619 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1620 * So when migrating from those versions, poke the incoming offset 1621 * value into the RTC device */ 1622 if (version_id < 3) { 1623 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1624 } 1625 1626 if (kvm_enabled() && spapr->patb_entry) { 1627 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1628 bool radix = !!(spapr->patb_entry & PATBE1_GR); 1629 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1630 1631 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1632 if (err) { 1633 error_report("Process table config unsupported by the host"); 1634 return -EINVAL; 1635 } 1636 } 1637 1638 return err; 1639 } 1640 1641 static int spapr_pre_save(void *opaque) 1642 { 1643 int rc; 1644 1645 rc = spapr_caps_pre_save(opaque); 1646 if (rc) { 1647 return rc; 1648 } 1649 1650 return 0; 1651 } 1652 1653 static bool version_before_3(void *opaque, int version_id) 1654 { 1655 return version_id < 3; 1656 } 1657 1658 static bool spapr_pending_events_needed(void *opaque) 1659 { 1660 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1661 return !QTAILQ_EMPTY(&spapr->pending_events); 1662 } 1663 1664 static const VMStateDescription vmstate_spapr_event_entry = { 1665 .name = "spapr_event_log_entry", 1666 .version_id = 1, 1667 .minimum_version_id = 1, 1668 .fields = (VMStateField[]) { 1669 VMSTATE_UINT32(summary, sPAPREventLogEntry), 1670 VMSTATE_UINT32(extended_length, sPAPREventLogEntry), 1671 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0, 1672 NULL, extended_length), 1673 VMSTATE_END_OF_LIST() 1674 }, 1675 }; 1676 1677 static const VMStateDescription vmstate_spapr_pending_events = { 1678 .name = "spapr_pending_events", 1679 .version_id = 1, 1680 .minimum_version_id = 1, 1681 .needed = spapr_pending_events_needed, 1682 .fields = (VMStateField[]) { 1683 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1, 1684 vmstate_spapr_event_entry, sPAPREventLogEntry, next), 1685 VMSTATE_END_OF_LIST() 1686 }, 1687 }; 1688 1689 static bool spapr_ov5_cas_needed(void *opaque) 1690 { 1691 sPAPRMachineState *spapr = opaque; 1692 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1693 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1694 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1695 bool cas_needed; 1696 1697 /* Prior to the introduction of sPAPROptionVector, we had two option 1698 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1699 * Both of these options encode machine topology into the device-tree 1700 * in such a way that the now-booted OS should still be able to interact 1701 * appropriately with QEMU regardless of what options were actually 1702 * negotiatied on the source side. 1703 * 1704 * As such, we can avoid migrating the CAS-negotiated options if these 1705 * are the only options available on the current machine/platform. 1706 * Since these are the only options available for pseries-2.7 and 1707 * earlier, this allows us to maintain old->new/new->old migration 1708 * compatibility. 1709 * 1710 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1711 * via default pseries-2.8 machines and explicit command-line parameters. 1712 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1713 * of the actual CAS-negotiated values to continue working properly. For 1714 * example, availability of memory unplug depends on knowing whether 1715 * OV5_HP_EVT was negotiated via CAS. 1716 * 1717 * Thus, for any cases where the set of available CAS-negotiatable 1718 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1719 * include the CAS-negotiated options in the migration stream. 1720 */ 1721 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1722 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1723 1724 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1725 * the mask itself since in the future it's possible "legacy" bits may be 1726 * removed via machine options, which could generate a false positive 1727 * that breaks migration. 1728 */ 1729 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1730 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1731 1732 spapr_ovec_cleanup(ov5_mask); 1733 spapr_ovec_cleanup(ov5_legacy); 1734 spapr_ovec_cleanup(ov5_removed); 1735 1736 return cas_needed; 1737 } 1738 1739 static const VMStateDescription vmstate_spapr_ov5_cas = { 1740 .name = "spapr_option_vector_ov5_cas", 1741 .version_id = 1, 1742 .minimum_version_id = 1, 1743 .needed = spapr_ov5_cas_needed, 1744 .fields = (VMStateField[]) { 1745 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1746 vmstate_spapr_ovec, sPAPROptionVector), 1747 VMSTATE_END_OF_LIST() 1748 }, 1749 }; 1750 1751 static bool spapr_patb_entry_needed(void *opaque) 1752 { 1753 sPAPRMachineState *spapr = opaque; 1754 1755 return !!spapr->patb_entry; 1756 } 1757 1758 static const VMStateDescription vmstate_spapr_patb_entry = { 1759 .name = "spapr_patb_entry", 1760 .version_id = 1, 1761 .minimum_version_id = 1, 1762 .needed = spapr_patb_entry_needed, 1763 .fields = (VMStateField[]) { 1764 VMSTATE_UINT64(patb_entry, sPAPRMachineState), 1765 VMSTATE_END_OF_LIST() 1766 }, 1767 }; 1768 1769 static const VMStateDescription vmstate_spapr = { 1770 .name = "spapr", 1771 .version_id = 3, 1772 .minimum_version_id = 1, 1773 .pre_load = spapr_pre_load, 1774 .post_load = spapr_post_load, 1775 .pre_save = spapr_pre_save, 1776 .fields = (VMStateField[]) { 1777 /* used to be @next_irq */ 1778 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1779 1780 /* RTC offset */ 1781 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1782 1783 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1784 VMSTATE_END_OF_LIST() 1785 }, 1786 .subsections = (const VMStateDescription*[]) { 1787 &vmstate_spapr_ov5_cas, 1788 &vmstate_spapr_patb_entry, 1789 &vmstate_spapr_pending_events, 1790 &vmstate_spapr_cap_htm, 1791 &vmstate_spapr_cap_vsx, 1792 &vmstate_spapr_cap_dfp, 1793 &vmstate_spapr_cap_cfpc, 1794 &vmstate_spapr_cap_sbbc, 1795 &vmstate_spapr_cap_ibs, 1796 NULL 1797 } 1798 }; 1799 1800 static int htab_save_setup(QEMUFile *f, void *opaque) 1801 { 1802 sPAPRMachineState *spapr = opaque; 1803 1804 /* "Iteration" header */ 1805 if (!spapr->htab_shift) { 1806 qemu_put_be32(f, -1); 1807 } else { 1808 qemu_put_be32(f, spapr->htab_shift); 1809 } 1810 1811 if (spapr->htab) { 1812 spapr->htab_save_index = 0; 1813 spapr->htab_first_pass = true; 1814 } else { 1815 if (spapr->htab_shift) { 1816 assert(kvm_enabled()); 1817 } 1818 } 1819 1820 1821 return 0; 1822 } 1823 1824 static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr, 1825 int chunkstart, int n_valid, int n_invalid) 1826 { 1827 qemu_put_be32(f, chunkstart); 1828 qemu_put_be16(f, n_valid); 1829 qemu_put_be16(f, n_invalid); 1830 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1831 HASH_PTE_SIZE_64 * n_valid); 1832 } 1833 1834 static void htab_save_end_marker(QEMUFile *f) 1835 { 1836 qemu_put_be32(f, 0); 1837 qemu_put_be16(f, 0); 1838 qemu_put_be16(f, 0); 1839 } 1840 1841 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1842 int64_t max_ns) 1843 { 1844 bool has_timeout = max_ns != -1; 1845 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1846 int index = spapr->htab_save_index; 1847 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1848 1849 assert(spapr->htab_first_pass); 1850 1851 do { 1852 int chunkstart; 1853 1854 /* Consume invalid HPTEs */ 1855 while ((index < htabslots) 1856 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1857 CLEAN_HPTE(HPTE(spapr->htab, index)); 1858 index++; 1859 } 1860 1861 /* Consume valid HPTEs */ 1862 chunkstart = index; 1863 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1864 && HPTE_VALID(HPTE(spapr->htab, index))) { 1865 CLEAN_HPTE(HPTE(spapr->htab, index)); 1866 index++; 1867 } 1868 1869 if (index > chunkstart) { 1870 int n_valid = index - chunkstart; 1871 1872 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 1873 1874 if (has_timeout && 1875 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1876 break; 1877 } 1878 } 1879 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1880 1881 if (index >= htabslots) { 1882 assert(index == htabslots); 1883 index = 0; 1884 spapr->htab_first_pass = false; 1885 } 1886 spapr->htab_save_index = index; 1887 } 1888 1889 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1890 int64_t max_ns) 1891 { 1892 bool final = max_ns < 0; 1893 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1894 int examined = 0, sent = 0; 1895 int index = spapr->htab_save_index; 1896 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1897 1898 assert(!spapr->htab_first_pass); 1899 1900 do { 1901 int chunkstart, invalidstart; 1902 1903 /* Consume non-dirty HPTEs */ 1904 while ((index < htabslots) 1905 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1906 index++; 1907 examined++; 1908 } 1909 1910 chunkstart = index; 1911 /* Consume valid dirty HPTEs */ 1912 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1913 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1914 && HPTE_VALID(HPTE(spapr->htab, index))) { 1915 CLEAN_HPTE(HPTE(spapr->htab, index)); 1916 index++; 1917 examined++; 1918 } 1919 1920 invalidstart = index; 1921 /* Consume invalid dirty HPTEs */ 1922 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1923 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1924 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1925 CLEAN_HPTE(HPTE(spapr->htab, index)); 1926 index++; 1927 examined++; 1928 } 1929 1930 if (index > chunkstart) { 1931 int n_valid = invalidstart - chunkstart; 1932 int n_invalid = index - invalidstart; 1933 1934 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 1935 sent += index - chunkstart; 1936 1937 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1938 break; 1939 } 1940 } 1941 1942 if (examined >= htabslots) { 1943 break; 1944 } 1945 1946 if (index >= htabslots) { 1947 assert(index == htabslots); 1948 index = 0; 1949 } 1950 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1951 1952 if (index >= htabslots) { 1953 assert(index == htabslots); 1954 index = 0; 1955 } 1956 1957 spapr->htab_save_index = index; 1958 1959 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1960 } 1961 1962 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1963 #define MAX_KVM_BUF_SIZE 2048 1964 1965 static int htab_save_iterate(QEMUFile *f, void *opaque) 1966 { 1967 sPAPRMachineState *spapr = opaque; 1968 int fd; 1969 int rc = 0; 1970 1971 /* Iteration header */ 1972 if (!spapr->htab_shift) { 1973 qemu_put_be32(f, -1); 1974 return 1; 1975 } else { 1976 qemu_put_be32(f, 0); 1977 } 1978 1979 if (!spapr->htab) { 1980 assert(kvm_enabled()); 1981 1982 fd = get_htab_fd(spapr); 1983 if (fd < 0) { 1984 return fd; 1985 } 1986 1987 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1988 if (rc < 0) { 1989 return rc; 1990 } 1991 } else if (spapr->htab_first_pass) { 1992 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1993 } else { 1994 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1995 } 1996 1997 htab_save_end_marker(f); 1998 1999 return rc; 2000 } 2001 2002 static int htab_save_complete(QEMUFile *f, void *opaque) 2003 { 2004 sPAPRMachineState *spapr = opaque; 2005 int fd; 2006 2007 /* Iteration header */ 2008 if (!spapr->htab_shift) { 2009 qemu_put_be32(f, -1); 2010 return 0; 2011 } else { 2012 qemu_put_be32(f, 0); 2013 } 2014 2015 if (!spapr->htab) { 2016 int rc; 2017 2018 assert(kvm_enabled()); 2019 2020 fd = get_htab_fd(spapr); 2021 if (fd < 0) { 2022 return fd; 2023 } 2024 2025 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2026 if (rc < 0) { 2027 return rc; 2028 } 2029 } else { 2030 if (spapr->htab_first_pass) { 2031 htab_save_first_pass(f, spapr, -1); 2032 } 2033 htab_save_later_pass(f, spapr, -1); 2034 } 2035 2036 /* End marker */ 2037 htab_save_end_marker(f); 2038 2039 return 0; 2040 } 2041 2042 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2043 { 2044 sPAPRMachineState *spapr = opaque; 2045 uint32_t section_hdr; 2046 int fd = -1; 2047 Error *local_err = NULL; 2048 2049 if (version_id < 1 || version_id > 1) { 2050 error_report("htab_load() bad version"); 2051 return -EINVAL; 2052 } 2053 2054 section_hdr = qemu_get_be32(f); 2055 2056 if (section_hdr == -1) { 2057 spapr_free_hpt(spapr); 2058 return 0; 2059 } 2060 2061 if (section_hdr) { 2062 /* First section gives the htab size */ 2063 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2064 if (local_err) { 2065 error_report_err(local_err); 2066 return -EINVAL; 2067 } 2068 return 0; 2069 } 2070 2071 if (!spapr->htab) { 2072 assert(kvm_enabled()); 2073 2074 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2075 if (fd < 0) { 2076 error_report_err(local_err); 2077 return fd; 2078 } 2079 } 2080 2081 while (true) { 2082 uint32_t index; 2083 uint16_t n_valid, n_invalid; 2084 2085 index = qemu_get_be32(f); 2086 n_valid = qemu_get_be16(f); 2087 n_invalid = qemu_get_be16(f); 2088 2089 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2090 /* End of Stream */ 2091 break; 2092 } 2093 2094 if ((index + n_valid + n_invalid) > 2095 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2096 /* Bad index in stream */ 2097 error_report( 2098 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2099 index, n_valid, n_invalid, spapr->htab_shift); 2100 return -EINVAL; 2101 } 2102 2103 if (spapr->htab) { 2104 if (n_valid) { 2105 qemu_get_buffer(f, HPTE(spapr->htab, index), 2106 HASH_PTE_SIZE_64 * n_valid); 2107 } 2108 if (n_invalid) { 2109 memset(HPTE(spapr->htab, index + n_valid), 0, 2110 HASH_PTE_SIZE_64 * n_invalid); 2111 } 2112 } else { 2113 int rc; 2114 2115 assert(fd >= 0); 2116 2117 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2118 if (rc < 0) { 2119 return rc; 2120 } 2121 } 2122 } 2123 2124 if (!spapr->htab) { 2125 assert(fd >= 0); 2126 close(fd); 2127 } 2128 2129 return 0; 2130 } 2131 2132 static void htab_save_cleanup(void *opaque) 2133 { 2134 sPAPRMachineState *spapr = opaque; 2135 2136 close_htab_fd(spapr); 2137 } 2138 2139 static SaveVMHandlers savevm_htab_handlers = { 2140 .save_setup = htab_save_setup, 2141 .save_live_iterate = htab_save_iterate, 2142 .save_live_complete_precopy = htab_save_complete, 2143 .save_cleanup = htab_save_cleanup, 2144 .load_state = htab_load, 2145 }; 2146 2147 static void spapr_boot_set(void *opaque, const char *boot_device, 2148 Error **errp) 2149 { 2150 MachineState *machine = MACHINE(opaque); 2151 machine->boot_order = g_strdup(boot_device); 2152 } 2153 2154 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 2155 { 2156 MachineState *machine = MACHINE(spapr); 2157 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2158 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2159 int i; 2160 2161 for (i = 0; i < nr_lmbs; i++) { 2162 uint64_t addr; 2163 2164 addr = i * lmb_size + spapr->hotplug_memory.base; 2165 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2166 addr / lmb_size); 2167 } 2168 } 2169 2170 /* 2171 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2172 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2173 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2174 */ 2175 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2176 { 2177 int i; 2178 2179 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2180 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2181 " is not aligned to %llu MiB", 2182 machine->ram_size, 2183 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2184 return; 2185 } 2186 2187 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2188 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2189 " is not aligned to %llu MiB", 2190 machine->ram_size, 2191 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2192 return; 2193 } 2194 2195 for (i = 0; i < nb_numa_nodes; i++) { 2196 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2197 error_setg(errp, 2198 "Node %d memory size 0x%" PRIx64 2199 " is not aligned to %llu MiB", 2200 i, numa_info[i].node_mem, 2201 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2202 return; 2203 } 2204 } 2205 } 2206 2207 /* find cpu slot in machine->possible_cpus by core_id */ 2208 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2209 { 2210 int index = id / smp_threads; 2211 2212 if (index >= ms->possible_cpus->len) { 2213 return NULL; 2214 } 2215 if (idx) { 2216 *idx = index; 2217 } 2218 return &ms->possible_cpus->cpus[index]; 2219 } 2220 2221 static void spapr_init_cpus(sPAPRMachineState *spapr) 2222 { 2223 MachineState *machine = MACHINE(spapr); 2224 MachineClass *mc = MACHINE_GET_CLASS(machine); 2225 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2226 int smt = kvmppc_smt_threads(); 2227 const CPUArchIdList *possible_cpus; 2228 int boot_cores_nr = smp_cpus / smp_threads; 2229 int i; 2230 2231 possible_cpus = mc->possible_cpu_arch_ids(machine); 2232 if (mc->has_hotpluggable_cpus) { 2233 if (smp_cpus % smp_threads) { 2234 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2235 smp_cpus, smp_threads); 2236 exit(1); 2237 } 2238 if (max_cpus % smp_threads) { 2239 error_report("max_cpus (%u) must be multiple of threads (%u)", 2240 max_cpus, smp_threads); 2241 exit(1); 2242 } 2243 } else { 2244 if (max_cpus != smp_cpus) { 2245 error_report("This machine version does not support CPU hotplug"); 2246 exit(1); 2247 } 2248 boot_cores_nr = possible_cpus->len; 2249 } 2250 2251 for (i = 0; i < possible_cpus->len; i++) { 2252 int core_id = i * smp_threads; 2253 2254 if (mc->has_hotpluggable_cpus) { 2255 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2256 (core_id / smp_threads) * smt); 2257 } 2258 2259 if (i < boot_cores_nr) { 2260 Object *core = object_new(type); 2261 int nr_threads = smp_threads; 2262 2263 /* Handle the partially filled core for older machine types */ 2264 if ((i + 1) * smp_threads >= smp_cpus) { 2265 nr_threads = smp_cpus - i * smp_threads; 2266 } 2267 2268 object_property_set_int(core, nr_threads, "nr-threads", 2269 &error_fatal); 2270 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2271 &error_fatal); 2272 object_property_set_bool(core, true, "realized", &error_fatal); 2273 } 2274 } 2275 } 2276 2277 static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp) 2278 { 2279 Error *local_err = NULL; 2280 bool vsmt_user = !!spapr->vsmt; 2281 int kvm_smt = kvmppc_smt_threads(); 2282 int ret; 2283 2284 if (!kvm_enabled() && (smp_threads > 1)) { 2285 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2286 "on a pseries machine"); 2287 goto out; 2288 } 2289 if (!is_power_of_2(smp_threads)) { 2290 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2291 "machine because it must be a power of 2", smp_threads); 2292 goto out; 2293 } 2294 2295 /* Detemine the VSMT mode to use: */ 2296 if (vsmt_user) { 2297 if (spapr->vsmt < smp_threads) { 2298 error_setg(&local_err, "Cannot support VSMT mode %d" 2299 " because it must be >= threads/core (%d)", 2300 spapr->vsmt, smp_threads); 2301 goto out; 2302 } 2303 /* In this case, spapr->vsmt has been set by the command line */ 2304 } else { 2305 /* 2306 * Default VSMT value is tricky, because we need it to be as 2307 * consistent as possible (for migration), but this requires 2308 * changing it for at least some existing cases. We pick 8 as 2309 * the value that we'd get with KVM on POWER8, the 2310 * overwhelmingly common case in production systems. 2311 */ 2312 spapr->vsmt = 8; 2313 } 2314 2315 /* KVM: If necessary, set the SMT mode: */ 2316 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2317 ret = kvmppc_set_smt_threads(spapr->vsmt); 2318 if (ret) { 2319 /* Looks like KVM isn't able to change VSMT mode */ 2320 error_setg(&local_err, 2321 "Failed to set KVM's VSMT mode to %d (errno %d)", 2322 spapr->vsmt, ret); 2323 /* We can live with that if the default one is big enough 2324 * for the number of threads, and a submultiple of the one 2325 * we want. In this case we'll waste some vcpu ids, but 2326 * behaviour will be correct */ 2327 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2328 warn_report_err(local_err); 2329 local_err = NULL; 2330 goto out; 2331 } else { 2332 if (!vsmt_user) { 2333 error_append_hint(&local_err, 2334 "On PPC, a VM with %d threads/core" 2335 " on a host with %d threads/core" 2336 " requires the use of VSMT mode %d.\n", 2337 smp_threads, kvm_smt, spapr->vsmt); 2338 } 2339 kvmppc_hint_smt_possible(&local_err); 2340 goto out; 2341 } 2342 } 2343 } 2344 /* else TCG: nothing to do currently */ 2345 out: 2346 error_propagate(errp, local_err); 2347 } 2348 2349 /* pSeries LPAR / sPAPR hardware init */ 2350 static void spapr_machine_init(MachineState *machine) 2351 { 2352 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2353 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2354 const char *kernel_filename = machine->kernel_filename; 2355 const char *initrd_filename = machine->initrd_filename; 2356 PCIHostState *phb; 2357 int i; 2358 MemoryRegion *sysmem = get_system_memory(); 2359 MemoryRegion *ram = g_new(MemoryRegion, 1); 2360 MemoryRegion *rma_region; 2361 void *rma = NULL; 2362 hwaddr rma_alloc_size; 2363 hwaddr node0_size = spapr_node0_size(machine); 2364 long load_limit, fw_size; 2365 char *filename; 2366 Error *resize_hpt_err = NULL; 2367 2368 msi_nonbroken = true; 2369 2370 QLIST_INIT(&spapr->phbs); 2371 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2372 2373 /* Check HPT resizing availability */ 2374 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2375 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2376 /* 2377 * If the user explicitly requested a mode we should either 2378 * supply it, or fail completely (which we do below). But if 2379 * it's not set explicitly, we reset our mode to something 2380 * that works 2381 */ 2382 if (resize_hpt_err) { 2383 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2384 error_free(resize_hpt_err); 2385 resize_hpt_err = NULL; 2386 } else { 2387 spapr->resize_hpt = smc->resize_hpt_default; 2388 } 2389 } 2390 2391 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2392 2393 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2394 /* 2395 * User requested HPT resize, but this host can't supply it. Bail out 2396 */ 2397 error_report_err(resize_hpt_err); 2398 exit(1); 2399 } 2400 2401 /* Allocate RMA if necessary */ 2402 rma_alloc_size = kvmppc_alloc_rma(&rma); 2403 2404 if (rma_alloc_size == -1) { 2405 error_report("Unable to create RMA"); 2406 exit(1); 2407 } 2408 2409 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 2410 spapr->rma_size = rma_alloc_size; 2411 } else { 2412 spapr->rma_size = node0_size; 2413 2414 /* With KVM, we don't actually know whether KVM supports an 2415 * unbounded RMA (PR KVM) or is limited by the hash table size 2416 * (HV KVM using VRMA), so we always assume the latter 2417 * 2418 * In that case, we also limit the initial allocations for RTAS 2419 * etc... to 256M since we have no way to know what the VRMA size 2420 * is going to be as it depends on the size of the hash table 2421 * isn't determined yet. 2422 */ 2423 if (kvm_enabled()) { 2424 spapr->vrma_adjust = 1; 2425 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2426 } 2427 2428 /* Actually we don't support unbounded RMA anymore since we 2429 * added proper emulation of HV mode. The max we can get is 2430 * 16G which also happens to be what we configure for PAPR 2431 * mode so make sure we don't do anything bigger than that 2432 */ 2433 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2434 } 2435 2436 if (spapr->rma_size > node0_size) { 2437 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2438 spapr->rma_size); 2439 exit(1); 2440 } 2441 2442 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2443 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2444 2445 /* Set up Interrupt Controller before we create the VCPUs */ 2446 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal); 2447 2448 /* Set up containers for ibm,client-architecture-support negotiated options 2449 */ 2450 spapr->ov5 = spapr_ovec_new(); 2451 spapr->ov5_cas = spapr_ovec_new(); 2452 2453 if (smc->dr_lmb_enabled) { 2454 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2455 spapr_validate_node_memory(machine, &error_fatal); 2456 } 2457 2458 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2459 if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) { 2460 /* KVM and TCG always allow GTSE with radix... */ 2461 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2462 } 2463 /* ... but not with hash (currently). */ 2464 2465 /* advertise support for dedicated HP event source to guests */ 2466 if (spapr->use_hotplug_event_source) { 2467 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2468 } 2469 2470 /* advertise support for HPT resizing */ 2471 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2472 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2473 } 2474 2475 /* init CPUs */ 2476 spapr_set_vsmt_mode(spapr, &error_fatal); 2477 2478 spapr_init_cpus(spapr); 2479 2480 if (kvm_enabled()) { 2481 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2482 kvmppc_enable_logical_ci_hcalls(); 2483 kvmppc_enable_set_mode_hcall(); 2484 2485 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2486 kvmppc_enable_clear_ref_mod_hcalls(); 2487 } 2488 2489 /* allocate RAM */ 2490 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2491 machine->ram_size); 2492 memory_region_add_subregion(sysmem, 0, ram); 2493 2494 if (rma_alloc_size && rma) { 2495 rma_region = g_new(MemoryRegion, 1); 2496 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 2497 rma_alloc_size, rma); 2498 vmstate_register_ram_global(rma_region); 2499 memory_region_add_subregion(sysmem, 0, rma_region); 2500 } 2501 2502 /* initialize hotplug memory address space */ 2503 if (machine->ram_size < machine->maxram_size) { 2504 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 2505 /* 2506 * Limit the number of hotpluggable memory slots to half the number 2507 * slots that KVM supports, leaving the other half for PCI and other 2508 * devices. However ensure that number of slots doesn't drop below 32. 2509 */ 2510 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2511 SPAPR_MAX_RAM_SLOTS; 2512 2513 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2514 max_memslots = SPAPR_MAX_RAM_SLOTS; 2515 } 2516 if (machine->ram_slots > max_memslots) { 2517 error_report("Specified number of memory slots %" 2518 PRIu64" exceeds max supported %d", 2519 machine->ram_slots, max_memslots); 2520 exit(1); 2521 } 2522 2523 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 2524 SPAPR_HOTPLUG_MEM_ALIGN); 2525 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 2526 "hotplug-memory", hotplug_mem_size); 2527 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 2528 &spapr->hotplug_memory.mr); 2529 } 2530 2531 if (smc->dr_lmb_enabled) { 2532 spapr_create_lmb_dr_connectors(spapr); 2533 } 2534 2535 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2536 if (!filename) { 2537 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2538 exit(1); 2539 } 2540 spapr->rtas_size = get_image_size(filename); 2541 if (spapr->rtas_size < 0) { 2542 error_report("Could not get size of LPAR rtas '%s'", filename); 2543 exit(1); 2544 } 2545 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2546 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2547 error_report("Could not load LPAR rtas '%s'", filename); 2548 exit(1); 2549 } 2550 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2551 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2552 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2553 exit(1); 2554 } 2555 g_free(filename); 2556 2557 /* Set up RTAS event infrastructure */ 2558 spapr_events_init(spapr); 2559 2560 /* Set up the RTC RTAS interfaces */ 2561 spapr_rtc_create(spapr); 2562 2563 /* Set up VIO bus */ 2564 spapr->vio_bus = spapr_vio_bus_init(); 2565 2566 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 2567 if (serial_hds[i]) { 2568 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 2569 } 2570 } 2571 2572 /* We always have at least the nvram device on VIO */ 2573 spapr_create_nvram(spapr); 2574 2575 /* Set up PCI */ 2576 spapr_pci_rtas_init(); 2577 2578 phb = spapr_create_phb(spapr, 0); 2579 2580 for (i = 0; i < nb_nics; i++) { 2581 NICInfo *nd = &nd_table[i]; 2582 2583 if (!nd->model) { 2584 nd->model = g_strdup("ibmveth"); 2585 } 2586 2587 if (strcmp(nd->model, "ibmveth") == 0) { 2588 spapr_vlan_create(spapr->vio_bus, nd); 2589 } else { 2590 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2591 } 2592 } 2593 2594 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2595 spapr_vscsi_create(spapr->vio_bus); 2596 } 2597 2598 /* Graphics */ 2599 if (spapr_vga_init(phb->bus, &error_fatal)) { 2600 spapr->has_graphics = true; 2601 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2602 } 2603 2604 if (machine->usb) { 2605 if (smc->use_ohci_by_default) { 2606 pci_create_simple(phb->bus, -1, "pci-ohci"); 2607 } else { 2608 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2609 } 2610 2611 if (spapr->has_graphics) { 2612 USBBus *usb_bus = usb_bus_find(-1); 2613 2614 usb_create_simple(usb_bus, "usb-kbd"); 2615 usb_create_simple(usb_bus, "usb-mouse"); 2616 } 2617 } 2618 2619 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 2620 error_report( 2621 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2622 MIN_RMA_SLOF); 2623 exit(1); 2624 } 2625 2626 if (kernel_filename) { 2627 uint64_t lowaddr = 0; 2628 2629 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2630 NULL, NULL, &lowaddr, NULL, 1, 2631 PPC_ELF_MACHINE, 0, 0); 2632 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2633 spapr->kernel_size = load_elf(kernel_filename, 2634 translate_kernel_address, NULL, NULL, 2635 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2636 0, 0); 2637 spapr->kernel_le = spapr->kernel_size > 0; 2638 } 2639 if (spapr->kernel_size < 0) { 2640 error_report("error loading %s: %s", kernel_filename, 2641 load_elf_strerror(spapr->kernel_size)); 2642 exit(1); 2643 } 2644 2645 /* load initrd */ 2646 if (initrd_filename) { 2647 /* Try to locate the initrd in the gap between the kernel 2648 * and the firmware. Add a bit of space just in case 2649 */ 2650 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2651 + 0x1ffff) & ~0xffff; 2652 spapr->initrd_size = load_image_targphys(initrd_filename, 2653 spapr->initrd_base, 2654 load_limit 2655 - spapr->initrd_base); 2656 if (spapr->initrd_size < 0) { 2657 error_report("could not load initial ram disk '%s'", 2658 initrd_filename); 2659 exit(1); 2660 } 2661 } 2662 } 2663 2664 if (bios_name == NULL) { 2665 bios_name = FW_FILE_NAME; 2666 } 2667 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2668 if (!filename) { 2669 error_report("Could not find LPAR firmware '%s'", bios_name); 2670 exit(1); 2671 } 2672 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2673 if (fw_size <= 0) { 2674 error_report("Could not load LPAR firmware '%s'", filename); 2675 exit(1); 2676 } 2677 g_free(filename); 2678 2679 /* FIXME: Should register things through the MachineState's qdev 2680 * interface, this is a legacy from the sPAPREnvironment structure 2681 * which predated MachineState but had a similar function */ 2682 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2683 register_savevm_live(NULL, "spapr/htab", -1, 1, 2684 &savevm_htab_handlers, spapr); 2685 2686 qemu_register_boot_set(spapr_boot_set, spapr); 2687 2688 if (kvm_enabled()) { 2689 /* to stop and start vmclock */ 2690 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2691 &spapr->tb); 2692 2693 kvmppc_spapr_enable_inkernel_multitce(); 2694 } 2695 } 2696 2697 static int spapr_kvm_type(const char *vm_type) 2698 { 2699 if (!vm_type) { 2700 return 0; 2701 } 2702 2703 if (!strcmp(vm_type, "HV")) { 2704 return 1; 2705 } 2706 2707 if (!strcmp(vm_type, "PR")) { 2708 return 2; 2709 } 2710 2711 error_report("Unknown kvm-type specified '%s'", vm_type); 2712 exit(1); 2713 } 2714 2715 /* 2716 * Implementation of an interface to adjust firmware path 2717 * for the bootindex property handling. 2718 */ 2719 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2720 DeviceState *dev) 2721 { 2722 #define CAST(type, obj, name) \ 2723 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2724 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2725 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2726 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 2727 2728 if (d) { 2729 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2730 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2731 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2732 2733 if (spapr) { 2734 /* 2735 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2736 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2737 * in the top 16 bits of the 64-bit LUN 2738 */ 2739 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2740 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2741 (uint64_t)id << 48); 2742 } else if (virtio) { 2743 /* 2744 * We use SRP luns of the form 01000000 | (target << 8) | lun 2745 * in the top 32 bits of the 64-bit LUN 2746 * Note: the quote above is from SLOF and it is wrong, 2747 * the actual binding is: 2748 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2749 */ 2750 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2751 if (d->lun >= 256) { 2752 /* Use the LUN "flat space addressing method" */ 2753 id |= 0x4000; 2754 } 2755 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2756 (uint64_t)id << 32); 2757 } else if (usb) { 2758 /* 2759 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2760 * in the top 32 bits of the 64-bit LUN 2761 */ 2762 unsigned usb_port = atoi(usb->port->path); 2763 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2764 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2765 (uint64_t)id << 32); 2766 } 2767 } 2768 2769 /* 2770 * SLOF probes the USB devices, and if it recognizes that the device is a 2771 * storage device, it changes its name to "storage" instead of "usb-host", 2772 * and additionally adds a child node for the SCSI LUN, so the correct 2773 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2774 */ 2775 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2776 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2777 if (usb_host_dev_is_scsi_storage(usbdev)) { 2778 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2779 } 2780 } 2781 2782 if (phb) { 2783 /* Replace "pci" with "pci@800000020000000" */ 2784 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2785 } 2786 2787 if (vsc) { 2788 /* Same logic as virtio above */ 2789 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 2790 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 2791 } 2792 2793 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 2794 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 2795 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 2796 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 2797 } 2798 2799 return NULL; 2800 } 2801 2802 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2803 { 2804 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2805 2806 return g_strdup(spapr->kvm_type); 2807 } 2808 2809 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2810 { 2811 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2812 2813 g_free(spapr->kvm_type); 2814 spapr->kvm_type = g_strdup(value); 2815 } 2816 2817 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2818 { 2819 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2820 2821 return spapr->use_hotplug_event_source; 2822 } 2823 2824 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2825 Error **errp) 2826 { 2827 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2828 2829 spapr->use_hotplug_event_source = value; 2830 } 2831 2832 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 2833 { 2834 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2835 2836 switch (spapr->resize_hpt) { 2837 case SPAPR_RESIZE_HPT_DEFAULT: 2838 return g_strdup("default"); 2839 case SPAPR_RESIZE_HPT_DISABLED: 2840 return g_strdup("disabled"); 2841 case SPAPR_RESIZE_HPT_ENABLED: 2842 return g_strdup("enabled"); 2843 case SPAPR_RESIZE_HPT_REQUIRED: 2844 return g_strdup("required"); 2845 } 2846 g_assert_not_reached(); 2847 } 2848 2849 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 2850 { 2851 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2852 2853 if (strcmp(value, "default") == 0) { 2854 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 2855 } else if (strcmp(value, "disabled") == 0) { 2856 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2857 } else if (strcmp(value, "enabled") == 0) { 2858 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 2859 } else if (strcmp(value, "required") == 0) { 2860 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 2861 } else { 2862 error_setg(errp, "Bad value for \"resize-hpt\" property"); 2863 } 2864 } 2865 2866 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 2867 void *opaque, Error **errp) 2868 { 2869 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 2870 } 2871 2872 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 2873 void *opaque, Error **errp) 2874 { 2875 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 2876 } 2877 2878 static void spapr_instance_init(Object *obj) 2879 { 2880 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2881 2882 spapr->htab_fd = -1; 2883 spapr->use_hotplug_event_source = true; 2884 object_property_add_str(obj, "kvm-type", 2885 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2886 object_property_set_description(obj, "kvm-type", 2887 "Specifies the KVM virtualization mode (HV, PR)", 2888 NULL); 2889 object_property_add_bool(obj, "modern-hotplug-events", 2890 spapr_get_modern_hotplug_events, 2891 spapr_set_modern_hotplug_events, 2892 NULL); 2893 object_property_set_description(obj, "modern-hotplug-events", 2894 "Use dedicated hotplug event mechanism in" 2895 " place of standard EPOW events when possible" 2896 " (required for memory hot-unplug support)", 2897 NULL); 2898 2899 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 2900 "Maximum permitted CPU compatibility mode", 2901 &error_fatal); 2902 2903 object_property_add_str(obj, "resize-hpt", 2904 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 2905 object_property_set_description(obj, "resize-hpt", 2906 "Resizing of the Hash Page Table (enabled, disabled, required)", 2907 NULL); 2908 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 2909 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 2910 object_property_set_description(obj, "vsmt", 2911 "Virtual SMT: KVM behaves as if this were" 2912 " the host's SMT mode", &error_abort); 2913 } 2914 2915 static void spapr_machine_finalizefn(Object *obj) 2916 { 2917 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2918 2919 g_free(spapr->kvm_type); 2920 } 2921 2922 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 2923 { 2924 cpu_synchronize_state(cs); 2925 ppc_cpu_do_system_reset(cs); 2926 } 2927 2928 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2929 { 2930 CPUState *cs; 2931 2932 CPU_FOREACH(cs) { 2933 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 2934 } 2935 } 2936 2937 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2938 uint32_t node, bool dedicated_hp_event_source, 2939 Error **errp) 2940 { 2941 sPAPRDRConnector *drc; 2942 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2943 int i, fdt_offset, fdt_size; 2944 void *fdt; 2945 uint64_t addr = addr_start; 2946 bool hotplugged = spapr_drc_hotplugged(dev); 2947 Error *local_err = NULL; 2948 2949 for (i = 0; i < nr_lmbs; i++) { 2950 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2951 addr / SPAPR_MEMORY_BLOCK_SIZE); 2952 g_assert(drc); 2953 2954 fdt = create_device_tree(&fdt_size); 2955 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2956 SPAPR_MEMORY_BLOCK_SIZE); 2957 2958 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 2959 if (local_err) { 2960 while (addr > addr_start) { 2961 addr -= SPAPR_MEMORY_BLOCK_SIZE; 2962 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2963 addr / SPAPR_MEMORY_BLOCK_SIZE); 2964 spapr_drc_detach(drc); 2965 } 2966 g_free(fdt); 2967 error_propagate(errp, local_err); 2968 return; 2969 } 2970 if (!hotplugged) { 2971 spapr_drc_reset(drc); 2972 } 2973 addr += SPAPR_MEMORY_BLOCK_SIZE; 2974 } 2975 /* send hotplug notification to the 2976 * guest only in case of hotplugged memory 2977 */ 2978 if (hotplugged) { 2979 if (dedicated_hp_event_source) { 2980 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2981 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2982 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2983 nr_lmbs, 2984 spapr_drc_index(drc)); 2985 } else { 2986 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 2987 nr_lmbs); 2988 } 2989 } 2990 } 2991 2992 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2993 uint32_t node, Error **errp) 2994 { 2995 Error *local_err = NULL; 2996 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2997 PCDIMMDevice *dimm = PC_DIMM(dev); 2998 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2999 MemoryRegion *mr; 3000 uint64_t align, size, addr; 3001 3002 mr = ddc->get_memory_region(dimm, &local_err); 3003 if (local_err) { 3004 goto out; 3005 } 3006 align = memory_region_get_alignment(mr); 3007 size = memory_region_size(mr); 3008 3009 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 3010 if (local_err) { 3011 goto out; 3012 } 3013 3014 addr = object_property_get_uint(OBJECT(dimm), 3015 PC_DIMM_ADDR_PROP, &local_err); 3016 if (local_err) { 3017 goto out_unplug; 3018 } 3019 3020 spapr_add_lmbs(dev, addr, size, node, 3021 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 3022 &local_err); 3023 if (local_err) { 3024 goto out_unplug; 3025 } 3026 3027 return; 3028 3029 out_unplug: 3030 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 3031 out: 3032 error_propagate(errp, local_err); 3033 } 3034 3035 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3036 Error **errp) 3037 { 3038 PCDIMMDevice *dimm = PC_DIMM(dev); 3039 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3040 MemoryRegion *mr; 3041 uint64_t size; 3042 char *mem_dev; 3043 3044 mr = ddc->get_memory_region(dimm, errp); 3045 if (!mr) { 3046 return; 3047 } 3048 size = memory_region_size(mr); 3049 3050 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3051 error_setg(errp, "Hotplugged memory size must be a multiple of " 3052 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 3053 return; 3054 } 3055 3056 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); 3057 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { 3058 error_setg(errp, "Memory backend has bad page size. " 3059 "Use 'memory-backend-file' with correct mem-path."); 3060 goto out; 3061 } 3062 3063 out: 3064 g_free(mem_dev); 3065 } 3066 3067 struct sPAPRDIMMState { 3068 PCDIMMDevice *dimm; 3069 uint32_t nr_lmbs; 3070 QTAILQ_ENTRY(sPAPRDIMMState) next; 3071 }; 3072 3073 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, 3074 PCDIMMDevice *dimm) 3075 { 3076 sPAPRDIMMState *dimm_state = NULL; 3077 3078 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3079 if (dimm_state->dimm == dimm) { 3080 break; 3081 } 3082 } 3083 return dimm_state; 3084 } 3085 3086 static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, 3087 uint32_t nr_lmbs, 3088 PCDIMMDevice *dimm) 3089 { 3090 sPAPRDIMMState *ds = NULL; 3091 3092 /* 3093 * If this request is for a DIMM whose removal had failed earlier 3094 * (due to guest's refusal to remove the LMBs), we would have this 3095 * dimm already in the pending_dimm_unplugs list. In that 3096 * case don't add again. 3097 */ 3098 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3099 if (!ds) { 3100 ds = g_malloc0(sizeof(sPAPRDIMMState)); 3101 ds->nr_lmbs = nr_lmbs; 3102 ds->dimm = dimm; 3103 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3104 } 3105 return ds; 3106 } 3107 3108 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, 3109 sPAPRDIMMState *dimm_state) 3110 { 3111 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3112 g_free(dimm_state); 3113 } 3114 3115 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, 3116 PCDIMMDevice *dimm) 3117 { 3118 sPAPRDRConnector *drc; 3119 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3120 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); 3121 uint64_t size = memory_region_size(mr); 3122 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3123 uint32_t avail_lmbs = 0; 3124 uint64_t addr_start, addr; 3125 int i; 3126 3127 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3128 &error_abort); 3129 3130 addr = addr_start; 3131 for (i = 0; i < nr_lmbs; i++) { 3132 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3133 addr / SPAPR_MEMORY_BLOCK_SIZE); 3134 g_assert(drc); 3135 if (drc->dev) { 3136 avail_lmbs++; 3137 } 3138 addr += SPAPR_MEMORY_BLOCK_SIZE; 3139 } 3140 3141 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3142 } 3143 3144 /* Callback to be called during DRC release. */ 3145 void spapr_lmb_release(DeviceState *dev) 3146 { 3147 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_hotplug_handler(dev)); 3148 PCDIMMDevice *dimm = PC_DIMM(dev); 3149 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3150 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); 3151 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3152 3153 /* This information will get lost if a migration occurs 3154 * during the unplug process. In this case recover it. */ 3155 if (ds == NULL) { 3156 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3157 g_assert(ds); 3158 /* The DRC being examined by the caller at least must be counted */ 3159 g_assert(ds->nr_lmbs); 3160 } 3161 3162 if (--ds->nr_lmbs) { 3163 return; 3164 } 3165 3166 /* 3167 * Now that all the LMBs have been removed by the guest, call the 3168 * pc-dimm unplug handler to cleanup up the pc-dimm device. 3169 */ 3170 pc_dimm_memory_unplug(dev, &spapr->hotplug_memory, mr); 3171 object_unparent(OBJECT(dev)); 3172 spapr_pending_dimm_unplugs_remove(spapr, ds); 3173 } 3174 3175 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3176 DeviceState *dev, Error **errp) 3177 { 3178 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3179 Error *local_err = NULL; 3180 PCDIMMDevice *dimm = PC_DIMM(dev); 3181 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3182 MemoryRegion *mr; 3183 uint32_t nr_lmbs; 3184 uint64_t size, addr_start, addr; 3185 int i; 3186 sPAPRDRConnector *drc; 3187 3188 mr = ddc->get_memory_region(dimm, &local_err); 3189 if (local_err) { 3190 goto out; 3191 } 3192 size = memory_region_size(mr); 3193 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3194 3195 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3196 &local_err); 3197 if (local_err) { 3198 goto out; 3199 } 3200 3201 /* 3202 * An existing pending dimm state for this DIMM means that there is an 3203 * unplug operation in progress, waiting for the spapr_lmb_release 3204 * callback to complete the job (BQL can't cover that far). In this case, 3205 * bail out to avoid detaching DRCs that were already released. 3206 */ 3207 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3208 error_setg(&local_err, 3209 "Memory unplug already in progress for device %s", 3210 dev->id); 3211 goto out; 3212 } 3213 3214 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3215 3216 addr = addr_start; 3217 for (i = 0; i < nr_lmbs; i++) { 3218 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3219 addr / SPAPR_MEMORY_BLOCK_SIZE); 3220 g_assert(drc); 3221 3222 spapr_drc_detach(drc); 3223 addr += SPAPR_MEMORY_BLOCK_SIZE; 3224 } 3225 3226 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3227 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3228 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3229 nr_lmbs, spapr_drc_index(drc)); 3230 out: 3231 error_propagate(errp, local_err); 3232 } 3233 3234 static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 3235 sPAPRMachineState *spapr) 3236 { 3237 PowerPCCPU *cpu = POWERPC_CPU(cs); 3238 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3239 int id = spapr_vcpu_id(cpu); 3240 void *fdt; 3241 int offset, fdt_size; 3242 char *nodename; 3243 3244 fdt = create_device_tree(&fdt_size); 3245 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3246 offset = fdt_add_subnode(fdt, 0, nodename); 3247 3248 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3249 g_free(nodename); 3250 3251 *fdt_offset = offset; 3252 return fdt; 3253 } 3254 3255 /* Callback to be called during DRC release. */ 3256 void spapr_core_release(DeviceState *dev) 3257 { 3258 MachineState *ms = MACHINE(qdev_get_hotplug_handler(dev)); 3259 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3260 CPUCore *cc = CPU_CORE(dev); 3261 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3262 3263 if (smc->pre_2_10_has_unused_icps) { 3264 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3265 int i; 3266 3267 for (i = 0; i < cc->nr_threads; i++) { 3268 CPUState *cs = CPU(sc->threads[i]); 3269 3270 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3271 } 3272 } 3273 3274 assert(core_slot); 3275 core_slot->cpu = NULL; 3276 object_unparent(OBJECT(dev)); 3277 } 3278 3279 static 3280 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3281 Error **errp) 3282 { 3283 int index; 3284 sPAPRDRConnector *drc; 3285 CPUCore *cc = CPU_CORE(dev); 3286 int smt = kvmppc_smt_threads(); 3287 3288 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3289 error_setg(errp, "Unable to find CPU core with core-id: %d", 3290 cc->core_id); 3291 return; 3292 } 3293 if (index == 0) { 3294 error_setg(errp, "Boot CPU core may not be unplugged"); 3295 return; 3296 } 3297 3298 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt); 3299 g_assert(drc); 3300 3301 spapr_drc_detach(drc); 3302 3303 spapr_hotplug_req_remove_by_index(drc); 3304 } 3305 3306 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3307 Error **errp) 3308 { 3309 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3310 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3311 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3312 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3313 CPUCore *cc = CPU_CORE(dev); 3314 CPUState *cs = CPU(core->threads[0]); 3315 sPAPRDRConnector *drc; 3316 Error *local_err = NULL; 3317 int smt = kvmppc_smt_threads(); 3318 CPUArchId *core_slot; 3319 int index; 3320 bool hotplugged = spapr_drc_hotplugged(dev); 3321 3322 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3323 if (!core_slot) { 3324 error_setg(errp, "Unable to find CPU core with core-id: %d", 3325 cc->core_id); 3326 return; 3327 } 3328 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt); 3329 3330 g_assert(drc || !mc->has_hotpluggable_cpus); 3331 3332 if (drc) { 3333 void *fdt; 3334 int fdt_offset; 3335 3336 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 3337 3338 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 3339 if (local_err) { 3340 g_free(fdt); 3341 error_propagate(errp, local_err); 3342 return; 3343 } 3344 3345 if (hotplugged) { 3346 /* 3347 * Send hotplug notification interrupt to the guest only 3348 * in case of hotplugged CPUs. 3349 */ 3350 spapr_hotplug_req_add_by_index(drc); 3351 } else { 3352 spapr_drc_reset(drc); 3353 } 3354 } 3355 3356 core_slot->cpu = OBJECT(dev); 3357 3358 if (smc->pre_2_10_has_unused_icps) { 3359 int i; 3360 3361 for (i = 0; i < cc->nr_threads; i++) { 3362 cs = CPU(core->threads[i]); 3363 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3364 } 3365 } 3366 } 3367 3368 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3369 Error **errp) 3370 { 3371 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3372 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3373 Error *local_err = NULL; 3374 CPUCore *cc = CPU_CORE(dev); 3375 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3376 const char *type = object_get_typename(OBJECT(dev)); 3377 CPUArchId *core_slot; 3378 int index; 3379 3380 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3381 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3382 goto out; 3383 } 3384 3385 if (strcmp(base_core_type, type)) { 3386 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3387 goto out; 3388 } 3389 3390 if (cc->core_id % smp_threads) { 3391 error_setg(&local_err, "invalid core id %d", cc->core_id); 3392 goto out; 3393 } 3394 3395 /* 3396 * In general we should have homogeneous threads-per-core, but old 3397 * (pre hotplug support) machine types allow the last core to have 3398 * reduced threads as a compatibility hack for when we allowed 3399 * total vcpus not a multiple of threads-per-core. 3400 */ 3401 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3402 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3403 cc->nr_threads, smp_threads); 3404 goto out; 3405 } 3406 3407 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3408 if (!core_slot) { 3409 error_setg(&local_err, "core id %d out of range", cc->core_id); 3410 goto out; 3411 } 3412 3413 if (core_slot->cpu) { 3414 error_setg(&local_err, "core %d already populated", cc->core_id); 3415 goto out; 3416 } 3417 3418 numa_cpu_pre_plug(core_slot, dev, &local_err); 3419 3420 out: 3421 error_propagate(errp, local_err); 3422 } 3423 3424 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 3425 DeviceState *dev, Error **errp) 3426 { 3427 MachineState *ms = MACHINE(hotplug_dev); 3428 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3429 3430 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3431 int node; 3432 3433 if (!smc->dr_lmb_enabled) { 3434 error_setg(errp, "Memory hotplug not supported for this machine"); 3435 return; 3436 } 3437 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 3438 if (*errp) { 3439 return; 3440 } 3441 if (node < 0 || node >= MAX_NODES) { 3442 error_setg(errp, "Invaild node %d", node); 3443 return; 3444 } 3445 3446 /* 3447 * Currently PowerPC kernel doesn't allow hot-adding memory to 3448 * memory-less node, but instead will silently add the memory 3449 * to the first node that has some memory. This causes two 3450 * unexpected behaviours for the user. 3451 * 3452 * - Memory gets hotplugged to a different node than what the user 3453 * specified. 3454 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 3455 * to memory-less node, a reboot will set things accordingly 3456 * and the previously hotplugged memory now ends in the right node. 3457 * This appears as if some memory moved from one node to another. 3458 * 3459 * So until kernel starts supporting memory hotplug to memory-less 3460 * nodes, just prevent such attempts upfront in QEMU. 3461 */ 3462 if (nb_numa_nodes && !numa_info[node].node_mem) { 3463 error_setg(errp, "Can't hotplug memory to memory-less node %d", 3464 node); 3465 return; 3466 } 3467 3468 spapr_memory_plug(hotplug_dev, dev, node, errp); 3469 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3470 spapr_core_plug(hotplug_dev, dev, errp); 3471 } 3472 } 3473 3474 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 3475 DeviceState *dev, Error **errp) 3476 { 3477 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3478 MachineClass *mc = MACHINE_GET_CLASS(sms); 3479 3480 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3481 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3482 spapr_memory_unplug_request(hotplug_dev, dev, errp); 3483 } else { 3484 /* NOTE: this means there is a window after guest reset, prior to 3485 * CAS negotiation, where unplug requests will fail due to the 3486 * capability not being detected yet. This is a bit different than 3487 * the case with PCI unplug, where the events will be queued and 3488 * eventually handled by the guest after boot 3489 */ 3490 error_setg(errp, "Memory hot unplug not supported for this guest"); 3491 } 3492 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3493 if (!mc->has_hotpluggable_cpus) { 3494 error_setg(errp, "CPU hot unplug not supported on this machine"); 3495 return; 3496 } 3497 spapr_core_unplug_request(hotplug_dev, dev, errp); 3498 } 3499 } 3500 3501 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 3502 DeviceState *dev, Error **errp) 3503 { 3504 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3505 spapr_memory_pre_plug(hotplug_dev, dev, errp); 3506 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3507 spapr_core_pre_plug(hotplug_dev, dev, errp); 3508 } 3509 } 3510 3511 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 3512 DeviceState *dev) 3513 { 3514 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3515 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3516 return HOTPLUG_HANDLER(machine); 3517 } 3518 return NULL; 3519 } 3520 3521 static CpuInstanceProperties 3522 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 3523 { 3524 CPUArchId *core_slot; 3525 MachineClass *mc = MACHINE_GET_CLASS(machine); 3526 3527 /* make sure possible_cpu are intialized */ 3528 mc->possible_cpu_arch_ids(machine); 3529 /* get CPU core slot containing thread that matches cpu_index */ 3530 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 3531 assert(core_slot); 3532 return core_slot->props; 3533 } 3534 3535 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 3536 { 3537 return idx / smp_cores % nb_numa_nodes; 3538 } 3539 3540 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 3541 { 3542 int i; 3543 const char *core_type; 3544 int spapr_max_cores = max_cpus / smp_threads; 3545 MachineClass *mc = MACHINE_GET_CLASS(machine); 3546 3547 if (!mc->has_hotpluggable_cpus) { 3548 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 3549 } 3550 if (machine->possible_cpus) { 3551 assert(machine->possible_cpus->len == spapr_max_cores); 3552 return machine->possible_cpus; 3553 } 3554 3555 core_type = spapr_get_cpu_core_type(machine->cpu_type); 3556 if (!core_type) { 3557 error_report("Unable to find sPAPR CPU Core definition"); 3558 exit(1); 3559 } 3560 3561 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 3562 sizeof(CPUArchId) * spapr_max_cores); 3563 machine->possible_cpus->len = spapr_max_cores; 3564 for (i = 0; i < machine->possible_cpus->len; i++) { 3565 int core_id = i * smp_threads; 3566 3567 machine->possible_cpus->cpus[i].type = core_type; 3568 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 3569 machine->possible_cpus->cpus[i].arch_id = core_id; 3570 machine->possible_cpus->cpus[i].props.has_core_id = true; 3571 machine->possible_cpus->cpus[i].props.core_id = core_id; 3572 } 3573 return machine->possible_cpus; 3574 } 3575 3576 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 3577 uint64_t *buid, hwaddr *pio, 3578 hwaddr *mmio32, hwaddr *mmio64, 3579 unsigned n_dma, uint32_t *liobns, Error **errp) 3580 { 3581 /* 3582 * New-style PHB window placement. 3583 * 3584 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 3585 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 3586 * windows. 3587 * 3588 * Some guest kernels can't work with MMIO windows above 1<<46 3589 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 3590 * 3591 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 3592 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 3593 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 3594 * 1TiB 64-bit MMIO windows for each PHB. 3595 */ 3596 const uint64_t base_buid = 0x800000020000000ULL; 3597 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 3598 SPAPR_PCI_MEM64_WIN_SIZE - 1) 3599 int i; 3600 3601 /* Sanity check natural alignments */ 3602 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3603 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3604 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 3605 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 3606 /* Sanity check bounds */ 3607 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 3608 SPAPR_PCI_MEM32_WIN_SIZE); 3609 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 3610 SPAPR_PCI_MEM64_WIN_SIZE); 3611 3612 if (index >= SPAPR_MAX_PHBS) { 3613 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 3614 SPAPR_MAX_PHBS - 1); 3615 return; 3616 } 3617 3618 *buid = base_buid + index; 3619 for (i = 0; i < n_dma; ++i) { 3620 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3621 } 3622 3623 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 3624 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 3625 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 3626 } 3627 3628 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 3629 { 3630 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3631 3632 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 3633 } 3634 3635 static void spapr_ics_resend(XICSFabric *dev) 3636 { 3637 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3638 3639 ics_resend(spapr->ics); 3640 } 3641 3642 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 3643 { 3644 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 3645 3646 return cpu ? ICP(cpu->intc) : NULL; 3647 } 3648 3649 #define ICS_IRQ_FREE(ics, srcno) \ 3650 (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK))) 3651 3652 static int ics_find_free_block(ICSState *ics, int num, int alignnum) 3653 { 3654 int first, i; 3655 3656 for (first = 0; first < ics->nr_irqs; first += alignnum) { 3657 if (num > (ics->nr_irqs - first)) { 3658 return -1; 3659 } 3660 for (i = first; i < first + num; ++i) { 3661 if (!ICS_IRQ_FREE(ics, i)) { 3662 break; 3663 } 3664 } 3665 if (i == (first + num)) { 3666 return first; 3667 } 3668 } 3669 3670 return -1; 3671 } 3672 3673 /* 3674 * Allocate the IRQ number and set the IRQ type, LSI or MSI 3675 */ 3676 static void spapr_irq_set_lsi(sPAPRMachineState *spapr, int irq, bool lsi) 3677 { 3678 ics_set_irq_type(spapr->ics, irq - spapr->ics->offset, lsi); 3679 } 3680 3681 int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi, 3682 Error **errp) 3683 { 3684 ICSState *ics = spapr->ics; 3685 int irq; 3686 3687 if (!ics) { 3688 return -1; 3689 } 3690 if (irq_hint) { 3691 if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) { 3692 error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint); 3693 return -1; 3694 } 3695 irq = irq_hint; 3696 } else { 3697 irq = ics_find_free_block(ics, 1, 1); 3698 if (irq < 0) { 3699 error_setg(errp, "can't allocate IRQ: no IRQ left"); 3700 return -1; 3701 } 3702 irq += ics->offset; 3703 } 3704 3705 spapr_irq_set_lsi(spapr, irq, lsi); 3706 trace_spapr_irq_alloc(irq); 3707 3708 return irq; 3709 } 3710 3711 /* 3712 * Allocate block of consecutive IRQs, and return the number of the first IRQ in 3713 * the block. If align==true, aligns the first IRQ number to num. 3714 */ 3715 int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi, 3716 bool align, Error **errp) 3717 { 3718 ICSState *ics = spapr->ics; 3719 int i, first = -1; 3720 3721 if (!ics) { 3722 return -1; 3723 } 3724 3725 /* 3726 * MSIMesage::data is used for storing VIRQ so 3727 * it has to be aligned to num to support multiple 3728 * MSI vectors. MSI-X is not affected by this. 3729 * The hint is used for the first IRQ, the rest should 3730 * be allocated continuously. 3731 */ 3732 if (align) { 3733 assert((num == 1) || (num == 2) || (num == 4) || 3734 (num == 8) || (num == 16) || (num == 32)); 3735 first = ics_find_free_block(ics, num, num); 3736 } else { 3737 first = ics_find_free_block(ics, num, 1); 3738 } 3739 if (first < 0) { 3740 error_setg(errp, "can't find a free %d-IRQ block", num); 3741 return -1; 3742 } 3743 3744 first += ics->offset; 3745 for (i = first; i < first + num; ++i) { 3746 spapr_irq_set_lsi(spapr, i, lsi); 3747 } 3748 3749 trace_spapr_irq_alloc_block(first, num, lsi, align); 3750 3751 return first; 3752 } 3753 3754 void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num) 3755 { 3756 ICSState *ics = spapr->ics; 3757 int srcno = irq - ics->offset; 3758 int i; 3759 3760 if (ics_valid_irq(ics, irq)) { 3761 trace_spapr_irq_free(0, irq, num); 3762 for (i = srcno; i < srcno + num; ++i) { 3763 if (ICS_IRQ_FREE(ics, i)) { 3764 trace_spapr_irq_free_warn(0, i + ics->offset); 3765 } 3766 memset(&ics->irqs[i], 0, sizeof(ICSIRQState)); 3767 } 3768 } 3769 } 3770 3771 qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq) 3772 { 3773 ICSState *ics = spapr->ics; 3774 3775 if (ics_valid_irq(ics, irq)) { 3776 return ics->qirqs[irq - ics->offset]; 3777 } 3778 3779 return NULL; 3780 } 3781 3782 static void spapr_pic_print_info(InterruptStatsProvider *obj, 3783 Monitor *mon) 3784 { 3785 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3786 CPUState *cs; 3787 3788 CPU_FOREACH(cs) { 3789 PowerPCCPU *cpu = POWERPC_CPU(cs); 3790 3791 icp_pic_print_info(ICP(cpu->intc), mon); 3792 } 3793 3794 ics_pic_print_info(spapr->ics, mon); 3795 } 3796 3797 int spapr_vcpu_id(PowerPCCPU *cpu) 3798 { 3799 CPUState *cs = CPU(cpu); 3800 3801 if (kvm_enabled()) { 3802 return kvm_arch_vcpu_id(cs); 3803 } else { 3804 return cs->cpu_index; 3805 } 3806 } 3807 3808 PowerPCCPU *spapr_find_cpu(int vcpu_id) 3809 { 3810 CPUState *cs; 3811 3812 CPU_FOREACH(cs) { 3813 PowerPCCPU *cpu = POWERPC_CPU(cs); 3814 3815 if (spapr_vcpu_id(cpu) == vcpu_id) { 3816 return cpu; 3817 } 3818 } 3819 3820 return NULL; 3821 } 3822 3823 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3824 { 3825 MachineClass *mc = MACHINE_CLASS(oc); 3826 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3827 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3828 NMIClass *nc = NMI_CLASS(oc); 3829 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3830 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3831 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3832 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 3833 3834 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3835 3836 /* 3837 * We set up the default / latest behaviour here. The class_init 3838 * functions for the specific versioned machine types can override 3839 * these details for backwards compatibility 3840 */ 3841 mc->init = spapr_machine_init; 3842 mc->reset = spapr_machine_reset; 3843 mc->block_default_type = IF_SCSI; 3844 mc->max_cpus = 1024; 3845 mc->no_parallel = 1; 3846 mc->default_boot_order = ""; 3847 mc->default_ram_size = 512 * M_BYTE; 3848 mc->kvm_type = spapr_kvm_type; 3849 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 3850 mc->pci_allow_0_address = true; 3851 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3852 hc->pre_plug = spapr_machine_device_pre_plug; 3853 hc->plug = spapr_machine_device_plug; 3854 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 3855 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 3856 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3857 hc->unplug_request = spapr_machine_device_unplug_request; 3858 3859 smc->dr_lmb_enabled = true; 3860 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 3861 mc->has_hotpluggable_cpus = true; 3862 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 3863 fwc->get_dev_path = spapr_get_fw_dev_path; 3864 nc->nmi_monitor_handler = spapr_nmi; 3865 smc->phb_placement = spapr_phb_placement; 3866 vhc->hypercall = emulate_spapr_hypercall; 3867 vhc->hpt_mask = spapr_hpt_mask; 3868 vhc->map_hptes = spapr_map_hptes; 3869 vhc->unmap_hptes = spapr_unmap_hptes; 3870 vhc->store_hpte = spapr_store_hpte; 3871 vhc->get_patbe = spapr_get_patbe; 3872 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 3873 xic->ics_get = spapr_ics_get; 3874 xic->ics_resend = spapr_ics_resend; 3875 xic->icp_get = spapr_icp_get; 3876 ispc->print_info = spapr_pic_print_info; 3877 /* Force NUMA node memory size to be a multiple of 3878 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 3879 * in which LMBs are represented and hot-added 3880 */ 3881 mc->numa_mem_align_shift = 28; 3882 3883 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 3884 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 3885 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 3886 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 3887 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 3888 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 3889 spapr_caps_add_properties(smc, &error_abort); 3890 } 3891 3892 static const TypeInfo spapr_machine_info = { 3893 .name = TYPE_SPAPR_MACHINE, 3894 .parent = TYPE_MACHINE, 3895 .abstract = true, 3896 .instance_size = sizeof(sPAPRMachineState), 3897 .instance_init = spapr_instance_init, 3898 .instance_finalize = spapr_machine_finalizefn, 3899 .class_size = sizeof(sPAPRMachineClass), 3900 .class_init = spapr_machine_class_init, 3901 .interfaces = (InterfaceInfo[]) { 3902 { TYPE_FW_PATH_PROVIDER }, 3903 { TYPE_NMI }, 3904 { TYPE_HOTPLUG_HANDLER }, 3905 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 3906 { TYPE_XICS_FABRIC }, 3907 { TYPE_INTERRUPT_STATS_PROVIDER }, 3908 { } 3909 }, 3910 }; 3911 3912 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 3913 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 3914 void *data) \ 3915 { \ 3916 MachineClass *mc = MACHINE_CLASS(oc); \ 3917 spapr_machine_##suffix##_class_options(mc); \ 3918 if (latest) { \ 3919 mc->alias = "pseries"; \ 3920 mc->is_default = 1; \ 3921 } \ 3922 } \ 3923 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 3924 { \ 3925 MachineState *machine = MACHINE(obj); \ 3926 spapr_machine_##suffix##_instance_options(machine); \ 3927 } \ 3928 static const TypeInfo spapr_machine_##suffix##_info = { \ 3929 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 3930 .parent = TYPE_SPAPR_MACHINE, \ 3931 .class_init = spapr_machine_##suffix##_class_init, \ 3932 .instance_init = spapr_machine_##suffix##_instance_init, \ 3933 }; \ 3934 static void spapr_machine_register_##suffix(void) \ 3935 { \ 3936 type_register(&spapr_machine_##suffix##_info); \ 3937 } \ 3938 type_init(spapr_machine_register_##suffix) 3939 3940 /* 3941 * pseries-2.12 3942 */ 3943 static void spapr_machine_2_12_instance_options(MachineState *machine) 3944 { 3945 } 3946 3947 static void spapr_machine_2_12_class_options(MachineClass *mc) 3948 { 3949 /* Defaults for the latest behaviour inherited from the base class */ 3950 } 3951 3952 DEFINE_SPAPR_MACHINE(2_12, "2.12", true); 3953 3954 /* 3955 * pseries-2.11 3956 */ 3957 #define SPAPR_COMPAT_2_11 \ 3958 HW_COMPAT_2_11 3959 3960 static void spapr_machine_2_11_instance_options(MachineState *machine) 3961 { 3962 spapr_machine_2_12_instance_options(machine); 3963 } 3964 3965 static void spapr_machine_2_11_class_options(MachineClass *mc) 3966 { 3967 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3968 3969 spapr_machine_2_12_class_options(mc); 3970 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 3971 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11); 3972 } 3973 3974 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 3975 3976 /* 3977 * pseries-2.10 3978 */ 3979 #define SPAPR_COMPAT_2_10 \ 3980 HW_COMPAT_2_10 3981 3982 static void spapr_machine_2_10_instance_options(MachineState *machine) 3983 { 3984 spapr_machine_2_11_instance_options(machine); 3985 } 3986 3987 static void spapr_machine_2_10_class_options(MachineClass *mc) 3988 { 3989 spapr_machine_2_11_class_options(mc); 3990 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10); 3991 } 3992 3993 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 3994 3995 /* 3996 * pseries-2.9 3997 */ 3998 #define SPAPR_COMPAT_2_9 \ 3999 HW_COMPAT_2_9 \ 4000 { \ 4001 .driver = TYPE_POWERPC_CPU, \ 4002 .property = "pre-2.10-migration", \ 4003 .value = "on", \ 4004 }, \ 4005 4006 static void spapr_machine_2_9_instance_options(MachineState *machine) 4007 { 4008 spapr_machine_2_10_instance_options(machine); 4009 } 4010 4011 static void spapr_machine_2_9_class_options(MachineClass *mc) 4012 { 4013 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4014 4015 spapr_machine_2_10_class_options(mc); 4016 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); 4017 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 4018 smc->pre_2_10_has_unused_icps = true; 4019 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 4020 } 4021 4022 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 4023 4024 /* 4025 * pseries-2.8 4026 */ 4027 #define SPAPR_COMPAT_2_8 \ 4028 HW_COMPAT_2_8 \ 4029 { \ 4030 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4031 .property = "pcie-extended-configuration-space", \ 4032 .value = "off", \ 4033 }, 4034 4035 static void spapr_machine_2_8_instance_options(MachineState *machine) 4036 { 4037 spapr_machine_2_9_instance_options(machine); 4038 } 4039 4040 static void spapr_machine_2_8_class_options(MachineClass *mc) 4041 { 4042 spapr_machine_2_9_class_options(mc); 4043 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 4044 mc->numa_mem_align_shift = 23; 4045 } 4046 4047 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 4048 4049 /* 4050 * pseries-2.7 4051 */ 4052 #define SPAPR_COMPAT_2_7 \ 4053 HW_COMPAT_2_7 \ 4054 { \ 4055 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4056 .property = "mem_win_size", \ 4057 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 4058 }, \ 4059 { \ 4060 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4061 .property = "mem64_win_size", \ 4062 .value = "0", \ 4063 }, \ 4064 { \ 4065 .driver = TYPE_POWERPC_CPU, \ 4066 .property = "pre-2.8-migration", \ 4067 .value = "on", \ 4068 }, \ 4069 { \ 4070 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 4071 .property = "pre-2.8-migration", \ 4072 .value = "on", \ 4073 }, 4074 4075 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 4076 uint64_t *buid, hwaddr *pio, 4077 hwaddr *mmio32, hwaddr *mmio64, 4078 unsigned n_dma, uint32_t *liobns, Error **errp) 4079 { 4080 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 4081 const uint64_t base_buid = 0x800000020000000ULL; 4082 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 4083 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 4084 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 4085 const uint32_t max_index = 255; 4086 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 4087 4088 uint64_t ram_top = MACHINE(spapr)->ram_size; 4089 hwaddr phb0_base, phb_base; 4090 int i; 4091 4092 /* Do we have hotpluggable memory? */ 4093 if (MACHINE(spapr)->maxram_size > ram_top) { 4094 /* Can't just use maxram_size, because there may be an 4095 * alignment gap between normal and hotpluggable memory 4096 * regions */ 4097 ram_top = spapr->hotplug_memory.base + 4098 memory_region_size(&spapr->hotplug_memory.mr); 4099 } 4100 4101 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 4102 4103 if (index > max_index) { 4104 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 4105 max_index); 4106 return; 4107 } 4108 4109 *buid = base_buid + index; 4110 for (i = 0; i < n_dma; ++i) { 4111 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4112 } 4113 4114 phb_base = phb0_base + index * phb_spacing; 4115 *pio = phb_base + pio_offset; 4116 *mmio32 = phb_base + mmio_offset; 4117 /* 4118 * We don't set the 64-bit MMIO window, relying on the PHB's 4119 * fallback behaviour of automatically splitting a large "32-bit" 4120 * window into contiguous 32-bit and 64-bit windows 4121 */ 4122 } 4123 4124 static void spapr_machine_2_7_instance_options(MachineState *machine) 4125 { 4126 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 4127 4128 spapr_machine_2_8_instance_options(machine); 4129 spapr->use_hotplug_event_source = false; 4130 } 4131 4132 static void spapr_machine_2_7_class_options(MachineClass *mc) 4133 { 4134 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4135 4136 spapr_machine_2_8_class_options(mc); 4137 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 4138 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 4139 smc->phb_placement = phb_placement_2_7; 4140 } 4141 4142 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 4143 4144 /* 4145 * pseries-2.6 4146 */ 4147 #define SPAPR_COMPAT_2_6 \ 4148 HW_COMPAT_2_6 \ 4149 { \ 4150 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 4151 .property = "ddw",\ 4152 .value = stringify(off),\ 4153 }, 4154 4155 static void spapr_machine_2_6_instance_options(MachineState *machine) 4156 { 4157 spapr_machine_2_7_instance_options(machine); 4158 } 4159 4160 static void spapr_machine_2_6_class_options(MachineClass *mc) 4161 { 4162 spapr_machine_2_7_class_options(mc); 4163 mc->has_hotpluggable_cpus = false; 4164 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 4165 } 4166 4167 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 4168 4169 /* 4170 * pseries-2.5 4171 */ 4172 #define SPAPR_COMPAT_2_5 \ 4173 HW_COMPAT_2_5 \ 4174 { \ 4175 .driver = "spapr-vlan", \ 4176 .property = "use-rx-buffer-pools", \ 4177 .value = "off", \ 4178 }, 4179 4180 static void spapr_machine_2_5_instance_options(MachineState *machine) 4181 { 4182 spapr_machine_2_6_instance_options(machine); 4183 } 4184 4185 static void spapr_machine_2_5_class_options(MachineClass *mc) 4186 { 4187 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4188 4189 spapr_machine_2_6_class_options(mc); 4190 smc->use_ohci_by_default = true; 4191 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 4192 } 4193 4194 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 4195 4196 /* 4197 * pseries-2.4 4198 */ 4199 #define SPAPR_COMPAT_2_4 \ 4200 HW_COMPAT_2_4 4201 4202 static void spapr_machine_2_4_instance_options(MachineState *machine) 4203 { 4204 spapr_machine_2_5_instance_options(machine); 4205 } 4206 4207 static void spapr_machine_2_4_class_options(MachineClass *mc) 4208 { 4209 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4210 4211 spapr_machine_2_5_class_options(mc); 4212 smc->dr_lmb_enabled = false; 4213 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 4214 } 4215 4216 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 4217 4218 /* 4219 * pseries-2.3 4220 */ 4221 #define SPAPR_COMPAT_2_3 \ 4222 HW_COMPAT_2_3 \ 4223 {\ 4224 .driver = "spapr-pci-host-bridge",\ 4225 .property = "dynamic-reconfiguration",\ 4226 .value = "off",\ 4227 }, 4228 4229 static void spapr_machine_2_3_instance_options(MachineState *machine) 4230 { 4231 spapr_machine_2_4_instance_options(machine); 4232 } 4233 4234 static void spapr_machine_2_3_class_options(MachineClass *mc) 4235 { 4236 spapr_machine_2_4_class_options(mc); 4237 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 4238 } 4239 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 4240 4241 /* 4242 * pseries-2.2 4243 */ 4244 4245 #define SPAPR_COMPAT_2_2 \ 4246 HW_COMPAT_2_2 \ 4247 {\ 4248 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 4249 .property = "mem_win_size",\ 4250 .value = "0x20000000",\ 4251 }, 4252 4253 static void spapr_machine_2_2_instance_options(MachineState *machine) 4254 { 4255 spapr_machine_2_3_instance_options(machine); 4256 machine->suppress_vmdesc = true; 4257 } 4258 4259 static void spapr_machine_2_2_class_options(MachineClass *mc) 4260 { 4261 spapr_machine_2_3_class_options(mc); 4262 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 4263 } 4264 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 4265 4266 /* 4267 * pseries-2.1 4268 */ 4269 #define SPAPR_COMPAT_2_1 \ 4270 HW_COMPAT_2_1 4271 4272 static void spapr_machine_2_1_instance_options(MachineState *machine) 4273 { 4274 spapr_machine_2_2_instance_options(machine); 4275 } 4276 4277 static void spapr_machine_2_1_class_options(MachineClass *mc) 4278 { 4279 spapr_machine_2_2_class_options(mc); 4280 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 4281 } 4282 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4283 4284 static void spapr_machine_register_types(void) 4285 { 4286 type_register_static(&spapr_machine_info); 4287 } 4288 4289 type_init(spapr_machine_register_types) 4290